[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / intel / igbvf / vf.h

/* SPDX-License-Identifier: GPL-2.0 */
/*******************************************************************************

  Intel(R) 82576 Virtual Function Linux driver
  Copyright(c) 2009 - 2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, see <http://www.gnu.org/licenses/>.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_VF_H_
#define _E1000_VF_H_

#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/if_ether.h>

#include "regs.h"
#include "defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82576_VF		0x10CA
#define E1000_DEV_ID_I350_VF		0x1520
#define E1000_REVISION_0	0
#define E1000_REVISION_1	1
#define E1000_REVISION_2	2
#define E1000_REVISION_3	3
#define E1000_REVISION_4	4

#define E1000_FUNC_0	0
#define E1000_FUNC_1	1

/* Receive Address Register Count
 * Number of high/low register pairs in the RAR.  The RAR (Receive Address
 * Registers) holds the directed and multicast addresses that we monitor.
 * These entries are also used for MAC-based filtering.
 */
#define E1000_RAR_ENTRIES_VF	1

/* Receive Descriptor - Advanced */
union e1000_adv_rx_desc {
	struct {
		u64 pkt_addr; /* Packet buffer address */
		u64 hdr_addr; /* Header buffer address */
	} read;
	struct {
		struct {
			union {
				u32 data;
				struct {
					u16 pkt_info; /* RSS/Packet type */
					/* Split Header, hdr buffer length */
					u16 hdr_info;
				} hs_rss;
			} lo_dword;
			union {
				u32 rss; /* RSS Hash */
				struct {
					u16 ip_id; /* IP id */
					u16 csum;  /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			u32 status_error; /* ext status/error */
			u16 length; /* Packet length */
			u16 vlan;   /* VLAN tag */
		} upper;
	} wb;  /* writeback */
};

#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
#define E1000_RXDADV_HDRBUFLEN_SHIFT	5

/* Transmit Descriptor - Advanced */
union e1000_adv_tx_desc {
	struct {
		u64 buffer_addr; /* Address of descriptor's data buf */
		u32 cmd_type_len;
		u32 olinfo_status;
	} read;
	struct {
		u64 rsvd; /* Reserved */
		u32 nxtseq_seed;
		u32 status;
	} wb;
};

/* Adv Transmit Descriptor Config Masks */
#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */

/* Context descriptors */
struct e1000_adv_tx_context_desc {
	u32 vlan_macip_lens;
	u32 seqnum_seed;
	u32 type_tucmd_mlhl;
	u32 mss_l4len_idx;
};

#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
#define E1000_ADVTXD_TUCMD_IPV4		0x00000400 /* IP Packet Type: 1=IPv4 */
#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800 /* L4 Packet TYPE of TCP */
#define E1000_ADVTXD_TUCMD_L4T_SCTP	0x00001000 /* L4 packet TYPE of SCTP */
#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
#define E1000_ADVTXD_MSS_SHIFT		16 /* Adv ctxt MSS shift */

enum e1000_mac_type {
	e1000_undefined = 0,
	e1000_vfadapt,
	e1000_vfadapt_i350,
	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
};

struct e1000_vf_stats {
	u64 base_gprc;
	u64 base_gptc;
	u64 base_gorc;
	u64 base_gotc;
	u64 base_mprc;
	u64 base_gotlbc;
	u64 base_gptlbc;
	u64 base_gorlbc;
	u64 base_gprlbc;

	u32 last_gprc;
	u32 last_gptc;
	u32 last_gorc;
	u32 last_gotc;
	u32 last_mprc;
	u32 last_gotlbc;
	u32 last_gptlbc;
	u32 last_gorlbc;
	u32 last_gprlbc;

	u64 gprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 mprc;
	u64 gotlbc;
	u64 gptlbc;
	u64 gorlbc;
	u64 gprlbc;
};

#include "mbx.h"

struct e1000_mac_operations {
	/* Function pointers for the MAC. */
	s32  (*init_params)(struct e1000_hw *);
	s32  (*check_for_link)(struct e1000_hw *);
	void (*clear_vfta)(struct e1000_hw *);
	s32  (*get_bus_info)(struct e1000_hw *);
	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
	s32  (*set_uc_addr)(struct e1000_hw *, u32, u8 *);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	s32  (*setup_link)(struct e1000_hw *);
	void (*write_vfta)(struct e1000_hw *, u32, u32);
	void (*mta_set)(struct e1000_hw *, u32);
	void (*rar_set)(struct e1000_hw *, u8*, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
	s32  (*set_vfta)(struct e1000_hw *, u16, bool);
};

struct e1000_mac_info {
	struct e1000_mac_operations ops;
	u8 addr[6];
	u8 perm_addr[6];

	enum e1000_mac_type type;

	u16 mta_reg_count;
	u16 rar_entry_count;

	bool get_link_status;
};

struct e1000_mbx_operations {
	s32 (*init_params)(struct e1000_hw *hw);
	s32 (*read)(struct e1000_hw *, u32 *, u16);
	s32 (*write)(struct e1000_hw *, u32 *, u16);
	s32 (*read_posted)(struct e1000_hw *, u32 *, u16);
	s32 (*write_posted)(struct e1000_hw *, u32 *, u16);
	s32 (*check_for_msg)(struct e1000_hw *);
	s32 (*check_for_ack)(struct e1000_hw *);
	s32 (*check_for_rst)(struct e1000_hw *);
};

struct e1000_mbx_stats {
	u32 msgs_tx;
	u32 msgs_rx;

	u32 acks;
	u32 reqs;
	u32 rsts;
};

struct e1000_mbx_info {
	struct e1000_mbx_operations ops;
	struct e1000_mbx_stats stats;
	u32 timeout;
	u32 usec_delay;
	u16 size;
};

struct e1000_dev_spec_vf {
	u32 vf_number;
	u32 v2p_mailbox;
};

struct e1000_hw {
	void *back;

	u8 __iomem *hw_addr;
	u8 __iomem *flash_address;
	unsigned long io_base;

	struct e1000_mac_info  mac;
	struct e1000_mbx_info mbx;
	spinlock_t mbx_lock;		/* serializes mailbox ops */

	union {
		struct e1000_dev_spec_vf vf;
	} dev_spec;

	u16 device_id;
	u16 subsystem_vendor_id;
	u16 subsystem_device_id;
	u16 vendor_id;

	u8  revision_id;
};

/* These functions must be implemented by drivers */
void e1000_rlpml_set_vf(struct e1000_hw *, u16);
void e1000_init_function_pointers_vf(struct e1000_hw *hw);

#endif /* _E1000_VF_H_ */
Commit	Line	Data
ae06c70b	1	/* SPDX-License-Identifier: GPL-2.0 */
d4e0fe01 AD	2	/*******************************************************************************
	3
	4	Intel(R) 82576 Virtual Function Linux driver
2a06ed92	5	Copyright(c) 2009 - 2012 Intel Corporation.
d4e0fe01 AD	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
0340501b	17	this program; if not, see <http://www.gnu.org/licenses/>.
d4e0fe01 AD	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _E1000_VF_H_
	29	#define _E1000_VF_H_
	30
	31	#include <linux/pci.h>
	32	#include <linux/delay.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/if_ether.h>
	35
	36	#include "regs.h"
	37	#include "defines.h"
	38
	39	struct e1000_hw;
	40
0340501b JK	41	#define E1000_DEV_ID_82576_VF 0x10CA
	42	#define E1000_DEV_ID_I350_VF 0x1520
	43	#define E1000_REVISION_0 0
	44	#define E1000_REVISION_1 1
	45	#define E1000_REVISION_2 2
	46	#define E1000_REVISION_3 3
	47	#define E1000_REVISION_4 4
d4e0fe01	48
0340501b JK	49	#define E1000_FUNC_0 0
0340501b JK	50	#define E1000_FUNC_1 1
d4e0fe01	51
0340501b	52	/* Receive Address Register Count
d4e0fe01 AD	53	* Number of high/low register pairs in the RAR. The RAR (Receive Address
	54	* Registers) holds the directed and multicast addresses that we monitor.
	55	* These entries are also used for MAC-based filtering.
	56	*/
0340501b	57	#define E1000_RAR_ENTRIES_VF 1
d4e0fe01 AD	58
	59	/* Receive Descriptor - Advanced */
	60	union e1000_adv_rx_desc {
	61	struct {
0340501b JK	62	u64 pkt_addr; /* Packet buffer address */
0340501b JK	63	u64 hdr_addr; /* Header buffer address */
d4e0fe01 AD	64	} read;
	65	struct {
	66	struct {
	67	union {
	68	u32 data;
	69	struct {
	70	u16 pkt_info; /* RSS/Packet type */
0340501b JK	71	/* Split Header, hdr buffer length */
0340501b JK	72	u16 hdr_info;
d4e0fe01 AD	73	} hs_rss;
	74	} lo_dword;
	75	union {
0340501b	76	u32 rss; /* RSS Hash */
d4e0fe01	77	struct {
0340501b JK	78	u16 ip_id; /* IP id */
0340501b JK	79	u16 csum; /* Packet Checksum */
d4e0fe01 AD	80	} csum_ip;
	81	} hi_dword;
	82	} lower;
	83	struct {
0340501b JK	84	u32 status_error; /* ext status/error */
	85	u16 length; /* Packet length */
	86	u16 vlan; /* VLAN tag */
d4e0fe01 AD	87	} upper;
	88	} wb; /* writeback */
	89	};
	90
0340501b JK	91	#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
0340501b JK	92	#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
d4e0fe01 AD	93
	94	/* Transmit Descriptor - Advanced */
	95	union e1000_adv_tx_desc {
	96	struct {
0340501b	97	u64 buffer_addr; /* Address of descriptor's data buf */
d4e0fe01 AD	98	u32 cmd_type_len;
	99	u32 olinfo_status;
	100	} read;
	101	struct {
0340501b	102	u64 rsvd; /* Reserved */
d4e0fe01 AD	103	u32 nxtseq_seed;
	104	u32 status;
	105	} wb;
	106	};
	107
	108	/* Adv Transmit Descriptor Config Masks */
0340501b JK	109	#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
	110	#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
	111	#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
	112	#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
	113	#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
	114	#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
	115	#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
	116	#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
	117	#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
d4e0fe01 AD	118
	119	/* Context descriptors */
	120	struct e1000_adv_tx_context_desc {
	121	u32 vlan_macip_lens;
	122	u32 seqnum_seed;
	123	u32 type_tucmd_mlhl;
	124	u32 mss_l4len_idx;
	125	};
	126
0340501b JK	127	#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
	128	#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
	129	#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
ea6ce602	130	#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
0340501b JK	131	#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
0340501b JK	132	#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
d4e0fe01 AD	133
	134	enum e1000_mac_type {
	135	e1000_undefined = 0,
	136	e1000_vfadapt,
031d7952	137	e1000_vfadapt_i350,
d4e0fe01 AD	138	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	139	};
	140
	141	struct e1000_vf_stats {
	142	u64 base_gprc;
	143	u64 base_gptc;
	144	u64 base_gorc;
	145	u64 base_gotc;
	146	u64 base_mprc;
	147	u64 base_gotlbc;
	148	u64 base_gptlbc;
	149	u64 base_gorlbc;
	150	u64 base_gprlbc;
	151
	152	u32 last_gprc;
	153	u32 last_gptc;
	154	u32 last_gorc;
	155	u32 last_gotc;
	156	u32 last_mprc;
	157	u32 last_gotlbc;
	158	u32 last_gptlbc;
	159	u32 last_gorlbc;
	160	u32 last_gprlbc;
	161
	162	u64 gprc;
	163	u64 gptc;
	164	u64 gorc;
	165	u64 gotc;
	166	u64 mprc;
	167	u64 gotlbc;
	168	u64 gptlbc;
	169	u64 gorlbc;
	170	u64 gprlbc;
	171	};
	172
	173	#include "mbx.h"
	174
	175	struct e1000_mac_operations {
	176	/* Function pointers for the MAC. */
	177	s32 (init_params)(struct e1000_hw );
	178	s32 (check_for_link)(struct e1000_hw );
	179	void (clear_vfta)(struct e1000_hw );
	180	s32 (get_bus_info)(struct e1000_hw );
	181	s32 (get_link_up_info)(struct e1000_hw , u16 , u16 );
	182	void (update_mc_addr_list)(struct e1000_hw , u8 *, u32, u32, u32);
4827cc37	183	s32 (set_uc_addr)(struct e1000_hw , u32, u8 *);
d4e0fe01 AD	184	s32 (reset_hw)(struct e1000_hw );
	185	s32 (init_hw)(struct e1000_hw );
	186	s32 (setup_link)(struct e1000_hw );
	187	void (write_vfta)(struct e1000_hw , u32, u32);
	188	void (mta_set)(struct e1000_hw , u32);
	189	void (rar_set)(struct e1000_hw , u8*, u32);
	190	s32 (read_mac_addr)(struct e1000_hw );
	191	s32 (set_vfta)(struct e1000_hw , u16, bool);
	192	};
	193
	194	struct e1000_mac_info {
	195	struct e1000_mac_operations ops;
	196	u8 addr[6];
	197	u8 perm_addr[6];
	198
	199	enum e1000_mac_type type;
	200
	201	u16 mta_reg_count;
	202	u16 rar_entry_count;
	203
	204	bool get_link_status;
	205	};
	206
	207	struct e1000_mbx_operations {
	208	s32 (init_params)(struct e1000_hw hw);
	209	s32 (read)(struct e1000_hw , u32 *, u16);
	210	s32 (write)(struct e1000_hw , u32 *, u16);
	211	s32 (read_posted)(struct e1000_hw , u32 *, u16);
	212	s32 (write_posted)(struct e1000_hw , u32 *, u16);
	213	s32 (check_for_msg)(struct e1000_hw );
	214	s32 (check_for_ack)(struct e1000_hw );
	215	s32 (check_for_rst)(struct e1000_hw );
	216	};
	217
	218	struct e1000_mbx_stats {
	219	u32 msgs_tx;
	220	u32 msgs_rx;
	221
	222	u32 acks;
	223	u32 reqs;
	224	u32 rsts;
	225	};
	226
	227	struct e1000_mbx_info {
	228	struct e1000_mbx_operations ops;
	229	struct e1000_mbx_stats stats;
	230	u32 timeout;
	231	u32 usec_delay;
	232	u16 size;
	233	};
	234
	235	struct e1000_dev_spec_vf {
	236	u32 vf_number;
	237	u32 v2p_mailbox;
	238	};
	239
	240	struct e1000_hw {
	241	void *back;
	242
	243	u8 __iomem *hw_addr;
	244	u8 __iomem *flash_address;
	245	unsigned long io_base;
	246
	247	struct e1000_mac_info mac;
248	struct e1000_mbx_info mbx;
32652c2a	249	spinlock_t mbx_lock; /* serializes mailbox ops */
d4e0fe01 AD	250
	251	union {
	252	struct e1000_dev_spec_vf vf;
	253	} dev_spec;
	254
	255	u16 device_id;
	256	u16 subsystem_vendor_id;
	257	u16 subsystem_device_id;
	258	u16 vendor_id;
	259
	260	u8 revision_id;
	261	};
	262
	263	/* These functions must be implemented by drivers */
	264	void e1000_rlpml_set_vf(struct e1000_hw *, u16);
	265	void e1000_init_function_pointers_vf(struct e1000_hw *hw);
d4e0fe01	266
d4e0fe01	267	#endif /* _E1000_VF_H_ */