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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_H_ | |
29 | #define _IXGBE_H_ | |
30 | ||
f62bbb5e | 31 | #include <linux/bitops.h> |
9a799d71 AK |
32 | #include <linux/types.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/netdevice.h> | |
b25ebfd2 | 35 | #include <linux/cpumask.h> |
6fabd715 | 36 | #include <linux/aer.h> |
f62bbb5e | 37 | #include <linux/if_vlan.h> |
9a799d71 | 38 | |
3a6a4eda JK |
39 | #ifdef CONFIG_IXGBE_PTP |
40 | #include <linux/clocksource.h> | |
41 | #include <linux/net_tstamp.h> | |
42 | #include <linux/ptp_clock_kernel.h> | |
43 | #endif /* CONFIG_IXGBE_PTP */ | |
44 | ||
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
48 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
49 | #define IXGBE_FCOE | |
50 | #include "ixgbe_fcoe.h" | |
51 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
849c4542 ET |
56 | /* common prefix used by pr_<> macros */ |
57 | #undef pr_fmt | |
58 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
59 | |
60 | /* TX/RX descriptor defines */ | |
6bacb300 | 61 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 62 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
63 | #define IXGBE_MAX_TXD 4096 |
64 | #define IXGBE_MIN_TXD 64 | |
65 | ||
6bacb300 | 66 | #define IXGBE_DEFAULT_RXD 512 |
9a799d71 AK |
67 | #define IXGBE_MAX_RXD 4096 |
68 | #define IXGBE_MIN_RXD 64 | |
69 | ||
9a799d71 | 70 | /* flow control */ |
2b9ade93 | 71 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 72 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 73 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 74 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 75 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
76 | #define IXGBE_MIN_FCPAUSE 0 |
77 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
78 | ||
79 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 80 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
81 | #define IXGBE_RXBUFFER_2K 2048 |
82 | #define IXGBE_RXBUFFER_3K 3072 | |
83 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 84 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 85 | |
13958070 | 86 | /* |
252562c2 AD |
87 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
88 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
89 | * this adds up to 448 bytes of extra data. | |
90 | * | |
91 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
92 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 93 | */ |
252562c2 | 94 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 AK |
95 | |
96 | #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) | |
97 | ||
9a799d71 AK |
98 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
99 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
100 | ||
101 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) | |
66f32a8b AD |
102 | #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1) |
103 | #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2) | |
104 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3) | |
105 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4) | |
106 | #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5) | |
107 | #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6) | |
7f9643fd | 108 | #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7) |
3a6a4eda | 109 | #define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8) |
62748b7b | 110 | #define IXGBE_TX_FLAGS_NO_IFCS (u32)(1 << 9) |
9a799d71 | 111 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
112 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
113 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
114 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
115 | ||
7f870475 GR |
116 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
117 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
118 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
119 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 120 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 121 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
122 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
123 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
124 | |
125 | struct vf_data_storage { | |
126 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
127 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
128 | u16 num_vf_mc_hashes; | |
129 | u16 default_vf_vlan_id; | |
130 | u16 vlans_enabled; | |
7f870475 | 131 | bool clear_to_send; |
7f01648a | 132 | bool pf_set_mac; |
7f01648a GR |
133 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
134 | u16 pf_qos; | |
ff4ab206 | 135 | u16 tx_rate; |
de4c7f65 GR |
136 | u16 vlan_count; |
137 | u8 spoofchk_enabled; | |
374c65d6 | 138 | unsigned int vf_api; |
7f870475 GR |
139 | }; |
140 | ||
a1cbb15c GR |
141 | struct vf_macvlans { |
142 | struct list_head l; | |
143 | int vf; | |
144 | int rar_entry; | |
145 | bool free; | |
146 | bool is_macvlan; | |
147 | u8 vf_macvlan[ETH_ALEN]; | |
148 | }; | |
149 | ||
a535c30e AD |
150 | #define IXGBE_MAX_TXD_PWR 14 |
151 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
152 | ||
153 | /* Tx Descriptors needed, worst case */ | |
154 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
155 | #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4) | |
156 | ||
9a799d71 AK |
157 | /* wrapper around a pointer to a socket buffer, |
158 | * so a DMA handle can be stored along with the buffer */ | |
159 | struct ixgbe_tx_buffer { | |
d3d00239 | 160 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 161 | unsigned long time_stamp; |
fd0db0ed AD |
162 | struct sk_buff *skb; |
163 | unsigned int bytecount; | |
164 | unsigned short gso_segs; | |
244e27ad | 165 | __be16 protocol; |
729739b7 AD |
166 | DEFINE_DMA_UNMAP_ADDR(dma); |
167 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 168 | u32 tx_flags; |
9a799d71 AK |
169 | }; |
170 | ||
171 | struct ixgbe_rx_buffer { | |
172 | struct sk_buff *skb; | |
173 | dma_addr_t dma; | |
174 | struct page *page; | |
762f4c57 | 175 | unsigned int page_offset; |
9a799d71 AK |
176 | }; |
177 | ||
178 | struct ixgbe_queue_stats { | |
179 | u64 packets; | |
180 | u64 bytes; | |
181 | }; | |
182 | ||
5b7da515 AD |
183 | struct ixgbe_tx_queue_stats { |
184 | u64 restart_queue; | |
185 | u64 tx_busy; | |
c84d324c | 186 | u64 tx_done_old; |
5b7da515 AD |
187 | }; |
188 | ||
189 | struct ixgbe_rx_queue_stats { | |
190 | u64 rsc_count; | |
191 | u64 rsc_flush; | |
192 | u64 non_eop_descs; | |
193 | u64 alloc_rx_page_failed; | |
194 | u64 alloc_rx_buff_failed; | |
8a0da21b | 195 | u64 csum_err; |
5b7da515 AD |
196 | }; |
197 | ||
f800326d | 198 | enum ixgbe_ring_state_t { |
7d637bcc AD |
199 | __IXGBE_TX_FDIR_INIT_DONE, |
200 | __IXGBE_TX_DETECT_HANG, | |
c84d324c | 201 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 202 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 203 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 204 | __IXGBE_RX_FCOE, |
7d637bcc AD |
205 | }; |
206 | ||
7d637bcc AD |
207 | #define check_for_tx_hang(ring) \ |
208 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
209 | #define set_check_for_tx_hang(ring) \ | |
210 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
211 | #define clear_check_for_tx_hang(ring) \ | |
212 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
213 | #define ring_is_rsc_enabled(ring) \ | |
214 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
215 | #define set_ring_rsc_enabled(ring) \ | |
216 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
217 | #define clear_ring_rsc_enabled(ring) \ | |
218 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 219 | struct ixgbe_ring { |
efe3d3c8 | 220 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
221 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
222 | struct net_device *netdev; /* netdev ring belongs to */ | |
223 | struct device *dev; /* device for DMA mapping */ | |
9a799d71 | 224 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
225 | union { |
226 | struct ixgbe_tx_buffer *tx_buffer_info; | |
227 | struct ixgbe_rx_buffer *rx_buffer_info; | |
228 | }; | |
7d637bcc | 229 | unsigned long state; |
bd198058 | 230 | u8 __iomem *tail; |
d3ee4294 AD |
231 | dma_addr_t dma; /* phys. address of descriptor ring */ |
232 | unsigned int size; /* length in bytes */ | |
bd198058 | 233 | |
ae540af1 | 234 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
235 | |
236 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
237 | u8 reg_idx; /* holds the special value that gets |
238 | * the hardware register offset | |
239 | * associated with this ring, which is | |
240 | * different for DCB and RSS modes | |
241 | */ | |
d3ee4294 AD |
242 | u16 next_to_use; |
243 | u16 next_to_clean; | |
244 | ||
f800326d | 245 | union { |
d3ee4294 | 246 | u16 next_to_alloc; |
f800326d AD |
247 | struct { |
248 | u8 atr_sample_rate; | |
249 | u8 atr_count; | |
250 | }; | |
f800326d | 251 | }; |
9a799d71 | 252 | |
bd198058 | 253 | u8 dcb_tc; |
9a799d71 | 254 | struct ixgbe_queue_stats stats; |
de1036b1 | 255 | struct u64_stats_sync syncp; |
5b7da515 AD |
256 | union { |
257 | struct ixgbe_tx_queue_stats tx_stats; | |
258 | struct ixgbe_rx_queue_stats rx_stats; | |
259 | }; | |
7ca3bc58 | 260 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 261 | |
c7e4358a SN |
262 | enum ixgbe_ring_f_enum { |
263 | RING_F_NONE = 0, | |
7f870475 | 264 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 265 | RING_F_RSS, |
c4cf55e5 | 266 | RING_F_FDIR, |
0331a832 YZ |
267 | #ifdef IXGBE_FCOE |
268 | RING_F_FCOE, | |
269 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
270 | |
271 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
272 | }; | |
273 | ||
021230d4 | 274 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 275 | #define IXGBE_MAX_VMDQ_INDICES 64 |
c4cf55e5 | 276 | #define IXGBE_MAX_FDIR_INDICES 64 |
0331a832 YZ |
277 | #ifdef IXGBE_FCOE |
278 | #define IXGBE_MAX_FCOE_INDICES 8 | |
e0fce695 JF |
279 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) |
280 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) | |
281 | #else | |
282 | #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES | |
283 | #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES | |
0331a832 | 284 | #endif /* IXGBE_FCOE */ |
021230d4 | 285 | struct ixgbe_ring_feature { |
c087663e AD |
286 | u16 limit; /* upper limit on feature indices */ |
287 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
288 | u16 mask; /* Mask used for feature to ring mapping */ |
289 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 290 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 291 | |
73079ea0 AD |
292 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
293 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
294 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
295 | ||
f800326d AD |
296 | /* |
297 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
298 | * this is twice the size of a half page we need to double the page order | |
299 | * for FCoE enabled Rx queues. | |
300 | */ | |
09816fbe | 301 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 302 | { |
09816fbe AD |
303 | #ifdef IXGBE_FCOE |
304 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
305 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
306 | IXGBE_RXBUFFER_3K; | |
307 | #endif | |
308 | return IXGBE_RXBUFFER_2K; | |
f800326d | 309 | } |
09816fbe AD |
310 | |
311 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
312 | { | |
313 | #ifdef IXGBE_FCOE | |
314 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
315 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 316 | #endif |
09816fbe AD |
317 | return 0; |
318 | } | |
f800326d | 319 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 320 | |
08c8833b | 321 | struct ixgbe_ring_container { |
efe3d3c8 | 322 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
323 | unsigned int total_bytes; /* total bytes processed this int */ |
324 | unsigned int total_packets; /* total packets processed this int */ | |
325 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
326 | u8 count; /* total number of rings in vector */ |
327 | u8 itr; /* current ITR setting for ring */ | |
328 | }; | |
021230d4 | 329 | |
a557928e AD |
330 | /* iterator for handling rings in ring container */ |
331 | #define ixgbe_for_each_ring(pos, head) \ | |
332 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
333 | ||
2f90b865 AD |
334 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
335 | ? 8 : 1) | |
336 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
337 | ||
49c7ffbe | 338 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
339 | * but we only use one per queue-specific vector. |
340 | */ | |
341 | struct ixgbe_q_vector { | |
342 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
343 | #ifdef CONFIG_IXGBE_DCA |
344 | int cpu; /* CPU for DCA */ | |
345 | #endif | |
d5bf4f67 ET |
346 | u16 v_idx; /* index of q_vector within array, also used for |
347 | * finding the bit in EICR and friends that | |
348 | * represents the vector for this ring */ | |
349 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 350 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
351 | |
352 | struct napi_struct napi; | |
de88eeeb AD |
353 | cpumask_t affinity_mask; |
354 | int numa_node; | |
355 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 356 | char name[IFNAMSIZ + 9]; |
de88eeeb AD |
357 | |
358 | /* for dynamic allocation of rings associated with this q_vector */ | |
359 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 360 | }; |
3ca8bc6d DS |
361 | #ifdef CONFIG_IXGBE_HWMON |
362 | ||
363 | #define IXGBE_HWMON_TYPE_LOC 0 | |
364 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
365 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
366 | #define IXGBE_HWMON_TYPE_MAX 3 | |
367 | ||
368 | struct hwmon_attr { | |
369 | struct device_attribute dev_attr; | |
370 | struct ixgbe_hw *hw; | |
371 | struct ixgbe_thermal_diode_data *sensor; | |
372 | char name[12]; | |
373 | }; | |
374 | ||
375 | struct hwmon_buff { | |
376 | struct device *device; | |
377 | struct hwmon_attr *hwmon_list; | |
378 | unsigned int n_hwmon; | |
379 | }; | |
380 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 381 | |
d5bf4f67 ET |
382 | /* |
383 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
384 | * with the first 3 bits reserved 0 | |
9a799d71 | 385 | */ |
d5bf4f67 ET |
386 | #define IXGBE_MIN_RSC_ITR 24 |
387 | #define IXGBE_100K_ITR 40 | |
388 | #define IXGBE_20K_ITR 200 | |
389 | #define IXGBE_10K_ITR 400 | |
390 | #define IXGBE_8K_ITR 500 | |
9a799d71 | 391 | |
f56e0cb1 AD |
392 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
393 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
394 | const u32 stat_err_bits) | |
395 | { | |
396 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
397 | } | |
398 | ||
7d4987de AD |
399 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
400 | { | |
401 | u16 ntc = ring->next_to_clean; | |
402 | u16 ntu = ring->next_to_use; | |
403 | ||
404 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
405 | } | |
9a799d71 | 406 | |
e4f74028 | 407 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 408 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 409 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 410 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 411 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 412 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 413 | |
c88887e0 | 414 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
415 | #ifdef IXGBE_FCOE |
416 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
417 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
418 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 419 | |
021230d4 AV |
420 | #define OTHER_VECTOR 1 |
421 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
422 | ||
e8e26350 | 423 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 424 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 425 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 426 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 427 | |
49c7ffbe | 428 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 429 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 430 | |
8f15486d | 431 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
432 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
433 | ||
46646e61 AD |
434 | /* default to trying for four seconds */ |
435 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
436 | ||
9a799d71 AK |
437 | /* board specific private data structure */ |
438 | struct ixgbe_adapter { | |
46646e61 AD |
439 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
440 | /* OS defined structs */ | |
441 | struct net_device *netdev; | |
442 | struct pci_dev *pdev; | |
443 | ||
e606bfe7 AD |
444 | unsigned long state; |
445 | ||
446 | /* Some features need tri-state capability, | |
447 | * thus the additional *_CAPABLE flags. | |
448 | */ | |
449 | u32 flags; | |
a16a0d2f AD |
450 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0) |
451 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) | |
452 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2) | |
453 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) | |
454 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) | |
455 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) | |
456 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) | |
457 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) | |
458 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) | |
459 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) | |
460 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) | |
461 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) | |
462 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) | |
463 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) | |
464 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) | |
465 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) | |
466 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) | |
467 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) | |
468 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) | |
469 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) | |
470 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) | |
471 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) | |
472 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) | |
473 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) | |
e606bfe7 AD |
474 | |
475 | u32 flags2; | |
a16a0d2f | 476 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) |
e606bfe7 AD |
477 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) |
478 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 479 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
480 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
481 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 482 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 483 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
ef6afc0c AD |
484 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) |
485 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) | |
1a71ab24 | 486 | #define IXGBE_FLAG2_PTP_ENABLED (u32)(1 << 10) |
681ae1ad | 487 | #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11) |
d033d526 | 488 | |
46646e61 AD |
489 | /* Tx fast path data */ |
490 | int num_tx_queues; | |
491 | u16 tx_itr_setting; | |
bd198058 AD |
492 | u16 tx_work_limit; |
493 | ||
46646e61 AD |
494 | /* Rx fast path data */ |
495 | int num_rx_queues; | |
496 | u16 rx_itr_setting; | |
497 | ||
9a799d71 | 498 | /* TX */ |
4a0b9ca0 | 499 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 500 | |
7ca3bc58 JB |
501 | u64 restart_queue; |
502 | u64 lsc_int; | |
46646e61 | 503 | u32 tx_timeout_count; |
7ca3bc58 | 504 | |
9a799d71 | 505 | /* RX */ |
46646e61 | 506 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
507 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
508 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 509 | u64 hw_csum_rx_error; |
e8e26350 | 510 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
511 | u64 rsc_total_count; |
512 | u64 rsc_total_flush; | |
9a799d71 | 513 | u64 non_eop_descs; |
9a799d71 AK |
514 | u32 alloc_rx_page_failed; |
515 | u32 alloc_rx_buff_failed; | |
516 | ||
49c7ffbe | 517 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 518 | |
46646e61 AD |
519 | /* DCB parameters */ |
520 | struct ieee_pfc *ixgbe_ieee_pfc; | |
521 | struct ieee_ets *ixgbe_ieee_ets; | |
522 | struct ixgbe_dcb_config dcb_cfg; | |
523 | struct ixgbe_dcb_config temp_dcb_cfg; | |
524 | u8 dcb_set_bitmap; | |
525 | u8 dcbx_cap; | |
526 | enum ixgbe_fc_mode last_lfc_mode; | |
527 | ||
49c7ffbe AD |
528 | int num_q_vectors; /* current number of q_vectors for device */ |
529 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
530 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
531 | struct msix_entry *msix_entries; | |
9a799d71 | 532 | |
da4dd0f7 PWJ |
533 | u32 test_icr; |
534 | struct ixgbe_ring test_tx_ring; | |
535 | struct ixgbe_ring test_rx_ring; | |
536 | ||
9a799d71 AK |
537 | /* structs defined in ixgbe_hw.h */ |
538 | struct ixgbe_hw hw; | |
539 | u16 msg_enable; | |
540 | struct ixgbe_hw_stats stats; | |
021230d4 | 541 | |
9a799d71 | 542 | u64 tx_busy; |
30efa5a3 JB |
543 | unsigned int tx_ring_count; |
544 | unsigned int rx_ring_count; | |
cf8280ee JB |
545 | |
546 | u32 link_speed; | |
547 | bool link_up; | |
548 | unsigned long link_check_timeout; | |
549 | ||
7086400d | 550 | struct timer_list service_timer; |
46646e61 AD |
551 | struct work_struct service_task; |
552 | ||
553 | struct hlist_head fdir_filter_list; | |
554 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
555 | union ixgbe_atr_input fdir_mask; | |
556 | int fdir_filter_count; | |
c4cf55e5 PWJ |
557 | u32 fdir_pballoc; |
558 | u32 atr_sample_rate; | |
559 | spinlock_t fdir_perfect_lock; | |
46646e61 | 560 | |
d0ed8937 YZ |
561 | #ifdef IXGBE_FCOE |
562 | struct ixgbe_fcoe fcoe; | |
563 | #endif /* IXGBE_FCOE */ | |
e8e26350 | 564 | u32 wol; |
46646e61 | 565 | |
46646e61 AD |
566 | u16 bd_number; |
567 | ||
15e5209f ET |
568 | u16 eeprom_verh; |
569 | u16 eeprom_verl; | |
c23f5b6b | 570 | u16 eeprom_cap; |
7f870475 | 571 | |
119fc60a | 572 | u32 interrupt_event; |
46646e61 | 573 | u32 led_reg; |
1a6c14a2 | 574 | |
3a6a4eda JK |
575 | #ifdef CONFIG_IXGBE_PTP |
576 | struct ptp_clock *ptp_clock; | |
577 | struct ptp_clock_info ptp_caps; | |
578 | unsigned long last_overflow_check; | |
579 | spinlock_t tmreg_lock; | |
580 | struct cyclecounter cc; | |
581 | struct timecounter tc; | |
1d1a79b5 | 582 | int rx_hwtstamp_filter; |
3a6a4eda | 583 | u32 base_incval; |
3a6a4eda JK |
584 | #endif /* CONFIG_IXGBE_PTP */ |
585 | ||
7f870475 GR |
586 | /* SR-IOV */ |
587 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
588 | unsigned int num_vfs; | |
589 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 590 | int vf_rate_link_speed; |
a1cbb15c GR |
591 | struct vf_macvlans vf_mvs; |
592 | struct vf_macvlans *mv_list; | |
3e05334f | 593 | |
83c61fa9 GR |
594 | u32 timer_event_accumulator; |
595 | u32 vferr_refcount; | |
3ca8bc6d DS |
596 | struct kobject *info_kobj; |
597 | #ifdef CONFIG_IXGBE_HWMON | |
598 | struct hwmon_buff ixgbe_hwmon_buff; | |
599 | #endif /* CONFIG_IXGBE_HWMON */ | |
00949167 CS |
600 | #ifdef CONFIG_DEBUG_FS |
601 | struct dentry *ixgbe_dbg_adapter; | |
602 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
603 | |
604 | u8 default_up; | |
3e05334f AD |
605 | }; |
606 | ||
607 | struct ixgbe_fdir_filter { | |
608 | struct hlist_node fdir_node; | |
609 | union ixgbe_atr_input filter; | |
610 | u16 sw_idx; | |
611 | u16 action; | |
9a799d71 AK |
612 | }; |
613 | ||
70e5576c | 614 | enum ixgbe_state_t { |
9a799d71 AK |
615 | __IXGBE_TESTING, |
616 | __IXGBE_RESETTING, | |
c4900be0 | 617 | __IXGBE_DOWN, |
7086400d AD |
618 | __IXGBE_SERVICE_SCHED, |
619 | __IXGBE_IN_SFP_INIT, | |
9a799d71 AK |
620 | }; |
621 | ||
4c1975d7 AD |
622 | struct ixgbe_cb { |
623 | union { /* Union defining head/tail partner */ | |
624 | struct sk_buff *head; | |
625 | struct sk_buff *tail; | |
626 | }; | |
aa80175a | 627 | dma_addr_t dma; |
4c1975d7 | 628 | u16 append_cnt; |
f800326d | 629 | bool page_released; |
aa80175a | 630 | }; |
4c1975d7 | 631 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 632 | |
9a799d71 | 633 | enum ixgbe_boards { |
3957d63d | 634 | board_82598, |
e8e26350 | 635 | board_82599, |
fe15e8e1 | 636 | board_X540, |
9a799d71 AK |
637 | }; |
638 | ||
3957d63d | 639 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 640 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 641 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 642 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 643 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 644 | #endif |
9a799d71 AK |
645 | |
646 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 647 | extern const char ixgbe_driver_version[]; |
8af3c33f | 648 | #ifdef IXGBE_FCOE |
ea81875a | 649 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 650 | #endif /* IXGBE_FCOE */ |
9a799d71 | 651 | |
c7ccde0f | 652 | extern void ixgbe_up(struct ixgbe_adapter *adapter); |
9a799d71 | 653 | extern void ixgbe_down(struct ixgbe_adapter *adapter); |
d4f80882 | 654 | extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); |
9a799d71 | 655 | extern void ixgbe_reset(struct ixgbe_adapter *adapter); |
9a799d71 | 656 | extern void ixgbe_set_ethtool_ops(struct net_device *netdev); |
b6ec895e AD |
657 | extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); |
658 | extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
659 | extern void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
660 | extern void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
84418e3b AD |
661 | extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); |
662 | extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); | |
2d39d576 YZ |
663 | extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
664 | struct ixgbe_ring *); | |
b4617240 | 665 | extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); |
2f90b865 | 666 | extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); |
8e2813f5 JK |
667 | extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, |
668 | u16 subdevice_id); | |
7a921c93 | 669 | extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
84418e3b | 670 | extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, |
84418e3b AD |
671 | struct ixgbe_adapter *, |
672 | struct ixgbe_ring *); | |
b6ec895e | 673 | extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, |
84418e3b | 674 | struct ixgbe_tx_buffer *); |
fc77dc3c | 675 | extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); |
fe49f04a | 676 | extern void ixgbe_write_eitr(struct ixgbe_q_vector *); |
8af3c33f | 677 | extern int ixgbe_poll(struct napi_struct *napi, int budget); |
fe49f04a | 678 | extern int ethtool_ioctl(struct ifreq *ifr); |
ffff4772 | 679 | extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); |
c04f6ca8 AD |
680 | extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); |
681 | extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
ffff4772 | 682 | extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, |
69830529 AD |
683 | union ixgbe_atr_hash_dword input, |
684 | union ixgbe_atr_hash_dword common, | |
ffff4772 | 685 | u8 queue); |
c04f6ca8 AD |
686 | extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, |
687 | union ixgbe_atr_input *input_mask); | |
688 | extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
689 | union ixgbe_atr_input *input, | |
690 | u16 soft_id, u8 queue); | |
691 | extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
692 | union ixgbe_atr_input *input, | |
693 | u16 soft_id); | |
694 | extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
695 | union ixgbe_atr_input *mask); | |
7f870475 | 696 | extern void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 697 | #ifdef CONFIG_IXGBE_DCB |
3ebe8fde | 698 | extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
e5b64635 | 699 | extern int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
8af3c33f | 700 | #endif |
897ab156 | 701 | extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); |
082757af | 702 | extern void ixgbe_do_reset(struct net_device *netdev); |
1210982b | 703 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
704 | extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
705 | extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 706 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 YZ |
707 | #ifdef IXGBE_FCOE |
708 | extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); | |
fd0db0ed AD |
709 | extern int ixgbe_fso(struct ixgbe_ring *tx_ring, |
710 | struct ixgbe_tx_buffer *first, | |
244e27ad | 711 | u8 *hdr_len); |
332d4a7d | 712 | extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, |
ff886dfc | 713 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 714 | struct sk_buff *skb); |
332d4a7d YZ |
715 | extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, |
716 | struct scatterlist *sgl, unsigned int sgc); | |
68a683cf YZ |
717 | extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, |
718 | struct scatterlist *sgl, unsigned int sgc); | |
332d4a7d | 719 | extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); |
7c8ae65a AD |
720 | extern int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); |
721 | extern void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
8450ff8c YZ |
722 | extern int ixgbe_fcoe_enable(struct net_device *netdev); |
723 | extern int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 YZ |
724 | #ifdef CONFIG_IXGBE_DCB |
725 | extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); | |
726 | extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
727 | #endif /* CONFIG_IXGBE_DCB */ | |
61a1fa10 | 728 | extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
ea81875a NP |
729 | extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, |
730 | struct netdev_fcoe_hbainfo *info); | |
800bd607 | 731 | extern u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); |
eacd73f7 | 732 | #endif /* IXGBE_FCOE */ |
00949167 CS |
733 | #ifdef CONFIG_DEBUG_FS |
734 | extern void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); | |
735 | extern void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
736 | extern void ixgbe_dbg_init(void); | |
737 | extern void ixgbe_dbg_exit(void); | |
738 | #endif /* CONFIG_DEBUG_FS */ | |
b2d96e0a AD |
739 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
740 | { | |
741 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
742 | } | |
743 | ||
3a6a4eda JK |
744 | #ifdef CONFIG_IXGBE_PTP |
745 | extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter); | |
746 | extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); | |
747 | extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
748 | extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector, | |
749 | struct sk_buff *skb); | |
750 | extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, | |
1d1a79b5 | 751 | union ixgbe_adv_rx_desc *rx_desc, |
3a6a4eda JK |
752 | struct sk_buff *skb); |
753 | extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, | |
754 | struct ifreq *ifr, int cmd); | |
755 | extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); | |
1a71ab24 | 756 | extern void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); |
681ae1ad | 757 | extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); |
3a6a4eda JK |
758 | #endif /* CONFIG_IXGBE_PTP */ |
759 | ||
9a799d71 | 760 | #endif /* _IXGBE_H_ */ |