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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
37689010 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_H_ | |
30 | #define _IXGBE_H_ | |
31 | ||
f62bbb5e | 32 | #include <linux/bitops.h> |
9a799d71 AK |
33 | #include <linux/types.h> |
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
b25ebfd2 | 36 | #include <linux/cpumask.h> |
6fabd715 | 37 | #include <linux/aer.h> |
f62bbb5e | 38 | #include <linux/if_vlan.h> |
6cb562d6 | 39 | #include <linux/jiffies.h> |
9a799d71 | 40 | |
74d23cc7 | 41 | #include <linux/timecounter.h> |
3a6a4eda JK |
42 | #include <linux/net_tstamp.h> |
43 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 44 | |
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
ee58c114 | 48 | #if IS_ENABLED(CONFIG_FCOE) |
eacd73f7 YZ |
49 | #define IXGBE_FCOE |
50 | #include "ixgbe_fcoe.h" | |
ee58c114 | 51 | #endif /* IS_ENABLED(CONFIG_FCOE) */ |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
076bb0c8 | 56 | #include <net/busy_poll.h> |
5a85e737 | 57 | |
849c4542 ET |
58 | /* common prefix used by pr_<> macros */ |
59 | #undef pr_fmt | |
60 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
61 | |
62 | /* TX/RX descriptor defines */ | |
6bacb300 | 63 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 64 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
65 | #define IXGBE_MAX_TXD 4096 |
66 | #define IXGBE_MIN_TXD 64 | |
67 | ||
fb44519d | 68 | #if (PAGE_SIZE < 8192) |
6bacb300 | 69 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
70 | #else |
71 | #define IXGBE_DEFAULT_RXD 128 | |
72 | #endif | |
9a799d71 AK |
73 | #define IXGBE_MAX_RXD 4096 |
74 | #define IXGBE_MIN_RXD 64 | |
75 | ||
5b7f000f DS |
76 | #define IXGBE_ETH_P_LLDP 0x88CC |
77 | ||
9a799d71 | 78 | /* flow control */ |
2b9ade93 | 79 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 80 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 81 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 82 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 83 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
84 | #define IXGBE_MIN_FCPAUSE 0 |
85 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
86 | ||
87 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 88 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
89 | #define IXGBE_RXBUFFER_2K 2048 |
90 | #define IXGBE_RXBUFFER_3K 3072 | |
91 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 92 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 93 | |
2de6aa3a AD |
94 | #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) |
95 | #if (PAGE_SIZE < 8192) | |
96 | #define IXGBE_MAX_FRAME_BUILD_SKB \ | |
97 | (SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K) - IXGBE_SKB_PAD) | |
98 | #else | |
c74042f3 | 99 | #define IXGBE_MAX_FRAME_BUILD_SKB IXGBE_RXBUFFER_2K |
2de6aa3a AD |
100 | #endif |
101 | ||
13958070 | 102 | /* |
252562c2 AD |
103 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
104 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
105 | * this adds up to 448 bytes of extra data. | |
106 | * | |
107 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
108 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 109 | */ |
252562c2 | 110 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 111 | |
9a799d71 AK |
112 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
113 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
114 | ||
f3213d93 AD |
115 | #define IXGBE_RX_DMA_ATTR \ |
116 | (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) | |
117 | ||
472148c3 AD |
118 | enum ixgbe_tx_flags { |
119 | /* cmd_type flags */ | |
120 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
121 | IXGBE_TX_FLAGS_TSO = 0x02, | |
122 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
123 | ||
124 | /* olinfo flags */ | |
125 | IXGBE_TX_FLAGS_CC = 0x08, | |
126 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
127 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
128 | ||
129 | /* software defined flags */ | |
130 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
131 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
132 | }; | |
133 | ||
134 | /* VLAN info */ | |
9a799d71 | 135 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
136 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
137 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
138 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
139 | ||
7f870475 GR |
140 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
141 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
142 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
143 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 144 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 145 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
146 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
147 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
148 | |
149 | struct vf_data_storage { | |
988d1307 | 150 | struct pci_dev *vfdev; |
7f870475 GR |
151 | unsigned char vf_mac_addresses[ETH_ALEN]; |
152 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
153 | u16 num_vf_mc_hashes; | |
7f870475 | 154 | bool clear_to_send; |
7f01648a | 155 | bool pf_set_mac; |
7f01648a GR |
156 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
157 | u16 pf_qos; | |
ff4ab206 | 158 | u16 tx_rate; |
de4c7f65 | 159 | u8 spoofchk_enabled; |
e65ce0d3 | 160 | bool rss_query_enabled; |
54011e4d | 161 | u8 trusted; |
8443c1a4 | 162 | int xcast_mode; |
374c65d6 | 163 | unsigned int vf_api; |
7f870475 GR |
164 | }; |
165 | ||
8443c1a4 HS |
166 | enum ixgbevf_xcast_modes { |
167 | IXGBEVF_XCAST_MODE_NONE = 0, | |
168 | IXGBEVF_XCAST_MODE_MULTI, | |
169 | IXGBEVF_XCAST_MODE_ALLMULTI, | |
07eea570 | 170 | IXGBEVF_XCAST_MODE_PROMISC, |
8443c1a4 HS |
171 | }; |
172 | ||
a1cbb15c GR |
173 | struct vf_macvlans { |
174 | struct list_head l; | |
175 | int vf; | |
a1cbb15c GR |
176 | bool free; |
177 | bool is_macvlan; | |
178 | u8 vf_macvlan[ETH_ALEN]; | |
179 | }; | |
180 | ||
a535c30e | 181 | #define IXGBE_MAX_TXD_PWR 14 |
b4f47a48 | 182 | #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) |
a535c30e AD |
183 | |
184 | /* Tx Descriptors needed, worst case */ | |
185 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 186 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 187 | |
9a799d71 AK |
188 | /* wrapper around a pointer to a socket buffer, |
189 | * so a DMA handle can be stored along with the buffer */ | |
190 | struct ixgbe_tx_buffer { | |
d3d00239 | 191 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 192 | unsigned long time_stamp; |
fd0db0ed AD |
193 | struct sk_buff *skb; |
194 | unsigned int bytecount; | |
195 | unsigned short gso_segs; | |
244e27ad | 196 | __be16 protocol; |
729739b7 AD |
197 | DEFINE_DMA_UNMAP_ADDR(dma); |
198 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 199 | u32 tx_flags; |
9a799d71 AK |
200 | }; |
201 | ||
202 | struct ixgbe_rx_buffer { | |
203 | struct sk_buff *skb; | |
204 | dma_addr_t dma; | |
205 | struct page *page; | |
1b56cf49 AD |
206 | #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) |
207 | __u32 page_offset; | |
208 | #else | |
209 | __u16 page_offset; | |
210 | #endif | |
211 | __u16 pagecnt_bias; | |
9a799d71 AK |
212 | }; |
213 | ||
214 | struct ixgbe_queue_stats { | |
215 | u64 packets; | |
216 | u64 bytes; | |
217 | }; | |
218 | ||
5b7da515 AD |
219 | struct ixgbe_tx_queue_stats { |
220 | u64 restart_queue; | |
221 | u64 tx_busy; | |
c84d324c | 222 | u64 tx_done_old; |
5b7da515 AD |
223 | }; |
224 | ||
225 | struct ixgbe_rx_queue_stats { | |
226 | u64 rsc_count; | |
227 | u64 rsc_flush; | |
228 | u64 non_eop_descs; | |
229 | u64 alloc_rx_page_failed; | |
230 | u64 alloc_rx_buff_failed; | |
8a0da21b | 231 | u64 csum_err; |
5b7da515 AD |
232 | }; |
233 | ||
a9763f3c MR |
234 | #define IXGBE_TS_HDR_LEN 8 |
235 | ||
f800326d | 236 | enum ixgbe_ring_state_t { |
4f4542bf | 237 | __IXGBE_RX_3K_BUFFER, |
2de6aa3a | 238 | __IXGBE_RX_BUILD_SKB_ENABLED, |
4f4542bf AD |
239 | __IXGBE_RX_RSC_ENABLED, |
240 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, | |
241 | __IXGBE_RX_FCOE, | |
7d637bcc | 242 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 243 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 244 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 245 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc AD |
246 | }; |
247 | ||
2de6aa3a AD |
248 | #define ring_uses_build_skb(ring) \ |
249 | test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) | |
250 | ||
2a47fa45 JF |
251 | struct ixgbe_fwd_adapter { |
252 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
253 | struct net_device *netdev; | |
254 | struct ixgbe_adapter *real_adapter; | |
255 | unsigned int tx_base_queue; | |
256 | unsigned int rx_base_queue; | |
257 | int pool; | |
258 | }; | |
259 | ||
7d637bcc AD |
260 | #define check_for_tx_hang(ring) \ |
261 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
262 | #define set_check_for_tx_hang(ring) \ | |
263 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
264 | #define clear_check_for_tx_hang(ring) \ | |
265 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
266 | #define ring_is_rsc_enabled(ring) \ | |
267 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
268 | #define set_ring_rsc_enabled(ring) \ | |
269 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
270 | #define clear_ring_rsc_enabled(ring) \ | |
271 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 272 | struct ixgbe_ring { |
efe3d3c8 | 273 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
274 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
275 | struct net_device *netdev; /* netdev ring belongs to */ | |
276 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 277 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 278 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
279 | union { |
280 | struct ixgbe_tx_buffer *tx_buffer_info; | |
281 | struct ixgbe_rx_buffer *rx_buffer_info; | |
282 | }; | |
7d637bcc | 283 | unsigned long state; |
bd198058 | 284 | u8 __iomem *tail; |
d3ee4294 AD |
285 | dma_addr_t dma; /* phys. address of descriptor ring */ |
286 | unsigned int size; /* length in bytes */ | |
bd198058 | 287 | |
ae540af1 | 288 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
289 | |
290 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
291 | u8 reg_idx; /* holds the special value that gets |
292 | * the hardware register offset | |
293 | * associated with this ring, which is | |
294 | * different for DCB and RSS modes | |
295 | */ | |
d3ee4294 AD |
296 | u16 next_to_use; |
297 | u16 next_to_clean; | |
298 | ||
a9763f3c MR |
299 | unsigned long last_rx_timestamp; |
300 | ||
f800326d | 301 | union { |
d3ee4294 | 302 | u16 next_to_alloc; |
f800326d AD |
303 | struct { |
304 | u8 atr_sample_rate; | |
305 | u8 atr_count; | |
306 | }; | |
f800326d | 307 | }; |
9a799d71 | 308 | |
bd198058 | 309 | u8 dcb_tc; |
9a799d71 | 310 | struct ixgbe_queue_stats stats; |
de1036b1 | 311 | struct u64_stats_sync syncp; |
5b7da515 AD |
312 | union { |
313 | struct ixgbe_tx_queue_stats tx_stats; | |
314 | struct ixgbe_rx_queue_stats rx_stats; | |
315 | }; | |
7ca3bc58 | 316 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 317 | |
c7e4358a SN |
318 | enum ixgbe_ring_f_enum { |
319 | RING_F_NONE = 0, | |
7f870475 | 320 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 321 | RING_F_RSS, |
c4cf55e5 | 322 | RING_F_FDIR, |
0331a832 YZ |
323 | #ifdef IXGBE_FCOE |
324 | RING_F_FCOE, | |
325 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
326 | |
327 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
328 | }; | |
329 | ||
0f9b232b | 330 | #define IXGBE_MAX_RSS_INDICES 16 |
e9ee3238 | 331 | #define IXGBE_MAX_RSS_INDICES_X550 63 |
0f9b232b DS |
332 | #define IXGBE_MAX_VMDQ_INDICES 64 |
333 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ | |
334 | #define IXGBE_MAX_FCOE_INDICES 8 | |
335 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
336 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
337 | #define IXGBE_MAX_L2A_QUEUES 4 | |
338 | #define IXGBE_BAD_L2A_QUEUE 3 | |
339 | #define IXGBE_MAX_MACVLANS 31 | |
340 | #define IXGBE_MAX_DCBMACVLANS 8 | |
2a47fa45 | 341 | |
021230d4 | 342 | struct ixgbe_ring_feature { |
c087663e AD |
343 | u16 limit; /* upper limit on feature indices */ |
344 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
345 | u16 mask; /* Mask used for feature to ring mapping */ |
346 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 347 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 348 | |
73079ea0 AD |
349 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
350 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
351 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
352 | ||
f800326d AD |
353 | /* |
354 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
355 | * this is twice the size of a half page we need to double the page order | |
356 | * for FCoE enabled Rx queues. | |
357 | */ | |
09816fbe | 358 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 359 | { |
4f4542bf AD |
360 | if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) |
361 | return IXGBE_RXBUFFER_3K; | |
2de6aa3a AD |
362 | #if (PAGE_SIZE < 8192) |
363 | if (ring_uses_build_skb(ring)) | |
364 | return IXGBE_MAX_FRAME_BUILD_SKB; | |
365 | #endif | |
09816fbe | 366 | return IXGBE_RXBUFFER_2K; |
f800326d | 367 | } |
09816fbe AD |
368 | |
369 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
370 | { | |
4f4542bf AD |
371 | #if (PAGE_SIZE < 8192) |
372 | if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) | |
373 | return 1; | |
f800326d | 374 | #endif |
09816fbe AD |
375 | return 0; |
376 | } | |
f800326d | 377 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 378 | |
08c8833b | 379 | struct ixgbe_ring_container { |
efe3d3c8 | 380 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
381 | unsigned int total_bytes; /* total bytes processed this int */ |
382 | unsigned int total_packets; /* total packets processed this int */ | |
383 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
384 | u8 count; /* total number of rings in vector */ |
385 | u8 itr; /* current ITR setting for ring */ | |
386 | }; | |
021230d4 | 387 | |
a557928e AD |
388 | /* iterator for handling rings in ring container */ |
389 | #define ixgbe_for_each_ring(pos, head) \ | |
390 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
391 | ||
2f90b865 | 392 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
e7cf745b | 393 | ? 8 : 1) |
2f90b865 AD |
394 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS |
395 | ||
49c7ffbe | 396 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
397 | * but we only use one per queue-specific vector. |
398 | */ | |
399 | struct ixgbe_q_vector { | |
400 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
401 | #ifdef CONFIG_IXGBE_DCA |
402 | int cpu; /* CPU for DCA */ | |
403 | #endif | |
d5bf4f67 ET |
404 | u16 v_idx; /* index of q_vector within array, also used for |
405 | * finding the bit in EICR and friends that | |
406 | * represents the vector for this ring */ | |
407 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 408 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
409 | |
410 | struct napi_struct napi; | |
de88eeeb AD |
411 | cpumask_t affinity_mask; |
412 | int numa_node; | |
413 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 414 | char name[IFNAMSIZ + 9]; |
de88eeeb AD |
415 | |
416 | /* for dynamic allocation of rings associated with this q_vector */ | |
417 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 418 | }; |
adc81090 | 419 | |
3ca8bc6d DS |
420 | #ifdef CONFIG_IXGBE_HWMON |
421 | ||
422 | #define IXGBE_HWMON_TYPE_LOC 0 | |
423 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
424 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
425 | #define IXGBE_HWMON_TYPE_MAX 3 | |
426 | ||
427 | struct hwmon_attr { | |
428 | struct device_attribute dev_attr; | |
429 | struct ixgbe_hw *hw; | |
430 | struct ixgbe_thermal_diode_data *sensor; | |
431 | char name[12]; | |
432 | }; | |
433 | ||
434 | struct hwmon_buff { | |
03b77d81 GR |
435 | struct attribute_group group; |
436 | const struct attribute_group *groups[2]; | |
437 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
438 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
439 | unsigned int n_hwmon; |
440 | }; | |
441 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 442 | |
d5bf4f67 ET |
443 | /* |
444 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
445 | * with the first 3 bits reserved 0 | |
9a799d71 | 446 | */ |
d5bf4f67 ET |
447 | #define IXGBE_MIN_RSC_ITR 24 |
448 | #define IXGBE_100K_ITR 40 | |
449 | #define IXGBE_20K_ITR 200 | |
8ac34f10 | 450 | #define IXGBE_12K_ITR 336 |
9a799d71 | 451 | |
f56e0cb1 AD |
452 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
453 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
454 | const u32 stat_err_bits) | |
455 | { | |
456 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
457 | } | |
458 | ||
7d4987de AD |
459 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
460 | { | |
461 | u16 ntc = ring->next_to_clean; | |
462 | u16 ntu = ring->next_to_use; | |
463 | ||
464 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
465 | } | |
9a799d71 | 466 | |
e4f74028 | 467 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 468 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 469 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 470 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 471 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 472 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 473 | |
c88887e0 | 474 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
475 | #ifdef IXGBE_FCOE |
476 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
477 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
478 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 479 | |
021230d4 AV |
480 | #define OTHER_VECTOR 1 |
481 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
482 | ||
e8e26350 | 483 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 484 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 485 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 486 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 487 | |
5d7daa35 JK |
488 | struct ixgbe_mac_addr { |
489 | u8 addr[ETH_ALEN]; | |
c9f53e63 | 490 | u16 pool; |
5d7daa35 JK |
491 | u16 state; /* bitmask */ |
492 | }; | |
c9f53e63 | 493 | |
5d7daa35 JK |
494 | #define IXGBE_MAC_STATE_DEFAULT 0x1 |
495 | #define IXGBE_MAC_STATE_MODIFIED 0x2 | |
496 | #define IXGBE_MAC_STATE_IN_USE 0x4 | |
497 | ||
49c7ffbe | 498 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 499 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 500 | |
8f15486d | 501 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
502 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
503 | ||
46646e61 AD |
504 | /* default to trying for four seconds */ |
505 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
58e7cd24 | 506 | #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ |
46646e61 | 507 | |
9a799d71 AK |
508 | /* board specific private data structure */ |
509 | struct ixgbe_adapter { | |
46646e61 AD |
510 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
511 | /* OS defined structs */ | |
512 | struct net_device *netdev; | |
513 | struct pci_dev *pdev; | |
514 | ||
e606bfe7 AD |
515 | unsigned long state; |
516 | ||
517 | /* Some features need tri-state capability, | |
518 | * thus the additional *_CAPABLE flags. | |
519 | */ | |
520 | u32 flags; | |
b4f47a48 JK |
521 | #define IXGBE_FLAG_MSI_ENABLED BIT(1) |
522 | #define IXGBE_FLAG_MSIX_ENABLED BIT(3) | |
523 | #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) | |
524 | #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) | |
525 | #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) | |
526 | #define IXGBE_FLAG_DCA_ENABLED BIT(8) | |
527 | #define IXGBE_FLAG_DCA_CAPABLE BIT(9) | |
528 | #define IXGBE_FLAG_IMIR_ENABLED BIT(10) | |
529 | #define IXGBE_FLAG_MQ_CAPABLE BIT(11) | |
530 | #define IXGBE_FLAG_DCB_ENABLED BIT(12) | |
531 | #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) | |
532 | #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) | |
533 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) | |
534 | #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) | |
535 | #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) | |
536 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) | |
537 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) | |
538 | #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) | |
539 | #define IXGBE_FLAG_FCOE_ENABLED BIT(21) | |
540 | #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) | |
541 | #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) | |
67359c3c | 542 | #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) |
a9763f3c MR |
543 | #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) |
544 | #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) | |
8829009d | 545 | #define IXGBE_FLAG_DCB_CAPABLE BIT(27) |
a21d0822 | 546 | #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28) |
e606bfe7 AD |
547 | |
548 | u32 flags2; | |
b4f47a48 JK |
549 | #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) |
550 | #define IXGBE_FLAG2_RSC_ENABLED BIT(1) | |
551 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) | |
552 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) | |
553 | #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) | |
554 | #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) | |
b4f47a48 JK |
555 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) |
556 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) | |
557 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) | |
558 | #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) | |
559 | #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) | |
a21d0822 | 560 | #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12) |
16369564 | 561 | #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) |
b3eb4e18 MR |
562 | #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) |
563 | #define IXGBE_FLAG2_EEE_ENABLED BIT(15) | |
2de6aa3a | 564 | #define IXGBE_FLAG2_RX_LEGACY BIT(16) |
d033d526 | 565 | |
46646e61 AD |
566 | /* Tx fast path data */ |
567 | int num_tx_queues; | |
568 | u16 tx_itr_setting; | |
bd198058 AD |
569 | u16 tx_work_limit; |
570 | ||
46646e61 AD |
571 | /* Rx fast path data */ |
572 | int num_rx_queues; | |
573 | u16 rx_itr_setting; | |
574 | ||
9f12df90 AD |
575 | /* Port number used to identify VXLAN traffic */ |
576 | __be16 vxlan_port; | |
a21d0822 | 577 | __be16 geneve_port; |
9f12df90 | 578 | |
9a799d71 | 579 | /* TX */ |
4a0b9ca0 | 580 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 581 | |
7ca3bc58 JB |
582 | u64 restart_queue; |
583 | u64 lsc_int; | |
46646e61 | 584 | u32 tx_timeout_count; |
7ca3bc58 | 585 | |
9a799d71 | 586 | /* RX */ |
46646e61 | 587 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
588 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
589 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 590 | u64 hw_csum_rx_error; |
e8e26350 | 591 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
592 | u64 rsc_total_count; |
593 | u64 rsc_total_flush; | |
9a799d71 | 594 | u64 non_eop_descs; |
9a799d71 AK |
595 | u32 alloc_rx_page_failed; |
596 | u32 alloc_rx_buff_failed; | |
597 | ||
49c7ffbe | 598 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 599 | |
46646e61 AD |
600 | /* DCB parameters */ |
601 | struct ieee_pfc *ixgbe_ieee_pfc; | |
602 | struct ieee_ets *ixgbe_ieee_ets; | |
603 | struct ixgbe_dcb_config dcb_cfg; | |
604 | struct ixgbe_dcb_config temp_dcb_cfg; | |
605 | u8 dcb_set_bitmap; | |
606 | u8 dcbx_cap; | |
607 | enum ixgbe_fc_mode last_lfc_mode; | |
608 | ||
49c7ffbe AD |
609 | int num_q_vectors; /* current number of q_vectors for device */ |
610 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
611 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
612 | struct msix_entry *msix_entries; | |
9a799d71 | 613 | |
da4dd0f7 PWJ |
614 | u32 test_icr; |
615 | struct ixgbe_ring test_tx_ring; | |
616 | struct ixgbe_ring test_rx_ring; | |
617 | ||
9a799d71 AK |
618 | /* structs defined in ixgbe_hw.h */ |
619 | struct ixgbe_hw hw; | |
620 | u16 msg_enable; | |
621 | struct ixgbe_hw_stats stats; | |
021230d4 | 622 | |
9a799d71 | 623 | u64 tx_busy; |
30efa5a3 JB |
624 | unsigned int tx_ring_count; |
625 | unsigned int rx_ring_count; | |
cf8280ee JB |
626 | |
627 | u32 link_speed; | |
628 | bool link_up; | |
58e7cd24 | 629 | unsigned long sfp_poll_time; |
cf8280ee JB |
630 | unsigned long link_check_timeout; |
631 | ||
7086400d | 632 | struct timer_list service_timer; |
46646e61 AD |
633 | struct work_struct service_task; |
634 | ||
635 | struct hlist_head fdir_filter_list; | |
636 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
637 | union ixgbe_atr_input fdir_mask; | |
638 | int fdir_filter_count; | |
c4cf55e5 PWJ |
639 | u32 fdir_pballoc; |
640 | u32 atr_sample_rate; | |
641 | spinlock_t fdir_perfect_lock; | |
46646e61 | 642 | |
d0ed8937 YZ |
643 | #ifdef IXGBE_FCOE |
644 | struct ixgbe_fcoe fcoe; | |
645 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 646 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 647 | u32 wol; |
46646e61 | 648 | |
aa2bacb6 DS |
649 | u16 bridge_mode; |
650 | ||
15e5209f ET |
651 | u16 eeprom_verh; |
652 | u16 eeprom_verl; | |
c23f5b6b | 653 | u16 eeprom_cap; |
7f870475 | 654 | |
119fc60a | 655 | u32 interrupt_event; |
46646e61 | 656 | u32 led_reg; |
1a6c14a2 | 657 | |
3a6a4eda JK |
658 | struct ptp_clock *ptp_clock; |
659 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
660 | struct work_struct ptp_tx_work; |
661 | struct sk_buff *ptp_tx_skb; | |
93501d48 | 662 | struct hwtstamp_config tstamp_config; |
891dc082 | 663 | unsigned long ptp_tx_start; |
3a6a4eda | 664 | unsigned long last_overflow_check; |
6cb562d6 | 665 | unsigned long last_rx_ptp_check; |
eda183c2 | 666 | unsigned long last_rx_timestamp; |
3a6a4eda | 667 | spinlock_t tmreg_lock; |
a9763f3c MR |
668 | struct cyclecounter hw_cc; |
669 | struct timecounter hw_tc; | |
3a6a4eda | 670 | u32 base_incval; |
a9763f3c MR |
671 | u32 tx_hwtstamp_timeouts; |
672 | u32 rx_hwtstamp_cleared; | |
673 | void (*ptp_setup_sdp)(struct ixgbe_adapter *); | |
3a6a4eda | 674 | |
7f870475 GR |
675 | /* SR-IOV */ |
676 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
677 | unsigned int num_vfs; | |
678 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 679 | int vf_rate_link_speed; |
a1cbb15c GR |
680 | struct vf_macvlans vf_mvs; |
681 | struct vf_macvlans *mv_list; | |
3e05334f | 682 | |
83c61fa9 GR |
683 | u32 timer_event_accumulator; |
684 | u32 vferr_refcount; | |
5d7daa35 | 685 | struct ixgbe_mac_addr *mac_table; |
3ca8bc6d DS |
686 | struct kobject *info_kobj; |
687 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 688 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 689 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
690 | #ifdef CONFIG_DEBUG_FS |
691 | struct dentry *ixgbe_dbg_adapter; | |
692 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
693 | |
694 | u8 default_up; | |
2a47fa45 | 695 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
dfaf891d | 696 | |
b82b17d9 | 697 | #define IXGBE_MAX_LINK_HANDLE 10 |
1cdaaf54 | 698 | struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; |
db956ae8 | 699 | unsigned long tables; |
b82b17d9 | 700 | |
dfaf891d VZ |
701 | /* maximum number of RETA entries among all devices supported by ixgbe |
702 | * driver: currently it's x550 device in non-SRIOV mode | |
703 | */ | |
704 | #define IXGBE_MAX_RETA_ENTRIES 512 | |
705 | u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; | |
706 | ||
707 | #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ | |
708 | u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; | |
3e05334f AD |
709 | }; |
710 | ||
0f9b232b DS |
711 | static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) |
712 | { | |
713 | switch (adapter->hw.mac.type) { | |
714 | case ixgbe_mac_82598EB: | |
715 | case ixgbe_mac_82599EB: | |
716 | case ixgbe_mac_X540: | |
717 | return IXGBE_MAX_RSS_INDICES; | |
718 | case ixgbe_mac_X550: | |
719 | case ixgbe_mac_X550EM_x: | |
49425dfc | 720 | case ixgbe_mac_x550em_a: |
0f9b232b DS |
721 | return IXGBE_MAX_RSS_INDICES_X550; |
722 | default: | |
723 | return 0; | |
724 | } | |
725 | } | |
726 | ||
3e05334f AD |
727 | struct ixgbe_fdir_filter { |
728 | struct hlist_node fdir_node; | |
729 | union ixgbe_atr_input filter; | |
730 | u16 sw_idx; | |
2a9ed5d1 | 731 | u64 action; |
9a799d71 AK |
732 | }; |
733 | ||
70e5576c | 734 | enum ixgbe_state_t { |
9a799d71 AK |
735 | __IXGBE_TESTING, |
736 | __IXGBE_RESETTING, | |
c4900be0 | 737 | __IXGBE_DOWN, |
41c62843 | 738 | __IXGBE_DISABLED, |
09f40aed | 739 | __IXGBE_REMOVING, |
7086400d | 740 | __IXGBE_SERVICE_SCHED, |
58cf663f | 741 | __IXGBE_SERVICE_INITED, |
7086400d | 742 | __IXGBE_IN_SFP_INIT, |
8fecf67c | 743 | __IXGBE_PTP_RUNNING, |
151b260c | 744 | __IXGBE_PTP_TX_IN_PROGRESS, |
57ca2a4f | 745 | __IXGBE_RESET_REQUESTED, |
9a799d71 AK |
746 | }; |
747 | ||
4c1975d7 AD |
748 | struct ixgbe_cb { |
749 | union { /* Union defining head/tail partner */ | |
750 | struct sk_buff *head; | |
751 | struct sk_buff *tail; | |
752 | }; | |
aa80175a | 753 | dma_addr_t dma; |
4c1975d7 | 754 | u16 append_cnt; |
f800326d | 755 | bool page_released; |
aa80175a | 756 | }; |
4c1975d7 | 757 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 758 | |
9a799d71 | 759 | enum ixgbe_boards { |
3957d63d | 760 | board_82598, |
e8e26350 | 761 | board_82599, |
fe15e8e1 | 762 | board_X540, |
6a14ee0c DS |
763 | board_X550, |
764 | board_X550EM_x, | |
49425dfc | 765 | board_x550em_a, |
b3eb4e18 | 766 | board_x550em_a_fw, |
9a799d71 AK |
767 | }; |
768 | ||
37689010 MR |
769 | extern const struct ixgbe_info ixgbe_82598_info; |
770 | extern const struct ixgbe_info ixgbe_82599_info; | |
771 | extern const struct ixgbe_info ixgbe_X540_info; | |
772 | extern const struct ixgbe_info ixgbe_X550_info; | |
773 | extern const struct ixgbe_info ixgbe_X550EM_x_info; | |
49425dfc | 774 | extern const struct ixgbe_info ixgbe_x550em_a_info; |
b3eb4e18 | 775 | extern const struct ixgbe_info ixgbe_x550em_a_fw_info; |
7a6b6f51 | 776 | #ifdef CONFIG_IXGBE_DCB |
3f40c74c | 777 | extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; |
2f90b865 | 778 | #endif |
9a799d71 AK |
779 | |
780 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 781 | extern const char ixgbe_driver_version[]; |
8af3c33f | 782 | #ifdef IXGBE_FCOE |
ea81875a | 783 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 784 | #endif /* IXGBE_FCOE */ |
9a799d71 | 785 | |
6c211fe1 SA |
786 | int ixgbe_open(struct net_device *netdev); |
787 | int ixgbe_close(struct net_device *netdev); | |
5ccc921a JP |
788 | void ixgbe_up(struct ixgbe_adapter *adapter); |
789 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
790 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
791 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
792 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
793 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
794 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
795 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
796 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
797 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
798 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
799 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
800 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
801 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
740234f0 ET |
802 | bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, |
803 | u16 subdevice_id); | |
5d7daa35 JK |
804 | #ifdef CONFIG_PCI_IOV |
805 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); | |
806 | #endif | |
807 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, | |
c9f53e63 | 808 | const u8 *addr, u16 queue); |
5d7daa35 | 809 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
c9f53e63 | 810 | const u8 *addr, u16 queue); |
e1d0a2af | 811 | void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); |
5ccc921a JP |
812 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
813 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
814 | struct ixgbe_ring *); | |
815 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
816 | struct ixgbe_tx_buffer *); | |
817 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
818 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
819 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
820 | int ethtool_ioctl(struct ifreq *ifr); | |
821 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
822 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
823 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
824 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
825 | union ixgbe_atr_hash_dword input, | |
826 | union ixgbe_atr_hash_dword common, | |
827 | u8 queue); | |
828 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
829 | union ixgbe_atr_input *input_mask); | |
830 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
831 | union ixgbe_atr_input *input, | |
832 | u16 soft_id, u8 queue); | |
833 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
834 | union ixgbe_atr_input *input, | |
835 | u16 soft_id); | |
836 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
837 | union ixgbe_atr_input *mask); | |
b82b17d9 JF |
838 | int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, |
839 | struct ixgbe_fdir_filter *input, | |
840 | u16 sw_idx); | |
5ccc921a | 841 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 842 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 843 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 844 | #endif |
5ccc921a JP |
845 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
846 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
847 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 848 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
849 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
850 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 851 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 852 | #ifdef IXGBE_FCOE |
5ccc921a JP |
853 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
854 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
855 | u8 *hdr_len); | |
856 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
857 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
858 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
859 | struct scatterlist *sgl, unsigned int sgc); | |
860 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
861 | struct scatterlist *sgl, unsigned int sgc); | |
862 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
863 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
864 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
865 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
866 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 867 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
868 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
869 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 870 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
871 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
872 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
873 | struct netdev_fcoe_hbainfo *info); | |
874 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 875 | #endif /* IXGBE_FCOE */ |
00949167 | 876 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
877 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
878 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
879 | void ixgbe_dbg_init(void); | |
880 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
881 | #else |
882 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
883 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
884 | static inline void ixgbe_dbg_init(void) {} | |
885 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 886 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
887 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
888 | { | |
889 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
890 | } | |
891 | ||
5ccc921a | 892 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
9966d1ee | 893 | void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); |
5ccc921a JP |
894 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); |
895 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
896 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
a9763f3c MR |
897 | void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); |
898 | void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); | |
899 | static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, | |
900 | union ixgbe_adv_rx_desc *rx_desc, | |
901 | struct sk_buff *skb) | |
902 | { | |
903 | if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { | |
904 | ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); | |
905 | return; | |
906 | } | |
907 | ||
908 | if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) | |
909 | return; | |
910 | ||
911 | ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); | |
912 | ||
913 | /* Update the last_rx_timestamp timer in order to enable watchdog check | |
914 | * for error case of latched timestamp on a dropped packet. | |
915 | */ | |
916 | rx_ring->last_rx_timestamp = jiffies; | |
917 | } | |
918 | ||
93501d48 JK |
919 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); |
920 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); | |
5ccc921a JP |
921 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); |
922 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
a9763f3c | 923 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); |
da36b647 GR |
924 | #ifdef CONFIG_PCI_IOV |
925 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
926 | #endif | |
3a6a4eda | 927 | |
2a47fa45 JF |
928 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
929 | struct ixgbe_adapter *adapter, | |
930 | struct ixgbe_ring *tx_ring); | |
7f276efb | 931 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); |
d3aa9c9f | 932 | void ixgbe_store_key(struct ixgbe_adapter *adapter); |
1c7cf078 | 933 | void ixgbe_store_reta(struct ixgbe_adapter *adapter); |
2916500d DS |
934 | s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, |
935 | u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); | |
9a799d71 | 936 | #endif /* _IXGBE_H_ */ |