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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_H_ | |
29 | #define _IXGBE_H_ | |
30 | ||
f62bbb5e | 31 | #include <linux/bitops.h> |
9a799d71 AK |
32 | #include <linux/types.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/netdevice.h> | |
b25ebfd2 | 35 | #include <linux/cpumask.h> |
6fabd715 | 36 | #include <linux/aer.h> |
f62bbb5e | 37 | #include <linux/if_vlan.h> |
9a799d71 AK |
38 | |
39 | #include "ixgbe_type.h" | |
40 | #include "ixgbe_common.h" | |
2f90b865 | 41 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
42 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
43 | #define IXGBE_FCOE | |
44 | #include "ixgbe_fcoe.h" | |
45 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 46 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
47 | #include <linux/dca.h> |
48 | #endif | |
9a799d71 | 49 | |
849c4542 ET |
50 | /* common prefix used by pr_<> macros */ |
51 | #undef pr_fmt | |
52 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
53 | |
54 | /* TX/RX descriptor defines */ | |
6bacb300 | 55 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 56 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
57 | #define IXGBE_MAX_TXD 4096 |
58 | #define IXGBE_MIN_TXD 64 | |
59 | ||
6bacb300 | 60 | #define IXGBE_DEFAULT_RXD 512 |
9a799d71 AK |
61 | #define IXGBE_MAX_RXD 4096 |
62 | #define IXGBE_MIN_RXD 64 | |
63 | ||
9a799d71 | 64 | /* flow control */ |
2b9ade93 | 65 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 66 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 67 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 68 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 69 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
70 | #define IXGBE_MIN_FCPAUSE 0 |
71 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
72 | ||
73 | /* Supported Rx Buffer Sizes */ | |
13958070 | 74 | #define IXGBE_RXBUFFER_512 512 /* Used for packet split */ |
919e78a6 AD |
75 | #define IXGBE_RXBUFFER_2K 2048 |
76 | #define IXGBE_RXBUFFER_3K 3072 | |
77 | #define IXGBE_RXBUFFER_4K 4096 | |
78 | #define IXGBE_RXBUFFER_7K 7168 | |
79 | #define IXGBE_RXBUFFER_8K 8192 | |
80 | #define IXGBE_RXBUFFER_15K 15360 | |
81 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ | |
9a799d71 | 82 | |
13958070 AD |
83 | /* |
84 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we | |
85 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, | |
86 | * this adds up to 512 bytes of extra data meaning the smallest allocation | |
87 | * we could have is 1K. | |
88 | * i.e. RXBUFFER_512 --> size-1024 slab | |
89 | */ | |
90 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512 | |
9a799d71 AK |
91 | |
92 | #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) | |
93 | ||
9a799d71 AK |
94 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
95 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
96 | ||
97 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) | |
66f32a8b AD |
98 | #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1) |
99 | #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2) | |
100 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3) | |
101 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4) | |
102 | #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5) | |
103 | #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6) | |
7f9643fd AD |
104 | #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7) |
105 | #define IXGBE_TX_FLAGS_MAPPED_AS_PAGE (u32)(1 << 8) | |
9a799d71 | 106 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
107 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
108 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
109 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
110 | ||
0a924578 PWJ |
111 | #define IXGBE_MAX_RSC_INT_RATE 162760 |
112 | ||
7f870475 GR |
113 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
114 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
115 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
116 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 117 | #define IXGBE_MAX_PF_MACVLANS 15 |
7f870475 GR |
118 | #define VMDQ_P(p) ((p) + adapter->num_vfs) |
119 | ||
120 | struct vf_data_storage { | |
121 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
122 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
123 | u16 num_vf_mc_hashes; | |
124 | u16 default_vf_vlan_id; | |
125 | u16 vlans_enabled; | |
7f870475 | 126 | bool clear_to_send; |
7f01648a | 127 | bool pf_set_mac; |
7f01648a GR |
128 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
129 | u16 pf_qos; | |
ff4ab206 | 130 | u16 tx_rate; |
7f870475 GR |
131 | }; |
132 | ||
a1cbb15c GR |
133 | struct vf_macvlans { |
134 | struct list_head l; | |
135 | int vf; | |
136 | int rar_entry; | |
137 | bool free; | |
138 | bool is_macvlan; | |
139 | u8 vf_macvlan[ETH_ALEN]; | |
140 | }; | |
141 | ||
a535c30e AD |
142 | #define IXGBE_MAX_TXD_PWR 14 |
143 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
144 | ||
145 | /* Tx Descriptors needed, worst case */ | |
146 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
147 | #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4) | |
148 | ||
9a799d71 AK |
149 | /* wrapper around a pointer to a socket buffer, |
150 | * so a DMA handle can be stored along with the buffer */ | |
151 | struct ixgbe_tx_buffer { | |
d3d00239 | 152 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 153 | unsigned long time_stamp; |
d3d00239 AD |
154 | dma_addr_t dma; |
155 | u32 length; | |
156 | u32 tx_flags; | |
157 | struct sk_buff *skb; | |
158 | u32 bytecount; | |
8ad494b0 | 159 | u16 gso_segs; |
9a799d71 AK |
160 | }; |
161 | ||
162 | struct ixgbe_rx_buffer { | |
163 | struct sk_buff *skb; | |
164 | dma_addr_t dma; | |
165 | struct page *page; | |
166 | dma_addr_t page_dma; | |
762f4c57 | 167 | unsigned int page_offset; |
9a799d71 AK |
168 | }; |
169 | ||
170 | struct ixgbe_queue_stats { | |
171 | u64 packets; | |
172 | u64 bytes; | |
173 | }; | |
174 | ||
5b7da515 AD |
175 | struct ixgbe_tx_queue_stats { |
176 | u64 restart_queue; | |
177 | u64 tx_busy; | |
c84d324c JF |
178 | u64 completed; |
179 | u64 tx_done_old; | |
5b7da515 AD |
180 | }; |
181 | ||
182 | struct ixgbe_rx_queue_stats { | |
183 | u64 rsc_count; | |
184 | u64 rsc_flush; | |
185 | u64 non_eop_descs; | |
186 | u64 alloc_rx_page_failed; | |
187 | u64 alloc_rx_buff_failed; | |
188 | }; | |
189 | ||
7d637bcc AD |
190 | enum ixbge_ring_state_t { |
191 | __IXGBE_TX_FDIR_INIT_DONE, | |
192 | __IXGBE_TX_DETECT_HANG, | |
c84d324c | 193 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc AD |
194 | __IXGBE_RX_PS_ENABLED, |
195 | __IXGBE_RX_RSC_ENABLED, | |
196 | }; | |
197 | ||
198 | #define ring_is_ps_enabled(ring) \ | |
199 | test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) | |
200 | #define set_ring_ps_enabled(ring) \ | |
201 | set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) | |
202 | #define clear_ring_ps_enabled(ring) \ | |
203 | clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) | |
204 | #define check_for_tx_hang(ring) \ | |
205 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
206 | #define set_check_for_tx_hang(ring) \ | |
207 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
208 | #define clear_check_for_tx_hang(ring) \ | |
209 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
210 | #define ring_is_rsc_enabled(ring) \ | |
211 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
212 | #define set_ring_rsc_enabled(ring) \ | |
213 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
214 | #define clear_ring_rsc_enabled(ring) \ | |
215 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 216 | struct ixgbe_ring { |
efe3d3c8 | 217 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
9a799d71 | 218 | void *desc; /* descriptor ring memory */ |
b6ec895e | 219 | struct device *dev; /* device for DMA mapping */ |
fc77dc3c | 220 | struct net_device *netdev; /* netdev ring belongs to */ |
9a799d71 AK |
221 | union { |
222 | struct ixgbe_tx_buffer *tx_buffer_info; | |
223 | struct ixgbe_rx_buffer *rx_buffer_info; | |
224 | }; | |
7d637bcc | 225 | unsigned long state; |
bd198058 AD |
226 | u8 __iomem *tail; |
227 | ||
ae540af1 JB |
228 | u16 count; /* amount of descriptors */ |
229 | u16 rx_buf_len; | |
ae540af1 JB |
230 | |
231 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
232 | u8 reg_idx; /* holds the special value that gets |
233 | * the hardware register offset | |
234 | * associated with this ring, which is | |
235 | * different for DCB and RSS modes | |
236 | */ | |
bd198058 AD |
237 | u8 atr_sample_rate; |
238 | u8 atr_count; | |
9a799d71 | 239 | |
bd198058 AD |
240 | u16 next_to_use; |
241 | u16 next_to_clean; | |
9a799d71 | 242 | |
bd198058 | 243 | u8 dcb_tc; |
9a799d71 | 244 | struct ixgbe_queue_stats stats; |
de1036b1 | 245 | struct u64_stats_sync syncp; |
5b7da515 AD |
246 | union { |
247 | struct ixgbe_tx_queue_stats tx_stats; | |
248 | struct ixgbe_rx_queue_stats rx_stats; | |
249 | }; | |
5b7da515 | 250 | int numa_node; |
ae540af1 JB |
251 | unsigned int size; /* length in bytes */ |
252 | dma_addr_t dma; /* phys. address of descriptor ring */ | |
1a51502b | 253 | struct rcu_head rcu; |
33cf09c9 | 254 | struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */ |
7ca3bc58 | 255 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 256 | |
c7e4358a SN |
257 | enum ixgbe_ring_f_enum { |
258 | RING_F_NONE = 0, | |
7f870475 | 259 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 260 | RING_F_RSS, |
c4cf55e5 | 261 | RING_F_FDIR, |
0331a832 YZ |
262 | #ifdef IXGBE_FCOE |
263 | RING_F_FCOE, | |
264 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
265 | |
266 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
267 | }; | |
268 | ||
021230d4 | 269 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 270 | #define IXGBE_MAX_VMDQ_INDICES 64 |
c4cf55e5 | 271 | #define IXGBE_MAX_FDIR_INDICES 64 |
0331a832 YZ |
272 | #ifdef IXGBE_FCOE |
273 | #define IXGBE_MAX_FCOE_INDICES 8 | |
e0fce695 JF |
274 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) |
275 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) | |
276 | #else | |
277 | #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES | |
278 | #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES | |
0331a832 | 279 | #endif /* IXGBE_FCOE */ |
021230d4 AV |
280 | struct ixgbe_ring_feature { |
281 | int indices; | |
282 | int mask; | |
7ca3bc58 | 283 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 284 | |
08c8833b | 285 | struct ixgbe_ring_container { |
efe3d3c8 | 286 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
287 | unsigned int total_bytes; /* total bytes processed this int */ |
288 | unsigned int total_packets; /* total packets processed this int */ | |
289 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
290 | u8 count; /* total number of rings in vector */ |
291 | u8 itr; /* current ITR setting for ring */ | |
292 | }; | |
021230d4 | 293 | |
2f90b865 AD |
294 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
295 | ? 8 : 1) | |
296 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
297 | ||
021230d4 AV |
298 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
299 | * but we only use one per queue-specific vector. | |
300 | */ | |
301 | struct ixgbe_q_vector { | |
302 | struct ixgbe_adapter *adapter; | |
fe49f04a AD |
303 | unsigned int v_idx; /* index of q_vector within array, also used for |
304 | * finding the bit in EICR and friends that | |
305 | * represents the vector for this ring */ | |
33cf09c9 AD |
306 | #ifdef CONFIG_IXGBE_DCA |
307 | int cpu; /* CPU for DCA */ | |
308 | #endif | |
021230d4 | 309 | struct napi_struct napi; |
08c8833b | 310 | struct ixgbe_ring_container rx, tx; |
021230d4 | 311 | u32 eitr; |
b25ebfd2 | 312 | cpumask_var_t affinity_mask; |
d0759ebb | 313 | char name[IFNAMSIZ + 9]; |
021230d4 AV |
314 | }; |
315 | ||
9a799d71 | 316 | /* Helper macros to switch between ints/sec and what the register uses. |
509ee935 JB |
317 | * And yes, it's the same math going both ways. The lowest value |
318 | * supported by all of the ixgbe hardware is 8. | |
9a799d71 AK |
319 | */ |
320 | #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ | |
509ee935 | 321 | ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) |
9a799d71 AK |
322 | #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG |
323 | ||
7d4987de AD |
324 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
325 | { | |
326 | u16 ntc = ring->next_to_clean; | |
327 | u16 ntu = ring->next_to_use; | |
328 | ||
329 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
330 | } | |
9a799d71 AK |
331 | |
332 | #define IXGBE_RX_DESC_ADV(R, i) \ | |
31f05a2d | 333 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
9a799d71 | 334 | #define IXGBE_TX_DESC_ADV(R, i) \ |
31f05a2d | 335 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
9a799d71 | 336 | #define IXGBE_TX_CTXTDESC_ADV(R, i) \ |
31f05a2d | 337 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 AK |
338 | |
339 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 | |
63f39bd1 YZ |
340 | #ifdef IXGBE_FCOE |
341 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
342 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
343 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 344 | |
021230d4 AV |
345 | #define OTHER_VECTOR 1 |
346 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
347 | ||
e8e26350 PW |
348 | #define MAX_MSIX_VECTORS_82599 64 |
349 | #define MAX_MSIX_Q_VECTORS_82599 64 | |
eb7f139c PWJ |
350 | #define MAX_MSIX_VECTORS_82598 18 |
351 | #define MAX_MSIX_Q_VECTORS_82598 16 | |
352 | ||
e8e26350 PW |
353 | #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599 |
354 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 | |
eb7f139c | 355 | |
021230d4 | 356 | #define MIN_MSIX_Q_VECTORS 2 |
021230d4 AV |
357 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
358 | ||
9a799d71 AK |
359 | /* board specific private data structure */ |
360 | struct ixgbe_adapter { | |
e606bfe7 AD |
361 | unsigned long state; |
362 | ||
363 | /* Some features need tri-state capability, | |
364 | * thus the additional *_CAPABLE flags. | |
365 | */ | |
366 | u32 flags; | |
367 | #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1) | |
368 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) | |
369 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) | |
370 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) | |
371 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) | |
372 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) | |
373 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) | |
374 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) | |
375 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) | |
376 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) | |
377 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) | |
378 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) | |
379 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) | |
380 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) | |
381 | #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) | |
382 | #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) | |
383 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) | |
384 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) | |
385 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) | |
386 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) | |
7086400d AD |
387 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23) |
388 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24) | |
389 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25) | |
390 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26) | |
391 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27) | |
392 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28) | |
393 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29) | |
e606bfe7 AD |
394 | |
395 | u32 flags2; | |
396 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) | |
397 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) | |
398 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 399 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
400 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
401 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 402 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 403 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
e606bfe7 | 404 | |
f62bbb5e | 405 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
9a799d71 | 406 | u16 bd_number; |
7a921c93 | 407 | struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; |
d033d526 JF |
408 | |
409 | /* DCB parameters */ | |
410 | struct ieee_pfc *ixgbe_ieee_pfc; | |
411 | struct ieee_ets *ixgbe_ieee_ets; | |
2f90b865 AD |
412 | struct ixgbe_dcb_config dcb_cfg; |
413 | struct ixgbe_dcb_config temp_dcb_cfg; | |
414 | u8 dcb_set_bitmap; | |
3032309b | 415 | u8 dcbx_cap; |
264857b8 | 416 | enum ixgbe_fc_mode last_lfc_mode; |
9a799d71 | 417 | |
f494e8fa | 418 | /* Interrupt Throttle Rate */ |
f7554a2b NS |
419 | u32 rx_itr_setting; |
420 | u32 tx_itr_setting; | |
f494e8fa AV |
421 | u16 eitr_low; |
422 | u16 eitr_high; | |
423 | ||
bd198058 AD |
424 | /* Work limits */ |
425 | u16 tx_work_limit; | |
426 | ||
9a799d71 | 427 | /* TX */ |
4a0b9ca0 | 428 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
30efa5a3 | 429 | int num_tx_queues; |
9a799d71 AK |
430 | u32 tx_timeout_count; |
431 | bool detect_tx_hung; | |
432 | ||
7ca3bc58 JB |
433 | u64 restart_queue; |
434 | u64 lsc_int; | |
435 | ||
9a799d71 | 436 | /* RX */ |
4a0b9ca0 | 437 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp; |
30efa5a3 | 438 | int num_rx_queues; |
7f870475 GR |
439 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
440 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 441 | u64 hw_csum_rx_error; |
e8e26350 | 442 | u64 hw_rx_no_dma_resources; |
9a799d71 | 443 | u64 non_eop_descs; |
021230d4 | 444 | int num_msix_vectors; |
eb7f139c | 445 | int max_msix_q_vectors; /* true count of q_vectors for device */ |
c7e4358a | 446 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
9a799d71 AK |
447 | struct msix_entry *msix_entries; |
448 | ||
9a799d71 AK |
449 | u32 alloc_rx_page_failed; |
450 | u32 alloc_rx_buff_failed; | |
451 | ||
96b0e0f6 JB |
452 | /* default to trying for four seconds */ |
453 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
9a799d71 AK |
454 | |
455 | /* OS defined structs */ | |
456 | struct net_device *netdev; | |
457 | struct pci_dev *pdev; | |
9a799d71 | 458 | |
da4dd0f7 PWJ |
459 | u32 test_icr; |
460 | struct ixgbe_ring test_tx_ring; | |
461 | struct ixgbe_ring test_rx_ring; | |
462 | ||
9a799d71 AK |
463 | /* structs defined in ixgbe_hw.h */ |
464 | struct ixgbe_hw hw; | |
465 | u16 msg_enable; | |
466 | struct ixgbe_hw_stats stats; | |
021230d4 AV |
467 | |
468 | /* Interrupt Throttle Rate */ | |
f7554a2b NS |
469 | u32 rx_eitr_param; |
470 | u32 tx_eitr_param; | |
9a799d71 | 471 | |
9a799d71 | 472 | u64 tx_busy; |
30efa5a3 JB |
473 | unsigned int tx_ring_count; |
474 | unsigned int rx_ring_count; | |
cf8280ee JB |
475 | |
476 | u32 link_speed; | |
477 | bool link_up; | |
478 | unsigned long link_check_timeout; | |
479 | ||
7086400d | 480 | struct work_struct service_task; |
7086400d | 481 | struct timer_list service_timer; |
c4cf55e5 PWJ |
482 | u32 fdir_pballoc; |
483 | u32 atr_sample_rate; | |
d034acf1 | 484 | unsigned long fdir_overflow; /* number of times ATR was backed off */ |
c4cf55e5 | 485 | spinlock_t fdir_perfect_lock; |
d0ed8937 YZ |
486 | #ifdef IXGBE_FCOE |
487 | struct ixgbe_fcoe fcoe; | |
488 | #endif /* IXGBE_FCOE */ | |
94b982b2 MC |
489 | u64 rsc_total_count; |
490 | u64 rsc_total_flush; | |
e8e26350 | 491 | u32 wol; |
34b0368c | 492 | u16 eeprom_version; |
7f870475 | 493 | |
1a6c14a2 | 494 | int node; |
66e6961c | 495 | u32 led_reg; |
119fc60a | 496 | u32 interrupt_event; |
1a6c14a2 | 497 | |
7f870475 GR |
498 | /* SR-IOV */ |
499 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
500 | unsigned int num_vfs; | |
501 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 502 | int vf_rate_link_speed; |
a1cbb15c GR |
503 | struct vf_macvlans vf_mvs; |
504 | struct vf_macvlans *mv_list; | |
505 | bool antispoofing_enabled; | |
3e05334f AD |
506 | |
507 | struct hlist_head fdir_filter_list; | |
508 | union ixgbe_atr_input fdir_mask; | |
509 | int fdir_filter_count; | |
510 | }; | |
511 | ||
512 | struct ixgbe_fdir_filter { | |
513 | struct hlist_node fdir_node; | |
514 | union ixgbe_atr_input filter; | |
515 | u16 sw_idx; | |
516 | u16 action; | |
9a799d71 AK |
517 | }; |
518 | ||
519 | enum ixbge_state_t { | |
520 | __IXGBE_TESTING, | |
521 | __IXGBE_RESETTING, | |
c4900be0 | 522 | __IXGBE_DOWN, |
7086400d AD |
523 | __IXGBE_SERVICE_SCHED, |
524 | __IXGBE_IN_SFP_INIT, | |
9a799d71 AK |
525 | }; |
526 | ||
aa80175a AD |
527 | struct ixgbe_rsc_cb { |
528 | dma_addr_t dma; | |
529 | u16 skb_cnt; | |
530 | bool delay_unmap; | |
531 | }; | |
532 | #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) | |
533 | ||
9a799d71 | 534 | enum ixgbe_boards { |
3957d63d | 535 | board_82598, |
e8e26350 | 536 | board_82599, |
fe15e8e1 | 537 | board_X540, |
9a799d71 AK |
538 | }; |
539 | ||
3957d63d | 540 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 541 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 542 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 543 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 544 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 AD |
545 | extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, |
546 | struct ixgbe_dcb_config *dst_dcb_cfg, | |
547 | int tc_max); | |
548 | #endif | |
9a799d71 AK |
549 | |
550 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 551 | extern const char ixgbe_driver_version[]; |
9a799d71 | 552 | |
c7ccde0f | 553 | extern void ixgbe_up(struct ixgbe_adapter *adapter); |
9a799d71 | 554 | extern void ixgbe_down(struct ixgbe_adapter *adapter); |
d4f80882 | 555 | extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); |
9a799d71 | 556 | extern void ixgbe_reset(struct ixgbe_adapter *adapter); |
9a799d71 | 557 | extern void ixgbe_set_ethtool_ops(struct net_device *netdev); |
b6ec895e AD |
558 | extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); |
559 | extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
560 | extern void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
561 | extern void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
84418e3b AD |
562 | extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); |
563 | extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); | |
2d39d576 YZ |
564 | extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
565 | struct ixgbe_ring *); | |
b4617240 | 566 | extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); |
2f90b865 | 567 | extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); |
7a921c93 | 568 | extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
84418e3b | 569 | extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, |
84418e3b AD |
570 | struct ixgbe_adapter *, |
571 | struct ixgbe_ring *); | |
b6ec895e | 572 | extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, |
84418e3b | 573 | struct ixgbe_tx_buffer *); |
fc77dc3c | 574 | extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); |
fe49f04a AD |
575 | extern void ixgbe_write_eitr(struct ixgbe_q_vector *); |
576 | extern int ethtool_ioctl(struct ifreq *ifr); | |
ffff4772 | 577 | extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); |
c04f6ca8 AD |
578 | extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); |
579 | extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
ffff4772 | 580 | extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, |
69830529 AD |
581 | union ixgbe_atr_hash_dword input, |
582 | union ixgbe_atr_hash_dword common, | |
ffff4772 | 583 | u8 queue); |
c04f6ca8 AD |
584 | extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, |
585 | union ixgbe_atr_input *input_mask); | |
586 | extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
587 | union ixgbe_atr_input *input, | |
588 | u16 soft_id, u8 queue); | |
589 | extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
590 | union ixgbe_atr_input *input, | |
591 | u16 soft_id); | |
592 | extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
593 | union ixgbe_atr_input *mask); | |
7f870475 | 594 | extern void ixgbe_set_rx_mode(struct net_device *netdev); |
e5b64635 | 595 | extern int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
897ab156 | 596 | extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); |
082757af | 597 | extern void ixgbe_do_reset(struct net_device *netdev); |
eacd73f7 YZ |
598 | #ifdef IXGBE_FCOE |
599 | extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); | |
897ab156 | 600 | extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
eacd73f7 | 601 | u32 tx_flags, u8 *hdr_len); |
332d4a7d YZ |
602 | extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); |
603 | extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
ff886dfc AD |
604 | union ixgbe_adv_rx_desc *rx_desc, |
605 | struct sk_buff *skb, | |
606 | u32 staterr); | |
332d4a7d YZ |
607 | extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, |
608 | struct scatterlist *sgl, unsigned int sgc); | |
68a683cf YZ |
609 | extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, |
610 | struct scatterlist *sgl, unsigned int sgc); | |
332d4a7d | 611 | extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); |
8450ff8c YZ |
612 | extern int ixgbe_fcoe_enable(struct net_device *netdev); |
613 | extern int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 YZ |
614 | #ifdef CONFIG_IXGBE_DCB |
615 | extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); | |
616 | extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
617 | #endif /* CONFIG_IXGBE_DCB */ | |
61a1fa10 | 618 | extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
eacd73f7 | 619 | #endif /* IXGBE_FCOE */ |
9a799d71 AK |
620 | |
621 | #endif /* _IXGBE_H_ */ |