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ixgbe: cleanup checksum to allow error results
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
14438464 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_COMMON_H_
30#define _IXGBE_COMMON_H_
31
32#include "ixgbe_type.h"
32f75466 33#include "ixgbe.h"
9a799d71 34
71161302 35u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
c44ade9e
JB		 36s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
37s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
38s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
7184b7cf 39s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
c44ade9e 40s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
289700db 41s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 42 u32 pba_num_size);
c44ade9e 43s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
ef1889d5
JK		 44enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status);
45enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status);
c44ade9e 46s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
11afc1b1 47void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
c44ade9e
JB		 48s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
49
50s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
51s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
52
53s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
11afc1b1 54s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
68c7005d
ET		 55s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
21ce849b 57s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
68c7005d
ET		 58s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
eb9c3e3e 60s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
68c7005d
ET		 61s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
62 u16 words, u16 *data);
c44ade9e 63s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
e7cf745b 64 u16 *data);
68c7005d
ET		 65s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
66 u16 words, u16 *data);
735c35af 67s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
c44ade9e 68s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 69 u16 *checksum_val);
c44ade9e
JB		 70s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
71
72s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 73 u32 enable_addr);
c44ade9e
JB		 74s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
75s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
2853eb89
JP		 76s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
77 struct net_device *netdev);
c44ade9e
JB		 78s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
79s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
d2f5e7f3
AS		 80s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);
81s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);
11afc1b1 82s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
041441d0 83s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
73d80953 84bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
786e9a5f 85void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
9a799d71 86
030eaece
DS		 87s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);
88void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);
21ce849b
MC		 89s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
90s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
7fa7c9dc 91s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
21ce849b
MC		 92s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
93s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
94s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
e7cf745b 95 u32 vind, bool vlan_on);
21ce849b
MC		 96s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
97s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
e7cf745b
JK		 98 ixgbe_link_speed *speed,
99 bool *link_up, bool link_up_wait_to_complete);
a391f1d5 100s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 101 u16 *wwpn_prefix);
429d6a3b
DS		 102
103s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
104s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
105
87c12017
PW		 106s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
107s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
a985b6c3
GR		 108void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
109void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
b776d104 110s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
9612de92
ET		 111s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
112 u8 build, u8 ver);
ff9d1a5a 113void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
7155d051 114bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
87c12017 115
80605c65
JF		 116void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
117 u32 headroom, int strategy);
118
e1ea9158
DS		 119#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
120#define IXGBE_EMC_INTERNAL_DATA 0x00
121#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
122#define IXGBE_EMC_DIODE1_DATA 0x01
123#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
124#define IXGBE_EMC_DIODE2_DATA 0x23
125#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
126#define IXGBE_EMC_DIODE3_DATA 0x2A
127#define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30
128
129s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
130s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
131
2a1a091c 132#define IXGBE_FAILED_READ_REG 0xffffffffU
14438464
MR		 133#define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU
134#define IXGBE_FAILED_READ_CFG_WORD 0xffffU
135
136u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
ed19231c 137void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
2a1a091c
MR		 138
139static inline bool ixgbe_removed(void __iomem *addr)
140{
141 return unlikely(!addr);
142}
143
84227bcd
MR		 144static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value)
145{
b12babd4
MR		 146 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
147
148 if (ixgbe_removed(reg_addr))
149 return;
150 writel(value, reg_addr + reg);
84227bcd
MR		 151}
152#define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value))
9a799d71 153
11afc1b1 154#ifndef writeq
84227bcd
MR		 155#define writeq writeq
156static inline void writeq(u64 val, void __iomem *addr)
157{
158 writel((u32)val, addr);
159 writel((u32)(val >> 32), addr + 4);
160}
11afc1b1
PW		 161#endif
162
84227bcd
MR		 163static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value)
164{
b12babd4
MR		 165 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
166
167 if (ixgbe_removed(reg_addr))
168 return;
169 writeq(value, reg_addr + reg);
84227bcd
MR		 170}
171#define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value))
11afc1b1 172
f8e2472f 173u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg);
84227bcd 174#define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg))
9a799d71 175
84227bcd
MR		 176#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \
177 ixgbe_write_reg((a), (reg) + ((offset) << 2), (value))
9a799d71 178
84227bcd
MR		 179#define IXGBE_READ_REG_ARRAY(a, reg, offset) \
180 ixgbe_read_reg((a), (reg) + ((offset) << 2))
9a799d71 181
84227bcd 182#define IXGBE_WRITE_FLUSH(a) ixgbe_read_reg((a), IXGBE_STATUS)
9a799d71 183
be0c27b4
MR		 184#define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev)
185
9a799d71 186#define hw_dbg(hw, format, arg...) \
be0c27b4
MR		 187 netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg)
188#define hw_err(hw, format, arg...) \
189 netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg)
849c4542
ET		 190#define e_dev_info(format, arg...) \
191 dev_info(&adapter->pdev->dev, format, ## arg)
192#define e_dev_warn(format, arg...) \
193 dev_warn(&adapter->pdev->dev, format, ## arg)
194#define e_dev_err(format, arg...) \
195 dev_err(&adapter->pdev->dev, format, ## arg)
196#define e_dev_notice(format, arg...) \
197 dev_notice(&adapter->pdev->dev, format, ## arg)
396e799c
ET		 198#define e_info(msglvl, format, arg...) \
199 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
200#define e_err(msglvl, format, arg...) \
201 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
202#define e_warn(msglvl, format, arg...) \
203 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
204#define e_crit(msglvl, format, arg...) \
205 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
9a799d71 206#endif /* IXGBE_COMMON */
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