[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_dcb.h

/* SPDX-License-Identifier: GPL-2.0 */
/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2013 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _DCB_CONFIG_H_
#define _DCB_CONFIG_H_

#include <linux/dcbnl.h>
#include "ixgbe_type.h"

/* DCB data structures */

#define IXGBE_MAX_PACKET_BUFFERS 8
#define MAX_USER_PRIORITY        8
#define MAX_BW_GROUP             8
#define BW_PERCENT               100

#define DCB_TX_CONFIG            0
#define DCB_RX_CONFIG            1

/* DCB error Codes */
#define DCB_SUCCESS              0
#define DCB_ERR_CONFIG           -1
#define DCB_ERR_PARAM            -2

/* Transmit and receive Errors */
/* Error in bandwidth group allocation */
#define DCB_ERR_BW_GROUP        -3
/* Error in traffic class bandwidth allocation */
#define DCB_ERR_TC_BW           -4
/* Traffic class has both link strict and group strict enabled */
#define DCB_ERR_LS_GS           -5
/* Link strict traffic class has non zero bandwidth */
#define DCB_ERR_LS_BW_NONZERO   -6
/* Link strict bandwidth group has non zero bandwidth */
#define DCB_ERR_LS_BWG_NONZERO  -7
/*  Traffic class has zero bandwidth */
#define DCB_ERR_TC_BW_ZERO      -8

#define DCB_NOT_IMPLEMENTED      0x7FFFFFFF

struct dcb_pfc_tc_debug {
	u8  tc;
	u8  pause_status;
	u64 pause_quanta;
};

enum strict_prio_type {
	prio_none = 0,
	prio_group,
	prio_link
};

/* DCB capability definitions */
#define IXGBE_DCB_PG_SUPPORT        0x00000001
#define IXGBE_DCB_PFC_SUPPORT       0x00000002
#define IXGBE_DCB_BCN_SUPPORT       0x00000004
#define IXGBE_DCB_UP2TC_SUPPORT     0x00000008
#define IXGBE_DCB_GSP_SUPPORT       0x00000010

#define IXGBE_DCB_8_TC_SUPPORT      0x80

struct dcb_support {
	/* DCB capabilities */
	u32 capabilities;

	/* Each bit represents a number of TCs configurable in the hw.
	 * If 8 traffic classes can be configured, the value is 0x80.
	 */
	u8  traffic_classes;
	u8  pfc_traffic_classes;
};

/* Traffic class bandwidth allocation per direction */
struct tc_bw_alloc {
	u8 bwg_id;		  /* Bandwidth Group (BWG) ID */
	u8 bwg_percent;		  /* % of BWG's bandwidth */
	u8 link_percent;	  /* % of link bandwidth */
	u8 up_to_tc_bitmap;	  /* User Priority to Traffic Class mapping */
	u16 data_credits_refill;  /* Credit refill amount in 64B granularity */
	u16 data_credits_max;	  /* Max credits for a configured packet buffer
				   * in 64B granularity.*/
	enum strict_prio_type prio_type; /* Link or Group Strict Priority */
};

enum dcb_pfc_type {
	pfc_disabled = 0,
	pfc_enabled_full,
	pfc_enabled_tx,
	pfc_enabled_rx
};

/* Traffic class configuration */
struct tc_configuration {
	struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
	enum dcb_pfc_type  dcb_pfc; /* Class based flow control setting */

	u16 desc_credits_max; /* For Tx Descriptor arbitration */
	u8 tc; /* Traffic class (TC) */
};

struct dcb_num_tcs {
	u8 pg_tcs;
	u8 pfc_tcs;
};

struct ixgbe_dcb_config {
	struct dcb_support support;
	struct dcb_num_tcs num_tcs;
	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
	u8     bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
	bool   pfc_mode_enable;

	u32  dcb_cfg_version; /* Not used...OS-specific? */
	u32  link_speed; /* For bandwidth allocation validation purpose */
};

/* DCB driver APIs */
void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en);
void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *);
void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *);
void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *);
void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *);
void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *, int, u8 *);
u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);

/* DCB credits calculation */
s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
				   struct ixgbe_dcb_config *, int, u8);

/* DCB hw initialization */
s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max);
s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
			    u8 *bwg_id, u8 *prio_type, u8 *tc_prio);
s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *tc_prio);
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);

void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map);

/* DCB definitions for credit calculation */
#define DCB_CREDIT_QUANTUM	64   /* DCB Quantum */
#define MAX_CREDIT_REFILL       511  /* 0x1FF * 64B = 32704B */
#define DCB_MAX_TSO_SIZE        (32*1024) /* MAX TSO packet size supported in DCB mode */
#define MINIMUM_CREDIT_FOR_TSO  (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
#define MAX_CREDIT              4095 /* Maximum credit supported: 256KB * 1204 / 64B */

#endif /* _DCB_CONFIG_H */
Commit	Line	Data
ae06c70b	1	/* SPDX-License-Identifier: GPL-2.0 */
2f90b865 AD	2	/*******************************************************************************
	3
	4	Intel 10 Gigabit PCI Express Linux driver
434c5e39	5	Copyright(c) 1999 - 2013 Intel Corporation.
2f90b865 AD	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc.,
	18	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19
	20	The full GNU General Public License is included in this distribution in
	21	the file called "COPYING".
	22
	23	Contact Information:
	24	Linux NICS <linux.nics@intel.com>
	25	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	26	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27
	28	*******************************************************************************/
	29
	30	#ifndef _DCB_CONFIG_H_
	31	#define _DCB_CONFIG_H_
	32
4c09f3a0	33	#include <linux/dcbnl.h>
2f90b865 AD	34	#include "ixgbe_type.h"
	35
	36	/* DCB data structures */
	37
	38	#define IXGBE_MAX_PACKET_BUFFERS 8
	39	#define MAX_USER_PRIORITY 8
2f90b865 AD	40	#define MAX_BW_GROUP 8
	41	#define BW_PERCENT 100
	42
	43	#define DCB_TX_CONFIG 0
	44	#define DCB_RX_CONFIG 1
	45
	46	/* DCB error Codes */
	47	#define DCB_SUCCESS 0
	48	#define DCB_ERR_CONFIG -1
	49	#define DCB_ERR_PARAM -2
	50
	51	/* Transmit and receive Errors */
	52	/* Error in bandwidth group allocation */
	53	#define DCB_ERR_BW_GROUP -3
	54	/* Error in traffic class bandwidth allocation */
	55	#define DCB_ERR_TC_BW -4
	56	/* Traffic class has both link strict and group strict enabled */
	57	#define DCB_ERR_LS_GS -5
	58	/* Link strict traffic class has non zero bandwidth */
	59	#define DCB_ERR_LS_BW_NONZERO -6
	60	/* Link strict bandwidth group has non zero bandwidth */
	61	#define DCB_ERR_LS_BWG_NONZERO -7
	62	/* Traffic class has zero bandwidth */
	63	#define DCB_ERR_TC_BW_ZERO -8
	64
	65	#define DCB_NOT_IMPLEMENTED 0x7FFFFFFF
	66
	67	struct dcb_pfc_tc_debug {
	68	u8 tc;
	69	u8 pause_status;
	70	u64 pause_quanta;
	71	};
	72
	73	enum strict_prio_type {
	74	prio_none = 0,
	75	prio_group,
	76	prio_link
	77	};
	78
235ea828 PW	79	/* DCB capability definitions */
	80	#define IXGBE_DCB_PG_SUPPORT 0x00000001
	81	#define IXGBE_DCB_PFC_SUPPORT 0x00000002
	82	#define IXGBE_DCB_BCN_SUPPORT 0x00000004
	83	#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
	84	#define IXGBE_DCB_GSP_SUPPORT 0x00000010
	85
	86	#define IXGBE_DCB_8_TC_SUPPORT 0x80
	87
	88	struct dcb_support {
	89	/* DCB capabilities */
	90	u32 capabilities;
	91
	92	/* Each bit represents a number of TCs configurable in the hw.
	93	* If 8 traffic classes can be configured, the value is 0x80.
	94	*/
	95	u8 traffic_classes;
	96	u8 pfc_traffic_classes;
	97	};
	98
2f90b865 AD	99	/* Traffic class bandwidth allocation per direction */
	100	struct tc_bw_alloc {
	101	u8 bwg_id; /* Bandwidth Group (BWG) ID */
	102	u8 bwg_percent; /* % of BWG's bandwidth */
	103	u8 link_percent; /* % of link bandwidth */
	104	u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
	105	u16 data_credits_refill; /* Credit refill amount in 64B granularity */
	106	u16 data_credits_max; /* Max credits for a configured packet buffer
	107	* in 64B granularity.*/
	108	enum strict_prio_type prio_type; /* Link or Group Strict Priority */
	109	};
	110
	111	enum dcb_pfc_type {
	112	pfc_disabled = 0,
	113	pfc_enabled_full,
	114	pfc_enabled_tx,
	115	pfc_enabled_rx
	116	};
	117
	118	/* Traffic class configuration */
	119	struct tc_configuration {
	120	struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
	121	enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */
	122
	123	u16 desc_credits_max; /* For Tx Descriptor arbitration */
	124	u8 tc; /* Traffic class (TC) */
	125	};
	126
235ea828 PW	127	struct dcb_num_tcs {
	128	u8 pg_tcs;
	129	u8 pfc_tcs;
859ee3c4 AD	130	};
859ee3c4 AD	131
2f90b865	132	struct ixgbe_dcb_config {
235ea828 PW	133	struct dcb_support support;
235ea828 PW	134	struct dcb_num_tcs num_tcs;
2f90b865 AD	135	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
2f90b865 AD	136	u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
235ea828	137	bool pfc_mode_enable;
2f90b865	138
2f90b865 AD	139	u32 dcb_cfg_version; /* Not used...OS-specific? */
	140	u32 link_speed; /* For bandwidth allocation validation purpose */
	141	};
	142
	143	/* DCB driver APIs */
55320cb5	144	void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config cfg, u8 pfc_en);
d43f5c21 JF	145	void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config , int, u16 );
	146	void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config , u16 );
	147	void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config , int, u8 );
	148	void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config , int, u8 );
32701dc2	149	void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config , int, u8 );
02debdc9	150	u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
2f90b865	151
2f90b865	152	/* DCB credits calculation */
80ab193d JF	153	s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
80ab193d JF	154	struct ixgbe_dcb_config *, int, u8);
2f90b865	155
2f90b865	156	/* DCB hw initialization */
4c09f3a0	157	s32 ixgbe_dcb_hw_ets(struct ixgbe_hw hw, struct ieee_ets ets, int max);
17049d30 JF	158	s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw hw, u16 refill, u16 *max,
17049d30 JF	159	u8 bwg_id, u8 prio_type, u8 *tc_prio);
32701dc2	160	s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw hw, u8 pfc_en, u8 tc_prio);
2f90b865 AD	161	s32 ixgbe_dcb_hw_config(struct ixgbe_hw , struct ixgbe_dcb_config );
2f90b865 AD	162
e8915beb AH	163	void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw hw, u8 map);
e8915beb AH	164
2f90b865	165	/* DCB definitions for credit calculation */
9806307a	166	#define DCB_CREDIT_QUANTUM 64 /* DCB Quantum */
2f90b865	167	#define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */
2f90b865 AD	168	#define DCB_MAX_TSO_SIZE (321024) / MAX TSO packet size supported in DCB mode */
	169	#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
	170	#define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */
	171
	172	#endif /* _DCB_CONFIG_H */