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ixgbe: fix gso type
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
14a8d4bb 66#define DRV_VERSION "3.11.33-k"
9c8eb720 67const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 68static const char ixgbe_copyright[] =
94971820 69 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 70
71static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 72 [board_82598] = &ixgbe_82598_info,
e8e26350 73 [board_82599] = &ixgbe_82599_info,
fe15e8e1 74 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 75};
76
77/* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 115 /* required last entry */
116 {0, }
117};
118MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
5dd2d332 120#ifdef CONFIG_IXGBE_DCA
bd0362dd 121static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 122 void *p);
bd0362dd
JC		 123static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127};
128#endif
129
1cdd1ec8
GR		 130#ifdef CONFIG_PCI_IOV
131static unsigned int max_vfs;
132module_param(max_vfs, uint, 0);
e8e9f696 133MODULE_PARM_DESC(max_vfs,
6b42a9c5 134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 135#endif /* CONFIG_PCI_IOV */
136
8ef78adc
PWJ		 137static unsigned int allow_unsupported_sfp;
138module_param(allow_unsupported_sfp, uint, 0);
139MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
b3f4d599 142#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143static int debug = -1;
144module_param(debug, int, 0);
145MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
9a799d71
AK		 147MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
7086400d
AD		 152static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
153{
154 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
155 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
156 schedule_work(&adapter->service_task);
157}
158
159static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
160{
161 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
162
52f33af8 163 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 164 smp_mb__before_clear_bit();
165 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
166}
167
dcd79aeb
TI		 168struct ixgbe_reg_info {
169 u32 ofs;
170 char *name;
171};
172
173static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
174
175 /* General Registers */
176 {IXGBE_CTRL, "CTRL"},
177 {IXGBE_STATUS, "STATUS"},
178 {IXGBE_CTRL_EXT, "CTRL_EXT"},
179
180 /* Interrupt Registers */
181 {IXGBE_EICR, "EICR"},
182
183 /* RX Registers */
184 {IXGBE_SRRCTL(0), "SRRCTL"},
185 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
186 {IXGBE_RDLEN(0), "RDLEN"},
187 {IXGBE_RDH(0), "RDH"},
188 {IXGBE_RDT(0), "RDT"},
189 {IXGBE_RXDCTL(0), "RXDCTL"},
190 {IXGBE_RDBAL(0), "RDBAL"},
191 {IXGBE_RDBAH(0), "RDBAH"},
192
193 /* TX Registers */
194 {IXGBE_TDBAL(0), "TDBAL"},
195 {IXGBE_TDBAH(0), "TDBAH"},
196 {IXGBE_TDLEN(0), "TDLEN"},
197 {IXGBE_TDH(0), "TDH"},
198 {IXGBE_TDT(0), "TDT"},
199 {IXGBE_TXDCTL(0), "TXDCTL"},
200
201 /* List Terminator */
202 {}
203};
204
205
206/*
207 * ixgbe_regdump - register printout routine
208 */
209static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
210{
211 int i = 0, j = 0;
212 char rname[16];
213 u32 regs[64];
214
215 switch (reginfo->ofs) {
216 case IXGBE_SRRCTL(0):
217 for (i = 0; i < 64; i++)
218 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
219 break;
220 case IXGBE_DCA_RXCTRL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
223 break;
224 case IXGBE_RDLEN(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
227 break;
228 case IXGBE_RDH(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
231 break;
232 case IXGBE_RDT(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
235 break;
236 case IXGBE_RXDCTL(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
239 break;
240 case IXGBE_RDBAL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
243 break;
244 case IXGBE_RDBAH(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
247 break;
248 case IXGBE_TDBAL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
251 break;
252 case IXGBE_TDBAH(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
255 break;
256 case IXGBE_TDLEN(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
259 break;
260 case IXGBE_TDH(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
263 break;
264 case IXGBE_TDT(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
267 break;
268 case IXGBE_TXDCTL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
271 break;
272 default:
c7689578 273 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 274 IXGBE_READ_REG(hw, reginfo->ofs));
275 return;
276 }
277
278 for (i = 0; i < 8; i++) {
279 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 280 pr_err("%-15s", rname);
dcd79aeb 281 for (j = 0; j < 8; j++)
c7689578
JP		 282 pr_cont(" %08x", regs[i*8+j]);
283 pr_cont("\n");
dcd79aeb
TI		 284 }
285
286}
287
288/*
289 * ixgbe_dump - Print registers, tx-rings and rx-rings
290 */
291static void ixgbe_dump(struct ixgbe_adapter *adapter)
292{
293 struct net_device *netdev = adapter->netdev;
294 struct ixgbe_hw *hw = &adapter->hw;
295 struct ixgbe_reg_info *reginfo;
296 int n = 0;
297 struct ixgbe_ring *tx_ring;
729739b7 298 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 299 union ixgbe_adv_tx_desc *tx_desc;
300 struct my_u0 { u64 a; u64 b; } *u0;
301 struct ixgbe_ring *rx_ring;
302 union ixgbe_adv_rx_desc *rx_desc;
303 struct ixgbe_rx_buffer *rx_buffer_info;
304 u32 staterr;
305 int i = 0;
306
307 if (!netif_msg_hw(adapter))
308 return;
309
310 /* Print netdevice Info */
311 if (netdev) {
312 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 313 pr_info("Device Name state "
dcd79aeb 314 "trans_start last_rx\n");
c7689578
JP		 315 pr_info("%-15s %016lX %016lX %016lX\n",
316 netdev->name,
317 netdev->state,
318 netdev->trans_start,
319 netdev->last_rx);
dcd79aeb
TI		 320 }
321
322 /* Print Registers */
323 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 324 pr_info(" Register Name Value\n");
dcd79aeb
TI		 325 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
326 reginfo->name; reginfo++) {
327 ixgbe_regdump(hw, reginfo);
328 }
329
330 /* Print TX Ring Summary */
331 if (!netdev || !netif_running(netdev))
332 goto exit;
333
334 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 335 pr_info(" %s %s %s %s\n",
336 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
337 "leng", "ntw", "timestamp");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 341 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
39ac868a 357 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
39ac868a 361 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 364 *
365 * 82598 Advanced Transmit Descriptor (Write-Back Format)
366 * +--------------------------------------------------------------+
367 * 0 | RSV [63:0] |
368 * +--------------------------------------------------------------+
369 * 8 | RSV | STA | NXTSEQ |
370 * +--------------------------------------------------------------+
371 * 63 36 35 32 31 0
372 *
373 * 82599+ Advanced Transmit Descriptor
374 * +--------------------------------------------------------------+
375 * 0 | Buffer Address [63:0] |
376 * +--------------------------------------------------------------+
377 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
378 * +--------------------------------------------------------------+
379 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
380 *
381 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
382 * +--------------------------------------------------------------+
383 * 0 | RSV [63:0] |
384 * +--------------------------------------------------------------+
385 * 8 | RSV | STA | RSV |
386 * +--------------------------------------------------------------+
387 * 63 36 35 32 31 0
dcd79aeb
TI		 388 */
389
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 tx_ring = adapter->tx_ring[n];
c7689578
JP		 392 pr_info("------------------------------------\n");
393 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
394 pr_info("------------------------------------\n");
8ad88e37
JH		 395 pr_info("%s%s %s %s %s %s\n",
396 "T [desc] [address 63:0 ] ",
397 "[PlPOIdStDDt Ln] [bi->dma ] ",
398 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 399
400 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 401 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 402 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 403 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 404 if (dma_unmap_len(tx_buffer, len) > 0) {
405 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
406 i,
407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
409 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 410 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
416 pr_cont(" NTC/U\n");
417 else if (i == tx_ring->next_to_use)
418 pr_cont(" NTU\n");
419 else if (i == tx_ring->next_to_clean)
420 pr_cont(" NTC\n");
421 else
422 pr_cont("\n");
423
424 if (netif_msg_pktdata(adapter) &&
425 tx_buffer->skb)
426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
428 tx_buffer->skb->data,
429 dma_unmap_len(tx_buffer, len),
430 true);
431 }
dcd79aeb
TI		 432 }
433 }
434
435 /* Print RX Rings Summary */
436rx_ring_summary:
437 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 438 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 439 for (n = 0; n < adapter->num_rx_queues; n++) {
440 rx_ring = adapter->rx_ring[n];
c7689578
JP		 441 pr_info("%5d %5X %5X\n",
442 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 443 }
444
445 /* Print RX Rings */
446 if (!netif_msg_rx_status(adapter))
447 goto exit;
448
449 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
450
39ac868a
JH		 451 /* Receive Descriptor Formats
452 *
453 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 454 * 63 1 0
455 * +-----------------------------------------------------+
456 * 0 | Packet Buffer Address [63:1] |A0/NSE|
457 * +----------------------------------------------+------+
458 * 8 | Header Buffer Address [63:1] | DD |
459 * +-----------------------------------------------------+
460 *
461 *
39ac868a 462 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 463 *
464 * 63 48 47 32 31 30 21 20 16 15 4 3 0
465 * +------------------------------------------------------+
39ac868a
JH		 466 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
467 * | Packet | IP | | | | Type | Type |
468 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 469 * +------------------------------------------------------+
470 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
471 * +------------------------------------------------------+
472 * 63 48 47 32 31 20 19 0
39ac868a
JH		 473 *
474 * 82599+ Advanced Receive Descriptor (Read) Format
475 * 63 1 0
476 * +-----------------------------------------------------+
477 * 0 | Packet Buffer Address [63:1] |A0/NSE|
478 * +----------------------------------------------+------+
479 * 8 | Header Buffer Address [63:1] | DD |
480 * +-----------------------------------------------------+
481 *
482 *
483 * 82599+ Advanced Receive Descriptor (Write-Back) Format
484 *
485 * 63 48 47 32 31 30 21 20 17 16 4 3 0
486 * +------------------------------------------------------+
487 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
488 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
489 * |/ Flow Dir Flt ID | | | | | |
490 * +------------------------------------------------------+
491 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
492 * +------------------------------------------------------+
493 * 63 48 47 32 31 20 19 0
dcd79aeb 494 */
39ac868a 495
dcd79aeb
TI		 496 for (n = 0; n < adapter->num_rx_queues; n++) {
497 rx_ring = adapter->rx_ring[n];
c7689578
JP		 498 pr_info("------------------------------------\n");
499 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
500 pr_info("------------------------------------\n");
8ad88e37
JH		 501 pr_info("%s%s%s",
502 "R [desc] [ PktBuf A0] ",
503 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 504 "<-- Adv Rx Read format\n");
8ad88e37
JH		 505 pr_info("%s%s%s",
506 "RWB[desc] [PcsmIpSHl PtRs] ",
507 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 508 "<-- Adv Rx Write-Back format\n");
509
510 for (i = 0; i < rx_ring->count; i++) {
511 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 512 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 513 u0 = (struct my_u0 *)rx_desc;
514 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
515 if (staterr & IXGBE_RXD_STAT_DD) {
516 /* Descriptor Done */
c7689578 517 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 518 "%016llX ---------------- %p", i,
519 le64_to_cpu(u0->a),
520 le64_to_cpu(u0->b),
521 rx_buffer_info->skb);
522 } else {
c7689578 523 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 524 "%016llX %016llX %p", i,
525 le64_to_cpu(u0->a),
526 le64_to_cpu(u0->b),
527 (u64)rx_buffer_info->dma,
528 rx_buffer_info->skb);
529
9c50c035
ET		 530 if (netif_msg_pktdata(adapter) &&
531 rx_buffer_info->dma) {
dcd79aeb
TI		 532 print_hex_dump(KERN_INFO, "",
533 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 534 page_address(rx_buffer_info->page) +
535 rx_buffer_info->page_offset,
f800326d 536 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 537 }
538 }
539
540 if (i == rx_ring->next_to_use)
c7689578 541 pr_cont(" NTU\n");
dcd79aeb 542 else if (i == rx_ring->next_to_clean)
c7689578 543 pr_cont(" NTC\n");
dcd79aeb 544 else
c7689578 545 pr_cont("\n");
dcd79aeb
TI		 546
547 }
548 }
549
550exit:
551 return;
552}
553
5eba3699
AV		 554static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555{
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 562}
563
564static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565{
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 572}
9a799d71 573
49ce9c2c 574/**
e8e26350
PW		 575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 583 u8 queue, u8 msix_vector)
9a799d71
AK		 584{
585 u32 ivar, index;
e8e26350
PW		 586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
b93a2226 599 case ixgbe_mac_X540:
e8e26350
PW		 600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
9a799d71
AK		 622}
623
fe49f04a 624static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 625 u64 qmask)
fe49f04a
AD		 626{
627 u32 mask;
628
bd508178
AD		 629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
fe49f04a
AD		 631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 633 break;
634 case ixgbe_mac_82599EB:
b93a2226 635 case ixgbe_mac_X540:
fe49f04a
AD		 636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 640 break;
641 default:
642 break;
fe49f04a
AD		 643 }
644}
645
729739b7
AD		 646void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 648{
729739b7
AD		 649 if (tx_buffer->skb) {
650 dev_kfree_skb_any(tx_buffer->skb);
651 if (dma_unmap_len(tx_buffer, len))
d3d00239 652 dma_unmap_single(ring->dev,
729739b7
AD		 653 dma_unmap_addr(tx_buffer, dma),
654 dma_unmap_len(tx_buffer, len),
655 DMA_TO_DEVICE);
656 } else if (dma_unmap_len(tx_buffer, len)) {
657 dma_unmap_page(ring->dev,
658 dma_unmap_addr(tx_buffer, dma),
659 dma_unmap_len(tx_buffer, len),
660 DMA_TO_DEVICE);
e5a43549 661 }
729739b7
AD		 662 tx_buffer->next_to_watch = NULL;
663 tx_buffer->skb = NULL;
664 dma_unmap_len_set(tx_buffer, len, 0);
665 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 666}
667
943561d3 668static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 669{
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 672 int i;
943561d3 673 u32 data;
c84d324c 674
943561d3
AD		 675 if ((hw->fc.current_mode != ixgbe_fc_full) &&
676 (hw->fc.current_mode != ixgbe_fc_rx_pause))
677 return;
c84d324c 678
943561d3
AD		 679 switch (hw->mac.type) {
680 case ixgbe_mac_82598EB:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
682 break;
683 default:
684 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
685 }
686 hwstats->lxoffrxc += data;
c84d324c 687
943561d3
AD		 688 /* refill credits (no tx hang) if we received xoff */
689 if (!data)
c84d324c 690 return;
943561d3
AD		 691
692 for (i = 0; i < adapter->num_tx_queues; i++)
693 clear_bit(__IXGBE_HANG_CHECK_ARMED,
694 &adapter->tx_ring[i]->state);
695}
696
697static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
698{
699 struct ixgbe_hw *hw = &adapter->hw;
700 struct ixgbe_hw_stats *hwstats = &adapter->stats;
701 u32 xoff[8] = {0};
2afaa00d 702 u8 tc;
943561d3
AD		 703 int i;
704 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
705
706 if (adapter->ixgbe_ieee_pfc)
707 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
708
709 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
710 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 711 return;
943561d3 712 }
c84d324c
JF		 713
714 /* update stats for each tc, only valid with PFC enabled */
715 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 716 u32 pxoffrxc;
717
c84d324c
JF		 718 switch (hw->mac.type) {
719 case ixgbe_mac_82598EB:
2afaa00d 720 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 721 break;
c84d324c 722 default:
2afaa00d 723 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 724 }
2afaa00d
PN		 725 hwstats->pxoffrxc[i] += pxoffrxc;
726 /* Get the TC for given UP */
727 tc = netdev_get_prio_tc_map(adapter->netdev, i);
728 xoff[tc] += pxoffrxc;
c84d324c
JF		 729 }
730
731 /* disarm tx queues that have received xoff frames */
732 for (i = 0; i < adapter->num_tx_queues; i++) {
733 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 734
2afaa00d 735 tc = tx_ring->dcb_tc;
c84d324c
JF		 736 if (xoff[tc])
737 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 738 }
26f23d82
YZ		 739}
740
c84d324c 741static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 742{
7d7ce682 743 return ring->stats.packets;
c84d324c
JF		 744}
745
746static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
747{
748 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 749 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 750
c84d324c
JF		 751 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
752 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
753
754 if (head != tail)
755 return (head < tail) ?
756 tail - head : (tail + ring->count - head);
757
758 return 0;
759}
760
761static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
762{
763 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
764 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
765 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
766 bool ret = false;
767
7d637bcc 768 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 769
770 /*
771 * Check for a hung queue, but be thorough. This verifies
772 * that a transmit has been completed since the previous
773 * check AND there is at least one packet pending. The
774 * ARMED bit is set to indicate a potential hang. The
775 * bit is cleared if a pause frame is received to remove
776 * false hang detection due to PFC or 802.3x frames. By
777 * requiring this to fail twice we avoid races with
778 * pfc clearing the ARMED bit and conditions where we
779 * run the check_tx_hang logic with a transmit completion
780 * pending but without time to complete it yet.
781 */
782 if ((tx_done_old == tx_done) && tx_pending) {
783 /* make sure it is true for two checks in a row */
784 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
785 &tx_ring->state);
786 } else {
787 /* update completed stats and continue */
788 tx_ring->tx_stats.tx_done_old = tx_done;
789 /* reset the countdown */
790 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 791 }
792
c84d324c 793 return ret;
9a799d71
AK		 794}
795
c83c6cbd
AD		 796/**
797 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
798 * @adapter: driver private struct
799 **/
800static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
801{
802
803 /* Do the reset outside of interrupt context */
804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
805 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
806 ixgbe_service_event_schedule(adapter);
807 }
808}
e01c31a5 809
9a799d71
AK		 810/**
811 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 812 * @q_vector: structure containing interrupt and ring information
e01c31a5 813 * @tx_ring: tx ring to clean
9a799d71 814 **/
fe49f04a 815static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 816 struct ixgbe_ring *tx_ring)
9a799d71 817{
fe49f04a 818 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 819 struct ixgbe_tx_buffer *tx_buffer;
820 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 821 unsigned int total_bytes = 0, total_packets = 0;
59224555 822 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 823 unsigned int i = tx_ring->next_to_clean;
824
825 if (test_bit(__IXGBE_DOWN, &adapter->state))
826 return true;
9a799d71 827
d3d00239 828 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 829 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 830 i -= tx_ring->count;
12207e49 831
729739b7 832 do {
d3d00239
AD		 833 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
834
835 /* if next_to_watch is not set then there is no work pending */
836 if (!eop_desc)
837 break;
838
7f83a9e6
AD		 839 /* prevent any other reads prior to eop_desc */
840 rmb();
841
d3d00239
AD		 842 /* if DD is not set pending work has not been completed */
843 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
844 break;
8ad494b0 845
d3d00239
AD		 846 /* clear next_to_watch to prevent false hangs */
847 tx_buffer->next_to_watch = NULL;
8ad494b0 848
091a6246
AD		 849 /* update the statistics for this packet */
850 total_bytes += tx_buffer->bytecount;
851 total_packets += tx_buffer->gso_segs;
852
0ede4a60
JK		 853 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
854 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
0ede4a60 855
fd0db0ed
AD		 856 /* free the skb */
857 dev_kfree_skb_any(tx_buffer->skb);
858
729739b7
AD		 859 /* unmap skb header data */
860 dma_unmap_single(tx_ring->dev,
861 dma_unmap_addr(tx_buffer, dma),
862 dma_unmap_len(tx_buffer, len),
863 DMA_TO_DEVICE);
864
fd0db0ed
AD		 865 /* clear tx_buffer data */
866 tx_buffer->skb = NULL;
729739b7 867 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 868
729739b7
AD		 869 /* unmap remaining buffers */
870 while (tx_desc != eop_desc) {
d3d00239
AD		 871 tx_buffer++;
872 tx_desc++;
8ad494b0 873 i++;
729739b7
AD		 874 if (unlikely(!i)) {
875 i -= tx_ring->count;
d3d00239 876 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 877 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 878 }
e01c31a5 879
729739b7
AD		 880 /* unmap any remaining paged data */
881 if (dma_unmap_len(tx_buffer, len)) {
882 dma_unmap_page(tx_ring->dev,
883 dma_unmap_addr(tx_buffer, dma),
884 dma_unmap_len(tx_buffer, len),
885 DMA_TO_DEVICE);
886 dma_unmap_len_set(tx_buffer, len, 0);
887 }
888 }
889
890 /* move us one more past the eop_desc for start of next pkt */
891 tx_buffer++;
892 tx_desc++;
893 i++;
894 if (unlikely(!i)) {
895 i -= tx_ring->count;
896 tx_buffer = tx_ring->tx_buffer_info;
897 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
898 }
899
900 /* issue prefetch for next Tx descriptor */
901 prefetch(tx_desc);
12207e49 902
729739b7
AD		 903 /* update budget accounting */
904 budget--;
905 } while (likely(budget));
906
907 i += tx_ring->count;
9a799d71 908 tx_ring->next_to_clean = i;
d3d00239 909 u64_stats_update_begin(&tx_ring->syncp);
b953799e 910 tx_ring->stats.bytes += total_bytes;
bd198058 911 tx_ring->stats.packets += total_packets;
d3d00239 912 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 913 q_vector->tx.total_bytes += total_bytes;
914 q_vector->tx.total_packets += total_packets;
b953799e 915
c84d324c
JF		 916 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
917 /* schedule immediate reset if we believe we hung */
918 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 919 e_err(drv, "Detected Tx Unit Hang\n"
920 " Tx Queue <%d>\n"
921 " TDH, TDT <%x>, <%x>\n"
922 " next_to_use <%x>\n"
923 " next_to_clean <%x>\n"
924 "tx_buffer_info[next_to_clean]\n"
925 " time_stamp <%lx>\n"
926 " jiffies <%lx>\n",
927 tx_ring->queue_index,
928 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
929 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 930 tx_ring->next_to_use, i,
931 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 932
933 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
934
935 e_info(probe,
936 "tx hang %d detected on queue %d, resetting adapter\n",
937 adapter->tx_timeout_count + 1, tx_ring->queue_index);
938
b953799e 939 /* schedule immediate reset if we believe we hung */
c83c6cbd 940 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 941
942 /* the adapter is about to reset, no point in enabling stuff */
59224555 943 return true;
b953799e 944 }
9a799d71 945
b2d96e0a
AD		 946 netdev_tx_completed_queue(txring_txq(tx_ring),
947 total_packets, total_bytes);
948
e092be60 949#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 950 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 951 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 952 /* Make sure that anybody stopping the queue after this
953 * sees the new next_to_clean.
954 */
955 smp_mb();
729739b7
AD		 956 if (__netif_subqueue_stopped(tx_ring->netdev,
957 tx_ring->queue_index)
958 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
959 netif_wake_subqueue(tx_ring->netdev,
960 tx_ring->queue_index);
5b7da515 961 ++tx_ring->tx_stats.restart_queue;
30eba97a 962 }
e092be60 963 }
9a799d71 964
59224555 965 return !!budget;
9a799d71
AK		 966}
967
5dd2d332 968#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 969static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
970 struct ixgbe_ring *tx_ring,
33cf09c9 971 int cpu)
bd0362dd 972{
33cf09c9 973 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 974 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
975 u16 reg_offset;
33cf09c9 976
33cf09c9
AD		 977 switch (hw->mac.type) {
978 case ixgbe_mac_82598EB:
bdda1a61 979 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 980 break;
981 case ixgbe_mac_82599EB:
b93a2226 982 case ixgbe_mac_X540:
bdda1a61
AD		 983 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
984 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 985 break;
986 default:
bdda1a61
AD		 987 /* for unknown hardware do not write register */
988 return;
bd0362dd 989 }
bdda1a61
AD		 990
991 /*
992 * We can enable relaxed ordering for reads, but not writes when
993 * DCA is enabled. This is due to a known issue in some chipsets
994 * which will cause the DCA tag to be cleared.
995 */
996 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
997 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
998 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
999
1000 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1001}
1002
bdda1a61
AD		 1003static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1004 struct ixgbe_ring *rx_ring,
33cf09c9 1005 int cpu)
bd0362dd 1006{
33cf09c9 1007 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1008 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1009 u8 reg_idx = rx_ring->reg_idx;
1010
33cf09c9
AD		 1011
1012 switch (hw->mac.type) {
33cf09c9 1013 case ixgbe_mac_82599EB:
b93a2226 1014 case ixgbe_mac_X540:
bdda1a61 1015 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1016 break;
1017 default:
1018 break;
1019 }
bdda1a61
AD		 1020
1021 /*
1022 * We can enable relaxed ordering for reads, but not writes when
1023 * DCA is enabled. This is due to a known issue in some chipsets
1024 * which will cause the DCA tag to be cleared.
1025 */
1026 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1027 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1028
1029 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1030}
1031
1032static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1033{
1034 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1035 struct ixgbe_ring *ring;
bd0362dd 1036 int cpu = get_cpu();
bd0362dd 1037
33cf09c9
AD		 1038 if (q_vector->cpu == cpu)
1039 goto out_no_update;
1040
a557928e 1041 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1042 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1043
a557928e 1044 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1045 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1046
1047 q_vector->cpu = cpu;
1048out_no_update:
bd0362dd
JC		 1049 put_cpu();
1050}
1051
1052static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1053{
1054 int i;
1055
1056 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1057 return;
1058
e35ec126
AD		 1059 /* always use CB2 mode, difference is masked in the CB driver */
1060 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1061
49c7ffbe 1062 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1063 adapter->q_vector[i]->cpu = -1;
1064 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1065 }
1066}
1067
1068static int __ixgbe_notify_dca(struct device *dev, void *data)
1069{
c60fbb00 1070 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1071 unsigned long event = *(unsigned long *)data;
1072
2a72c31e 1073 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1074 return 0;
1075
bd0362dd
JC		 1076 switch (event) {
1077 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1078 /* if we're already enabled, don't do it again */
1079 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1080 break;
652f093f 1081 if (dca_add_requester(dev) == 0) {
96b0e0f6 1082 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1083 ixgbe_setup_dca(adapter);
1084 break;
1085 }
1086 /* Fall Through since DCA is disabled. */
1087 case DCA_PROVIDER_REMOVE:
1088 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1089 dca_remove_requester(dev);
1090 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1091 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1092 }
1093 break;
1094 }
1095
652f093f 1096 return 0;
bd0362dd 1097}
67a74ee2 1098
bdda1a61 1099#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1100static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1101 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1102 struct sk_buff *skb)
1103{
8a0da21b
AD		 1104 if (ring->netdev->features & NETIF_F_RXHASH)
1105 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1106}
1107
f800326d 1108#ifdef IXGBE_FCOE
ff886dfc
AD		 1109/**
1110 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1111 * @ring: structure containing ring specific data
ff886dfc
AD		 1112 * @rx_desc: advanced rx descriptor
1113 *
1114 * Returns : true if it is FCoE pkt
1115 */
57efd44c 1116static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1117 union ixgbe_adv_rx_desc *rx_desc)
1118{
1119 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1120
57efd44c 1121 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1122 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1123 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1124 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1125}
1126
f800326d 1127#endif /* IXGBE_FCOE */
e59bd25d
AV		 1128/**
1129 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1130 * @ring: structure containing ring specific data
1131 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1132 * @skb: skb currently being received and modified
1133 **/
8a0da21b 1134static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1135 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1136 struct sk_buff *skb)
9a799d71 1137{
8a0da21b 1138 skb_checksum_none_assert(skb);
9a799d71 1139
712744be 1140 /* Rx csum disabled */
8a0da21b 1141 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1142 return;
e59bd25d
AV		 1143
1144 /* if IP and error */
f56e0cb1
AD		 1145 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1146 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1147 ring->rx_stats.csum_err++;
9a799d71
AK		 1148 return;
1149 }
e59bd25d 1150
f56e0cb1 1151 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1152 return;
1153
f56e0cb1 1154 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1155 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1156
1157 /*
1158 * 82599 errata, UDP frames with a 0 checksum can be marked as
1159 * checksum errors.
1160 */
8a0da21b
AD		 1161 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1162 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1163 return;
1164
8a0da21b 1165 ring->rx_stats.csum_err++;
e59bd25d
AV		 1166 return;
1167 }
1168
9a799d71 1169 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1170 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1171}
1172
84ea2591 1173static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1174{
f56e0cb1 1175 rx_ring->next_to_use = val;
f800326d
AD		 1176
1177 /* update next to alloc since we have filled the ring */
1178 rx_ring->next_to_alloc = val;
e8e26350
PW		 1179 /*
1180 * Force memory writes to complete before letting h/w
1181 * know there are new descriptors to fetch. (Only
1182 * applicable for weak-ordered memory model archs,
1183 * such as IA-64).
1184 */
1185 wmb();
84ea2591 1186 writel(val, rx_ring->tail);
e8e26350
PW		 1187}
1188
f990b79b
AD		 1189static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1190 struct ixgbe_rx_buffer *bi)
1191{
1192 struct page *page = bi->page;
f800326d 1193 dma_addr_t dma = bi->dma;
f990b79b 1194
f800326d
AD		 1195 /* since we are recycling buffers we should seldom need to alloc */
1196 if (likely(dma))
f990b79b
AD		 1197 return true;
1198
f800326d
AD		 1199 /* alloc new page for storage */
1200 if (likely(!page)) {
0614002b
MG		 1201 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1202 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1203 if (unlikely(!page)) {
1204 rx_ring->rx_stats.alloc_rx_page_failed++;
1205 return false;
1206 }
f800326d 1207 bi->page = page;
f990b79b
AD		 1208 }
1209
f800326d
AD		 1210 /* map page for use */
1211 dma = dma_map_page(rx_ring->dev, page, 0,
1212 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1213
1214 /*
1215 * if mapping failed free memory back to system since
1216 * there isn't much point in holding memory we can't use
1217 */
1218 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1219 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1220 bi->page = NULL;
f990b79b 1221
f990b79b
AD		 1222 rx_ring->rx_stats.alloc_rx_page_failed++;
1223 return false;
1224 }
1225
f800326d 1226 bi->dma = dma;
afaa9459 1227 bi->page_offset = 0;
f800326d 1228
f990b79b
AD		 1229 return true;
1230}
1231
9a799d71 1232/**
f990b79b 1233 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1234 * @rx_ring: ring to place buffers on
1235 * @cleaned_count: number of buffers to replace
9a799d71 1236 **/
fc77dc3c 1237void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1238{
9a799d71 1239 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1240 struct ixgbe_rx_buffer *bi;
d5f398ed 1241 u16 i = rx_ring->next_to_use;
9a799d71 1242
f800326d
AD		 1243 /* nothing to do */
1244 if (!cleaned_count)
fc77dc3c
AD		 1245 return;
1246
e4f74028 1247 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1248 bi = &rx_ring->rx_buffer_info[i];
1249 i -= rx_ring->count;
9a799d71 1250
f800326d
AD		 1251 do {
1252 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1253 break;
d5f398ed 1254
f800326d
AD		 1255 /*
1256 * Refresh the desc even if buffer_addrs didn't change
1257 * because each write-back erases this info.
1258 */
1259 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1260
f990b79b
AD		 1261 rx_desc++;
1262 bi++;
9a799d71 1263 i++;
f990b79b 1264 if (unlikely(!i)) {
e4f74028 1265 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1266 bi = rx_ring->rx_buffer_info;
1267 i -= rx_ring->count;
1268 }
1269
1270 /* clear the hdr_addr for the next_to_use descriptor */
1271 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1272
1273 cleaned_count--;
1274 } while (cleaned_count);
7c6e0a43 1275
f990b79b
AD		 1276 i += rx_ring->count;
1277
f56e0cb1 1278 if (rx_ring->next_to_use != i)
84ea2591 1279 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1280}
1281
1d2024f6
AD		 1282/**
1283 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1284 * @data: pointer to the start of the headers
1285 * @max_len: total length of section to find headers in
1286 *
1287 * This function is meant to determine the length of headers that will
1288 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1289 * motivation of doing this is to only perform one pull for IPv4 TCP
1290 * packets so that we can do basic things like calculating the gso_size
1291 * based on the average data per packet.
1292 **/
1293static unsigned int ixgbe_get_headlen(unsigned char *data,
1294 unsigned int max_len)
1295{
1296 union {
1297 unsigned char *network;
1298 /* l2 headers */
1299 struct ethhdr *eth;
1300 struct vlan_hdr *vlan;
1301 /* l3 headers */
1302 struct iphdr *ipv4;
a048b40e 1303 struct ipv6hdr *ipv6;
1d2024f6
AD		 1304 } hdr;
1305 __be16 protocol;
1306 u8 nexthdr = 0; /* default to not TCP */
1307 u8 hlen;
1308
1309 /* this should never happen, but better safe than sorry */
1310 if (max_len < ETH_HLEN)
1311 return max_len;
1312
1313 /* initialize network frame pointer */
1314 hdr.network = data;
1315
1316 /* set first protocol and move network header forward */
1317 protocol = hdr.eth->h_proto;
1318 hdr.network += ETH_HLEN;
1319
1320 /* handle any vlan tag if present */
1321 if (protocol == __constant_htons(ETH_P_8021Q)) {
1322 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1323 return max_len;
1324
1325 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1326 hdr.network += VLAN_HLEN;
1327 }
1328
1329 /* handle L3 protocols */
1330 if (protocol == __constant_htons(ETH_P_IP)) {
1331 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1332 return max_len;
1333
1334 /* access ihl as a u8 to avoid unaligned access on ia64 */
1335 hlen = (hdr.network[0] & 0x0F) << 2;
1336
1337 /* verify hlen meets minimum size requirements */
1338 if (hlen < sizeof(struct iphdr))
1339 return hdr.network - data;
1340
ed83da12
AD		 1341 /* record next protocol if header is present */
1342 if (!hdr.ipv4->frag_off)
1343 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1344 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1345 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1346 return max_len;
1347
1348 /* record next protocol */
1349 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1350 hlen = sizeof(struct ipv6hdr);
f800326d 1351#ifdef IXGBE_FCOE
1d2024f6
AD		 1352 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1353 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1354 return max_len;
ed83da12 1355 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1356#endif
1357 } else {
1358 return hdr.network - data;
1359 }
1360
ed83da12
AD		 1361 /* relocate pointer to start of L4 header */
1362 hdr.network += hlen;
1363
a048b40e 1364 /* finally sort out TCP/UDP */
1d2024f6
AD		 1365 if (nexthdr == IPPROTO_TCP) {
1366 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1367 return max_len;
1368
1369 /* access doff as a u8 to avoid unaligned access on ia64 */
1370 hlen = (hdr.network[12] & 0xF0) >> 2;
1371
1372 /* verify hlen meets minimum size requirements */
1373 if (hlen < sizeof(struct tcphdr))
1374 return hdr.network - data;
1375
1376 hdr.network += hlen;
a048b40e
AD		 1377 } else if (nexthdr == IPPROTO_UDP) {
1378 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1379 return max_len;
1380
1381 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1382 }
1383
1384 /*
1385 * If everything has gone correctly hdr.network should be the
1386 * data section of the packet and will be the end of the header.
1387 * If not then it probably represents the end of the last recognized
1388 * header.
1389 */
1390 if ((hdr.network - data) < max_len)
1391 return hdr.network - data;
1392 else
1393 return max_len;
1394}
1395
1d2024f6
AD		 1396static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1397 struct sk_buff *skb)
1398{
f800326d 1399 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1400
1401 /* set gso_size to avoid messing up TCP MSS */
1402 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1403 IXGBE_CB(skb)->append_cnt);
1594712f
MT		 1404 if (skb->protocol == __constant_htons(ETH_P_IPV6))
1405 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
1406 else
1407 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1408}
1409
1410static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1411 struct sk_buff *skb)
1412{
1413 /* if append_cnt is 0 then frame is not RSC */
1414 if (!IXGBE_CB(skb)->append_cnt)
1415 return;
1416
1417 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1418 rx_ring->rx_stats.rsc_flush++;
1419
1420 ixgbe_set_rsc_gso_size(rx_ring, skb);
1421
1422 /* gso_size is computed using append_cnt so always clear it last */
1423 IXGBE_CB(skb)->append_cnt = 0;
1424}
1425
8a0da21b
AD		 1426/**
1427 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1428 * @rx_ring: rx descriptor ring packet is being transacted on
1429 * @rx_desc: pointer to the EOP Rx descriptor
1430 * @skb: pointer to current skb being populated
f8212f97 1431 *
8a0da21b
AD		 1432 * This function checks the ring, descriptor, and packet information in
1433 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1434 * other fields within the skb.
f8212f97 1435 **/
8a0da21b
AD		 1436static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1437 union ixgbe_adv_rx_desc *rx_desc,
1438 struct sk_buff *skb)
f8212f97 1439{
43e95f11
JF		 1440 struct net_device *dev = rx_ring->netdev;
1441
1594712f
MT		 1442 skb->protocol = eth_type_trans(skb, dev);
1443
8a0da21b
AD		 1444 ixgbe_update_rsc_stats(rx_ring, skb);
1445
1446 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1447
8a0da21b
AD		 1448 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1449
1d1a79b5 1450 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda 1451
43e95f11
JF		 1452 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1453 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1454 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1455 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1456 }
1457
8a0da21b 1458 skb_record_rx_queue(skb, rx_ring->queue_index);
f8212f97
AD		 1459}
1460
8a0da21b
AD		 1461static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1462 struct sk_buff *skb)
aa80175a 1463{
8a0da21b
AD		 1464 struct ixgbe_adapter *adapter = q_vector->adapter;
1465
1466 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1467 napi_gro_receive(&q_vector->napi, skb);
1468 else
1469 netif_rx(skb);
aa80175a 1470}
43634e82 1471
f800326d
AD		 1472/**
1473 * ixgbe_is_non_eop - process handling of non-EOP buffers
1474 * @rx_ring: Rx ring being processed
1475 * @rx_desc: Rx descriptor for current buffer
1476 * @skb: Current socket buffer containing buffer in progress
1477 *
1478 * This function updates next to clean. If the buffer is an EOP buffer
1479 * this function exits returning false, otherwise it will place the
1480 * sk_buff in the next buffer to be chained and return true indicating
1481 * that this is in fact a non-EOP buffer.
1482 **/
1483static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1484 union ixgbe_adv_rx_desc *rx_desc,
1485 struct sk_buff *skb)
1486{
1487 u32 ntc = rx_ring->next_to_clean + 1;
1488
1489 /* fetch, update, and store next to clean */
1490 ntc = (ntc < rx_ring->count) ? ntc : 0;
1491 rx_ring->next_to_clean = ntc;
1492
1493 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1494
5a02cbd1
AD		 1495 /* update RSC append count if present */
1496 if (ring_is_rsc_enabled(rx_ring)) {
1497 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1498 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1499
1500 if (unlikely(rsc_enabled)) {
1501 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1502
1503 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1504 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1505
5a02cbd1
AD		 1506 /* update ntc based on RSC value */
1507 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1508 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1509 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1510 }
f800326d
AD		 1511 }
1512
5a02cbd1
AD		 1513 /* if we are the last buffer then there is nothing else to do */
1514 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1515 return false;
1516
f800326d
AD		 1517 /* place skb in next buffer to be received */
1518 rx_ring->rx_buffer_info[ntc].skb = skb;
1519 rx_ring->rx_stats.non_eop_descs++;
1520
1521 return true;
1522}
1523
19861ce2
AD		 1524/**
1525 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1526 * @rx_ring: rx descriptor ring packet is being transacted on
1527 * @skb: pointer to current skb being adjusted
1528 *
1529 * This function is an ixgbe specific version of __pskb_pull_tail. The
1530 * main difference between this version and the original function is that
1531 * this function can make several assumptions about the state of things
1532 * that allow for significant optimizations versus the standard function.
1533 * As a result we can do things like drop a frag and maintain an accurate
1534 * truesize for the skb.
1535 */
1536static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1537 struct sk_buff *skb)
1538{
1539 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1540 unsigned char *va;
1541 unsigned int pull_len;
1542
1543 /*
1544 * it is valid to use page_address instead of kmap since we are
1545 * working with pages allocated out of the lomem pool per
1546 * alloc_page(GFP_ATOMIC)
1547 */
1548 va = skb_frag_address(frag);
1549
1550 /*
1551 * we need the header to contain the greater of either ETH_HLEN or
1552 * 60 bytes if the skb->len is less than 60 for skb_pad.
1553 */
cf3fe7ac 1554 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1555
1556 /* align pull length to size of long to optimize memcpy performance */
1557 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1558
1559 /* update all of the pointers */
1560 skb_frag_size_sub(frag, pull_len);
1561 frag->page_offset += pull_len;
1562 skb->data_len -= pull_len;
1563 skb->tail += pull_len;
19861ce2
AD		 1564}
1565
42073d91
AD		 1566/**
1567 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1568 * @rx_ring: rx descriptor ring packet is being transacted on
1569 * @skb: pointer to current skb being updated
1570 *
1571 * This function provides a basic DMA sync up for the first fragment of an
1572 * skb. The reason for doing this is that the first fragment cannot be
1573 * unmapped until we have reached the end of packet descriptor for a buffer
1574 * chain.
1575 */
1576static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1577 struct sk_buff *skb)
1578{
1579 /* if the page was released unmap it, else just sync our portion */
1580 if (unlikely(IXGBE_CB(skb)->page_released)) {
1581 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1582 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1583 IXGBE_CB(skb)->page_released = false;
1584 } else {
1585 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1586
1587 dma_sync_single_range_for_cpu(rx_ring->dev,
1588 IXGBE_CB(skb)->dma,
1589 frag->page_offset,
1590 ixgbe_rx_bufsz(rx_ring),
1591 DMA_FROM_DEVICE);
1592 }
1593 IXGBE_CB(skb)->dma = 0;
1594}
1595
f800326d
AD		 1596/**
1597 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1598 * @rx_ring: rx descriptor ring packet is being transacted on
1599 * @rx_desc: pointer to the EOP Rx descriptor
1600 * @skb: pointer to current skb being fixed
1601 *
1602 * Check for corrupted packet headers caused by senders on the local L2
1603 * embedded NIC switch not setting up their Tx Descriptors right. These
1604 * should be very rare.
1605 *
1606 * Also address the case where we are pulling data in on pages only
1607 * and as such no data is present in the skb header.
1608 *
1609 * In addition if skb is not at least 60 bytes we need to pad it so that
1610 * it is large enough to qualify as a valid Ethernet frame.
1611 *
1612 * Returns true if an error was encountered and skb was freed.
1613 **/
1614static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1615 union ixgbe_adv_rx_desc *rx_desc,
1616 struct sk_buff *skb)
1617{
f800326d 1618 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1619
1620 /* verify that the packet does not have any known errors */
1621 if (unlikely(ixgbe_test_staterr(rx_desc,
1622 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1623 !(netdev->features & NETIF_F_RXALL))) {
1624 dev_kfree_skb_any(skb);
1625 return true;
1626 }
1627
19861ce2 1628 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1629 if (skb_is_nonlinear(skb))
1630 ixgbe_pull_tail(rx_ring, skb);
f800326d 1631
57efd44c
AD		 1632#ifdef IXGBE_FCOE
1633 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1634 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1635 return false;
1636
1637#endif
f800326d
AD		 1638 /* if skb_pad returns an error the skb was freed */
1639 if (unlikely(skb->len < 60)) {
1640 int pad_len = 60 - skb->len;
1641
1642 if (skb_pad(skb, pad_len))
1643 return true;
1644 __skb_put(skb, pad_len);
1645 }
1646
1647 return false;
1648}
1649
f800326d
AD		 1650/**
1651 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1652 * @rx_ring: rx descriptor ring to store buffers on
1653 * @old_buff: donor buffer to have page reused
1654 *
0549ae20 1655 * Synchronizes page for reuse by the adapter
f800326d
AD		 1656 **/
1657static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1658 struct ixgbe_rx_buffer *old_buff)
1659{
1660 struct ixgbe_rx_buffer *new_buff;
1661 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1662
1663 new_buff = &rx_ring->rx_buffer_info[nta];
1664
1665 /* update, and store next to alloc */
1666 nta++;
1667 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1668
1669 /* transfer page from old buffer to new buffer */
1670 new_buff->page = old_buff->page;
1671 new_buff->dma = old_buff->dma;
0549ae20 1672 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1673
1674 /* sync the buffer for use by the device */
1675 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1676 new_buff->page_offset,
1677 ixgbe_rx_bufsz(rx_ring),
f800326d 1678 DMA_FROM_DEVICE);
f800326d
AD		 1679}
1680
1681/**
1682 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1683 * @rx_ring: rx descriptor ring to transact packets on
1684 * @rx_buffer: buffer containing page to add
1685 * @rx_desc: descriptor containing length of buffer written by hardware
1686 * @skb: sk_buff to place the data into
1687 *
0549ae20
AD		 1688 * This function will add the data contained in rx_buffer->page to the skb.
1689 * This is done either through a direct copy if the data in the buffer is
1690 * less than the skb header size, otherwise it will just attach the page as
1691 * a frag to the skb.
1692 *
1693 * The function will then update the page offset if necessary and return
1694 * true if the buffer can be reused by the adapter.
f800326d 1695 **/
0549ae20 1696static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1697 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1698 union ixgbe_adv_rx_desc *rx_desc,
1699 struct sk_buff *skb)
f800326d 1700{
0549ae20
AD		 1701 struct page *page = rx_buffer->page;
1702 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1703#if (PAGE_SIZE < 8192)
0549ae20 1704 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1705#else
1706 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1707 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1708 ixgbe_rx_bufsz(rx_ring);
1709#endif
0549ae20 1710
cf3fe7ac
AD		 1711 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1712 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1713
1714 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1715
1716 /* we can reuse buffer as-is, just make sure it is local */
1717 if (likely(page_to_nid(page) == numa_node_id()))
1718 return true;
1719
1720 /* this page cannot be reused so discard it */
1721 put_page(page);
1722 return false;
1723 }
1724
0549ae20
AD		 1725 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1726 rx_buffer->page_offset, size, truesize);
1727
09816fbe
AD		 1728 /* avoid re-using remote pages */
1729 if (unlikely(page_to_nid(page) != numa_node_id()))
1730 return false;
1731
1732#if (PAGE_SIZE < 8192)
1733 /* if we are only owner of page we can reuse it */
1734 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1735 return false;
1736
1737 /* flip page offset to other buffer */
1738 rx_buffer->page_offset ^= truesize;
1739
09816fbe
AD		 1740 /*
1741 * since we are the only owner of the page and we need to
1742 * increment it, just set the value to 2 in order to avoid
1743 * an unecessary locked operation
1744 */
1745 atomic_set(&page->_count, 2);
1746#else
1747 /* move offset up to the next cache line */
1748 rx_buffer->page_offset += truesize;
1749
1750 if (rx_buffer->page_offset > last_offset)
1751 return false;
1752
0549ae20
AD		 1753 /* bump ref count on page before it is given to the stack */
1754 get_page(page);
09816fbe 1755#endif
0549ae20
AD		 1756
1757 return true;
f800326d
AD		 1758}
1759
18806c9e
AD		 1760static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1761 union ixgbe_adv_rx_desc *rx_desc)
1762{
1763 struct ixgbe_rx_buffer *rx_buffer;
1764 struct sk_buff *skb;
1765 struct page *page;
1766
1767 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1768 page = rx_buffer->page;
1769 prefetchw(page);
1770
1771 skb = rx_buffer->skb;
1772
1773 if (likely(!skb)) {
1774 void *page_addr = page_address(page) +
1775 rx_buffer->page_offset;
1776
1777 /* prefetch first cache line of first page */
1778 prefetch(page_addr);
1779#if L1_CACHE_BYTES < 128
1780 prefetch(page_addr + L1_CACHE_BYTES);
1781#endif
1782
1783 /* allocate a skb to store the frags */
1784 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1785 IXGBE_RX_HDR_SIZE);
1786 if (unlikely(!skb)) {
1787 rx_ring->rx_stats.alloc_rx_buff_failed++;
1788 return NULL;
1789 }
1790
1791 /*
1792 * we will be copying header into skb->data in
1793 * pskb_may_pull so it is in our interest to prefetch
1794 * it now to avoid a possible cache miss
1795 */
1796 prefetchw(skb->data);
1797
1798 /*
1799 * Delay unmapping of the first packet. It carries the
1800 * header information, HW may still access the header
1801 * after the writeback. Only unmap it when EOP is
1802 * reached
1803 */
1804 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1805 goto dma_sync;
1806
1807 IXGBE_CB(skb)->dma = rx_buffer->dma;
1808 } else {
1809 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1810 ixgbe_dma_sync_frag(rx_ring, skb);
1811
1812dma_sync:
1813 /* we are reusing so sync this buffer for CPU use */
1814 dma_sync_single_range_for_cpu(rx_ring->dev,
1815 rx_buffer->dma,
1816 rx_buffer->page_offset,
1817 ixgbe_rx_bufsz(rx_ring),
1818 DMA_FROM_DEVICE);
1819 }
1820
1821 /* pull page into skb */
1822 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1823 /* hand second half of page back to the ring */
1824 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1825 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1826 /* the page has been released from the ring */
1827 IXGBE_CB(skb)->page_released = true;
1828 } else {
1829 /* we are not reusing the buffer so unmap it */
1830 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1831 ixgbe_rx_pg_size(rx_ring),
1832 DMA_FROM_DEVICE);
1833 }
1834
1835 /* clear contents of buffer_info */
1836 rx_buffer->skb = NULL;
1837 rx_buffer->dma = 0;
1838 rx_buffer->page = NULL;
1839
1840 return skb;
f800326d
AD		 1841}
1842
1843/**
1844 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1845 * @q_vector: structure containing interrupt and ring information
1846 * @rx_ring: rx descriptor ring to transact packets on
1847 * @budget: Total limit on number of packets to process
1848 *
1849 * This function provides a "bounce buffer" approach to Rx interrupt
1850 * processing. The advantage to this is that on systems that have
1851 * expensive overhead for IOMMU access this provides a means of avoiding
1852 * it by maintaining the mapping of the page to the syste.
1853 *
1854 * Returns true if all work is completed without reaching budget
1855 **/
4ff7fb12 1856static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1857 struct ixgbe_ring *rx_ring,
f4de00ed 1858 const int budget)
9a799d71 1859{
d2f4fbe2 1860 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1861#ifdef IXGBE_FCOE
f800326d 1862 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1863 int ddp_bytes;
1864 unsigned int mss = 0;
3d8fd385 1865#endif /* IXGBE_FCOE */
f800326d 1866 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1867
f800326d 1868 do {
f800326d
AD		 1869 union ixgbe_adv_rx_desc *rx_desc;
1870 struct sk_buff *skb;
f800326d
AD		 1871
1872 /* return some buffers to hardware, one at a time is too slow */
1873 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1874 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1875 cleaned_count = 0;
1876 }
1877
18806c9e 1878 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1879
1880 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1881 break;
9a799d71 1882
f800326d
AD		 1883 /*
1884 * This memory barrier is needed to keep us from reading
1885 * any other fields out of the rx_desc until we know the
1886 * RXD_STAT_DD bit is set
1887 */
1888 rmb();
9a799d71 1889
18806c9e
AD		 1890 /* retrieve a buffer from the ring */
1891 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1892
18806c9e
AD		 1893 /* exit if we failed to retrieve a buffer */
1894 if (!skb)
1895 break;
9a799d71 1896
9a799d71 1897 cleaned_count++;
f8212f97 1898
f800326d
AD		 1899 /* place incomplete frames back on ring for completion */
1900 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1901 continue;
c267fc16 1902
f800326d
AD		 1903 /* verify the packet layout is correct */
1904 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1905 continue;
9a799d71 1906
d2f4fbe2
AV		 1907 /* probably a little skewed due to removing CRC */
1908 total_rx_bytes += skb->len;
d2f4fbe2 1909
8a0da21b
AD		 1910 /* populate checksum, timestamp, VLAN, and protocol */
1911 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1912
332d4a7d
YZ		 1913#ifdef IXGBE_FCOE
1914 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1915 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1916 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1917 /* include DDPed FCoE data */
1918 if (ddp_bytes > 0) {
1919 if (!mss) {
1920 mss = rx_ring->netdev->mtu -
1921 sizeof(struct fcoe_hdr) -
1922 sizeof(struct fc_frame_header) -
1923 sizeof(struct fcoe_crc_eof);
1924 if (mss > 512)
1925 mss &= ~511;
1926 }
1927 total_rx_bytes += ddp_bytes;
1928 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1929 mss);
1930 }
63d635b2
AD		 1931 if (!ddp_bytes) {
1932 dev_kfree_skb_any(skb);
f800326d 1933 continue;
63d635b2 1934 }
3d8fd385 1935 }
f800326d 1936
332d4a7d 1937#endif /* IXGBE_FCOE */
8a0da21b 1938 ixgbe_rx_skb(q_vector, skb);
9a799d71 1939
f800326d 1940 /* update budget accounting */
f4de00ed
AD		 1941 total_rx_packets++;
1942 } while (likely(total_rx_packets < budget));
9a799d71 1943
c267fc16
AD		 1944 u64_stats_update_begin(&rx_ring->syncp);
1945 rx_ring->stats.packets += total_rx_packets;
1946 rx_ring->stats.bytes += total_rx_bytes;
1947 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1948 q_vector->rx.total_packets += total_rx_packets;
1949 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1950
f800326d
AD		 1951 if (cleaned_count)
1952 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1953
f4de00ed 1954 return (total_rx_packets < budget);
9a799d71
AK		 1955}
1956
9a799d71
AK		 1957/**
1958 * ixgbe_configure_msix - Configure MSI-X hardware
1959 * @adapter: board private structure
1960 *
1961 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1962 * interrupts.
1963 **/
1964static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1965{
021230d4 1966 struct ixgbe_q_vector *q_vector;
49c7ffbe 1967 int v_idx;
021230d4 1968 u32 mask;
9a799d71 1969
8e34d1aa
AD		 1970 /* Populate MSIX to EITR Select */
1971 if (adapter->num_vfs > 32) {
1972 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1973 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1974 }
1975
4df10466
JB		 1976 /*
1977 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1978 * corresponding register.
1979 */
49c7ffbe 1980 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1981 struct ixgbe_ring *ring;
7a921c93 1982 q_vector = adapter->q_vector[v_idx];
021230d4 1983
a557928e 1984 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1985 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1986
a557928e 1987 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1988 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1989
fe49f04a 1990 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1991 }
1992
bd508178
AD		 1993 switch (adapter->hw.mac.type) {
1994 case ixgbe_mac_82598EB:
e8e26350 1995 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1996 v_idx);
bd508178
AD		 1997 break;
1998 case ixgbe_mac_82599EB:
b93a2226 1999 case ixgbe_mac_X540:
e8e26350 2000 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2001 break;
bd508178
AD		 2002 default:
2003 break;
2004 }
021230d4
AV		 2005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2006
41fb9248 2007 /* set up to autoclear timer, and the vectors */
021230d4 2008 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2009 mask &= ~(IXGBE_EIMS_OTHER |
2010 IXGBE_EIMS_MAILBOX |
2011 IXGBE_EIMS_LSC);
2012
021230d4 2013 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2014}
2015
f494e8fa
AV		 2016enum latency_range {
2017 lowest_latency = 0,
2018 low_latency = 1,
2019 bulk_latency = 2,
2020 latency_invalid = 255
2021};
2022
2023/**
2024 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2025 * @q_vector: structure containing interrupt and ring information
2026 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2027 *
2028 * Stores a new ITR value based on packets and byte
2029 * counts during the last interrupt. The advantage of per interrupt
2030 * computation is faster updates and more accurate ITR for the current
2031 * traffic pattern. Constants in this function were computed
2032 * based on theoretical maximum wire speed and thresholds were set based
2033 * on testing data as well as attempting to minimize response time
2034 * while increasing bulk throughput.
2035 * this functionality is controlled by the InterruptThrottleRate module
2036 * parameter (see ixgbe_param.c)
2037 **/
bd198058
AD		 2038static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2039 struct ixgbe_ring_container *ring_container)
f494e8fa 2040{
bd198058
AD		 2041 int bytes = ring_container->total_bytes;
2042 int packets = ring_container->total_packets;
2043 u32 timepassed_us;
621bd70e 2044 u64 bytes_perint;
bd198058 2045 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2046
2047 if (packets == 0)
bd198058 2048 return;
f494e8fa
AV		 2049
2050 /* simple throttlerate management
621bd70e
AD		 2051 * 0-10MB/s lowest (100000 ints/s)
2052 * 10-20MB/s low (20000 ints/s)
2053 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2054 */
2055 /* what was last interrupt timeslice? */
d5bf4f67 2056 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 2057 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2058
2059 switch (itr_setting) {
2060 case lowest_latency:
621bd70e 2061 if (bytes_perint > 10)
bd198058 2062 itr_setting = low_latency;
f494e8fa
AV		 2063 break;
2064 case low_latency:
621bd70e 2065 if (bytes_perint > 20)
bd198058 2066 itr_setting = bulk_latency;
621bd70e 2067 else if (bytes_perint <= 10)
bd198058 2068 itr_setting = lowest_latency;
f494e8fa
AV		 2069 break;
2070 case bulk_latency:
621bd70e 2071 if (bytes_perint <= 20)
bd198058 2072 itr_setting = low_latency;
f494e8fa
AV		 2073 break;
2074 }
2075
bd198058
AD		 2076 /* clear work counters since we have the values we need */
2077 ring_container->total_bytes = 0;
2078 ring_container->total_packets = 0;
2079
2080 /* write updated itr to ring container */
2081 ring_container->itr = itr_setting;
f494e8fa
AV		 2082}
2083
509ee935
JB		 2084/**
2085 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2086 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2087 *
2088 * This function is made to be called by ethtool and by the driver
2089 * when it needs to update EITR registers at runtime. Hardware
2090 * specific quirks/differences are taken care of here.
2091 */
fe49f04a 2092void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2093{
fe49f04a 2094 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2095 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2096 int v_idx = q_vector->v_idx;
5d967eb7 2097 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2098
bd508178
AD		 2099 switch (adapter->hw.mac.type) {
2100 case ixgbe_mac_82598EB:
509ee935
JB		 2101 /* must write high and low 16 bits to reset counter */
2102 itr_reg |= (itr_reg << 16);
bd508178
AD		 2103 break;
2104 case ixgbe_mac_82599EB:
b93a2226 2105 case ixgbe_mac_X540:
509ee935
JB		 2106 /*
2107 * set the WDIS bit to not clear the timer bits and cause an
2108 * immediate assertion of the interrupt
2109 */
2110 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2111 break;
2112 default:
2113 break;
509ee935
JB		 2114 }
2115 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2116}
2117
bd198058 2118static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2119{
d5bf4f67 2120 u32 new_itr = q_vector->itr;
bd198058 2121 u8 current_itr;
f494e8fa 2122
bd198058
AD		 2123 ixgbe_update_itr(q_vector, &q_vector->tx);
2124 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2125
08c8833b 2126 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2127
2128 switch (current_itr) {
2129 /* counts and packets in update_itr are dependent on these numbers */
2130 case lowest_latency:
d5bf4f67 2131 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2132 break;
2133 case low_latency:
d5bf4f67 2134 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2135 break;
2136 case bulk_latency:
d5bf4f67 2137 new_itr = IXGBE_8K_ITR;
f494e8fa 2138 break;
bd198058
AD		 2139 default:
2140 break;
f494e8fa
AV		 2141 }
2142
d5bf4f67 2143 if (new_itr != q_vector->itr) {
fe49f04a 2144 /* do an exponential smoothing */
d5bf4f67
ET		 2145 new_itr = (10 * new_itr * q_vector->itr) /
2146 ((9 * new_itr) + q_vector->itr);
509ee935 2147
bd198058 2148 /* save the algorithm value here */
5d967eb7 2149 q_vector->itr = new_itr;
fe49f04a
AD		 2150
2151 ixgbe_write_eitr(q_vector);
f494e8fa 2152 }
f494e8fa
AV		 2153}
2154
119fc60a 2155/**
de88eeeb 2156 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2157 * @adapter: pointer to adapter
119fc60a 2158 **/
f0f9778d 2159static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2160{
119fc60a
MC		 2161 struct ixgbe_hw *hw = &adapter->hw;
2162 u32 eicr = adapter->interrupt_event;
2163
f0f9778d 2164 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2165 return;
2166
f0f9778d
AD		 2167 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2168 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2169 return;
2170
2171 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2172
7ca647bd 2173 switch (hw->device_id) {
f0f9778d
AD		 2174 case IXGBE_DEV_ID_82599_T3_LOM:
2175 /*
2176 * Since the warning interrupt is for both ports
2177 * we don't have to check if:
2178 * - This interrupt wasn't for our port.
2179 * - We may have missed the interrupt so always have to
2180 * check if we got a LSC
2181 */
2182 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2183 !(eicr & IXGBE_EICR_LSC))
2184 return;
2185
2186 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2187 u32 autoneg;
2188 bool link_up = false;
7ca647bd 2189
7ca647bd
JP		 2190 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2191
f0f9778d
AD		 2192 if (link_up)
2193 return;
2194 }
2195
2196 /* Check if this is not due to overtemp */
2197 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2198 return;
2199
2200 break;
7ca647bd
JP		 2201 default:
2202 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2203 return;
7ca647bd 2204 break;
119fc60a 2205 }
7ca647bd
JP		 2206 e_crit(drv,
2207 "Network adapter has been stopped because it has over heated. "
2208 "Restart the computer. If the problem persists, "
2209 "power off the system and replace the adapter\n");
f0f9778d
AD		 2210
2211 adapter->interrupt_event = 0;
119fc60a
MC		 2212}
2213
0befdb3e
JB		 2214static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2215{
2216 struct ixgbe_hw *hw = &adapter->hw;
2217
2218 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2219 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2220 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2221 /* write to clear the interrupt */
2222 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2223 }
2224}
cf8280ee 2225
4f51bf70
JK		 2226static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2227{
2228 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2229 return;
2230
2231 switch (adapter->hw.mac.type) {
2232 case ixgbe_mac_82599EB:
2233 /*
2234 * Need to check link state so complete overtemp check
2235 * on service task
2236 */
2237 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2238 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2239 adapter->interrupt_event = eicr;
2240 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2241 ixgbe_service_event_schedule(adapter);
2242 return;
2243 }
2244 return;
2245 case ixgbe_mac_X540:
2246 if (!(eicr & IXGBE_EICR_TS))
2247 return;
2248 break;
2249 default:
2250 return;
2251 }
2252
2253 e_crit(drv,
2254 "Network adapter has been stopped because it has over heated. "
2255 "Restart the computer. If the problem persists, "
2256 "power off the system and replace the adapter\n");
2257}
2258
e8e26350
PW		 2259static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2260{
2261 struct ixgbe_hw *hw = &adapter->hw;
2262
73c4b7cd
AD		 2263 if (eicr & IXGBE_EICR_GPI_SDP2) {
2264 /* Clear the interrupt */
2265 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2266 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2267 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2268 ixgbe_service_event_schedule(adapter);
2269 }
73c4b7cd
AD		 2270 }
2271
e8e26350
PW		 2272 if (eicr & IXGBE_EICR_GPI_SDP1) {
2273 /* Clear the interrupt */
2274 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2275 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2276 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2277 ixgbe_service_event_schedule(adapter);
2278 }
e8e26350
PW		 2279 }
2280}
2281
cf8280ee
JB		 2282static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2283{
2284 struct ixgbe_hw *hw = &adapter->hw;
2285
2286 adapter->lsc_int++;
2287 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2288 adapter->link_check_timeout = jiffies;
2289 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2290 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2291 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2292 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2293 }
2294}
2295
fe49f04a
AD		 2296static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2297 u64 qmask)
2298{
2299 u32 mask;
bd508178 2300 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2301
bd508178
AD		 2302 switch (hw->mac.type) {
2303 case ixgbe_mac_82598EB:
fe49f04a 2304 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2305 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2306 break;
2307 case ixgbe_mac_82599EB:
b93a2226 2308 case ixgbe_mac_X540:
fe49f04a 2309 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2310 if (mask)
2311 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2312 mask = (qmask >> 32);
bd508178
AD		 2313 if (mask)
2314 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2315 break;
2316 default:
2317 break;
fe49f04a
AD		 2318 }
2319 /* skip the flush */
2320}
2321
2322static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2323 u64 qmask)
fe49f04a
AD		 2324{
2325 u32 mask;
bd508178 2326 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2327
bd508178
AD		 2328 switch (hw->mac.type) {
2329 case ixgbe_mac_82598EB:
fe49f04a 2330 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2331 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2332 break;
2333 case ixgbe_mac_82599EB:
b93a2226 2334 case ixgbe_mac_X540:
fe49f04a 2335 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2336 if (mask)
2337 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2338 mask = (qmask >> 32);
bd508178
AD		 2339 if (mask)
2340 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2341 break;
2342 default:
2343 break;
fe49f04a
AD		 2344 }
2345 /* skip the flush */
2346}
2347
021230d4 2348/**
2c4af694
AD		 2349 * ixgbe_irq_enable - Enable default interrupt generation settings
2350 * @adapter: board private structure
021230d4 2351 **/
2c4af694
AD		 2352static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2353 bool flush)
9a799d71 2354{
2c4af694 2355 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2356
2c4af694
AD		 2357 /* don't reenable LSC while waiting for link */
2358 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2359 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2360
2c4af694 2361 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2362 switch (adapter->hw.mac.type) {
2363 case ixgbe_mac_82599EB:
2364 mask |= IXGBE_EIMS_GPI_SDP0;
2365 break;
2366 case ixgbe_mac_X540:
2367 mask |= IXGBE_EIMS_TS;
2368 break;
2369 default:
2370 break;
2371 }
2c4af694
AD		 2372 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2373 mask |= IXGBE_EIMS_GPI_SDP1;
2374 switch (adapter->hw.mac.type) {
2375 case ixgbe_mac_82599EB:
2c4af694
AD		 2376 mask |= IXGBE_EIMS_GPI_SDP1;
2377 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2378 case ixgbe_mac_X540:
2379 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2380 mask |= IXGBE_EIMS_MAILBOX;
2381 break;
2382 default:
2383 break;
9a799d71 2384 }
db0677fa 2385
db0677fa
JK		 2386 if (adapter->hw.mac.type == ixgbe_mac_X540)
2387 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2388
2c4af694
AD		 2389 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2390 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2391 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2392
2c4af694
AD		 2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2394 if (queues)
2395 ixgbe_irq_enable_queues(adapter, ~0);
2396 if (flush)
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2398}
2399
2c4af694 2400static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2401{
a65151ba 2402 struct ixgbe_adapter *adapter = data;
9a799d71 2403 struct ixgbe_hw *hw = &adapter->hw;
54037505 2404 u32 eicr;
91281fd3 2405
54037505
DS		 2406 /*
2407 * Workaround for Silicon errata. Use clear-by-write instead
2408 * of clear-by-read. Reading with EICS will return the
2409 * interrupt causes without clearing, which later be done
2410 * with the write to EICR.
2411 */
2412 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2413 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2414
cf8280ee
JB		 2415 if (eicr & IXGBE_EICR_LSC)
2416 ixgbe_check_lsc(adapter);
f0848276 2417
1cdd1ec8
GR		 2418 if (eicr & IXGBE_EICR_MAILBOX)
2419 ixgbe_msg_task(adapter);
efe3d3c8 2420
bd508178
AD		 2421 switch (hw->mac.type) {
2422 case ixgbe_mac_82599EB:
b93a2226 2423 case ixgbe_mac_X540:
2c4af694
AD		 2424 if (eicr & IXGBE_EICR_ECC)
2425 e_info(link, "Received unrecoverable ECC Err, please "
2426 "reboot\n");
c4cf55e5
PWJ		 2427 /* Handle Flow Director Full threshold interrupt */
2428 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2429 int reinit_count = 0;
c4cf55e5 2430 int i;
c4cf55e5 2431 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2432 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2433 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2434 &ring->state))
2435 reinit_count++;
2436 }
2437 if (reinit_count) {
2438 /* no more flow director interrupts until after init */
2439 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2440 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2441 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2442 }
2443 }
f0f9778d 2444 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2445 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2446 break;
2447 default:
2448 break;
c4cf55e5 2449 }
f0848276 2450
bd508178 2451 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2452
db0677fa
JK		 2453 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2454 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2455
7086400d 2456 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2457 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2458 ixgbe_irq_enable(adapter, false, false);
f0848276 2459
9a799d71 2460 return IRQ_HANDLED;
f0848276 2461}
91281fd3 2462
4ff7fb12 2463static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2464{
021230d4 2465 struct ixgbe_q_vector *q_vector = data;
91281fd3 2466
9b471446 2467 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2468
4ff7fb12
AD		 2469 if (q_vector->rx.ring || q_vector->tx.ring)
2470 napi_schedule(&q_vector->napi);
91281fd3 2471
9a799d71 2472 return IRQ_HANDLED;
91281fd3
AD		 2473}
2474
eb01b975
AD		 2475/**
2476 * ixgbe_poll - NAPI Rx polling callback
2477 * @napi: structure for representing this polling device
2478 * @budget: how many packets driver is allowed to clean
2479 *
2480 * This function is used for legacy and MSI, NAPI mode
2481 **/
8af3c33f 2482int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2483{
2484 struct ixgbe_q_vector *q_vector =
2485 container_of(napi, struct ixgbe_q_vector, napi);
2486 struct ixgbe_adapter *adapter = q_vector->adapter;
2487 struct ixgbe_ring *ring;
2488 int per_ring_budget;
2489 bool clean_complete = true;
2490
2491#ifdef CONFIG_IXGBE_DCA
2492 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2493 ixgbe_update_dca(q_vector);
2494#endif
2495
2496 ixgbe_for_each_ring(ring, q_vector->tx)
2497 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2498
2499 /* attempt to distribute budget to each queue fairly, but don't allow
2500 * the budget to go below 1 because we'll exit polling */
2501 if (q_vector->rx.count > 1)
2502 per_ring_budget = max(budget/q_vector->rx.count, 1);
2503 else
2504 per_ring_budget = budget;
2505
2506 ixgbe_for_each_ring(ring, q_vector->rx)
2507 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2508 per_ring_budget);
2509
2510 /* If all work not completed, return budget and keep polling */
2511 if (!clean_complete)
2512 return budget;
2513
2514 /* all work done, exit the polling mode */
2515 napi_complete(napi);
2516 if (adapter->rx_itr_setting & 1)
2517 ixgbe_set_itr(q_vector);
2518 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2519 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2520
2521 return 0;
2522}
2523
021230d4
AV		 2524/**
2525 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2526 * @adapter: board private structure
2527 *
2528 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2529 * interrupts from the kernel.
2530 **/
2531static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2532{
2533 struct net_device *netdev = adapter->netdev;
207867f5 2534 int vector, err;
e8e9f696 2535 int ri = 0, ti = 0;
021230d4 2536
49c7ffbe 2537 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2538 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2539 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2540
4ff7fb12 2541 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2542 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2543 "%s-%s-%d", netdev->name, "TxRx", ri++);
2544 ti++;
2545 } else if (q_vector->rx.ring) {
9fe93afd 2546 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2547 "%s-%s-%d", netdev->name, "rx", ri++);
2548 } else if (q_vector->tx.ring) {
9fe93afd 2549 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2550 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2551 } else {
2552 /* skip this unused q_vector */
2553 continue;
32aa77a4 2554 }
207867f5
AD		 2555 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2556 q_vector->name, q_vector);
9a799d71 2557 if (err) {
396e799c 2558 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2559 "Error: %d\n", err);
021230d4 2560 goto free_queue_irqs;
9a799d71 2561 }
207867f5
AD		 2562 /* If Flow Director is enabled, set interrupt affinity */
2563 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2564 /* assign the mask for this irq */
2565 irq_set_affinity_hint(entry->vector,
de88eeeb 2566 &q_vector->affinity_mask);
207867f5 2567 }
9a799d71
AK		 2568 }
2569
021230d4 2570 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2571 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2572 if (err) {
de88eeeb 2573 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2574 goto free_queue_irqs;
9a799d71
AK		 2575 }
2576
9a799d71
AK		 2577 return 0;
2578
021230d4 2579free_queue_irqs:
207867f5
AD		 2580 while (vector) {
2581 vector--;
2582 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2583 NULL);
2584 free_irq(adapter->msix_entries[vector].vector,
2585 adapter->q_vector[vector]);
2586 }
021230d4
AV		 2587 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2588 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2589 kfree(adapter->msix_entries);
2590 adapter->msix_entries = NULL;
9a799d71
AK		 2591 return err;
2592}
2593
2594/**
021230d4 2595 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2596 * @irq: interrupt number
2597 * @data: pointer to a network interface device structure
9a799d71
AK		 2598 **/
2599static irqreturn_t ixgbe_intr(int irq, void *data)
2600{
a65151ba 2601 struct ixgbe_adapter *adapter = data;
9a799d71 2602 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2603 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2604 u32 eicr;
2605
54037505 2606 /*
24ddd967 2607 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2608 * before the read of EICR.
2609 */
2610 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2611
021230d4 2612 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2613 * therefore no explicit interrupt disable is necessary */
021230d4 2614 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2615 if (!eicr) {
6af3b9eb
ET		 2616 /*
2617 * shared interrupt alert!
f47cf66e 2618 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2619 * have disabled interrupts due to EIAM
2620 * finish the workaround of silicon errata on 82598. Unmask
2621 * the interrupt that we masked before the EICR read.
2622 */
2623 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2624 ixgbe_irq_enable(adapter, true, true);
9a799d71 2625 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2626 }
9a799d71 2627
cf8280ee
JB		 2628 if (eicr & IXGBE_EICR_LSC)
2629 ixgbe_check_lsc(adapter);
021230d4 2630
bd508178
AD		 2631 switch (hw->mac.type) {
2632 case ixgbe_mac_82599EB:
e8e26350 2633 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2634 /* Fall through */
2635 case ixgbe_mac_X540:
2636 if (eicr & IXGBE_EICR_ECC)
2637 e_info(link, "Received unrecoverable ECC err, please "
2638 "reboot\n");
4f51bf70 2639 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2640 break;
2641 default:
2642 break;
2643 }
e8e26350 2644
0befdb3e 2645 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2646 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2647 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2648
b9f6ed2b
AD		 2649 /* would disable interrupts here but EIAM disabled it */
2650 napi_schedule(&q_vector->napi);
9a799d71 2651
6af3b9eb
ET		 2652 /*
2653 * re-enable link(maybe) and non-queue interrupts, no flush.
2654 * ixgbe_poll will re-enable the queue interrupts
2655 */
6af3b9eb
ET		 2656 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2657 ixgbe_irq_enable(adapter, false, false);
2658
9a799d71
AK		 2659 return IRQ_HANDLED;
2660}
2661
2662/**
2663 * ixgbe_request_irq - initialize interrupts
2664 * @adapter: board private structure
2665 *
2666 * Attempts to configure interrupts using the best available
2667 * capabilities of the hardware and kernel.
2668 **/
021230d4 2669static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2670{
2671 struct net_device *netdev = adapter->netdev;
021230d4 2672 int err;
9a799d71 2673
4cc6df29 2674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2675 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2676 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2677 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2678 netdev->name, adapter);
4cc6df29 2679 else
a0607fd3 2680 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2681 netdev->name, adapter);
9a799d71 2682
de88eeeb 2683 if (err)
396e799c 2684 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2685
9a799d71
AK		 2686 return err;
2687}
2688
2689static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2690{
49c7ffbe 2691 int vector;
9a799d71 2692
49c7ffbe
AD		 2693 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2694 free_irq(adapter->pdev->irq, adapter);
2695 return;
2696 }
4cc6df29 2697
49c7ffbe
AD		 2698 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2699 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2700 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2701
49c7ffbe
AD		 2702 /* free only the irqs that were actually requested */
2703 if (!q_vector->rx.ring && !q_vector->tx.ring)
2704 continue;
207867f5 2705
49c7ffbe
AD		 2706 /* clear the affinity_mask in the IRQ descriptor */
2707 irq_set_affinity_hint(entry->vector, NULL);
2708
2709 free_irq(entry->vector, q_vector);
9a799d71 2710 }
49c7ffbe
AD		 2711
2712 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2713}
2714
22d5a71b
JB		 2715/**
2716 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2717 * @adapter: board private structure
2718 **/
2719static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2720{
bd508178
AD		 2721 switch (adapter->hw.mac.type) {
2722 case ixgbe_mac_82598EB:
835462fc 2723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2724 break;
2725 case ixgbe_mac_82599EB:
b93a2226 2726 case ixgbe_mac_X540:
835462fc
NS		 2727 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2729 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2730 break;
2731 default:
2732 break;
22d5a71b
JB		 2733 }
2734 IXGBE_WRITE_FLUSH(&adapter->hw);
2735 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2736 int vector;
2737
2738 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2739 synchronize_irq(adapter->msix_entries[vector].vector);
2740
2741 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2742 } else {
2743 synchronize_irq(adapter->pdev->irq);
2744 }
2745}
2746
9a799d71
AK		 2747/**
2748 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2749 *
2750 **/
2751static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2752{
d5bf4f67 2753 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2754
d5bf4f67 2755 ixgbe_write_eitr(q_vector);
9a799d71 2756
e8e26350
PW		 2757 ixgbe_set_ivar(adapter, 0, 0, 0);
2758 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2759
396e799c 2760 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2761}
2762
43e69bf0
AD		 2763/**
2764 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2765 * @adapter: board private structure
2766 * @ring: structure containing ring specific data
2767 *
2768 * Configure the Tx descriptor ring after a reset.
2769 **/
84418e3b
AD		 2770void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2771 struct ixgbe_ring *ring)
43e69bf0
AD		 2772{
2773 struct ixgbe_hw *hw = &adapter->hw;
2774 u64 tdba = ring->dma;
2f1860b8 2775 int wait_loop = 10;
b88c6de2 2776 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2777 u8 reg_idx = ring->reg_idx;
43e69bf0 2778
2f1860b8 2779 /* disable queue to avoid issues while updating state */
b88c6de2 2780 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2781 IXGBE_WRITE_FLUSH(hw);
2782
43e69bf0 2783 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2784 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2785 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2786 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2787 ring->count * sizeof(union ixgbe_adv_tx_desc));
2788 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2789 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2790 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2791
b88c6de2
AD		 2792 /*
2793 * set WTHRESH to encourage burst writeback, it should not be set
2794 * higher than 1 when ITR is 0 as it could cause false TX hangs
2795 *
2796 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2797 * to or less than the number of on chip descriptors, which is
2798 * currently 40.
2799 */
e954b374 2800 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2801 txdctl |= (1 << 16); /* WTHRESH = 1 */
2802 else
2803 txdctl |= (8 << 16); /* WTHRESH = 8 */
2804
e954b374
AD		 2805 /*
2806 * Setting PTHRESH to 32 both improves performance
2807 * and avoids a TX hang with DFP enabled
2808 */
b88c6de2
AD		 2809 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2810 32; /* PTHRESH = 32 */
2f1860b8
AD		 2811
2812 /* reinitialize flowdirector state */
39cb681b 2813 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2814 ring->atr_sample_rate = adapter->atr_sample_rate;
2815 ring->atr_count = 0;
2816 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2817 } else {
2818 ring->atr_sample_rate = 0;
2819 }
2f1860b8 2820
c84d324c
JF		 2821 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2822
2f1860b8 2823 /* enable queue */
2f1860b8
AD		 2824 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2825
2826 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2827 if (hw->mac.type == ixgbe_mac_82598EB &&
2828 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2829 return;
2830
2831 /* poll to verify queue is enabled */
2832 do {
032b4325 2833 usleep_range(1000, 2000);
2f1860b8
AD		 2834 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2835 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2836 if (!wait_loop)
2837 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2838}
2839
120ff942
AD		 2840static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2841{
2842 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2843 u32 rttdcs, mtqc;
8b1c0b24 2844 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2845
2846 if (hw->mac.type == ixgbe_mac_82598EB)
2847 return;
2848
2849 /* disable the arbiter while setting MTQC */
2850 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2851 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2852 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2853
2854 /* set transmit pool layout */
671c0adb
AD		 2855 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2856 mtqc = IXGBE_MTQC_VT_ENA;
2857 if (tcs > 4)
2858 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2859 else if (tcs > 1)
2860 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2861 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2862 mtqc |= IXGBE_MTQC_32VF;
2863 else
2864 mtqc |= IXGBE_MTQC_64VF;
2865 } else {
2866 if (tcs > 4)
2867 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2868 else if (tcs > 1)
2869 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2870 else
671c0adb
AD		 2871 mtqc = IXGBE_MTQC_64Q_1PB;
2872 }
120ff942 2873
671c0adb 2874 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2875
671c0adb
AD		 2876 /* Enable Security TX Buffer IFG for multiple pb */
2877 if (tcs) {
2878 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2879 sectx |= IXGBE_SECTX_DCB;
2880 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2881 }
2882
2883 /* re-enable the arbiter */
2884 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2885 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2886}
2887
9a799d71 2888/**
3a581073 2889 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2890 * @adapter: board private structure
2891 *
2892 * Configure the Tx unit of the MAC after a reset.
2893 **/
2894static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2895{
2f1860b8
AD		 2896 struct ixgbe_hw *hw = &adapter->hw;
2897 u32 dmatxctl;
43e69bf0 2898 u32 i;
9a799d71 2899
2f1860b8
AD		 2900 ixgbe_setup_mtqc(adapter);
2901
2902 if (hw->mac.type != ixgbe_mac_82598EB) {
2903 /* DMATXCTL.EN must be before Tx queues are enabled */
2904 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2905 dmatxctl |= IXGBE_DMATXCTL_TE;
2906 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2907 }
2908
9a799d71 2909 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2910 for (i = 0; i < adapter->num_tx_queues; i++)
2911 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2912}
2913
3ebe8fde
AD		 2914static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2915 struct ixgbe_ring *ring)
2916{
2917 struct ixgbe_hw *hw = &adapter->hw;
2918 u8 reg_idx = ring->reg_idx;
2919 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2920
2921 srrctl |= IXGBE_SRRCTL_DROP_EN;
2922
2923 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2924}
2925
2926static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2927 struct ixgbe_ring *ring)
2928{
2929 struct ixgbe_hw *hw = &adapter->hw;
2930 u8 reg_idx = ring->reg_idx;
2931 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2932
2933 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2934
2935 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2936}
2937
2938#ifdef CONFIG_IXGBE_DCB
2939void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2940#else
2941static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2942#endif
2943{
2944 int i;
2945 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2946
2947 if (adapter->ixgbe_ieee_pfc)
2948 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2949
2950 /*
2951 * We should set the drop enable bit if:
2952 * SR-IOV is enabled
2953 * or
2954 * Number of Rx queues > 1 and flow control is disabled
2955 *
2956 * This allows us to avoid head of line blocking for security
2957 * and performance reasons.
2958 */
2959 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2960 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2961 for (i = 0; i < adapter->num_rx_queues; i++)
2962 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2963 } else {
2964 for (i = 0; i < adapter->num_rx_queues; i++)
2965 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2966 }
2967}
2968
e8e26350 2969#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2970
a6616b42 2971static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2972 struct ixgbe_ring *rx_ring)
cc41ac7c 2973{
45e9baa5 2974 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2975 u32 srrctl;
bf29ee6c 2976 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2977
45e9baa5
AD		 2978 if (hw->mac.type == ixgbe_mac_82598EB) {
2979 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2980
45e9baa5
AD		 2981 /*
2982 * if VMDq is not active we must program one srrctl register
2983 * per RSS queue since we have enabled RDRXCTL.MVMEN
2984 */
2985 reg_idx &= mask;
2986 }
cc41ac7c 2987
45e9baa5
AD		 2988 /* configure header buffer length, needed for RSC */
2989 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2990
45e9baa5 2991 /* configure the packet buffer length */
f800326d 2992 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2993
2994 /* configure descriptor type */
f800326d 2995 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2996
45e9baa5 2997 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2998}
9a799d71 2999
05abb126 3000static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3001{
05abb126
AD		 3002 struct ixgbe_hw *hw = &adapter->hw;
3003 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3004 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3005 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3006 u32 mrqc = 0, reta = 0;
3007 u32 rxcsum;
3008 int i, j;
671c0adb
AD		 3009 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3010
671c0adb
AD		 3011 /*
3012 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3013 * make full use of any rings they may have. We will use the
3014 * PSRTYPE register to control how many rings we use within the PF.
3015 */
3016 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3017 rss_i = 2;
0cefafad 3018
05abb126
AD		 3019 /* Fill out hash function seeds */
3020 for (i = 0; i < 10; i++)
3021 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3022
3023 /* Fill out redirection table */
3024 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3025 if (j == rss_i)
05abb126
AD		 3026 j = 0;
3027 /* reta = 4-byte sliding window of
3028 * 0x00..(indices-1)(indices-1)00..etc. */
3029 reta = (reta << 8) | (j * 0x11);
3030 if ((i & 3) == 3)
3031 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3032 }
0cefafad 3033
05abb126
AD		 3034 /* Disable indicating checksum in descriptor, enables RSS hash */
3035 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3036 rxcsum |= IXGBE_RXCSUM_PCSD;
3037 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3038
671c0adb 3039 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3040 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3041 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3042 } else {
671c0adb
AD		 3043 u8 tcs = netdev_get_num_tc(adapter->netdev);
3044
3045 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3046 if (tcs > 4)
3047 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3048 else if (tcs > 1)
3049 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3050 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3051 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3052 else
671c0adb
AD		 3053 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3054 } else {
3055 if (tcs > 4)
8b1c0b24 3056 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3057 else if (tcs > 1)
3058 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3059 else
3060 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3061 }
0cefafad
JB		 3062 }
3063
05abb126 3064 /* Perform hash on these packet types */
671c0adb
AD		 3065 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3066 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3067 IXGBE_MRQC_RSS_FIELD_IPV6 |
3068 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3069
ef6afc0c
AD		 3070 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3071 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3072 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3073 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3074
05abb126 3075 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3076}
3077
bb5a9ad2
NS		 3078/**
3079 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3080 * @adapter: address of board private structure
3081 * @index: index of ring to set
bb5a9ad2 3082 **/
082757af 3083static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3084 struct ixgbe_ring *ring)
bb5a9ad2 3085{
bb5a9ad2 3086 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3087 u32 rscctrl;
bf29ee6c 3088 u8 reg_idx = ring->reg_idx;
7367096a 3089
7d637bcc 3090 if (!ring_is_rsc_enabled(ring))
7367096a 3091 return;
bb5a9ad2 3092
7367096a 3093 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3094 rscctrl |= IXGBE_RSCCTL_RSCEN;
3095 /*
3096 * we must limit the number of descriptors so that the
3097 * total size of max desc * buf_len is not greater
642c680e 3098 * than 65536
bb5a9ad2 3099 */
f800326d 3100 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3101 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3102}
3103
9e10e045
AD		 3104#define IXGBE_MAX_RX_DESC_POLL 10
3105static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3106 struct ixgbe_ring *ring)
3107{
3108 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3109 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3110 u32 rxdctl;
bf29ee6c 3111 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3112
3113 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3114 if (hw->mac.type == ixgbe_mac_82598EB &&
3115 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3116 return;
3117
3118 do {
032b4325 3119 usleep_range(1000, 2000);
9e10e045
AD		 3120 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3121 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3122
3123 if (!wait_loop) {
3124 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3125 "the polling period\n", reg_idx);
3126 }
3127}
3128
2d39d576
YZ		 3129void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3130 struct ixgbe_ring *ring)
3131{
3132 struct ixgbe_hw *hw = &adapter->hw;
3133 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3134 u32 rxdctl;
3135 u8 reg_idx = ring->reg_idx;
3136
3137 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3138 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3139
3140 /* write value back with RXDCTL.ENABLE bit cleared */
3141 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3142
3143 if (hw->mac.type == ixgbe_mac_82598EB &&
3144 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3145 return;
3146
3147 /* the hardware may take up to 100us to really disable the rx queue */
3148 do {
3149 udelay(10);
3150 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3151 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3152
3153 if (!wait_loop) {
3154 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3155 "the polling period\n", reg_idx);
3156 }
3157}
3158
84418e3b
AD		 3159void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3160 struct ixgbe_ring *ring)
acd37177
AD		 3161{
3162 struct ixgbe_hw *hw = &adapter->hw;
3163 u64 rdba = ring->dma;
9e10e045 3164 u32 rxdctl;
bf29ee6c 3165 u8 reg_idx = ring->reg_idx;
acd37177 3166
9e10e045
AD		 3167 /* disable queue to avoid issues while updating state */
3168 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3169 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3170
acd37177
AD		 3171 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3172 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3173 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3174 ring->count * sizeof(union ixgbe_adv_rx_desc));
3175 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3176 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3177 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3178
3179 ixgbe_configure_srrctl(adapter, ring);
3180 ixgbe_configure_rscctl(adapter, ring);
3181
3182 if (hw->mac.type == ixgbe_mac_82598EB) {
3183 /*
3184 * enable cache line friendly hardware writes:
3185 * PTHRESH=32 descriptors (half the internal cache),
3186 * this also removes ugly rx_no_buffer_count increment
3187 * HTHRESH=4 descriptors (to minimize latency on fetch)
3188 * WTHRESH=8 burst writeback up to two cache lines
3189 */
3190 rxdctl &= ~0x3FFFFF;
3191 rxdctl |= 0x080420;
3192 }
3193
3194 /* enable receive descriptor ring */
3195 rxdctl |= IXGBE_RXDCTL_ENABLE;
3196 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3197
3198 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3199 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3200}
3201
48654521
AD		 3202static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3203{
3204 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3205 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3206 int p;
3207
3208 /* PSRTYPE must be initialized in non 82598 adapters */
3209 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3210 IXGBE_PSRTYPE_UDPHDR |
3211 IXGBE_PSRTYPE_IPV4HDR |
48654521 3212 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3213 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3214
3215 if (hw->mac.type == ixgbe_mac_82598EB)
3216 return;
3217
fbe7ca7f
AD		 3218 if (rss_i > 3)
3219 psrtype |= 2 << 29;
3220 else if (rss_i > 1)
3221 psrtype |= 1 << 29;
48654521
AD		 3222
3223 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3224 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3225 psrtype);
3226}
3227
f5b4a52e
AD		 3228static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3229{
3230 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3231 u32 reg_offset, vf_shift;
435b19f6 3232 u32 gcr_ext, vmdctl;
de4c7f65 3233 int i;
f5b4a52e
AD		 3234
3235 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3236 return;
3237
3238 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3239 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3240 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3241 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3242 vmdctl |= IXGBE_VT_CTL_REPLEN;
3243 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3244
1d9c0bfd
AD		 3245 vf_shift = VMDQ_P(0) % 32;
3246 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3247
3248 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3249 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3250 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3251 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3252 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3253 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3254 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3255
3256 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3257 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3258
3259 /*
3260 * Set up VF register offsets for selected VT Mode,
3261 * i.e. 32 or 64 VFs for SR-IOV
3262 */
73079ea0
AD		 3263 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3264 case IXGBE_82599_VMDQ_8Q_MASK:
3265 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3266 break;
3267 case IXGBE_82599_VMDQ_4Q_MASK:
3268 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3269 break;
3270 default:
3271 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3272 break;
3273 }
3274
f5b4a52e
AD		 3275 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3276
435b19f6 3277
a985b6c3 3278 /* Enable MAC Anti-Spoofing */
435b19f6 3279 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3280 adapter->num_vfs);
de4c7f65
GR		 3281 /* For VFs that have spoof checking turned off */
3282 for (i = 0; i < adapter->num_vfs; i++) {
3283 if (!adapter->vfinfo[i].spoofchk_enabled)
3284 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3285 }
f5b4a52e
AD		 3286}
3287
477de6ed 3288static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3289{
9a799d71
AK		 3290 struct ixgbe_hw *hw = &adapter->hw;
3291 struct net_device *netdev = adapter->netdev;
3292 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3293 struct ixgbe_ring *rx_ring;
3294 int i;
3295 u32 mhadd, hlreg0;
48654521 3296
63f39bd1 3297#ifdef IXGBE_FCOE
477de6ed
AD		 3298 /* adjust max frame to be able to do baby jumbo for FCoE */
3299 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3300 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3301 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3302
477de6ed 3303#endif /* IXGBE_FCOE */
872844dd
AD		 3304
3305 /* adjust max frame to be at least the size of a standard frame */
3306 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3307 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3308
477de6ed
AD		 3309 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3310 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3311 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3312 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3313
3314 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3315 }
3316
3317 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3318 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3319 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3320 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3321
0cefafad
JB		 3322 /*
3323 * Setup the HW Rx Head and Tail Descriptor Pointers and
3324 * the Base and Length of the Rx Descriptor Ring
3325 */
9a799d71 3326 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3327 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3328 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3329 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3330 else
7d637bcc 3331 clear_ring_rsc_enabled(rx_ring);
477de6ed 3332 }
477de6ed
AD		 3333}
3334
7367096a
AD		 3335static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3336{
3337 struct ixgbe_hw *hw = &adapter->hw;
3338 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3339
3340 switch (hw->mac.type) {
3341 case ixgbe_mac_82598EB:
3342 /*
3343 * For VMDq support of different descriptor types or
3344 * buffer sizes through the use of multiple SRRCTL
3345 * registers, RDRXCTL.MVMEN must be set to 1
3346 *
3347 * also, the manual doesn't mention it clearly but DCA hints
3348 * will only use queue 0's tags unless this bit is set. Side
3349 * effects of setting this bit are only that SRRCTL must be
3350 * fully programmed [0..15]
3351 */
3352 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3353 break;
3354 case ixgbe_mac_82599EB:
b93a2226 3355 case ixgbe_mac_X540:
7367096a
AD		 3356 /* Disable RSC for ACK packets */
3357 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3358 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3359 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3360 /* hardware requires some bits to be set by default */
3361 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3362 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3363 break;
3364 default:
3365 /* We should do nothing since we don't know this hardware */
3366 return;
3367 }
3368
3369 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3370}
3371
477de6ed
AD		 3372/**
3373 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3374 * @adapter: board private structure
3375 *
3376 * Configure the Rx unit of the MAC after a reset.
3377 **/
3378static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3379{
3380 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3381 int i;
3382 u32 rxctrl;
477de6ed
AD		 3383
3384 /* disable receives while setting up the descriptors */
3385 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3386 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3387
3388 ixgbe_setup_psrtype(adapter);
7367096a 3389 ixgbe_setup_rdrxctl(adapter);
477de6ed 3390
9e10e045 3391 /* Program registers for the distribution of queues */
f5b4a52e 3392 ixgbe_setup_mrqc(adapter);
f5b4a52e 3393
477de6ed
AD		 3394 /* set_rx_buffer_len must be called before ring initialization */
3395 ixgbe_set_rx_buffer_len(adapter);
3396
3397 /*
3398 * Setup the HW Rx Head and Tail Descriptor Pointers and
3399 * the Base and Length of the Rx Descriptor Ring
3400 */
9e10e045
AD		 3401 for (i = 0; i < adapter->num_rx_queues; i++)
3402 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3403
9e10e045
AD		 3404 /* disable drop enable for 82598 parts */
3405 if (hw->mac.type == ixgbe_mac_82598EB)
3406 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3407
3408 /* enable all receives */
3409 rxctrl |= IXGBE_RXCTRL_RXEN;
3410 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3411}
3412
8e586137 3413static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3414{
3415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3416 struct ixgbe_hw *hw = &adapter->hw;
3417
3418 /* add VID to filter table */
1d9c0bfd 3419 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3420 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3421
3422 return 0;
068c89b0
DS		 3423}
3424
8e586137 3425static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3426{
3427 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3428 struct ixgbe_hw *hw = &adapter->hw;
3429
068c89b0 3430 /* remove VID from filter table */
1d9c0bfd 3431 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3432 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3433
3434 return 0;
068c89b0
DS		 3435}
3436
5f6c0181
JB		 3437/**
3438 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3439 * @adapter: driver data
3440 */
3441static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3442{
3443 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3444 u32 vlnctrl;
3445
3446 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3447 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3448 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3449}
3450
3451/**
3452 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3453 * @adapter: driver data
3454 */
3455static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3456{
3457 struct ixgbe_hw *hw = &adapter->hw;
3458 u32 vlnctrl;
3459
3460 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3461 vlnctrl |= IXGBE_VLNCTRL_VFE;
3462 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3463 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3464}
3465
3466/**
3467 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3468 * @adapter: driver data
3469 */
3470static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3471{
3472 struct ixgbe_hw *hw = &adapter->hw;
3473 u32 vlnctrl;
5f6c0181
JB		 3474 int i, j;
3475
3476 switch (hw->mac.type) {
3477 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3478 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3479 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3480 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3481 break;
3482 case ixgbe_mac_82599EB:
b93a2226 3483 case ixgbe_mac_X540:
5f6c0181
JB		 3484 for (i = 0; i < adapter->num_rx_queues; i++) {
3485 j = adapter->rx_ring[i]->reg_idx;
3486 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3487 vlnctrl &= ~IXGBE_RXDCTL_VME;
3488 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3489 }
3490 break;
3491 default:
3492 break;
3493 }
3494}
3495
3496/**
f62bbb5e 3497 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3498 * @adapter: driver data
3499 */
f62bbb5e 3500static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3501{
3502 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3503 u32 vlnctrl;
5f6c0181
JB		 3504 int i, j;
3505
3506 switch (hw->mac.type) {
3507 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3508 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3509 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3510 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3511 break;
3512 case ixgbe_mac_82599EB:
b93a2226 3513 case ixgbe_mac_X540:
5f6c0181
JB		 3514 for (i = 0; i < adapter->num_rx_queues; i++) {
3515 j = adapter->rx_ring[i]->reg_idx;
3516 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3517 vlnctrl |= IXGBE_RXDCTL_VME;
3518 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3519 }
3520 break;
3521 default:
3522 break;
3523 }
3524}
3525
9a799d71
AK		 3526static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3527{
f62bbb5e 3528 u16 vid;
9a799d71 3529
f62bbb5e
JG		 3530 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3531
3532 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3533 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3534}
3535
2850062a
AD		 3536/**
3537 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3538 * @netdev: network interface device structure
3539 *
3540 * Writes unicast address list to the RAR table.
3541 * Returns: -ENOMEM on failure/insufficient address space
3542 * 0 on no addresses written
3543 * X on writing X addresses to the RAR table
3544 **/
3545static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3546{
3547 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3548 struct ixgbe_hw *hw = &adapter->hw;
95447461 3549 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3550 int count = 0;
3551
95447461
JF		 3552 /* In SR-IOV mode significantly less RAR entries are available */
3553 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3554 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3555
2850062a
AD		 3556 /* return ENOMEM indicating insufficient memory for addresses */
3557 if (netdev_uc_count(netdev) > rar_entries)
3558 return -ENOMEM;
3559
95447461 3560 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3561 struct netdev_hw_addr *ha;
3562 /* return error if we do not support writing to RAR table */
3563 if (!hw->mac.ops.set_rar)
3564 return -ENOMEM;
3565
3566 netdev_for_each_uc_addr(ha, netdev) {
3567 if (!rar_entries)
3568 break;
3569 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3570 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3571 count++;
3572 }
3573 }
3574 /* write the addresses in reverse order to avoid write combining */
3575 for (; rar_entries > 0 ; rar_entries--)
3576 hw->mac.ops.clear_rar(hw, rar_entries);
3577
3578 return count;
3579}
3580
9a799d71 3581/**
2c5645cf 3582 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3583 * @netdev: network interface device structure
3584 *
2c5645cf
CL		 3585 * The set_rx_method entry point is called whenever the unicast/multicast
3586 * address list or the network interface flags are updated. This routine is
3587 * responsible for configuring the hardware for proper unicast, multicast and
3588 * promiscuous mode.
9a799d71 3589 **/
7f870475 3590void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3591{
3592 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3593 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3594 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3595 int count;
9a799d71
AK		 3596
3597 /* Check for Promiscuous and All Multicast modes */
3598
3599 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3600
f5dc442b 3601 /* set all bits that we expect to always be set */
3f2d1c0f 3602 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3603 fctrl |= IXGBE_FCTRL_BAM;
3604 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3605 fctrl |= IXGBE_FCTRL_PMCF;
3606
2850062a
AD		 3607 /* clear the bits we are changing the status of */
3608 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3609
9a799d71 3610 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3611 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3612 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3613 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3614 /* don't hardware filter vlans in promisc mode */
3615 ixgbe_vlan_filter_disable(adapter);
9a799d71 3616 } else {
746b9f02
PM		 3617 if (netdev->flags & IFF_ALLMULTI) {
3618 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3619 vmolr |= IXGBE_VMOLR_MPE;
3620 } else {
3621 /*
3622 * Write addresses to the MTA, if the attempt fails
25985edc 3623 * then we should just turn on promiscuous mode so
2850062a
AD		 3624 * that we can at least receive multicast traffic
3625 */
3626 hw->mac.ops.update_mc_addr_list(hw, netdev);
3627 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3628 }
5f6c0181 3629 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3630 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3631 }
3632
3633 /*
3634 * Write addresses to available RAR registers, if there is not
3635 * sufficient space to store all the addresses then enable
3636 * unicast promiscuous mode
3637 */
3638 count = ixgbe_write_uc_addr_list(netdev);
3639 if (count < 0) {
3640 fctrl |= IXGBE_FCTRL_UPE;
3641 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3642 }
3643
1d9c0bfd 3644 if (adapter->num_vfs)
1cdd1ec8 3645 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3646
3647 if (hw->mac.type != ixgbe_mac_82598EB) {
3648 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3649 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3650 IXGBE_VMOLR_ROPE);
1d9c0bfd 3651 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3652 }
3653
3f2d1c0f
BG		 3654 /* This is useful for sniffing bad packets. */
3655 if (adapter->netdev->features & NETIF_F_RXALL) {
3656 /* UPE and MPE will be handled by normal PROMISC logic
3657 * in e1000e_set_rx_mode */
3658 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3659 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3660 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3661
3662 fctrl &= ~(IXGBE_FCTRL_DPF);
3663 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3664 }
3665
2850062a 3666 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3667
3668 if (netdev->features & NETIF_F_HW_VLAN_RX)
3669 ixgbe_vlan_strip_enable(adapter);
3670 else
3671 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3672}
3673
021230d4
AV		 3674static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3675{
3676 int q_idx;
021230d4 3677
49c7ffbe
AD		 3678 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3679 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3680}
3681
3682static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3683{
3684 int q_idx;
021230d4 3685
49c7ffbe
AD		 3686 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3687 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3688}
3689
7a6b6f51 3690#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3691/**
2f90b865
AD		 3692 * ixgbe_configure_dcb - Configure DCB hardware
3693 * @adapter: ixgbe adapter struct
3694 *
3695 * This is called by the driver on open to configure the DCB hardware.
3696 * This is also called by the gennetlink interface when reconfiguring
3697 * the DCB state.
3698 */
3699static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3700{
3701 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3702 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3703
67ebd791
AD		 3704 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3705 if (hw->mac.type == ixgbe_mac_82598EB)
3706 netif_set_gso_max_size(adapter->netdev, 65536);
3707 return;
3708 }
3709
3710 if (hw->mac.type == ixgbe_mac_82598EB)
3711 netif_set_gso_max_size(adapter->netdev, 32768);
3712
971060b1 3713#ifdef IXGBE_FCOE
b120818e
JF		 3714 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3715 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3716#endif
b120818e
JF		 3717
3718 /* reconfigure the hardware */
3719 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3720 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3721 DCB_TX_CONFIG);
3722 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3723 DCB_RX_CONFIG);
3724 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3725 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3726 ixgbe_dcb_hw_ets(&adapter->hw,
3727 adapter->ixgbe_ieee_ets,
3728 max_frame);
3729 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3730 adapter->ixgbe_ieee_pfc->pfc_en,
3731 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3732 }
8187cd48
JF		 3733
3734 /* Enable RSS Hash per TC */
3735 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3736 u32 msb = 0;
3737 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3738
d411a936
AD		 3739 while (rss_i) {
3740 msb++;
3741 rss_i >>= 1;
3742 }
8187cd48 3743
4ae63730
AD		 3744 /* write msb to all 8 TCs in one write */
3745 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3746 }
2f90b865 3747}
9da712d2
JF		 3748#endif
3749
3750/* Additional bittime to account for IXGBE framing */
3751#define IXGBE_ETH_FRAMING 20
3752
49ce9c2c 3753/**
9da712d2
JF		 3754 * ixgbe_hpbthresh - calculate high water mark for flow control
3755 *
3756 * @adapter: board private structure to calculate for
49ce9c2c 3757 * @pb: packet buffer to calculate
9da712d2
JF		 3758 */
3759static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3760{
3761 struct ixgbe_hw *hw = &adapter->hw;
3762 struct net_device *dev = adapter->netdev;
3763 int link, tc, kb, marker;
3764 u32 dv_id, rx_pba;
3765
3766 /* Calculate max LAN frame size */
3767 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3768
3769#ifdef IXGBE_FCOE
3770 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3771 if ((dev->features & NETIF_F_FCOE_MTU) &&
3772 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3773 (pb == ixgbe_fcoe_get_tc(adapter)))
3774 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3775
3776#endif
9da712d2
JF		 3777 /* Calculate delay value for device */
3778 switch (hw->mac.type) {
3779 case ixgbe_mac_X540:
3780 dv_id = IXGBE_DV_X540(link, tc);
3781 break;
3782 default:
3783 dv_id = IXGBE_DV(link, tc);
3784 break;
3785 }
3786
3787 /* Loopback switch introduces additional latency */
3788 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3789 dv_id += IXGBE_B2BT(tc);
3790
3791 /* Delay value is calculated in bit times convert to KB */
3792 kb = IXGBE_BT2KB(dv_id);
3793 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3794
3795 marker = rx_pba - kb;
3796
3797 /* It is possible that the packet buffer is not large enough
3798 * to provide required headroom. In this case throw an error
3799 * to user and a do the best we can.
3800 */
3801 if (marker < 0) {
3802 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3803 "headroom to support flow control."
3804 "Decrease MTU or number of traffic classes\n", pb);
3805 marker = tc + 1;
3806 }
3807
3808 return marker;
3809}
3810
49ce9c2c 3811/**
9da712d2
JF		 3812 * ixgbe_lpbthresh - calculate low water mark for for flow control
3813 *
3814 * @adapter: board private structure to calculate for
49ce9c2c 3815 * @pb: packet buffer to calculate
9da712d2
JF		 3816 */
3817static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3818{
3819 struct ixgbe_hw *hw = &adapter->hw;
3820 struct net_device *dev = adapter->netdev;
3821 int tc;
3822 u32 dv_id;
3823
3824 /* Calculate max LAN frame size */
3825 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3826
3827 /* Calculate delay value for device */
3828 switch (hw->mac.type) {
3829 case ixgbe_mac_X540:
3830 dv_id = IXGBE_LOW_DV_X540(tc);
3831 break;
3832 default:
3833 dv_id = IXGBE_LOW_DV(tc);
3834 break;
3835 }
3836
3837 /* Delay value is calculated in bit times convert to KB */
3838 return IXGBE_BT2KB(dv_id);
3839}
3840
3841/*
3842 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3843 */
3844static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3845{
3846 struct ixgbe_hw *hw = &adapter->hw;
3847 int num_tc = netdev_get_num_tc(adapter->netdev);
3848 int i;
3849
3850 if (!num_tc)
3851 num_tc = 1;
3852
3853 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3854
3855 for (i = 0; i < num_tc; i++) {
3856 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3857
3858 /* Low water marks must not be larger than high water marks */
3859 if (hw->fc.low_water > hw->fc.high_water[i])
3860 hw->fc.low_water = 0;
3861 }
3862}
3863
80605c65
JF		 3864static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3865{
80605c65 3866 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3867 int hdrm;
3868 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3869
3870 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3871 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3872 hdrm = 32 << adapter->fdir_pballoc;
3873 else
3874 hdrm = 0;
80605c65 3875
f7e1027f 3876 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3877 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3878}
3879
e4911d57
AD		 3880static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3881{
3882 struct ixgbe_hw *hw = &adapter->hw;
3883 struct hlist_node *node, *node2;
3884 struct ixgbe_fdir_filter *filter;
3885
3886 spin_lock(&adapter->fdir_perfect_lock);
3887
3888 if (!hlist_empty(&adapter->fdir_filter_list))
3889 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3890
3891 hlist_for_each_entry_safe(filter, node, node2,
3892 &adapter->fdir_filter_list, fdir_node) {
3893 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3894 &filter->filter,
3895 filter->sw_idx,
3896 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3897 IXGBE_FDIR_DROP_QUEUE :
3898 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3899 }
3900
3901 spin_unlock(&adapter->fdir_perfect_lock);
3902}
3903
9a799d71
AK		 3904static void ixgbe_configure(struct ixgbe_adapter *adapter)
3905{
d2f5e7f3
AS		 3906 struct ixgbe_hw *hw = &adapter->hw;
3907
80605c65 3908 ixgbe_configure_pb(adapter);
7a6b6f51 3909#ifdef CONFIG_IXGBE_DCB
67ebd791 3910 ixgbe_configure_dcb(adapter);
2f90b865 3911#endif
b35d4d42
AD		 3912 /*
3913 * We must restore virtualization before VLANs or else
3914 * the VLVF registers will not be populated
3915 */
3916 ixgbe_configure_virtualization(adapter);
9a799d71 3917
4c1d7b4b 3918 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3919 ixgbe_restore_vlan(adapter);
3920
d2f5e7f3
AS		 3921 switch (hw->mac.type) {
3922 case ixgbe_mac_82599EB:
3923 case ixgbe_mac_X540:
3924 hw->mac.ops.disable_rx_buff(hw);
3925 break;
3926 default:
3927 break;
3928 }
3929
c4cf55e5 3930 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3931 ixgbe_init_fdir_signature_82599(&adapter->hw,
3932 adapter->fdir_pballoc);
e4911d57
AD		 3933 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3934 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3935 adapter->fdir_pballoc);
3936 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3937 }
4c1d7b4b 3938
d2f5e7f3
AS		 3939 switch (hw->mac.type) {
3940 case ixgbe_mac_82599EB:
3941 case ixgbe_mac_X540:
3942 hw->mac.ops.enable_rx_buff(hw);
3943 break;
3944 default:
3945 break;
3946 }
3947
7c8ae65a
AD		 3948#ifdef IXGBE_FCOE
3949 /* configure FCoE L2 filters, redirection table, and Rx control */
3950 ixgbe_configure_fcoe(adapter);
3951
3952#endif /* IXGBE_FCOE */
9a799d71
AK		 3953 ixgbe_configure_tx(adapter);
3954 ixgbe_configure_rx(adapter);
9a799d71
AK		 3955}
3956
e8e26350
PW		 3957static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3958{
3959 switch (hw->phy.type) {
3960 case ixgbe_phy_sfp_avago:
3961 case ixgbe_phy_sfp_ftl:
3962 case ixgbe_phy_sfp_intel:
3963 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3964 case ixgbe_phy_sfp_passive_tyco:
3965 case ixgbe_phy_sfp_passive_unknown:
3966 case ixgbe_phy_sfp_active_unknown:
3967 case ixgbe_phy_sfp_ftl_active:
e8e26350 3968 return true;
8917b447
AD		 3969 case ixgbe_phy_nl:
3970 if (hw->mac.type == ixgbe_mac_82598EB)
3971 return true;
e8e26350
PW		 3972 default:
3973 return false;
3974 }
3975}
3976
0ecc061d 3977/**
e8e26350
PW		 3978 * ixgbe_sfp_link_config - set up SFP+ link
3979 * @adapter: pointer to private adapter struct
3980 **/
3981static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3982{
7086400d 3983 /*
52f33af8 3984 * We are assuming the worst case scenario here, and that
7086400d
AD		 3985 * is that an SFP was inserted/removed after the reset
3986 * but before SFP detection was enabled. As such the best
3987 * solution is to just start searching as soon as we start
3988 */
3989 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3990 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3991
7086400d 3992 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3993}
3994
3995/**
3996 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3997 * @hw: pointer to private hardware struct
3998 *
3999 * Returns 0 on success, negative on failure
4000 **/
e8e26350 4001static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 4002{
4003 u32 autoneg;
8620a103 4004 bool negotiation, link_up = false;
0ecc061d
PWJ		 4005 u32 ret = IXGBE_ERR_LINK_SETUP;
4006
4007 if (hw->mac.ops.check_link)
4008 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
4009
4010 if (ret)
4011 goto link_cfg_out;
4012
0b0c2b31
ET		 4013 autoneg = hw->phy.autoneg_advertised;
4014 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 4015 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4016 &negotiation);
0ecc061d
PWJ		 4017 if (ret)
4018 goto link_cfg_out;
4019
8620a103
MC		 4020 if (hw->mac.ops.setup_link)
4021 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 4022link_cfg_out:
4023 return ret;
4024}
4025
a34bcfff 4026static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4027{
9a799d71 4028 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4029 u32 gpie = 0;
9a799d71 4030
9b471446 4031 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4032 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4033 IXGBE_GPIE_OCD;
4034 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4035 /*
4036 * use EIAM to auto-mask when MSI-X interrupt is asserted
4037 * this saves a register write for every interrupt
4038 */
4039 switch (hw->mac.type) {
4040 case ixgbe_mac_82598EB:
4041 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4042 break;
9b471446 4043 case ixgbe_mac_82599EB:
b93a2226
DS		 4044 case ixgbe_mac_X540:
4045 default:
9b471446
JB		 4046 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4047 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4048 break;
4049 }
4050 } else {
021230d4
AV		 4051 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4052 * specifically only auto mask tx and rx interrupts */
4053 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4054 }
9a799d71 4055
a34bcfff
AD		 4056 /* XXX: to interrupt immediately for EICS writes, enable this */
4057 /* gpie |= IXGBE_GPIE_EIMEN; */
4058
4059 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4060 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4061
4062 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4063 case IXGBE_82599_VMDQ_8Q_MASK:
4064 gpie |= IXGBE_GPIE_VTMODE_16;
4065 break;
4066 case IXGBE_82599_VMDQ_4Q_MASK:
4067 gpie |= IXGBE_GPIE_VTMODE_32;
4068 break;
4069 default:
4070 gpie |= IXGBE_GPIE_VTMODE_64;
4071 break;
4072 }
119fc60a
MC		 4073 }
4074
5fdd31f9 4075 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4076 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4077 switch (adapter->hw.mac.type) {
4078 case ixgbe_mac_82599EB:
4079 gpie |= IXGBE_SDP0_GPIEN;
4080 break;
4081 case ixgbe_mac_X540:
4082 gpie |= IXGBE_EIMS_TS;
4083 break;
4084 default:
4085 break;
4086 }
4087 }
5fdd31f9 4088
a34bcfff
AD		 4089 /* Enable fan failure interrupt */
4090 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4091 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4092
2698b208 4093 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4094 gpie |= IXGBE_SDP1_GPIEN;
4095 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4096 }
a34bcfff
AD		 4097
4098 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4099}
4100
c7ccde0f 4101static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4102{
4103 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4104 int err;
a34bcfff
AD		 4105 u32 ctrl_ext;
4106
4107 ixgbe_get_hw_control(adapter);
4108 ixgbe_setup_gpie(adapter);
e8e26350 4109
9a799d71
AK		 4110 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4111 ixgbe_configure_msix(adapter);
4112 else
4113 ixgbe_configure_msi_and_legacy(adapter);
4114
ec74a471
ET		 4115 /* enable the optics for 82599 SFP+ fiber */
4116 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4117 hw->mac.ops.enable_tx_laser(hw);
4118
9a799d71 4119 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4120 ixgbe_napi_enable_all(adapter);
4121
73c4b7cd
AD		 4122 if (ixgbe_is_sfp(hw)) {
4123 ixgbe_sfp_link_config(adapter);
4124 } else {
4125 err = ixgbe_non_sfp_link_config(hw);
4126 if (err)
4127 e_err(probe, "link_config FAILED %d\n", err);
4128 }
4129
021230d4
AV		 4130 /* clear any pending interrupts, may auto mask */
4131 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4132 ixgbe_irq_enable(adapter, true, true);
9a799d71 4133
bf069c97
DS		 4134 /*
4135 * If this adapter has a fan, check to see if we had a failure
4136 * before we enabled the interrupt.
4137 */
4138 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4139 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4140 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4141 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4142 }
4143
1da100bb 4144 /* enable transmits */
477de6ed 4145 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4146
9a799d71
AK		 4147 /* bring the link up in the watchdog, this could race with our first
4148 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4149 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4150 adapter->link_check_timeout = jiffies;
7086400d 4151 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4152
4153 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4154 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4155 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4156 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4157}
4158
d4f80882
AV		 4159void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4160{
4161 WARN_ON(in_interrupt());
7086400d
AD		 4162 /* put off any impending NetWatchDogTimeout */
4163 adapter->netdev->trans_start = jiffies;
4164
d4f80882 4165 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4166 usleep_range(1000, 2000);
d4f80882 4167 ixgbe_down(adapter);
5809a1ae
GR		 4168 /*
4169 * If SR-IOV enabled then wait a bit before bringing the adapter
4170 * back up to give the VFs time to respond to the reset. The
4171 * two second wait is based upon the watchdog timer cycle in
4172 * the VF driver.
4173 */
4174 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4175 msleep(2000);
d4f80882
AV		 4176 ixgbe_up(adapter);
4177 clear_bit(__IXGBE_RESETTING, &adapter->state);
4178}
4179
c7ccde0f 4180void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4181{
4182 /* hardware has been reset, we need to reload some things */
4183 ixgbe_configure(adapter);
4184
c7ccde0f 4185 ixgbe_up_complete(adapter);
9a799d71
AK		 4186}
4187
4188void ixgbe_reset(struct ixgbe_adapter *adapter)
4189{
c44ade9e 4190 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4191 int err;
4192
7086400d
AD		 4193 /* lock SFP init bit to prevent race conditions with the watchdog */
4194 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4195 usleep_range(1000, 2000);
4196
4197 /* clear all SFP and link config related flags while holding SFP_INIT */
4198 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4199 IXGBE_FLAG2_SFP_NEEDS_RESET);
4200 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4201
8ca783ab 4202 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4203 switch (err) {
4204 case 0:
4205 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4206 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4207 break;
4208 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4209 e_dev_err("master disable timed out\n");
da4dd0f7 4210 break;
794caeb2
PWJ		 4211 case IXGBE_ERR_EEPROM_VERSION:
4212 /* We are running on a pre-production device, log a warning */
849c4542 4213 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4214 "Please be aware there may be issues associated with "
849c4542
ET		 4215 "your hardware. If you are experiencing problems "
4216 "please contact your Intel or hardware "
4217 "representative who provided you with this "
4218 "hardware.\n");
794caeb2 4219 break;
da4dd0f7 4220 default:
849c4542 4221 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4222 }
9a799d71 4223
7086400d
AD		 4224 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4225
9a799d71 4226 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4227 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4228
4229 /* update SAN MAC vmdq pool selection */
4230 if (hw->mac.san_mac_rar_index)
4231 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4232
1a71ab24
JK		 4233 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4234 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4235}
4236
9a799d71
AK		 4237/**
4238 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4239 * @rx_ring: ring to free buffers from
4240 **/
b6ec895e 4241static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4242{
b6ec895e 4243 struct device *dev = rx_ring->dev;
9a799d71 4244 unsigned long size;
b6ec895e 4245 u16 i;
9a799d71 4246
84418e3b
AD		 4247 /* ring already cleared, nothing to do */
4248 if (!rx_ring->rx_buffer_info)
4249 return;
9a799d71 4250
84418e3b 4251 /* Free all the Rx ring sk_buffs */
9a799d71 4252 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4253 struct ixgbe_rx_buffer *rx_buffer;
4254
4255 rx_buffer = &rx_ring->rx_buffer_info[i];
4256 if (rx_buffer->skb) {
4257 struct sk_buff *skb = rx_buffer->skb;
4258 if (IXGBE_CB(skb)->page_released) {
4259 dma_unmap_page(dev,
4260 IXGBE_CB(skb)->dma,
4261 ixgbe_rx_bufsz(rx_ring),
4262 DMA_FROM_DEVICE);
4263 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4264 }
4265 dev_kfree_skb(skb);
9a799d71 4266 }
f800326d
AD		 4267 rx_buffer->skb = NULL;
4268 if (rx_buffer->dma)
4269 dma_unmap_page(dev, rx_buffer->dma,
4270 ixgbe_rx_pg_size(rx_ring),
4271 DMA_FROM_DEVICE);
4272 rx_buffer->dma = 0;
4273 if (rx_buffer->page)
dd411ec4
AD		 4274 __free_pages(rx_buffer->page,
4275 ixgbe_rx_pg_order(rx_ring));
f800326d 4276 rx_buffer->page = NULL;
9a799d71
AK		 4277 }
4278
4279 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4280 memset(rx_ring->rx_buffer_info, 0, size);
4281
4282 /* Zero out the descriptor ring */
4283 memset(rx_ring->desc, 0, rx_ring->size);
4284
f800326d 4285 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4286 rx_ring->next_to_clean = 0;
4287 rx_ring->next_to_use = 0;
9a799d71
AK		 4288}
4289
4290/**
4291 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4292 * @tx_ring: ring to be cleaned
4293 **/
b6ec895e 4294static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4295{
4296 struct ixgbe_tx_buffer *tx_buffer_info;
4297 unsigned long size;
b6ec895e 4298 u16 i;
9a799d71 4299
84418e3b
AD		 4300 /* ring already cleared, nothing to do */
4301 if (!tx_ring->tx_buffer_info)
4302 return;
9a799d71 4303
84418e3b 4304 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4305 for (i = 0; i < tx_ring->count; i++) {
4306 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4307 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4308 }
4309
dad8a3b3
JF		 4310 netdev_tx_reset_queue(txring_txq(tx_ring));
4311
9a799d71
AK		 4312 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4313 memset(tx_ring->tx_buffer_info, 0, size);
4314
4315 /* Zero out the descriptor ring */
4316 memset(tx_ring->desc, 0, tx_ring->size);
4317
4318 tx_ring->next_to_use = 0;
4319 tx_ring->next_to_clean = 0;
9a799d71
AK		 4320}
4321
4322/**
021230d4 4323 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4324 * @adapter: board private structure
4325 **/
021230d4 4326static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4327{
4328 int i;
4329
021230d4 4330 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4331 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4332}
4333
4334/**
021230d4 4335 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4336 * @adapter: board private structure
4337 **/
021230d4 4338static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4339{
4340 int i;
4341
021230d4 4342 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4343 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4344}
4345
e4911d57
AD		 4346static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4347{
4348 struct hlist_node *node, *node2;
4349 struct ixgbe_fdir_filter *filter;
4350
4351 spin_lock(&adapter->fdir_perfect_lock);
4352
4353 hlist_for_each_entry_safe(filter, node, node2,
4354 &adapter->fdir_filter_list, fdir_node) {
4355 hlist_del(&filter->fdir_node);
4356 kfree(filter);
4357 }
4358 adapter->fdir_filter_count = 0;
4359
4360 spin_unlock(&adapter->fdir_perfect_lock);
4361}
4362
9a799d71
AK		 4363void ixgbe_down(struct ixgbe_adapter *adapter)
4364{
4365 struct net_device *netdev = adapter->netdev;
7f821875 4366 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4367 u32 rxctrl;
bf29ee6c 4368 int i;
9a799d71
AK		 4369
4370 /* signal that we are down to the interrupt handler */
4371 set_bit(__IXGBE_DOWN, &adapter->state);
4372
4373 /* disable receives */
7f821875
JB		 4374 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4375 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4376
2d39d576
YZ		 4377 /* disable all enabled rx queues */
4378 for (i = 0; i < adapter->num_rx_queues; i++)
4379 /* this call also flushes the previous write */
4380 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4381
032b4325 4382 usleep_range(10000, 20000);
9a799d71 4383
7f821875
JB		 4384 netif_tx_stop_all_queues(netdev);
4385
7086400d 4386 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4387 netif_carrier_off(netdev);
4388 netif_tx_disable(netdev);
4389
4390 ixgbe_irq_disable(adapter);
4391
4392 ixgbe_napi_disable_all(adapter);
4393
d034acf1
AD		 4394 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4395 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4396 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4397
4398 del_timer_sync(&adapter->service_timer);
4399
34cecbbf 4400 if (adapter->num_vfs) {
8e34d1aa
AD		 4401 /* Clear EITR Select mapping */
4402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4403
4404 /* Mark all the VFs as inactive */
4405 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4406 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4407
34cecbbf
AD		 4408 /* ping all the active vfs to let them know we are going down */
4409 ixgbe_ping_all_vfs(adapter);
4410
4411 /* Disable all VFTE/VFRE TX/RX */
4412 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4413 }
4414
7f821875
JB		 4415 /* disable transmits in the hardware now that interrupts are off */
4416 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4417 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4418 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4419 }
34cecbbf
AD		 4420
4421 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4422 switch (hw->mac.type) {
4423 case ixgbe_mac_82599EB:
b93a2226 4424 case ixgbe_mac_X540:
88512539 4425 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4426 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4427 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4428 break;
4429 default:
4430 break;
4431 }
7f821875 4432
6f4a0e45
PL		 4433 if (!pci_channel_offline(adapter->pdev))
4434 ixgbe_reset(adapter);
c6ecf39a 4435
ec74a471
ET		 4436 /* power down the optics for 82599 SFP+ fiber */
4437 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4438 hw->mac.ops.disable_tx_laser(hw);
4439
9a799d71
AK		 4440 ixgbe_clean_all_tx_rings(adapter);
4441 ixgbe_clean_all_rx_rings(adapter);
4442
5dd2d332 4443#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4444 /* since we reset the hardware DCA settings were cleared */
e35ec126 4445 ixgbe_setup_dca(adapter);
96b0e0f6 4446#endif
9a799d71
AK		 4447}
4448
9a799d71
AK		 4449/**
4450 * ixgbe_tx_timeout - Respond to a Tx Hang
4451 * @netdev: network interface device structure
4452 **/
4453static void ixgbe_tx_timeout(struct net_device *netdev)
4454{
4455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4456
4457 /* Do the reset outside of interrupt context */
c83c6cbd 4458 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4459}
4460
9a799d71
AK		 4461/**
4462 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4463 * @adapter: board private structure to initialize
4464 *
4465 * ixgbe_sw_init initializes the Adapter private data structure.
4466 * Fields are initialized based on PCI device information and
4467 * OS network device settings (MTU size).
4468 **/
9f9a12f8 4469static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4470{
4471 struct ixgbe_hw *hw = &adapter->hw;
4472 struct pci_dev *pdev = adapter->pdev;
021230d4 4473 unsigned int rss;
cb6d0f5e 4474 u32 fwsm;
7a6b6f51 4475#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4476 int j;
4477 struct tc_configuration *tc;
4478#endif
021230d4 4479
c44ade9e
JB		 4480 /* PCI config space info */
4481
4482 hw->vendor_id = pdev->vendor;
4483 hw->device_id = pdev->device;
4484 hw->revision_id = pdev->revision;
4485 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4486 hw->subsystem_device_id = pdev->subsystem_device;
4487
021230d4 4488 /* Set capability flags */
3ed69d7e 4489 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4490 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4491 switch (hw->mac.type) {
4492 case ixgbe_mac_82598EB:
bf069c97
DS		 4493 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4494 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4495 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4496 break;
b93a2226 4497 case ixgbe_mac_X540:
cb6d0f5e
JK		 4498 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4499 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4500 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4f51bf70 4501 case ixgbe_mac_82599EB:
49c7ffbe 4502 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4503 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4504 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4505 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4506 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4507 /* Flow Director hash filters enabled */
45b9f509 4508 adapter->atr_sample_rate = 20;
c087663e 4509 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4510 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4511 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4512#ifdef IXGBE_FCOE
0d551589
YZ		 4513 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4514 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4515#ifdef CONFIG_IXGBE_DCB
6ee16520 4516 /* Default traffic class to use for FCoE */
56075a98 4517 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4518#endif
eacd73f7 4519#endif /* IXGBE_FCOE */
bd508178
AD		 4520 break;
4521 default:
4522 break;
f8212f97 4523 }
2f90b865 4524
7c8ae65a
AD		 4525#ifdef IXGBE_FCOE
4526 /* FCoE support exists, always init the FCoE lock */
4527 spin_lock_init(&adapter->fcoe.lock);
4528
4529#endif
1fc5f038
AD		 4530 /* n-tuple support exists, always init our spinlock */
4531 spin_lock_init(&adapter->fdir_perfect_lock);
4532
7a6b6f51 4533#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4534 switch (hw->mac.type) {
4535 case ixgbe_mac_X540:
4536 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4537 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4538 break;
4539 default:
4540 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4541 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4542 break;
4543 }
4544
2f90b865
AD		 4545 /* Configure DCB traffic classes */
4546 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4547 tc = &adapter->dcb_cfg.tc_config[j];
4548 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4549 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4550 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4551 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4552 tc->dcb_pfc = pfc_disabled;
4553 }
4de2a022
JF		 4554
4555 /* Initialize default user to priority mapping, UPx->TC0 */
4556 tc = &adapter->dcb_cfg.tc_config[0];
4557 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4558 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4559
2f90b865
AD		 4560 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4561 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4562 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4563 adapter->dcb_set_bitmap = 0x00;
3032309b 4564 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4565 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4566 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4567
4568#endif
9a799d71
AK		 4569
4570 /* default flow control settings */
cd7664f6 4571 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4572 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4573 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4574 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4575 hw->fc.send_xon = true;
db2adc2d
JK		 4576 hw->fc.disable_fc_autoneg =
4577 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
9a799d71 4578
99d74487
AD		 4579#ifdef CONFIG_PCI_IOV
4580 /* assign number of SR-IOV VFs */
4581 if (hw->mac.type != ixgbe_mac_82598EB)
4582 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4583
4584#endif
30efa5a3 4585 /* enable itr by default in dynamic mode */
f7554a2b 4586 adapter->rx_itr_setting = 1;
f7554a2b 4587 adapter->tx_itr_setting = 1;
30efa5a3 4588
30efa5a3
JB		 4589 /* set default ring sizes */
4590 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4591 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4592
bd198058 4593 /* set default work limits */
59224555 4594 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4595
9a799d71 4596 /* initialize eeprom parameters */
c44ade9e 4597 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4598 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4599 return -EIO;
4600 }
4601
9a799d71
AK		 4602 set_bit(__IXGBE_DOWN, &adapter->state);
4603
4604 return 0;
4605}
4606
4607/**
4608 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4609 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4610 *
4611 * Return 0 on success, negative on failure
4612 **/
b6ec895e 4613int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4614{
b6ec895e 4615 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4616 int orig_node = dev_to_node(dev);
4617 int numa_node = -1;
9a799d71
AK		 4618 int size;
4619
3a581073 4620 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4621
4622 if (tx_ring->q_vector)
4623 numa_node = tx_ring->q_vector->numa_node;
4624
4625 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4626 if (!tx_ring->tx_buffer_info)
89bf67f1 4627 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4628 if (!tx_ring->tx_buffer_info)
4629 goto err;
9a799d71
AK		 4630
4631 /* round up to nearest 4K */
12207e49 4632 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4633 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4634
de88eeeb
AD		 4635 set_dev_node(dev, numa_node);
4636 tx_ring->desc = dma_alloc_coherent(dev,
4637 tx_ring->size,
4638 &tx_ring->dma,
4639 GFP_KERNEL);
4640 set_dev_node(dev, orig_node);
4641 if (!tx_ring->desc)
4642 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4643 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4644 if (!tx_ring->desc)
4645 goto err;
9a799d71 4646
3a581073
JB		 4647 tx_ring->next_to_use = 0;
4648 tx_ring->next_to_clean = 0;
9a799d71 4649 return 0;
e01c31a5
JB		 4650
4651err:
4652 vfree(tx_ring->tx_buffer_info);
4653 tx_ring->tx_buffer_info = NULL;
b6ec895e 4654 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4655 return -ENOMEM;
9a799d71
AK		 4656}
4657
69888674
AD		 4658/**
4659 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4660 * @adapter: board private structure
4661 *
4662 * If this function returns with an error, then it's possible one or
4663 * more of the rings is populated (while the rest are not). It is the
4664 * callers duty to clean those orphaned rings.
4665 *
4666 * Return 0 on success, negative on failure
4667 **/
4668static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4669{
4670 int i, err = 0;
4671
4672 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4673 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4674 if (!err)
4675 continue;
de3d5b94 4676
396e799c 4677 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4678 goto err_setup_tx;
69888674
AD		 4679 }
4680
de3d5b94
AD		 4681 return 0;
4682err_setup_tx:
4683 /* rewind the index freeing the rings as we go */
4684 while (i--)
4685 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4686 return err;
4687}
4688
9a799d71
AK		 4689/**
4690 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4691 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4692 *
4693 * Returns 0 on success, negative on failure
4694 **/
b6ec895e 4695int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4696{
b6ec895e 4697 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4698 int orig_node = dev_to_node(dev);
4699 int numa_node = -1;
021230d4 4700 int size;
9a799d71 4701
3a581073 4702 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4703
4704 if (rx_ring->q_vector)
4705 numa_node = rx_ring->q_vector->numa_node;
4706
4707 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4708 if (!rx_ring->rx_buffer_info)
89bf67f1 4709 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4710 if (!rx_ring->rx_buffer_info)
4711 goto err;
9a799d71 4712
9a799d71 4713 /* Round up to nearest 4K */
3a581073
JB		 4714 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4715 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4716
de88eeeb
AD		 4717 set_dev_node(dev, numa_node);
4718 rx_ring->desc = dma_alloc_coherent(dev,
4719 rx_ring->size,
4720 &rx_ring->dma,
4721 GFP_KERNEL);
4722 set_dev_node(dev, orig_node);
4723 if (!rx_ring->desc)
4724 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4725 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4726 if (!rx_ring->desc)
4727 goto err;
9a799d71 4728
3a581073
JB		 4729 rx_ring->next_to_clean = 0;
4730 rx_ring->next_to_use = 0;
9a799d71
AK		 4731
4732 return 0;
b6ec895e
AD		 4733err:
4734 vfree(rx_ring->rx_buffer_info);
4735 rx_ring->rx_buffer_info = NULL;
4736 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4737 return -ENOMEM;
9a799d71
AK		 4738}
4739
69888674
AD		 4740/**
4741 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4742 * @adapter: board private structure
4743 *
4744 * If this function returns with an error, then it's possible one or
4745 * more of the rings is populated (while the rest are not). It is the
4746 * callers duty to clean those orphaned rings.
4747 *
4748 * Return 0 on success, negative on failure
4749 **/
69888674
AD		 4750static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4751{
4752 int i, err = 0;
4753
4754 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4755 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4756 if (!err)
4757 continue;
de3d5b94 4758
396e799c 4759 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4760 goto err_setup_rx;
69888674
AD		 4761 }
4762
7c8ae65a
AD		 4763#ifdef IXGBE_FCOE
4764 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4765 if (!err)
4766#endif
4767 return 0;
de3d5b94
AD		 4768err_setup_rx:
4769 /* rewind the index freeing the rings as we go */
4770 while (i--)
4771 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4772 return err;
4773}
4774
9a799d71
AK		 4775/**
4776 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4777 * @tx_ring: Tx descriptor ring for a specific queue
4778 *
4779 * Free all transmit software resources
4780 **/
b6ec895e 4781void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4782{
b6ec895e 4783 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4784
4785 vfree(tx_ring->tx_buffer_info);
4786 tx_ring->tx_buffer_info = NULL;
4787
b6ec895e
AD		 4788 /* if not set, then don't free */
4789 if (!tx_ring->desc)
4790 return;
4791
4792 dma_free_coherent(tx_ring->dev, tx_ring->size,
4793 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4794
4795 tx_ring->desc = NULL;
4796}
4797
4798/**
4799 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4800 * @adapter: board private structure
4801 *
4802 * Free all transmit software resources
4803 **/
4804static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4805{
4806 int i;
4807
4808 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4809 if (adapter->tx_ring[i]->desc)
b6ec895e 4810 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4811}
4812
4813/**
b4617240 4814 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4815 * @rx_ring: ring to clean the resources from
4816 *
4817 * Free all receive software resources
4818 **/
b6ec895e 4819void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4820{
b6ec895e 4821 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4822
4823 vfree(rx_ring->rx_buffer_info);
4824 rx_ring->rx_buffer_info = NULL;
4825
b6ec895e
AD		 4826 /* if not set, then don't free */
4827 if (!rx_ring->desc)
4828 return;
4829
4830 dma_free_coherent(rx_ring->dev, rx_ring->size,
4831 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4832
4833 rx_ring->desc = NULL;
4834}
4835
4836/**
4837 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4838 * @adapter: board private structure
4839 *
4840 * Free all receive software resources
4841 **/
4842static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4843{
4844 int i;
4845
7c8ae65a
AD		 4846#ifdef IXGBE_FCOE
4847 ixgbe_free_fcoe_ddp_resources(adapter);
4848
4849#endif
9a799d71 4850 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4851 if (adapter->rx_ring[i]->desc)
b6ec895e 4852 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4853}
4854
9a799d71
AK		 4855/**
4856 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4857 * @netdev: network interface device structure
4858 * @new_mtu: new value for maximum frame size
4859 *
4860 * Returns 0 on success, negative on failure
4861 **/
4862static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4863{
4864 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4865 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4866
42c783c5 4867 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4868 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4869 return -EINVAL;
4870
4871 /*
872844dd
AD		 4872 * For 82599EB we cannot allow legacy VFs to enable their receive
4873 * paths when MTU greater than 1500 is configured. So display a
4874 * warning that legacy VFs will be disabled.
655309e9
AD		 4875 */
4876 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4877 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4878 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
872844dd 4879 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 4880
396e799c 4881 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4882
021230d4 4883 /* must set new MTU before calling down or up */
9a799d71
AK		 4884 netdev->mtu = new_mtu;
4885
d4f80882
AV		 4886 if (netif_running(netdev))
4887 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4888
4889 return 0;
4890}
4891
4892/**
4893 * ixgbe_open - Called when a network interface is made active
4894 * @netdev: network interface device structure
4895 *
4896 * Returns 0 on success, negative value on failure
4897 *
4898 * The open entry point is called when a network interface is made
4899 * active by the system (IFF_UP). At this point all resources needed
4900 * for transmit and receive operations are allocated, the interrupt
4901 * handler is registered with the OS, the watchdog timer is started,
4902 * and the stack is notified that the interface is ready.
4903 **/
4904static int ixgbe_open(struct net_device *netdev)
4905{
4906 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4907 int err;
4bebfaa5
AK		 4908
4909 /* disallow open during test */
4910 if (test_bit(__IXGBE_TESTING, &adapter->state))
4911 return -EBUSY;
9a799d71 4912
54386467
JB		 4913 netif_carrier_off(netdev);
4914
9a799d71
AK		 4915 /* allocate transmit descriptors */
4916 err = ixgbe_setup_all_tx_resources(adapter);
4917 if (err)
4918 goto err_setup_tx;
4919
9a799d71
AK		 4920 /* allocate receive descriptors */
4921 err = ixgbe_setup_all_rx_resources(adapter);
4922 if (err)
4923 goto err_setup_rx;
4924
4925 ixgbe_configure(adapter);
4926
021230d4 4927 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4928 if (err)
4929 goto err_req_irq;
4930
ac802f5d
AD		 4931 /* Notify the stack of the actual queue counts. */
4932 err = netif_set_real_num_tx_queues(netdev,
4933 adapter->num_rx_pools > 1 ? 1 :
4934 adapter->num_tx_queues);
4935 if (err)
4936 goto err_set_queues;
4937
4938
4939 err = netif_set_real_num_rx_queues(netdev,
4940 adapter->num_rx_pools > 1 ? 1 :
4941 adapter->num_rx_queues);
4942 if (err)
4943 goto err_set_queues;
4944
1a71ab24 4945 ixgbe_ptp_init(adapter);
1a71ab24 4946
c7ccde0f 4947 ixgbe_up_complete(adapter);
9a799d71
AK		 4948
4949 return 0;
4950
ac802f5d
AD		 4951err_set_queues:
4952 ixgbe_free_irq(adapter);
9a799d71 4953err_req_irq:
a20a1199 4954 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4955err_setup_rx:
a20a1199 4956 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4957err_setup_tx:
9a799d71
AK		 4958 ixgbe_reset(adapter);
4959
4960 return err;
4961}
4962
4963/**
4964 * ixgbe_close - Disables a network interface
4965 * @netdev: network interface device structure
4966 *
4967 * Returns 0, this is not allowed to fail
4968 *
4969 * The close entry point is called when an interface is de-activated
4970 * by the OS. The hardware is still under the drivers control, but
4971 * needs to be disabled. A global MAC reset is issued to stop the
4972 * hardware, and all transmit and receive resources are freed.
4973 **/
4974static int ixgbe_close(struct net_device *netdev)
4975{
4976 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 4977
1a71ab24 4978 ixgbe_ptp_stop(adapter);
1a71ab24 4979
9a799d71
AK		 4980 ixgbe_down(adapter);
4981 ixgbe_free_irq(adapter);
4982
e4911d57
AD		 4983 ixgbe_fdir_filter_exit(adapter);
4984
9a799d71
AK		 4985 ixgbe_free_all_tx_resources(adapter);
4986 ixgbe_free_all_rx_resources(adapter);
4987
5eba3699 4988 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4989
4990 return 0;
4991}
4992
b3c8b4ba
AD		 4993#ifdef CONFIG_PM
4994static int ixgbe_resume(struct pci_dev *pdev)
4995{
c60fbb00
AD		 4996 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4997 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4998 u32 err;
4999
5000 pci_set_power_state(pdev, PCI_D0);
5001 pci_restore_state(pdev);
656ab817
DS		 5002 /*
5003 * pci_restore_state clears dev->state_saved so call
5004 * pci_save_state to restore it.
5005 */
5006 pci_save_state(pdev);
9ce77666 5007
5008 err = pci_enable_device_mem(pdev);
b3c8b4ba 5009 if (err) {
849c4542 5010 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5011 return err;
5012 }
5013 pci_set_master(pdev);
5014
dd4d8ca6 5015 pci_wake_from_d3(pdev, false);
b3c8b4ba 5016
b3c8b4ba
AD		 5017 ixgbe_reset(adapter);
5018
495dce12
WJP		 5019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5020
ac802f5d
AD		 5021 rtnl_lock();
5022 err = ixgbe_init_interrupt_scheme(adapter);
5023 if (!err && netif_running(netdev))
c60fbb00 5024 err = ixgbe_open(netdev);
ac802f5d
AD		 5025
5026 rtnl_unlock();
5027
5028 if (err)
5029 return err;
b3c8b4ba
AD		 5030
5031 netif_device_attach(netdev);
5032
5033 return 0;
5034}
b3c8b4ba 5035#endif /* CONFIG_PM */
9d8d05ae
RW		 5036
5037static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5038{
c60fbb00
AD		 5039 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5040 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5041 struct ixgbe_hw *hw = &adapter->hw;
5042 u32 ctrl, fctrl;
5043 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5044#ifdef CONFIG_PM
5045 int retval = 0;
5046#endif
5047
5048 netif_device_detach(netdev);
5049
5050 if (netif_running(netdev)) {
ab6039a7 5051 rtnl_lock();
b3c8b4ba
AD		 5052 ixgbe_down(adapter);
5053 ixgbe_free_irq(adapter);
5054 ixgbe_free_all_tx_resources(adapter);
5055 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5056 rtnl_unlock();
b3c8b4ba 5057 }
b3c8b4ba 5058
5f5ae6fc
AD		 5059 ixgbe_clear_interrupt_scheme(adapter);
5060
b3c8b4ba
AD		 5061#ifdef CONFIG_PM
5062 retval = pci_save_state(pdev);
5063 if (retval)
5064 return retval;
4df10466 5065
b3c8b4ba 5066#endif
e8e26350
PW		 5067 if (wufc) {
5068 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5069
ec74a471
ET		 5070 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5071 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5072 hw->mac.ops.enable_tx_laser(hw);
5073
e8e26350
PW		 5074 /* turn on all-multi mode if wake on multicast is enabled */
5075 if (wufc & IXGBE_WUFC_MC) {
5076 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5077 fctrl |= IXGBE_FCTRL_MPE;
5078 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5079 }
5080
5081 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5082 ctrl |= IXGBE_CTRL_GIO_DIS;
5083 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5084
5085 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5086 } else {
5087 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5088 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5089 }
5090
bd508178
AD		 5091 switch (hw->mac.type) {
5092 case ixgbe_mac_82598EB:
dd4d8ca6 5093 pci_wake_from_d3(pdev, false);
bd508178
AD		 5094 break;
5095 case ixgbe_mac_82599EB:
b93a2226 5096 case ixgbe_mac_X540:
bd508178
AD		 5097 pci_wake_from_d3(pdev, !!wufc);
5098 break;
5099 default:
5100 break;
5101 }
b3c8b4ba 5102
9d8d05ae
RW		 5103 *enable_wake = !!wufc;
5104
b3c8b4ba
AD		 5105 ixgbe_release_hw_control(adapter);
5106
5107 pci_disable_device(pdev);
5108
9d8d05ae
RW		 5109 return 0;
5110}
5111
5112#ifdef CONFIG_PM
5113static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5114{
5115 int retval;
5116 bool wake;
5117
5118 retval = __ixgbe_shutdown(pdev, &wake);
5119 if (retval)
5120 return retval;
5121
5122 if (wake) {
5123 pci_prepare_to_sleep(pdev);
5124 } else {
5125 pci_wake_from_d3(pdev, false);
5126 pci_set_power_state(pdev, PCI_D3hot);
5127 }
b3c8b4ba
AD		 5128
5129 return 0;
5130}
9d8d05ae 5131#endif /* CONFIG_PM */
b3c8b4ba
AD		 5132
5133static void ixgbe_shutdown(struct pci_dev *pdev)
5134{
9d8d05ae
RW		 5135 bool wake;
5136
5137 __ixgbe_shutdown(pdev, &wake);
5138
5139 if (system_state == SYSTEM_POWER_OFF) {
5140 pci_wake_from_d3(pdev, wake);
5141 pci_set_power_state(pdev, PCI_D3hot);
5142 }
b3c8b4ba
AD		 5143}
5144
9a799d71
AK		 5145/**
5146 * ixgbe_update_stats - Update the board statistics counters.
5147 * @adapter: board private structure
5148 **/
5149void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5150{
2d86f139 5151 struct net_device *netdev = adapter->netdev;
9a799d71 5152 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5153 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5154 u64 total_mpc = 0;
5155 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5156 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5157 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5158 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5159
d08935c2
DS		 5160 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5161 test_bit(__IXGBE_RESETTING, &adapter->state))
5162 return;
5163
94b982b2 5164 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5165 u64 rsc_count = 0;
94b982b2 5166 u64 rsc_flush = 0;
94b982b2 5167 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5168 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5169 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5170 }
5171 adapter->rsc_total_count = rsc_count;
5172 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5173 }
5174
5b7da515
AD		 5175 for (i = 0; i < adapter->num_rx_queues; i++) {
5176 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5177 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5178 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5179 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5180 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5181 bytes += rx_ring->stats.bytes;
5182 packets += rx_ring->stats.packets;
5183 }
5184 adapter->non_eop_descs = non_eop_descs;
5185 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5186 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5187 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5188 netdev->stats.rx_bytes = bytes;
5189 netdev->stats.rx_packets = packets;
5190
5191 bytes = 0;
5192 packets = 0;
7ca3bc58 5193 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5194 for (i = 0; i < adapter->num_tx_queues; i++) {
5195 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5196 restart_queue += tx_ring->tx_stats.restart_queue;
5197 tx_busy += tx_ring->tx_stats.tx_busy;
5198 bytes += tx_ring->stats.bytes;
5199 packets += tx_ring->stats.packets;
5200 }
eb985f09 5201 adapter->restart_queue = restart_queue;
5b7da515
AD		 5202 adapter->tx_busy = tx_busy;
5203 netdev->stats.tx_bytes = bytes;
5204 netdev->stats.tx_packets = packets;
7ca3bc58 5205
7ca647bd 5206 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5207
5208 /* 8 register reads */
6f11eef7
AV		 5209 for (i = 0; i < 8; i++) {
5210 /* for packet buffers not used, the register should read 0 */
5211 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5212 missed_rx += mpc;
7ca647bd
JP		 5213 hwstats->mpc[i] += mpc;
5214 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5215 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5216 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5217 switch (hw->mac.type) {
5218 case ixgbe_mac_82598EB:
1a70db4b
ET		 5219 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5220 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5221 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5222 hwstats->pxonrxc[i] +=
5223 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5224 break;
5225 case ixgbe_mac_82599EB:
b93a2226 5226 case ixgbe_mac_X540:
bd508178
AD		 5227 hwstats->pxonrxc[i] +=
5228 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5229 break;
5230 default:
5231 break;
e8e26350 5232 }
6f11eef7 5233 }
1a70db4b
ET		 5234
5235 /*16 register reads */
5236 for (i = 0; i < 16; i++) {
5237 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5238 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5239 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5240 (hw->mac.type == ixgbe_mac_X540)) {
5241 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5242 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5243 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5244 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5245 }
5246 }
5247
7ca647bd 5248 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5249 /* work around hardware counting issue */
7ca647bd 5250 hwstats->gprc -= missed_rx;
6f11eef7 5251
c84d324c
JF		 5252 ixgbe_update_xoff_received(adapter);
5253
6f11eef7 5254 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5255 switch (hw->mac.type) {
5256 case ixgbe_mac_82598EB:
5257 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5258 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5259 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5260 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5261 break;
b93a2226 5262 case ixgbe_mac_X540:
58f6bcf9
ET		 5263 /* OS2BMC stats are X540 only*/
5264 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5265 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5266 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5267 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5268 case ixgbe_mac_82599EB:
a4d4f629
AD		 5269 for (i = 0; i < 16; i++)
5270 adapter->hw_rx_no_dma_resources +=
5271 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5272 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5273 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5274 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5275 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5276 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5277 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5278 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5279 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5280 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5281#ifdef IXGBE_FCOE
7ca647bd
JP		 5282 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5283 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5284 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5285 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5286 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5287 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5288 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5289 if (adapter->fcoe.ddp_pool) {
5290 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5291 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5292 unsigned int cpu;
5293 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5294 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5295 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5296 noddp += ddp_pool->noddp;
5297 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5298 }
5a1ee270
AD		 5299 hwstats->fcoe_noddp = noddp;
5300 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5301 }
6d45522c 5302#endif /* IXGBE_FCOE */
bd508178
AD		 5303 break;
5304 default:
5305 break;
e8e26350 5306 }
9a799d71 5307 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5308 hwstats->bprc += bprc;
5309 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5310 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5311 hwstats->mprc -= bprc;
5312 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5313 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5314 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5315 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5316 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5317 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5318 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5319 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5320 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5321 hwstats->lxontxc += lxon;
6f11eef7 5322 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5323 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5324 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5325 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5326 /*
5327 * 82598 errata - tx of flow control packets is included in tx counters
5328 */
5329 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5330 hwstats->gptc -= xon_off_tot;
5331 hwstats->mptc -= xon_off_tot;
5332 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5333 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5334 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5335 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5336 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5337 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5338 hwstats->ptc64 -= xon_off_tot;
5339 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5340 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5341 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5342 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5343 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5344 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5345
5346 /* Fill out the OS statistics structure */
7ca647bd 5347 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5348
5349 /* Rx Errors */
7ca647bd 5350 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5351 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5352 netdev->stats.rx_length_errors = hwstats->rlec;
5353 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5354 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5355}
5356
5357/**
d034acf1 5358 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5359 * @adapter: pointer to the device adapter structure
9a799d71 5360 **/
d034acf1 5361static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5362{
cf8280ee 5363 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5364 int i;
cf8280ee 5365
d034acf1
AD		 5366 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5367 return;
5368
5369 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5370
d034acf1 5371 /* if interface is down do nothing */
fe49f04a 5372 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5373 return;
5374
5375 /* do nothing if we are not using signature filters */
5376 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5377 return;
5378
5379 adapter->fdir_overflow++;
5380
93c52dd0
AD		 5381 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5382 for (i = 0; i < adapter->num_tx_queues; i++)
5383 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5384 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5385 /* re-enable flow director interrupts */
5386 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5387 } else {
5388 e_err(probe, "failed to finish FDIR re-initialization, "
5389 "ignored adding FDIR ATR filters\n");
5390 }
93c52dd0
AD		 5391}
5392
5393/**
5394 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5395 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5396 *
5397 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5398 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5399 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5400 * determine if a hang has occurred.
93c52dd0
AD		 5401 */
5402static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5403{
cf8280ee 5404 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5405 u64 eics = 0;
5406 int i;
cf8280ee 5407
93c52dd0
AD		 5408 /* If we're down or resetting, just bail */
5409 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5410 test_bit(__IXGBE_RESETTING, &adapter->state))
5411 return;
22d5a71b 5412
93c52dd0
AD		 5413 /* Force detection of hung controller */
5414 if (netif_carrier_ok(adapter->netdev)) {
5415 for (i = 0; i < adapter->num_tx_queues; i++)
5416 set_check_for_tx_hang(adapter->tx_ring[i]);
5417 }
22d5a71b 5418
fe49f04a
AD		 5419 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5420 /*
5421 * for legacy and MSI interrupts don't set any bits
5422 * that are enabled for EIAM, because this operation
5423 * would set *both* EIMS and EICS for any bit in EIAM
5424 */
5425 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5426 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5427 } else {
5428 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5429 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5430 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5431 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5432 eics |= ((u64)1 << i);
5433 }
cf8280ee 5434 }
9a799d71 5435
93c52dd0 5436 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5437 ixgbe_irq_rearm_queues(adapter, eics);
5438
cf8280ee
JB		 5439}
5440
e8e26350 5441/**
93c52dd0 5442 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5443 * @adapter: pointer to the device adapter structure
5444 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5445 **/
93c52dd0 5446static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5447{
e8e26350 5448 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5449 u32 link_speed = adapter->link_speed;
5450 bool link_up = adapter->link_up;
041441d0 5451 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5452
93c52dd0
AD		 5453 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5454 return;
5455
5456 if (hw->mac.ops.check_link) {
5457 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5458 } else {
93c52dd0
AD		 5459 /* always assume link is up, if no check link function */
5460 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5461 link_up = true;
c4cf55e5 5462 }
041441d0
AD		 5463
5464 if (adapter->ixgbe_ieee_pfc)
5465 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5466
3ebe8fde 5467 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5468 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5469 ixgbe_set_rx_drop_en(adapter);
5470 }
93c52dd0
AD		 5471
5472 if (link_up ||
5473 time_after(jiffies, (adapter->link_check_timeout +
5474 IXGBE_TRY_LINK_TIMEOUT))) {
5475 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5476 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5477 IXGBE_WRITE_FLUSH(hw);
5478 }
5479
5480 adapter->link_up = link_up;
5481 adapter->link_speed = link_speed;
e8e26350
PW		 5482}
5483
107d3018
AD		 5484static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5485{
5486#ifdef CONFIG_IXGBE_DCB
5487 struct net_device *netdev = adapter->netdev;
5488 struct dcb_app app = {
5489 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5490 .protocol = 0,
5491 };
5492 u8 up = 0;
5493
5494 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5495 up = dcb_ieee_getapp_mask(netdev, &app);
5496
5497 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5498#endif
5499}
5500
e8e26350 5501/**
93c52dd0
AD		 5502 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5503 * print link up message
49ce9c2c 5504 * @adapter: pointer to the device adapter structure
e8e26350 5505 **/
93c52dd0 5506static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5507{
93c52dd0 5508 struct net_device *netdev = adapter->netdev;
e8e26350 5509 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5510 u32 link_speed = adapter->link_speed;
5511 bool flow_rx, flow_tx;
e8e26350 5512
93c52dd0
AD		 5513 /* only continue if link was previously down */
5514 if (netif_carrier_ok(netdev))
a985b6c3 5515 return;
63d6e1d8 5516
93c52dd0 5517 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5518
93c52dd0
AD		 5519 switch (hw->mac.type) {
5520 case ixgbe_mac_82598EB: {
5521 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5522 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5523 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5524 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5525 }
5526 break;
5527 case ixgbe_mac_X540:
5528 case ixgbe_mac_82599EB: {
5529 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5530 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5531 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5532 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5533 }
5534 break;
5535 default:
5536 flow_tx = false;
5537 flow_rx = false;
5538 break;
e8e26350 5539 }
3a6a4eda 5540
1a71ab24
JK		 5541 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5542 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5543
93c52dd0
AD		 5544 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5545 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5546 "10 Gbps" :
5547 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5548 "1 Gbps" :
5549 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5550 "100 Mbps" :
5551 "unknown speed"))),
5552 ((flow_rx && flow_tx) ? "RX/TX" :
5553 (flow_rx ? "RX" :
5554 (flow_tx ? "TX" : "None"))));
e8e26350 5555
93c52dd0 5556 netif_carrier_on(netdev);
93c52dd0 5557 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5558
107d3018
AD		 5559 /* update the default user priority for VFs */
5560 ixgbe_update_default_up(adapter);
5561
befa2af7
AD		 5562 /* ping all the active vfs to let them know link has changed */
5563 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5564}
5565
c4cf55e5 5566/**
93c52dd0
AD		 5567 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5568 * print link down message
49ce9c2c 5569 * @adapter: pointer to the adapter structure
c4cf55e5 5570 **/
581330ba 5571static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5572{
cf8280ee 5573 struct net_device *netdev = adapter->netdev;
c4cf55e5 5574 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5575
93c52dd0
AD		 5576 adapter->link_up = false;
5577 adapter->link_speed = 0;
cf8280ee 5578
93c52dd0
AD		 5579 /* only continue if link was up previously */
5580 if (!netif_carrier_ok(netdev))
5581 return;
264857b8 5582
93c52dd0
AD		 5583 /* poll for SFP+ cable when link is down */
5584 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5585 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5586
1a71ab24
JK		 5587 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5588 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5589
93c52dd0
AD		 5590 e_info(drv, "NIC Link is Down\n");
5591 netif_carrier_off(netdev);
befa2af7
AD		 5592
5593 /* ping all the active vfs to let them know link has changed */
5594 ixgbe_ping_all_vfs(adapter);
93c52dd0 5595}
e8e26350 5596
93c52dd0
AD		 5597/**
5598 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5599 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5600 **/
5601static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5602{
c4cf55e5 5603 int i;
93c52dd0 5604 int some_tx_pending = 0;
c4cf55e5 5605
93c52dd0 5606 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5607 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5608 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5609 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5610 some_tx_pending = 1;
5611 break;
5612 }
5613 }
5614
5615 if (some_tx_pending) {
5616 /* We've lost link, so the controller stops DMA,
5617 * but we've got queued Tx work that's never going
5618 * to get done, so reset controller to flush Tx.
5619 * (Do the reset outside of interrupt context).
5620 */
c83c6cbd 5621 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5622 }
c4cf55e5 5623 }
c4cf55e5
PWJ		 5624}
5625
a985b6c3
GR		 5626static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5627{
5628 u32 ssvpc;
5629
0584d999
GR		 5630 /* Do not perform spoof check for 82598 or if not in IOV mode */
5631 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5632 adapter->num_vfs == 0)
a985b6c3
GR		 5633 return;
5634
5635 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5636
5637 /*
5638 * ssvpc register is cleared on read, if zero then no
5639 * spoofed packets in the last interval.
5640 */
5641 if (!ssvpc)
5642 return;
5643
d6ea0754 5644 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5645}
5646
93c52dd0
AD		 5647/**
5648 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5649 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5650 **/
5651static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5652{
5653 /* if interface is down do nothing */
7edebf9a
ET		 5654 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5655 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5656 return;
5657
5658 ixgbe_watchdog_update_link(adapter);
5659
5660 if (adapter->link_up)
5661 ixgbe_watchdog_link_is_up(adapter);
5662 else
5663 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5664
a985b6c3 5665 ixgbe_spoof_check(adapter);
9a799d71 5666 ixgbe_update_stats(adapter);
93c52dd0
AD		 5667
5668 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5669}
10eec955 5670
cf8280ee 5671/**
7086400d 5672 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5673 * @adapter: the ixgbe adapter structure
cf8280ee 5674 **/
7086400d 5675static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5676{
cf8280ee 5677 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5678 s32 err;
cf8280ee 5679
7086400d
AD		 5680 /* not searching for SFP so there is nothing to do here */
5681 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5682 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5683 return;
10eec955 5684
7086400d
AD		 5685 /* someone else is in init, wait until next service event */
5686 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5687 return;
cf8280ee 5688
7086400d
AD		 5689 err = hw->phy.ops.identify_sfp(hw);
5690 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5691 goto sfp_out;
264857b8 5692
7086400d
AD		 5693 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5694 /* If no cable is present, then we need to reset
5695 * the next time we find a good cable. */
5696 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5697 }
9a799d71 5698
7086400d
AD		 5699 /* exit on error */
5700 if (err)
5701 goto sfp_out;
e8e26350 5702
7086400d
AD		 5703 /* exit if reset not needed */
5704 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5705 goto sfp_out;
9a799d71 5706
7086400d 5707 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5708
7086400d
AD		 5709 /*
5710 * A module may be identified correctly, but the EEPROM may not have
5711 * support for that module. setup_sfp() will fail in that case, so
5712 * we should not allow that module to load.
5713 */
5714 if (hw->mac.type == ixgbe_mac_82598EB)
5715 err = hw->phy.ops.reset(hw);
5716 else
5717 err = hw->mac.ops.setup_sfp(hw);
5718
5719 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5720 goto sfp_out;
5721
5722 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5723 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5724
5725sfp_out:
5726 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5727
5728 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5729 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5730 e_dev_err("failed to initialize because an unsupported "
5731 "SFP+ module type was detected.\n");
5732 e_dev_err("Reload the driver after installing a "
5733 "supported module.\n");
5734 unregister_netdev(adapter->netdev);
bc59fcda 5735 }
7086400d 5736}
bc59fcda 5737
7086400d
AD		 5738/**
5739 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5740 * @adapter: the ixgbe adapter structure
7086400d
AD		 5741 **/
5742static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5743{
5744 struct ixgbe_hw *hw = &adapter->hw;
5745 u32 autoneg;
5746 bool negotiation;
5747
5748 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5749 return;
5750
5751 /* someone else is in init, wait until next service event */
5752 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5753 return;
5754
5755 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5756
5757 autoneg = hw->phy.autoneg_advertised;
5758 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5759 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5760 if (hw->mac.ops.setup_link)
5761 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5762
5763 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5764 adapter->link_check_timeout = jiffies;
5765 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5766}
5767
83c61fa9
GR		 5768#ifdef CONFIG_PCI_IOV
5769static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5770{
5771 int vf;
5772 struct ixgbe_hw *hw = &adapter->hw;
5773 struct net_device *netdev = adapter->netdev;
5774 u32 gpc;
5775 u32 ciaa, ciad;
5776
5777 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5778 if (gpc) /* If incrementing then no need for the check below */
5779 return;
5780 /*
5781 * Check to see if a bad DMA write target from an errant or
5782 * malicious VF has caused a PCIe error. If so then we can
5783 * issue a VFLR to the offending VF(s) and then resume without
5784 * requesting a full slot reset.
5785 */
5786
5787 for (vf = 0; vf < adapter->num_vfs; vf++) {
5788 ciaa = (vf << 16) | 0x80000000;
5789 /* 32 bit read so align, we really want status at offset 6 */
5790 ciaa |= PCI_COMMAND;
5791 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5792 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5793 ciaa &= 0x7FFFFFFF;
5794 /* disable debug mode asap after reading data */
5795 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5796 /* Get the upper 16 bits which will be the PCI status reg */
5797 ciad >>= 16;
5798 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5799 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5800 /* Issue VFLR */
5801 ciaa = (vf << 16) | 0x80000000;
5802 ciaa |= 0xA8;
5803 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5804 ciad = 0x00008000; /* VFLR */
5805 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5806 ciaa &= 0x7FFFFFFF;
5807 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5808 }
5809 }
5810}
5811
5812#endif
7086400d
AD		 5813/**
5814 * ixgbe_service_timer - Timer Call-back
5815 * @data: pointer to adapter cast into an unsigned long
5816 **/
5817static void ixgbe_service_timer(unsigned long data)
5818{
5819 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5820 unsigned long next_event_offset;
83c61fa9 5821 bool ready = true;
7086400d 5822
6bb78cfb
AD		 5823 /* poll faster when waiting for link */
5824 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5825 next_event_offset = HZ / 10;
5826 else
5827 next_event_offset = HZ * 2;
83c61fa9 5828
6bb78cfb 5829#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5830 /*
5831 * don't bother with SR-IOV VF DMA hang check if there are
5832 * no VFs or the link is down
5833 */
5834 if (!adapter->num_vfs ||
6bb78cfb 5835 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5836 goto normal_timer_service;
83c61fa9
GR		 5837
5838 /* If we have VFs allocated then we must check for DMA hangs */
5839 ixgbe_check_for_bad_vf(adapter);
5840 next_event_offset = HZ / 50;
5841 adapter->timer_event_accumulator++;
5842
6bb78cfb 5843 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5844 adapter->timer_event_accumulator = 0;
7086400d 5845 else
6bb78cfb 5846 ready = false;
7086400d 5847
6bb78cfb 5848normal_timer_service:
83c61fa9 5849#endif
7086400d
AD		 5850 /* Reset the timer */
5851 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5852
83c61fa9
GR		 5853 if (ready)
5854 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5855}
5856
c83c6cbd
AD		 5857static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5858{
5859 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5860 return;
5861
5862 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5863
5864 /* If we're already down or resetting, just bail */
5865 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5866 test_bit(__IXGBE_RESETTING, &adapter->state))
5867 return;
5868
5869 ixgbe_dump(adapter);
5870 netdev_err(adapter->netdev, "Reset adapter\n");
5871 adapter->tx_timeout_count++;
5872
5873 ixgbe_reinit_locked(adapter);
5874}
5875
7086400d
AD		 5876/**
5877 * ixgbe_service_task - manages and runs subtasks
5878 * @work: pointer to work_struct containing our data
5879 **/
5880static void ixgbe_service_task(struct work_struct *work)
5881{
5882 struct ixgbe_adapter *adapter = container_of(work,
5883 struct ixgbe_adapter,
5884 service_task);
5885
c83c6cbd 5886 ixgbe_reset_subtask(adapter);
7086400d
AD		 5887 ixgbe_sfp_detection_subtask(adapter);
5888 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5889 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5890 ixgbe_watchdog_subtask(adapter);
d034acf1 5891 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5892 ixgbe_check_hang_subtask(adapter);
3a6a4eda 5893 ixgbe_ptp_overflow_check(adapter);
7086400d
AD		 5894
5895 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5896}
5897
fd0db0ed
AD		 5898static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5899 struct ixgbe_tx_buffer *first,
244e27ad 5900 u8 *hdr_len)
897ab156 5901{
fd0db0ed 5902 struct sk_buff *skb = first->skb;
897ab156
AD		 5903 u32 vlan_macip_lens, type_tucmd;
5904 u32 mss_l4len_idx, l4len;
9a799d71 5905
897ab156
AD		 5906 if (!skb_is_gso(skb))
5907 return 0;
9a799d71 5908
897ab156 5909 if (skb_header_cloned(skb)) {
244e27ad 5910 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5911 if (err)
5912 return err;
9a799d71 5913 }
9a799d71 5914
897ab156
AD		 5915 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5916 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5917
244e27ad 5918 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5919 struct iphdr *iph = ip_hdr(skb);
5920 iph->tot_len = 0;
5921 iph->check = 0;
5922 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5923 iph->daddr, 0,
5924 IPPROTO_TCP,
5925 0);
5926 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5927 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5928 IXGBE_TX_FLAGS_CSUM |
5929 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5930 } else if (skb_is_gso_v6(skb)) {
5931 ipv6_hdr(skb)->payload_len = 0;
5932 tcp_hdr(skb)->check =
5933 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5934 &ipv6_hdr(skb)->daddr,
5935 0, IPPROTO_TCP, 0);
244e27ad
AD		 5936 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5937 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5938 }
5939
091a6246 5940 /* compute header lengths */
897ab156
AD		 5941 l4len = tcp_hdrlen(skb);
5942 *hdr_len = skb_transport_offset(skb) + l4len;
5943
091a6246
AD		 5944 /* update gso size and bytecount with header size */
5945 first->gso_segs = skb_shinfo(skb)->gso_segs;
5946 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5947
897ab156
AD		 5948 /* mss_l4len_id: use 1 as index for TSO */
5949 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5950 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5951 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5952
5953 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5954 vlan_macip_lens = skb_network_header_len(skb);
5955 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5956 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5957
5958 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5959 mss_l4len_idx);
897ab156
AD		 5960
5961 return 1;
5962}
5963
244e27ad
AD		 5964static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5965 struct ixgbe_tx_buffer *first)
7ca647bd 5966{
fd0db0ed 5967 struct sk_buff *skb = first->skb;
897ab156
AD		 5968 u32 vlan_macip_lens = 0;
5969 u32 mss_l4len_idx = 0;
5970 u32 type_tucmd = 0;
7ca647bd 5971
897ab156 5972 if (skb->ip_summed != CHECKSUM_PARTIAL) {
62748b7b
AD		 5973 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5974 if (unlikely(skb->no_fcs))
5975 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5976 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5977 return;
5978 }
897ab156
AD		 5979 } else {
5980 u8 l4_hdr = 0;
244e27ad 5981 switch (first->protocol) {
897ab156
AD		 5982 case __constant_htons(ETH_P_IP):
5983 vlan_macip_lens |= skb_network_header_len(skb);
5984 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5985 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5986 break;
897ab156
AD		 5987 case __constant_htons(ETH_P_IPV6):
5988 vlan_macip_lens |= skb_network_header_len(skb);
5989 l4_hdr = ipv6_hdr(skb)->nexthdr;
5990 break;
5991 default:
5992 if (unlikely(net_ratelimit())) {
5993 dev_warn(tx_ring->dev,
5994 "partial checksum but proto=%x!\n",
244e27ad 5995 first->protocol);
897ab156 5996 }
7ca647bd
JP		 5997 break;
5998 }
897ab156
AD		 5999
6000 switch (l4_hdr) {
7ca647bd 6001 case IPPROTO_TCP:
897ab156
AD		 6002 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6003 mss_l4len_idx = tcp_hdrlen(skb) <<
6004 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6005 break;
6006 case IPPROTO_SCTP:
897ab156
AD		 6007 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6008 mss_l4len_idx = sizeof(struct sctphdr) <<
6009 IXGBE_ADVTXD_L4LEN_SHIFT;
6010 break;
6011 case IPPROTO_UDP:
6012 mss_l4len_idx = sizeof(struct udphdr) <<
6013 IXGBE_ADVTXD_L4LEN_SHIFT;
6014 break;
6015 default:
6016 if (unlikely(net_ratelimit())) {
6017 dev_warn(tx_ring->dev,
6018 "partial checksum but l4 proto=%x!\n",
244e27ad 6019 l4_hdr);
897ab156 6020 }
7ca647bd
JP		 6021 break;
6022 }
244e27ad
AD		 6023
6024 /* update TX checksum flag */
6025 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6026 }
6027
244e27ad 6028 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6029 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6030 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6031
897ab156
AD		 6032 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6033 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6034}
6035
d3d00239 6036static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6037{
d3d00239
AD		 6038 /* set type for advanced descriptor with frame checksum insertion */
6039 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
d3d00239 6040 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6041
d3d00239 6042 /* set HW vlan bit if vlan is present */
66f32a8b 6043 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6044 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6045
3a6a4eda
JK		 6046 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6047 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
3a6a4eda 6048
d3d00239
AD		 6049 /* set segmentation enable bits for TSO/FSO */
6050#ifdef IXGBE_FCOE
93f5b3c1 6051 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 6052#else
6053 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6054#endif
6055 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6056
62748b7b
AD		 6057 /* insert frame checksum */
6058 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6059 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6060
d3d00239
AD		 6061 return cmd_type;
6062}
9a799d71 6063
729739b7
AD		 6064static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6065 u32 tx_flags, unsigned int paylen)
d3d00239 6066{
93f5b3c1 6067 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 6068
d3d00239
AD		 6069 /* enable L4 checksum for TSO and TX checksum offload */
6070 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6071 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6072
93f5b3c1
AD		 6073 /* enble IPv4 checksum for TSO */
6074 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6075 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6076
93f5b3c1
AD		 6077 /* use index 1 context for TSO/FSO/FCOE */
6078#ifdef IXGBE_FCOE
6079 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6080#else
6081 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6082#endif
93f5b3c1
AD		 6083 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6084
7f9643fd
AD		 6085 /*
6086 * Check Context must be set if Tx switch is enabled, which it
6087 * always is for case where virtual functions are running
6088 */
93f5b3c1
AD		 6089#ifdef IXGBE_FCOE
6090 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6091#else
7f9643fd 6092 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6093#endif
7f9643fd
AD		 6094 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6095
729739b7 6096 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6097}
44df32c5 6098
d3d00239
AD		 6099#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6100 IXGBE_TXD_CMD_RS)
6101
6102static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6103 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6104 const u8 hdr_len)
6105{
729739b7 6106 dma_addr_t dma;
fd0db0ed 6107 struct sk_buff *skb = first->skb;
729739b7 6108 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6109 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6110 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6111 unsigned int data_len = skb->data_len;
6112 unsigned int size = skb_headlen(skb);
729739b7 6113 unsigned int paylen = skb->len - hdr_len;
244e27ad 6114 u32 tx_flags = first->tx_flags;
729739b7 6115 __le32 cmd_type;
d3d00239 6116 u16 i = tx_ring->next_to_use;
d3d00239 6117
729739b7
AD		 6118 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6119
6120 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6121 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6122
d3d00239
AD		 6123#ifdef IXGBE_FCOE
6124 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6125 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6126 size -= sizeof(struct fcoe_crc_eof) - data_len;
6127 data_len = 0;
729739b7
AD		 6128 } else {
6129 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6130 }
6131 }
44df32c5 6132
d3d00239 6133#endif
729739b7
AD		 6134 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6135 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6136 goto dma_error;
8ad494b0 6137
729739b7
AD		 6138 /* record length, and DMA address */
6139 dma_unmap_len_set(first, len, size);
6140 dma_unmap_addr_set(first, dma, dma);
9a799d71 6141
729739b7 6142 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6143
d3d00239 6144 for (;;) {
729739b7 6145 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6146 tx_desc->read.cmd_type_len =
6147 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6148
d3d00239 6149 i++;
729739b7 6150 tx_desc++;
d3d00239 6151 if (i == tx_ring->count) {
e4f74028 6152 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6153 i = 0;
6154 }
729739b7
AD		 6155
6156 dma += IXGBE_MAX_DATA_PER_TXD;
6157 size -= IXGBE_MAX_DATA_PER_TXD;
6158
6159 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6160 tx_desc->read.olinfo_status = 0;
d3d00239 6161 }
e5a43549 6162
729739b7
AD		 6163 if (likely(!data_len))
6164 break;
9a799d71 6165
d3d00239 6166 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6167
729739b7
AD		 6168 i++;
6169 tx_desc++;
6170 if (i == tx_ring->count) {
6171 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6172 i = 0;
6173 }
9a799d71 6174
d3d00239 6175#ifdef IXGBE_FCOE
9e903e08 6176 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6177#else
9e903e08 6178 size = skb_frag_size(frag);
d3d00239
AD		 6179#endif
6180 data_len -= size;
9a799d71 6181
729739b7
AD		 6182 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6183 DMA_TO_DEVICE);
6184 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6185 goto dma_error;
9a799d71 6186
729739b7
AD		 6187 tx_buffer = &tx_ring->tx_buffer_info[i];
6188 dma_unmap_len_set(tx_buffer, len, size);
6189 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6190
729739b7
AD		 6191 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6192 tx_desc->read.olinfo_status = 0;
9a799d71 6193
729739b7
AD		 6194 frag++;
6195 }
9a799d71 6196
729739b7
AD		 6197 /* write last descriptor with RS and EOP bits */
6198 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6199 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6200
091a6246 6201 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6202
d3d00239
AD		 6203 /* set the timestamp */
6204 first->time_stamp = jiffies;
9a799d71
AK		 6205
6206 /*
729739b7
AD		 6207 * Force memory writes to complete before letting h/w know there
6208 * are new descriptors to fetch. (Only applicable for weak-ordered
6209 * memory model archs, such as IA-64).
6210 *
6211 * We also need this memory barrier to make certain all of the
6212 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6213 */
6214 wmb();
6215
d3d00239
AD		 6216 /* set next_to_watch value indicating a packet is present */
6217 first->next_to_watch = tx_desc;
6218
729739b7
AD		 6219 i++;
6220 if (i == tx_ring->count)
6221 i = 0;
6222
6223 tx_ring->next_to_use = i;
6224
d3d00239 6225 /* notify HW of packet */
84ea2591 6226 writel(i, tx_ring->tail);
d3d00239
AD		 6227
6228 return;
6229dma_error:
729739b7 6230 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6231
6232 /* clear dma mappings for failed tx_buffer_info map */
6233 for (;;) {
729739b7
AD		 6234 tx_buffer = &tx_ring->tx_buffer_info[i];
6235 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6236 if (tx_buffer == first)
d3d00239
AD		 6237 break;
6238 if (i == 0)
6239 i = tx_ring->count;
6240 i--;
6241 }
6242
d3d00239 6243 tx_ring->next_to_use = i;
9a799d71
AK		 6244}
6245
fd0db0ed 6246static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6247 struct ixgbe_tx_buffer *first)
69830529
AD		 6248{
6249 struct ixgbe_q_vector *q_vector = ring->q_vector;
6250 union ixgbe_atr_hash_dword input = { .dword = 0 };
6251 union ixgbe_atr_hash_dword common = { .dword = 0 };
6252 union {
6253 unsigned char *network;
6254 struct iphdr *ipv4;
6255 struct ipv6hdr *ipv6;
6256 } hdr;
ee9e0f0b 6257 struct tcphdr *th;
905e4a41 6258 __be16 vlan_id;
c4cf55e5 6259
69830529
AD		 6260 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6261 if (!q_vector)
6262 return;
6263
6264 /* do nothing if sampling is disabled */
6265 if (!ring->atr_sample_rate)
d3ead241 6266 return;
c4cf55e5 6267
69830529 6268 ring->atr_count++;
c4cf55e5 6269
69830529 6270 /* snag network header to get L4 type and address */
fd0db0ed 6271 hdr.network = skb_network_header(first->skb);
69830529
AD		 6272
6273 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6274 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6275 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6276 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6277 hdr.ipv4->protocol != IPPROTO_TCP))
6278 return;
ee9e0f0b 6279
fd0db0ed 6280 th = tcp_hdr(first->skb);
c4cf55e5 6281
66f32a8b
AD		 6282 /* skip this packet since it is invalid or the socket is closing */
6283 if (!th || th->fin)
69830529
AD		 6284 return;
6285
6286 /* sample on all syn packets or once every atr sample count */
6287 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6288 return;
6289
6290 /* reset sample count */
6291 ring->atr_count = 0;
6292
244e27ad 6293 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6294
6295 /*
6296 * src and dst are inverted, think how the receiver sees them
6297 *
6298 * The input is broken into two sections, a non-compressed section
6299 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6300 * is XORed together and stored in the compressed dword.
6301 */
6302 input.formatted.vlan_id = vlan_id;
6303
6304 /*
6305 * since src port and flex bytes occupy the same word XOR them together
6306 * and write the value to source port portion of compressed dword
6307 */
244e27ad 6308 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6309 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6310 else
244e27ad 6311 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6312 common.port.dst ^= th->source;
6313
244e27ad 6314 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6315 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6316 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6317 } else {
6318 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6319 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6320 hdr.ipv6->saddr.s6_addr32[1] ^
6321 hdr.ipv6->saddr.s6_addr32[2] ^
6322 hdr.ipv6->saddr.s6_addr32[3] ^
6323 hdr.ipv6->daddr.s6_addr32[0] ^
6324 hdr.ipv6->daddr.s6_addr32[1] ^
6325 hdr.ipv6->daddr.s6_addr32[2] ^
6326 hdr.ipv6->daddr.s6_addr32[3];
6327 }
c4cf55e5
PWJ		 6328
6329 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6330 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6331 input, common, ring->queue_index);
c4cf55e5
PWJ		 6332}
6333
63544e9c 6334static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6335{
fc77dc3c 6336 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6337 /* Herbert's original patch had:
6338 * smp_mb__after_netif_stop_queue();
6339 * but since that doesn't exist yet, just open code it. */
6340 smp_mb();
6341
6342 /* We need to check again in a case another CPU has just
6343 * made room available. */
7d4987de 6344 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6345 return -EBUSY;
6346
6347 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6348 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6349 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6350 return 0;
6351}
6352
82d4e46e 6353static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6354{
7d4987de 6355 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6356 return 0;
fc77dc3c 6357 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6358}
6359
09a3b1f8
SH		 6360static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6361{
6362 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6363 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6364 smp_processor_id();
56075a98 6365#ifdef IXGBE_FCOE
6440752c 6366 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6367
e5b64635
JF		 6368 if (((protocol == htons(ETH_P_FCOE)) ||
6369 (protocol == htons(ETH_P_FIP))) &&
6370 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6371 struct ixgbe_ring_feature *f;
6372
6373 f = &adapter->ring_feature[RING_F_FCOE];
6374
6375 while (txq >= f->indices)
6376 txq -= f->indices;
e4b317e9 6377 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6378
e5b64635 6379 return txq;
56075a98
JF		 6380 }
6381#endif
6382
fdd3d631
KK		 6383 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6384 while (unlikely(txq >= dev->real_num_tx_queues))
6385 txq -= dev->real_num_tx_queues;
5f715823 6386 return txq;
fdd3d631 6387 }
c4cf55e5 6388
09a3b1f8
SH		 6389 return skb_tx_hash(dev, skb);
6390}
6391
fc77dc3c 6392netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6393 struct ixgbe_adapter *adapter,
6394 struct ixgbe_ring *tx_ring)
9a799d71 6395{
d3d00239 6396 struct ixgbe_tx_buffer *first;
5f715823 6397 int tso;
d3d00239 6398 u32 tx_flags = 0;
a535c30e
AD		 6399#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6400 unsigned short f;
6401#endif
a535c30e 6402 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6403 __be16 protocol = skb->protocol;
63544e9c 6404 u8 hdr_len = 0;
5e09a105 6405
a535c30e
AD		 6406 /*
6407 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6408 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6409 * + 2 desc gap to keep tail from touching head,
6410 * + 1 desc for context descriptor,
6411 * otherwise try next time
6412 */
6413#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6414 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6415 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6416#else
6417 count += skb_shinfo(skb)->nr_frags;
6418#endif
6419 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6420 tx_ring->tx_stats.tx_busy++;
6421 return NETDEV_TX_BUSY;
6422 }
6423
fd0db0ed
AD		 6424 /* record the location of the first descriptor for this packet */
6425 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6426 first->skb = skb;
091a6246
AD		 6427 first->bytecount = skb->len;
6428 first->gso_segs = 1;
fd0db0ed 6429
66f32a8b 6430 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6431 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6432 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6433 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6434 /* else if it is a SW VLAN check the next protocol and store the tag */
6435 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6436 struct vlan_hdr *vhdr, _vhdr;
6437 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6438 if (!vhdr)
6439 goto out_drop;
6440
6441 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6442 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6443 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6444 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6445 }
6446
aa7bd467
JK		 6447 skb_tx_timestamp(skb);
6448
3a6a4eda
JK		 6449 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6450 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6451 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6452 }
3a6a4eda 6453
9e0c5648
AD		 6454#ifdef CONFIG_PCI_IOV
6455 /*
6456 * Use the l2switch_enable flag - would be false if the DMA
6457 * Tx switch had been disabled.
6458 */
6459 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6460 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6461
6462#endif
32701dc2 6463 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6464 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6465 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6466 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6467 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6468 tx_flags |= (skb->priority & 0x7) <<
6469 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6470 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6471 struct vlan_ethhdr *vhdr;
6472 if (skb_header_cloned(skb) &&
6473 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6474 goto out_drop;
6475 vhdr = (struct vlan_ethhdr *)skb->data;
6476 vhdr->h_vlan_TCI = htons(tx_flags >>
6477 IXGBE_TX_FLAGS_VLAN_SHIFT);
6478 } else {
6479 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6480 }
9a799d71 6481 }
eacd73f7 6482
244e27ad
AD		 6483 /* record initial flags and protocol */
6484 first->tx_flags = tx_flags;
6485 first->protocol = protocol;
6486
eacd73f7 6487#ifdef IXGBE_FCOE
66f32a8b
AD		 6488 /* setup tx offload for FCoE */
6489 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6490 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6491 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6492 if (tso < 0)
6493 goto out_drop;
9a799d71 6494
66f32a8b 6495 goto xmit_fcoe;
eacd73f7 6496 }
9a799d71 6497
66f32a8b 6498#endif /* IXGBE_FCOE */
244e27ad 6499 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6500 if (tso < 0)
897ab156 6501 goto out_drop;
244e27ad
AD		 6502 else if (!tso)
6503 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6504
6505 /* add the ATR filter if ATR is on */
6506 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6507 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6508
6509#ifdef IXGBE_FCOE
6510xmit_fcoe:
6511#endif /* IXGBE_FCOE */
244e27ad 6512 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6513
6514 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6515
6516 return NETDEV_TX_OK;
897ab156
AD		 6517
6518out_drop:
fd0db0ed
AD		 6519 dev_kfree_skb_any(first->skb);
6520 first->skb = NULL;
6521
897ab156 6522 return NETDEV_TX_OK;
9a799d71
AK		 6523}
6524
a50c29dd
AD		 6525static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6526 struct net_device *netdev)
84418e3b
AD		 6527{
6528 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6529 struct ixgbe_ring *tx_ring;
6530
a50c29dd
AD		 6531 /*
6532 * The minimum packet size for olinfo paylen is 17 so pad the skb
6533 * in order to meet this minimum size requirement.
6534 */
f73332fc
SH		 6535 if (unlikely(skb->len < 17)) {
6536 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6537 return NETDEV_TX_OK;
6538 skb->len = 17;
71a49f77 6539 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6540 }
6541
84418e3b 6542 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6543 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6544}
6545
9a799d71
AK		 6546/**
6547 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6548 * @netdev: network interface device structure
6549 * @p: pointer to an address structure
6550 *
6551 * Returns 0 on success, negative on failure
6552 **/
6553static int ixgbe_set_mac(struct net_device *netdev, void *p)
6554{
6555 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6556 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6557 struct sockaddr *addr = p;
6558
6559 if (!is_valid_ether_addr(addr->sa_data))
6560 return -EADDRNOTAVAIL;
6561
6562 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6563 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6564
1d9c0bfd 6565 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6566
6567 return 0;
6568}
6569
6b73e10d
BH		 6570static int
6571ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6572{
6573 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6574 struct ixgbe_hw *hw = &adapter->hw;
6575 u16 value;
6576 int rc;
6577
6578 if (prtad != hw->phy.mdio.prtad)
6579 return -EINVAL;
6580 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6581 if (!rc)
6582 rc = value;
6583 return rc;
6584}
6585
6586static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6587 u16 addr, u16 value)
6588{
6589 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6590 struct ixgbe_hw *hw = &adapter->hw;
6591
6592 if (prtad != hw->phy.mdio.prtad)
6593 return -EINVAL;
6594 return hw->phy.ops.write_reg(hw, addr, devad, value);
6595}
6596
6597static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6598{
6599 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6600
3a6a4eda 6601 switch (cmd) {
3a6a4eda
JK		 6602 case SIOCSHWTSTAMP:
6603 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6604 default:
6605 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6606 }
6b73e10d
BH		 6607}
6608
0365e6e4
PW		 6609/**
6610 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6611 * netdev->dev_addrs
0365e6e4
PW		 6612 * @netdev: network interface device structure
6613 *
6614 * Returns non-zero on failure
6615 **/
6616static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6617{
6618 int err = 0;
6619 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6620 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6621
7fa7c9dc 6622 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6623 rtnl_lock();
7fa7c9dc 6624 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6625 rtnl_unlock();
7fa7c9dc
AD		 6626
6627 /* update SAN MAC vmdq pool selection */
6628 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6629 }
6630 return err;
6631}
6632
6633/**
6634 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6635 * netdev->dev_addrs
0365e6e4
PW		 6636 * @netdev: network interface device structure
6637 *
6638 * Returns non-zero on failure
6639 **/
6640static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6641{
6642 int err = 0;
6643 struct ixgbe_adapter *adapter = netdev_priv(dev);
6644 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6645
6646 if (is_valid_ether_addr(mac->san_addr)) {
6647 rtnl_lock();
6648 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6649 rtnl_unlock();
6650 }
6651 return err;
6652}
6653
9a799d71
AK		 6654#ifdef CONFIG_NET_POLL_CONTROLLER
6655/*
6656 * Polling 'interrupt' - used by things like netconsole to send skbs
6657 * without having to re-enable interrupts. It's not called while
6658 * the interrupt routine is executing.
6659 */
6660static void ixgbe_netpoll(struct net_device *netdev)
6661{
6662 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6663 int i;
9a799d71 6664
1a647bd2
AD		 6665 /* if interface is down do nothing */
6666 if (test_bit(__IXGBE_DOWN, &adapter->state))
6667 return;
6668
9a799d71 6669 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6670 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6671 for (i = 0; i < adapter->num_q_vectors; i++)
6672 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6673 } else {
6674 ixgbe_intr(adapter->pdev->irq, netdev);
6675 }
9a799d71 6676 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6677}
9a799d71 6678
581330ba 6679#endif
de1036b1
ED		 6680static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6681 struct rtnl_link_stats64 *stats)
6682{
6683 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6684 int i;
6685
1a51502b 6686 rcu_read_lock();
de1036b1 6687 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6688 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6689 u64 bytes, packets;
6690 unsigned int start;
6691
1a51502b
ED		 6692 if (ring) {
6693 do {
6694 start = u64_stats_fetch_begin_bh(&ring->syncp);
6695 packets = ring->stats.packets;
6696 bytes = ring->stats.bytes;
6697 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6698 stats->rx_packets += packets;
6699 stats->rx_bytes += bytes;
6700 }
de1036b1 6701 }
1ac9ad13
ED		 6702
6703 for (i = 0; i < adapter->num_tx_queues; i++) {
6704 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6705 u64 bytes, packets;
6706 unsigned int start;
6707
6708 if (ring) {
6709 do {
6710 start = u64_stats_fetch_begin_bh(&ring->syncp);
6711 packets = ring->stats.packets;
6712 bytes = ring->stats.bytes;
6713 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6714 stats->tx_packets += packets;
6715 stats->tx_bytes += bytes;
6716 }
6717 }
1a51502b 6718 rcu_read_unlock();
de1036b1
ED		 6719 /* following stats updated by ixgbe_watchdog_task() */
6720 stats->multicast = netdev->stats.multicast;
6721 stats->rx_errors = netdev->stats.rx_errors;
6722 stats->rx_length_errors = netdev->stats.rx_length_errors;
6723 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6724 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6725 return stats;
6726}
6727
8af3c33f 6728#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6729/**
6730 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6731 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6732 * @tc: number of traffic classes currently enabled
6733 *
6734 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6735 * 802.1Q priority maps to a packet buffer that exists.
6736 */
6737static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6738{
6739 struct ixgbe_hw *hw = &adapter->hw;
6740 u32 reg, rsave;
6741 int i;
6742
6743 /* 82598 have a static priority to TC mapping that can not
6744 * be changed so no validation is needed.
6745 */
6746 if (hw->mac.type == ixgbe_mac_82598EB)
6747 return;
6748
6749 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6750 rsave = reg;
6751
6752 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6753 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6754
6755 /* If up2tc is out of bounds default to zero */
6756 if (up2tc > tc)
6757 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6758 }
6759
6760 if (reg != rsave)
6761 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6762
6763 return;
6764}
6765
02debdc9
AD		 6766/**
6767 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6768 * @adapter: Pointer to adapter struct
6769 *
6770 * Populate the netdev user priority to tc map
6771 */
6772static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6773{
6774 struct net_device *dev = adapter->netdev;
6775 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6776 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6777 u8 prio;
6778
6779 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6780 u8 tc = 0;
6781
6782 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6783 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6784 else if (ets)
6785 tc = ets->prio_tc[prio];
6786
6787 netdev_set_prio_tc_map(dev, prio, tc);
6788 }
6789}
6790
49ce9c2c
BH		 6791/**
6792 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6793 *
6794 * @netdev: net device to configure
6795 * @tc: number of traffic classes to enable
6796 */
6797int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6798{
8b1c0b24
JF		 6799 struct ixgbe_adapter *adapter = netdev_priv(dev);
6800 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6801
8b1c0b24 6802 /* Hardware supports up to 8 traffic classes */
4de2a022 6803 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6804 (hw->mac.type == ixgbe_mac_82598EB &&
6805 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6806 return -EINVAL;
6807
6808 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6809 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6810 * hardware is not flexible enough to do this dynamically.
6811 */
6812 if (netif_running(dev))
6813 ixgbe_close(dev);
6814 ixgbe_clear_interrupt_scheme(adapter);
6815
e7589eab 6816 if (tc) {
8b1c0b24 6817 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6818 ixgbe_set_prio_tc_map(adapter);
6819
e7589eab 6820 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6821
943561d3
AD		 6822 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6823 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6824 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6825 }
e7589eab 6826 } else {
8b1c0b24 6827 netdev_reset_tc(dev);
02debdc9 6828
943561d3
AD		 6829 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6830 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6831
6832 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6833
6834 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6835 adapter->dcb_cfg.pfc_mode_enable = false;
6836 }
6837
8b1c0b24
JF		 6838 ixgbe_init_interrupt_scheme(adapter);
6839 ixgbe_validate_rtr(adapter, tc);
6840 if (netif_running(dev))
6841 ixgbe_open(dev);
6842
6843 return 0;
6844}
de1036b1 6845
8af3c33f 6846#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6847void ixgbe_do_reset(struct net_device *netdev)
6848{
6849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6850
6851 if (netif_running(netdev))
6852 ixgbe_reinit_locked(adapter);
6853 else
6854 ixgbe_reset(adapter);
6855}
6856
c8f44aff 6857static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6858 netdev_features_t features)
082757af
DS		 6859{
6860 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6861
082757af 6862 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6863 if (!(features & NETIF_F_RXCSUM))
6864 features &= ~NETIF_F_LRO;
082757af 6865
567d2de2
AD		 6866 /* Turn off LRO if not RSC capable */
6867 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6868 features &= ~NETIF_F_LRO;
8e2813f5 6869
567d2de2 6870 return features;
082757af
DS		 6871}
6872
c8f44aff 6873static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6874 netdev_features_t features)
082757af
DS		 6875{
6876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6877 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6878 bool need_reset = false;
6879
082757af 6880 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6881 if (!(features & NETIF_F_LRO)) {
6882 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6883 need_reset = true;
567d2de2
AD		 6884 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6885 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6886 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6887 if (adapter->rx_itr_setting == 1 ||
6888 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6889 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6890 need_reset = true;
6891 } else if ((changed ^ features) & NETIF_F_LRO) {
6892 e_info(probe, "rx-usecs set too low, "
6893 "disabling RSC\n");
082757af
DS		 6894 }
6895 }
6896
6897 /*
6898 * Check if Flow Director n-tuple support was enabled or disabled. If
6899 * the state changed, we need to reset.
6900 */
39cb681b
AD		 6901 switch (features & NETIF_F_NTUPLE) {
6902 case NETIF_F_NTUPLE:
567d2de2 6903 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6904 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6905 need_reset = true;
6906
567d2de2
AD		 6907 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6908 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6909 break;
6910 default:
6911 /* turn off perfect filters, enable ATR and reset */
6912 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6913 need_reset = true;
6914
6915 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6916
6917 /* We cannot enable ATR if SR-IOV is enabled */
6918 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6919 break;
6920
6921 /* We cannot enable ATR if we have 2 or more traffic classes */
6922 if (netdev_get_num_tc(netdev) > 1)
6923 break;
6924
6925 /* We cannot enable ATR if RSS is disabled */
6926 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6927 break;
6928
6929 /* A sample rate of 0 indicates ATR disabled */
6930 if (!adapter->atr_sample_rate)
6931 break;
6932
6933 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6934 break;
082757af
DS		 6935 }
6936
146d4cc9
JF		 6937 if (features & NETIF_F_HW_VLAN_RX)
6938 ixgbe_vlan_strip_enable(adapter);
6939 else
6940 ixgbe_vlan_strip_disable(adapter);
6941
3f2d1c0f
BG		 6942 if (changed & NETIF_F_RXALL)
6943 need_reset = true;
6944
567d2de2 6945 netdev->features = features;
082757af
DS		 6946 if (need_reset)
6947 ixgbe_do_reset(netdev);
6948
6949 return 0;
082757af
DS		 6950}
6951
edc7d573 6952static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 6953 struct net_device *dev,
6b6e2725 6954 const unsigned char *addr,
0f4b0add
JF		 6955 u16 flags)
6956{
6957 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6958 int err;
6959
6960 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6961 return -EOPNOTSUPP;
0f4b0add 6962
b1ac1ef7
JF		 6963 /* Hardware does not support aging addresses so if a
6964 * ndm_state is given only allow permanent addresses
6965 */
6966 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 6967 pr_info("%s: FDB only supports static addresses\n",
6968 ixgbe_driver_name);
6969 return -EINVAL;
6970 }
6971
46acc460 6972 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 6973 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6974
6975 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6976 err = dev_uc_add_excl(dev, addr);
0f4b0add 6977 else
95447461
JF		 6978 err = -ENOMEM;
6979 } else if (is_multicast_ether_addr(addr)) {
6980 err = dev_mc_add_excl(dev, addr);
6981 } else {
6982 err = -EINVAL;
0f4b0add
JF		 6983 }
6984
6985 /* Only return duplicate errors if NLM_F_EXCL is set */
6986 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6987 err = 0;
6988
6989 return err;
6990}
6991
6992static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6993 struct net_device *dev,
6b6e2725 6994 const unsigned char *addr)
0f4b0add
JF		 6995{
6996 struct ixgbe_adapter *adapter = netdev_priv(dev);
6997 int err = -EOPNOTSUPP;
6998
6999 if (ndm->ndm_state & NUD_PERMANENT) {
7000 pr_info("%s: FDB only supports static addresses\n",
7001 ixgbe_driver_name);
7002 return -EINVAL;
7003 }
7004
7005 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7006 if (is_unicast_ether_addr(addr))
7007 err = dev_uc_del(dev, addr);
7008 else if (is_multicast_ether_addr(addr))
7009 err = dev_mc_del(dev, addr);
7010 else
7011 err = -EINVAL;
7012 }
7013
7014 return err;
7015}
7016
7017static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7018 struct netlink_callback *cb,
7019 struct net_device *dev,
7020 int idx)
7021{
7022 struct ixgbe_adapter *adapter = netdev_priv(dev);
7023
7024 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7025 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7026
7027 return idx;
7028}
7029
815cccbf
JF		 7030static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7031 struct nlmsghdr *nlh)
7032{
7033 struct ixgbe_adapter *adapter = netdev_priv(dev);
7034 struct nlattr *attr, *br_spec;
7035 int rem;
7036
7037 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7038 return -EOPNOTSUPP;
7039
7040 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7041
7042 nla_for_each_nested(attr, br_spec, rem) {
7043 __u16 mode;
7044 u32 reg = 0;
7045
7046 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7047 continue;
7048
7049 mode = nla_get_u16(attr);
9b735984 7050 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7051 reg = 0;
9b735984
GR		 7052 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7053 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7054 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7055 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7056 } else
815cccbf
JF		 7057 return -EINVAL;
7058
7059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7060
7061 e_info(drv, "enabling bridge mode: %s\n",
7062 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7063 }
7064
7065 return 0;
7066}
7067
7068static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7069 struct net_device *dev)
7070{
7071 struct ixgbe_adapter *adapter = netdev_priv(dev);
7072 u16 mode;
7073
7074 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7075 return 0;
7076
9b735984 7077 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7078 mode = BRIDGE_MODE_VEB;
7079 else
7080 mode = BRIDGE_MODE_VEPA;
7081
7082 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7083}
7084
0edc3527 7085static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7086 .ndo_open = ixgbe_open,
0edc3527 7087 .ndo_stop = ixgbe_close,
00829823 7088 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7089 .ndo_select_queue = ixgbe_select_queue,
581330ba 7090 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7091 .ndo_validate_addr = eth_validate_addr,
7092 .ndo_set_mac_address = ixgbe_set_mac,
7093 .ndo_change_mtu = ixgbe_change_mtu,
7094 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7095 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7096 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7097 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7098 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7099 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7100 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7101 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7102 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7103 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7104#ifdef CONFIG_IXGBE_DCB
24095aa3 7105 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7106#endif
0edc3527
SH		 7107#ifdef CONFIG_NET_POLL_CONTROLLER
7108 .ndo_poll_controller = ixgbe_netpoll,
7109#endif
332d4a7d
YZ		 7110#ifdef IXGBE_FCOE
7111 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7112 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7113 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7114 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7115 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7116 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7117 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7118#endif /* IXGBE_FCOE */
082757af
DS		 7119 .ndo_set_features = ixgbe_set_features,
7120 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 7121 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7122 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7123 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
815cccbf
JF		 7124 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7125 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7126};
7127
8e2813f5
JK		 7128/**
7129 * ixgbe_wol_supported - Check whether device supports WoL
7130 * @hw: hw specific details
7131 * @device_id: the device ID
7132 * @subdev_id: the subsystem device ID
7133 *
7134 * This function is used by probe and ethtool to determine
7135 * which devices have WoL support
7136 *
7137 **/
7138int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7139 u16 subdevice_id)
7140{
7141 struct ixgbe_hw *hw = &adapter->hw;
7142 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7143 int is_wol_supported = 0;
7144
7145 switch (device_id) {
7146 case IXGBE_DEV_ID_82599_SFP:
7147 /* Only these subdevices could supports WOL */
7148 switch (subdevice_id) {
7149 case IXGBE_SUBDEV_ID_82599_560FLR:
7150 /* only support first port */
7151 if (hw->bus.func != 0)
7152 break;
7153 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7154 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7155 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8e2813f5
JK		 7156 is_wol_supported = 1;
7157 break;
7158 }
7159 break;
7160 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7161 /* All except this subdevice support WOL */
7162 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7163 is_wol_supported = 1;
7164 break;
7165 case IXGBE_DEV_ID_82599_KX4:
7166 is_wol_supported = 1;
7167 break;
7168 case IXGBE_DEV_ID_X540T:
df376f0d 7169 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7170 /* check eeprom to see if enabled wol */
7171 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7172 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7173 (hw->bus.func == 0))) {
7174 is_wol_supported = 1;
7175 }
7176 break;
7177 }
7178
7179 return is_wol_supported;
7180}
7181
9a799d71
AK		 7182/**
7183 * ixgbe_probe - Device Initialization Routine
7184 * @pdev: PCI device information struct
7185 * @ent: entry in ixgbe_pci_tbl
7186 *
7187 * Returns 0 on success, negative on failure
7188 *
7189 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7190 * The OS initialization, configuring of the adapter private structure,
7191 * and a hardware reset occur.
7192 **/
1dd06ae8 7193static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7194{
7195 struct net_device *netdev;
7196 struct ixgbe_adapter *adapter = NULL;
7197 struct ixgbe_hw *hw;
7198 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7199 static int cards_found;
7200 int i, err, pci_using_dac;
289700db 7201 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7202 unsigned int indices = num_possible_cpus();
3f4a6f00 7203 unsigned int dcb_max = 0;
eacd73f7
YZ		 7204#ifdef IXGBE_FCOE
7205 u16 device_caps;
7206#endif
289700db 7207 u32 eec;
9a799d71 7208
bded64a7
AG		 7209 /* Catch broken hardware that put the wrong VF device ID in
7210 * the PCIe SR-IOV capability.
7211 */
7212 if (pdev->is_virtfn) {
7213 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7214 pci_name(pdev), pdev->vendor, pdev->device);
7215 return -EINVAL;
7216 }
7217
9ce77666 7218 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7219 if (err)
7220 return err;
7221
1b507730
NN		 7222 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7223 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7224 pci_using_dac = 1;
7225 } else {
1b507730 7226 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7227 if (err) {
1b507730
NN		 7228 err = dma_set_coherent_mask(&pdev->dev,
7229 DMA_BIT_MASK(32));
9a799d71 7230 if (err) {
b8bc0421
DC		 7231 dev_err(&pdev->dev,
7232 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7233 goto err_dma;
7234 }
7235 }
7236 pci_using_dac = 0;
7237 }
7238
9ce77666 7239 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7240 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7241 if (err) {
b8bc0421
DC		 7242 dev_err(&pdev->dev,
7243 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7244 goto err_pci_reg;
7245 }
7246
19d5afd4 7247 pci_enable_pcie_error_reporting(pdev);
6fabd715 7248
9a799d71 7249 pci_set_master(pdev);
fb3b27bc 7250 pci_save_state(pdev);
9a799d71 7251
e901acd6 7252#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7253 if (ii->mac == ixgbe_mac_82598EB)
7254 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7255 IXGBE_MAX_RSS_INDICES);
7256 else
7257 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7258 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7259#endif
7260
c85a2618
JF		 7261 if (ii->mac == ixgbe_mac_82598EB)
7262 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7263 else
7264 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7265
e901acd6 7266#ifdef IXGBE_FCOE
c85a2618
JF		 7267 indices += min_t(unsigned int, num_possible_cpus(),
7268 IXGBE_MAX_FCOE_INDICES);
7269#endif
3f4a6f00 7270 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7271 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7272 if (!netdev) {
7273 err = -ENOMEM;
7274 goto err_alloc_etherdev;
7275 }
7276
9a799d71
AK		 7277 SET_NETDEV_DEV(netdev, &pdev->dev);
7278
9a799d71 7279 adapter = netdev_priv(netdev);
c60fbb00 7280 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7281
7282 adapter->netdev = netdev;
7283 adapter->pdev = pdev;
7284 hw = &adapter->hw;
7285 hw->back = adapter;
b3f4d599 7286 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7287
05857980 7288 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7289 pci_resource_len(pdev, 0));
9a799d71
AK		 7290 if (!hw->hw_addr) {
7291 err = -EIO;
7292 goto err_ioremap;
7293 }
7294
0edc3527 7295 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7296 ixgbe_set_ethtool_ops(netdev);
9a799d71 7297 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7298 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7299
9a799d71
AK		 7300 adapter->bd_number = cards_found;
7301
9a799d71
AK		 7302 /* Setup hw api */
7303 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7304 hw->mac.type = ii->mac;
9a799d71 7305
c44ade9e
JB		 7306 /* EEPROM */
7307 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7308 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7309 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7310 if (!(eec & (1 << 8)))
7311 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7312
7313 /* PHY */
7314 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7315 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7316 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7317 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7318 hw->phy.mdio.mmds = 0;
7319 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7320 hw->phy.mdio.dev = netdev;
7321 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7322 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7323
8ca783ab 7324 ii->get_invariants(hw);
9a799d71
AK		 7325
7326 /* setup the private structure */
7327 err = ixgbe_sw_init(adapter);
7328 if (err)
7329 goto err_sw_init;
7330
e86bff0e 7331 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7332 switch (adapter->hw.mac.type) {
7333 case ixgbe_mac_82599EB:
7334 case ixgbe_mac_X540:
e86bff0e 7335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7336 break;
7337 default:
7338 break;
7339 }
e86bff0e 7340
bf069c97
DS		 7341 /*
7342 * If there is a fan on this device and it has failed log the
7343 * failure.
7344 */
7345 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7346 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7347 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7348 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7349 }
7350
8ef78adc
PWJ		 7351 if (allow_unsupported_sfp)
7352 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7353
c44ade9e 7354 /* reset_hw fills in the perm_addr as well */
119fc60a 7355 hw->phy.reset_if_overtemp = true;
c44ade9e 7356 err = hw->mac.ops.reset_hw(hw);
119fc60a 7357 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7358 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7359 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7360 err = 0;
7361 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7362 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7363 "module type was detected.\n");
7364 e_dev_err("Reload the driver after installing a supported "
7365 "module.\n");
04f165ef
PW		 7366 goto err_sw_init;
7367 } else if (err) {
849c4542 7368 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7369 goto err_sw_init;
7370 }
7371
99d74487
AD		 7372#ifdef CONFIG_PCI_IOV
7373 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7374
99d74487 7375#endif
396e799c 7376 netdev->features = NETIF_F_SG |
e8e9f696 7377 NETIF_F_IP_CSUM |
082757af 7378 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7379 NETIF_F_HW_VLAN_TX |
7380 NETIF_F_HW_VLAN_RX |
082757af
DS		 7381 NETIF_F_HW_VLAN_FILTER |
7382 NETIF_F_TSO |
7383 NETIF_F_TSO6 |
082757af
DS		 7384 NETIF_F_RXHASH |
7385 NETIF_F_RXCSUM;
9a799d71 7386
082757af 7387 netdev->hw_features = netdev->features;
ad31c402 7388
58be7666
DS		 7389 switch (adapter->hw.mac.type) {
7390 case ixgbe_mac_82599EB:
7391 case ixgbe_mac_X540:
45a5ead0 7392 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7393 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7394 NETIF_F_NTUPLE;
58be7666
DS		 7395 break;
7396 default:
7397 break;
7398 }
45a5ead0 7399
3f2d1c0f
BG		 7400 netdev->hw_features |= NETIF_F_RXALL;
7401
ad31c402
JK		 7402 netdev->vlan_features |= NETIF_F_TSO;
7403 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7404 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7405 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7406 netdev->vlan_features |= NETIF_F_SG;
7407
01789349 7408 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7409 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7410
7a6b6f51 7411#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7412 netdev->dcbnl_ops = &dcbnl_ops;
7413#endif
7414
eacd73f7 7415#ifdef IXGBE_FCOE
0d551589 7416 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7417 if (hw->mac.ops.get_device_caps) {
7418 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7419 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7420 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7421 }
7c8ae65a
AD		 7422
7423 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7424
a58915c7
AD		 7425 netdev->features |= NETIF_F_FSO |
7426 NETIF_F_FCOE_CRC;
7427
7c8ae65a
AD		 7428 netdev->vlan_features |= NETIF_F_FSO |
7429 NETIF_F_FCOE_CRC |
7430 NETIF_F_FCOE_MTU;
5e09d7f6 7431 }
eacd73f7 7432#endif /* IXGBE_FCOE */
7b872a55 7433 if (pci_using_dac) {
9a799d71 7434 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7435 netdev->vlan_features |= NETIF_F_HIGHDMA;
7436 }
9a799d71 7437
082757af
DS		 7438 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7439 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7440 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7441 netdev->features |= NETIF_F_LRO;
7442
9a799d71 7443 /* make sure the EEPROM is good */
c44ade9e 7444 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7445 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7446 err = -EIO;
35937c05 7447 goto err_sw_init;
9a799d71
AK		 7448 }
7449
7450 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7451 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7452
f8ebc683 7453 if (!is_valid_ether_addr(netdev->perm_addr)) {
849c4542 7454 e_dev_err("invalid MAC address\n");
9a799d71 7455 err = -EIO;
35937c05 7456 goto err_sw_init;
9a799d71
AK		 7457 }
7458
7086400d 7459 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7460 (unsigned long) adapter);
9a799d71 7461
7086400d
AD		 7462 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7463 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7464
021230d4
AV		 7465 err = ixgbe_init_interrupt_scheme(adapter);
7466 if (err)
7467 goto err_sw_init;
9a799d71 7468
8e2813f5 7469 /* WOL not supported for all devices */
c23f5b6b 7470 adapter->wol = 0;
8e2813f5
JK		 7471 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7472 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7473 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7474
e8e26350
PW		 7475 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7476
15e5209f
ET		 7477 /* save off EEPROM version number */
7478 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7479 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7480
04f165ef
PW		 7481 /* pick up the PCI bus settings for reporting later */
7482 hw->mac.ops.get_bus_info(hw);
7483
9a799d71 7484 /* print bus type/speed/width info */
849c4542 7485 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7486 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7487 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7488 "Unknown"),
7489 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7490 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7491 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7492 "Unknown"),
7493 netdev->dev_addr);
289700db
DS		 7494
7495 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7496 if (err)
9fe93afd 7497 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7498 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7499 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7500 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7501 part_str);
e8e26350 7502 else
289700db
DS		 7503 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7504 hw->mac.type, hw->phy.type, part_str);
9a799d71 7505
e8e26350 7506 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7507 e_dev_warn("PCI-Express bandwidth available for this card is "
7508 "not sufficient for optimal performance.\n");
7509 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7510 "is required.\n");
0c254d86
AK		 7511 }
7512
9a799d71 7513 /* reset the hardware with the new settings */
794caeb2 7514 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7515 if (err == IXGBE_ERR_EEPROM_VERSION) {
7516 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7517 e_dev_warn("This device is a pre-production adapter/LOM. "
7518 "Please be aware there may be issues associated "
7519 "with your hardware. If you are experiencing "
7520 "problems please contact your Intel or hardware "
7521 "representative who provided you with this "
7522 "hardware.\n");
794caeb2 7523 }
9a799d71
AK		 7524 strcpy(netdev->name, "eth%d");
7525 err = register_netdev(netdev);
7526 if (err)
7527 goto err_register;
7528
ec74a471
ET		 7529 /* power down the optics for 82599 SFP+ fiber */
7530 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7531 hw->mac.ops.disable_tx_laser(hw);
7532
54386467
JB		 7533 /* carrier off reporting is important to ethtool even BEFORE open */
7534 netif_carrier_off(netdev);
7535
5dd2d332 7536#ifdef CONFIG_IXGBE_DCA
652f093f 7537 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7538 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7539 ixgbe_setup_dca(adapter);
7540 }
7541#endif
1cdd1ec8 7542 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7543 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7544 for (i = 0; i < adapter->num_vfs; i++)
7545 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7546 }
7547
2466dd9c
JK		 7548 /* firmware requires driver version to be 0xFFFFFFFF
7549 * since os does not support feature
7550 */
9612de92 7551 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7552 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7553 0xFF);
9612de92 7554
0365e6e4
PW		 7555 /* add san mac addr to netdev */
7556 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7557
ea81875a 7558 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7559 cards_found++;
3ca8bc6d 7560
1210982b 7561#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7562 if (ixgbe_sysfs_init(adapter))
7563 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7564#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7565
00949167
CS		 7566#ifdef CONFIG_DEBUG_FS
7567 ixgbe_dbg_adapter_init(adapter);
7568#endif /* CONFIG_DEBUG_FS */
7569
9a799d71
AK		 7570 return 0;
7571
7572err_register:
5eba3699 7573 ixgbe_release_hw_control(adapter);
7a921c93 7574 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7575err_sw_init:
99d74487 7576 ixgbe_disable_sriov(adapter);
7086400d 7577 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7578 iounmap(hw->hw_addr);
7579err_ioremap:
7580 free_netdev(netdev);
7581err_alloc_etherdev:
e8e9f696
JP		 7582 pci_release_selected_regions(pdev,
7583 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7584err_pci_reg:
7585err_dma:
7586 pci_disable_device(pdev);
7587 return err;
7588}
7589
7590/**
7591 * ixgbe_remove - Device Removal Routine
7592 * @pdev: PCI device information struct
7593 *
7594 * ixgbe_remove is called by the PCI subsystem to alert the driver
7595 * that it should release a PCI device. The could be caused by a
7596 * Hot-Plug event, or because the driver is going to be removed from
7597 * memory.
7598 **/
9f9a12f8 7599static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 7600{
c60fbb00
AD		 7601 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7602 struct net_device *netdev = adapter->netdev;
9a799d71 7603
00949167
CS		 7604#ifdef CONFIG_DEBUG_FS
7605 ixgbe_dbg_adapter_exit(adapter);
7606#endif /*CONFIG_DEBUG_FS */
7607
9a799d71 7608 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7609 cancel_work_sync(&adapter->service_task);
9a799d71 7610
3a6a4eda 7611
5dd2d332 7612#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7613 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7614 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7615 dca_remove_requester(&pdev->dev);
7616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7617 }
7618
7619#endif
1210982b 7620#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7621 ixgbe_sysfs_exit(adapter);
1210982b 7622#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7623
0365e6e4
PW		 7624 /* remove the added san mac */
7625 ixgbe_del_sanmac_netdev(netdev);
7626
c4900be0
DS		 7627 if (netdev->reg_state == NETREG_REGISTERED)
7628 unregister_netdev(netdev);
9a799d71 7629
9297127b 7630 ixgbe_disable_sriov(adapter);
1cdd1ec8 7631
7a921c93 7632 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7633
021230d4 7634 ixgbe_release_hw_control(adapter);
9a799d71 7635
2b1588c3
AD		 7636#ifdef CONFIG_DCB
7637 kfree(adapter->ixgbe_ieee_pfc);
7638 kfree(adapter->ixgbe_ieee_ets);
7639
7640#endif
9a799d71 7641 iounmap(adapter->hw.hw_addr);
9ce77666 7642 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7643 IORESOURCE_MEM));
9a799d71 7644
849c4542 7645 e_dev_info("complete\n");
021230d4 7646
9a799d71
AK		 7647 free_netdev(netdev);
7648
19d5afd4 7649 pci_disable_pcie_error_reporting(pdev);
6fabd715 7650
9a799d71
AK		 7651 pci_disable_device(pdev);
7652}
7653
7654/**
7655 * ixgbe_io_error_detected - called when PCI error is detected
7656 * @pdev: Pointer to PCI device
7657 * @state: The current pci connection state
7658 *
7659 * This function is called after a PCI bus error affecting
7660 * this device has been detected.
7661 */
7662static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7663 pci_channel_state_t state)
9a799d71 7664{
c60fbb00
AD		 7665 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7666 struct net_device *netdev = adapter->netdev;
9a799d71 7667
83c61fa9
GR		 7668#ifdef CONFIG_PCI_IOV
7669 struct pci_dev *bdev, *vfdev;
7670 u32 dw0, dw1, dw2, dw3;
7671 int vf, pos;
7672 u16 req_id, pf_func;
7673
7674 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7675 adapter->num_vfs == 0)
7676 goto skip_bad_vf_detection;
7677
7678 bdev = pdev->bus->self;
62f87c0e 7679 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7680 bdev = bdev->bus->self;
7681
7682 if (!bdev)
7683 goto skip_bad_vf_detection;
7684
7685 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7686 if (!pos)
7687 goto skip_bad_vf_detection;
7688
7689 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7690 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7691 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7692 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7693
7694 req_id = dw1 >> 16;
7695 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7696 if (!(req_id & 0x0080))
7697 goto skip_bad_vf_detection;
7698
7699 pf_func = req_id & 0x01;
7700 if ((pf_func & 1) == (pdev->devfn & 1)) {
7701 unsigned int device_id;
7702
7703 vf = (req_id & 0x7F) >> 1;
7704 e_dev_err("VF %d has caused a PCIe error\n", vf);
7705 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7706 "%8.8x\tdw3: %8.8x\n",
7707 dw0, dw1, dw2, dw3);
7708 switch (adapter->hw.mac.type) {
7709 case ixgbe_mac_82599EB:
7710 device_id = IXGBE_82599_VF_DEVICE_ID;
7711 break;
7712 case ixgbe_mac_X540:
7713 device_id = IXGBE_X540_VF_DEVICE_ID;
7714 break;
7715 default:
7716 device_id = 0;
7717 break;
7718 }
7719
7720 /* Find the pci device of the offending VF */
36e90319 7721 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7722 while (vfdev) {
7723 if (vfdev->devfn == (req_id & 0xFF))
7724 break;
36e90319 7725 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7726 device_id, vfdev);
7727 }
7728 /*
7729 * There's a slim chance the VF could have been hot plugged,
7730 * so if it is no longer present we don't need to issue the
7731 * VFLR. Just clean up the AER in that case.
7732 */
7733 if (vfdev) {
7734 e_dev_err("Issuing VFLR to VF %d\n", vf);
7735 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7736 }
7737
7738 pci_cleanup_aer_uncorrect_error_status(pdev);
7739 }
7740
7741 /*
7742 * Even though the error may have occurred on the other port
7743 * we still need to increment the vf error reference count for
7744 * both ports because the I/O resume function will be called
7745 * for both of them.
7746 */
7747 adapter->vferr_refcount++;
7748
7749 return PCI_ERS_RESULT_RECOVERED;
7750
7751skip_bad_vf_detection:
7752#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7753 netif_device_detach(netdev);
7754
3044b8d1
BL		 7755 if (state == pci_channel_io_perm_failure)
7756 return PCI_ERS_RESULT_DISCONNECT;
7757
9a799d71
AK		 7758 if (netif_running(netdev))
7759 ixgbe_down(adapter);
7760 pci_disable_device(pdev);
7761
b4617240 7762 /* Request a slot reset. */
9a799d71
AK		 7763 return PCI_ERS_RESULT_NEED_RESET;
7764}
7765
7766/**
7767 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7768 * @pdev: Pointer to PCI device
7769 *
7770 * Restart the card from scratch, as if from a cold-boot.
7771 */
7772static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7773{
c60fbb00 7774 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7775 pci_ers_result_t result;
7776 int err;
9a799d71 7777
9ce77666 7778 if (pci_enable_device_mem(pdev)) {
396e799c 7779 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7780 result = PCI_ERS_RESULT_DISCONNECT;
7781 } else {
7782 pci_set_master(pdev);
7783 pci_restore_state(pdev);
c0e1f68b 7784 pci_save_state(pdev);
9a799d71 7785
dd4d8ca6 7786 pci_wake_from_d3(pdev, false);
9a799d71 7787
6fabd715 7788 ixgbe_reset(adapter);
88512539 7789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7790 result = PCI_ERS_RESULT_RECOVERED;
7791 }
7792
7793 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7794 if (err) {
849c4542
ET		 7795 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7796 "failed 0x%0x\n", err);
6fabd715
PWJ		 7797 /* non-fatal, continue */
7798 }
9a799d71 7799
6fabd715 7800 return result;
9a799d71
AK		 7801}
7802
7803/**
7804 * ixgbe_io_resume - called when traffic can start flowing again.
7805 * @pdev: Pointer to PCI device
7806 *
7807 * This callback is called when the error recovery driver tells us that
7808 * its OK to resume normal operation.
7809 */
7810static void ixgbe_io_resume(struct pci_dev *pdev)
7811{
c60fbb00
AD		 7812 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7813 struct net_device *netdev = adapter->netdev;
9a799d71 7814
83c61fa9
GR		 7815#ifdef CONFIG_PCI_IOV
7816 if (adapter->vferr_refcount) {
7817 e_info(drv, "Resuming after VF err\n");
7818 adapter->vferr_refcount--;
7819 return;
7820 }
7821
7822#endif
c7ccde0f
AD		 7823 if (netif_running(netdev))
7824 ixgbe_up(adapter);
9a799d71
AK		 7825
7826 netif_device_attach(netdev);
9a799d71
AK		 7827}
7828
3646f0e5 7829static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7830 .error_detected = ixgbe_io_error_detected,
7831 .slot_reset = ixgbe_io_slot_reset,
7832 .resume = ixgbe_io_resume,
7833};
7834
7835static struct pci_driver ixgbe_driver = {
7836 .name = ixgbe_driver_name,
7837 .id_table = ixgbe_pci_tbl,
7838 .probe = ixgbe_probe,
9f9a12f8 7839 .remove = ixgbe_remove,
9a799d71
AK		 7840#ifdef CONFIG_PM
7841 .suspend = ixgbe_suspend,
7842 .resume = ixgbe_resume,
7843#endif
7844 .shutdown = ixgbe_shutdown,
7845 .err_handler = &ixgbe_err_handler
7846};
7847
7848/**
7849 * ixgbe_init_module - Driver Registration Routine
7850 *
7851 * ixgbe_init_module is the first routine called when the driver is
7852 * loaded. All it does is register with the PCI subsystem.
7853 **/
7854static int __init ixgbe_init_module(void)
7855{
7856 int ret;
c7689578 7857 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7858 pr_info("%s\n", ixgbe_copyright);
9a799d71 7859
00949167
CS		 7860#ifdef CONFIG_DEBUG_FS
7861 ixgbe_dbg_init();
7862#endif /* CONFIG_DEBUG_FS */
7863
5dd2d332 7864#ifdef CONFIG_IXGBE_DCA
bd0362dd 7865 dca_register_notify(&dca_notifier);
bd0362dd 7866#endif
5dd2d332 7867
9a799d71
AK		 7868 ret = pci_register_driver(&ixgbe_driver);
7869 return ret;
7870}
b4617240 7871
9a799d71
AK		 7872module_init(ixgbe_init_module);
7873
7874/**
7875 * ixgbe_exit_module - Driver Exit Cleanup Routine
7876 *
7877 * ixgbe_exit_module is called just before the driver is removed
7878 * from memory.
7879 **/
7880static void __exit ixgbe_exit_module(void)
7881{
5dd2d332 7882#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7883 dca_unregister_notify(&dca_notifier);
7884#endif
9a799d71 7885 pci_unregister_driver(&ixgbe_driver);
00949167
CS		 7886
7887#ifdef CONFIG_DEBUG_FS
7888 ixgbe_dbg_exit();
7889#endif /* CONFIG_DEBUG_FS */
7890
1a51502b 7891 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7892}
bd0362dd 7893
5dd2d332 7894#ifdef CONFIG_IXGBE_DCA
bd0362dd 7895static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7896 void *p)
bd0362dd
JC		 7897{
7898 int ret_val;
7899
7900 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7901 __ixgbe_notify_dca);
bd0362dd
JC		 7902
7903 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7904}
b453368d 7905
5dd2d332 7906#endif /* CONFIG_IXGBE_DCA */
849c4542 7907
9a799d71
AK		 7908module_exit(ixgbe_exit_module);
7909
7910/* ixgbe_main.c */
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