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ixgbe: Fix case of Tx Hang in PF with 32 VFs
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
9a799d71
AK		 134MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
135MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
136MODULE_LICENSE("GPL");
137MODULE_VERSION(DRV_VERSION);
138
139#define DEFAULT_DEBUG_LEVEL_SHIFT 3
140
7086400d
AD		 141static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
142{
143 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
144 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
145 schedule_work(&adapter->service_task);
146}
147
148static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
149{
150 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
151
52f33af8 152 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 153 smp_mb__before_clear_bit();
154 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
155}
156
dcd79aeb
TI		 157struct ixgbe_reg_info {
158 u32 ofs;
159 char *name;
160};
161
162static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
163
164 /* General Registers */
165 {IXGBE_CTRL, "CTRL"},
166 {IXGBE_STATUS, "STATUS"},
167 {IXGBE_CTRL_EXT, "CTRL_EXT"},
168
169 /* Interrupt Registers */
170 {IXGBE_EICR, "EICR"},
171
172 /* RX Registers */
173 {IXGBE_SRRCTL(0), "SRRCTL"},
174 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
175 {IXGBE_RDLEN(0), "RDLEN"},
176 {IXGBE_RDH(0), "RDH"},
177 {IXGBE_RDT(0), "RDT"},
178 {IXGBE_RXDCTL(0), "RXDCTL"},
179 {IXGBE_RDBAL(0), "RDBAL"},
180 {IXGBE_RDBAH(0), "RDBAH"},
181
182 /* TX Registers */
183 {IXGBE_TDBAL(0), "TDBAL"},
184 {IXGBE_TDBAH(0), "TDBAH"},
185 {IXGBE_TDLEN(0), "TDLEN"},
186 {IXGBE_TDH(0), "TDH"},
187 {IXGBE_TDT(0), "TDT"},
188 {IXGBE_TXDCTL(0), "TXDCTL"},
189
190 /* List Terminator */
191 {}
192};
193
194
195/*
196 * ixgbe_regdump - register printout routine
197 */
198static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
199{
200 int i = 0, j = 0;
201 char rname[16];
202 u32 regs[64];
203
204 switch (reginfo->ofs) {
205 case IXGBE_SRRCTL(0):
206 for (i = 0; i < 64; i++)
207 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
208 break;
209 case IXGBE_DCA_RXCTRL(0):
210 for (i = 0; i < 64; i++)
211 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
212 break;
213 case IXGBE_RDLEN(0):
214 for (i = 0; i < 64; i++)
215 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
216 break;
217 case IXGBE_RDH(0):
218 for (i = 0; i < 64; i++)
219 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
220 break;
221 case IXGBE_RDT(0):
222 for (i = 0; i < 64; i++)
223 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
224 break;
225 case IXGBE_RXDCTL(0):
226 for (i = 0; i < 64; i++)
227 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
228 break;
229 case IXGBE_RDBAL(0):
230 for (i = 0; i < 64; i++)
231 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
232 break;
233 case IXGBE_RDBAH(0):
234 for (i = 0; i < 64; i++)
235 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
236 break;
237 case IXGBE_TDBAL(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
240 break;
241 case IXGBE_TDBAH(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
244 break;
245 case IXGBE_TDLEN(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
248 break;
249 case IXGBE_TDH(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
252 break;
253 case IXGBE_TDT(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
256 break;
257 case IXGBE_TXDCTL(0):
258 for (i = 0; i < 64; i++)
259 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
260 break;
261 default:
c7689578 262 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 263 IXGBE_READ_REG(hw, reginfo->ofs));
264 return;
265 }
266
267 for (i = 0; i < 8; i++) {
268 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 269 pr_err("%-15s", rname);
dcd79aeb 270 for (j = 0; j < 8; j++)
c7689578
JP		 271 pr_cont(" %08x", regs[i*8+j]);
272 pr_cont("\n");
dcd79aeb
TI		 273 }
274
275}
276
277/*
278 * ixgbe_dump - Print registers, tx-rings and rx-rings
279 */
280static void ixgbe_dump(struct ixgbe_adapter *adapter)
281{
282 struct net_device *netdev = adapter->netdev;
283 struct ixgbe_hw *hw = &adapter->hw;
284 struct ixgbe_reg_info *reginfo;
285 int n = 0;
286 struct ixgbe_ring *tx_ring;
287 struct ixgbe_tx_buffer *tx_buffer_info;
288 union ixgbe_adv_tx_desc *tx_desc;
289 struct my_u0 { u64 a; u64 b; } *u0;
290 struct ixgbe_ring *rx_ring;
291 union ixgbe_adv_rx_desc *rx_desc;
292 struct ixgbe_rx_buffer *rx_buffer_info;
293 u32 staterr;
294 int i = 0;
295
296 if (!netif_msg_hw(adapter))
297 return;
298
299 /* Print netdevice Info */
300 if (netdev) {
301 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 302 pr_info("Device Name state "
dcd79aeb 303 "trans_start last_rx\n");
c7689578
JP		 304 pr_info("%-15s %016lX %016lX %016lX\n",
305 netdev->name,
306 netdev->state,
307 netdev->trans_start,
308 netdev->last_rx);
dcd79aeb
TI		 309 }
310
311 /* Print Registers */
312 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 313 pr_info(" Register Name Value\n");
dcd79aeb
TI		 314 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
315 reginfo->name; reginfo++) {
316 ixgbe_regdump(hw, reginfo);
317 }
318
319 /* Print TX Ring Summary */
320 if (!netdev || !netif_running(netdev))
321 goto exit;
322
323 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 324 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 325 for (n = 0; n < adapter->num_tx_queues; n++) {
326 tx_ring = adapter->tx_ring[n];
327 tx_buffer_info =
328 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 329 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 330 n, tx_ring->next_to_use, tx_ring->next_to_clean,
331 (u64)tx_buffer_info->dma,
332 tx_buffer_info->length,
333 tx_buffer_info->next_to_watch,
334 (u64)tx_buffer_info->time_stamp);
335 }
336
337 /* Print TX Rings */
338 if (!netif_msg_tx_done(adapter))
339 goto rx_ring_summary;
340
341 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
342
343 /* Transmit Descriptor Formats
344 *
345 * Advanced Transmit Descriptor
346 * +--------------------------------------------------------------+
347 * 0 | Buffer Address [63:0] |
348 * +--------------------------------------------------------------+
349 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
350 * +--------------------------------------------------------------+
351 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
352 */
353
354 for (n = 0; n < adapter->num_tx_queues; n++) {
355 tx_ring = adapter->tx_ring[n];
c7689578
JP		 356 pr_info("------------------------------------\n");
357 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
358 pr_info("------------------------------------\n");
359 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 360 "[PlPOIdStDDt Ln] [bi->dma ] "
361 "leng ntw timestamp bi->skb\n");
362
363 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 364 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 365 tx_buffer_info = &tx_ring->tx_buffer_info[i];
366 u0 = (struct my_u0 *)tx_desc;
c7689578 367 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 368 " %04X %p %016llX %p", i,
dcd79aeb
TI		 369 le64_to_cpu(u0->a),
370 le64_to_cpu(u0->b),
371 (u64)tx_buffer_info->dma,
372 tx_buffer_info->length,
373 tx_buffer_info->next_to_watch,
374 (u64)tx_buffer_info->time_stamp,
375 tx_buffer_info->skb);
376 if (i == tx_ring->next_to_use &&
377 i == tx_ring->next_to_clean)
c7689578 378 pr_cont(" NTC/U\n");
dcd79aeb 379 else if (i == tx_ring->next_to_use)
c7689578 380 pr_cont(" NTU\n");
dcd79aeb 381 else if (i == tx_ring->next_to_clean)
c7689578 382 pr_cont(" NTC\n");
dcd79aeb 383 else
c7689578 384 pr_cont("\n");
dcd79aeb
TI		 385
386 if (netif_msg_pktdata(adapter) &&
387 tx_buffer_info->dma != 0)
388 print_hex_dump(KERN_INFO, "",
389 DUMP_PREFIX_ADDRESS, 16, 1,
390 phys_to_virt(tx_buffer_info->dma),
391 tx_buffer_info->length, true);
392 }
393 }
394
395 /* Print RX Rings Summary */
396rx_ring_summary:
397 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 398 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 399 for (n = 0; n < adapter->num_rx_queues; n++) {
400 rx_ring = adapter->rx_ring[n];
c7689578
JP		 401 pr_info("%5d %5X %5X\n",
402 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 403 }
404
405 /* Print RX Rings */
406 if (!netif_msg_rx_status(adapter))
407 goto exit;
408
409 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
410
411 /* Advanced Receive Descriptor (Read) Format
412 * 63 1 0
413 * +-----------------------------------------------------+
414 * 0 | Packet Buffer Address [63:1] |A0/NSE|
415 * +----------------------------------------------+------+
416 * 8 | Header Buffer Address [63:1] | DD |
417 * +-----------------------------------------------------+
418 *
419 *
420 * Advanced Receive Descriptor (Write-Back) Format
421 *
422 * 63 48 47 32 31 30 21 20 16 15 4 3 0
423 * +------------------------------------------------------+
424 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
425 * | Checksum Ident | | | | Type | Type |
426 * +------------------------------------------------------+
427 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
428 * +------------------------------------------------------+
429 * 63 48 47 32 31 20 19 0
430 */
431 for (n = 0; n < adapter->num_rx_queues; n++) {
432 rx_ring = adapter->rx_ring[n];
c7689578
JP		 433 pr_info("------------------------------------\n");
434 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
435 pr_info("------------------------------------\n");
436 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 437 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
438 "<-- Adv Rx Read format\n");
c7689578 439 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 440 "[vl er S cks ln] ---------------- [bi->skb] "
441 "<-- Adv Rx Write-Back format\n");
442
443 for (i = 0; i < rx_ring->count; i++) {
444 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 445 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 446 u0 = (struct my_u0 *)rx_desc;
447 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
448 if (staterr & IXGBE_RXD_STAT_DD) {
449 /* Descriptor Done */
c7689578 450 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 451 "%016llX ---------------- %p", i,
452 le64_to_cpu(u0->a),
453 le64_to_cpu(u0->b),
454 rx_buffer_info->skb);
455 } else {
c7689578 456 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 457 "%016llX %016llX %p", i,
458 le64_to_cpu(u0->a),
459 le64_to_cpu(u0->b),
460 (u64)rx_buffer_info->dma,
461 rx_buffer_info->skb);
462
463 if (netif_msg_pktdata(adapter)) {
464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS, 16, 1,
466 phys_to_virt(rx_buffer_info->dma),
467 rx_ring->rx_buf_len, true);
468
469 if (rx_ring->rx_buf_len
919e78a6 470 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 471 print_hex_dump(KERN_INFO, "",
472 DUMP_PREFIX_ADDRESS, 16, 1,
473 phys_to_virt(
474 rx_buffer_info->page_dma +
475 rx_buffer_info->page_offset
476 ),
477 PAGE_SIZE/2, true);
478 }
479 }
480
481 if (i == rx_ring->next_to_use)
c7689578 482 pr_cont(" NTU\n");
dcd79aeb 483 else if (i == rx_ring->next_to_clean)
c7689578 484 pr_cont(" NTC\n");
dcd79aeb 485 else
c7689578 486 pr_cont("\n");
dcd79aeb
TI		 487
488 }
489 }
490
491exit:
492 return;
493}
494
5eba3699
AV		 495static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
496{
497 u32 ctrl_ext;
498
499 /* Let firmware take over control of h/w */
500 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
501 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 502 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 503}
504
505static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
506{
507 u32 ctrl_ext;
508
509 /* Let firmware know the driver has taken over */
510 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
511 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 512 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 513}
9a799d71 514
e8e26350
PW		 515/*
516 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
517 * @adapter: pointer to adapter struct
518 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
519 * @queue: queue to map the corresponding interrupt to
520 * @msix_vector: the vector to map to the corresponding queue
521 *
522 */
523static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 524 u8 queue, u8 msix_vector)
9a799d71
AK		 525{
526 u32 ivar, index;
e8e26350
PW		 527 struct ixgbe_hw *hw = &adapter->hw;
528 switch (hw->mac.type) {
529 case ixgbe_mac_82598EB:
530 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
531 if (direction == -1)
532 direction = 0;
533 index = (((direction * 64) + queue) >> 2) & 0x1F;
534 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
535 ivar &= ~(0xFF << (8 * (queue & 0x3)));
536 ivar |= (msix_vector << (8 * (queue & 0x3)));
537 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
538 break;
539 case ixgbe_mac_82599EB:
b93a2226 540 case ixgbe_mac_X540:
e8e26350
PW		 541 if (direction == -1) {
542 /* other causes */
543 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
544 index = ((queue & 1) * 8);
545 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
546 ivar &= ~(0xFF << index);
547 ivar |= (msix_vector << index);
548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
549 break;
550 } else {
551 /* tx or rx causes */
552 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
553 index = ((16 * (queue & 1)) + (8 * direction));
554 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
555 ivar &= ~(0xFF << index);
556 ivar |= (msix_vector << index);
557 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
558 break;
559 }
560 default:
561 break;
562 }
9a799d71
AK		 563}
564
fe49f04a 565static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 566 u64 qmask)
fe49f04a
AD		 567{
568 u32 mask;
569
bd508178
AD		 570 switch (adapter->hw.mac.type) {
571 case ixgbe_mac_82598EB:
fe49f04a
AD		 572 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 574 break;
575 case ixgbe_mac_82599EB:
b93a2226 576 case ixgbe_mac_X540:
fe49f04a
AD		 577 mask = (qmask & 0xFFFFFFFF);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
579 mask = (qmask >> 32);
580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 581 break;
582 default:
583 break;
fe49f04a
AD		 584 }
585}
586
d3d00239
AD		 587static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
588 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 589{
d3d00239
AD		 590 if (tx_buffer->dma) {
591 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
592 dma_unmap_page(ring->dev,
593 tx_buffer->dma,
594 tx_buffer->length,
595 DMA_TO_DEVICE);
e5a43549 596 else
d3d00239
AD		 597 dma_unmap_single(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 }
d3d00239
AD		 602 tx_buffer->dma = 0;
603}
604
605void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
606 struct ixgbe_tx_buffer *tx_buffer_info)
607{
608 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
609 if (tx_buffer_info->skb)
9a799d71 610 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 611 tx_buffer_info->skb = NULL;
9a799d71
AK		 612 /* tx_buffer_info must be completely set up in the transmit path */
613}
614
c84d324c
JF		 615static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
616{
617 struct ixgbe_hw *hw = &adapter->hw;
618 struct ixgbe_hw_stats *hwstats = &adapter->stats;
619 u32 data = 0;
620 u32 xoff[8] = {0};
621 int i;
622
623 if ((hw->fc.current_mode == ixgbe_fc_full) ||
624 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
625 switch (hw->mac.type) {
626 case ixgbe_mac_82598EB:
627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 628 break;
629 default:
c84d324c
JF		 630 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
631 }
632 hwstats->lxoffrxc += data;
633
634 /* refill credits (no tx hang) if we received xoff */
635 if (!data)
636 return;
637
638 for (i = 0; i < adapter->num_tx_queues; i++)
639 clear_bit(__IXGBE_HANG_CHECK_ARMED,
640 &adapter->tx_ring[i]->state);
641 return;
642 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
643 return;
644
645 /* update stats for each tc, only valid with PFC enabled */
646 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
647 switch (hw->mac.type) {
648 case ixgbe_mac_82598EB:
649 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 650 break;
c84d324c
JF		 651 default:
652 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 653 }
c84d324c
JF		 654 hwstats->pxoffrxc[i] += xoff[i];
655 }
656
657 /* disarm tx queues that have received xoff frames */
658 for (i = 0; i < adapter->num_tx_queues; i++) {
659 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 660 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 661
662 if (xoff[tc])
663 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 664 }
26f23d82
YZ		 665}
666
c84d324c 667static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 668{
c84d324c
JF		 669 return ring->tx_stats.completed;
670}
671
672static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
673{
674 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 675 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 676
c84d324c
JF		 677 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
678 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
679
680 if (head != tail)
681 return (head < tail) ?
682 tail - head : (tail + ring->count - head);
683
684 return 0;
685}
686
687static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
688{
689 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
690 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
691 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
692 bool ret = false;
693
7d637bcc 694 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 695
696 /*
697 * Check for a hung queue, but be thorough. This verifies
698 * that a transmit has been completed since the previous
699 * check AND there is at least one packet pending. The
700 * ARMED bit is set to indicate a potential hang. The
701 * bit is cleared if a pause frame is received to remove
702 * false hang detection due to PFC or 802.3x frames. By
703 * requiring this to fail twice we avoid races with
704 * pfc clearing the ARMED bit and conditions where we
705 * run the check_tx_hang logic with a transmit completion
706 * pending but without time to complete it yet.
707 */
708 if ((tx_done_old == tx_done) && tx_pending) {
709 /* make sure it is true for two checks in a row */
710 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
711 &tx_ring->state);
712 } else {
713 /* update completed stats and continue */
714 tx_ring->tx_stats.tx_done_old = tx_done;
715 /* reset the countdown */
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 717 }
718
c84d324c 719 return ret;
9a799d71
AK		 720}
721
c83c6cbd
AD		 722/**
723 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
724 * @adapter: driver private struct
725 **/
726static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
727{
728
729 /* Do the reset outside of interrupt context */
730 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
731 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
732 ixgbe_service_event_schedule(adapter);
733 }
734}
e01c31a5 735
9a799d71
AK		 736/**
737 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 738 * @q_vector: structure containing interrupt and ring information
e01c31a5 739 * @tx_ring: tx ring to clean
9a799d71 740 **/
fe49f04a 741static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 742 struct ixgbe_ring *tx_ring)
9a799d71 743{
fe49f04a 744 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 745 struct ixgbe_tx_buffer *tx_buffer;
746 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 747 unsigned int total_bytes = 0, total_packets = 0;
59224555 748 unsigned int budget = q_vector->tx.work_limit;
d3d00239 749 u16 i = tx_ring->next_to_clean;
9a799d71 750
d3d00239
AD		 751 tx_buffer = &tx_ring->tx_buffer_info[i];
752 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 753
30065e63 754 for (; budget; budget--) {
d3d00239
AD		 755 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
756
757 /* if next_to_watch is not set then there is no work pending */
758 if (!eop_desc)
759 break;
760
761 /* if DD is not set pending work has not been completed */
762 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
763 break;
8ad494b0 764
d3d00239
AD		 765 /* count the packet as being completed */
766 tx_ring->tx_stats.completed++;
767
768 /* clear next_to_watch to prevent false hangs */
769 tx_buffer->next_to_watch = NULL;
8ad494b0 770
d3d00239
AD		 771 /* prevent any other reads prior to eop_desc being verified */
772 rmb();
773
774 do {
775 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 776 tx_desc->wb.status = 0;
d3d00239
AD		 777 if (likely(tx_desc == eop_desc)) {
778 eop_desc = NULL;
779 dev_kfree_skb_any(tx_buffer->skb);
780 tx_buffer->skb = NULL;
781
782 total_bytes += tx_buffer->bytecount;
783 total_packets += tx_buffer->gso_segs;
784 }
9a799d71 785
d3d00239
AD		 786 tx_buffer++;
787 tx_desc++;
8ad494b0 788 i++;
d3d00239 789 if (unlikely(i == tx_ring->count)) {
8ad494b0 790 i = 0;
e01c31a5 791
d3d00239
AD		 792 tx_buffer = tx_ring->tx_buffer_info;
793 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 794 }
e01c31a5 795
d3d00239 796 } while (eop_desc);
12207e49
PWJ		 797 }
798
9a799d71 799 tx_ring->next_to_clean = i;
d3d00239 800 u64_stats_update_begin(&tx_ring->syncp);
b953799e 801 tx_ring->stats.bytes += total_bytes;
bd198058 802 tx_ring->stats.packets += total_packets;
d3d00239 803 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 804 q_vector->tx.total_bytes += total_bytes;
805 q_vector->tx.total_packets += total_packets;
b953799e 806
c84d324c
JF		 807 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
808 /* schedule immediate reset if we believe we hung */
809 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 810 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 811 e_err(drv, "Detected Tx Unit Hang\n"
812 " Tx Queue <%d>\n"
813 " TDH, TDT <%x>, <%x>\n"
814 " next_to_use <%x>\n"
815 " next_to_clean <%x>\n"
816 "tx_buffer_info[next_to_clean]\n"
817 " time_stamp <%lx>\n"
818 " jiffies <%lx>\n",
819 tx_ring->queue_index,
820 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
821 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 822 tx_ring->next_to_use, i,
823 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 824
825 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
826
827 e_info(probe,
828 "tx hang %d detected on queue %d, resetting adapter\n",
829 adapter->tx_timeout_count + 1, tx_ring->queue_index);
830
b953799e 831 /* schedule immediate reset if we believe we hung */
c83c6cbd 832 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 833
834 /* the adapter is about to reset, no point in enabling stuff */
59224555 835 return true;
b953799e 836 }
9a799d71 837
e092be60 838#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 839 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 840 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 841 /* Make sure that anybody stopping the queue after this
842 * sees the new next_to_clean.
843 */
844 smp_mb();
fc77dc3c 845 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 846 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 847 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 848 ++tx_ring->tx_stats.restart_queue;
30eba97a 849 }
e092be60 850 }
9a799d71 851
59224555 852 return !!budget;
9a799d71
AK		 853}
854
5dd2d332 855#ifdef CONFIG_IXGBE_DCA
bd0362dd 856static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 857 struct ixgbe_ring *rx_ring,
858 int cpu)
bd0362dd 859{
33cf09c9 860 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 861 u32 rxctrl;
33cf09c9
AD		 862 u8 reg_idx = rx_ring->reg_idx;
863
864 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
865 switch (hw->mac.type) {
866 case ixgbe_mac_82598EB:
867 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 868 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 869 break;
870 case ixgbe_mac_82599EB:
b93a2226 871 case ixgbe_mac_X540:
33cf09c9 872 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 873 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 874 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
875 break;
876 default:
877 break;
bd0362dd 878 }
33cf09c9
AD		 879 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
880 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
881 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 882 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 883}
884
885static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 886 struct ixgbe_ring *tx_ring,
887 int cpu)
bd0362dd 888{
33cf09c9 889 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 890 u32 txctrl;
33cf09c9
AD		 891 u8 reg_idx = tx_ring->reg_idx;
892
893 switch (hw->mac.type) {
894 case ixgbe_mac_82598EB:
895 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
896 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 897 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 898 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 899 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
900 break;
901 case ixgbe_mac_82599EB:
b93a2226 902 case ixgbe_mac_X540:
33cf09c9
AD		 903 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
904 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 905 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 906 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
907 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 908 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
909 break;
910 default:
911 break;
912 }
913}
914
915static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
916{
917 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 918 struct ixgbe_ring *ring;
bd0362dd 919 int cpu = get_cpu();
bd0362dd 920
33cf09c9
AD		 921 if (q_vector->cpu == cpu)
922 goto out_no_update;
923
efe3d3c8
AD		 924 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
925 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 926
efe3d3c8
AD		 927 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
928 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 929
930 q_vector->cpu = cpu;
931out_no_update:
bd0362dd
JC		 932 put_cpu();
933}
934
935static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
936{
33cf09c9 937 int num_q_vectors;
bd0362dd
JC		 938 int i;
939
940 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
941 return;
942
e35ec126
AD		 943 /* always use CB2 mode, difference is masked in the CB driver */
944 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
945
33cf09c9
AD		 946 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
947 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
948 else
949 num_q_vectors = 1;
950
951 for (i = 0; i < num_q_vectors; i++) {
952 adapter->q_vector[i]->cpu = -1;
953 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 954 }
955}
956
957static int __ixgbe_notify_dca(struct device *dev, void *data)
958{
c60fbb00 959 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 960 unsigned long event = *(unsigned long *)data;
961
2a72c31e 962 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 963 return 0;
964
bd0362dd
JC		 965 switch (event) {
966 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 967 /* if we're already enabled, don't do it again */
968 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
969 break;
652f093f 970 if (dca_add_requester(dev) == 0) {
96b0e0f6 971 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 972 ixgbe_setup_dca(adapter);
973 break;
974 }
975 /* Fall Through since DCA is disabled. */
976 case DCA_PROVIDER_REMOVE:
977 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
978 dca_remove_requester(dev);
979 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
980 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
981 }
982 break;
983 }
984
652f093f 985 return 0;
bd0362dd 986}
5dd2d332 987#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 988
989static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
990 struct sk_buff *skb)
991{
992 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
993}
994
ff886dfc
AD		 995/**
996 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
997 * @adapter: address of board private structure
998 * @rx_desc: advanced rx descriptor
999 *
1000 * Returns : true if it is FCoE pkt
1001 */
1002static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1003 union ixgbe_adv_rx_desc *rx_desc)
1004{
1005 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1006
1007 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1008 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1009 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1010 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1011}
1012
9a799d71
AK		 1013/**
1014 * ixgbe_receive_skb - Send a completed packet up the stack
1015 * @adapter: board private structure
1016 * @skb: packet to send up
177db6ff
MC		 1017 * @status: hardware indication of status of receive
1018 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1019 * @rx_desc: rx descriptor
9a799d71 1020 **/
78b6f4ce 1021static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1022 struct sk_buff *skb, u8 status,
1023 struct ixgbe_ring *ring,
1024 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1025{
78b6f4ce
HX		 1026 struct ixgbe_adapter *adapter = q_vector->adapter;
1027 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1028 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1029 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1030
f62bbb5e
JG		 1031 if (is_vlan && (tag & VLAN_VID_MASK))
1032 __vlan_hwaccel_put_tag(skb, tag);
1033
1034 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1035 napi_gro_receive(napi, skb);
1036 else
1037 netif_rx(skb);
9a799d71
AK		 1038}
1039
e59bd25d
AV		 1040/**
1041 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1042 * @adapter: address of board private structure
1043 * @status_err: hardware indication of status of receive
1044 * @skb: skb currently being received and modified
ff886dfc 1045 * @status_err: status error value of last descriptor in packet
e59bd25d 1046 **/
9a799d71 1047static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1048 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1049 struct sk_buff *skb,
1050 u32 status_err)
9a799d71 1051{
ff886dfc 1052 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1053
712744be
JB		 1054 /* Rx csum disabled */
1055 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1056 return;
e59bd25d
AV		 1057
1058 /* if IP and error */
1059 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1060 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1061 adapter->hw_csum_rx_error++;
1062 return;
1063 }
e59bd25d
AV		 1064
1065 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1066 return;
1067
1068 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1069 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1070
1071 /*
1072 * 82599 errata, UDP frames with a 0 checksum can be marked as
1073 * checksum errors.
1074 */
1075 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1076 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1077 return;
1078
e59bd25d
AV		 1079 adapter->hw_csum_rx_error++;
1080 return;
1081 }
1082
9a799d71 1083 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1084 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1085}
1086
84ea2591 1087static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1088{
1089 /*
1090 * Force memory writes to complete before letting h/w
1091 * know there are new descriptors to fetch. (Only
1092 * applicable for weak-ordered memory model archs,
1093 * such as IA-64).
1094 */
1095 wmb();
84ea2591 1096 writel(val, rx_ring->tail);
e8e26350
PW		 1097}
1098
9a799d71
AK		 1099/**
1100 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1101 * @rx_ring: ring to place buffers on
1102 * @cleaned_count: number of buffers to replace
9a799d71 1103 **/
fc77dc3c 1104void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1105{
9a799d71 1106 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1107 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1108 struct sk_buff *skb;
1109 u16 i = rx_ring->next_to_use;
9a799d71 1110
fc77dc3c
AD		 1111 /* do nothing if no valid netdev defined */
1112 if (!rx_ring->netdev)
1113 return;
1114
9a799d71 1115 while (cleaned_count--) {
31f05a2d 1116 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1117 bi = &rx_ring->rx_buffer_info[i];
1118 skb = bi->skb;
9a799d71 1119
d5f398ed 1120 if (!skb) {
fc77dc3c 1121 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1122 rx_ring->rx_buf_len);
9a799d71 1123 if (!skb) {
5b7da515 1124 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1125 goto no_buffers;
1126 }
d716a7d8
AD		 1127 /* initialize queue mapping */
1128 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1129 bi->skb = skb;
d716a7d8 1130 }
9a799d71 1131
d716a7d8 1132 if (!bi->dma) {
b6ec895e 1133 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1134 skb->data,
e8e9f696 1135 rx_ring->rx_buf_len,
1b507730 1136 DMA_FROM_DEVICE);
b6ec895e 1137 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1138 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1139 bi->dma = 0;
1140 goto no_buffers;
1141 }
9a799d71 1142 }
d5f398ed 1143
7d637bcc 1144 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1145 if (!bi->page) {
1f2149c1 1146 bi->page = alloc_page(GFP_ATOMIC | __GFP_COLD);
d5f398ed 1147 if (!bi->page) {
5b7da515 1148 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1149 goto no_buffers;
1150 }
1151 }
1152
1153 if (!bi->page_dma) {
1154 /* use a half page if we're re-using */
1155 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1156 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1157 bi->page,
1158 bi->page_offset,
1159 PAGE_SIZE / 2,
1160 DMA_FROM_DEVICE);
b6ec895e 1161 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1162 bi->page_dma)) {
5b7da515 1163 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1164 bi->page_dma = 0;
1165 goto no_buffers;
1166 }
1167 }
1168
1169 /* Refresh the desc even if buffer_addrs didn't change
1170 * because each write-back erases this info. */
3a581073
JB		 1171 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1172 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1173 } else {
3a581073 1174 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1175 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1176 }
1177
1178 i++;
1179 if (i == rx_ring->count)
1180 i = 0;
9a799d71 1181 }
7c6e0a43 1182
9a799d71
AK		 1183no_buffers:
1184 if (rx_ring->next_to_use != i) {
1185 rx_ring->next_to_use = i;
84ea2591 1186 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1187 }
1188}
1189
c267fc16 1190static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1191{
c267fc16
AD		 1192 /* HW will not DMA in data larger than the given buffer, even if it
1193 * parses the (NFS, of course) header to be larger. In that case, it
1194 * fills the header buffer and spills the rest into the page.
1195 */
1196 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1197 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1198 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1199 if (hlen > IXGBE_RX_HDR_SIZE)
1200 hlen = IXGBE_RX_HDR_SIZE;
1201 return hlen;
7c6e0a43
JB		 1202}
1203
f8212f97
AD		 1204/**
1205 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1206 * @skb: pointer to the last skb in the rsc queue
1207 *
1208 * This function changes a queue full of hw rsc buffers into a completed
1209 * packet. It uses the ->prev pointers to find the first packet and then
1210 * turns it into the frag list owner.
1211 **/
aa80175a 1212static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1213{
1214 unsigned int frag_list_size = 0;
aa80175a 1215 unsigned int skb_cnt = 1;
f8212f97
AD		 1216
1217 while (skb->prev) {
1218 struct sk_buff *prev = skb->prev;
1219 frag_list_size += skb->len;
1220 skb->prev = NULL;
1221 skb = prev;
aa80175a 1222 skb_cnt++;
f8212f97
AD		 1223 }
1224
1225 skb_shinfo(skb)->frag_list = skb->next;
1226 skb->next = NULL;
1227 skb->len += frag_list_size;
1228 skb->data_len += frag_list_size;
1229 skb->truesize += frag_list_size;
aa80175a
AD		 1230 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1231
f8212f97
AD		 1232 return skb;
1233}
1234
aa80175a
AD		 1235static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1236{
1237 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1238 IXGBE_RXDADV_RSCCNT_MASK);
1239}
43634e82 1240
4ff7fb12 1241static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1242 struct ixgbe_ring *rx_ring,
4ff7fb12 1243 int budget)
9a799d71 1244{
78b6f4ce 1245 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1246 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1247 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1248 struct sk_buff *skb;
d2f4fbe2 1249 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1250 const int current_node = numa_node_id();
3d8fd385
YZ		 1251#ifdef IXGBE_FCOE
1252 int ddp_bytes = 0;
1253#endif /* IXGBE_FCOE */
c267fc16
AD		 1254 u32 staterr;
1255 u16 i;
1256 u16 cleaned_count = 0;
aa80175a 1257 bool pkt_is_rsc = false;
9a799d71
AK		 1258
1259 i = rx_ring->next_to_clean;
31f05a2d 1260 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1261 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1262
1263 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1264 u32 upper_len = 0;
9a799d71 1265
3c945e5b 1266 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1267
c267fc16
AD		 1268 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1269
9a799d71 1270 skb = rx_buffer_info->skb;
9a799d71 1271 rx_buffer_info->skb = NULL;
c267fc16 1272 prefetch(skb->data);
9a799d71 1273
c267fc16 1274 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1275 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16 1276
b811ce91
JB		 1277 /* linear means we are building an skb from multiple pages */
1278 if (!skb_is_nonlinear(skb)) {
c267fc16 1279 u16 hlen;
aa80175a 1280 if (pkt_is_rsc &&
c267fc16
AD		 1281 !(staterr & IXGBE_RXD_STAT_EOP) &&
1282 !skb->prev) {
43634e82
MC		 1283 /*
1284 * When HWRSC is enabled, delay unmapping
1285 * of the first packet. It carries the
1286 * header information, HW may still
1287 * access the header after the writeback.
1288 * Only unmap it when EOP is reached
1289 */
e8171aaa 1290 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1291 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1292 } else {
b6ec895e 1293 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1294 rx_buffer_info->dma,
1295 rx_ring->rx_buf_len,
1296 DMA_FROM_DEVICE);
e8171aaa 1297 }
4f57ca6e 1298 rx_buffer_info->dma = 0;
c267fc16
AD		 1299
1300 if (ring_is_ps_enabled(rx_ring)) {
1301 hlen = ixgbe_get_hlen(rx_desc);
1302 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1303 } else {
1304 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1305 }
1306
1307 skb_put(skb, hlen);
1308 } else {
1309 /* assume packet split since header is unmapped */
1310 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1311 }
1312
1313 if (upper_len) {
b6ec895e
AD		 1314 dma_unmap_page(rx_ring->dev,
1315 rx_buffer_info->page_dma,
1316 PAGE_SIZE / 2,
1317 DMA_FROM_DEVICE);
9a799d71
AK		 1318 rx_buffer_info->page_dma = 0;
1319 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1320 rx_buffer_info->page,
1321 rx_buffer_info->page_offset,
1322 upper_len);
762f4c57 1323
c267fc16
AD		 1324 if ((page_count(rx_buffer_info->page) == 1) &&
1325 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1326 get_page(rx_buffer_info->page);
c267fc16
AD		 1327 else
1328 rx_buffer_info->page = NULL;
9a799d71
AK		 1329
1330 skb->len += upper_len;
1331 skb->data_len += upper_len;
98130646 1332 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1333 }
1334
1335 i++;
1336 if (i == rx_ring->count)
1337 i = 0;
9a799d71 1338
31f05a2d 1339 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1340 prefetch(next_rxd);
9a799d71 1341 cleaned_count++;
f8212f97 1342
aa80175a 1343 if (pkt_is_rsc) {
f8212f97
AD		 1344 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1345 IXGBE_RXDADV_NEXTP_SHIFT;
1346 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1347 } else {
1348 next_buffer = &rx_ring->rx_buffer_info[i];
1349 }
1350
c267fc16 1351 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1352 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1353 rx_buffer_info->skb = next_buffer->skb;
1354 rx_buffer_info->dma = next_buffer->dma;
1355 next_buffer->skb = skb;
1356 next_buffer->dma = 0;
1357 } else {
1358 skb->next = next_buffer->skb;
1359 skb->next->prev = skb;
1360 }
5b7da515 1361 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1362 goto next_desc;
1363 }
1364
aa80175a
AD		 1365 if (skb->prev) {
1366 skb = ixgbe_transform_rsc_queue(skb);
1367 /* if we got here without RSC the packet is invalid */
1368 if (!pkt_is_rsc) {
1369 __pskb_trim(skb, 0);
1370 rx_buffer_info->skb = skb;
1371 goto next_desc;
1372 }
1373 }
c267fc16
AD		 1374
1375 if (ring_is_rsc_enabled(rx_ring)) {
1376 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1377 dma_unmap_single(rx_ring->dev,
1378 IXGBE_RSC_CB(skb)->dma,
1379 rx_ring->rx_buf_len,
1380 DMA_FROM_DEVICE);
1381 IXGBE_RSC_CB(skb)->dma = 0;
1382 IXGBE_RSC_CB(skb)->delay_unmap = false;
1383 }
aa80175a
AD		 1384 }
1385 if (pkt_is_rsc) {
c267fc16
AD		 1386 if (ring_is_ps_enabled(rx_ring))
1387 rx_ring->rx_stats.rsc_count +=
aa80175a 1388 skb_shinfo(skb)->nr_frags;
c267fc16 1389 else
aa80175a
AD		 1390 rx_ring->rx_stats.rsc_count +=
1391 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1392 rx_ring->rx_stats.rsc_flush++;
1393 }
1394
1395 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1396 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1397 dev_kfree_skb_any(skb);
9a799d71
AK		 1398 goto next_desc;
1399 }
1400
ff886dfc 1401 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1402 if (adapter->netdev->features & NETIF_F_RXHASH)
1403 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1404
1405 /* probably a little skewed due to removing CRC */
1406 total_rx_bytes += skb->len;
1407 total_rx_packets++;
1408
fc77dc3c 1409 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1410#ifdef IXGBE_FCOE
1411 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1412 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1413 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1414 staterr);
63d635b2
AD		 1415 if (!ddp_bytes) {
1416 dev_kfree_skb_any(skb);
332d4a7d 1417 goto next_desc;
63d635b2 1418 }
3d8fd385 1419 }
332d4a7d 1420#endif /* IXGBE_FCOE */
fdaff1ce 1421 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1422
4ff7fb12 1423 budget--;
9a799d71
AK		 1424next_desc:
1425 rx_desc->wb.upper.status_error = 0;
1426
4ff7fb12 1427 if (!budget)
c267fc16
AD		 1428 break;
1429
9a799d71
AK		 1430 /* return some buffers to hardware, one at a time is too slow */
1431 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1432 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1433 cleaned_count = 0;
1434 }
1435
1436 /* use prefetched values */
1437 rx_desc = next_rxd;
9a799d71 1438 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1439 }
1440
9a799d71 1441 rx_ring->next_to_clean = i;
7d4987de 1442 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1443
1444 if (cleaned_count)
fc77dc3c 1445 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1446
3d8fd385
YZ		 1447#ifdef IXGBE_FCOE
1448 /* include DDPed FCoE data */
1449 if (ddp_bytes > 0) {
1450 unsigned int mss;
1451
fc77dc3c 1452 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1453 sizeof(struct fc_frame_header) -
1454 sizeof(struct fcoe_crc_eof);
1455 if (mss > 512)
1456 mss &= ~511;
1457 total_rx_bytes += ddp_bytes;
1458 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1459 }
1460#endif /* IXGBE_FCOE */
1461
c267fc16
AD		 1462 u64_stats_update_begin(&rx_ring->syncp);
1463 rx_ring->stats.packets += total_rx_packets;
1464 rx_ring->stats.bytes += total_rx_bytes;
1465 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1466 q_vector->rx.total_packets += total_rx_packets;
1467 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1468
1469 return !!budget;
9a799d71
AK		 1470}
1471
9a799d71
AK		 1472/**
1473 * ixgbe_configure_msix - Configure MSI-X hardware
1474 * @adapter: board private structure
1475 *
1476 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1477 * interrupts.
1478 **/
1479static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1480{
021230d4 1481 struct ixgbe_q_vector *q_vector;
efe3d3c8 1482 int q_vectors, v_idx;
021230d4 1483 u32 mask;
9a799d71 1484
021230d4 1485 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1486
8e34d1aa
AD		 1487 /* Populate MSIX to EITR Select */
1488 if (adapter->num_vfs > 32) {
1489 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1491 }
1492
4df10466
JB		 1493 /*
1494 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1495 * corresponding register.
1496 */
1497 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1498 struct ixgbe_ring *ring;
7a921c93 1499 q_vector = adapter->q_vector[v_idx];
021230d4 1500
efe3d3c8
AD		 1501 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1502 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1503
1504 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1505 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1506
d5bf4f67
ET		 1507 if (q_vector->tx.ring && !q_vector->rx.ring) {
1508 /* tx only vector */
1509 if (adapter->tx_itr_setting == 1)
1510 q_vector->itr = IXGBE_10K_ITR;
1511 else
1512 q_vector->itr = adapter->tx_itr_setting;
1513 } else {
1514 /* rx or rx/tx vector */
1515 if (adapter->rx_itr_setting == 1)
1516 q_vector->itr = IXGBE_20K_ITR;
1517 else
1518 q_vector->itr = adapter->rx_itr_setting;
1519 }
021230d4 1520
fe49f04a 1521 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1522 }
1523
bd508178
AD		 1524 switch (adapter->hw.mac.type) {
1525 case ixgbe_mac_82598EB:
e8e26350 1526 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1527 v_idx);
bd508178
AD		 1528 break;
1529 case ixgbe_mac_82599EB:
b93a2226 1530 case ixgbe_mac_X540:
e8e26350 1531 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1532 break;
bd508178
AD		 1533 default:
1534 break;
1535 }
021230d4
AV		 1536 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1537
41fb9248 1538 /* set up to autoclear timer, and the vectors */
021230d4 1539 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1540 mask &= ~(IXGBE_EIMS_OTHER |
1541 IXGBE_EIMS_MAILBOX |
1542 IXGBE_EIMS_LSC);
1543
021230d4 1544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1545}
1546
f494e8fa
AV		 1547enum latency_range {
1548 lowest_latency = 0,
1549 low_latency = 1,
1550 bulk_latency = 2,
1551 latency_invalid = 255
1552};
1553
1554/**
1555 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1556 * @q_vector: structure containing interrupt and ring information
1557 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1558 *
1559 * Stores a new ITR value based on packets and byte
1560 * counts during the last interrupt. The advantage of per interrupt
1561 * computation is faster updates and more accurate ITR for the current
1562 * traffic pattern. Constants in this function were computed
1563 * based on theoretical maximum wire speed and thresholds were set based
1564 * on testing data as well as attempting to minimize response time
1565 * while increasing bulk throughput.
1566 * this functionality is controlled by the InterruptThrottleRate module
1567 * parameter (see ixgbe_param.c)
1568 **/
bd198058
AD		 1569static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1570 struct ixgbe_ring_container *ring_container)
f494e8fa 1571{
f494e8fa 1572 u64 bytes_perint;
bd198058
AD		 1573 struct ixgbe_adapter *adapter = q_vector->adapter;
1574 int bytes = ring_container->total_bytes;
1575 int packets = ring_container->total_packets;
1576 u32 timepassed_us;
1577 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1578
1579 if (packets == 0)
bd198058 1580 return;
f494e8fa
AV		 1581
1582 /* simple throttlerate management
1583 * 0-20MB/s lowest (100000 ints/s)
1584 * 20-100MB/s low (20000 ints/s)
1585 * 100-1249MB/s bulk (8000 ints/s)
1586 */
1587 /* what was last interrupt timeslice? */
d5bf4f67 1588 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1589 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1590
1591 switch (itr_setting) {
1592 case lowest_latency:
1593 if (bytes_perint > adapter->eitr_low)
bd198058 1594 itr_setting = low_latency;
f494e8fa
AV		 1595 break;
1596 case low_latency:
1597 if (bytes_perint > adapter->eitr_high)
bd198058 1598 itr_setting = bulk_latency;
f494e8fa 1599 else if (bytes_perint <= adapter->eitr_low)
bd198058 1600 itr_setting = lowest_latency;
f494e8fa
AV		 1601 break;
1602 case bulk_latency:
1603 if (bytes_perint <= adapter->eitr_high)
bd198058 1604 itr_setting = low_latency;
f494e8fa
AV		 1605 break;
1606 }
1607
bd198058
AD		 1608 /* clear work counters since we have the values we need */
1609 ring_container->total_bytes = 0;
1610 ring_container->total_packets = 0;
1611
1612 /* write updated itr to ring container */
1613 ring_container->itr = itr_setting;
f494e8fa
AV		 1614}
1615
509ee935
JB		 1616/**
1617 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1618 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1619 *
1620 * This function is made to be called by ethtool and by the driver
1621 * when it needs to update EITR registers at runtime. Hardware
1622 * specific quirks/differences are taken care of here.
1623 */
fe49f04a 1624void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1625{
fe49f04a 1626 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1627 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1628 int v_idx = q_vector->v_idx;
d5bf4f67 1629 u32 itr_reg = q_vector->itr;
fe49f04a 1630
bd508178
AD		 1631 switch (adapter->hw.mac.type) {
1632 case ixgbe_mac_82598EB:
509ee935
JB		 1633 /* must write high and low 16 bits to reset counter */
1634 itr_reg |= (itr_reg << 16);
bd508178
AD		 1635 break;
1636 case ixgbe_mac_82599EB:
b93a2226 1637 case ixgbe_mac_X540:
509ee935
JB		 1638 /*
1639 * set the WDIS bit to not clear the timer bits and cause an
1640 * immediate assertion of the interrupt
1641 */
1642 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1643 break;
1644 default:
1645 break;
509ee935
JB		 1646 }
1647 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1648}
1649
bd198058 1650static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1651{
d5bf4f67 1652 u32 new_itr = q_vector->itr;
bd198058 1653 u8 current_itr;
f494e8fa 1654
bd198058
AD		 1655 ixgbe_update_itr(q_vector, &q_vector->tx);
1656 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1657
08c8833b 1658 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1659
1660 switch (current_itr) {
1661 /* counts and packets in update_itr are dependent on these numbers */
1662 case lowest_latency:
d5bf4f67 1663 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1664 break;
1665 case low_latency:
d5bf4f67 1666 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1667 break;
1668 case bulk_latency:
d5bf4f67 1669 new_itr = IXGBE_8K_ITR;
f494e8fa 1670 break;
bd198058
AD		 1671 default:
1672 break;
f494e8fa
AV		 1673 }
1674
d5bf4f67 1675 if (new_itr != q_vector->itr) {
fe49f04a 1676 /* do an exponential smoothing */
d5bf4f67
ET		 1677 new_itr = (10 * new_itr * q_vector->itr) /
1678 ((9 * new_itr) + q_vector->itr);
509ee935 1679
bd198058 1680 /* save the algorithm value here */
d5bf4f67 1681 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1682
1683 ixgbe_write_eitr(q_vector);
f494e8fa 1684 }
f494e8fa
AV		 1685}
1686
119fc60a 1687/**
f0f9778d
AD		 1688 * ixgbe_check_overtemp_subtask - check for over tempurature
1689 * @adapter: pointer to adapter
119fc60a 1690 **/
f0f9778d 1691static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1692{
119fc60a
MC		 1693 struct ixgbe_hw *hw = &adapter->hw;
1694 u32 eicr = adapter->interrupt_event;
1695
f0f9778d 1696 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1697 return;
1698
f0f9778d
AD		 1699 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1700 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1701 return;
1702
1703 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1704
7ca647bd 1705 switch (hw->device_id) {
f0f9778d
AD		 1706 case IXGBE_DEV_ID_82599_T3_LOM:
1707 /*
1708 * Since the warning interrupt is for both ports
1709 * we don't have to check if:
1710 * - This interrupt wasn't for our port.
1711 * - We may have missed the interrupt so always have to
1712 * check if we got a LSC
1713 */
1714 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1715 !(eicr & IXGBE_EICR_LSC))
1716 return;
1717
1718 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1719 u32 autoneg;
1720 bool link_up = false;
7ca647bd 1721
7ca647bd
JP		 1722 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1723
f0f9778d
AD		 1724 if (link_up)
1725 return;
1726 }
1727
1728 /* Check if this is not due to overtemp */
1729 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1730 return;
1731
1732 break;
7ca647bd
JP		 1733 default:
1734 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1735 return;
7ca647bd 1736 break;
119fc60a 1737 }
7ca647bd
JP		 1738 e_crit(drv,
1739 "Network adapter has been stopped because it has over heated. "
1740 "Restart the computer. If the problem persists, "
1741 "power off the system and replace the adapter\n");
f0f9778d
AD		 1742
1743 adapter->interrupt_event = 0;
119fc60a
MC		 1744}
1745
0befdb3e
JB		 1746static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1747{
1748 struct ixgbe_hw *hw = &adapter->hw;
1749
1750 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1751 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1752 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1753 /* write to clear the interrupt */
1754 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1755 }
1756}
cf8280ee 1757
4f51bf70
JK		 1758static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1759{
1760 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1761 return;
1762
1763 switch (adapter->hw.mac.type) {
1764 case ixgbe_mac_82599EB:
1765 /*
1766 * Need to check link state so complete overtemp check
1767 * on service task
1768 */
1769 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1770 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1771 adapter->interrupt_event = eicr;
1772 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1773 ixgbe_service_event_schedule(adapter);
1774 return;
1775 }
1776 return;
1777 case ixgbe_mac_X540:
1778 if (!(eicr & IXGBE_EICR_TS))
1779 return;
1780 break;
1781 default:
1782 return;
1783 }
1784
1785 e_crit(drv,
1786 "Network adapter has been stopped because it has over heated. "
1787 "Restart the computer. If the problem persists, "
1788 "power off the system and replace the adapter\n");
1789}
1790
e8e26350
PW		 1791static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1792{
1793 struct ixgbe_hw *hw = &adapter->hw;
1794
73c4b7cd
AD		 1795 if (eicr & IXGBE_EICR_GPI_SDP2) {
1796 /* Clear the interrupt */
1797 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1798 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1799 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1800 ixgbe_service_event_schedule(adapter);
1801 }
73c4b7cd
AD		 1802 }
1803
e8e26350
PW		 1804 if (eicr & IXGBE_EICR_GPI_SDP1) {
1805 /* Clear the interrupt */
1806 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1807 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1808 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1809 ixgbe_service_event_schedule(adapter);
1810 }
e8e26350
PW		 1811 }
1812}
1813
cf8280ee
JB		 1814static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1815{
1816 struct ixgbe_hw *hw = &adapter->hw;
1817
1818 adapter->lsc_int++;
1819 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1820 adapter->link_check_timeout = jiffies;
1821 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1822 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1823 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1824 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1825 }
1826}
1827
fe49f04a
AD		 1828static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1829 u64 qmask)
1830{
1831 u32 mask;
bd508178 1832 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1833
bd508178
AD		 1834 switch (hw->mac.type) {
1835 case ixgbe_mac_82598EB:
fe49f04a 1836 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1837 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1838 break;
1839 case ixgbe_mac_82599EB:
b93a2226 1840 case ixgbe_mac_X540:
fe49f04a 1841 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1842 if (mask)
1843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1844 mask = (qmask >> 32);
bd508178
AD		 1845 if (mask)
1846 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1847 break;
1848 default:
1849 break;
fe49f04a
AD		 1850 }
1851 /* skip the flush */
1852}
1853
1854static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1855 u64 qmask)
fe49f04a
AD		 1856{
1857 u32 mask;
bd508178 1858 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1859
bd508178
AD		 1860 switch (hw->mac.type) {
1861 case ixgbe_mac_82598EB:
fe49f04a 1862 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1863 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1864 break;
1865 case ixgbe_mac_82599EB:
b93a2226 1866 case ixgbe_mac_X540:
fe49f04a 1867 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1868 if (mask)
1869 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1870 mask = (qmask >> 32);
bd508178
AD		 1871 if (mask)
1872 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1873 break;
1874 default:
1875 break;
fe49f04a
AD		 1876 }
1877 /* skip the flush */
1878}
1879
021230d4 1880/**
2c4af694
AD		 1881 * ixgbe_irq_enable - Enable default interrupt generation settings
1882 * @adapter: board private structure
021230d4 1883 **/
2c4af694
AD		 1884static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1885 bool flush)
9a799d71 1886{
2c4af694 1887 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1888
2c4af694
AD		 1889 /* don't reenable LSC while waiting for link */
1890 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1891 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1892
2c4af694 1893 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 1894 switch (adapter->hw.mac.type) {
1895 case ixgbe_mac_82599EB:
1896 mask |= IXGBE_EIMS_GPI_SDP0;
1897 break;
1898 case ixgbe_mac_X540:
1899 mask |= IXGBE_EIMS_TS;
1900 break;
1901 default:
1902 break;
1903 }
2c4af694
AD		 1904 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1905 mask |= IXGBE_EIMS_GPI_SDP1;
1906 switch (adapter->hw.mac.type) {
1907 case ixgbe_mac_82599EB:
2c4af694
AD		 1908 mask |= IXGBE_EIMS_GPI_SDP1;
1909 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1910 case ixgbe_mac_X540:
1911 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1912 mask |= IXGBE_EIMS_MAILBOX;
1913 break;
1914 default:
1915 break;
9a799d71 1916 }
2c4af694
AD		 1917 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1918 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1919 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1920
2c4af694
AD		 1921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1922 if (queues)
1923 ixgbe_irq_enable_queues(adapter, ~0);
1924 if (flush)
1925 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1926}
1927
2c4af694 1928static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1929{
a65151ba 1930 struct ixgbe_adapter *adapter = data;
9a799d71 1931 struct ixgbe_hw *hw = &adapter->hw;
54037505 1932 u32 eicr;
91281fd3 1933
54037505
DS		 1934 /*
1935 * Workaround for Silicon errata. Use clear-by-write instead
1936 * of clear-by-read. Reading with EICS will return the
1937 * interrupt causes without clearing, which later be done
1938 * with the write to EICR.
1939 */
1940 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1941 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1942
cf8280ee
JB		 1943 if (eicr & IXGBE_EICR_LSC)
1944 ixgbe_check_lsc(adapter);
f0848276 1945
1cdd1ec8
GR		 1946 if (eicr & IXGBE_EICR_MAILBOX)
1947 ixgbe_msg_task(adapter);
efe3d3c8 1948
bd508178
AD		 1949 switch (hw->mac.type) {
1950 case ixgbe_mac_82599EB:
b93a2226 1951 case ixgbe_mac_X540:
2c4af694
AD		 1952 if (eicr & IXGBE_EICR_ECC)
1953 e_info(link, "Received unrecoverable ECC Err, please "
1954 "reboot\n");
c4cf55e5
PWJ		 1955 /* Handle Flow Director Full threshold interrupt */
1956 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1957 int reinit_count = 0;
c4cf55e5 1958 int i;
c4cf55e5 1959 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1960 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1961 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1962 &ring->state))
1963 reinit_count++;
1964 }
1965 if (reinit_count) {
1966 /* no more flow director interrupts until after init */
1967 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 1968 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1969 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1970 }
1971 }
f0f9778d 1972 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 1973 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 1974 break;
1975 default:
1976 break;
c4cf55e5 1977 }
f0848276 1978
bd508178 1979 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 1980
7086400d 1981 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1982 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 1983 ixgbe_irq_enable(adapter, false, false);
f0848276 1984
9a799d71 1985 return IRQ_HANDLED;
f0848276 1986}
91281fd3 1987
4ff7fb12 1988static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 1989{
021230d4 1990 struct ixgbe_q_vector *q_vector = data;
91281fd3 1991
9b471446 1992 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1993
4ff7fb12
AD		 1994 if (q_vector->rx.ring || q_vector->tx.ring)
1995 napi_schedule(&q_vector->napi);
91281fd3 1996
9a799d71 1997 return IRQ_HANDLED;
91281fd3
AD		 1998}
1999
021230d4 2000static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2001 int r_idx)
021230d4 2002{
7a921c93 2003 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2004 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2005
2274543f 2006 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2007 rx_ring->next = q_vector->rx.ring;
2008 q_vector->rx.ring = rx_ring;
2009 q_vector->rx.count++;
021230d4
AV		 2010}
2011
2012static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2013 int t_idx)
021230d4 2014{
7a921c93 2015 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2016 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2017
2274543f 2018 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2019 tx_ring->next = q_vector->tx.ring;
2020 q_vector->tx.ring = tx_ring;
2021 q_vector->tx.count++;
bd198058 2022 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2023}
2024
9a799d71 2025/**
021230d4
AV		 2026 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2027 * @adapter: board private structure to initialize
9a799d71 2028 *
021230d4
AV		 2029 * This function maps descriptor rings to the queue-specific vectors
2030 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2031 * one vector per ring/queue, but on a constrained vector budget, we
2032 * group the rings as "efficiently" as possible. You would add new
2033 * mapping configurations in here.
9a799d71 2034 **/
4cc6df29 2035static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2036{
4cc6df29
AD		 2037 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2038 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2039 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2040 int v_start = 0;
021230d4 2041
4cc6df29 2042 /* only one q_vector if MSI-X is disabled. */
021230d4 2043 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2044 q_vectors = 1;
d0759ebb 2045
021230d4 2046 /*
4cc6df29
AD		 2047 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2048 * group them so there are multiple queues per vector.
2049 *
2050 * Re-adjusting *qpv takes care of the remainder.
021230d4 2051 */
4cc6df29
AD		 2052 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2053 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2054 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2055 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2056 }
9a799d71 2057
021230d4 2058 /*
4cc6df29
AD		 2059 * If there are not enough q_vectors for each ring to have it's own
2060 * vector then we must pair up Rx/Tx on a each vector
021230d4 2061 */
4cc6df29
AD		 2062 if ((v_start + txr_remaining) > q_vectors)
2063 v_start = 0;
2064
2065 for (; v_start < q_vectors && txr_remaining; v_start++) {
2066 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2067 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2068 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2069 }
021230d4
AV		 2070}
2071
2072/**
2073 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2074 * @adapter: board private structure
2075 *
2076 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2077 * interrupts from the kernel.
2078 **/
2079static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2080{
2081 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2082 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2083 int vector, err;
e8e9f696 2084 int ri = 0, ti = 0;
021230d4 2085
021230d4 2086 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2087 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2088 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2089
4ff7fb12 2090 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2091 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2092 "%s-%s-%d", netdev->name, "TxRx", ri++);
2093 ti++;
2094 } else if (q_vector->rx.ring) {
9fe93afd 2095 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2096 "%s-%s-%d", netdev->name, "rx", ri++);
2097 } else if (q_vector->tx.ring) {
9fe93afd 2098 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2099 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2100 } else {
2101 /* skip this unused q_vector */
2102 continue;
32aa77a4 2103 }
207867f5
AD		 2104 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2105 q_vector->name, q_vector);
9a799d71 2106 if (err) {
396e799c 2107 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2108 "Error: %d\n", err);
021230d4 2109 goto free_queue_irqs;
9a799d71 2110 }
207867f5
AD		 2111 /* If Flow Director is enabled, set interrupt affinity */
2112 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2113 /* assign the mask for this irq */
2114 irq_set_affinity_hint(entry->vector,
2115 q_vector->affinity_mask);
2116 }
9a799d71
AK		 2117 }
2118
021230d4 2119 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2120 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2121 if (err) {
396e799c 2122 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2123 goto free_queue_irqs;
9a799d71
AK		 2124 }
2125
9a799d71
AK		 2126 return 0;
2127
021230d4 2128free_queue_irqs:
207867f5
AD		 2129 while (vector) {
2130 vector--;
2131 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2132 NULL);
2133 free_irq(adapter->msix_entries[vector].vector,
2134 adapter->q_vector[vector]);
2135 }
021230d4
AV		 2136 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2137 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2138 kfree(adapter->msix_entries);
2139 adapter->msix_entries = NULL;
9a799d71
AK		 2140 return err;
2141}
2142
2143/**
021230d4 2144 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2145 * @irq: interrupt number
2146 * @data: pointer to a network interface device structure
9a799d71
AK		 2147 **/
2148static irqreturn_t ixgbe_intr(int irq, void *data)
2149{
a65151ba 2150 struct ixgbe_adapter *adapter = data;
9a799d71 2151 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2152 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2153 u32 eicr;
2154
54037505 2155 /*
6af3b9eb 2156 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2157 * before the read of EICR.
2158 */
2159 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2160
021230d4 2161 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2162 * therefore no explicit interrupt disable is necessary */
021230d4 2163 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2164 if (!eicr) {
6af3b9eb
ET		 2165 /*
2166 * shared interrupt alert!
f47cf66e 2167 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2168 * have disabled interrupts due to EIAM
2169 * finish the workaround of silicon errata on 82598. Unmask
2170 * the interrupt that we masked before the EICR read.
2171 */
2172 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2173 ixgbe_irq_enable(adapter, true, true);
9a799d71 2174 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2175 }
9a799d71 2176
cf8280ee
JB		 2177 if (eicr & IXGBE_EICR_LSC)
2178 ixgbe_check_lsc(adapter);
021230d4 2179
bd508178
AD		 2180 switch (hw->mac.type) {
2181 case ixgbe_mac_82599EB:
e8e26350 2182 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2183 /* Fall through */
2184 case ixgbe_mac_X540:
2185 if (eicr & IXGBE_EICR_ECC)
2186 e_info(link, "Received unrecoverable ECC err, please "
2187 "reboot\n");
4f51bf70 2188 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2189 break;
2190 default:
2191 break;
2192 }
e8e26350 2193
0befdb3e
JB		 2194 ixgbe_check_fan_failure(adapter, eicr);
2195
7a921c93 2196 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2197 /* would disable interrupts here but EIAM disabled it */
7a921c93 2198 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2199 }
2200
6af3b9eb
ET		 2201 /*
2202 * re-enable link(maybe) and non-queue interrupts, no flush.
2203 * ixgbe_poll will re-enable the queue interrupts
2204 */
2205
2206 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2207 ixgbe_irq_enable(adapter, false, false);
2208
9a799d71
AK		 2209 return IRQ_HANDLED;
2210}
2211
021230d4
AV		 2212static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2213{
efe3d3c8
AD		 2214 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2215 int i;
2216
2217 /* legacy and MSI only use one vector */
2218 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2219 q_vectors = 1;
2220
2221 for (i = 0; i < adapter->num_rx_queues; i++) {
2222 adapter->rx_ring[i]->q_vector = NULL;
2223 adapter->rx_ring[i]->next = NULL;
2224 }
2225 for (i = 0; i < adapter->num_tx_queues; i++) {
2226 adapter->tx_ring[i]->q_vector = NULL;
2227 adapter->tx_ring[i]->next = NULL;
2228 }
021230d4
AV		 2229
2230 for (i = 0; i < q_vectors; i++) {
7a921c93 2231 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2232 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2233 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2234 }
2235}
2236
9a799d71
AK		 2237/**
2238 * ixgbe_request_irq - initialize interrupts
2239 * @adapter: board private structure
2240 *
2241 * Attempts to configure interrupts using the best available
2242 * capabilities of the hardware and kernel.
2243 **/
021230d4 2244static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2245{
2246 struct net_device *netdev = adapter->netdev;
021230d4 2247 int err;
9a799d71 2248
4cc6df29
AD		 2249 /* map all of the rings to the q_vectors */
2250 ixgbe_map_rings_to_vectors(adapter);
2251
2252 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2253 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2254 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2255 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2256 netdev->name, adapter);
4cc6df29 2257 else
a0607fd3 2258 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2259 netdev->name, adapter);
9a799d71 2260
4cc6df29 2261 if (err) {
396e799c 2262 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2263
4cc6df29
AD		 2264 /* place q_vectors and rings back into a known good state */
2265 ixgbe_reset_q_vectors(adapter);
2266 }
2267
9a799d71
AK		 2268 return err;
2269}
2270
2271static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2272{
9a799d71 2273 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2274 int i, q_vectors;
9a799d71 2275
021230d4 2276 q_vectors = adapter->num_msix_vectors;
021230d4 2277 i = q_vectors - 1;
a65151ba 2278 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2279 i--;
4cc6df29 2280
021230d4 2281 for (; i >= 0; i--) {
894ff7cf 2282 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2283 if (!adapter->q_vector[i]->rx.ring &&
2284 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2285 continue;
2286
207867f5
AD		 2287 /* clear the affinity_mask in the IRQ descriptor */
2288 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2289 NULL);
2290
021230d4 2291 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2292 adapter->q_vector[i]);
021230d4 2293 }
021230d4 2294 } else {
a65151ba 2295 free_irq(adapter->pdev->irq, adapter);
9a799d71 2296 }
207867f5
AD		 2297
2298 /* clear q_vector state information */
2299 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2300}
2301
22d5a71b
JB		 2302/**
2303 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2304 * @adapter: board private structure
2305 **/
2306static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2307{
bd508178
AD		 2308 switch (adapter->hw.mac.type) {
2309 case ixgbe_mac_82598EB:
835462fc 2310 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2311 break;
2312 case ixgbe_mac_82599EB:
b93a2226 2313 case ixgbe_mac_X540:
835462fc
NS		 2314 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2316 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2317 break;
2318 default:
2319 break;
22d5a71b
JB		 2320 }
2321 IXGBE_WRITE_FLUSH(&adapter->hw);
2322 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2323 int i;
2324 for (i = 0; i < adapter->num_msix_vectors; i++)
2325 synchronize_irq(adapter->msix_entries[i].vector);
2326 } else {
2327 synchronize_irq(adapter->pdev->irq);
2328 }
2329}
2330
9a799d71
AK		 2331/**
2332 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2333 *
2334 **/
2335static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2336{
d5bf4f67 2337 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2338
d5bf4f67
ET		 2339 /* rx/tx vector */
2340 if (adapter->rx_itr_setting == 1)
2341 q_vector->itr = IXGBE_20K_ITR;
2342 else
2343 q_vector->itr = adapter->rx_itr_setting;
2344
2345 ixgbe_write_eitr(q_vector);
9a799d71 2346
e8e26350
PW		 2347 ixgbe_set_ivar(adapter, 0, 0, 0);
2348 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2349
396e799c 2350 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2351}
2352
43e69bf0
AD		 2353/**
2354 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2355 * @adapter: board private structure
2356 * @ring: structure containing ring specific data
2357 *
2358 * Configure the Tx descriptor ring after a reset.
2359 **/
84418e3b
AD		 2360void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2361 struct ixgbe_ring *ring)
43e69bf0
AD		 2362{
2363 struct ixgbe_hw *hw = &adapter->hw;
2364 u64 tdba = ring->dma;
2f1860b8 2365 int wait_loop = 10;
b88c6de2 2366 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2367 u8 reg_idx = ring->reg_idx;
43e69bf0 2368
2f1860b8 2369 /* disable queue to avoid issues while updating state */
b88c6de2 2370 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2371 IXGBE_WRITE_FLUSH(hw);
2372
43e69bf0 2373 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2374 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2375 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2376 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2377 ring->count * sizeof(union ixgbe_adv_tx_desc));
2378 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2379 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2380 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2381
b88c6de2
AD		 2382 /*
2383 * set WTHRESH to encourage burst writeback, it should not be set
2384 * higher than 1 when ITR is 0 as it could cause false TX hangs
2385 *
2386 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2387 * to or less than the number of on chip descriptors, which is
2388 * currently 40.
2389 */
2390 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2391 txdctl |= (1 << 16); /* WTHRESH = 1 */
2392 else
2393 txdctl |= (8 << 16); /* WTHRESH = 8 */
2394
2395 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2396 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2397 32; /* PTHRESH = 32 */
2f1860b8
AD		 2398
2399 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2400 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2401 adapter->atr_sample_rate) {
2402 ring->atr_sample_rate = adapter->atr_sample_rate;
2403 ring->atr_count = 0;
2404 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2405 } else {
2406 ring->atr_sample_rate = 0;
2407 }
2f1860b8 2408
c84d324c
JF		 2409 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2410
2f1860b8 2411 /* enable queue */
2f1860b8
AD		 2412 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2413
2414 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2415 if (hw->mac.type == ixgbe_mac_82598EB &&
2416 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2417 return;
2418
2419 /* poll to verify queue is enabled */
2420 do {
032b4325 2421 usleep_range(1000, 2000);
2f1860b8
AD		 2422 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2423 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2424 if (!wait_loop)
2425 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2426}
2427
120ff942
AD		 2428static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2429{
2430 struct ixgbe_hw *hw = &adapter->hw;
2431 u32 rttdcs;
72a32f1f 2432 u32 reg;
8b1c0b24 2433 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2434
2435 if (hw->mac.type == ixgbe_mac_82598EB)
2436 return;
2437
2438 /* disable the arbiter while setting MTQC */
2439 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2440 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2441 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2442
2443 /* set transmit pool layout */
8b1c0b24 2444 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2445 case (IXGBE_FLAG_SRIOV_ENABLED):
2446 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2447 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2448 break;
8b1c0b24
JF		 2449 default:
2450 if (!tcs)
2451 reg = IXGBE_MTQC_64Q_1PB;
2452 else if (tcs <= 4)
2453 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2454 else
2455 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2456
8b1c0b24 2457 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2458
8b1c0b24
JF		 2459 /* Enable Security TX Buffer IFG for multiple pb */
2460 if (tcs) {
2461 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2462 reg |= IXGBE_SECTX_DCB;
2463 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2464 }
120ff942
AD		 2465 break;
2466 }
2467
2468 /* re-enable the arbiter */
2469 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2470 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2471}
2472
9a799d71 2473/**
3a581073 2474 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2475 * @adapter: board private structure
2476 *
2477 * Configure the Tx unit of the MAC after a reset.
2478 **/
2479static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2480{
2f1860b8
AD		 2481 struct ixgbe_hw *hw = &adapter->hw;
2482 u32 dmatxctl;
43e69bf0 2483 u32 i;
9a799d71 2484
2f1860b8
AD		 2485 ixgbe_setup_mtqc(adapter);
2486
2487 if (hw->mac.type != ixgbe_mac_82598EB) {
2488 /* DMATXCTL.EN must be before Tx queues are enabled */
2489 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2490 dmatxctl |= IXGBE_DMATXCTL_TE;
2491 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2492 }
2493
9a799d71 2494 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2495 for (i = 0; i < adapter->num_tx_queues; i++)
2496 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2497}
2498
e8e26350 2499#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2500
a6616b42 2501static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2502 struct ixgbe_ring *rx_ring)
cc41ac7c 2503{
cc41ac7c 2504 u32 srrctl;
bf29ee6c 2505 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2506
bd508178
AD		 2507 switch (adapter->hw.mac.type) {
2508 case ixgbe_mac_82598EB: {
2509 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2510 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2511 reg_idx = reg_idx & mask;
cc41ac7c 2512 }
bd508178
AD		 2513 break;
2514 case ixgbe_mac_82599EB:
b93a2226 2515 case ixgbe_mac_X540:
bd508178
AD		 2516 default:
2517 break;
2518 }
2519
bf29ee6c 2520 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2521
2522 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2523 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2524 if (adapter->num_vfs)
2525 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2526
afafd5b0
AD		 2527 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2528 IXGBE_SRRCTL_BSIZEHDR_MASK;
2529
7d637bcc 2530 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2531#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2532 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2533#else
2534 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535#endif
cc41ac7c 2536 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2537 } else {
afafd5b0
AD		 2538 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2539 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2540 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2541 }
e8e26350 2542
bf29ee6c 2543 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2544}
9a799d71 2545
05abb126 2546static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2547{
05abb126
AD		 2548 struct ixgbe_hw *hw = &adapter->hw;
2549 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2550 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2551 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2552 u32 mrqc = 0, reta = 0;
2553 u32 rxcsum;
2554 int i, j;
8b1c0b24 2555 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2556 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2557
2558 if (tcs)
2559 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2560
05abb126
AD		 2561 /* Fill out hash function seeds */
2562 for (i = 0; i < 10; i++)
2563 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2564
2565 /* Fill out redirection table */
2566 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2567 if (j == maxq)
05abb126
AD		 2568 j = 0;
2569 /* reta = 4-byte sliding window of
2570 * 0x00..(indices-1)(indices-1)00..etc. */
2571 reta = (reta << 8) | (j * 0x11);
2572 if ((i & 3) == 3)
2573 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2574 }
0cefafad 2575
05abb126
AD		 2576 /* Disable indicating checksum in descriptor, enables RSS hash */
2577 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2578 rxcsum |= IXGBE_RXCSUM_PCSD;
2579 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2580
8b1c0b24
JF		 2581 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2582 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2583 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2584 } else {
2585 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2586 | IXGBE_FLAG_SRIOV_ENABLED);
2587
2588 switch (mask) {
2589 case (IXGBE_FLAG_RSS_ENABLED):
2590 if (!tcs)
2591 mrqc = IXGBE_MRQC_RSSEN;
2592 else if (tcs <= 4)
2593 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2594 else
2595 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2596 break;
2597 case (IXGBE_FLAG_SRIOV_ENABLED):
2598 mrqc = IXGBE_MRQC_VMDQEN;
2599 break;
2600 default:
2601 break;
2602 }
0cefafad
JB		 2603 }
2604
05abb126
AD		 2605 /* Perform hash on these packet types */
2606 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608 | IXGBE_MRQC_RSS_FIELD_IPV6
2609 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2612}
2613
bb5a9ad2
NS		 2614/**
2615 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616 * @adapter: address of board private structure
2617 * @index: index of ring to set
bb5a9ad2 2618 **/
082757af 2619static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2620 struct ixgbe_ring *ring)
bb5a9ad2 2621{
bb5a9ad2 2622 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2623 u32 rscctrl;
edd2ea55 2624 int rx_buf_len;
bf29ee6c 2625 u8 reg_idx = ring->reg_idx;
7367096a 2626
7d637bcc 2627 if (!ring_is_rsc_enabled(ring))
7367096a 2628 return;
bb5a9ad2 2629
7367096a
AD		 2630 rx_buf_len = ring->rx_buf_len;
2631 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2632 rscctrl |= IXGBE_RSCCTL_RSCEN;
2633 /*
2634 * we must limit the number of descriptors so that the
2635 * total size of max desc * buf_len is not greater
2636 * than 65535
2637 */
7d637bcc 2638 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2639#if (MAX_SKB_FRAGS > 16)
2640 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2641#elif (MAX_SKB_FRAGS > 8)
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2643#elif (MAX_SKB_FRAGS > 4)
2644 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2645#else
2646 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2647#endif
2648 } else {
919e78a6 2649 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2650 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2651 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2652 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2653 else
2654 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2655 }
7367096a 2656 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2657}
2658
9e10e045
AD		 2659/**
2660 * ixgbe_set_uta - Set unicast filter table address
2661 * @adapter: board private structure
2662 *
2663 * The unicast table address is a register array of 32-bit registers.
2664 * The table is meant to be used in a way similar to how the MTA is used
2665 * however due to certain limitations in the hardware it is necessary to
2666 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2667 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2668 **/
2669static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2670{
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 int i;
2673
2674 /* The UTA table only exists on 82599 hardware and newer */
2675 if (hw->mac.type < ixgbe_mac_82599EB)
2676 return;
2677
2678 /* we only need to do this if VMDq is enabled */
2679 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2680 return;
2681
2682 for (i = 0; i < 128; i++)
2683 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2684}
2685
2686#define IXGBE_MAX_RX_DESC_POLL 10
2687static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2688 struct ixgbe_ring *ring)
2689{
2690 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2691 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2692 u32 rxdctl;
bf29ee6c 2693 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2694
2695 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2696 if (hw->mac.type == ixgbe_mac_82598EB &&
2697 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2698 return;
2699
2700 do {
032b4325 2701 usleep_range(1000, 2000);
9e10e045
AD		 2702 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2703 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2704
2705 if (!wait_loop) {
2706 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2707 "the polling period\n", reg_idx);
2708 }
2709}
2710
2d39d576
YZ		 2711void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2712 struct ixgbe_ring *ring)
2713{
2714 struct ixgbe_hw *hw = &adapter->hw;
2715 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2716 u32 rxdctl;
2717 u8 reg_idx = ring->reg_idx;
2718
2719 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2720 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2721
2722 /* write value back with RXDCTL.ENABLE bit cleared */
2723 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2724
2725 if (hw->mac.type == ixgbe_mac_82598EB &&
2726 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2727 return;
2728
2729 /* the hardware may take up to 100us to really disable the rx queue */
2730 do {
2731 udelay(10);
2732 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2733 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2734
2735 if (!wait_loop) {
2736 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2737 "the polling period\n", reg_idx);
2738 }
2739}
2740
84418e3b
AD		 2741void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2742 struct ixgbe_ring *ring)
acd37177
AD		 2743{
2744 struct ixgbe_hw *hw = &adapter->hw;
2745 u64 rdba = ring->dma;
9e10e045 2746 u32 rxdctl;
bf29ee6c 2747 u8 reg_idx = ring->reg_idx;
acd37177 2748
9e10e045
AD		 2749 /* disable queue to avoid issues while updating state */
2750 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2751 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2752
acd37177
AD		 2753 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2754 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2755 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2756 ring->count * sizeof(union ixgbe_adv_rx_desc));
2757 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2758 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2759 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2760
2761 ixgbe_configure_srrctl(adapter, ring);
2762 ixgbe_configure_rscctl(adapter, ring);
2763
e9f98072
GR		 2764 /* If operating in IOV mode set RLPML for X540 */
2765 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2766 hw->mac.type == ixgbe_mac_X540) {
2767 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2768 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2769 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2770 }
2771
9e10e045
AD		 2772 if (hw->mac.type == ixgbe_mac_82598EB) {
2773 /*
2774 * enable cache line friendly hardware writes:
2775 * PTHRESH=32 descriptors (half the internal cache),
2776 * this also removes ugly rx_no_buffer_count increment
2777 * HTHRESH=4 descriptors (to minimize latency on fetch)
2778 * WTHRESH=8 burst writeback up to two cache lines
2779 */
2780 rxdctl &= ~0x3FFFFF;
2781 rxdctl |= 0x080420;
2782 }
2783
2784 /* enable receive descriptor ring */
2785 rxdctl |= IXGBE_RXDCTL_ENABLE;
2786 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2787
2788 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2789 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2790}
2791
48654521
AD		 2792static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2793{
2794 struct ixgbe_hw *hw = &adapter->hw;
2795 int p;
2796
2797 /* PSRTYPE must be initialized in non 82598 adapters */
2798 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2799 IXGBE_PSRTYPE_UDPHDR |
2800 IXGBE_PSRTYPE_IPV4HDR |
48654521 2801 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2802 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2803
2804 if (hw->mac.type == ixgbe_mac_82598EB)
2805 return;
2806
2807 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2808 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2809
2810 for (p = 0; p < adapter->num_rx_pools; p++)
2811 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2812 psrtype);
2813}
2814
f5b4a52e
AD		 2815static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2816{
2817 struct ixgbe_hw *hw = &adapter->hw;
2818 u32 gcr_ext;
2819 u32 vt_reg_bits;
2820 u32 reg_offset, vf_shift;
2821 u32 vmdctl;
de4c7f65 2822 int i;
f5b4a52e
AD		 2823
2824 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2825 return;
2826
2827 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2828 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2829 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2830 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2831
2832 vf_shift = adapter->num_vfs % 32;
4cd6923d 2833 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 2834
2835 /* Enable only the PF's pool for Tx/Rx */
2836 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2837 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2838 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2839 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2840 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2841
2842 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2843 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2844
2845 /*
2846 * Set up VF register offsets for selected VT Mode,
2847 * i.e. 32 or 64 VFs for SR-IOV
2848 */
2849 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2850 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2851 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2852 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2853
2854 /* enable Tx loopback for VF/PF communication */
2855 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2856 /* Enable MAC Anti-Spoofing */
a1cbb15c 2857 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 2858 (adapter->num_vfs != 0),
a985b6c3 2859 adapter->num_vfs);
de4c7f65
GR		 2860 /* For VFs that have spoof checking turned off */
2861 for (i = 0; i < adapter->num_vfs; i++) {
2862 if (!adapter->vfinfo[i].spoofchk_enabled)
2863 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2864 }
f5b4a52e
AD		 2865}
2866
477de6ed 2867static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2868{
9a799d71
AK		 2869 struct ixgbe_hw *hw = &adapter->hw;
2870 struct net_device *netdev = adapter->netdev;
2871 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2872 int rx_buf_len;
477de6ed
AD		 2873 struct ixgbe_ring *rx_ring;
2874 int i;
2875 u32 mhadd, hlreg0;
48654521 2876
9a799d71 2877 /* Decide whether to use packet split mode or not */
a124339a
DS		 2878 /* On by default */
2879 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2880
1cdd1ec8 2881 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2882 if (adapter->num_vfs)
2883 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2884
2885 /* Disable packet split due to 82599 erratum #45 */
2886 if (hw->mac.type == ixgbe_mac_82599EB)
2887 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2888
63f39bd1 2889#ifdef IXGBE_FCOE
477de6ed
AD		 2890 /* adjust max frame to be able to do baby jumbo for FCoE */
2891 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2892 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2893 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2894
477de6ed
AD		 2895#endif /* IXGBE_FCOE */
2896 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2897 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2898 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2899 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2900
2901 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2902 }
2903
919e78a6
AD		 2904 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2905 max_frame += VLAN_HLEN;
2906
2907 /* Set the RX buffer length according to the mode */
2908 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2909 rx_buf_len = IXGBE_RX_HDR_SIZE;
2910 } else {
2911 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2912 (netdev->mtu <= ETH_DATA_LEN))
2913 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2914 /*
2915 * Make best use of allocation by using all but 1K of a
2916 * power of 2 allocation that will be used for skb->head.
2917 */
2918 else if (max_frame <= IXGBE_RXBUFFER_3K)
2919 rx_buf_len = IXGBE_RXBUFFER_3K;
2920 else if (max_frame <= IXGBE_RXBUFFER_7K)
2921 rx_buf_len = IXGBE_RXBUFFER_7K;
2922 else if (max_frame <= IXGBE_RXBUFFER_15K)
2923 rx_buf_len = IXGBE_RXBUFFER_15K;
2924 else
2925 rx_buf_len = IXGBE_MAX_RXBUFFER;
2926 }
2927
477de6ed
AD		 2928 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2929 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2930 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2931 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2932
0cefafad
JB		 2933 /*
2934 * Setup the HW Rx Head and Tail Descriptor Pointers and
2935 * the Base and Length of the Rx Descriptor Ring
2936 */
9a799d71 2937 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2938 rx_ring = adapter->rx_ring[i];
a6616b42 2939 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2940
6e455b89 2941 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2942 set_ring_ps_enabled(rx_ring);
2943 else
2944 clear_ring_ps_enabled(rx_ring);
2945
2946 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2947 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2948 else
7d637bcc 2949 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2950
63f39bd1 2951#ifdef IXGBE_FCOE
e8e9f696 2952 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2953 struct ixgbe_ring_feature *f;
2954 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2955 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2956 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2957 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2958 rx_ring->rx_buf_len =
e8e9f696 2959 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2960 } else if (!ring_is_rsc_enabled(rx_ring) &&
2961 !ring_is_ps_enabled(rx_ring)) {
2962 rx_ring->rx_buf_len =
2963 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2964 }
63f39bd1 2965 }
63f39bd1 2966#endif /* IXGBE_FCOE */
477de6ed 2967 }
477de6ed
AD		 2968}
2969
7367096a
AD		 2970static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2971{
2972 struct ixgbe_hw *hw = &adapter->hw;
2973 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2974
2975 switch (hw->mac.type) {
2976 case ixgbe_mac_82598EB:
2977 /*
2978 * For VMDq support of different descriptor types or
2979 * buffer sizes through the use of multiple SRRCTL
2980 * registers, RDRXCTL.MVMEN must be set to 1
2981 *
2982 * also, the manual doesn't mention it clearly but DCA hints
2983 * will only use queue 0's tags unless this bit is set. Side
2984 * effects of setting this bit are only that SRRCTL must be
2985 * fully programmed [0..15]
2986 */
2987 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2988 break;
2989 case ixgbe_mac_82599EB:
b93a2226 2990 case ixgbe_mac_X540:
7367096a
AD		 2991 /* Disable RSC for ACK packets */
2992 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2993 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2994 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2995 /* hardware requires some bits to be set by default */
2996 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2997 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2998 break;
2999 default:
3000 /* We should do nothing since we don't know this hardware */
3001 return;
3002 }
3003
3004 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3005}
3006
477de6ed
AD		 3007/**
3008 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3009 * @adapter: board private structure
3010 *
3011 * Configure the Rx unit of the MAC after a reset.
3012 **/
3013static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3014{
3015 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3016 int i;
3017 u32 rxctrl;
477de6ed
AD		 3018
3019 /* disable receives while setting up the descriptors */
3020 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3021 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3022
3023 ixgbe_setup_psrtype(adapter);
7367096a 3024 ixgbe_setup_rdrxctl(adapter);
477de6ed 3025
9e10e045 3026 /* Program registers for the distribution of queues */
f5b4a52e 3027 ixgbe_setup_mrqc(adapter);
f5b4a52e 3028
9e10e045
AD		 3029 ixgbe_set_uta(adapter);
3030
477de6ed
AD		 3031 /* set_rx_buffer_len must be called before ring initialization */
3032 ixgbe_set_rx_buffer_len(adapter);
3033
3034 /*
3035 * Setup the HW Rx Head and Tail Descriptor Pointers and
3036 * the Base and Length of the Rx Descriptor Ring
3037 */
9e10e045
AD		 3038 for (i = 0; i < adapter->num_rx_queues; i++)
3039 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3040
9e10e045
AD		 3041 /* disable drop enable for 82598 parts */
3042 if (hw->mac.type == ixgbe_mac_82598EB)
3043 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3044
3045 /* enable all receives */
3046 rxctrl |= IXGBE_RXCTRL_RXEN;
3047 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3048}
3049
8e586137 3050static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3051{
3052 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3053 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3054 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3055
3056 /* add VID to filter table */
1ada1b1b 3057 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3058 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3059
3060 return 0;
068c89b0
DS		 3061}
3062
8e586137 3063static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3064{
3065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3066 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3067 int pool_ndx = adapter->num_vfs;
068c89b0 3068
068c89b0 3069 /* remove VID from filter table */
1ada1b1b 3070 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3071 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3072
3073 return 0;
068c89b0
DS		 3074}
3075
5f6c0181
JB		 3076/**
3077 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3078 * @adapter: driver data
3079 */
3080static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3081{
3082 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3083 u32 vlnctrl;
3084
3085 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3086 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3087 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3088}
3089
3090/**
3091 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3092 * @adapter: driver data
3093 */
3094static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3095{
3096 struct ixgbe_hw *hw = &adapter->hw;
3097 u32 vlnctrl;
3098
3099 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3100 vlnctrl |= IXGBE_VLNCTRL_VFE;
3101 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3102 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3103}
3104
3105/**
3106 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3107 * @adapter: driver data
3108 */
3109static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3110{
3111 struct ixgbe_hw *hw = &adapter->hw;
3112 u32 vlnctrl;
5f6c0181
JB		 3113 int i, j;
3114
3115 switch (hw->mac.type) {
3116 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3117 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3118 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3119 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3120 break;
3121 case ixgbe_mac_82599EB:
b93a2226 3122 case ixgbe_mac_X540:
5f6c0181
JB		 3123 for (i = 0; i < adapter->num_rx_queues; i++) {
3124 j = adapter->rx_ring[i]->reg_idx;
3125 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3126 vlnctrl &= ~IXGBE_RXDCTL_VME;
3127 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3128 }
3129 break;
3130 default:
3131 break;
3132 }
3133}
3134
3135/**
f62bbb5e 3136 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3137 * @adapter: driver data
3138 */
f62bbb5e 3139static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3140{
3141 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3142 u32 vlnctrl;
5f6c0181
JB		 3143 int i, j;
3144
3145 switch (hw->mac.type) {
3146 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3147 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3148 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3149 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3150 break;
3151 case ixgbe_mac_82599EB:
b93a2226 3152 case ixgbe_mac_X540:
5f6c0181
JB		 3153 for (i = 0; i < adapter->num_rx_queues; i++) {
3154 j = adapter->rx_ring[i]->reg_idx;
3155 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3156 vlnctrl |= IXGBE_RXDCTL_VME;
3157 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3158 }
3159 break;
3160 default:
3161 break;
3162 }
3163}
3164
9a799d71
AK		 3165static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3166{
f62bbb5e 3167 u16 vid;
9a799d71 3168
f62bbb5e
JG		 3169 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3170
3171 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3172 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3173}
3174
2850062a
AD		 3175/**
3176 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3177 * @netdev: network interface device structure
3178 *
3179 * Writes unicast address list to the RAR table.
3180 * Returns: -ENOMEM on failure/insufficient address space
3181 * 0 on no addresses written
3182 * X on writing X addresses to the RAR table
3183 **/
3184static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3185{
3186 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3187 struct ixgbe_hw *hw = &adapter->hw;
3188 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3189 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3190 int count = 0;
3191
3192 /* return ENOMEM indicating insufficient memory for addresses */
3193 if (netdev_uc_count(netdev) > rar_entries)
3194 return -ENOMEM;
3195
3196 if (!netdev_uc_empty(netdev) && rar_entries) {
3197 struct netdev_hw_addr *ha;
3198 /* return error if we do not support writing to RAR table */
3199 if (!hw->mac.ops.set_rar)
3200 return -ENOMEM;
3201
3202 netdev_for_each_uc_addr(ha, netdev) {
3203 if (!rar_entries)
3204 break;
3205 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3206 vfn, IXGBE_RAH_AV);
3207 count++;
3208 }
3209 }
3210 /* write the addresses in reverse order to avoid write combining */
3211 for (; rar_entries > 0 ; rar_entries--)
3212 hw->mac.ops.clear_rar(hw, rar_entries);
3213
3214 return count;
3215}
3216
9a799d71 3217/**
2c5645cf 3218 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3219 * @netdev: network interface device structure
3220 *
2c5645cf
CL		 3221 * The set_rx_method entry point is called whenever the unicast/multicast
3222 * address list or the network interface flags are updated. This routine is
3223 * responsible for configuring the hardware for proper unicast, multicast and
3224 * promiscuous mode.
9a799d71 3225 **/
7f870475 3226void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3227{
3228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3229 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3230 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3231 int count;
9a799d71
AK		 3232
3233 /* Check for Promiscuous and All Multicast modes */
3234
3235 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3236
f5dc442b
AD		 3237 /* set all bits that we expect to always be set */
3238 fctrl |= IXGBE_FCTRL_BAM;
3239 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3240 fctrl |= IXGBE_FCTRL_PMCF;
3241
2850062a
AD		 3242 /* clear the bits we are changing the status of */
3243 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3244
9a799d71 3245 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3246 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3247 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3248 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3249 /* don't hardware filter vlans in promisc mode */
3250 ixgbe_vlan_filter_disable(adapter);
9a799d71 3251 } else {
746b9f02
PM		 3252 if (netdev->flags & IFF_ALLMULTI) {
3253 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3254 vmolr |= IXGBE_VMOLR_MPE;
3255 } else {
3256 /*
3257 * Write addresses to the MTA, if the attempt fails
25985edc 3258 * then we should just turn on promiscuous mode so
2850062a
AD		 3259 * that we can at least receive multicast traffic
3260 */
3261 hw->mac.ops.update_mc_addr_list(hw, netdev);
3262 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3263 }
5f6c0181 3264 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3265 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3266 /*
3267 * Write addresses to available RAR registers, if there is not
3268 * sufficient space to store all the addresses then enable
25985edc 3269 * unicast promiscuous mode
2850062a
AD		 3270 */
3271 count = ixgbe_write_uc_addr_list(netdev);
3272 if (count < 0) {
3273 fctrl |= IXGBE_FCTRL_UPE;
3274 vmolr |= IXGBE_VMOLR_ROPE;
3275 }
9a799d71
AK		 3276 }
3277
2850062a 3278 if (adapter->num_vfs) {
1cdd1ec8 3279 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3280 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3281 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3282 IXGBE_VMOLR_ROPE);
3283 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3284 }
3285
3286 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3287
3288 if (netdev->features & NETIF_F_HW_VLAN_RX)
3289 ixgbe_vlan_strip_enable(adapter);
3290 else
3291 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3292}
3293
021230d4
AV		 3294static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3295{
3296 int q_idx;
3297 struct ixgbe_q_vector *q_vector;
3298 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3299
3300 /* legacy and MSI only use one vector */
3301 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3302 q_vectors = 1;
3303
3304 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3305 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3306 napi_enable(&q_vector->napi);
021230d4
AV		 3307 }
3308}
3309
3310static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3311{
3312 int q_idx;
3313 struct ixgbe_q_vector *q_vector;
3314 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3315
3316 /* legacy and MSI only use one vector */
3317 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3318 q_vectors = 1;
3319
3320 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3321 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3322 napi_disable(&q_vector->napi);
3323 }
3324}
3325
7a6b6f51 3326#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3327/*
3328 * ixgbe_configure_dcb - Configure DCB hardware
3329 * @adapter: ixgbe adapter struct
3330 *
3331 * This is called by the driver on open to configure the DCB hardware.
3332 * This is also called by the gennetlink interface when reconfiguring
3333 * the DCB state.
3334 */
3335static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3336{
3337 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3338 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3339
67ebd791
AD		 3340 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3341 if (hw->mac.type == ixgbe_mac_82598EB)
3342 netif_set_gso_max_size(adapter->netdev, 65536);
3343 return;
3344 }
3345
3346 if (hw->mac.type == ixgbe_mac_82598EB)
3347 netif_set_gso_max_size(adapter->netdev, 32768);
3348
2f90b865 3349
2f90b865 3350 /* Enable VLAN tag insert/strip */
f62bbb5e 3351 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3352
2f90b865 3353 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3354
971060b1 3355#ifdef IXGBE_FCOE
b120818e
JF		 3356 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3357 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3358#endif
b120818e
JF		 3359
3360 /* reconfigure the hardware */
3361 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3362 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3363 DCB_TX_CONFIG);
3364 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3365 DCB_RX_CONFIG);
3366 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3367 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3368 ixgbe_dcb_hw_ets(&adapter->hw,
3369 adapter->ixgbe_ieee_ets,
3370 max_frame);
3371 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3372 adapter->ixgbe_ieee_pfc->pfc_en,
3373 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3374 }
8187cd48
JF		 3375
3376 /* Enable RSS Hash per TC */
3377 if (hw->mac.type != ixgbe_mac_82598EB) {
3378 int i;
3379 u32 reg = 0;
3380
3381 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3382 u8 msb = 0;
3383 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3384
3385 while (cnt >>= 1)
3386 msb++;
3387
3388 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3389 }
3390 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3391 }
2f90b865 3392}
9da712d2
JF		 3393#endif
3394
3395/* Additional bittime to account for IXGBE framing */
3396#define IXGBE_ETH_FRAMING 20
3397
3398/*
3399 * ixgbe_hpbthresh - calculate high water mark for flow control
3400 *
3401 * @adapter: board private structure to calculate for
3402 * @pb - packet buffer to calculate
3403 */
3404static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3405{
3406 struct ixgbe_hw *hw = &adapter->hw;
3407 struct net_device *dev = adapter->netdev;
3408 int link, tc, kb, marker;
3409 u32 dv_id, rx_pba;
3410
3411 /* Calculate max LAN frame size */
3412 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3413
3414#ifdef IXGBE_FCOE
3415 /* FCoE traffic class uses FCOE jumbo frames */
3416 if (dev->features & NETIF_F_FCOE_MTU) {
3417 int fcoe_pb = 0;
2f90b865 3418
9da712d2
JF		 3419#ifdef CONFIG_IXGBE_DCB
3420 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3421
3422#endif
3423 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3424 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3425 }
2f90b865 3426#endif
80605c65 3427
9da712d2
JF		 3428 /* Calculate delay value for device */
3429 switch (hw->mac.type) {
3430 case ixgbe_mac_X540:
3431 dv_id = IXGBE_DV_X540(link, tc);
3432 break;
3433 default:
3434 dv_id = IXGBE_DV(link, tc);
3435 break;
3436 }
3437
3438 /* Loopback switch introduces additional latency */
3439 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3440 dv_id += IXGBE_B2BT(tc);
3441
3442 /* Delay value is calculated in bit times convert to KB */
3443 kb = IXGBE_BT2KB(dv_id);
3444 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3445
3446 marker = rx_pba - kb;
3447
3448 /* It is possible that the packet buffer is not large enough
3449 * to provide required headroom. In this case throw an error
3450 * to user and a do the best we can.
3451 */
3452 if (marker < 0) {
3453 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3454 "headroom to support flow control."
3455 "Decrease MTU or number of traffic classes\n", pb);
3456 marker = tc + 1;
3457 }
3458
3459 return marker;
3460}
3461
3462/*
3463 * ixgbe_lpbthresh - calculate low water mark for for flow control
3464 *
3465 * @adapter: board private structure to calculate for
3466 * @pb - packet buffer to calculate
3467 */
3468static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3469{
3470 struct ixgbe_hw *hw = &adapter->hw;
3471 struct net_device *dev = adapter->netdev;
3472 int tc;
3473 u32 dv_id;
3474
3475 /* Calculate max LAN frame size */
3476 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3477
3478 /* Calculate delay value for device */
3479 switch (hw->mac.type) {
3480 case ixgbe_mac_X540:
3481 dv_id = IXGBE_LOW_DV_X540(tc);
3482 break;
3483 default:
3484 dv_id = IXGBE_LOW_DV(tc);
3485 break;
3486 }
3487
3488 /* Delay value is calculated in bit times convert to KB */
3489 return IXGBE_BT2KB(dv_id);
3490}
3491
3492/*
3493 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3494 */
3495static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3496{
3497 struct ixgbe_hw *hw = &adapter->hw;
3498 int num_tc = netdev_get_num_tc(adapter->netdev);
3499 int i;
3500
3501 if (!num_tc)
3502 num_tc = 1;
3503
3504 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3505
3506 for (i = 0; i < num_tc; i++) {
3507 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3508
3509 /* Low water marks must not be larger than high water marks */
3510 if (hw->fc.low_water > hw->fc.high_water[i])
3511 hw->fc.low_water = 0;
3512 }
3513}
3514
80605c65
JF		 3515static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3516{
80605c65 3517 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3518 int hdrm;
3519 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3520
3521 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3522 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3523 hdrm = 32 << adapter->fdir_pballoc;
3524 else
3525 hdrm = 0;
80605c65 3526
f7e1027f 3527 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3528 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3529}
3530
e4911d57
AD		 3531static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3532{
3533 struct ixgbe_hw *hw = &adapter->hw;
3534 struct hlist_node *node, *node2;
3535 struct ixgbe_fdir_filter *filter;
3536
3537 spin_lock(&adapter->fdir_perfect_lock);
3538
3539 if (!hlist_empty(&adapter->fdir_filter_list))
3540 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3541
3542 hlist_for_each_entry_safe(filter, node, node2,
3543 &adapter->fdir_filter_list, fdir_node) {
3544 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3545 &filter->filter,
3546 filter->sw_idx,
3547 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3548 IXGBE_FDIR_DROP_QUEUE :
3549 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3550 }
3551
3552 spin_unlock(&adapter->fdir_perfect_lock);
3553}
3554
9a799d71
AK		 3555static void ixgbe_configure(struct ixgbe_adapter *adapter)
3556{
80605c65 3557 ixgbe_configure_pb(adapter);
7a6b6f51 3558#ifdef CONFIG_IXGBE_DCB
67ebd791 3559 ixgbe_configure_dcb(adapter);
2f90b865 3560#endif
9a799d71 3561
4c1d7b4b 3562 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3563 ixgbe_restore_vlan(adapter);
3564
eacd73f7
YZ		 3565#ifdef IXGBE_FCOE
3566 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3567 ixgbe_configure_fcoe(adapter);
3568
3569#endif /* IXGBE_FCOE */
c4cf55e5 3570 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3571 ixgbe_init_fdir_signature_82599(&adapter->hw,
3572 adapter->fdir_pballoc);
e4911d57
AD		 3573 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3574 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3575 adapter->fdir_pballoc);
3576 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3577 }
4c1d7b4b 3578
933d41f1 3579 ixgbe_configure_virtualization(adapter);
c4cf55e5 3580
9a799d71
AK		 3581 ixgbe_configure_tx(adapter);
3582 ixgbe_configure_rx(adapter);
9a799d71
AK		 3583}
3584
e8e26350
PW		 3585static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3586{
3587 switch (hw->phy.type) {
3588 case ixgbe_phy_sfp_avago:
3589 case ixgbe_phy_sfp_ftl:
3590 case ixgbe_phy_sfp_intel:
3591 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3592 case ixgbe_phy_sfp_passive_tyco:
3593 case ixgbe_phy_sfp_passive_unknown:
3594 case ixgbe_phy_sfp_active_unknown:
3595 case ixgbe_phy_sfp_ftl_active:
e8e26350 3596 return true;
8917b447
AD		 3597 case ixgbe_phy_nl:
3598 if (hw->mac.type == ixgbe_mac_82598EB)
3599 return true;
e8e26350
PW		 3600 default:
3601 return false;
3602 }
3603}
3604
0ecc061d 3605/**
e8e26350
PW		 3606 * ixgbe_sfp_link_config - set up SFP+ link
3607 * @adapter: pointer to private adapter struct
3608 **/
3609static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3610{
7086400d 3611 /*
52f33af8 3612 * We are assuming the worst case scenario here, and that
7086400d
AD		 3613 * is that an SFP was inserted/removed after the reset
3614 * but before SFP detection was enabled. As such the best
3615 * solution is to just start searching as soon as we start
3616 */
3617 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3618 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3619
7086400d 3620 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3621}
3622
3623/**
3624 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3625 * @hw: pointer to private hardware struct
3626 *
3627 * Returns 0 on success, negative on failure
3628 **/
e8e26350 3629static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3630{
3631 u32 autoneg;
8620a103 3632 bool negotiation, link_up = false;
0ecc061d
PWJ		 3633 u32 ret = IXGBE_ERR_LINK_SETUP;
3634
3635 if (hw->mac.ops.check_link)
3636 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3637
3638 if (ret)
3639 goto link_cfg_out;
3640
0b0c2b31
ET		 3641 autoneg = hw->phy.autoneg_advertised;
3642 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3643 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3644 &negotiation);
0ecc061d
PWJ		 3645 if (ret)
3646 goto link_cfg_out;
3647
8620a103
MC		 3648 if (hw->mac.ops.setup_link)
3649 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3650link_cfg_out:
3651 return ret;
3652}
3653
a34bcfff 3654static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3655{
9a799d71 3656 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3657 u32 gpie = 0;
9a799d71 3658
9b471446 3659 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3660 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3661 IXGBE_GPIE_OCD;
3662 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3663 /*
3664 * use EIAM to auto-mask when MSI-X interrupt is asserted
3665 * this saves a register write for every interrupt
3666 */
3667 switch (hw->mac.type) {
3668 case ixgbe_mac_82598EB:
3669 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3670 break;
9b471446 3671 case ixgbe_mac_82599EB:
b93a2226
DS		 3672 case ixgbe_mac_X540:
3673 default:
9b471446
JB		 3674 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3675 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3676 break;
3677 }
3678 } else {
021230d4
AV		 3679 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3680 * specifically only auto mask tx and rx interrupts */
3681 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3682 }
9a799d71 3683
a34bcfff
AD		 3684 /* XXX: to interrupt immediately for EICS writes, enable this */
3685 /* gpie |= IXGBE_GPIE_EIMEN; */
3686
3687 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3688 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3689 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3690 }
3691
5fdd31f9 3692 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3693 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3694 switch (adapter->hw.mac.type) {
3695 case ixgbe_mac_82599EB:
3696 gpie |= IXGBE_SDP0_GPIEN;
3697 break;
3698 case ixgbe_mac_X540:
3699 gpie |= IXGBE_EIMS_TS;
3700 break;
3701 default:
3702 break;
3703 }
3704 }
5fdd31f9 3705
a34bcfff
AD		 3706 /* Enable fan failure interrupt */
3707 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3708 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3709
2698b208 3710 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3711 gpie |= IXGBE_SDP1_GPIEN;
3712 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3713 }
a34bcfff
AD		 3714
3715 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3716}
3717
c7ccde0f 3718static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3719{
3720 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3721 int err;
a34bcfff
AD		 3722 u32 ctrl_ext;
3723
3724 ixgbe_get_hw_control(adapter);
3725 ixgbe_setup_gpie(adapter);
e8e26350 3726
9a799d71
AK		 3727 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3728 ixgbe_configure_msix(adapter);
3729 else
3730 ixgbe_configure_msi_and_legacy(adapter);
3731
c6ecf39a
DS		 3732 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3733 if (hw->mac.ops.enable_tx_laser &&
3734 ((hw->phy.multispeed_fiber) ||
9f911707 3735 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3736 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3737 hw->mac.ops.enable_tx_laser(hw);
3738
9a799d71 3739 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3740 ixgbe_napi_enable_all(adapter);
3741
73c4b7cd
AD		 3742 if (ixgbe_is_sfp(hw)) {
3743 ixgbe_sfp_link_config(adapter);
3744 } else {
3745 err = ixgbe_non_sfp_link_config(hw);
3746 if (err)
3747 e_err(probe, "link_config FAILED %d\n", err);
3748 }
3749
021230d4
AV		 3750 /* clear any pending interrupts, may auto mask */
3751 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3752 ixgbe_irq_enable(adapter, true, true);
9a799d71 3753
bf069c97
DS		 3754 /*
3755 * If this adapter has a fan, check to see if we had a failure
3756 * before we enabled the interrupt.
3757 */
3758 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3759 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3760 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3761 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3762 }
3763
1da100bb 3764 /* enable transmits */
477de6ed 3765 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3766
9a799d71
AK		 3767 /* bring the link up in the watchdog, this could race with our first
3768 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3769 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3770 adapter->link_check_timeout = jiffies;
7086400d 3771 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3772
3773 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3774 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3775 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3776 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3777}
3778
d4f80882
AV		 3779void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3780{
3781 WARN_ON(in_interrupt());
7086400d
AD		 3782 /* put off any impending NetWatchDogTimeout */
3783 adapter->netdev->trans_start = jiffies;
3784
d4f80882 3785 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3786 usleep_range(1000, 2000);
d4f80882 3787 ixgbe_down(adapter);
5809a1ae
GR		 3788 /*
3789 * If SR-IOV enabled then wait a bit before bringing the adapter
3790 * back up to give the VFs time to respond to the reset. The
3791 * two second wait is based upon the watchdog timer cycle in
3792 * the VF driver.
3793 */
3794 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3795 msleep(2000);
d4f80882
AV		 3796 ixgbe_up(adapter);
3797 clear_bit(__IXGBE_RESETTING, &adapter->state);
3798}
3799
c7ccde0f 3800void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3801{
3802 /* hardware has been reset, we need to reload some things */
3803 ixgbe_configure(adapter);
3804
c7ccde0f 3805 ixgbe_up_complete(adapter);
9a799d71
AK		 3806}
3807
3808void ixgbe_reset(struct ixgbe_adapter *adapter)
3809{
c44ade9e 3810 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3811 int err;
3812
7086400d
AD		 3813 /* lock SFP init bit to prevent race conditions with the watchdog */
3814 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3815 usleep_range(1000, 2000);
3816
3817 /* clear all SFP and link config related flags while holding SFP_INIT */
3818 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3819 IXGBE_FLAG2_SFP_NEEDS_RESET);
3820 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3821
8ca783ab 3822 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3823 switch (err) {
3824 case 0:
3825 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3826 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3827 break;
3828 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3829 e_dev_err("master disable timed out\n");
da4dd0f7 3830 break;
794caeb2
PWJ		 3831 case IXGBE_ERR_EEPROM_VERSION:
3832 /* We are running on a pre-production device, log a warning */
849c4542 3833 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 3834 "Please be aware there may be issues associated with "
849c4542
ET		 3835 "your hardware. If you are experiencing problems "
3836 "please contact your Intel or hardware "
3837 "representative who provided you with this "
3838 "hardware.\n");
794caeb2 3839 break;
da4dd0f7 3840 default:
849c4542 3841 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3842 }
9a799d71 3843
7086400d
AD		 3844 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3845
9a799d71 3846 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3847 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3848 IXGBE_RAH_AV);
9a799d71
AK		 3849}
3850
9a799d71
AK		 3851/**
3852 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3853 * @rx_ring: ring to free buffers from
3854 **/
b6ec895e 3855static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3856{
b6ec895e 3857 struct device *dev = rx_ring->dev;
9a799d71 3858 unsigned long size;
b6ec895e 3859 u16 i;
9a799d71 3860
84418e3b
AD		 3861 /* ring already cleared, nothing to do */
3862 if (!rx_ring->rx_buffer_info)
3863 return;
9a799d71 3864
84418e3b 3865 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3866 for (i = 0; i < rx_ring->count; i++) {
3867 struct ixgbe_rx_buffer *rx_buffer_info;
3868
3869 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3870 if (rx_buffer_info->dma) {
b6ec895e 3871 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3872 rx_ring->rx_buf_len,
1b507730 3873 DMA_FROM_DEVICE);
9a799d71
AK		 3874 rx_buffer_info->dma = 0;
3875 }
3876 if (rx_buffer_info->skb) {
f8212f97 3877 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3878 rx_buffer_info->skb = NULL;
f8212f97
AD		 3879 do {
3880 struct sk_buff *this = skb;
e8171aaa 3881 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3882 dma_unmap_single(dev,
1b507730 3883 IXGBE_RSC_CB(this)->dma,
e8e9f696 3884 rx_ring->rx_buf_len,
1b507730 3885 DMA_FROM_DEVICE);
fd3686a8 3886 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3887 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3888 }
f8212f97
AD		 3889 skb = skb->prev;
3890 dev_kfree_skb(this);
3891 } while (skb);
9a799d71
AK		 3892 }
3893 if (!rx_buffer_info->page)
3894 continue;
4f57ca6e 3895 if (rx_buffer_info->page_dma) {
b6ec895e 3896 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3897 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3898 rx_buffer_info->page_dma = 0;
3899 }
9a799d71
AK		 3900 put_page(rx_buffer_info->page);
3901 rx_buffer_info->page = NULL;
762f4c57 3902 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3903 }
3904
3905 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3906 memset(rx_ring->rx_buffer_info, 0, size);
3907
3908 /* Zero out the descriptor ring */
3909 memset(rx_ring->desc, 0, rx_ring->size);
3910
3911 rx_ring->next_to_clean = 0;
3912 rx_ring->next_to_use = 0;
9a799d71
AK		 3913}
3914
3915/**
3916 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3917 * @tx_ring: ring to be cleaned
3918 **/
b6ec895e 3919static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3920{
3921 struct ixgbe_tx_buffer *tx_buffer_info;
3922 unsigned long size;
b6ec895e 3923 u16 i;
9a799d71 3924
84418e3b
AD		 3925 /* ring already cleared, nothing to do */
3926 if (!tx_ring->tx_buffer_info)
3927 return;
9a799d71 3928
84418e3b 3929 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3930 for (i = 0; i < tx_ring->count; i++) {
3931 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3932 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3933 }
3934
3935 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3936 memset(tx_ring->tx_buffer_info, 0, size);
3937
3938 /* Zero out the descriptor ring */
3939 memset(tx_ring->desc, 0, tx_ring->size);
3940
3941 tx_ring->next_to_use = 0;
3942 tx_ring->next_to_clean = 0;
9a799d71
AK		 3943}
3944
3945/**
021230d4 3946 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3947 * @adapter: board private structure
3948 **/
021230d4 3949static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3950{
3951 int i;
3952
021230d4 3953 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3954 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3955}
3956
3957/**
021230d4 3958 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3959 * @adapter: board private structure
3960 **/
021230d4 3961static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3962{
3963 int i;
3964
021230d4 3965 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3966 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3967}
3968
e4911d57
AD		 3969static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3970{
3971 struct hlist_node *node, *node2;
3972 struct ixgbe_fdir_filter *filter;
3973
3974 spin_lock(&adapter->fdir_perfect_lock);
3975
3976 hlist_for_each_entry_safe(filter, node, node2,
3977 &adapter->fdir_filter_list, fdir_node) {
3978 hlist_del(&filter->fdir_node);
3979 kfree(filter);
3980 }
3981 adapter->fdir_filter_count = 0;
3982
3983 spin_unlock(&adapter->fdir_perfect_lock);
3984}
3985
9a799d71
AK		 3986void ixgbe_down(struct ixgbe_adapter *adapter)
3987{
3988 struct net_device *netdev = adapter->netdev;
7f821875 3989 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3990 u32 rxctrl;
bf29ee6c 3991 int i;
9a799d71
AK		 3992
3993 /* signal that we are down to the interrupt handler */
3994 set_bit(__IXGBE_DOWN, &adapter->state);
3995
3996 /* disable receives */
7f821875
JB		 3997 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3998 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3999
2d39d576
YZ		 4000 /* disable all enabled rx queues */
4001 for (i = 0; i < adapter->num_rx_queues; i++)
4002 /* this call also flushes the previous write */
4003 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4004
032b4325 4005 usleep_range(10000, 20000);
9a799d71 4006
7f821875
JB		 4007 netif_tx_stop_all_queues(netdev);
4008
7086400d 4009 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4010 netif_carrier_off(netdev);
4011 netif_tx_disable(netdev);
4012
4013 ixgbe_irq_disable(adapter);
4014
4015 ixgbe_napi_disable_all(adapter);
4016
d034acf1
AD		 4017 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4018 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4019 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4020
4021 del_timer_sync(&adapter->service_timer);
4022
34cecbbf 4023 if (adapter->num_vfs) {
8e34d1aa
AD		 4024 /* Clear EITR Select mapping */
4025 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4026
4027 /* Mark all the VFs as inactive */
4028 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4029 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4030
34cecbbf
AD		 4031 /* ping all the active vfs to let them know we are going down */
4032 ixgbe_ping_all_vfs(adapter);
4033
4034 /* Disable all VFTE/VFRE TX/RX */
4035 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4036 }
4037
7f821875
JB		 4038 /* disable transmits in the hardware now that interrupts are off */
4039 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4040 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4041 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4042 }
34cecbbf
AD		 4043
4044 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4045 switch (hw->mac.type) {
4046 case ixgbe_mac_82599EB:
b93a2226 4047 case ixgbe_mac_X540:
88512539 4048 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4049 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4050 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4051 break;
4052 default:
4053 break;
4054 }
7f821875 4055
6f4a0e45
PL		 4056 if (!pci_channel_offline(adapter->pdev))
4057 ixgbe_reset(adapter);
c6ecf39a
DS		 4058
4059 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4060 if (hw->mac.ops.disable_tx_laser &&
4061 ((hw->phy.multispeed_fiber) ||
9f911707 4062 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4063 (hw->mac.type == ixgbe_mac_82599EB))))
4064 hw->mac.ops.disable_tx_laser(hw);
4065
9a799d71
AK		 4066 ixgbe_clean_all_tx_rings(adapter);
4067 ixgbe_clean_all_rx_rings(adapter);
4068
5dd2d332 4069#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4070 /* since we reset the hardware DCA settings were cleared */
e35ec126 4071 ixgbe_setup_dca(adapter);
96b0e0f6 4072#endif
9a799d71
AK		 4073}
4074
9a799d71 4075/**
021230d4
AV		 4076 * ixgbe_poll - NAPI Rx polling callback
4077 * @napi: structure for representing this polling device
4078 * @budget: how many packets driver is allowed to clean
4079 *
4080 * This function is used for legacy and MSI, NAPI mode
9a799d71 4081 **/
021230d4 4082static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4083{
9a1a69ad 4084 struct ixgbe_q_vector *q_vector =
e8e9f696 4085 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4086 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4087 struct ixgbe_ring *ring;
4088 int per_ring_budget;
4089 bool clean_complete = true;
9a799d71 4090
5dd2d332 4091#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4092 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4093 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4094#endif
4095
4ff7fb12
AD		 4096 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4097 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4098
4ff7fb12
AD		 4099 /* attempt to distribute budget to each queue fairly, but don't allow
4100 * the budget to go below 1 because we'll exit polling */
4101 if (q_vector->rx.count > 1)
4102 per_ring_budget = max(budget/q_vector->rx.count, 1);
4103 else
4104 per_ring_budget = budget;
d2c7ddd6 4105
4ff7fb12
AD		 4106 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4107 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4108 per_ring_budget);
4109
4110 /* If all work not completed, return budget and keep polling */
4111 if (!clean_complete)
4112 return budget;
4113
4114 /* all work done, exit the polling mode */
4115 napi_complete(napi);
4116 if (adapter->rx_itr_setting & 1)
4117 ixgbe_set_itr(q_vector);
4118 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4119 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4120
4121 return 0;
9a799d71
AK		 4122}
4123
4124/**
4125 * ixgbe_tx_timeout - Respond to a Tx Hang
4126 * @netdev: network interface device structure
4127 **/
4128static void ixgbe_tx_timeout(struct net_device *netdev)
4129{
4130 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4131
4132 /* Do the reset outside of interrupt context */
c83c6cbd 4133 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4134}
4135
4df10466
JB		 4136/**
4137 * ixgbe_set_rss_queues: Allocate queues for RSS
4138 * @adapter: board private structure to initialize
4139 *
4140 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4141 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4142 *
4143 **/
bc97114d
PWJ		 4144static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4145{
4146 bool ret = false;
0cefafad 4147 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4148
4149 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4150 f->mask = 0xF;
4151 adapter->num_rx_queues = f->indices;
4152 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4153 ret = true;
4154 } else {
bc97114d 4155 ret = false;
b9804972
JB		 4156 }
4157
bc97114d
PWJ		 4158 return ret;
4159}
4160
c4cf55e5
PWJ		 4161/**
4162 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4163 * @adapter: board private structure to initialize
4164 *
4165 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4166 * to the original CPU that initiated the Tx session. This runs in addition
4167 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4168 * Rx load across CPUs using RSS.
4169 *
4170 **/
e8e9f696 4171static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4172{
4173 bool ret = false;
4174 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4175
4176 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4177 f_fdir->mask = 0;
4178
4179 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4180 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4181 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4182 adapter->num_tx_queues = f_fdir->indices;
4183 adapter->num_rx_queues = f_fdir->indices;
4184 ret = true;
4185 } else {
4186 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4187 }
4188 return ret;
4189}
4190
0331a832
YZ		 4191#ifdef IXGBE_FCOE
4192/**
4193 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4194 * @adapter: board private structure to initialize
4195 *
4196 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4197 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4198 * rx queues out of the max number of rx queues, instead, it is used as the
4199 * index of the first rx queue used by FCoE.
4200 *
4201 **/
4202static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4203{
0331a832
YZ		 4204 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4205
e5b64635
JF		 4206 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4207 return false;
4208
e901acd6 4209 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4210
e901acd6
JF		 4211 adapter->num_rx_queues = 1;
4212 adapter->num_tx_queues = 1;
e5b64635 4213
e901acd6
JF		 4214 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4215 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4216 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4217 ixgbe_set_fdir_queues(adapter);
4218 else
4219 ixgbe_set_rss_queues(adapter);
e5b64635 4220 }
03ecf91a 4221
e901acd6
JF		 4222 /* adding FCoE rx rings to the end */
4223 f->mask = adapter->num_rx_queues;
4224 adapter->num_rx_queues += f->indices;
4225 adapter->num_tx_queues += f->indices;
0331a832 4226
e5b64635
JF		 4227 return true;
4228}
4229#endif /* IXGBE_FCOE */
4230
e901acd6
JF		 4231/* Artificial max queue cap per traffic class in DCB mode */
4232#define DCB_QUEUE_CAP 8
4233
e5b64635
JF		 4234#ifdef CONFIG_IXGBE_DCB
4235static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4236{
e901acd6
JF		 4237 int per_tc_q, q, i, offset = 0;
4238 struct net_device *dev = adapter->netdev;
4239 int tcs = netdev_get_num_tc(dev);
e5b64635 4240
e901acd6
JF		 4241 if (!tcs)
4242 return false;
e5b64635 4243
e901acd6
JF		 4244 /* Map queue offset and counts onto allocated tx queues */
4245 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4246 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4247
8b1c0b24 4248 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4249 netdev_set_tc_queue(dev, i, q, offset);
4250 offset += q;
0331a832
YZ		 4251 }
4252
e901acd6
JF		 4253 adapter->num_tx_queues = q * tcs;
4254 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4255
4256#ifdef IXGBE_FCOE
e901acd6
JF		 4257 /* FCoE enabled queues require special configuration indexed
4258 * by feature specific indices and mask. Here we map FCoE
4259 * indices onto the DCB queue pairs allowing FCoE to own
4260 * configuration later.
e5b64635 4261 */
e901acd6
JF		 4262 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4263 int tc;
4264 struct ixgbe_ring_feature *f =
4265 &adapter->ring_feature[RING_F_FCOE];
4266
4267 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4268 f->indices = dev->tc_to_txq[tc].count;
4269 f->mask = dev->tc_to_txq[tc].offset;
4270 }
e5b64635
JF		 4271#endif
4272
e901acd6 4273 return true;
0331a832 4274}
e5b64635 4275#endif
0331a832 4276
1cdd1ec8
GR		 4277/**
4278 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4279 * @adapter: board private structure to initialize
4280 *
4281 * IOV doesn't actually use anything, so just NAK the
4282 * request for now and let the other queue routines
4283 * figure out what to do.
4284 */
4285static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4286{
4287 return false;
4288}
4289
4df10466 4290/*
25985edc 4291 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4292 * @adapter: board private structure to initialize
4293 *
4294 * This is the top level queue allocation routine. The order here is very
4295 * important, starting with the "most" number of features turned on at once,
4296 * and ending with the smallest set of features. This way large combinations
4297 * can be allocated if they're turned on, and smaller combinations are the
4298 * fallthrough conditions.
4299 *
4300 **/
847f53ff 4301static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4302{
1cdd1ec8
GR		 4303 /* Start with base case */
4304 adapter->num_rx_queues = 1;
4305 adapter->num_tx_queues = 1;
4306 adapter->num_rx_pools = adapter->num_rx_queues;
4307 adapter->num_rx_queues_per_pool = 1;
4308
4309 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4310 goto done;
1cdd1ec8 4311
bc97114d
PWJ		 4312#ifdef CONFIG_IXGBE_DCB
4313 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4314 goto done;
bc97114d
PWJ		 4315
4316#endif
e5b64635
JF		 4317#ifdef IXGBE_FCOE
4318 if (ixgbe_set_fcoe_queues(adapter))
4319 goto done;
4320
4321#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4322 if (ixgbe_set_fdir_queues(adapter))
4323 goto done;
4324
bc97114d 4325 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4326 goto done;
4327
4328 /* fallback to base case */
4329 adapter->num_rx_queues = 1;
4330 adapter->num_tx_queues = 1;
4331
4332done:
847f53ff 4333 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4334 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4335 return netif_set_real_num_rx_queues(adapter->netdev,
4336 adapter->num_rx_queues);
b9804972
JB		 4337}
4338
021230d4 4339static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4340 int vectors)
021230d4
AV		 4341{
4342 int err, vector_threshold;
4343
4344 /* We'll want at least 3 (vector_threshold):
4345 * 1) TxQ[0] Cleanup
4346 * 2) RxQ[0] Cleanup
4347 * 3) Other (Link Status Change, etc.)
4348 * 4) TCP Timer (optional)
4349 */
4350 vector_threshold = MIN_MSIX_COUNT;
4351
4352 /* The more we get, the more we will assign to Tx/Rx Cleanup
4353 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4354 * Right now, we simply care about how many we'll get; we'll
4355 * set them up later while requesting irq's.
4356 */
4357 while (vectors >= vector_threshold) {
4358 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4359 vectors);
021230d4
AV		 4360 if (!err) /* Success in acquiring all requested vectors. */
4361 break;
4362 else if (err < 0)
4363 vectors = 0; /* Nasty failure, quit now */
4364 else /* err == number of vectors we should try again with */
4365 vectors = err;
4366 }
4367
4368 if (vectors < vector_threshold) {
4369 /* Can't allocate enough MSI-X interrupts? Oh well.
4370 * This just means we'll go with either a single MSI
4371 * vector or fall back to legacy interrupts.
4372 */
849c4542
ET		 4373 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4374 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4375 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4376 kfree(adapter->msix_entries);
4377 adapter->msix_entries = NULL;
021230d4
AV		 4378 } else {
4379 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4380 /*
4381 * Adjust for only the vectors we'll use, which is minimum
4382 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4383 * vectors we were allocated.
4384 */
4385 adapter->num_msix_vectors = min(vectors,
e8e9f696 4386 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4387 }
4388}
4389
021230d4 4390/**
bc97114d 4391 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4392 * @adapter: board private structure to initialize
4393 *
bc97114d
PWJ		 4394 * Cache the descriptor ring offsets for RSS to the assigned rings.
4395 *
021230d4 4396 **/
bc97114d 4397static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4398{
bc97114d 4399 int i;
bc97114d 4400
9d6b758f
AD		 4401 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4402 return false;
bc97114d 4403
9d6b758f
AD		 4404 for (i = 0; i < adapter->num_rx_queues; i++)
4405 adapter->rx_ring[i]->reg_idx = i;
4406 for (i = 0; i < adapter->num_tx_queues; i++)
4407 adapter->tx_ring[i]->reg_idx = i;
4408
4409 return true;
bc97114d
PWJ		 4410}
4411
4412#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4413
4414/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4415static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4416 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4417{
4418 struct net_device *dev = adapter->netdev;
4419 struct ixgbe_hw *hw = &adapter->hw;
4420 u8 num_tcs = netdev_get_num_tc(dev);
4421
4422 *tx = 0;
4423 *rx = 0;
4424
4425 switch (hw->mac.type) {
4426 case ixgbe_mac_82598EB:
aba70d5e
JF		 4427 *tx = tc << 2;
4428 *rx = tc << 3;
e5b64635
JF		 4429 break;
4430 case ixgbe_mac_82599EB:
4431 case ixgbe_mac_X540:
4fa2e0e1 4432 if (num_tcs > 4) {
e5b64635
JF		 4433 if (tc < 3) {
4434 *tx = tc << 5;
4435 *rx = tc << 4;
4436 } else if (tc < 5) {
4437 *tx = ((tc + 2) << 4);
4438 *rx = tc << 4;
4439 } else if (tc < num_tcs) {
4440 *tx = ((tc + 8) << 3);
4441 *rx = tc << 4;
4442 }
4fa2e0e1 4443 } else {
e5b64635
JF		 4444 *rx = tc << 5;
4445 switch (tc) {
4446 case 0:
4447 *tx = 0;
4448 break;
4449 case 1:
4450 *tx = 64;
4451 break;
4452 case 2:
4453 *tx = 96;
4454 break;
4455 case 3:
4456 *tx = 112;
4457 break;
4458 default:
4459 break;
4460 }
4461 }
4462 break;
4463 default:
4464 break;
4465 }
4466}
4467
bc97114d
PWJ		 4468/**
4469 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4470 * @adapter: board private structure to initialize
4471 *
4472 * Cache the descriptor ring offsets for DCB to the assigned rings.
4473 *
4474 **/
4475static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4476{
e5b64635
JF		 4477 struct net_device *dev = adapter->netdev;
4478 int i, j, k;
4479 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4480
8b1c0b24 4481 if (!num_tcs)
bd508178 4482 return false;
f92ef202 4483
e5b64635
JF		 4484 for (i = 0, k = 0; i < num_tcs; i++) {
4485 unsigned int tx_s, rx_s;
4486 u16 count = dev->tc_to_txq[i].count;
4487
4488 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4489 for (j = 0; j < count; j++, k++) {
4490 adapter->tx_ring[k]->reg_idx = tx_s + j;
4491 adapter->rx_ring[k]->reg_idx = rx_s + j;
4492 adapter->tx_ring[k]->dcb_tc = i;
4493 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4494 }
021230d4 4495 }
e5b64635
JF		 4496
4497 return true;
bc97114d
PWJ		 4498}
4499#endif
4500
c4cf55e5
PWJ		 4501/**
4502 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4503 * @adapter: board private structure to initialize
4504 *
4505 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4506 *
4507 **/
e8e9f696 4508static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4509{
4510 int i;
4511 bool ret = false;
4512
03ecf91a
AD		 4513 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4514 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4515 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4516 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4517 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4518 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4519 ret = true;
4520 }
4521
4522 return ret;
4523}
4524
0331a832
YZ		 4525#ifdef IXGBE_FCOE
4526/**
4527 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4528 * @adapter: board private structure to initialize
4529 *
4530 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4531 *
4532 */
4533static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4534{
0331a832 4535 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4536 int i;
4537 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4538
4539 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4540 return false;
0331a832 4541
bf29ee6c 4542 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4543 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4544 ixgbe_cache_ring_fdir(adapter);
4545 else
4546 ixgbe_cache_ring_rss(adapter);
8faa2a78 4547
bf29ee6c
AD		 4548 fcoe_rx_i = f->mask;
4549 fcoe_tx_i = f->mask;
0331a832 4550 }
bf29ee6c
AD		 4551 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4552 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4553 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4554 }
4555 return true;
0331a832
YZ		 4556}
4557
4558#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4559/**
4560 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4561 * @adapter: board private structure to initialize
4562 *
4563 * SR-IOV doesn't use any descriptor rings but changes the default if
4564 * no other mapping is used.
4565 *
4566 */
4567static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4568{
4a0b9ca0
PW		 4569 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4570 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4571 if (adapter->num_vfs)
4572 return true;
4573 else
4574 return false;
4575}
4576
bc97114d
PWJ		 4577/**
4578 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4579 * @adapter: board private structure to initialize
4580 *
4581 * Once we know the feature-set enabled for the device, we'll cache
4582 * the register offset the descriptor ring is assigned to.
4583 *
4584 * Note, the order the various feature calls is important. It must start with
4585 * the "most" features enabled at the same time, then trickle down to the
4586 * least amount of features turned on at once.
4587 **/
4588static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4589{
4590 /* start with default case */
4a0b9ca0
PW		 4591 adapter->rx_ring[0]->reg_idx = 0;
4592 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4593
1cdd1ec8
GR		 4594 if (ixgbe_cache_ring_sriov(adapter))
4595 return;
4596
e5b64635
JF		 4597#ifdef CONFIG_IXGBE_DCB
4598 if (ixgbe_cache_ring_dcb(adapter))
4599 return;
4600#endif
4601
0331a832
YZ		 4602#ifdef IXGBE_FCOE
4603 if (ixgbe_cache_ring_fcoe(adapter))
4604 return;
0331a832 4605#endif /* IXGBE_FCOE */
bc97114d 4606
c4cf55e5
PWJ		 4607 if (ixgbe_cache_ring_fdir(adapter))
4608 return;
4609
bc97114d
PWJ		 4610 if (ixgbe_cache_ring_rss(adapter))
4611 return;
021230d4
AV		 4612}
4613
9a799d71
AK		 4614/**
4615 * ixgbe_alloc_queues - Allocate memory for all rings
4616 * @adapter: board private structure to initialize
4617 *
4618 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4619 * number of queues at compile-time. The polling_netdev array is
4620 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4621 **/
2f90b865 4622static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4623{
e2ddeba9 4624 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4625
e2ddeba9
ED		 4626 if (nid < 0 || !node_online(nid))
4627 nid = first_online_node;
4628
4629 for (; tx < adapter->num_tx_queues; tx++) {
4630 struct ixgbe_ring *ring;
4631
4632 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4633 if (!ring)
e2ddeba9 4634 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4635 if (!ring)
e2ddeba9 4636 goto err_allocation;
4a0b9ca0 4637 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4638 ring->queue_index = tx;
4639 ring->numa_node = nid;
b6ec895e 4640 ring->dev = &adapter->pdev->dev;
fc77dc3c 4641 ring->netdev = adapter->netdev;
4a0b9ca0 4642
e2ddeba9 4643 adapter->tx_ring[tx] = ring;
021230d4 4644 }
b9804972 4645
e2ddeba9
ED		 4646 for (; rx < adapter->num_rx_queues; rx++) {
4647 struct ixgbe_ring *ring;
4a0b9ca0 4648
e2ddeba9 4649 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4650 if (!ring)
e2ddeba9 4651 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4652 if (!ring)
e2ddeba9
ED		 4653 goto err_allocation;
4654 ring->count = adapter->rx_ring_count;
4655 ring->queue_index = rx;
4656 ring->numa_node = nid;
b6ec895e 4657 ring->dev = &adapter->pdev->dev;
fc77dc3c 4658 ring->netdev = adapter->netdev;
4a0b9ca0 4659
e2ddeba9 4660 adapter->rx_ring[rx] = ring;
021230d4
AV		 4661 }
4662
4663 ixgbe_cache_ring_register(adapter);
4664
4665 return 0;
4666
e2ddeba9
ED		 4667err_allocation:
4668 while (tx)
4669 kfree(adapter->tx_ring[--tx]);
4670
4671 while (rx)
4672 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4673 return -ENOMEM;
4674}
4675
4676/**
4677 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4678 * @adapter: board private structure to initialize
4679 *
4680 * Attempt to configure the interrupts using the best available
4681 * capabilities of the hardware and the kernel.
4682 **/
feea6a57 4683static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4684{
8be0e467 4685 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4686 int err = 0;
4687 int vector, v_budget;
4688
4689 /*
4690 * It's easy to be greedy for MSI-X vectors, but it really
4691 * doesn't do us much good if we have a lot more vectors
4692 * than CPU's. So let's be conservative and only ask for
342bde1b 4693 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4694 */
4695 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4696 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4697
4698 /*
4699 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4700 * hw.mac->max_msix_vectors vectors. With features
4701 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4702 * descriptor queues supported by our device. Thus, we cap it off in
4703 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4704 */
8be0e467 4705 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4706
4707 /* A failure in MSI-X entry allocation isn't fatal, but it does
4708 * mean we disable MSI-X capabilities of the adapter. */
4709 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4710 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4711 if (adapter->msix_entries) {
4712 for (vector = 0; vector < v_budget; vector++)
4713 adapter->msix_entries[vector].entry = vector;
021230d4 4714
7a921c93 4715 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4716
7a921c93
AD		 4717 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4718 goto out;
4719 }
26d27844 4720
7a921c93
AD		 4721 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4722 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4723 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4724 e_err(probe,
03ecf91a 4725 "ATR is not supported while multiple "
45b9f509
AD		 4726 "queues are disabled. Disabling Flow Director\n");
4727 }
c4cf55e5 4728 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4729 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4730 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4731 ixgbe_disable_sriov(adapter);
4732
847f53ff
BH		 4733 err = ixgbe_set_num_queues(adapter);
4734 if (err)
4735 return err;
021230d4 4736
021230d4
AV		 4737 err = pci_enable_msi(adapter->pdev);
4738 if (!err) {
4739 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4740 } else {
849c4542
ET		 4741 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4742 "Unable to allocate MSI interrupt, "
4743 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4744 /* reset err */
4745 err = 0;
4746 }
4747
4748out:
021230d4
AV		 4749 return err;
4750}
4751
7a921c93
AD		 4752/**
4753 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4754 * @adapter: board private structure to initialize
4755 *
4756 * We allocate one q_vector per queue interrupt. If allocation fails we
4757 * return -ENOMEM.
4758 **/
4759static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4760{
4ff7fb12 4761 int v_idx, num_q_vectors;
7a921c93 4762 struct ixgbe_q_vector *q_vector;
7a921c93 4763
4ff7fb12 4764 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4765 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4766 else
7a921c93 4767 num_q_vectors = 1;
7a921c93 4768
4ff7fb12 4769 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4770 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4771 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4772 if (!q_vector)
4773 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4774 GFP_KERNEL);
7a921c93
AD		 4775 if (!q_vector)
4776 goto err_out;
4ff7fb12 4777
7a921c93 4778 q_vector->adapter = adapter;
4ff7fb12
AD		 4779 q_vector->v_idx = v_idx;
4780
207867f5
AD		 4781 /* Allocate the affinity_hint cpumask, configure the mask */
4782 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4783 goto err_out;
4784 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4785 netif_napi_add(adapter->netdev, &q_vector->napi,
4786 ixgbe_poll, 64);
4787 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4788 }
4789
4790 return 0;
4791
4792err_out:
4ff7fb12
AD		 4793 while (v_idx) {
4794 v_idx--;
4795 q_vector = adapter->q_vector[v_idx];
7a921c93 4796 netif_napi_del(&q_vector->napi);
207867f5 4797 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4798 kfree(q_vector);
4ff7fb12 4799 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4800 }
4801 return -ENOMEM;
4802}
4803
4804/**
4805 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4806 * @adapter: board private structure to initialize
4807 *
4808 * This function frees the memory allocated to the q_vectors. In addition if
4809 * NAPI is enabled it will delete any references to the NAPI struct prior
4810 * to freeing the q_vector.
4811 **/
4812static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4813{
207867f5 4814 int v_idx, num_q_vectors;
7a921c93 4815
91281fd3 4816 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4817 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4818 else
7a921c93 4819 num_q_vectors = 1;
7a921c93 4820
207867f5
AD		 4821 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4822 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4823 adapter->q_vector[v_idx] = NULL;
91281fd3 4824 netif_napi_del(&q_vector->napi);
207867f5 4825 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4826 kfree(q_vector);
4827 }
4828}
4829
7b25cdba 4830static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4831{
4832 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4833 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4834 pci_disable_msix(adapter->pdev);
4835 kfree(adapter->msix_entries);
4836 adapter->msix_entries = NULL;
4837 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4838 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4839 pci_disable_msi(adapter->pdev);
4840 }
021230d4
AV		 4841}
4842
4843/**
4844 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4845 * @adapter: board private structure to initialize
4846 *
4847 * We determine which interrupt scheme to use based on...
4848 * - Kernel support (MSI, MSI-X)
4849 * - which can be user-defined (via MODULE_PARAM)
4850 * - Hardware queue count (num_*_queues)
4851 * - defined by miscellaneous hardware support/features (RSS, etc.)
4852 **/
2f90b865 4853int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4854{
4855 int err;
4856
4857 /* Number of supported queues */
847f53ff
BH		 4858 err = ixgbe_set_num_queues(adapter);
4859 if (err)
4860 return err;
021230d4 4861
021230d4
AV		 4862 err = ixgbe_set_interrupt_capability(adapter);
4863 if (err) {
849c4542 4864 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4865 goto err_set_interrupt;
9a799d71
AK		 4866 }
4867
7a921c93
AD		 4868 err = ixgbe_alloc_q_vectors(adapter);
4869 if (err) {
849c4542 4870 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4871 goto err_alloc_q_vectors;
4872 }
4873
4874 err = ixgbe_alloc_queues(adapter);
4875 if (err) {
849c4542 4876 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4877 goto err_alloc_queues;
4878 }
4879
849c4542 4880 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4881 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4882 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4883
4884 set_bit(__IXGBE_DOWN, &adapter->state);
4885
9a799d71 4886 return 0;
021230d4 4887
7a921c93
AD		 4888err_alloc_queues:
4889 ixgbe_free_q_vectors(adapter);
4890err_alloc_q_vectors:
4891 ixgbe_reset_interrupt_capability(adapter);
021230d4 4892err_set_interrupt:
7a921c93
AD		 4893 return err;
4894}
4895
4896/**
4897 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4898 * @adapter: board private structure to clear interrupt scheme on
4899 *
4900 * We go through and clear interrupt specific resources and reset the structure
4901 * to pre-load conditions
4902 **/
4903void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4904{
4a0b9ca0
PW		 4905 int i;
4906
4907 for (i = 0; i < adapter->num_tx_queues; i++) {
4908 kfree(adapter->tx_ring[i]);
4909 adapter->tx_ring[i] = NULL;
4910 }
4911 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4912 struct ixgbe_ring *ring = adapter->rx_ring[i];
4913
4914 /* ixgbe_get_stats64() might access this ring, we must wait
4915 * a grace period before freeing it.
4916 */
bcec8b65 4917 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4918 adapter->rx_ring[i] = NULL;
4919 }
7a921c93 4920
b8eb3a10
DS		 4921 adapter->num_tx_queues = 0;
4922 adapter->num_rx_queues = 0;
4923
7a921c93
AD		 4924 ixgbe_free_q_vectors(adapter);
4925 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4926}
4927
4928/**
4929 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4930 * @adapter: board private structure to initialize
4931 *
4932 * ixgbe_sw_init initializes the Adapter private data structure.
4933 * Fields are initialized based on PCI device information and
4934 * OS network device settings (MTU size).
4935 **/
4936static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4937{
4938 struct ixgbe_hw *hw = &adapter->hw;
4939 struct pci_dev *pdev = adapter->pdev;
021230d4 4940 unsigned int rss;
7a6b6f51 4941#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4942 int j;
4943 struct tc_configuration *tc;
4944#endif
021230d4 4945
c44ade9e
JB		 4946 /* PCI config space info */
4947
4948 hw->vendor_id = pdev->vendor;
4949 hw->device_id = pdev->device;
4950 hw->revision_id = pdev->revision;
4951 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4952 hw->subsystem_device_id = pdev->subsystem_device;
4953
021230d4
AV		 4954 /* Set capability flags */
4955 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4956 adapter->ring_feature[RING_F_RSS].indices = rss;
4957 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4958 switch (hw->mac.type) {
4959 case ixgbe_mac_82598EB:
bf069c97
DS		 4960 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4961 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4962 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 4963 break;
b93a2226 4964 case ixgbe_mac_X540:
4f51bf70
JK		 4965 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4966 case ixgbe_mac_82599EB:
e8e26350 4967 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4968 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4969 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4970 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4971 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4972 /* Flow Director hash filters enabled */
4973 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4974 adapter->atr_sample_rate = 20;
c4cf55e5 4975 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4976 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4977 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4978#ifdef IXGBE_FCOE
0d551589
YZ		 4979 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4980 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4981 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4982#ifdef CONFIG_IXGBE_DCB
6ee16520 4983 /* Default traffic class to use for FCoE */
56075a98 4984 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4985#endif
eacd73f7 4986#endif /* IXGBE_FCOE */
bd508178
AD		 4987 break;
4988 default:
4989 break;
f8212f97 4990 }
2f90b865 4991
1fc5f038
AD		 4992 /* n-tuple support exists, always init our spinlock */
4993 spin_lock_init(&adapter->fdir_perfect_lock);
4994
7a6b6f51 4995#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4996 switch (hw->mac.type) {
4997 case ixgbe_mac_X540:
4998 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4999 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5000 break;
5001 default:
5002 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5003 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5004 break;
5005 }
5006
2f90b865
AD		 5007 /* Configure DCB traffic classes */
5008 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5009 tc = &adapter->dcb_cfg.tc_config[j];
5010 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5011 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5012 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5013 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5014 tc->dcb_pfc = pfc_disabled;
5015 }
4de2a022
JF		 5016
5017 /* Initialize default user to priority mapping, UPx->TC0 */
5018 tc = &adapter->dcb_cfg.tc_config[0];
5019 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5020 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5021
2f90b865
AD		 5022 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5023 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5024 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5025 adapter->dcb_set_bitmap = 0x00;
3032309b 5026 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5027 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5028 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5029
5030#endif
9a799d71
AK		 5031
5032 /* default flow control settings */
cd7664f6 5033 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5034 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5035#ifdef CONFIG_DCB
5036 adapter->last_lfc_mode = hw->fc.current_mode;
5037#endif
9da712d2 5038 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5039 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5040 hw->fc.send_xon = true;
71fd570b 5041 hw->fc.disable_fc_autoneg = false;
9a799d71 5042
30efa5a3 5043 /* enable itr by default in dynamic mode */
f7554a2b 5044 adapter->rx_itr_setting = 1;
f7554a2b 5045 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5046
5047 /* set defaults for eitr in MegaBytes */
5048 adapter->eitr_low = 10;
5049 adapter->eitr_high = 20;
5050
5051 /* set default ring sizes */
5052 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5053 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5054
bd198058 5055 /* set default work limits */
59224555 5056 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5057
9a799d71 5058 /* initialize eeprom parameters */
c44ade9e 5059 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5060 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5061 return -EIO;
5062 }
5063
021230d4 5064 /* enable rx csum by default */
9a799d71
AK		 5065 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5066
1a6c14a2
JB		 5067 /* get assigned NUMA node */
5068 adapter->node = dev_to_node(&pdev->dev);
5069
9a799d71
AK		 5070 set_bit(__IXGBE_DOWN, &adapter->state);
5071
5072 return 0;
5073}
5074
5075/**
5076 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5077 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5078 *
5079 * Return 0 on success, negative on failure
5080 **/
b6ec895e 5081int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5082{
b6ec895e 5083 struct device *dev = tx_ring->dev;
9a799d71
AK		 5084 int size;
5085
3a581073 5086 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5087 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5088 if (!tx_ring->tx_buffer_info)
89bf67f1 5089 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5090 if (!tx_ring->tx_buffer_info)
5091 goto err;
9a799d71
AK		 5092
5093 /* round up to nearest 4K */
12207e49 5094 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5095 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5096
b6ec895e 5097 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5098 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5099 if (!tx_ring->desc)
5100 goto err;
9a799d71 5101
3a581073
JB		 5102 tx_ring->next_to_use = 0;
5103 tx_ring->next_to_clean = 0;
9a799d71 5104 return 0;
e01c31a5
JB		 5105
5106err:
5107 vfree(tx_ring->tx_buffer_info);
5108 tx_ring->tx_buffer_info = NULL;
b6ec895e 5109 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5110 return -ENOMEM;
9a799d71
AK		 5111}
5112
69888674
AD		 5113/**
5114 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5115 * @adapter: board private structure
5116 *
5117 * If this function returns with an error, then it's possible one or
5118 * more of the rings is populated (while the rest are not). It is the
5119 * callers duty to clean those orphaned rings.
5120 *
5121 * Return 0 on success, negative on failure
5122 **/
5123static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5124{
5125 int i, err = 0;
5126
5127 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5128 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5129 if (!err)
5130 continue;
396e799c 5131 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5132 break;
5133 }
5134
5135 return err;
5136}
5137
9a799d71
AK		 5138/**
5139 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5140 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5141 *
5142 * Returns 0 on success, negative on failure
5143 **/
b6ec895e 5144int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5145{
b6ec895e 5146 struct device *dev = rx_ring->dev;
021230d4 5147 int size;
9a799d71 5148
3a581073 5149 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5150 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5151 if (!rx_ring->rx_buffer_info)
89bf67f1 5152 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5153 if (!rx_ring->rx_buffer_info)
5154 goto err;
9a799d71 5155
9a799d71 5156 /* Round up to nearest 4K */
3a581073
JB		 5157 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5158 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5159
b6ec895e 5160 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5161 &rx_ring->dma, GFP_KERNEL);
9a799d71 5162
b6ec895e
AD		 5163 if (!rx_ring->desc)
5164 goto err;
9a799d71 5165
3a581073
JB		 5166 rx_ring->next_to_clean = 0;
5167 rx_ring->next_to_use = 0;
9a799d71
AK		 5168
5169 return 0;
b6ec895e
AD		 5170err:
5171 vfree(rx_ring->rx_buffer_info);
5172 rx_ring->rx_buffer_info = NULL;
5173 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5174 return -ENOMEM;
9a799d71
AK		 5175}
5176
69888674
AD		 5177/**
5178 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5179 * @adapter: board private structure
5180 *
5181 * If this function returns with an error, then it's possible one or
5182 * more of the rings is populated (while the rest are not). It is the
5183 * callers duty to clean those orphaned rings.
5184 *
5185 * Return 0 on success, negative on failure
5186 **/
69888674
AD		 5187static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5188{
5189 int i, err = 0;
5190
5191 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5192 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5193 if (!err)
5194 continue;
396e799c 5195 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5196 break;
5197 }
5198
5199 return err;
5200}
5201
9a799d71
AK		 5202/**
5203 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5204 * @tx_ring: Tx descriptor ring for a specific queue
5205 *
5206 * Free all transmit software resources
5207 **/
b6ec895e 5208void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5209{
b6ec895e 5210 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5211
5212 vfree(tx_ring->tx_buffer_info);
5213 tx_ring->tx_buffer_info = NULL;
5214
b6ec895e
AD		 5215 /* if not set, then don't free */
5216 if (!tx_ring->desc)
5217 return;
5218
5219 dma_free_coherent(tx_ring->dev, tx_ring->size,
5220 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5221
5222 tx_ring->desc = NULL;
5223}
5224
5225/**
5226 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5227 * @adapter: board private structure
5228 *
5229 * Free all transmit software resources
5230 **/
5231static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5232{
5233 int i;
5234
5235 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5236 if (adapter->tx_ring[i]->desc)
b6ec895e 5237 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5238}
5239
5240/**
b4617240 5241 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5242 * @rx_ring: ring to clean the resources from
5243 *
5244 * Free all receive software resources
5245 **/
b6ec895e 5246void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5247{
b6ec895e 5248 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5249
5250 vfree(rx_ring->rx_buffer_info);
5251 rx_ring->rx_buffer_info = NULL;
5252
b6ec895e
AD		 5253 /* if not set, then don't free */
5254 if (!rx_ring->desc)
5255 return;
5256
5257 dma_free_coherent(rx_ring->dev, rx_ring->size,
5258 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5259
5260 rx_ring->desc = NULL;
5261}
5262
5263/**
5264 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5265 * @adapter: board private structure
5266 *
5267 * Free all receive software resources
5268 **/
5269static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5270{
5271 int i;
5272
5273 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5274 if (adapter->rx_ring[i]->desc)
b6ec895e 5275 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5276}
5277
9a799d71
AK		 5278/**
5279 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5280 * @netdev: network interface device structure
5281 * @new_mtu: new value for maximum frame size
5282 *
5283 * Returns 0 on success, negative on failure
5284 **/
5285static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5286{
5287 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5288 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5289 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5290
42c783c5 5291 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5292 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5293 hw->mac.type != ixgbe_mac_X540) {
5294 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5295 return -EINVAL;
5296 } else {
5297 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5298 return -EINVAL;
5299 }
9a799d71 5300
396e799c 5301 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5302 /* must set new MTU before calling down or up */
9a799d71
AK		 5303 netdev->mtu = new_mtu;
5304
d4f80882
AV		 5305 if (netif_running(netdev))
5306 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5307
5308 return 0;
5309}
5310
5311/**
5312 * ixgbe_open - Called when a network interface is made active
5313 * @netdev: network interface device structure
5314 *
5315 * Returns 0 on success, negative value on failure
5316 *
5317 * The open entry point is called when a network interface is made
5318 * active by the system (IFF_UP). At this point all resources needed
5319 * for transmit and receive operations are allocated, the interrupt
5320 * handler is registered with the OS, the watchdog timer is started,
5321 * and the stack is notified that the interface is ready.
5322 **/
5323static int ixgbe_open(struct net_device *netdev)
5324{
5325 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5326 int err;
4bebfaa5
AK		 5327
5328 /* disallow open during test */
5329 if (test_bit(__IXGBE_TESTING, &adapter->state))
5330 return -EBUSY;
9a799d71 5331
54386467
JB		 5332 netif_carrier_off(netdev);
5333
9a799d71
AK		 5334 /* allocate transmit descriptors */
5335 err = ixgbe_setup_all_tx_resources(adapter);
5336 if (err)
5337 goto err_setup_tx;
5338
9a799d71
AK		 5339 /* allocate receive descriptors */
5340 err = ixgbe_setup_all_rx_resources(adapter);
5341 if (err)
5342 goto err_setup_rx;
5343
5344 ixgbe_configure(adapter);
5345
021230d4 5346 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5347 if (err)
5348 goto err_req_irq;
5349
c7ccde0f 5350 ixgbe_up_complete(adapter);
9a799d71
AK		 5351
5352 return 0;
5353
9a799d71 5354err_req_irq:
9a799d71 5355err_setup_rx:
a20a1199 5356 ixgbe_free_all_rx_resources(adapter);
9a799d71 5357err_setup_tx:
a20a1199 5358 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5359 ixgbe_reset(adapter);
5360
5361 return err;
5362}
5363
5364/**
5365 * ixgbe_close - Disables a network interface
5366 * @netdev: network interface device structure
5367 *
5368 * Returns 0, this is not allowed to fail
5369 *
5370 * The close entry point is called when an interface is de-activated
5371 * by the OS. The hardware is still under the drivers control, but
5372 * needs to be disabled. A global MAC reset is issued to stop the
5373 * hardware, and all transmit and receive resources are freed.
5374 **/
5375static int ixgbe_close(struct net_device *netdev)
5376{
5377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5378
5379 ixgbe_down(adapter);
5380 ixgbe_free_irq(adapter);
5381
e4911d57
AD		 5382 ixgbe_fdir_filter_exit(adapter);
5383
9a799d71
AK		 5384 ixgbe_free_all_tx_resources(adapter);
5385 ixgbe_free_all_rx_resources(adapter);
5386
5eba3699 5387 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5388
5389 return 0;
5390}
5391
b3c8b4ba
AD		 5392#ifdef CONFIG_PM
5393static int ixgbe_resume(struct pci_dev *pdev)
5394{
c60fbb00
AD		 5395 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5396 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5397 u32 err;
5398
5399 pci_set_power_state(pdev, PCI_D0);
5400 pci_restore_state(pdev);
656ab817
DS		 5401 /*
5402 * pci_restore_state clears dev->state_saved so call
5403 * pci_save_state to restore it.
5404 */
5405 pci_save_state(pdev);
9ce77666 5406
5407 err = pci_enable_device_mem(pdev);
b3c8b4ba 5408 if (err) {
849c4542 5409 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5410 return err;
5411 }
5412 pci_set_master(pdev);
5413
dd4d8ca6 5414 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5415
5416 err = ixgbe_init_interrupt_scheme(adapter);
5417 if (err) {
849c4542 5418 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5419 return err;
5420 }
5421
b3c8b4ba
AD		 5422 ixgbe_reset(adapter);
5423
495dce12
WJP		 5424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5425
b3c8b4ba 5426 if (netif_running(netdev)) {
c60fbb00 5427 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5428 if (err)
5429 return err;
5430 }
5431
5432 netif_device_attach(netdev);
5433
5434 return 0;
5435}
b3c8b4ba 5436#endif /* CONFIG_PM */
9d8d05ae
RW		 5437
5438static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5439{
c60fbb00
AD		 5440 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5441 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5442 struct ixgbe_hw *hw = &adapter->hw;
5443 u32 ctrl, fctrl;
5444 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5445#ifdef CONFIG_PM
5446 int retval = 0;
5447#endif
5448
5449 netif_device_detach(netdev);
5450
5451 if (netif_running(netdev)) {
5452 ixgbe_down(adapter);
5453 ixgbe_free_irq(adapter);
5454 ixgbe_free_all_tx_resources(adapter);
5455 ixgbe_free_all_rx_resources(adapter);
5456 }
b3c8b4ba 5457
5f5ae6fc 5458 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5459#ifdef CONFIG_DCB
5460 kfree(adapter->ixgbe_ieee_pfc);
5461 kfree(adapter->ixgbe_ieee_ets);
5462#endif
5f5ae6fc 5463
b3c8b4ba
AD		 5464#ifdef CONFIG_PM
5465 retval = pci_save_state(pdev);
5466 if (retval)
5467 return retval;
4df10466 5468
b3c8b4ba 5469#endif
e8e26350
PW		 5470 if (wufc) {
5471 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5472
e8e26350
PW		 5473 /* turn on all-multi mode if wake on multicast is enabled */
5474 if (wufc & IXGBE_WUFC_MC) {
5475 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5476 fctrl |= IXGBE_FCTRL_MPE;
5477 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5478 }
5479
5480 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5481 ctrl |= IXGBE_CTRL_GIO_DIS;
5482 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5483
5484 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5485 } else {
5486 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5487 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5488 }
5489
bd508178
AD		 5490 switch (hw->mac.type) {
5491 case ixgbe_mac_82598EB:
dd4d8ca6 5492 pci_wake_from_d3(pdev, false);
bd508178
AD		 5493 break;
5494 case ixgbe_mac_82599EB:
b93a2226 5495 case ixgbe_mac_X540:
bd508178
AD		 5496 pci_wake_from_d3(pdev, !!wufc);
5497 break;
5498 default:
5499 break;
5500 }
b3c8b4ba 5501
9d8d05ae
RW		 5502 *enable_wake = !!wufc;
5503
b3c8b4ba
AD		 5504 ixgbe_release_hw_control(adapter);
5505
5506 pci_disable_device(pdev);
5507
9d8d05ae
RW		 5508 return 0;
5509}
5510
5511#ifdef CONFIG_PM
5512static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5513{
5514 int retval;
5515 bool wake;
5516
5517 retval = __ixgbe_shutdown(pdev, &wake);
5518 if (retval)
5519 return retval;
5520
5521 if (wake) {
5522 pci_prepare_to_sleep(pdev);
5523 } else {
5524 pci_wake_from_d3(pdev, false);
5525 pci_set_power_state(pdev, PCI_D3hot);
5526 }
b3c8b4ba
AD		 5527
5528 return 0;
5529}
9d8d05ae 5530#endif /* CONFIG_PM */
b3c8b4ba
AD		 5531
5532static void ixgbe_shutdown(struct pci_dev *pdev)
5533{
9d8d05ae
RW		 5534 bool wake;
5535
5536 __ixgbe_shutdown(pdev, &wake);
5537
5538 if (system_state == SYSTEM_POWER_OFF) {
5539 pci_wake_from_d3(pdev, wake);
5540 pci_set_power_state(pdev, PCI_D3hot);
5541 }
b3c8b4ba
AD		 5542}
5543
9a799d71
AK		 5544/**
5545 * ixgbe_update_stats - Update the board statistics counters.
5546 * @adapter: board private structure
5547 **/
5548void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5549{
2d86f139 5550 struct net_device *netdev = adapter->netdev;
9a799d71 5551 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5552 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5553 u64 total_mpc = 0;
5554 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5555 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5556 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5557 u64 bytes = 0, packets = 0;
7b859ebc
AH		 5558#ifdef IXGBE_FCOE
5559 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5560 unsigned int cpu;
5561 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5562#endif /* IXGBE_FCOE */
9a799d71 5563
d08935c2
DS		 5564 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5565 test_bit(__IXGBE_RESETTING, &adapter->state))
5566 return;
5567
94b982b2 5568 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5569 u64 rsc_count = 0;
94b982b2 5570 u64 rsc_flush = 0;
d51019a4
PW		 5571 for (i = 0; i < 16; i++)
5572 adapter->hw_rx_no_dma_resources +=
7ca647bd 5573 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5574 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5575 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5576 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5577 }
5578 adapter->rsc_total_count = rsc_count;
5579 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5580 }
5581
5b7da515
AD		 5582 for (i = 0; i < adapter->num_rx_queues; i++) {
5583 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5584 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5585 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5586 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5587 bytes += rx_ring->stats.bytes;
5588 packets += rx_ring->stats.packets;
5589 }
5590 adapter->non_eop_descs = non_eop_descs;
5591 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5592 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5593 netdev->stats.rx_bytes = bytes;
5594 netdev->stats.rx_packets = packets;
5595
5596 bytes = 0;
5597 packets = 0;
7ca3bc58 5598 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5599 for (i = 0; i < adapter->num_tx_queues; i++) {
5600 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5601 restart_queue += tx_ring->tx_stats.restart_queue;
5602 tx_busy += tx_ring->tx_stats.tx_busy;
5603 bytes += tx_ring->stats.bytes;
5604 packets += tx_ring->stats.packets;
5605 }
eb985f09 5606 adapter->restart_queue = restart_queue;
5b7da515
AD		 5607 adapter->tx_busy = tx_busy;
5608 netdev->stats.tx_bytes = bytes;
5609 netdev->stats.tx_packets = packets;
7ca3bc58 5610
7ca647bd 5611 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5612
5613 /* 8 register reads */
6f11eef7
AV		 5614 for (i = 0; i < 8; i++) {
5615 /* for packet buffers not used, the register should read 0 */
5616 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5617 missed_rx += mpc;
7ca647bd
JP		 5618 hwstats->mpc[i] += mpc;
5619 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5620 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5621 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5622 switch (hw->mac.type) {
5623 case ixgbe_mac_82598EB:
1a70db4b
ET		 5624 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5625 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5626 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5627 hwstats->pxonrxc[i] +=
5628 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5629 break;
5630 case ixgbe_mac_82599EB:
b93a2226 5631 case ixgbe_mac_X540:
bd508178
AD		 5632 hwstats->pxonrxc[i] +=
5633 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5634 break;
5635 default:
5636 break;
e8e26350 5637 }
6f11eef7 5638 }
1a70db4b
ET		 5639
5640 /*16 register reads */
5641 for (i = 0; i < 16; i++) {
5642 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5643 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5644 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5645 (hw->mac.type == ixgbe_mac_X540)) {
5646 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5647 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5648 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5649 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5650 }
5651 }
5652
7ca647bd 5653 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5654 /* work around hardware counting issue */
7ca647bd 5655 hwstats->gprc -= missed_rx;
6f11eef7 5656
c84d324c
JF		 5657 ixgbe_update_xoff_received(adapter);
5658
6f11eef7 5659 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5660 switch (hw->mac.type) {
5661 case ixgbe_mac_82598EB:
5662 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5663 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5664 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5665 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5666 break;
b93a2226 5667 case ixgbe_mac_X540:
58f6bcf9
ET		 5668 /* OS2BMC stats are X540 only*/
5669 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5670 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5671 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5672 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5673 case ixgbe_mac_82599EB:
7ca647bd 5674 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5675 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5676 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5677 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5678 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5679 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5680 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5681 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5682 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5683#ifdef IXGBE_FCOE
7ca647bd
JP		 5684 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5685 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5686 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5687 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5688 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5689 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5690 /* Add up per cpu counters for total ddp aloc fail */
5691 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5692 for_each_possible_cpu(cpu) {
5693 fcoe_noddp_counts_sum +=
5694 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5695 fcoe_noddp_ext_buff_counts_sum +=
5696 *per_cpu_ptr(fcoe->
5697 pcpu_noddp_ext_buff, cpu);
5698 }
5699 }
5700 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5701 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5702#endif /* IXGBE_FCOE */
bd508178
AD		 5703 break;
5704 default:
5705 break;
e8e26350 5706 }
9a799d71 5707 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5708 hwstats->bprc += bprc;
5709 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5710 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5711 hwstats->mprc -= bprc;
5712 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5713 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5714 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5715 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5716 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5717 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5718 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5719 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5720 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5721 hwstats->lxontxc += lxon;
6f11eef7 5722 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5723 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5724 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5725 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5726 /*
5727 * 82598 errata - tx of flow control packets is included in tx counters
5728 */
5729 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5730 hwstats->gptc -= xon_off_tot;
5731 hwstats->mptc -= xon_off_tot;
5732 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5733 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5734 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5735 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5736 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5737 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5738 hwstats->ptc64 -= xon_off_tot;
5739 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5740 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5741 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5742 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5743 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5744 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5745
5746 /* Fill out the OS statistics structure */
7ca647bd 5747 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5748
5749 /* Rx Errors */
7ca647bd 5750 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5751 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5752 netdev->stats.rx_length_errors = hwstats->rlec;
5753 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5754 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5755}
5756
5757/**
d034acf1
AD		 5758 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5759 * @adapter - pointer to the device adapter structure
9a799d71 5760 **/
d034acf1 5761static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5762{
cf8280ee 5763 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5764 int i;
cf8280ee 5765
d034acf1
AD		 5766 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5767 return;
5768
5769 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5770
d034acf1 5771 /* if interface is down do nothing */
fe49f04a 5772 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5773 return;
5774
5775 /* do nothing if we are not using signature filters */
5776 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5777 return;
5778
5779 adapter->fdir_overflow++;
5780
93c52dd0
AD		 5781 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5782 for (i = 0; i < adapter->num_tx_queues; i++)
5783 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5784 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5785 /* re-enable flow director interrupts */
5786 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5787 } else {
5788 e_err(probe, "failed to finish FDIR re-initialization, "
5789 "ignored adding FDIR ATR filters\n");
5790 }
93c52dd0
AD		 5791}
5792
5793/**
5794 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5795 * @adapter - pointer to the device adapter structure
5796 *
5797 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5798 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5799 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5800 * determine if a hang has occurred.
93c52dd0
AD		 5801 */
5802static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5803{
cf8280ee 5804 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5805 u64 eics = 0;
5806 int i;
cf8280ee 5807
93c52dd0
AD		 5808 /* If we're down or resetting, just bail */
5809 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5810 test_bit(__IXGBE_RESETTING, &adapter->state))
5811 return;
22d5a71b 5812
93c52dd0
AD		 5813 /* Force detection of hung controller */
5814 if (netif_carrier_ok(adapter->netdev)) {
5815 for (i = 0; i < adapter->num_tx_queues; i++)
5816 set_check_for_tx_hang(adapter->tx_ring[i]);
5817 }
22d5a71b 5818
fe49f04a
AD		 5819 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5820 /*
5821 * for legacy and MSI interrupts don't set any bits
5822 * that are enabled for EIAM, because this operation
5823 * would set *both* EIMS and EICS for any bit in EIAM
5824 */
5825 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5826 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5827 } else {
5828 /* get one bit for every active tx/rx interrupt vector */
5829 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5830 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5831 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5832 eics |= ((u64)1 << i);
5833 }
cf8280ee 5834 }
9a799d71 5835
93c52dd0 5836 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5837 ixgbe_irq_rearm_queues(adapter, eics);
5838
cf8280ee
JB		 5839}
5840
e8e26350 5841/**
93c52dd0
AD		 5842 * ixgbe_watchdog_update_link - update the link status
5843 * @adapter - pointer to the device adapter structure
5844 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5845 **/
93c52dd0 5846static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5847{
e8e26350 5848 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5849 u32 link_speed = adapter->link_speed;
5850 bool link_up = adapter->link_up;
c4cf55e5 5851 int i;
e8e26350 5852
93c52dd0
AD		 5853 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5854 return;
5855
5856 if (hw->mac.ops.check_link) {
5857 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5858 } else {
93c52dd0
AD		 5859 /* always assume link is up, if no check link function */
5860 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5861 link_up = true;
c4cf55e5 5862 }
93c52dd0
AD		 5863 if (link_up) {
5864 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5865 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5866 hw->mac.ops.fc_enable(hw, i);
5867 } else {
5868 hw->mac.ops.fc_enable(hw, 0);
5869 }
5870 }
5871
5872 if (link_up ||
5873 time_after(jiffies, (adapter->link_check_timeout +
5874 IXGBE_TRY_LINK_TIMEOUT))) {
5875 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5876 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5877 IXGBE_WRITE_FLUSH(hw);
5878 }
5879
5880 adapter->link_up = link_up;
5881 adapter->link_speed = link_speed;
e8e26350
PW		 5882}
5883
5884/**
93c52dd0
AD		 5885 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5886 * print link up message
5887 * @adapter - pointer to the device adapter structure
e8e26350 5888 **/
93c52dd0 5889static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5890{
93c52dd0 5891 struct net_device *netdev = adapter->netdev;
e8e26350 5892 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5893 u32 link_speed = adapter->link_speed;
5894 bool flow_rx, flow_tx;
e8e26350 5895
93c52dd0
AD		 5896 /* only continue if link was previously down */
5897 if (netif_carrier_ok(netdev))
a985b6c3 5898 return;
63d6e1d8 5899
93c52dd0 5900 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5901
93c52dd0
AD		 5902 switch (hw->mac.type) {
5903 case ixgbe_mac_82598EB: {
5904 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5905 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5906 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5907 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5908 }
5909 break;
5910 case ixgbe_mac_X540:
5911 case ixgbe_mac_82599EB: {
5912 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5913 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5914 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5915 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5916 }
5917 break;
5918 default:
5919 flow_tx = false;
5920 flow_rx = false;
5921 break;
e8e26350 5922 }
93c52dd0
AD		 5923 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5924 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5925 "10 Gbps" :
5926 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5927 "1 Gbps" :
5928 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5929 "100 Mbps" :
5930 "unknown speed"))),
5931 ((flow_rx && flow_tx) ? "RX/TX" :
5932 (flow_rx ? "RX" :
5933 (flow_tx ? "TX" : "None"))));
e8e26350 5934
93c52dd0 5935 netif_carrier_on(netdev);
93c52dd0 5936 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5937}
5938
c4cf55e5 5939/**
93c52dd0
AD		 5940 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5941 * print link down message
5942 * @adapter - pointer to the adapter structure
c4cf55e5 5943 **/
93c52dd0 5944static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5945{
cf8280ee 5946 struct net_device *netdev = adapter->netdev;
c4cf55e5 5947 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5948
93c52dd0
AD		 5949 adapter->link_up = false;
5950 adapter->link_speed = 0;
cf8280ee 5951
93c52dd0
AD		 5952 /* only continue if link was up previously */
5953 if (!netif_carrier_ok(netdev))
5954 return;
264857b8 5955
93c52dd0
AD		 5956 /* poll for SFP+ cable when link is down */
5957 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5958 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5959
93c52dd0
AD		 5960 e_info(drv, "NIC Link is Down\n");
5961 netif_carrier_off(netdev);
5962}
e8e26350 5963
93c52dd0
AD		 5964/**
5965 * ixgbe_watchdog_flush_tx - flush queues on link down
5966 * @adapter - pointer to the device adapter structure
5967 **/
5968static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5969{
c4cf55e5 5970 int i;
93c52dd0 5971 int some_tx_pending = 0;
c4cf55e5 5972
93c52dd0 5973 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5974 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5975 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5976 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5977 some_tx_pending = 1;
5978 break;
5979 }
5980 }
5981
5982 if (some_tx_pending) {
5983 /* We've lost link, so the controller stops DMA,
5984 * but we've got queued Tx work that's never going
5985 * to get done, so reset controller to flush Tx.
5986 * (Do the reset outside of interrupt context).
5987 */
c83c6cbd 5988 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5989 }
c4cf55e5 5990 }
c4cf55e5
PWJ		 5991}
5992
a985b6c3
GR		 5993static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5994{
5995 u32 ssvpc;
5996
5997 /* Do not perform spoof check for 82598 */
5998 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5999 return;
6000
6001 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6002
6003 /*
6004 * ssvpc register is cleared on read, if zero then no
6005 * spoofed packets in the last interval.
6006 */
6007 if (!ssvpc)
6008 return;
6009
6010 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6011}
6012
93c52dd0
AD		 6013/**
6014 * ixgbe_watchdog_subtask - check and bring link up
6015 * @adapter - pointer to the device adapter structure
6016 **/
6017static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6018{
6019 /* if interface is down do nothing */
7edebf9a
ET		 6020 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6021 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6022 return;
6023
6024 ixgbe_watchdog_update_link(adapter);
6025
6026 if (adapter->link_up)
6027 ixgbe_watchdog_link_is_up(adapter);
6028 else
6029 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6030
a985b6c3 6031 ixgbe_spoof_check(adapter);
9a799d71 6032 ixgbe_update_stats(adapter);
93c52dd0
AD		 6033
6034 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6035}
10eec955 6036
cf8280ee 6037/**
7086400d
AD		 6038 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6039 * @adapter - the ixgbe adapter structure
cf8280ee 6040 **/
7086400d 6041static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6042{
cf8280ee 6043 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6044 s32 err;
cf8280ee 6045
7086400d
AD		 6046 /* not searching for SFP so there is nothing to do here */
6047 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6048 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6049 return;
10eec955 6050
7086400d
AD		 6051 /* someone else is in init, wait until next service event */
6052 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6053 return;
cf8280ee 6054
7086400d
AD		 6055 err = hw->phy.ops.identify_sfp(hw);
6056 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6057 goto sfp_out;
264857b8 6058
7086400d
AD		 6059 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6060 /* If no cable is present, then we need to reset
6061 * the next time we find a good cable. */
6062 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6063 }
9a799d71 6064
7086400d
AD		 6065 /* exit on error */
6066 if (err)
6067 goto sfp_out;
e8e26350 6068
7086400d
AD		 6069 /* exit if reset not needed */
6070 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6071 goto sfp_out;
9a799d71 6072
7086400d 6073 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6074
7086400d
AD		 6075 /*
6076 * A module may be identified correctly, but the EEPROM may not have
6077 * support for that module. setup_sfp() will fail in that case, so
6078 * we should not allow that module to load.
6079 */
6080 if (hw->mac.type == ixgbe_mac_82598EB)
6081 err = hw->phy.ops.reset(hw);
6082 else
6083 err = hw->mac.ops.setup_sfp(hw);
6084
6085 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6086 goto sfp_out;
6087
6088 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6089 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6090
6091sfp_out:
6092 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6093
6094 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6095 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6096 e_dev_err("failed to initialize because an unsupported "
6097 "SFP+ module type was detected.\n");
6098 e_dev_err("Reload the driver after installing a "
6099 "supported module.\n");
6100 unregister_netdev(adapter->netdev);
bc59fcda 6101 }
7086400d 6102}
bc59fcda 6103
7086400d
AD		 6104/**
6105 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6106 * @adapter - the ixgbe adapter structure
6107 **/
6108static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6109{
6110 struct ixgbe_hw *hw = &adapter->hw;
6111 u32 autoneg;
6112 bool negotiation;
6113
6114 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6115 return;
6116
6117 /* someone else is in init, wait until next service event */
6118 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6119 return;
6120
6121 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6122
6123 autoneg = hw->phy.autoneg_advertised;
6124 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6125 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6126 if (hw->mac.ops.setup_link)
6127 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6128
6129 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6130 adapter->link_check_timeout = jiffies;
6131 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6132}
6133
83c61fa9
GR		 6134#ifdef CONFIG_PCI_IOV
6135static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6136{
6137 int vf;
6138 struct ixgbe_hw *hw = &adapter->hw;
6139 struct net_device *netdev = adapter->netdev;
6140 u32 gpc;
6141 u32 ciaa, ciad;
6142
6143 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6144 if (gpc) /* If incrementing then no need for the check below */
6145 return;
6146 /*
6147 * Check to see if a bad DMA write target from an errant or
6148 * malicious VF has caused a PCIe error. If so then we can
6149 * issue a VFLR to the offending VF(s) and then resume without
6150 * requesting a full slot reset.
6151 */
6152
6153 for (vf = 0; vf < adapter->num_vfs; vf++) {
6154 ciaa = (vf << 16) | 0x80000000;
6155 /* 32 bit read so align, we really want status at offset 6 */
6156 ciaa |= PCI_COMMAND;
6157 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6158 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6159 ciaa &= 0x7FFFFFFF;
6160 /* disable debug mode asap after reading data */
6161 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6162 /* Get the upper 16 bits which will be the PCI status reg */
6163 ciad >>= 16;
6164 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6165 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6166 /* Issue VFLR */
6167 ciaa = (vf << 16) | 0x80000000;
6168 ciaa |= 0xA8;
6169 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6170 ciad = 0x00008000; /* VFLR */
6171 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6172 ciaa &= 0x7FFFFFFF;
6173 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6174 }
6175 }
6176}
6177
6178#endif
7086400d
AD		 6179/**
6180 * ixgbe_service_timer - Timer Call-back
6181 * @data: pointer to adapter cast into an unsigned long
6182 **/
6183static void ixgbe_service_timer(unsigned long data)
6184{
6185 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6186 unsigned long next_event_offset;
83c61fa9 6187 bool ready = true;
7086400d 6188
83c61fa9
GR		 6189#ifdef CONFIG_PCI_IOV
6190 ready = false;
6191
6192 /*
6193 * don't bother with SR-IOV VF DMA hang check if there are
6194 * no VFs or the link is down
6195 */
6196 if (!adapter->num_vfs ||
6197 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6198 ready = true;
6199 goto normal_timer_service;
6200 }
6201
6202 /* If we have VFs allocated then we must check for DMA hangs */
6203 ixgbe_check_for_bad_vf(adapter);
6204 next_event_offset = HZ / 50;
6205 adapter->timer_event_accumulator++;
6206
6207 if (adapter->timer_event_accumulator >= 100) {
6208 ready = true;
6209 adapter->timer_event_accumulator = 0;
6210 }
6211
6212 goto schedule_event;
6213
6214normal_timer_service:
6215#endif
7086400d
AD		 6216 /* poll faster when waiting for link */
6217 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6218 next_event_offset = HZ / 10;
6219 else
6220 next_event_offset = HZ * 2;
6221
83c61fa9
GR		 6222#ifdef CONFIG_PCI_IOV
6223schedule_event:
6224#endif
7086400d
AD		 6225 /* Reset the timer */
6226 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6227
83c61fa9
GR		 6228 if (ready)
6229 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6230}
6231
c83c6cbd
AD		 6232static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6233{
6234 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6235 return;
6236
6237 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6238
6239 /* If we're already down or resetting, just bail */
6240 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6241 test_bit(__IXGBE_RESETTING, &adapter->state))
6242 return;
6243
6244 ixgbe_dump(adapter);
6245 netdev_err(adapter->netdev, "Reset adapter\n");
6246 adapter->tx_timeout_count++;
6247
6248 ixgbe_reinit_locked(adapter);
6249}
6250
7086400d
AD		 6251/**
6252 * ixgbe_service_task - manages and runs subtasks
6253 * @work: pointer to work_struct containing our data
6254 **/
6255static void ixgbe_service_task(struct work_struct *work)
6256{
6257 struct ixgbe_adapter *adapter = container_of(work,
6258 struct ixgbe_adapter,
6259 service_task);
6260
c83c6cbd 6261 ixgbe_reset_subtask(adapter);
7086400d
AD		 6262 ixgbe_sfp_detection_subtask(adapter);
6263 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6264 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6265 ixgbe_watchdog_subtask(adapter);
d034acf1 6266 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6267 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6268
6269 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6270}
6271
897ab156
AD		 6272void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6273 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6274{
6275 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6276 u16 i = tx_ring->next_to_use;
9a799d71 6277
897ab156 6278 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6279
897ab156
AD		 6280 i++;
6281 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6282
897ab156
AD		 6283 /* set bits to identify this as an advanced context descriptor */
6284 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6285
897ab156
AD		 6286 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6287 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6288 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6289 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6290}
9a799d71 6291
897ab156
AD		 6292static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6293 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6294{
6295 int err;
6296 u32 vlan_macip_lens, type_tucmd;
6297 u32 mss_l4len_idx, l4len;
9a799d71 6298
897ab156
AD		 6299 if (!skb_is_gso(skb))
6300 return 0;
9a799d71 6301
897ab156
AD		 6302 if (skb_header_cloned(skb)) {
6303 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6304 if (err)
6305 return err;
9a799d71 6306 }
9a799d71 6307
897ab156
AD		 6308 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6309 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6310
6311 if (protocol == __constant_htons(ETH_P_IP)) {
6312 struct iphdr *iph = ip_hdr(skb);
6313 iph->tot_len = 0;
6314 iph->check = 0;
6315 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6316 iph->daddr, 0,
6317 IPPROTO_TCP,
6318 0);
6319 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6320 } else if (skb_is_gso_v6(skb)) {
6321 ipv6_hdr(skb)->payload_len = 0;
6322 tcp_hdr(skb)->check =
6323 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6324 &ipv6_hdr(skb)->daddr,
6325 0, IPPROTO_TCP, 0);
6326 }
6327
6328 l4len = tcp_hdrlen(skb);
6329 *hdr_len = skb_transport_offset(skb) + l4len;
6330
6331 /* mss_l4len_id: use 1 as index for TSO */
6332 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6333 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6334 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6335
6336 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6337 vlan_macip_lens = skb_network_header_len(skb);
6338 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6339 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6340
6341 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6342 mss_l4len_idx);
6343
6344 return 1;
6345}
6346
6347static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6348 struct sk_buff *skb, u32 tx_flags,
6349 __be16 protocol)
7ca647bd 6350{
897ab156
AD		 6351 u32 vlan_macip_lens = 0;
6352 u32 mss_l4len_idx = 0;
6353 u32 type_tucmd = 0;
7ca647bd 6354
897ab156 6355 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6356 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6357 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6358 return false;
6359 } else {
6360 u8 l4_hdr = 0;
6361 switch (protocol) {
6362 case __constant_htons(ETH_P_IP):
6363 vlan_macip_lens |= skb_network_header_len(skb);
6364 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6365 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6366 break;
897ab156
AD		 6367 case __constant_htons(ETH_P_IPV6):
6368 vlan_macip_lens |= skb_network_header_len(skb);
6369 l4_hdr = ipv6_hdr(skb)->nexthdr;
6370 break;
6371 default:
6372 if (unlikely(net_ratelimit())) {
6373 dev_warn(tx_ring->dev,
6374 "partial checksum but proto=%x!\n",
6375 skb->protocol);
6376 }
7ca647bd
JP		 6377 break;
6378 }
897ab156
AD		 6379
6380 switch (l4_hdr) {
7ca647bd 6381 case IPPROTO_TCP:
897ab156
AD		 6382 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6383 mss_l4len_idx = tcp_hdrlen(skb) <<
6384 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6385 break;
6386 case IPPROTO_SCTP:
897ab156
AD		 6387 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6388 mss_l4len_idx = sizeof(struct sctphdr) <<
6389 IXGBE_ADVTXD_L4LEN_SHIFT;
6390 break;
6391 case IPPROTO_UDP:
6392 mss_l4len_idx = sizeof(struct udphdr) <<
6393 IXGBE_ADVTXD_L4LEN_SHIFT;
6394 break;
6395 default:
6396 if (unlikely(net_ratelimit())) {
6397 dev_warn(tx_ring->dev,
6398 "partial checksum but l4 proto=%x!\n",
6399 skb->protocol);
6400 }
7ca647bd
JP		 6401 break;
6402 }
7ca647bd
JP		 6403 }
6404
897ab156
AD		 6405 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6406 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6407
897ab156
AD		 6408 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6409 type_tucmd, mss_l4len_idx);
9a799d71 6410
897ab156 6411 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6412}
6413
d3d00239 6414static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6415{
d3d00239
AD		 6416 /* set type for advanced descriptor with frame checksum insertion */
6417 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6418 IXGBE_ADVTXD_DCMD_IFCS |
6419 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6420
d3d00239 6421 /* set HW vlan bit if vlan is present */
66f32a8b 6422 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6423 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6424
d3d00239
AD		 6425 /* set segmentation enable bits for TSO/FSO */
6426#ifdef IXGBE_FCOE
6427 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6428#else
6429 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6430#endif
6431 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6432
d3d00239
AD		 6433 return cmd_type;
6434}
9a799d71 6435
d3d00239
AD		 6436static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6437{
6438 __le32 olinfo_status =
6439 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6440
d3d00239
AD		 6441 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6442 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6443 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6444 /* enble IPv4 checksum for TSO */
6445 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6446 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6447 }
6448
d3d00239
AD		 6449 /* enable L4 checksum for TSO and TX checksum offload */
6450 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6451 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6452
d3d00239
AD		 6453#ifdef IXGBE_FCOE
6454 /* use index 1 context for FCOE/FSO */
6455 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6456 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6457 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6458
d3d00239 6459#endif
7f9643fd
AD		 6460 /*
6461 * Check Context must be set if Tx switch is enabled, which it
6462 * always is for case where virtual functions are running
6463 */
6464 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6465 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6466
d3d00239
AD		 6467 return olinfo_status;
6468}
44df32c5 6469
d3d00239
AD		 6470#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6471 IXGBE_TXD_CMD_RS)
6472
6473static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6474 struct sk_buff *skb,
6475 struct ixgbe_tx_buffer *first,
6476 u32 tx_flags,
6477 const u8 hdr_len)
6478{
6479 struct device *dev = tx_ring->dev;
6480 struct ixgbe_tx_buffer *tx_buffer_info;
6481 union ixgbe_adv_tx_desc *tx_desc;
6482 dma_addr_t dma;
6483 __le32 cmd_type, olinfo_status;
6484 struct skb_frag_struct *frag;
6485 unsigned int f = 0;
6486 unsigned int data_len = skb->data_len;
6487 unsigned int size = skb_headlen(skb);
6488 u32 offset = 0;
6489 u32 paylen = skb->len - hdr_len;
6490 u16 i = tx_ring->next_to_use;
6491 u16 gso_segs;
6492
6493#ifdef IXGBE_FCOE
6494 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6495 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6496 data_len -= sizeof(struct fcoe_crc_eof);
6497 } else {
6498 size -= sizeof(struct fcoe_crc_eof) - data_len;
6499 data_len = 0;
9a799d71
AK		 6500 }
6501 }
44df32c5 6502
d3d00239
AD		 6503#endif
6504 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6505 if (dma_mapping_error(dev, dma))
6506 goto dma_error;
8ad494b0 6507
d3d00239
AD		 6508 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6509 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6510
d3d00239 6511 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6512
d3d00239
AD		 6513 for (;;) {
6514 while (size > IXGBE_MAX_DATA_PER_TXD) {
6515 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6516 tx_desc->read.cmd_type_len =
6517 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6518 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6519
d3d00239
AD		 6520 offset += IXGBE_MAX_DATA_PER_TXD;
6521 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6522
d3d00239
AD		 6523 tx_desc++;
6524 i++;
6525 if (i == tx_ring->count) {
6526 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6527 i = 0;
6528 }
6529 }
e5a43549 6530
e5a43549 6531 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6532 tx_buffer_info->length = offset + size;
6533 tx_buffer_info->tx_flags = tx_flags;
6534 tx_buffer_info->dma = dma;
9a799d71 6535
d3d00239
AD		 6536 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6537 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6538 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6539
d3d00239
AD		 6540 if (!data_len)
6541 break;
9a799d71 6542
d3d00239
AD		 6543 frag = &skb_shinfo(skb)->frags[f];
6544#ifdef IXGBE_FCOE
9e903e08 6545 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6546#else
9e903e08 6547 size = skb_frag_size(frag);
d3d00239
AD		 6548#endif
6549 data_len -= size;
6550 f++;
9a799d71 6551
d3d00239
AD		 6552 offset = 0;
6553 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6554
877749bf 6555 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6556 if (dma_mapping_error(dev, dma))
6557 goto dma_error;
9a799d71 6558
d3d00239
AD		 6559 tx_desc++;
6560 i++;
6561 if (i == tx_ring->count) {
6562 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6563 i = 0;
6564 }
6565 }
9a799d71 6566
d3d00239 6567 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6568
d3d00239
AD		 6569 i++;
6570 if (i == tx_ring->count)
6571 i = 0;
9a799d71 6572
d3d00239 6573 tx_ring->next_to_use = i;
eacd73f7 6574
d3d00239
AD		 6575 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6576 gso_segs = skb_shinfo(skb)->gso_segs;
6577#ifdef IXGBE_FCOE
6578 /* adjust for FCoE Sequence Offload */
6579 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6580 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6581 skb_shinfo(skb)->gso_size);
6582#endif /* IXGBE_FCOE */
6583 else
6584 gso_segs = 1;
9a799d71 6585
d3d00239
AD		 6586 /* multiply data chunks by size of headers */
6587 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6588 tx_buffer_info->gso_segs = gso_segs;
6589 tx_buffer_info->skb = skb;
9a799d71 6590
d3d00239
AD		 6591 /* set the timestamp */
6592 first->time_stamp = jiffies;
9a799d71
AK		 6593
6594 /*
6595 * Force memory writes to complete before letting h/w
6596 * know there are new descriptors to fetch. (Only
6597 * applicable for weak-ordered memory model archs,
6598 * such as IA-64).
6599 */
6600 wmb();
6601
d3d00239
AD		 6602 /* set next_to_watch value indicating a packet is present */
6603 first->next_to_watch = tx_desc;
6604
6605 /* notify HW of packet */
84ea2591 6606 writel(i, tx_ring->tail);
d3d00239
AD		 6607
6608 return;
6609dma_error:
6610 dev_err(dev, "TX DMA map failed\n");
6611
6612 /* clear dma mappings for failed tx_buffer_info map */
6613 for (;;) {
6614 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6615 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6616 if (tx_buffer_info == first)
6617 break;
6618 if (i == 0)
6619 i = tx_ring->count;
6620 i--;
6621 }
6622
6623 dev_kfree_skb_any(skb);
6624
6625 tx_ring->next_to_use = i;
9a799d71
AK		 6626}
6627
69830529
AD		 6628static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6629 u32 tx_flags, __be16 protocol)
6630{
6631 struct ixgbe_q_vector *q_vector = ring->q_vector;
6632 union ixgbe_atr_hash_dword input = { .dword = 0 };
6633 union ixgbe_atr_hash_dword common = { .dword = 0 };
6634 union {
6635 unsigned char *network;
6636 struct iphdr *ipv4;
6637 struct ipv6hdr *ipv6;
6638 } hdr;
ee9e0f0b 6639 struct tcphdr *th;
905e4a41 6640 __be16 vlan_id;
c4cf55e5 6641
69830529
AD		 6642 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6643 if (!q_vector)
6644 return;
6645
6646 /* do nothing if sampling is disabled */
6647 if (!ring->atr_sample_rate)
d3ead241 6648 return;
c4cf55e5 6649
69830529 6650 ring->atr_count++;
c4cf55e5 6651
69830529
AD		 6652 /* snag network header to get L4 type and address */
6653 hdr.network = skb_network_header(skb);
6654
6655 /* Currently only IPv4/IPv6 with TCP is supported */
6656 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6657 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6658 (protocol != __constant_htons(ETH_P_IP) ||
6659 hdr.ipv4->protocol != IPPROTO_TCP))
6660 return;
ee9e0f0b
AD		 6661
6662 th = tcp_hdr(skb);
c4cf55e5 6663
66f32a8b
AD		 6664 /* skip this packet since it is invalid or the socket is closing */
6665 if (!th || th->fin)
69830529
AD		 6666 return;
6667
6668 /* sample on all syn packets or once every atr sample count */
6669 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6670 return;
6671
6672 /* reset sample count */
6673 ring->atr_count = 0;
6674
6675 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6676
6677 /*
6678 * src and dst are inverted, think how the receiver sees them
6679 *
6680 * The input is broken into two sections, a non-compressed section
6681 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6682 * is XORed together and stored in the compressed dword.
6683 */
6684 input.formatted.vlan_id = vlan_id;
6685
6686 /*
6687 * since src port and flex bytes occupy the same word XOR them together
6688 * and write the value to source port portion of compressed dword
6689 */
66f32a8b 6690 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6691 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6692 else
6693 common.port.src ^= th->dest ^ protocol;
6694 common.port.dst ^= th->source;
6695
6696 if (protocol == __constant_htons(ETH_P_IP)) {
6697 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6698 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6699 } else {
6700 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6701 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6702 hdr.ipv6->saddr.s6_addr32[1] ^
6703 hdr.ipv6->saddr.s6_addr32[2] ^
6704 hdr.ipv6->saddr.s6_addr32[3] ^
6705 hdr.ipv6->daddr.s6_addr32[0] ^
6706 hdr.ipv6->daddr.s6_addr32[1] ^
6707 hdr.ipv6->daddr.s6_addr32[2] ^
6708 hdr.ipv6->daddr.s6_addr32[3];
6709 }
c4cf55e5
PWJ		 6710
6711 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6712 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6713 input, common, ring->queue_index);
c4cf55e5
PWJ		 6714}
6715
63544e9c 6716static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6717{
fc77dc3c 6718 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6719 /* Herbert's original patch had:
6720 * smp_mb__after_netif_stop_queue();
6721 * but since that doesn't exist yet, just open code it. */
6722 smp_mb();
6723
6724 /* We need to check again in a case another CPU has just
6725 * made room available. */
7d4987de 6726 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6727 return -EBUSY;
6728
6729 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6730 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6731 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6732 return 0;
6733}
6734
82d4e46e 6735static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6736{
7d4987de 6737 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6738 return 0;
fc77dc3c 6739 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6740}
6741
09a3b1f8
SH		 6742static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6743{
6744 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6745 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6746 smp_processor_id();
56075a98 6747#ifdef IXGBE_FCOE
6440752c 6748 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6749
e5b64635
JF		 6750 if (((protocol == htons(ETH_P_FCOE)) ||
6751 (protocol == htons(ETH_P_FIP))) &&
6752 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6753 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6754 txq += adapter->ring_feature[RING_F_FCOE].mask;
6755 return txq;
56075a98
JF		 6756 }
6757#endif
6758
fdd3d631
KK		 6759 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6760 while (unlikely(txq >= dev->real_num_tx_queues))
6761 txq -= dev->real_num_tx_queues;
5f715823 6762 return txq;
fdd3d631 6763 }
c4cf55e5 6764
09a3b1f8
SH		 6765 return skb_tx_hash(dev, skb);
6766}
6767
fc77dc3c 6768netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6769 struct ixgbe_adapter *adapter,
6770 struct ixgbe_ring *tx_ring)
9a799d71 6771{
d3d00239 6772 struct ixgbe_tx_buffer *first;
5f715823 6773 int tso;
d3d00239 6774 u32 tx_flags = 0;
a535c30e
AD		 6775#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6776 unsigned short f;
6777#endif
a535c30e 6778 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6779 __be16 protocol = skb->protocol;
63544e9c 6780 u8 hdr_len = 0;
5e09a105 6781
a535c30e
AD		 6782 /*
6783 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6784 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6785 * + 2 desc gap to keep tail from touching head,
6786 * + 1 desc for context descriptor,
6787 * otherwise try next time
6788 */
6789#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6790 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6791 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6792#else
6793 count += skb_shinfo(skb)->nr_frags;
6794#endif
6795 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6796 tx_ring->tx_stats.tx_busy++;
6797 return NETDEV_TX_BUSY;
6798 }
6799
7f9643fd
AD		 6800#ifdef CONFIG_PCI_IOV
6801 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6802 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6803
6804#endif
66f32a8b 6805 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6806 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6807 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6808 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6809 /* else if it is a SW VLAN check the next protocol and store the tag */
6810 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6811 struct vlan_hdr *vhdr, _vhdr;
6812 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6813 if (!vhdr)
6814 goto out_drop;
6815
6816 protocol = vhdr->h_vlan_encapsulated_proto;
6817 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6818 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6819 }
6820
32701dc2 6821 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6822 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6823 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6824 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6825 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6826 tx_flags |= (skb->priority & 0x7) <<
6827 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6828 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6829 struct vlan_ethhdr *vhdr;
6830 if (skb_header_cloned(skb) &&
6831 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6832 goto out_drop;
6833 vhdr = (struct vlan_ethhdr *)skb->data;
6834 vhdr->h_vlan_TCI = htons(tx_flags >>
6835 IXGBE_TX_FLAGS_VLAN_SHIFT);
6836 } else {
6837 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6838 }
9a799d71 6839 }
eacd73f7 6840
a535c30e 6841 /* record the location of the first descriptor for this packet */
d3d00239 6842 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6843
eacd73f7 6844#ifdef IXGBE_FCOE
66f32a8b
AD		 6845 /* setup tx offload for FCoE */
6846 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6847 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6848 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6849 if (tso < 0)
6850 goto out_drop;
6851 else if (tso)
66f32a8b
AD		 6852 tx_flags |= IXGBE_TX_FLAGS_FSO |
6853 IXGBE_TX_FLAGS_FCOE;
6854 else
6855 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6856
66f32a8b 6857 goto xmit_fcoe;
eacd73f7 6858 }
9a799d71 6859
66f32a8b
AD		 6860#endif /* IXGBE_FCOE */
6861 /* setup IPv4/IPv6 offloads */
6862 if (protocol == __constant_htons(ETH_P_IP))
6863 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6864
66f32a8b
AD		 6865 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6866 if (tso < 0)
897ab156 6867 goto out_drop;
66f32a8b
AD		 6868 else if (tso)
6869 tx_flags |= IXGBE_TX_FLAGS_TSO;
6870 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6871 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6872
6873 /* add the ATR filter if ATR is on */
6874 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6875 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6876
6877#ifdef IXGBE_FCOE
6878xmit_fcoe:
6879#endif /* IXGBE_FCOE */
d3d00239
AD		 6880 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6881
6882 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6883
6884 return NETDEV_TX_OK;
897ab156
AD		 6885
6886out_drop:
6887 dev_kfree_skb_any(skb);
6888 return NETDEV_TX_OK;
9a799d71
AK		 6889}
6890
84418e3b
AD		 6891static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6892{
6893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6894 struct ixgbe_ring *tx_ring;
6895
6896 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6897 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6898}
6899
9a799d71
AK		 6900/**
6901 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6902 * @netdev: network interface device structure
6903 * @p: pointer to an address structure
6904 *
6905 * Returns 0 on success, negative on failure
6906 **/
6907static int ixgbe_set_mac(struct net_device *netdev, void *p)
6908{
6909 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6910 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6911 struct sockaddr *addr = p;
6912
6913 if (!is_valid_ether_addr(addr->sa_data))
6914 return -EADDRNOTAVAIL;
6915
6916 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6917 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6918
1cdd1ec8
GR		 6919 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6920 IXGBE_RAH_AV);
9a799d71
AK		 6921
6922 return 0;
6923}
6924
6b73e10d
BH		 6925static int
6926ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6927{
6928 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6929 struct ixgbe_hw *hw = &adapter->hw;
6930 u16 value;
6931 int rc;
6932
6933 if (prtad != hw->phy.mdio.prtad)
6934 return -EINVAL;
6935 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6936 if (!rc)
6937 rc = value;
6938 return rc;
6939}
6940
6941static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6942 u16 addr, u16 value)
6943{
6944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6945 struct ixgbe_hw *hw = &adapter->hw;
6946
6947 if (prtad != hw->phy.mdio.prtad)
6948 return -EINVAL;
6949 return hw->phy.ops.write_reg(hw, addr, devad, value);
6950}
6951
6952static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6953{
6954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6955
6956 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6957}
6958
0365e6e4
PW		 6959/**
6960 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6961 * netdev->dev_addrs
0365e6e4
PW		 6962 * @netdev: network interface device structure
6963 *
6964 * Returns non-zero on failure
6965 **/
6966static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6967{
6968 int err = 0;
6969 struct ixgbe_adapter *adapter = netdev_priv(dev);
6970 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6971
6972 if (is_valid_ether_addr(mac->san_addr)) {
6973 rtnl_lock();
6974 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6975 rtnl_unlock();
6976 }
6977 return err;
6978}
6979
6980/**
6981 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6982 * netdev->dev_addrs
0365e6e4
PW		 6983 * @netdev: network interface device structure
6984 *
6985 * Returns non-zero on failure
6986 **/
6987static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6988{
6989 int err = 0;
6990 struct ixgbe_adapter *adapter = netdev_priv(dev);
6991 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6992
6993 if (is_valid_ether_addr(mac->san_addr)) {
6994 rtnl_lock();
6995 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6996 rtnl_unlock();
6997 }
6998 return err;
6999}
7000
9a799d71
AK		 7001#ifdef CONFIG_NET_POLL_CONTROLLER
7002/*
7003 * Polling 'interrupt' - used by things like netconsole to send skbs
7004 * without having to re-enable interrupts. It's not called while
7005 * the interrupt routine is executing.
7006 */
7007static void ixgbe_netpoll(struct net_device *netdev)
7008{
7009 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7010 int i;
9a799d71 7011
1a647bd2
AD		 7012 /* if interface is down do nothing */
7013 if (test_bit(__IXGBE_DOWN, &adapter->state))
7014 return;
7015
9a799d71 7016 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7017 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7018 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7019 for (i = 0; i < num_q_vectors; i++) {
7020 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7021 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7022 }
7023 } else {
7024 ixgbe_intr(adapter->pdev->irq, netdev);
7025 }
9a799d71 7026 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7027}
7028#endif
7029
de1036b1
ED		 7030static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7031 struct rtnl_link_stats64 *stats)
7032{
7033 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7034 int i;
7035
1a51502b 7036 rcu_read_lock();
de1036b1 7037 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7038 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7039 u64 bytes, packets;
7040 unsigned int start;
7041
1a51502b
ED		 7042 if (ring) {
7043 do {
7044 start = u64_stats_fetch_begin_bh(&ring->syncp);
7045 packets = ring->stats.packets;
7046 bytes = ring->stats.bytes;
7047 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7048 stats->rx_packets += packets;
7049 stats->rx_bytes += bytes;
7050 }
de1036b1 7051 }
1ac9ad13
ED		 7052
7053 for (i = 0; i < adapter->num_tx_queues; i++) {
7054 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7055 u64 bytes, packets;
7056 unsigned int start;
7057
7058 if (ring) {
7059 do {
7060 start = u64_stats_fetch_begin_bh(&ring->syncp);
7061 packets = ring->stats.packets;
7062 bytes = ring->stats.bytes;
7063 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7064 stats->tx_packets += packets;
7065 stats->tx_bytes += bytes;
7066 }
7067 }
1a51502b 7068 rcu_read_unlock();
de1036b1
ED		 7069 /* following stats updated by ixgbe_watchdog_task() */
7070 stats->multicast = netdev->stats.multicast;
7071 stats->rx_errors = netdev->stats.rx_errors;
7072 stats->rx_length_errors = netdev->stats.rx_length_errors;
7073 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7074 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7075 return stats;
7076}
7077
8b1c0b24
JF		 7078/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7079 * #adapter: pointer to ixgbe_adapter
7080 * @tc: number of traffic classes currently enabled
7081 *
7082 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7083 * 802.1Q priority maps to a packet buffer that exists.
7084 */
7085static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7086{
7087 struct ixgbe_hw *hw = &adapter->hw;
7088 u32 reg, rsave;
7089 int i;
7090
7091 /* 82598 have a static priority to TC mapping that can not
7092 * be changed so no validation is needed.
7093 */
7094 if (hw->mac.type == ixgbe_mac_82598EB)
7095 return;
7096
7097 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7098 rsave = reg;
7099
7100 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7101 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7102
7103 /* If up2tc is out of bounds default to zero */
7104 if (up2tc > tc)
7105 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7106 }
7107
7108 if (reg != rsave)
7109 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7110
7111 return;
7112}
7113
7114
7115/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7116 * classes.
7117 *
7118 * @netdev: net device to configure
7119 * @tc: number of traffic classes to enable
7120 */
7121int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7122{
8b1c0b24
JF		 7123 struct ixgbe_adapter *adapter = netdev_priv(dev);
7124 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7125
e7589eab
JF		 7126 /* Multiple traffic classes requires multiple queues */
7127 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7128 e_err(drv, "Enable failed, needs MSI-X\n");
7129 return -EINVAL;
7130 }
8b1c0b24
JF		 7131
7132 /* Hardware supports up to 8 traffic classes */
4de2a022 7133 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7134 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7135 return -EINVAL;
7136
7137 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7138 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7139 * hardware is not flexible enough to do this dynamically.
7140 */
7141 if (netif_running(dev))
7142 ixgbe_close(dev);
7143 ixgbe_clear_interrupt_scheme(adapter);
7144
e7589eab 7145 if (tc) {
8b1c0b24 7146 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7147 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7148
7149 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7150 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7151
7152 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7153 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7154 } else {
8b1c0b24
JF		 7155 netdev_reset_tc(dev);
7156
e7589eab
JF		 7157 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7158
7159 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7160 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7161
7162 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7163 adapter->dcb_cfg.pfc_mode_enable = false;
7164 }
7165
8b1c0b24
JF		 7166 ixgbe_init_interrupt_scheme(adapter);
7167 ixgbe_validate_rtr(adapter, tc);
7168 if (netif_running(dev))
7169 ixgbe_open(dev);
7170
7171 return 0;
7172}
de1036b1 7173
082757af
DS		 7174void ixgbe_do_reset(struct net_device *netdev)
7175{
7176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7177
7178 if (netif_running(netdev))
7179 ixgbe_reinit_locked(adapter);
7180 else
7181 ixgbe_reset(adapter);
7182}
7183
c8f44aff
MM		 7184static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7185 netdev_features_t data)
082757af
DS		 7186{
7187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7188
7189#ifdef CONFIG_DCB
7190 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7191 data &= ~NETIF_F_HW_VLAN_RX;
7192#endif
7193
7194 /* return error if RXHASH is being enabled when RSS is not supported */
7195 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7196 data &= ~NETIF_F_RXHASH;
7197
7198 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7199 if (!(data & NETIF_F_RXCSUM))
7200 data &= ~NETIF_F_LRO;
7201
7202 /* Turn off LRO if not RSC capable or invalid ITR settings */
7203 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7204 data &= ~NETIF_F_LRO;
7205 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7206 (adapter->rx_itr_setting != 1 &&
7207 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7208 data &= ~NETIF_F_LRO;
7209 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7210 }
7211
7212 return data;
7213}
7214
c8f44aff
MM		 7215static int ixgbe_set_features(struct net_device *netdev,
7216 netdev_features_t data)
082757af
DS		 7217{
7218 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7219 bool need_reset = false;
7220
7221 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7222 if (!(data & NETIF_F_RXCSUM))
7223 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7224 else
7225 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7226
7227 /* Make sure RSC matches LRO, reset if change */
7228 if (!!(data & NETIF_F_LRO) !=
7229 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7230 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7231 switch (adapter->hw.mac.type) {
7232 case ixgbe_mac_X540:
7233 case ixgbe_mac_82599EB:
7234 need_reset = true;
7235 break;
7236 default:
7237 break;
7238 }
7239 }
7240
7241 /*
7242 * Check if Flow Director n-tuple support was enabled or disabled. If
7243 * the state changed, we need to reset.
7244 */
7245 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7246 /* turn off ATR, enable perfect filters and reset */
7247 if (data & NETIF_F_NTUPLE) {
7248 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7249 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7250 need_reset = true;
7251 }
7252 } else if (!(data & NETIF_F_NTUPLE)) {
7253 /* turn off Flow Director, set ATR and reset */
7254 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7255 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7256 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7257 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7258 need_reset = true;
7259 }
7260
7261 if (need_reset)
7262 ixgbe_do_reset(netdev);
7263
7264 return 0;
7265
7266}
7267
0edc3527 7268static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7269 .ndo_open = ixgbe_open,
0edc3527 7270 .ndo_stop = ixgbe_close,
00829823 7271 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7272 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7273 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7274 .ndo_validate_addr = eth_validate_addr,
7275 .ndo_set_mac_address = ixgbe_set_mac,
7276 .ndo_change_mtu = ixgbe_change_mtu,
7277 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7278 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7279 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7280 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7281 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7282 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7283 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7284 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7285 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7286 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7287 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7288#ifdef CONFIG_NET_POLL_CONTROLLER
7289 .ndo_poll_controller = ixgbe_netpoll,
7290#endif
332d4a7d
YZ		 7291#ifdef IXGBE_FCOE
7292 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7293 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7294 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7295 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7296 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7297 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7298 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7299#endif /* IXGBE_FCOE */
082757af
DS		 7300 .ndo_set_features = ixgbe_set_features,
7301 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7302};
7303
1cdd1ec8
GR		 7304static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7305 const struct ixgbe_info *ii)
7306{
7307#ifdef CONFIG_PCI_IOV
7308 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7309
c6bda30a 7310 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7311 return;
7312
7313 /* The 82599 supports up to 64 VFs per physical function
7314 * but this implementation limits allocation to 63 so that
7315 * basic networking resources are still available to the
7316 * physical function
7317 */
7318 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7319 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7320#endif /* CONFIG_PCI_IOV */
7321}
7322
9a799d71
AK		 7323/**
7324 * ixgbe_probe - Device Initialization Routine
7325 * @pdev: PCI device information struct
7326 * @ent: entry in ixgbe_pci_tbl
7327 *
7328 * Returns 0 on success, negative on failure
7329 *
7330 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7331 * The OS initialization, configuring of the adapter private structure,
7332 * and a hardware reset occur.
7333 **/
7334static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7335 const struct pci_device_id *ent)
9a799d71
AK		 7336{
7337 struct net_device *netdev;
7338 struct ixgbe_adapter *adapter = NULL;
7339 struct ixgbe_hw *hw;
7340 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7341 static int cards_found;
7342 int i, err, pci_using_dac;
289700db 7343 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7344 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7345#ifdef IXGBE_FCOE
7346 u16 device_caps;
7347#endif
289700db 7348 u32 eec;
c23f5b6b 7349 u16 wol_cap;
9a799d71 7350
bded64a7
AG		 7351 /* Catch broken hardware that put the wrong VF device ID in
7352 * the PCIe SR-IOV capability.
7353 */
7354 if (pdev->is_virtfn) {
7355 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7356 pci_name(pdev), pdev->vendor, pdev->device);
7357 return -EINVAL;
7358 }
7359
9ce77666 7360 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7361 if (err)
7362 return err;
7363
1b507730
NN		 7364 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7365 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7366 pci_using_dac = 1;
7367 } else {
1b507730 7368 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7369 if (err) {
1b507730
NN		 7370 err = dma_set_coherent_mask(&pdev->dev,
7371 DMA_BIT_MASK(32));
9a799d71 7372 if (err) {
b8bc0421
DC		 7373 dev_err(&pdev->dev,
7374 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7375 goto err_dma;
7376 }
7377 }
7378 pci_using_dac = 0;
7379 }
7380
9ce77666 7381 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7382 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7383 if (err) {
b8bc0421
DC		 7384 dev_err(&pdev->dev,
7385 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7386 goto err_pci_reg;
7387 }
7388
19d5afd4 7389 pci_enable_pcie_error_reporting(pdev);
6fabd715 7390
9a799d71 7391 pci_set_master(pdev);
fb3b27bc 7392 pci_save_state(pdev);
9a799d71 7393
e901acd6
JF		 7394#ifdef CONFIG_IXGBE_DCB
7395 indices *= MAX_TRAFFIC_CLASS;
7396#endif
7397
c85a2618
JF		 7398 if (ii->mac == ixgbe_mac_82598EB)
7399 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7400 else
7401 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7402
e901acd6 7403#ifdef IXGBE_FCOE
c85a2618
JF		 7404 indices += min_t(unsigned int, num_possible_cpus(),
7405 IXGBE_MAX_FCOE_INDICES);
7406#endif
c85a2618 7407 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7408 if (!netdev) {
7409 err = -ENOMEM;
7410 goto err_alloc_etherdev;
7411 }
7412
9a799d71
AK		 7413 SET_NETDEV_DEV(netdev, &pdev->dev);
7414
9a799d71 7415 adapter = netdev_priv(netdev);
c60fbb00 7416 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7417
7418 adapter->netdev = netdev;
7419 adapter->pdev = pdev;
7420 hw = &adapter->hw;
7421 hw->back = adapter;
7422 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7423
05857980 7424 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7425 pci_resource_len(pdev, 0));
9a799d71
AK		 7426 if (!hw->hw_addr) {
7427 err = -EIO;
7428 goto err_ioremap;
7429 }
7430
7431 for (i = 1; i <= 5; i++) {
7432 if (pci_resource_len(pdev, i) == 0)
7433 continue;
7434 }
7435
0edc3527 7436 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7437 ixgbe_set_ethtool_ops(netdev);
9a799d71 7438 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7439 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7440
9a799d71
AK		 7441 adapter->bd_number = cards_found;
7442
9a799d71
AK		 7443 /* Setup hw api */
7444 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7445 hw->mac.type = ii->mac;
9a799d71 7446
c44ade9e
JB		 7447 /* EEPROM */
7448 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7449 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7450 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7451 if (!(eec & (1 << 8)))
7452 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7453
7454 /* PHY */
7455 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7456 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7457 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7458 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7459 hw->phy.mdio.mmds = 0;
7460 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7461 hw->phy.mdio.dev = netdev;
7462 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7463 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7464
8ca783ab 7465 ii->get_invariants(hw);
9a799d71
AK		 7466
7467 /* setup the private structure */
7468 err = ixgbe_sw_init(adapter);
7469 if (err)
7470 goto err_sw_init;
7471
e86bff0e 7472 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7473 switch (adapter->hw.mac.type) {
7474 case ixgbe_mac_82599EB:
7475 case ixgbe_mac_X540:
e86bff0e 7476 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7477 break;
7478 default:
7479 break;
7480 }
e86bff0e 7481
bf069c97
DS		 7482 /*
7483 * If there is a fan on this device and it has failed log the
7484 * failure.
7485 */
7486 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7487 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7488 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7489 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7490 }
7491
c44ade9e 7492 /* reset_hw fills in the perm_addr as well */
119fc60a 7493 hw->phy.reset_if_overtemp = true;
c44ade9e 7494 err = hw->mac.ops.reset_hw(hw);
119fc60a 7495 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7496 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7497 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7498 err = 0;
7499 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7500 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7501 "module type was detected.\n");
7502 e_dev_err("Reload the driver after installing a supported "
7503 "module.\n");
04f165ef
PW		 7504 goto err_sw_init;
7505 } else if (err) {
849c4542 7506 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7507 goto err_sw_init;
7508 }
7509
1cdd1ec8
GR		 7510 ixgbe_probe_vf(adapter, ii);
7511
396e799c 7512 netdev->features = NETIF_F_SG |
e8e9f696 7513 NETIF_F_IP_CSUM |
082757af 7514 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7515 NETIF_F_HW_VLAN_TX |
7516 NETIF_F_HW_VLAN_RX |
082757af
DS		 7517 NETIF_F_HW_VLAN_FILTER |
7518 NETIF_F_TSO |
7519 NETIF_F_TSO6 |
082757af
DS		 7520 NETIF_F_RXHASH |
7521 NETIF_F_RXCSUM;
9a799d71 7522
082757af 7523 netdev->hw_features = netdev->features;
ad31c402 7524
58be7666
DS		 7525 switch (adapter->hw.mac.type) {
7526 case ixgbe_mac_82599EB:
7527 case ixgbe_mac_X540:
45a5ead0 7528 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7529 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7530 NETIF_F_NTUPLE;
58be7666
DS		 7531 break;
7532 default:
7533 break;
7534 }
45a5ead0 7535
ad31c402
JK		 7536 netdev->vlan_features |= NETIF_F_TSO;
7537 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7538 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7539 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7540 netdev->vlan_features |= NETIF_F_SG;
7541
01789349
JP		 7542 netdev->priv_flags |= IFF_UNICAST_FLT;
7543
1cdd1ec8
GR		 7544 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7545 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7546 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7547
7a6b6f51 7548#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7549 netdev->dcbnl_ops = &dcbnl_ops;
7550#endif
7551
eacd73f7 7552#ifdef IXGBE_FCOE
0d551589 7553 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7554 if (hw->mac.ops.get_device_caps) {
7555 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7556 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7557 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7558 }
7559 }
5e09d7f6
YZ		 7560 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7561 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7562 netdev->vlan_features |= NETIF_F_FSO;
7563 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7564 }
eacd73f7 7565#endif /* IXGBE_FCOE */
7b872a55 7566 if (pci_using_dac) {
9a799d71 7567 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7568 netdev->vlan_features |= NETIF_F_HIGHDMA;
7569 }
9a799d71 7570
082757af
DS		 7571 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7572 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7573 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7574 netdev->features |= NETIF_F_LRO;
7575
9a799d71 7576 /* make sure the EEPROM is good */
c44ade9e 7577 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7578 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7579 err = -EIO;
7580 goto err_eeprom;
7581 }
7582
7583 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7584 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7585
c44ade9e 7586 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7587 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7588 err = -EIO;
7589 goto err_eeprom;
7590 }
7591
7086400d
AD		 7592 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7593 (unsigned long) adapter);
9a799d71 7594
7086400d
AD		 7595 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7596 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7597
021230d4
AV		 7598 err = ixgbe_init_interrupt_scheme(adapter);
7599 if (err)
7600 goto err_sw_init;
9a799d71 7601
082757af
DS		 7602 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7603 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7604 netdev->features &= ~NETIF_F_RXHASH;
082757af 7605 }
67a74ee2 7606
c23f5b6b
ET		 7607 /* WOL not supported for all but the following */
7608 adapter->wol = 0;
e8e26350 7609 switch (pdev->device) {
0b077fea 7610 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7611 /* Only these subdevice supports WOL */
7612 switch (pdev->subsystem_device) {
7613 case IXGBE_SUBDEV_ID_82599_560FLR:
7614 /* only support first port */
7615 if (hw->bus.func != 0)
7616 break;
7617 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7618 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7619 break;
7620 }
0b077fea 7621 break;
50d6c681
AD		 7622 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7623 /* All except this subdevice support WOL */
0b077fea 7624 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7625 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7626 break;
e8e26350 7627 case IXGBE_DEV_ID_82599_KX4:
9417c464 7628 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7629 break;
c23f5b6b
ET		 7630 case IXGBE_DEV_ID_X540T:
7631 /* Check eeprom to see if it is enabled */
7632 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7633 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7634
7635 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7636 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7637 (hw->bus.func == 0)))
7638 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7639 break;
7640 }
e8e26350
PW		 7641 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7642
15e5209f
ET		 7643 /* save off EEPROM version number */
7644 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7645 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7646
04f165ef
PW		 7647 /* pick up the PCI bus settings for reporting later */
7648 hw->mac.ops.get_bus_info(hw);
7649
9a799d71 7650 /* print bus type/speed/width info */
849c4542 7651 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7652 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7653 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7654 "Unknown"),
7655 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7656 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7657 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7658 "Unknown"),
7659 netdev->dev_addr);
289700db
DS		 7660
7661 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7662 if (err)
9fe93afd 7663 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7664 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7665 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7666 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7667 part_str);
e8e26350 7668 else
289700db
DS		 7669 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7670 hw->mac.type, hw->phy.type, part_str);
9a799d71 7671
e8e26350 7672 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7673 e_dev_warn("PCI-Express bandwidth available for this card is "
7674 "not sufficient for optimal performance.\n");
7675 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7676 "is required.\n");
0c254d86
AK		 7677 }
7678
9a799d71 7679 /* reset the hardware with the new settings */
794caeb2 7680 err = hw->mac.ops.start_hw(hw);
c44ade9e 7681
794caeb2
PWJ		 7682 if (err == IXGBE_ERR_EEPROM_VERSION) {
7683 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7684 e_dev_warn("This device is a pre-production adapter/LOM. "
7685 "Please be aware there may be issues associated "
7686 "with your hardware. If you are experiencing "
7687 "problems please contact your Intel or hardware "
7688 "representative who provided you with this "
7689 "hardware.\n");
794caeb2 7690 }
9a799d71
AK		 7691 strcpy(netdev->name, "eth%d");
7692 err = register_netdev(netdev);
7693 if (err)
7694 goto err_register;
7695
93d3ce8f
ET		 7696 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7697 if (hw->mac.ops.disable_tx_laser &&
7698 ((hw->phy.multispeed_fiber) ||
7699 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7700 (hw->mac.type == ixgbe_mac_82599EB))))
7701 hw->mac.ops.disable_tx_laser(hw);
7702
54386467
JB		 7703 /* carrier off reporting is important to ethtool even BEFORE open */
7704 netif_carrier_off(netdev);
7705
5dd2d332 7706#ifdef CONFIG_IXGBE_DCA
652f093f 7707 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7708 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7709 ixgbe_setup_dca(adapter);
7710 }
7711#endif
1cdd1ec8 7712 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7713 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7714 for (i = 0; i < adapter->num_vfs; i++)
7715 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7716 }
7717
2466dd9c
JK		 7718 /* firmware requires driver version to be 0xFFFFFFFF
7719 * since os does not support feature
7720 */
9612de92 7721 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7722 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7723 0xFF);
9612de92 7724
0365e6e4
PW		 7725 /* add san mac addr to netdev */
7726 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7727
ea81875a 7728 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7729 cards_found++;
7730 return 0;
7731
7732err_register:
5eba3699 7733 ixgbe_release_hw_control(adapter);
7a921c93 7734 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7735err_sw_init:
7736err_eeprom:
1cdd1ec8
GR		 7737 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7738 ixgbe_disable_sriov(adapter);
7086400d 7739 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7740 iounmap(hw->hw_addr);
7741err_ioremap:
7742 free_netdev(netdev);
7743err_alloc_etherdev:
e8e9f696
JP		 7744 pci_release_selected_regions(pdev,
7745 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7746err_pci_reg:
7747err_dma:
7748 pci_disable_device(pdev);
7749 return err;
7750}
7751
7752/**
7753 * ixgbe_remove - Device Removal Routine
7754 * @pdev: PCI device information struct
7755 *
7756 * ixgbe_remove is called by the PCI subsystem to alert the driver
7757 * that it should release a PCI device. The could be caused by a
7758 * Hot-Plug event, or because the driver is going to be removed from
7759 * memory.
7760 **/
7761static void __devexit ixgbe_remove(struct pci_dev *pdev)
7762{
c60fbb00
AD		 7763 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7764 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7765
7766 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7767 cancel_work_sync(&adapter->service_task);
9a799d71 7768
5dd2d332 7769#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7770 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7771 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7772 dca_remove_requester(&pdev->dev);
7773 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7774 }
7775
7776#endif
332d4a7d
YZ		 7777#ifdef IXGBE_FCOE
7778 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7779 ixgbe_cleanup_fcoe(adapter);
7780
7781#endif /* IXGBE_FCOE */
0365e6e4
PW		 7782
7783 /* remove the added san mac */
7784 ixgbe_del_sanmac_netdev(netdev);
7785
c4900be0
DS		 7786 if (netdev->reg_state == NETREG_REGISTERED)
7787 unregister_netdev(netdev);
9a799d71 7788
c6bda30a
GR		 7789 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7790 if (!(ixgbe_check_vf_assignment(adapter)))
7791 ixgbe_disable_sriov(adapter);
7792 else
7793 e_dev_warn("Unloading driver while VFs are assigned "
7794 "- VFs will not be deallocated\n");
7795 }
1cdd1ec8 7796
7a921c93 7797 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7798
021230d4 7799 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7800
7801 iounmap(adapter->hw.hw_addr);
9ce77666 7802 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7803 IORESOURCE_MEM));
9a799d71 7804
849c4542 7805 e_dev_info("complete\n");
021230d4 7806
9a799d71
AK		 7807 free_netdev(netdev);
7808
19d5afd4 7809 pci_disable_pcie_error_reporting(pdev);
6fabd715 7810
9a799d71
AK		 7811 pci_disable_device(pdev);
7812}
7813
7814/**
7815 * ixgbe_io_error_detected - called when PCI error is detected
7816 * @pdev: Pointer to PCI device
7817 * @state: The current pci connection state
7818 *
7819 * This function is called after a PCI bus error affecting
7820 * this device has been detected.
7821 */
7822static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7823 pci_channel_state_t state)
9a799d71 7824{
c60fbb00
AD		 7825 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7826 struct net_device *netdev = adapter->netdev;
9a799d71 7827
83c61fa9
GR		 7828#ifdef CONFIG_PCI_IOV
7829 struct pci_dev *bdev, *vfdev;
7830 u32 dw0, dw1, dw2, dw3;
7831 int vf, pos;
7832 u16 req_id, pf_func;
7833
7834 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7835 adapter->num_vfs == 0)
7836 goto skip_bad_vf_detection;
7837
7838 bdev = pdev->bus->self;
7839 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7840 bdev = bdev->bus->self;
7841
7842 if (!bdev)
7843 goto skip_bad_vf_detection;
7844
7845 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7846 if (!pos)
7847 goto skip_bad_vf_detection;
7848
7849 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7850 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7851 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7852 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7853
7854 req_id = dw1 >> 16;
7855 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7856 if (!(req_id & 0x0080))
7857 goto skip_bad_vf_detection;
7858
7859 pf_func = req_id & 0x01;
7860 if ((pf_func & 1) == (pdev->devfn & 1)) {
7861 unsigned int device_id;
7862
7863 vf = (req_id & 0x7F) >> 1;
7864 e_dev_err("VF %d has caused a PCIe error\n", vf);
7865 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7866 "%8.8x\tdw3: %8.8x\n",
7867 dw0, dw1, dw2, dw3);
7868 switch (adapter->hw.mac.type) {
7869 case ixgbe_mac_82599EB:
7870 device_id = IXGBE_82599_VF_DEVICE_ID;
7871 break;
7872 case ixgbe_mac_X540:
7873 device_id = IXGBE_X540_VF_DEVICE_ID;
7874 break;
7875 default:
7876 device_id = 0;
7877 break;
7878 }
7879
7880 /* Find the pci device of the offending VF */
7881 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7882 while (vfdev) {
7883 if (vfdev->devfn == (req_id & 0xFF))
7884 break;
7885 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7886 device_id, vfdev);
7887 }
7888 /*
7889 * There's a slim chance the VF could have been hot plugged,
7890 * so if it is no longer present we don't need to issue the
7891 * VFLR. Just clean up the AER in that case.
7892 */
7893 if (vfdev) {
7894 e_dev_err("Issuing VFLR to VF %d\n", vf);
7895 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7896 }
7897
7898 pci_cleanup_aer_uncorrect_error_status(pdev);
7899 }
7900
7901 /*
7902 * Even though the error may have occurred on the other port
7903 * we still need to increment the vf error reference count for
7904 * both ports because the I/O resume function will be called
7905 * for both of them.
7906 */
7907 adapter->vferr_refcount++;
7908
7909 return PCI_ERS_RESULT_RECOVERED;
7910
7911skip_bad_vf_detection:
7912#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7913 netif_device_detach(netdev);
7914
3044b8d1
BL		 7915 if (state == pci_channel_io_perm_failure)
7916 return PCI_ERS_RESULT_DISCONNECT;
7917
9a799d71
AK		 7918 if (netif_running(netdev))
7919 ixgbe_down(adapter);
7920 pci_disable_device(pdev);
7921
b4617240 7922 /* Request a slot reset. */
9a799d71
AK		 7923 return PCI_ERS_RESULT_NEED_RESET;
7924}
7925
7926/**
7927 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7928 * @pdev: Pointer to PCI device
7929 *
7930 * Restart the card from scratch, as if from a cold-boot.
7931 */
7932static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7933{
c60fbb00 7934 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7935 pci_ers_result_t result;
7936 int err;
9a799d71 7937
9ce77666 7938 if (pci_enable_device_mem(pdev)) {
396e799c 7939 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7940 result = PCI_ERS_RESULT_DISCONNECT;
7941 } else {
7942 pci_set_master(pdev);
7943 pci_restore_state(pdev);
c0e1f68b 7944 pci_save_state(pdev);
9a799d71 7945
dd4d8ca6 7946 pci_wake_from_d3(pdev, false);
9a799d71 7947
6fabd715 7948 ixgbe_reset(adapter);
88512539 7949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7950 result = PCI_ERS_RESULT_RECOVERED;
7951 }
7952
7953 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7954 if (err) {
849c4542
ET		 7955 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7956 "failed 0x%0x\n", err);
6fabd715
PWJ		 7957 /* non-fatal, continue */
7958 }
9a799d71 7959
6fabd715 7960 return result;
9a799d71
AK		 7961}
7962
7963/**
7964 * ixgbe_io_resume - called when traffic can start flowing again.
7965 * @pdev: Pointer to PCI device
7966 *
7967 * This callback is called when the error recovery driver tells us that
7968 * its OK to resume normal operation.
7969 */
7970static void ixgbe_io_resume(struct pci_dev *pdev)
7971{
c60fbb00
AD		 7972 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7973 struct net_device *netdev = adapter->netdev;
9a799d71 7974
83c61fa9
GR		 7975#ifdef CONFIG_PCI_IOV
7976 if (adapter->vferr_refcount) {
7977 e_info(drv, "Resuming after VF err\n");
7978 adapter->vferr_refcount--;
7979 return;
7980 }
7981
7982#endif
c7ccde0f
AD		 7983 if (netif_running(netdev))
7984 ixgbe_up(adapter);
9a799d71
AK		 7985
7986 netif_device_attach(netdev);
9a799d71
AK		 7987}
7988
7989static struct pci_error_handlers ixgbe_err_handler = {
7990 .error_detected = ixgbe_io_error_detected,
7991 .slot_reset = ixgbe_io_slot_reset,
7992 .resume = ixgbe_io_resume,
7993};
7994
7995static struct pci_driver ixgbe_driver = {
7996 .name = ixgbe_driver_name,
7997 .id_table = ixgbe_pci_tbl,
7998 .probe = ixgbe_probe,
7999 .remove = __devexit_p(ixgbe_remove),
8000#ifdef CONFIG_PM
8001 .suspend = ixgbe_suspend,
8002 .resume = ixgbe_resume,
8003#endif
8004 .shutdown = ixgbe_shutdown,
8005 .err_handler = &ixgbe_err_handler
8006};
8007
8008/**
8009 * ixgbe_init_module - Driver Registration Routine
8010 *
8011 * ixgbe_init_module is the first routine called when the driver is
8012 * loaded. All it does is register with the PCI subsystem.
8013 **/
8014static int __init ixgbe_init_module(void)
8015{
8016 int ret;
c7689578 8017 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8018 pr_info("%s\n", ixgbe_copyright);
9a799d71 8019
5dd2d332 8020#ifdef CONFIG_IXGBE_DCA
bd0362dd 8021 dca_register_notify(&dca_notifier);
bd0362dd 8022#endif
5dd2d332 8023
9a799d71
AK		 8024 ret = pci_register_driver(&ixgbe_driver);
8025 return ret;
8026}
b4617240 8027
9a799d71
AK		 8028module_init(ixgbe_init_module);
8029
8030/**
8031 * ixgbe_exit_module - Driver Exit Cleanup Routine
8032 *
8033 * ixgbe_exit_module is called just before the driver is removed
8034 * from memory.
8035 **/
8036static void __exit ixgbe_exit_module(void)
8037{
5dd2d332 8038#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8039 dca_unregister_notify(&dca_notifier);
8040#endif
9a799d71 8041 pci_unregister_driver(&ixgbe_driver);
1a51502b 8042 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8043}
bd0362dd 8044
5dd2d332 8045#ifdef CONFIG_IXGBE_DCA
bd0362dd 8046static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8047 void *p)
bd0362dd
JC		 8048{
8049 int ret_val;
8050
8051 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8052 __ixgbe_notify_dca);
bd0362dd
JC		 8053
8054 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8055}
b453368d 8056
5dd2d332 8057#endif /* CONFIG_IXGBE_DCA */
849c4542 8058
9a799d71
AK		 8059module_exit(ixgbe_exit_module);
8060
8061/* ixgbe_main.c */
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