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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 58 | #ifdef IXGBE_FCOE |
ea81875a NP |
59 | char ixgbe_default_device_descr[] = |
60 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
61 | #else |
62 | static char ixgbe_default_device_descr[] = | |
63 | "Intel(R) 10 Gigabit Network Connection"; | |
64 | #endif | |
75e3d3c6 | 65 | #define MAJ 3 |
eef4560f DS |
66 | #define MIN 9 |
67 | #define BUILD 15 | |
75e3d3c6 | 68 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 69 | __stringify(BUILD) "-k" |
9c8eb720 | 70 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 71 | static const char ixgbe_copyright[] = |
94971820 | 72 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
73 | |
74 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 75 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 76 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 77 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
78 | }; |
79 | ||
80 | /* ixgbe_pci_tbl - PCI Device ID Table | |
81 | * | |
82 | * Wildcard entries (PCI_ANY_ID) should come last | |
83 | * Last entry must be all 0s | |
84 | * | |
85 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
86 | * Class, Class Mask, private data (not used) } | |
87 | */ | |
a3aa1884 | 88 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
117 | /* required last entry */ |
118 | {0, } | |
119 | }; | |
120 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
121 | ||
5dd2d332 | 122 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 123 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 124 | void *p); |
bd0362dd JC |
125 | static struct notifier_block dca_notifier = { |
126 | .notifier_call = ixgbe_notify_dca, | |
127 | .next = NULL, | |
128 | .priority = 0 | |
129 | }; | |
130 | #endif | |
131 | ||
1cdd1ec8 GR |
132 | #ifdef CONFIG_PCI_IOV |
133 | static unsigned int max_vfs; | |
134 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 135 | MODULE_PARM_DESC(max_vfs, |
6b42a9c5 | 136 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63"); |
1cdd1ec8 GR |
137 | #endif /* CONFIG_PCI_IOV */ |
138 | ||
8ef78adc PWJ |
139 | static unsigned int allow_unsupported_sfp; |
140 | module_param(allow_unsupported_sfp, uint, 0); | |
141 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
142 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
143 | ||
b3f4d599 | 144 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
145 | static int debug = -1; | |
146 | module_param(debug, int, 0); | |
147 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
148 | ||
9a799d71 AK |
149 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
150 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | MODULE_VERSION(DRV_VERSION); | |
153 | ||
7086400d AD |
154 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
155 | { | |
156 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
157 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
158 | schedule_work(&adapter->service_task); | |
159 | } | |
160 | ||
161 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
162 | { | |
163 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
164 | ||
52f33af8 | 165 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
166 | smp_mb__before_clear_bit(); |
167 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
168 | } | |
169 | ||
dcd79aeb TI |
170 | struct ixgbe_reg_info { |
171 | u32 ofs; | |
172 | char *name; | |
173 | }; | |
174 | ||
175 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
176 | ||
177 | /* General Registers */ | |
178 | {IXGBE_CTRL, "CTRL"}, | |
179 | {IXGBE_STATUS, "STATUS"}, | |
180 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
181 | ||
182 | /* Interrupt Registers */ | |
183 | {IXGBE_EICR, "EICR"}, | |
184 | ||
185 | /* RX Registers */ | |
186 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
187 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
188 | {IXGBE_RDLEN(0), "RDLEN"}, | |
189 | {IXGBE_RDH(0), "RDH"}, | |
190 | {IXGBE_RDT(0), "RDT"}, | |
191 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
192 | {IXGBE_RDBAL(0), "RDBAL"}, | |
193 | {IXGBE_RDBAH(0), "RDBAH"}, | |
194 | ||
195 | /* TX Registers */ | |
196 | {IXGBE_TDBAL(0), "TDBAL"}, | |
197 | {IXGBE_TDBAH(0), "TDBAH"}, | |
198 | {IXGBE_TDLEN(0), "TDLEN"}, | |
199 | {IXGBE_TDH(0), "TDH"}, | |
200 | {IXGBE_TDT(0), "TDT"}, | |
201 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
202 | ||
203 | /* List Terminator */ | |
204 | {} | |
205 | }; | |
206 | ||
207 | ||
208 | /* | |
209 | * ixgbe_regdump - register printout routine | |
210 | */ | |
211 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
212 | { | |
213 | int i = 0, j = 0; | |
214 | char rname[16]; | |
215 | u32 regs[64]; | |
216 | ||
217 | switch (reginfo->ofs) { | |
218 | case IXGBE_SRRCTL(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
221 | break; | |
222 | case IXGBE_DCA_RXCTRL(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
225 | break; | |
226 | case IXGBE_RDLEN(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
229 | break; | |
230 | case IXGBE_RDH(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
233 | break; | |
234 | case IXGBE_RDT(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
237 | break; | |
238 | case IXGBE_RXDCTL(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
241 | break; | |
242 | case IXGBE_RDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
245 | break; | |
246 | case IXGBE_RDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDBAL(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
253 | break; | |
254 | case IXGBE_TDBAH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
257 | break; | |
258 | case IXGBE_TDLEN(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
261 | break; | |
262 | case IXGBE_TDH(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
265 | break; | |
266 | case IXGBE_TDT(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
269 | break; | |
270 | case IXGBE_TXDCTL(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
273 | break; | |
274 | default: | |
c7689578 | 275 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
276 | IXGBE_READ_REG(hw, reginfo->ofs)); |
277 | return; | |
278 | } | |
279 | ||
280 | for (i = 0; i < 8; i++) { | |
281 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 282 | pr_err("%-15s", rname); |
dcd79aeb | 283 | for (j = 0; j < 8; j++) |
c7689578 JP |
284 | pr_cont(" %08x", regs[i*8+j]); |
285 | pr_cont("\n"); | |
dcd79aeb TI |
286 | } |
287 | ||
288 | } | |
289 | ||
290 | /* | |
291 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
292 | */ | |
293 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
294 | { | |
295 | struct net_device *netdev = adapter->netdev; | |
296 | struct ixgbe_hw *hw = &adapter->hw; | |
297 | struct ixgbe_reg_info *reginfo; | |
298 | int n = 0; | |
299 | struct ixgbe_ring *tx_ring; | |
729739b7 | 300 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
301 | union ixgbe_adv_tx_desc *tx_desc; |
302 | struct my_u0 { u64 a; u64 b; } *u0; | |
303 | struct ixgbe_ring *rx_ring; | |
304 | union ixgbe_adv_rx_desc *rx_desc; | |
305 | struct ixgbe_rx_buffer *rx_buffer_info; | |
306 | u32 staterr; | |
307 | int i = 0; | |
308 | ||
309 | if (!netif_msg_hw(adapter)) | |
310 | return; | |
311 | ||
312 | /* Print netdevice Info */ | |
313 | if (netdev) { | |
314 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 315 | pr_info("Device Name state " |
dcd79aeb | 316 | "trans_start last_rx\n"); |
c7689578 JP |
317 | pr_info("%-15s %016lX %016lX %016lX\n", |
318 | netdev->name, | |
319 | netdev->state, | |
320 | netdev->trans_start, | |
321 | netdev->last_rx); | |
dcd79aeb TI |
322 | } |
323 | ||
324 | /* Print Registers */ | |
325 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 326 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
327 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
328 | reginfo->name; reginfo++) { | |
329 | ixgbe_regdump(hw, reginfo); | |
330 | } | |
331 | ||
332 | /* Print TX Ring Summary */ | |
333 | if (!netdev || !netif_running(netdev)) | |
334 | goto exit; | |
335 | ||
336 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 337 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
338 | for (n = 0; n < adapter->num_tx_queues; n++) { |
339 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 340 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
d3d00239 | 341 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb | 342 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
343 | (u64)dma_unmap_addr(tx_buffer, dma), |
344 | dma_unmap_len(tx_buffer, len), | |
345 | tx_buffer->next_to_watch, | |
346 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
347 | } |
348 | ||
349 | /* Print TX Rings */ | |
350 | if (!netif_msg_tx_done(adapter)) | |
351 | goto rx_ring_summary; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
354 | ||
355 | /* Transmit Descriptor Formats | |
356 | * | |
357 | * Advanced Transmit Descriptor | |
358 | * +--------------------------------------------------------------+ | |
359 | * 0 | Buffer Address [63:0] | | |
360 | * +--------------------------------------------------------------+ | |
361 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
362 | * +--------------------------------------------------------------+ | |
363 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
364 | */ | |
365 | ||
366 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
367 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
368 | pr_info("------------------------------------\n"); |
369 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
370 | pr_info("------------------------------------\n"); | |
371 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
372 | "[PlPOIdStDDt Ln] [bi->dma ] " |
373 | "leng ntw timestamp bi->skb\n"); | |
374 | ||
375 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 376 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 377 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 378 | u0 = (struct my_u0 *)tx_desc; |
c7689578 | 379 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 380 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
381 | le64_to_cpu(u0->a), |
382 | le64_to_cpu(u0->b), | |
729739b7 AD |
383 | (u64)dma_unmap_addr(tx_buffer, dma), |
384 | dma_unmap_len(tx_buffer, len), | |
385 | tx_buffer->next_to_watch, | |
386 | (u64)tx_buffer->time_stamp, | |
387 | tx_buffer->skb); | |
dcd79aeb TI |
388 | if (i == tx_ring->next_to_use && |
389 | i == tx_ring->next_to_clean) | |
c7689578 | 390 | pr_cont(" NTC/U\n"); |
dcd79aeb | 391 | else if (i == tx_ring->next_to_use) |
c7689578 | 392 | pr_cont(" NTU\n"); |
dcd79aeb | 393 | else if (i == tx_ring->next_to_clean) |
c7689578 | 394 | pr_cont(" NTC\n"); |
dcd79aeb | 395 | else |
c7689578 | 396 | pr_cont("\n"); |
dcd79aeb TI |
397 | |
398 | if (netif_msg_pktdata(adapter) && | |
729739b7 | 399 | dma_unmap_len(tx_buffer, len) != 0) |
dcd79aeb TI |
400 | print_hex_dump(KERN_INFO, "", |
401 | DUMP_PREFIX_ADDRESS, 16, 1, | |
729739b7 AD |
402 | phys_to_virt(dma_unmap_addr(tx_buffer, |
403 | dma)), | |
404 | dma_unmap_len(tx_buffer, len), | |
405 | true); | |
dcd79aeb TI |
406 | } |
407 | } | |
408 | ||
409 | /* Print RX Rings Summary */ | |
410 | rx_ring_summary: | |
411 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 412 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
413 | for (n = 0; n < adapter->num_rx_queues; n++) { |
414 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
415 | pr_info("%5d %5X %5X\n", |
416 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
417 | } |
418 | ||
419 | /* Print RX Rings */ | |
420 | if (!netif_msg_rx_status(adapter)) | |
421 | goto exit; | |
422 | ||
423 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
424 | ||
425 | /* Advanced Receive Descriptor (Read) Format | |
426 | * 63 1 0 | |
427 | * +-----------------------------------------------------+ | |
428 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
429 | * +----------------------------------------------+------+ | |
430 | * 8 | Header Buffer Address [63:1] | DD | | |
431 | * +-----------------------------------------------------+ | |
432 | * | |
433 | * | |
434 | * Advanced Receive Descriptor (Write-Back) Format | |
435 | * | |
436 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
437 | * +------------------------------------------------------+ | |
438 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
439 | * | Checksum Ident | | | | Type | Type | | |
440 | * +------------------------------------------------------+ | |
441 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
442 | * +------------------------------------------------------+ | |
443 | * 63 48 47 32 31 20 19 0 | |
444 | */ | |
445 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
446 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
447 | pr_info("------------------------------------\n"); |
448 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
449 | pr_info("------------------------------------\n"); | |
450 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
451 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
452 | "<-- Adv Rx Read format\n"); | |
c7689578 | 453 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
454 | "[vl er S cks ln] ---------------- [bi->skb] " |
455 | "<-- Adv Rx Write-Back format\n"); | |
456 | ||
457 | for (i = 0; i < rx_ring->count; i++) { | |
458 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 459 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
460 | u0 = (struct my_u0 *)rx_desc; |
461 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
462 | if (staterr & IXGBE_RXD_STAT_DD) { | |
463 | /* Descriptor Done */ | |
c7689578 | 464 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
465 | "%016llX ---------------- %p", i, |
466 | le64_to_cpu(u0->a), | |
467 | le64_to_cpu(u0->b), | |
468 | rx_buffer_info->skb); | |
469 | } else { | |
c7689578 | 470 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
471 | "%016llX %016llX %p", i, |
472 | le64_to_cpu(u0->a), | |
473 | le64_to_cpu(u0->b), | |
474 | (u64)rx_buffer_info->dma, | |
475 | rx_buffer_info->skb); | |
476 | ||
477 | if (netif_msg_pktdata(adapter)) { | |
478 | print_hex_dump(KERN_INFO, "", | |
479 | DUMP_PREFIX_ADDRESS, 16, 1, | |
480 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 481 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
482 | } |
483 | } | |
484 | ||
485 | if (i == rx_ring->next_to_use) | |
c7689578 | 486 | pr_cont(" NTU\n"); |
dcd79aeb | 487 | else if (i == rx_ring->next_to_clean) |
c7689578 | 488 | pr_cont(" NTC\n"); |
dcd79aeb | 489 | else |
c7689578 | 490 | pr_cont("\n"); |
dcd79aeb TI |
491 | |
492 | } | |
493 | } | |
494 | ||
495 | exit: | |
496 | return; | |
497 | } | |
498 | ||
5eba3699 AV |
499 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
500 | { | |
501 | u32 ctrl_ext; | |
502 | ||
503 | /* Let firmware take over control of h/w */ | |
504 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
505 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 506 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
507 | } |
508 | ||
509 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
510 | { | |
511 | u32 ctrl_ext; | |
512 | ||
513 | /* Let firmware know the driver has taken over */ | |
514 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 516 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 517 | } |
9a799d71 | 518 | |
49ce9c2c | 519 | /** |
e8e26350 PW |
520 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
521 | * @adapter: pointer to adapter struct | |
522 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
523 | * @queue: queue to map the corresponding interrupt to | |
524 | * @msix_vector: the vector to map to the corresponding queue | |
525 | * | |
526 | */ | |
527 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 528 | u8 queue, u8 msix_vector) |
9a799d71 AK |
529 | { |
530 | u32 ivar, index; | |
e8e26350 PW |
531 | struct ixgbe_hw *hw = &adapter->hw; |
532 | switch (hw->mac.type) { | |
533 | case ixgbe_mac_82598EB: | |
534 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
535 | if (direction == -1) | |
536 | direction = 0; | |
537 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
538 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
539 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
540 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
541 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
542 | break; | |
543 | case ixgbe_mac_82599EB: | |
b93a2226 | 544 | case ixgbe_mac_X540: |
e8e26350 PW |
545 | if (direction == -1) { |
546 | /* other causes */ | |
547 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
548 | index = ((queue & 1) * 8); | |
549 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
550 | ivar &= ~(0xFF << index); | |
551 | ivar |= (msix_vector << index); | |
552 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
553 | break; | |
554 | } else { | |
555 | /* tx or rx causes */ | |
556 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
557 | index = ((16 * (queue & 1)) + (8 * direction)); | |
558 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
559 | ivar &= ~(0xFF << index); | |
560 | ivar |= (msix_vector << index); | |
561 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
562 | break; | |
563 | } | |
564 | default: | |
565 | break; | |
566 | } | |
9a799d71 AK |
567 | } |
568 | ||
fe49f04a | 569 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 570 | u64 qmask) |
fe49f04a AD |
571 | { |
572 | u32 mask; | |
573 | ||
bd508178 AD |
574 | switch (adapter->hw.mac.type) { |
575 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
576 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
577 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
578 | break; |
579 | case ixgbe_mac_82599EB: | |
b93a2226 | 580 | case ixgbe_mac_X540: |
fe49f04a AD |
581 | mask = (qmask & 0xFFFFFFFF); |
582 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
583 | mask = (qmask >> 32); | |
584 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
585 | break; |
586 | default: | |
587 | break; | |
fe49f04a AD |
588 | } |
589 | } | |
590 | ||
729739b7 AD |
591 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
592 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 593 | { |
729739b7 AD |
594 | if (tx_buffer->skb) { |
595 | dev_kfree_skb_any(tx_buffer->skb); | |
596 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 597 | dma_unmap_single(ring->dev, |
729739b7 AD |
598 | dma_unmap_addr(tx_buffer, dma), |
599 | dma_unmap_len(tx_buffer, len), | |
600 | DMA_TO_DEVICE); | |
601 | } else if (dma_unmap_len(tx_buffer, len)) { | |
602 | dma_unmap_page(ring->dev, | |
603 | dma_unmap_addr(tx_buffer, dma), | |
604 | dma_unmap_len(tx_buffer, len), | |
605 | DMA_TO_DEVICE); | |
e5a43549 | 606 | } |
729739b7 AD |
607 | tx_buffer->next_to_watch = NULL; |
608 | tx_buffer->skb = NULL; | |
609 | dma_unmap_len_set(tx_buffer, len, 0); | |
610 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
611 | } |
612 | ||
943561d3 | 613 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
614 | { |
615 | struct ixgbe_hw *hw = &adapter->hw; | |
616 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 617 | int i; |
943561d3 | 618 | u32 data; |
c84d324c | 619 | |
943561d3 AD |
620 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
621 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
622 | return; | |
c84d324c | 623 | |
943561d3 AD |
624 | switch (hw->mac.type) { |
625 | case ixgbe_mac_82598EB: | |
626 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
627 | break; | |
628 | default: | |
629 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
630 | } | |
631 | hwstats->lxoffrxc += data; | |
c84d324c | 632 | |
943561d3 AD |
633 | /* refill credits (no tx hang) if we received xoff */ |
634 | if (!data) | |
c84d324c | 635 | return; |
943561d3 AD |
636 | |
637 | for (i = 0; i < adapter->num_tx_queues; i++) | |
638 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
639 | &adapter->tx_ring[i]->state); | |
640 | } | |
641 | ||
642 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
643 | { | |
644 | struct ixgbe_hw *hw = &adapter->hw; | |
645 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
646 | u32 xoff[8] = {0}; | |
647 | int i; | |
648 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
649 | ||
650 | if (adapter->ixgbe_ieee_pfc) | |
651 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
652 | ||
653 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
654 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 655 | return; |
943561d3 | 656 | } |
c84d324c JF |
657 | |
658 | /* update stats for each tc, only valid with PFC enabled */ | |
659 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
660 | switch (hw->mac.type) { | |
661 | case ixgbe_mac_82598EB: | |
662 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 663 | break; |
c84d324c JF |
664 | default: |
665 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 666 | } |
c84d324c JF |
667 | hwstats->pxoffrxc[i] += xoff[i]; |
668 | } | |
669 | ||
670 | /* disarm tx queues that have received xoff frames */ | |
671 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
672 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 673 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
674 | |
675 | if (xoff[tc]) | |
676 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 677 | } |
26f23d82 YZ |
678 | } |
679 | ||
c84d324c | 680 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 681 | { |
7d7ce682 | 682 | return ring->stats.packets; |
c84d324c JF |
683 | } |
684 | ||
685 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
686 | { | |
687 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 688 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 689 | |
c84d324c JF |
690 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
691 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
692 | ||
693 | if (head != tail) | |
694 | return (head < tail) ? | |
695 | tail - head : (tail + ring->count - head); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
701 | { | |
702 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
703 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
704 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
705 | bool ret = false; | |
706 | ||
7d637bcc | 707 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
708 | |
709 | /* | |
710 | * Check for a hung queue, but be thorough. This verifies | |
711 | * that a transmit has been completed since the previous | |
712 | * check AND there is at least one packet pending. The | |
713 | * ARMED bit is set to indicate a potential hang. The | |
714 | * bit is cleared if a pause frame is received to remove | |
715 | * false hang detection due to PFC or 802.3x frames. By | |
716 | * requiring this to fail twice we avoid races with | |
717 | * pfc clearing the ARMED bit and conditions where we | |
718 | * run the check_tx_hang logic with a transmit completion | |
719 | * pending but without time to complete it yet. | |
720 | */ | |
721 | if ((tx_done_old == tx_done) && tx_pending) { | |
722 | /* make sure it is true for two checks in a row */ | |
723 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
724 | &tx_ring->state); | |
725 | } else { | |
726 | /* update completed stats and continue */ | |
727 | tx_ring->tx_stats.tx_done_old = tx_done; | |
728 | /* reset the countdown */ | |
729 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
730 | } |
731 | ||
c84d324c | 732 | return ret; |
9a799d71 AK |
733 | } |
734 | ||
c83c6cbd AD |
735 | /** |
736 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
737 | * @adapter: driver private struct | |
738 | **/ | |
739 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
740 | { | |
741 | ||
742 | /* Do the reset outside of interrupt context */ | |
743 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
744 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
745 | ixgbe_service_event_schedule(adapter); | |
746 | } | |
747 | } | |
e01c31a5 | 748 | |
9a799d71 AK |
749 | /** |
750 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 751 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 752 | * @tx_ring: tx ring to clean |
9a799d71 | 753 | **/ |
fe49f04a | 754 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 755 | struct ixgbe_ring *tx_ring) |
9a799d71 | 756 | { |
fe49f04a | 757 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
758 | struct ixgbe_tx_buffer *tx_buffer; |
759 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 760 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 761 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
762 | unsigned int i = tx_ring->next_to_clean; |
763 | ||
764 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
765 | return true; | |
9a799d71 | 766 | |
d3d00239 | 767 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 768 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 769 | i -= tx_ring->count; |
12207e49 | 770 | |
729739b7 | 771 | do { |
d3d00239 AD |
772 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
773 | ||
774 | /* if next_to_watch is not set then there is no work pending */ | |
775 | if (!eop_desc) | |
776 | break; | |
777 | ||
7f83a9e6 AD |
778 | /* prevent any other reads prior to eop_desc */ |
779 | rmb(); | |
780 | ||
d3d00239 AD |
781 | /* if DD is not set pending work has not been completed */ |
782 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
783 | break; | |
8ad494b0 | 784 | |
d3d00239 AD |
785 | /* clear next_to_watch to prevent false hangs */ |
786 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 787 | |
091a6246 AD |
788 | /* update the statistics for this packet */ |
789 | total_bytes += tx_buffer->bytecount; | |
790 | total_packets += tx_buffer->gso_segs; | |
791 | ||
3a6a4eda | 792 | #ifdef CONFIG_IXGBE_PTP |
0ede4a60 JK |
793 | if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP)) |
794 | ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb); | |
3a6a4eda | 795 | #endif |
0ede4a60 | 796 | |
fd0db0ed AD |
797 | /* free the skb */ |
798 | dev_kfree_skb_any(tx_buffer->skb); | |
799 | ||
729739b7 AD |
800 | /* unmap skb header data */ |
801 | dma_unmap_single(tx_ring->dev, | |
802 | dma_unmap_addr(tx_buffer, dma), | |
803 | dma_unmap_len(tx_buffer, len), | |
804 | DMA_TO_DEVICE); | |
805 | ||
fd0db0ed AD |
806 | /* clear tx_buffer data */ |
807 | tx_buffer->skb = NULL; | |
729739b7 | 808 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 809 | |
729739b7 AD |
810 | /* unmap remaining buffers */ |
811 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
812 | tx_buffer++; |
813 | tx_desc++; | |
8ad494b0 | 814 | i++; |
729739b7 AD |
815 | if (unlikely(!i)) { |
816 | i -= tx_ring->count; | |
d3d00239 | 817 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 818 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 819 | } |
e01c31a5 | 820 | |
729739b7 AD |
821 | /* unmap any remaining paged data */ |
822 | if (dma_unmap_len(tx_buffer, len)) { | |
823 | dma_unmap_page(tx_ring->dev, | |
824 | dma_unmap_addr(tx_buffer, dma), | |
825 | dma_unmap_len(tx_buffer, len), | |
826 | DMA_TO_DEVICE); | |
827 | dma_unmap_len_set(tx_buffer, len, 0); | |
828 | } | |
829 | } | |
830 | ||
831 | /* move us one more past the eop_desc for start of next pkt */ | |
832 | tx_buffer++; | |
833 | tx_desc++; | |
834 | i++; | |
835 | if (unlikely(!i)) { | |
836 | i -= tx_ring->count; | |
837 | tx_buffer = tx_ring->tx_buffer_info; | |
838 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
839 | } | |
840 | ||
841 | /* issue prefetch for next Tx descriptor */ | |
842 | prefetch(tx_desc); | |
12207e49 | 843 | |
729739b7 AD |
844 | /* update budget accounting */ |
845 | budget--; | |
846 | } while (likely(budget)); | |
847 | ||
848 | i += tx_ring->count; | |
9a799d71 | 849 | tx_ring->next_to_clean = i; |
d3d00239 | 850 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 851 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 852 | tx_ring->stats.packets += total_packets; |
d3d00239 | 853 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
854 | q_vector->tx.total_bytes += total_bytes; |
855 | q_vector->tx.total_packets += total_packets; | |
b953799e | 856 | |
c84d324c JF |
857 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
858 | /* schedule immediate reset if we believe we hung */ | |
859 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
860 | e_err(drv, "Detected Tx Unit Hang\n" |
861 | " Tx Queue <%d>\n" | |
862 | " TDH, TDT <%x>, <%x>\n" | |
863 | " next_to_use <%x>\n" | |
864 | " next_to_clean <%x>\n" | |
865 | "tx_buffer_info[next_to_clean]\n" | |
866 | " time_stamp <%lx>\n" | |
867 | " jiffies <%lx>\n", | |
868 | tx_ring->queue_index, | |
869 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
870 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
871 | tx_ring->next_to_use, i, |
872 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
873 | |
874 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
875 | ||
876 | e_info(probe, | |
877 | "tx hang %d detected on queue %d, resetting adapter\n", | |
878 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
879 | ||
b953799e | 880 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 881 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
882 | |
883 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 884 | return true; |
b953799e | 885 | } |
9a799d71 | 886 | |
b2d96e0a AD |
887 | netdev_tx_completed_queue(txring_txq(tx_ring), |
888 | total_packets, total_bytes); | |
889 | ||
e092be60 | 890 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 891 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 892 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
893 | /* Make sure that anybody stopping the queue after this |
894 | * sees the new next_to_clean. | |
895 | */ | |
896 | smp_mb(); | |
729739b7 AD |
897 | if (__netif_subqueue_stopped(tx_ring->netdev, |
898 | tx_ring->queue_index) | |
899 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
900 | netif_wake_subqueue(tx_ring->netdev, | |
901 | tx_ring->queue_index); | |
5b7da515 | 902 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 903 | } |
e092be60 | 904 | } |
9a799d71 | 905 | |
59224555 | 906 | return !!budget; |
9a799d71 AK |
907 | } |
908 | ||
5dd2d332 | 909 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
910 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
911 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 912 | int cpu) |
bd0362dd | 913 | { |
33cf09c9 | 914 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
915 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
916 | u16 reg_offset; | |
33cf09c9 | 917 | |
33cf09c9 AD |
918 | switch (hw->mac.type) { |
919 | case ixgbe_mac_82598EB: | |
bdda1a61 | 920 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
921 | break; |
922 | case ixgbe_mac_82599EB: | |
b93a2226 | 923 | case ixgbe_mac_X540: |
bdda1a61 AD |
924 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
925 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
926 | break; |
927 | default: | |
bdda1a61 AD |
928 | /* for unknown hardware do not write register */ |
929 | return; | |
bd0362dd | 930 | } |
bdda1a61 AD |
931 | |
932 | /* | |
933 | * We can enable relaxed ordering for reads, but not writes when | |
934 | * DCA is enabled. This is due to a known issue in some chipsets | |
935 | * which will cause the DCA tag to be cleared. | |
936 | */ | |
937 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
938 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
939 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
940 | ||
941 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
942 | } |
943 | ||
bdda1a61 AD |
944 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
945 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 946 | int cpu) |
bd0362dd | 947 | { |
33cf09c9 | 948 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
949 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
950 | u8 reg_idx = rx_ring->reg_idx; | |
951 | ||
33cf09c9 AD |
952 | |
953 | switch (hw->mac.type) { | |
33cf09c9 | 954 | case ixgbe_mac_82599EB: |
b93a2226 | 955 | case ixgbe_mac_X540: |
bdda1a61 | 956 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
957 | break; |
958 | default: | |
959 | break; | |
960 | } | |
bdda1a61 AD |
961 | |
962 | /* | |
963 | * We can enable relaxed ordering for reads, but not writes when | |
964 | * DCA is enabled. This is due to a known issue in some chipsets | |
965 | * which will cause the DCA tag to be cleared. | |
966 | */ | |
967 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
968 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
969 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
970 | ||
971 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
972 | } |
973 | ||
974 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
975 | { | |
976 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 977 | struct ixgbe_ring *ring; |
bd0362dd | 978 | int cpu = get_cpu(); |
bd0362dd | 979 | |
33cf09c9 AD |
980 | if (q_vector->cpu == cpu) |
981 | goto out_no_update; | |
982 | ||
a557928e | 983 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 984 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 985 | |
a557928e | 986 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 987 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
988 | |
989 | q_vector->cpu = cpu; | |
990 | out_no_update: | |
bd0362dd JC |
991 | put_cpu(); |
992 | } | |
993 | ||
994 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
995 | { | |
996 | int i; | |
997 | ||
998 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
999 | return; | |
1000 | ||
e35ec126 AD |
1001 | /* always use CB2 mode, difference is masked in the CB driver */ |
1002 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1003 | ||
49c7ffbe | 1004 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1005 | adapter->q_vector[i]->cpu = -1; |
1006 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1007 | } |
1008 | } | |
1009 | ||
1010 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1011 | { | |
c60fbb00 | 1012 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1013 | unsigned long event = *(unsigned long *)data; |
1014 | ||
2a72c31e | 1015 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1016 | return 0; |
1017 | ||
bd0362dd JC |
1018 | switch (event) { |
1019 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1020 | /* if we're already enabled, don't do it again */ |
1021 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1022 | break; | |
652f093f | 1023 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1024 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1025 | ixgbe_setup_dca(adapter); |
1026 | break; | |
1027 | } | |
1028 | /* Fall Through since DCA is disabled. */ | |
1029 | case DCA_PROVIDER_REMOVE: | |
1030 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1031 | dca_remove_requester(dev); | |
1032 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1033 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1034 | } | |
1035 | break; | |
1036 | } | |
1037 | ||
652f093f | 1038 | return 0; |
bd0362dd | 1039 | } |
67a74ee2 | 1040 | |
bdda1a61 | 1041 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1042 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1043 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1044 | struct sk_buff *skb) |
1045 | { | |
8a0da21b AD |
1046 | if (ring->netdev->features & NETIF_F_RXHASH) |
1047 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1048 | } |
1049 | ||
f800326d | 1050 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1051 | /** |
1052 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1053 | * @ring: structure containing ring specific data |
ff886dfc AD |
1054 | * @rx_desc: advanced rx descriptor |
1055 | * | |
1056 | * Returns : true if it is FCoE pkt | |
1057 | */ | |
57efd44c | 1058 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1059 | union ixgbe_adv_rx_desc *rx_desc) |
1060 | { | |
1061 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1062 | ||
57efd44c | 1063 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1064 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1065 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1066 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1067 | } | |
1068 | ||
f800326d | 1069 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1070 | /** |
1071 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1072 | * @ring: structure containing ring specific data |
1073 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1074 | * @skb: skb currently being received and modified |
1075 | **/ | |
8a0da21b | 1076 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1077 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1078 | struct sk_buff *skb) |
9a799d71 | 1079 | { |
8a0da21b | 1080 | skb_checksum_none_assert(skb); |
9a799d71 | 1081 | |
712744be | 1082 | /* Rx csum disabled */ |
8a0da21b | 1083 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1084 | return; |
e59bd25d AV |
1085 | |
1086 | /* if IP and error */ | |
f56e0cb1 AD |
1087 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1088 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1089 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1090 | return; |
1091 | } | |
e59bd25d | 1092 | |
f56e0cb1 | 1093 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1094 | return; |
1095 | ||
f56e0cb1 | 1096 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1097 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1098 | |
1099 | /* | |
1100 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1101 | * checksum errors. | |
1102 | */ | |
8a0da21b AD |
1103 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1104 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1105 | return; |
1106 | ||
8a0da21b | 1107 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1108 | return; |
1109 | } | |
1110 | ||
9a799d71 | 1111 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1112 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1113 | } |
1114 | ||
84ea2591 | 1115 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1116 | { |
f56e0cb1 | 1117 | rx_ring->next_to_use = val; |
f800326d AD |
1118 | |
1119 | /* update next to alloc since we have filled the ring */ | |
1120 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1121 | /* |
1122 | * Force memory writes to complete before letting h/w | |
1123 | * know there are new descriptors to fetch. (Only | |
1124 | * applicable for weak-ordered memory model archs, | |
1125 | * such as IA-64). | |
1126 | */ | |
1127 | wmb(); | |
84ea2591 | 1128 | writel(val, rx_ring->tail); |
e8e26350 PW |
1129 | } |
1130 | ||
f990b79b AD |
1131 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1132 | struct ixgbe_rx_buffer *bi) | |
1133 | { | |
1134 | struct page *page = bi->page; | |
f800326d | 1135 | dma_addr_t dma = bi->dma; |
f990b79b | 1136 | |
f800326d AD |
1137 | /* since we are recycling buffers we should seldom need to alloc */ |
1138 | if (likely(dma)) | |
f990b79b AD |
1139 | return true; |
1140 | ||
f800326d AD |
1141 | /* alloc new page for storage */ |
1142 | if (likely(!page)) { | |
8633c084 | 1143 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP, |
f800326d | 1144 | ixgbe_rx_pg_order(rx_ring)); |
f990b79b AD |
1145 | if (unlikely(!page)) { |
1146 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1147 | return false; | |
1148 | } | |
f800326d | 1149 | bi->page = page; |
f990b79b AD |
1150 | } |
1151 | ||
f800326d AD |
1152 | /* map page for use */ |
1153 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1154 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1155 | ||
1156 | /* | |
1157 | * if mapping failed free memory back to system since | |
1158 | * there isn't much point in holding memory we can't use | |
1159 | */ | |
1160 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1161 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f800326d | 1162 | bi->page = NULL; |
f990b79b | 1163 | |
f990b79b AD |
1164 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1165 | return false; | |
1166 | } | |
1167 | ||
f800326d AD |
1168 | bi->dma = dma; |
1169 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1170 | ||
f990b79b AD |
1171 | return true; |
1172 | } | |
1173 | ||
9a799d71 | 1174 | /** |
f990b79b | 1175 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1176 | * @rx_ring: ring to place buffers on |
1177 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1178 | **/ |
fc77dc3c | 1179 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1180 | { |
9a799d71 | 1181 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1182 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1183 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1184 | |
f800326d AD |
1185 | /* nothing to do */ |
1186 | if (!cleaned_count) | |
fc77dc3c AD |
1187 | return; |
1188 | ||
e4f74028 | 1189 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1190 | bi = &rx_ring->rx_buffer_info[i]; |
1191 | i -= rx_ring->count; | |
9a799d71 | 1192 | |
f800326d AD |
1193 | do { |
1194 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1195 | break; |
d5f398ed | 1196 | |
f800326d AD |
1197 | /* |
1198 | * Refresh the desc even if buffer_addrs didn't change | |
1199 | * because each write-back erases this info. | |
1200 | */ | |
1201 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1202 | |
f990b79b AD |
1203 | rx_desc++; |
1204 | bi++; | |
9a799d71 | 1205 | i++; |
f990b79b | 1206 | if (unlikely(!i)) { |
e4f74028 | 1207 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1208 | bi = rx_ring->rx_buffer_info; |
1209 | i -= rx_ring->count; | |
1210 | } | |
1211 | ||
1212 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1213 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1214 | |
1215 | cleaned_count--; | |
1216 | } while (cleaned_count); | |
7c6e0a43 | 1217 | |
f990b79b AD |
1218 | i += rx_ring->count; |
1219 | ||
f56e0cb1 | 1220 | if (rx_ring->next_to_use != i) |
84ea2591 | 1221 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1222 | } |
1223 | ||
1d2024f6 AD |
1224 | /** |
1225 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1226 | * @data: pointer to the start of the headers | |
1227 | * @max_len: total length of section to find headers in | |
1228 | * | |
1229 | * This function is meant to determine the length of headers that will | |
1230 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1231 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1232 | * packets so that we can do basic things like calculating the gso_size | |
1233 | * based on the average data per packet. | |
1234 | **/ | |
1235 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1236 | unsigned int max_len) | |
1237 | { | |
1238 | union { | |
1239 | unsigned char *network; | |
1240 | /* l2 headers */ | |
1241 | struct ethhdr *eth; | |
1242 | struct vlan_hdr *vlan; | |
1243 | /* l3 headers */ | |
1244 | struct iphdr *ipv4; | |
1245 | } hdr; | |
1246 | __be16 protocol; | |
1247 | u8 nexthdr = 0; /* default to not TCP */ | |
1248 | u8 hlen; | |
1249 | ||
1250 | /* this should never happen, but better safe than sorry */ | |
1251 | if (max_len < ETH_HLEN) | |
1252 | return max_len; | |
1253 | ||
1254 | /* initialize network frame pointer */ | |
1255 | hdr.network = data; | |
1256 | ||
1257 | /* set first protocol and move network header forward */ | |
1258 | protocol = hdr.eth->h_proto; | |
1259 | hdr.network += ETH_HLEN; | |
1260 | ||
1261 | /* handle any vlan tag if present */ | |
1262 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1263 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1264 | return max_len; | |
1265 | ||
1266 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1267 | hdr.network += VLAN_HLEN; | |
1268 | } | |
1269 | ||
1270 | /* handle L3 protocols */ | |
1271 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1272 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1273 | return max_len; | |
1274 | ||
1275 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1276 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1277 | ||
1278 | /* verify hlen meets minimum size requirements */ | |
1279 | if (hlen < sizeof(struct iphdr)) | |
1280 | return hdr.network - data; | |
1281 | ||
1282 | /* record next protocol */ | |
1283 | nexthdr = hdr.ipv4->protocol; | |
1284 | hdr.network += hlen; | |
f800326d | 1285 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1286 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1287 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1288 | return max_len; | |
1289 | hdr.network += FCOE_HEADER_LEN; | |
1290 | #endif | |
1291 | } else { | |
1292 | return hdr.network - data; | |
1293 | } | |
1294 | ||
1295 | /* finally sort out TCP */ | |
1296 | if (nexthdr == IPPROTO_TCP) { | |
1297 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1298 | return max_len; | |
1299 | ||
1300 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1301 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1302 | ||
1303 | /* verify hlen meets minimum size requirements */ | |
1304 | if (hlen < sizeof(struct tcphdr)) | |
1305 | return hdr.network - data; | |
1306 | ||
1307 | hdr.network += hlen; | |
1308 | } | |
1309 | ||
1310 | /* | |
1311 | * If everything has gone correctly hdr.network should be the | |
1312 | * data section of the packet and will be the end of the header. | |
1313 | * If not then it probably represents the end of the last recognized | |
1314 | * header. | |
1315 | */ | |
1316 | if ((hdr.network - data) < max_len) | |
1317 | return hdr.network - data; | |
1318 | else | |
1319 | return max_len; | |
1320 | } | |
1321 | ||
4c1975d7 AD |
1322 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1323 | union ixgbe_adv_rx_desc *rx_desc, | |
1324 | struct sk_buff *skb) | |
aa80175a | 1325 | { |
4c1975d7 AD |
1326 | __le32 rsc_enabled; |
1327 | u32 rsc_cnt; | |
1328 | ||
1329 | if (!ring_is_rsc_enabled(rx_ring)) | |
1330 | return; | |
1331 | ||
1332 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1333 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1334 | ||
1335 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1336 | if (!rsc_enabled) | |
1337 | return; | |
1338 | ||
1339 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1340 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1341 | ||
1342 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1343 | } |
43634e82 | 1344 | |
1d2024f6 AD |
1345 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1346 | struct sk_buff *skb) | |
1347 | { | |
f800326d | 1348 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1349 | |
1350 | /* set gso_size to avoid messing up TCP MSS */ | |
1351 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1352 | IXGBE_CB(skb)->append_cnt); | |
1353 | } | |
1354 | ||
1355 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1356 | struct sk_buff *skb) | |
1357 | { | |
1358 | /* if append_cnt is 0 then frame is not RSC */ | |
1359 | if (!IXGBE_CB(skb)->append_cnt) | |
1360 | return; | |
1361 | ||
1362 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1363 | rx_ring->rx_stats.rsc_flush++; | |
1364 | ||
1365 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1366 | ||
1367 | /* gso_size is computed using append_cnt so always clear it last */ | |
1368 | IXGBE_CB(skb)->append_cnt = 0; | |
1369 | } | |
1370 | ||
8a0da21b AD |
1371 | /** |
1372 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1373 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1374 | * @rx_desc: pointer to the EOP Rx descriptor | |
1375 | * @skb: pointer to current skb being populated | |
f8212f97 | 1376 | * |
8a0da21b AD |
1377 | * This function checks the ring, descriptor, and packet information in |
1378 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1379 | * other fields within the skb. | |
f8212f97 | 1380 | **/ |
8a0da21b AD |
1381 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1382 | union ixgbe_adv_rx_desc *rx_desc, | |
1383 | struct sk_buff *skb) | |
f8212f97 | 1384 | { |
43e95f11 JF |
1385 | struct net_device *dev = rx_ring->netdev; |
1386 | ||
8a0da21b AD |
1387 | ixgbe_update_rsc_stats(rx_ring, skb); |
1388 | ||
1389 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1390 | |
8a0da21b AD |
1391 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1392 | ||
3a6a4eda | 1393 | #ifdef CONFIG_IXGBE_PTP |
1d1a79b5 | 1394 | ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
3a6a4eda JK |
1395 | #endif |
1396 | ||
43e95f11 JF |
1397 | if ((dev->features & NETIF_F_HW_VLAN_RX) && |
1398 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
8a0da21b AD |
1399 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
1400 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1401 | } |
1402 | ||
8a0da21b | 1403 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1404 | |
43e95f11 | 1405 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1406 | } |
1407 | ||
8a0da21b AD |
1408 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1409 | struct sk_buff *skb) | |
aa80175a | 1410 | { |
8a0da21b AD |
1411 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1412 | ||
1413 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1414 | napi_gro_receive(&q_vector->napi, skb); | |
1415 | else | |
1416 | netif_rx(skb); | |
aa80175a | 1417 | } |
43634e82 | 1418 | |
f800326d AD |
1419 | /** |
1420 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1421 | * @rx_ring: Rx ring being processed | |
1422 | * @rx_desc: Rx descriptor for current buffer | |
1423 | * @skb: Current socket buffer containing buffer in progress | |
1424 | * | |
1425 | * This function updates next to clean. If the buffer is an EOP buffer | |
1426 | * this function exits returning false, otherwise it will place the | |
1427 | * sk_buff in the next buffer to be chained and return true indicating | |
1428 | * that this is in fact a non-EOP buffer. | |
1429 | **/ | |
1430 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1431 | union ixgbe_adv_rx_desc *rx_desc, | |
1432 | struct sk_buff *skb) | |
1433 | { | |
1434 | u32 ntc = rx_ring->next_to_clean + 1; | |
1435 | ||
1436 | /* fetch, update, and store next to clean */ | |
1437 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1438 | rx_ring->next_to_clean = ntc; | |
1439 | ||
1440 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1441 | ||
1442 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1443 | return false; | |
1444 | ||
1445 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1446 | if (IXGBE_CB(skb)->append_cnt) { | |
1447 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1448 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1449 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1450 | } | |
1451 | ||
1452 | /* place skb in next buffer to be received */ | |
1453 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1454 | rx_ring->rx_stats.non_eop_descs++; | |
1455 | ||
1456 | return true; | |
1457 | } | |
1458 | ||
1459 | /** | |
1460 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1461 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1462 | * @rx_desc: pointer to the EOP Rx descriptor | |
1463 | * @skb: pointer to current skb being fixed | |
1464 | * | |
1465 | * Check for corrupted packet headers caused by senders on the local L2 | |
1466 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1467 | * should be very rare. | |
1468 | * | |
1469 | * Also address the case where we are pulling data in on pages only | |
1470 | * and as such no data is present in the skb header. | |
1471 | * | |
1472 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1473 | * it is large enough to qualify as a valid Ethernet frame. | |
1474 | * | |
1475 | * Returns true if an error was encountered and skb was freed. | |
1476 | **/ | |
1477 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1478 | union ixgbe_adv_rx_desc *rx_desc, | |
1479 | struct sk_buff *skb) | |
1480 | { | |
1481 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1482 | struct net_device *netdev = rx_ring->netdev; | |
1483 | unsigned char *va; | |
1484 | unsigned int pull_len; | |
1485 | ||
1486 | /* if the page was released unmap it, else just sync our portion */ | |
1487 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1488 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1489 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1490 | IXGBE_CB(skb)->page_released = false; | |
1491 | } else { | |
1492 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1493 | IXGBE_CB(skb)->dma, | |
1494 | frag->page_offset, | |
1495 | ixgbe_rx_bufsz(rx_ring), | |
1496 | DMA_FROM_DEVICE); | |
1497 | } | |
1498 | IXGBE_CB(skb)->dma = 0; | |
1499 | ||
1500 | /* verify that the packet does not have any known errors */ | |
1501 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1502 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1503 | !(netdev->features & NETIF_F_RXALL))) { | |
1504 | dev_kfree_skb_any(skb); | |
1505 | return true; | |
1506 | } | |
1507 | ||
1508 | /* | |
1509 | * it is valid to use page_address instead of kmap since we are | |
1510 | * working with pages allocated out of the lomem pool per | |
1511 | * alloc_page(GFP_ATOMIC) | |
1512 | */ | |
1513 | va = skb_frag_address(frag); | |
1514 | ||
1515 | /* | |
1516 | * we need the header to contain the greater of either ETH_HLEN or | |
1517 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1518 | */ | |
1519 | pull_len = skb_frag_size(frag); | |
1520 | if (pull_len > 256) | |
1521 | pull_len = ixgbe_get_headlen(va, pull_len); | |
1522 | ||
1523 | /* align pull length to size of long to optimize memcpy performance */ | |
1524 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1525 | ||
1526 | /* update all of the pointers */ | |
1527 | skb_frag_size_sub(frag, pull_len); | |
1528 | frag->page_offset += pull_len; | |
1529 | skb->data_len -= pull_len; | |
1530 | skb->tail += pull_len; | |
1531 | ||
1532 | /* | |
1533 | * if we sucked the frag empty then we should free it, | |
1534 | * if there are other frags here something is screwed up in hardware | |
1535 | */ | |
1536 | if (skb_frag_size(frag) == 0) { | |
1537 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1538 | skb_shinfo(skb)->nr_frags = 0; | |
1539 | __skb_frag_unref(frag); | |
1540 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1541 | } | |
1542 | ||
57efd44c AD |
1543 | #ifdef IXGBE_FCOE |
1544 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1545 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1546 | return false; | |
1547 | ||
1548 | #endif | |
f800326d AD |
1549 | /* if skb_pad returns an error the skb was freed */ |
1550 | if (unlikely(skb->len < 60)) { | |
1551 | int pad_len = 60 - skb->len; | |
1552 | ||
1553 | if (skb_pad(skb, pad_len)) | |
1554 | return true; | |
1555 | __skb_put(skb, pad_len); | |
1556 | } | |
1557 | ||
1558 | return false; | |
1559 | } | |
1560 | ||
1561 | /** | |
1562 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1563 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1564 | * | |
1565 | * Returns true if page can be reused in another Rx buffer | |
1566 | **/ | |
1567 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1568 | { | |
1569 | struct page *page = rx_buffer->page; | |
1570 | ||
1571 | /* if we are only owner of page and it is local we can reuse it */ | |
1572 | return likely(page_count(page) == 1) && | |
1573 | likely(page_to_nid(page) == numa_node_id()); | |
1574 | } | |
1575 | ||
1576 | /** | |
1577 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1578 | * @rx_ring: rx descriptor ring to store buffers on | |
1579 | * @old_buff: donor buffer to have page reused | |
1580 | * | |
1581 | * Syncronizes page for reuse by the adapter | |
1582 | **/ | |
1583 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1584 | struct ixgbe_rx_buffer *old_buff) | |
1585 | { | |
1586 | struct ixgbe_rx_buffer *new_buff; | |
1587 | u16 nta = rx_ring->next_to_alloc; | |
1588 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1589 | ||
1590 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1591 | ||
1592 | /* update, and store next to alloc */ | |
1593 | nta++; | |
1594 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1595 | ||
1596 | /* transfer page from old buffer to new buffer */ | |
1597 | new_buff->page = old_buff->page; | |
1598 | new_buff->dma = old_buff->dma; | |
1599 | ||
1600 | /* flip page offset to other buffer and store to new_buff */ | |
1601 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1602 | ||
1603 | /* sync the buffer for use by the device */ | |
1604 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1605 | new_buff->page_offset, bufsz, | |
1606 | DMA_FROM_DEVICE); | |
1607 | ||
1608 | /* bump ref count on page before it is given to the stack */ | |
1609 | get_page(new_buff->page); | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1614 | * @rx_ring: rx descriptor ring to transact packets on | |
1615 | * @rx_buffer: buffer containing page to add | |
1616 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1617 | * @skb: sk_buff to place the data into | |
1618 | * | |
1619 | * This function is based on skb_add_rx_frag. I would have used that | |
1620 | * function however it doesn't handle the truesize case correctly since we | |
1621 | * are allocating more memory than might be used for a single receive. | |
1622 | **/ | |
1623 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1624 | struct ixgbe_rx_buffer *rx_buffer, | |
1625 | struct sk_buff *skb, int size) | |
1626 | { | |
1627 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1628 | rx_buffer->page, rx_buffer->page_offset, | |
1629 | size); | |
1630 | skb->len += size; | |
1631 | skb->data_len += size; | |
1632 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1633 | } | |
1634 | ||
1635 | /** | |
1636 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1637 | * @q_vector: structure containing interrupt and ring information | |
1638 | * @rx_ring: rx descriptor ring to transact packets on | |
1639 | * @budget: Total limit on number of packets to process | |
1640 | * | |
1641 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1642 | * processing. The advantage to this is that on systems that have | |
1643 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1644 | * it by maintaining the mapping of the page to the syste. | |
1645 | * | |
1646 | * Returns true if all work is completed without reaching budget | |
1647 | **/ | |
4ff7fb12 | 1648 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1649 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1650 | int budget) |
9a799d71 | 1651 | { |
d2f4fbe2 | 1652 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1653 | #ifdef IXGBE_FCOE |
f800326d | 1654 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1655 | int ddp_bytes = 0; |
1656 | #endif /* IXGBE_FCOE */ | |
f800326d | 1657 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1658 | |
f800326d AD |
1659 | do { |
1660 | struct ixgbe_rx_buffer *rx_buffer; | |
1661 | union ixgbe_adv_rx_desc *rx_desc; | |
1662 | struct sk_buff *skb; | |
1663 | struct page *page; | |
1664 | u16 ntc; | |
1665 | ||
1666 | /* return some buffers to hardware, one at a time is too slow */ | |
1667 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1668 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1669 | cleaned_count = 0; | |
1670 | } | |
1671 | ||
1672 | ntc = rx_ring->next_to_clean; | |
1673 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1674 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1675 | ||
1676 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1677 | break; | |
9a799d71 | 1678 | |
f800326d AD |
1679 | /* |
1680 | * This memory barrier is needed to keep us from reading | |
1681 | * any other fields out of the rx_desc until we know the | |
1682 | * RXD_STAT_DD bit is set | |
1683 | */ | |
1684 | rmb(); | |
9a799d71 | 1685 | |
f800326d AD |
1686 | page = rx_buffer->page; |
1687 | prefetchw(page); | |
9a799d71 | 1688 | |
f800326d | 1689 | skb = rx_buffer->skb; |
c267fc16 | 1690 | |
f800326d AD |
1691 | if (likely(!skb)) { |
1692 | void *page_addr = page_address(page) + | |
1693 | rx_buffer->page_offset; | |
9a799d71 | 1694 | |
f800326d AD |
1695 | /* prefetch first cache line of first page */ |
1696 | prefetch(page_addr); | |
1697 | #if L1_CACHE_BYTES < 128 | |
1698 | prefetch(page_addr + L1_CACHE_BYTES); | |
1699 | #endif | |
1700 | ||
1701 | /* allocate a skb to store the frags */ | |
1702 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1703 | IXGBE_RX_HDR_SIZE); | |
1704 | if (unlikely(!skb)) { | |
1705 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1706 | break; | |
c267fc16 AD |
1707 | } |
1708 | ||
f800326d AD |
1709 | /* |
1710 | * we will be copying header into skb->data in | |
1711 | * pskb_may_pull so it is in our interest to prefetch | |
1712 | * it now to avoid a possible cache miss | |
1713 | */ | |
1714 | prefetchw(skb->data); | |
4c1975d7 AD |
1715 | |
1716 | /* | |
1717 | * Delay unmapping of the first packet. It carries the | |
1718 | * header information, HW may still access the header | |
f800326d AD |
1719 | * after the writeback. Only unmap it when EOP is |
1720 | * reached | |
4c1975d7 | 1721 | */ |
f800326d | 1722 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1723 | } else { |
f800326d AD |
1724 | /* we are reusing so sync this buffer for CPU use */ |
1725 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1726 | rx_buffer->dma, | |
1727 | rx_buffer->page_offset, | |
1728 | ixgbe_rx_bufsz(rx_ring), | |
1729 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1730 | } |
1731 | ||
f800326d AD |
1732 | /* pull page into skb */ |
1733 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1734 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1735 | |
f800326d AD |
1736 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1737 | /* hand second half of page back to the ring */ | |
1738 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1739 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1740 | /* the page has been released from the ring */ | |
1741 | IXGBE_CB(skb)->page_released = true; | |
1742 | } else { | |
1743 | /* we are not reusing the buffer so unmap it */ | |
1744 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1745 | ixgbe_rx_pg_size(rx_ring), | |
1746 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1747 | } |
1748 | ||
f800326d AD |
1749 | /* clear contents of buffer_info */ |
1750 | rx_buffer->skb = NULL; | |
1751 | rx_buffer->dma = 0; | |
1752 | rx_buffer->page = NULL; | |
4c1975d7 | 1753 | |
f800326d | 1754 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1755 | |
9a799d71 | 1756 | cleaned_count++; |
f8212f97 | 1757 | |
f800326d AD |
1758 | /* place incomplete frames back on ring for completion */ |
1759 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1760 | continue; | |
c267fc16 | 1761 | |
f800326d AD |
1762 | /* verify the packet layout is correct */ |
1763 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1764 | continue; | |
9a799d71 | 1765 | |
d2f4fbe2 AV |
1766 | /* probably a little skewed due to removing CRC */ |
1767 | total_rx_bytes += skb->len; | |
1768 | total_rx_packets++; | |
1769 | ||
8a0da21b AD |
1770 | /* populate checksum, timestamp, VLAN, and protocol */ |
1771 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1772 | ||
332d4a7d YZ |
1773 | #ifdef IXGBE_FCOE |
1774 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 1775 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 1776 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1777 | if (!ddp_bytes) { |
1778 | dev_kfree_skb_any(skb); | |
f800326d | 1779 | continue; |
63d635b2 | 1780 | } |
3d8fd385 | 1781 | } |
f800326d | 1782 | |
332d4a7d | 1783 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1784 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1785 | |
f800326d | 1786 | /* update budget accounting */ |
4ff7fb12 | 1787 | budget--; |
f800326d | 1788 | } while (likely(budget)); |
9a799d71 | 1789 | |
3d8fd385 YZ |
1790 | #ifdef IXGBE_FCOE |
1791 | /* include DDPed FCoE data */ | |
1792 | if (ddp_bytes > 0) { | |
1793 | unsigned int mss; | |
1794 | ||
fc77dc3c | 1795 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1796 | sizeof(struct fc_frame_header) - |
1797 | sizeof(struct fcoe_crc_eof); | |
1798 | if (mss > 512) | |
1799 | mss &= ~511; | |
1800 | total_rx_bytes += ddp_bytes; | |
1801 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1802 | } | |
3d8fd385 | 1803 | |
f800326d | 1804 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1805 | u64_stats_update_begin(&rx_ring->syncp); |
1806 | rx_ring->stats.packets += total_rx_packets; | |
1807 | rx_ring->stats.bytes += total_rx_bytes; | |
1808 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1809 | q_vector->rx.total_packets += total_rx_packets; |
1810 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1811 | |
f800326d AD |
1812 | if (cleaned_count) |
1813 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1814 | ||
4ff7fb12 | 1815 | return !!budget; |
9a799d71 AK |
1816 | } |
1817 | ||
9a799d71 AK |
1818 | /** |
1819 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1820 | * @adapter: board private structure | |
1821 | * | |
1822 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1823 | * interrupts. | |
1824 | **/ | |
1825 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1826 | { | |
021230d4 | 1827 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 1828 | int v_idx; |
021230d4 | 1829 | u32 mask; |
9a799d71 | 1830 | |
8e34d1aa AD |
1831 | /* Populate MSIX to EITR Select */ |
1832 | if (adapter->num_vfs > 32) { | |
1833 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1834 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1835 | } | |
1836 | ||
4df10466 JB |
1837 | /* |
1838 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1839 | * corresponding register. |
1840 | */ | |
49c7ffbe | 1841 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 1842 | struct ixgbe_ring *ring; |
7a921c93 | 1843 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1844 | |
a557928e | 1845 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1846 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1847 | ||
a557928e | 1848 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1849 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1850 | ||
d5bf4f67 ET |
1851 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1852 | /* tx only vector */ | |
1853 | if (adapter->tx_itr_setting == 1) | |
1854 | q_vector->itr = IXGBE_10K_ITR; | |
1855 | else | |
1856 | q_vector->itr = adapter->tx_itr_setting; | |
1857 | } else { | |
1858 | /* rx or rx/tx vector */ | |
1859 | if (adapter->rx_itr_setting == 1) | |
1860 | q_vector->itr = IXGBE_20K_ITR; | |
1861 | else | |
1862 | q_vector->itr = adapter->rx_itr_setting; | |
1863 | } | |
021230d4 | 1864 | |
fe49f04a | 1865 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1866 | } |
1867 | ||
bd508178 AD |
1868 | switch (adapter->hw.mac.type) { |
1869 | case ixgbe_mac_82598EB: | |
e8e26350 | 1870 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1871 | v_idx); |
bd508178 AD |
1872 | break; |
1873 | case ixgbe_mac_82599EB: | |
b93a2226 | 1874 | case ixgbe_mac_X540: |
e8e26350 | 1875 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1876 | break; |
bd508178 AD |
1877 | default: |
1878 | break; | |
1879 | } | |
021230d4 AV |
1880 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1881 | ||
41fb9248 | 1882 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1883 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1884 | mask &= ~(IXGBE_EIMS_OTHER | |
1885 | IXGBE_EIMS_MAILBOX | | |
1886 | IXGBE_EIMS_LSC); | |
1887 | ||
021230d4 | 1888 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1889 | } |
1890 | ||
f494e8fa AV |
1891 | enum latency_range { |
1892 | lowest_latency = 0, | |
1893 | low_latency = 1, | |
1894 | bulk_latency = 2, | |
1895 | latency_invalid = 255 | |
1896 | }; | |
1897 | ||
1898 | /** | |
1899 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1900 | * @q_vector: structure containing interrupt and ring information |
1901 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1902 | * |
1903 | * Stores a new ITR value based on packets and byte | |
1904 | * counts during the last interrupt. The advantage of per interrupt | |
1905 | * computation is faster updates and more accurate ITR for the current | |
1906 | * traffic pattern. Constants in this function were computed | |
1907 | * based on theoretical maximum wire speed and thresholds were set based | |
1908 | * on testing data as well as attempting to minimize response time | |
1909 | * while increasing bulk throughput. | |
1910 | * this functionality is controlled by the InterruptThrottleRate module | |
1911 | * parameter (see ixgbe_param.c) | |
1912 | **/ | |
bd198058 AD |
1913 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1914 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1915 | { |
bd198058 AD |
1916 | int bytes = ring_container->total_bytes; |
1917 | int packets = ring_container->total_packets; | |
1918 | u32 timepassed_us; | |
621bd70e | 1919 | u64 bytes_perint; |
bd198058 | 1920 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1921 | |
1922 | if (packets == 0) | |
bd198058 | 1923 | return; |
f494e8fa AV |
1924 | |
1925 | /* simple throttlerate management | |
621bd70e AD |
1926 | * 0-10MB/s lowest (100000 ints/s) |
1927 | * 10-20MB/s low (20000 ints/s) | |
1928 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1929 | */ |
1930 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1931 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1932 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1933 | ||
1934 | switch (itr_setting) { | |
1935 | case lowest_latency: | |
621bd70e | 1936 | if (bytes_perint > 10) |
bd198058 | 1937 | itr_setting = low_latency; |
f494e8fa AV |
1938 | break; |
1939 | case low_latency: | |
621bd70e | 1940 | if (bytes_perint > 20) |
bd198058 | 1941 | itr_setting = bulk_latency; |
621bd70e | 1942 | else if (bytes_perint <= 10) |
bd198058 | 1943 | itr_setting = lowest_latency; |
f494e8fa AV |
1944 | break; |
1945 | case bulk_latency: | |
621bd70e | 1946 | if (bytes_perint <= 20) |
bd198058 | 1947 | itr_setting = low_latency; |
f494e8fa AV |
1948 | break; |
1949 | } | |
1950 | ||
bd198058 AD |
1951 | /* clear work counters since we have the values we need */ |
1952 | ring_container->total_bytes = 0; | |
1953 | ring_container->total_packets = 0; | |
1954 | ||
1955 | /* write updated itr to ring container */ | |
1956 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1957 | } |
1958 | ||
509ee935 JB |
1959 | /** |
1960 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1961 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1962 | * |
1963 | * This function is made to be called by ethtool and by the driver | |
1964 | * when it needs to update EITR registers at runtime. Hardware | |
1965 | * specific quirks/differences are taken care of here. | |
1966 | */ | |
fe49f04a | 1967 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1968 | { |
fe49f04a | 1969 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1970 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1971 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1972 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1973 | |
bd508178 AD |
1974 | switch (adapter->hw.mac.type) { |
1975 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1976 | /* must write high and low 16 bits to reset counter */ |
1977 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1978 | break; |
1979 | case ixgbe_mac_82599EB: | |
b93a2226 | 1980 | case ixgbe_mac_X540: |
509ee935 JB |
1981 | /* |
1982 | * set the WDIS bit to not clear the timer bits and cause an | |
1983 | * immediate assertion of the interrupt | |
1984 | */ | |
1985 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1986 | break; |
1987 | default: | |
1988 | break; | |
509ee935 JB |
1989 | } |
1990 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1991 | } | |
1992 | ||
bd198058 | 1993 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1994 | { |
d5bf4f67 | 1995 | u32 new_itr = q_vector->itr; |
bd198058 | 1996 | u8 current_itr; |
f494e8fa | 1997 | |
bd198058 AD |
1998 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1999 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2000 | |
08c8833b | 2001 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2002 | |
2003 | switch (current_itr) { | |
2004 | /* counts and packets in update_itr are dependent on these numbers */ | |
2005 | case lowest_latency: | |
d5bf4f67 | 2006 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2007 | break; |
2008 | case low_latency: | |
d5bf4f67 | 2009 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2010 | break; |
2011 | case bulk_latency: | |
d5bf4f67 | 2012 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 2013 | break; |
bd198058 AD |
2014 | default: |
2015 | break; | |
f494e8fa AV |
2016 | } |
2017 | ||
d5bf4f67 | 2018 | if (new_itr != q_vector->itr) { |
fe49f04a | 2019 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2020 | new_itr = (10 * new_itr * q_vector->itr) / |
2021 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2022 | |
bd198058 | 2023 | /* save the algorithm value here */ |
5d967eb7 | 2024 | q_vector->itr = new_itr; |
fe49f04a AD |
2025 | |
2026 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2027 | } |
f494e8fa AV |
2028 | } |
2029 | ||
119fc60a | 2030 | /** |
de88eeeb | 2031 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2032 | * @adapter: pointer to adapter |
119fc60a | 2033 | **/ |
f0f9778d | 2034 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2035 | { |
119fc60a MC |
2036 | struct ixgbe_hw *hw = &adapter->hw; |
2037 | u32 eicr = adapter->interrupt_event; | |
2038 | ||
f0f9778d | 2039 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2040 | return; |
2041 | ||
f0f9778d AD |
2042 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2043 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2044 | return; | |
2045 | ||
2046 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2047 | ||
7ca647bd | 2048 | switch (hw->device_id) { |
f0f9778d AD |
2049 | case IXGBE_DEV_ID_82599_T3_LOM: |
2050 | /* | |
2051 | * Since the warning interrupt is for both ports | |
2052 | * we don't have to check if: | |
2053 | * - This interrupt wasn't for our port. | |
2054 | * - We may have missed the interrupt so always have to | |
2055 | * check if we got a LSC | |
2056 | */ | |
2057 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2058 | !(eicr & IXGBE_EICR_LSC)) | |
2059 | return; | |
2060 | ||
2061 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2062 | u32 autoneg; | |
2063 | bool link_up = false; | |
7ca647bd | 2064 | |
7ca647bd JP |
2065 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2066 | ||
f0f9778d AD |
2067 | if (link_up) |
2068 | return; | |
2069 | } | |
2070 | ||
2071 | /* Check if this is not due to overtemp */ | |
2072 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2073 | return; | |
2074 | ||
2075 | break; | |
7ca647bd JP |
2076 | default: |
2077 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2078 | return; |
7ca647bd | 2079 | break; |
119fc60a | 2080 | } |
7ca647bd JP |
2081 | e_crit(drv, |
2082 | "Network adapter has been stopped because it has over heated. " | |
2083 | "Restart the computer. If the problem persists, " | |
2084 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2085 | |
2086 | adapter->interrupt_event = 0; | |
119fc60a MC |
2087 | } |
2088 | ||
0befdb3e JB |
2089 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2090 | { | |
2091 | struct ixgbe_hw *hw = &adapter->hw; | |
2092 | ||
2093 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2094 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2095 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2096 | /* write to clear the interrupt */ |
2097 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2098 | } | |
2099 | } | |
cf8280ee | 2100 | |
4f51bf70 JK |
2101 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2102 | { | |
2103 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2104 | return; | |
2105 | ||
2106 | switch (adapter->hw.mac.type) { | |
2107 | case ixgbe_mac_82599EB: | |
2108 | /* | |
2109 | * Need to check link state so complete overtemp check | |
2110 | * on service task | |
2111 | */ | |
2112 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2113 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2114 | adapter->interrupt_event = eicr; | |
2115 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2116 | ixgbe_service_event_schedule(adapter); | |
2117 | return; | |
2118 | } | |
2119 | return; | |
2120 | case ixgbe_mac_X540: | |
2121 | if (!(eicr & IXGBE_EICR_TS)) | |
2122 | return; | |
2123 | break; | |
2124 | default: | |
2125 | return; | |
2126 | } | |
2127 | ||
2128 | e_crit(drv, | |
2129 | "Network adapter has been stopped because it has over heated. " | |
2130 | "Restart the computer. If the problem persists, " | |
2131 | "power off the system and replace the adapter\n"); | |
2132 | } | |
2133 | ||
e8e26350 PW |
2134 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2135 | { | |
2136 | struct ixgbe_hw *hw = &adapter->hw; | |
2137 | ||
73c4b7cd AD |
2138 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2139 | /* Clear the interrupt */ | |
2140 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2141 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2142 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2143 | ixgbe_service_event_schedule(adapter); | |
2144 | } | |
73c4b7cd AD |
2145 | } |
2146 | ||
e8e26350 PW |
2147 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2148 | /* Clear the interrupt */ | |
2149 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2150 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2151 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2152 | ixgbe_service_event_schedule(adapter); | |
2153 | } | |
e8e26350 PW |
2154 | } |
2155 | } | |
2156 | ||
cf8280ee JB |
2157 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2158 | { | |
2159 | struct ixgbe_hw *hw = &adapter->hw; | |
2160 | ||
2161 | adapter->lsc_int++; | |
2162 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2163 | adapter->link_check_timeout = jiffies; | |
2164 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2165 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2166 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2167 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2168 | } |
2169 | } | |
2170 | ||
fe49f04a AD |
2171 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2172 | u64 qmask) | |
2173 | { | |
2174 | u32 mask; | |
bd508178 | 2175 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2176 | |
bd508178 AD |
2177 | switch (hw->mac.type) { |
2178 | case ixgbe_mac_82598EB: | |
fe49f04a | 2179 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2180 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2181 | break; | |
2182 | case ixgbe_mac_82599EB: | |
b93a2226 | 2183 | case ixgbe_mac_X540: |
fe49f04a | 2184 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2185 | if (mask) |
2186 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2187 | mask = (qmask >> 32); |
bd508178 AD |
2188 | if (mask) |
2189 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2190 | break; | |
2191 | default: | |
2192 | break; | |
fe49f04a AD |
2193 | } |
2194 | /* skip the flush */ | |
2195 | } | |
2196 | ||
2197 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2198 | u64 qmask) |
fe49f04a AD |
2199 | { |
2200 | u32 mask; | |
bd508178 | 2201 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2202 | |
bd508178 AD |
2203 | switch (hw->mac.type) { |
2204 | case ixgbe_mac_82598EB: | |
fe49f04a | 2205 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2206 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2207 | break; | |
2208 | case ixgbe_mac_82599EB: | |
b93a2226 | 2209 | case ixgbe_mac_X540: |
fe49f04a | 2210 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2211 | if (mask) |
2212 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2213 | mask = (qmask >> 32); |
bd508178 AD |
2214 | if (mask) |
2215 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2216 | break; | |
2217 | default: | |
2218 | break; | |
fe49f04a AD |
2219 | } |
2220 | /* skip the flush */ | |
2221 | } | |
2222 | ||
021230d4 | 2223 | /** |
2c4af694 AD |
2224 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2225 | * @adapter: board private structure | |
021230d4 | 2226 | **/ |
2c4af694 AD |
2227 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2228 | bool flush) | |
9a799d71 | 2229 | { |
2c4af694 | 2230 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2231 | |
2c4af694 AD |
2232 | /* don't reenable LSC while waiting for link */ |
2233 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2234 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2235 | |
2c4af694 | 2236 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2237 | switch (adapter->hw.mac.type) { |
2238 | case ixgbe_mac_82599EB: | |
2239 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2240 | break; | |
2241 | case ixgbe_mac_X540: | |
2242 | mask |= IXGBE_EIMS_TS; | |
2243 | break; | |
2244 | default: | |
2245 | break; | |
2246 | } | |
2c4af694 AD |
2247 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2248 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2249 | switch (adapter->hw.mac.type) { | |
2250 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2251 | mask |= IXGBE_EIMS_GPI_SDP1; |
2252 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2253 | case ixgbe_mac_X540: |
2254 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2255 | mask |= IXGBE_EIMS_MAILBOX; |
2256 | break; | |
2257 | default: | |
2258 | break; | |
9a799d71 | 2259 | } |
2c4af694 AD |
2260 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2261 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2262 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2263 | |
2c4af694 AD |
2264 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2265 | if (queues) | |
2266 | ixgbe_irq_enable_queues(adapter, ~0); | |
2267 | if (flush) | |
2268 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2269 | } |
2270 | ||
2c4af694 | 2271 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2272 | { |
a65151ba | 2273 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2274 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2275 | u32 eicr; |
91281fd3 | 2276 | |
54037505 DS |
2277 | /* |
2278 | * Workaround for Silicon errata. Use clear-by-write instead | |
2279 | * of clear-by-read. Reading with EICS will return the | |
2280 | * interrupt causes without clearing, which later be done | |
2281 | * with the write to EICR. | |
2282 | */ | |
2283 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2284 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2285 | |
cf8280ee JB |
2286 | if (eicr & IXGBE_EICR_LSC) |
2287 | ixgbe_check_lsc(adapter); | |
f0848276 | 2288 | |
1cdd1ec8 GR |
2289 | if (eicr & IXGBE_EICR_MAILBOX) |
2290 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2291 | |
bd508178 AD |
2292 | switch (hw->mac.type) { |
2293 | case ixgbe_mac_82599EB: | |
b93a2226 | 2294 | case ixgbe_mac_X540: |
2c4af694 AD |
2295 | if (eicr & IXGBE_EICR_ECC) |
2296 | e_info(link, "Received unrecoverable ECC Err, please " | |
2297 | "reboot\n"); | |
c4cf55e5 PWJ |
2298 | /* Handle Flow Director Full threshold interrupt */ |
2299 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2300 | int reinit_count = 0; |
c4cf55e5 | 2301 | int i; |
c4cf55e5 | 2302 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2303 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2304 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2305 | &ring->state)) |
2306 | reinit_count++; | |
2307 | } | |
2308 | if (reinit_count) { | |
2309 | /* no more flow director interrupts until after init */ | |
2310 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2311 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2312 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2313 | } |
2314 | } | |
f0f9778d | 2315 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2316 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2317 | break; |
2318 | default: | |
2319 | break; | |
c4cf55e5 | 2320 | } |
f0848276 | 2321 | |
bd508178 | 2322 | ixgbe_check_fan_failure(adapter, eicr); |
681ae1ad JK |
2323 | #ifdef CONFIG_IXGBE_PTP |
2324 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
2325 | #endif | |
efe3d3c8 | 2326 | |
7086400d | 2327 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2328 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2329 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2330 | |
9a799d71 | 2331 | return IRQ_HANDLED; |
f0848276 | 2332 | } |
91281fd3 | 2333 | |
4ff7fb12 | 2334 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2335 | { |
021230d4 | 2336 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2337 | |
9b471446 | 2338 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2339 | |
4ff7fb12 AD |
2340 | if (q_vector->rx.ring || q_vector->tx.ring) |
2341 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2342 | |
9a799d71 | 2343 | return IRQ_HANDLED; |
91281fd3 AD |
2344 | } |
2345 | ||
eb01b975 AD |
2346 | /** |
2347 | * ixgbe_poll - NAPI Rx polling callback | |
2348 | * @napi: structure for representing this polling device | |
2349 | * @budget: how many packets driver is allowed to clean | |
2350 | * | |
2351 | * This function is used for legacy and MSI, NAPI mode | |
2352 | **/ | |
8af3c33f | 2353 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2354 | { |
2355 | struct ixgbe_q_vector *q_vector = | |
2356 | container_of(napi, struct ixgbe_q_vector, napi); | |
2357 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2358 | struct ixgbe_ring *ring; | |
2359 | int per_ring_budget; | |
2360 | bool clean_complete = true; | |
2361 | ||
2362 | #ifdef CONFIG_IXGBE_DCA | |
2363 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2364 | ixgbe_update_dca(q_vector); | |
2365 | #endif | |
2366 | ||
2367 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2368 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2369 | ||
2370 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2371 | * the budget to go below 1 because we'll exit polling */ | |
2372 | if (q_vector->rx.count > 1) | |
2373 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2374 | else | |
2375 | per_ring_budget = budget; | |
2376 | ||
2377 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2378 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2379 | per_ring_budget); | |
2380 | ||
2381 | /* If all work not completed, return budget and keep polling */ | |
2382 | if (!clean_complete) | |
2383 | return budget; | |
2384 | ||
2385 | /* all work done, exit the polling mode */ | |
2386 | napi_complete(napi); | |
2387 | if (adapter->rx_itr_setting & 1) | |
2388 | ixgbe_set_itr(q_vector); | |
2389 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2390 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
021230d4 AV |
2395 | /** |
2396 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2397 | * @adapter: board private structure | |
2398 | * | |
2399 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2400 | * interrupts from the kernel. | |
2401 | **/ | |
2402 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2403 | { | |
2404 | struct net_device *netdev = adapter->netdev; | |
207867f5 | 2405 | int vector, err; |
e8e9f696 | 2406 | int ri = 0, ti = 0; |
021230d4 | 2407 | |
49c7ffbe | 2408 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 2409 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2410 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2411 | |
4ff7fb12 | 2412 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2413 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2414 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2415 | ti++; | |
2416 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2417 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2418 | "%s-%s-%d", netdev->name, "rx", ri++); |
2419 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2420 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2421 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2422 | } else { |
2423 | /* skip this unused q_vector */ | |
2424 | continue; | |
32aa77a4 | 2425 | } |
207867f5 AD |
2426 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2427 | q_vector->name, q_vector); | |
9a799d71 | 2428 | if (err) { |
396e799c | 2429 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2430 | "Error: %d\n", err); |
021230d4 | 2431 | goto free_queue_irqs; |
9a799d71 | 2432 | } |
207867f5 AD |
2433 | /* If Flow Director is enabled, set interrupt affinity */ |
2434 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2435 | /* assign the mask for this irq */ | |
2436 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2437 | &q_vector->affinity_mask); |
207867f5 | 2438 | } |
9a799d71 AK |
2439 | } |
2440 | ||
021230d4 | 2441 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2442 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2443 | if (err) { |
de88eeeb | 2444 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2445 | goto free_queue_irqs; |
9a799d71 AK |
2446 | } |
2447 | ||
9a799d71 AK |
2448 | return 0; |
2449 | ||
021230d4 | 2450 | free_queue_irqs: |
207867f5 AD |
2451 | while (vector) { |
2452 | vector--; | |
2453 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2454 | NULL); | |
2455 | free_irq(adapter->msix_entries[vector].vector, | |
2456 | adapter->q_vector[vector]); | |
2457 | } | |
021230d4 AV |
2458 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2459 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2460 | kfree(adapter->msix_entries); |
2461 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2462 | return err; |
2463 | } | |
2464 | ||
2465 | /** | |
021230d4 | 2466 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2467 | * @irq: interrupt number |
2468 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2469 | **/ |
2470 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2471 | { | |
a65151ba | 2472 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2473 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2474 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2475 | u32 eicr; |
2476 | ||
54037505 | 2477 | /* |
24ddd967 | 2478 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2479 | * before the read of EICR. |
2480 | */ | |
2481 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2482 | ||
021230d4 | 2483 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2484 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2485 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2486 | if (!eicr) { |
6af3b9eb ET |
2487 | /* |
2488 | * shared interrupt alert! | |
f47cf66e | 2489 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2490 | * have disabled interrupts due to EIAM |
2491 | * finish the workaround of silicon errata on 82598. Unmask | |
2492 | * the interrupt that we masked before the EICR read. | |
2493 | */ | |
2494 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2495 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2496 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2497 | } |
9a799d71 | 2498 | |
cf8280ee JB |
2499 | if (eicr & IXGBE_EICR_LSC) |
2500 | ixgbe_check_lsc(adapter); | |
021230d4 | 2501 | |
bd508178 AD |
2502 | switch (hw->mac.type) { |
2503 | case ixgbe_mac_82599EB: | |
e8e26350 | 2504 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2505 | /* Fall through */ |
2506 | case ixgbe_mac_X540: | |
2507 | if (eicr & IXGBE_EICR_ECC) | |
2508 | e_info(link, "Received unrecoverable ECC err, please " | |
2509 | "reboot\n"); | |
4f51bf70 | 2510 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2511 | break; |
2512 | default: | |
2513 | break; | |
2514 | } | |
e8e26350 | 2515 | |
0befdb3e | 2516 | ixgbe_check_fan_failure(adapter, eicr); |
681ae1ad JK |
2517 | #ifdef CONFIG_IXGBE_PTP |
2518 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
2519 | #endif | |
0befdb3e | 2520 | |
b9f6ed2b AD |
2521 | /* would disable interrupts here but EIAM disabled it */ |
2522 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2523 | |
6af3b9eb ET |
2524 | /* |
2525 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2526 | * ixgbe_poll will re-enable the queue interrupts | |
2527 | */ | |
6af3b9eb ET |
2528 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2529 | ixgbe_irq_enable(adapter, false, false); | |
2530 | ||
9a799d71 AK |
2531 | return IRQ_HANDLED; |
2532 | } | |
2533 | ||
2534 | /** | |
2535 | * ixgbe_request_irq - initialize interrupts | |
2536 | * @adapter: board private structure | |
2537 | * | |
2538 | * Attempts to configure interrupts using the best available | |
2539 | * capabilities of the hardware and kernel. | |
2540 | **/ | |
021230d4 | 2541 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2542 | { |
2543 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2544 | int err; |
9a799d71 | 2545 | |
4cc6df29 | 2546 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2547 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2548 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2549 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2550 | netdev->name, adapter); |
4cc6df29 | 2551 | else |
a0607fd3 | 2552 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2553 | netdev->name, adapter); |
9a799d71 | 2554 | |
de88eeeb | 2555 | if (err) |
396e799c | 2556 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2557 | |
9a799d71 AK |
2558 | return err; |
2559 | } | |
2560 | ||
2561 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2562 | { | |
49c7ffbe | 2563 | int vector; |
9a799d71 | 2564 | |
49c7ffbe AD |
2565 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2566 | free_irq(adapter->pdev->irq, adapter); | |
2567 | return; | |
2568 | } | |
4cc6df29 | 2569 | |
49c7ffbe AD |
2570 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
2571 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
2572 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 2573 | |
49c7ffbe AD |
2574 | /* free only the irqs that were actually requested */ |
2575 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
2576 | continue; | |
207867f5 | 2577 | |
49c7ffbe AD |
2578 | /* clear the affinity_mask in the IRQ descriptor */ |
2579 | irq_set_affinity_hint(entry->vector, NULL); | |
2580 | ||
2581 | free_irq(entry->vector, q_vector); | |
9a799d71 | 2582 | } |
49c7ffbe AD |
2583 | |
2584 | free_irq(adapter->msix_entries[vector++].vector, adapter); | |
9a799d71 AK |
2585 | } |
2586 | ||
22d5a71b JB |
2587 | /** |
2588 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2589 | * @adapter: board private structure | |
2590 | **/ | |
2591 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2592 | { | |
bd508178 AD |
2593 | switch (adapter->hw.mac.type) { |
2594 | case ixgbe_mac_82598EB: | |
835462fc | 2595 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2596 | break; |
2597 | case ixgbe_mac_82599EB: | |
b93a2226 | 2598 | case ixgbe_mac_X540: |
835462fc NS |
2599 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2600 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2601 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2602 | break; |
2603 | default: | |
2604 | break; | |
22d5a71b JB |
2605 | } |
2606 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2607 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
2608 | int vector; |
2609 | ||
2610 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
2611 | synchronize_irq(adapter->msix_entries[vector].vector); | |
2612 | ||
2613 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
2614 | } else { |
2615 | synchronize_irq(adapter->pdev->irq); | |
2616 | } | |
2617 | } | |
2618 | ||
9a799d71 AK |
2619 | /** |
2620 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2621 | * | |
2622 | **/ | |
2623 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2624 | { | |
d5bf4f67 | 2625 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2626 | |
d5bf4f67 ET |
2627 | /* rx/tx vector */ |
2628 | if (adapter->rx_itr_setting == 1) | |
2629 | q_vector->itr = IXGBE_20K_ITR; | |
2630 | else | |
2631 | q_vector->itr = adapter->rx_itr_setting; | |
2632 | ||
2633 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2634 | |
e8e26350 PW |
2635 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2636 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2637 | |
396e799c | 2638 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2639 | } |
2640 | ||
43e69bf0 AD |
2641 | /** |
2642 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2643 | * @adapter: board private structure | |
2644 | * @ring: structure containing ring specific data | |
2645 | * | |
2646 | * Configure the Tx descriptor ring after a reset. | |
2647 | **/ | |
84418e3b AD |
2648 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2649 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2650 | { |
2651 | struct ixgbe_hw *hw = &adapter->hw; | |
2652 | u64 tdba = ring->dma; | |
2f1860b8 | 2653 | int wait_loop = 10; |
b88c6de2 | 2654 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2655 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2656 | |
2f1860b8 | 2657 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2658 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2659 | IXGBE_WRITE_FLUSH(hw); |
2660 | ||
43e69bf0 | 2661 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2662 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2663 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2664 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2665 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2666 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2667 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2668 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2669 | |
b88c6de2 AD |
2670 | /* |
2671 | * set WTHRESH to encourage burst writeback, it should not be set | |
2672 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2673 | * | |
2674 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2675 | * to or less than the number of on chip descriptors, which is | |
2676 | * currently 40. | |
2677 | */ | |
e954b374 | 2678 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2679 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2680 | else | |
2681 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2682 | ||
e954b374 AD |
2683 | /* |
2684 | * Setting PTHRESH to 32 both improves performance | |
2685 | * and avoids a TX hang with DFP enabled | |
2686 | */ | |
b88c6de2 AD |
2687 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2688 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2689 | |
2690 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2691 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2692 | adapter->atr_sample_rate) { | |
2693 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2694 | ring->atr_count = 0; | |
2695 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2696 | } else { | |
2697 | ring->atr_sample_rate = 0; | |
2698 | } | |
2f1860b8 | 2699 | |
c84d324c JF |
2700 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2701 | ||
2f1860b8 | 2702 | /* enable queue */ |
2f1860b8 AD |
2703 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2704 | ||
2705 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2706 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2707 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2708 | return; | |
2709 | ||
2710 | /* poll to verify queue is enabled */ | |
2711 | do { | |
032b4325 | 2712 | usleep_range(1000, 2000); |
2f1860b8 AD |
2713 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2714 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2715 | if (!wait_loop) | |
2716 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2717 | } |
2718 | ||
120ff942 AD |
2719 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2720 | { | |
2721 | struct ixgbe_hw *hw = &adapter->hw; | |
671c0adb | 2722 | u32 rttdcs, mtqc; |
8b1c0b24 | 2723 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2724 | |
2725 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2726 | return; | |
2727 | ||
2728 | /* disable the arbiter while setting MTQC */ | |
2729 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2730 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2731 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2732 | ||
2733 | /* set transmit pool layout */ | |
671c0adb AD |
2734 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
2735 | mtqc = IXGBE_MTQC_VT_ENA; | |
2736 | if (tcs > 4) | |
2737 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
2738 | else if (tcs > 1) | |
2739 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2740 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
2741 | mtqc |= IXGBE_MTQC_32VF; | |
2742 | else | |
2743 | mtqc |= IXGBE_MTQC_64VF; | |
2744 | } else { | |
2745 | if (tcs > 4) | |
2746 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
2747 | else if (tcs > 1) | |
2748 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
8b1c0b24 | 2749 | else |
671c0adb AD |
2750 | mtqc = IXGBE_MTQC_64Q_1PB; |
2751 | } | |
120ff942 | 2752 | |
671c0adb | 2753 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
120ff942 | 2754 | |
671c0adb AD |
2755 | /* Enable Security TX Buffer IFG for multiple pb */ |
2756 | if (tcs) { | |
2757 | u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2758 | sectx |= IXGBE_SECTX_DCB; | |
2759 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); | |
120ff942 AD |
2760 | } |
2761 | ||
2762 | /* re-enable the arbiter */ | |
2763 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2764 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2765 | } | |
2766 | ||
9a799d71 | 2767 | /** |
3a581073 | 2768 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2769 | * @adapter: board private structure |
2770 | * | |
2771 | * Configure the Tx unit of the MAC after a reset. | |
2772 | **/ | |
2773 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2774 | { | |
2f1860b8 AD |
2775 | struct ixgbe_hw *hw = &adapter->hw; |
2776 | u32 dmatxctl; | |
43e69bf0 | 2777 | u32 i; |
9a799d71 | 2778 | |
2f1860b8 AD |
2779 | ixgbe_setup_mtqc(adapter); |
2780 | ||
2781 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2782 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2783 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2784 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2785 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2786 | } | |
2787 | ||
9a799d71 | 2788 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2789 | for (i = 0; i < adapter->num_tx_queues; i++) |
2790 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2791 | } |
2792 | ||
3ebe8fde AD |
2793 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
2794 | struct ixgbe_ring *ring) | |
2795 | { | |
2796 | struct ixgbe_hw *hw = &adapter->hw; | |
2797 | u8 reg_idx = ring->reg_idx; | |
2798 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2799 | ||
2800 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
2801 | ||
2802 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2803 | } | |
2804 | ||
2805 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
2806 | struct ixgbe_ring *ring) | |
2807 | { | |
2808 | struct ixgbe_hw *hw = &adapter->hw; | |
2809 | u8 reg_idx = ring->reg_idx; | |
2810 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2811 | ||
2812 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
2813 | ||
2814 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2815 | } | |
2816 | ||
2817 | #ifdef CONFIG_IXGBE_DCB | |
2818 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2819 | #else | |
2820 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2821 | #endif | |
2822 | { | |
2823 | int i; | |
2824 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
2825 | ||
2826 | if (adapter->ixgbe_ieee_pfc) | |
2827 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
2828 | ||
2829 | /* | |
2830 | * We should set the drop enable bit if: | |
2831 | * SR-IOV is enabled | |
2832 | * or | |
2833 | * Number of Rx queues > 1 and flow control is disabled | |
2834 | * | |
2835 | * This allows us to avoid head of line blocking for security | |
2836 | * and performance reasons. | |
2837 | */ | |
2838 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
2839 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
2840 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2841 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
2842 | } else { | |
2843 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2844 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
2845 | } | |
2846 | } | |
2847 | ||
e8e26350 | 2848 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2849 | |
a6616b42 | 2850 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2851 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2852 | { |
45e9baa5 | 2853 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 2854 | u32 srrctl; |
bf29ee6c | 2855 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2856 | |
45e9baa5 AD |
2857 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2858 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 2859 | |
45e9baa5 AD |
2860 | /* |
2861 | * if VMDq is not active we must program one srrctl register | |
2862 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
2863 | */ | |
2864 | reg_idx &= mask; | |
2865 | } | |
cc41ac7c | 2866 | |
45e9baa5 AD |
2867 | /* configure header buffer length, needed for RSC */ |
2868 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 2869 | |
45e9baa5 | 2870 | /* configure the packet buffer length */ |
f800326d AD |
2871 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2872 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2873 | #else |
f800326d | 2874 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2875 | #endif |
45e9baa5 AD |
2876 | |
2877 | /* configure descriptor type */ | |
f800326d | 2878 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2879 | |
45e9baa5 | 2880 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2881 | } |
9a799d71 | 2882 | |
05abb126 | 2883 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2884 | { |
05abb126 AD |
2885 | struct ixgbe_hw *hw = &adapter->hw; |
2886 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2887 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2888 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2889 | u32 mrqc = 0, reta = 0; |
2890 | u32 rxcsum; | |
2891 | int i, j; | |
671c0adb AD |
2892 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2893 | ||
2894 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
2895 | rss_i = 1; | |
86b4db3b | 2896 | |
671c0adb AD |
2897 | /* |
2898 | * Program table for at least 2 queues w/ SR-IOV so that VFs can | |
2899 | * make full use of any rings they may have. We will use the | |
2900 | * PSRTYPE register to control how many rings we use within the PF. | |
2901 | */ | |
2902 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) | |
2903 | rss_i = 2; | |
0cefafad | 2904 | |
05abb126 AD |
2905 | /* Fill out hash function seeds */ |
2906 | for (i = 0; i < 10; i++) | |
2907 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2908 | ||
2909 | /* Fill out redirection table */ | |
2910 | for (i = 0, j = 0; i < 128; i++, j++) { | |
671c0adb | 2911 | if (j == rss_i) |
05abb126 AD |
2912 | j = 0; |
2913 | /* reta = 4-byte sliding window of | |
2914 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2915 | reta = (reta << 8) | (j * 0x11); | |
2916 | if ((i & 3) == 3) | |
2917 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2918 | } | |
0cefafad | 2919 | |
05abb126 AD |
2920 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2921 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2922 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2923 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2924 | ||
671c0adb AD |
2925 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2926 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
2927 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 2928 | } else { |
671c0adb AD |
2929 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
2930 | ||
2931 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
2932 | if (tcs > 4) | |
2933 | mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ | |
2934 | else if (tcs > 1) | |
2935 | mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ | |
2936 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
2937 | mrqc = IXGBE_MRQC_VMDQRSS32EN; | |
8b1c0b24 | 2938 | else |
671c0adb AD |
2939 | mrqc = IXGBE_MRQC_VMDQRSS64EN; |
2940 | } else { | |
2941 | if (tcs > 4) | |
8b1c0b24 | 2942 | mrqc = IXGBE_MRQC_RTRSS8TCEN; |
671c0adb AD |
2943 | else if (tcs > 1) |
2944 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2945 | else | |
2946 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 2947 | } |
0cefafad JB |
2948 | } |
2949 | ||
05abb126 | 2950 | /* Perform hash on these packet types */ |
671c0adb AD |
2951 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2952 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | | |
2953 | IXGBE_MRQC_RSS_FIELD_IPV6 | | |
2954 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
05abb126 | 2955 | |
ef6afc0c AD |
2956 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
2957 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; | |
2958 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) | |
2959 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
2960 | ||
05abb126 | 2961 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
0cefafad JB |
2962 | } |
2963 | ||
bb5a9ad2 NS |
2964 | /** |
2965 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2966 | * @adapter: address of board private structure | |
2967 | * @index: index of ring to set | |
bb5a9ad2 | 2968 | **/ |
082757af | 2969 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2970 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2971 | { |
bb5a9ad2 | 2972 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2973 | u32 rscctrl; |
bf29ee6c | 2974 | u8 reg_idx = ring->reg_idx; |
7367096a | 2975 | |
7d637bcc | 2976 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2977 | return; |
bb5a9ad2 | 2978 | |
7367096a | 2979 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2980 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2981 | /* | |
2982 | * we must limit the number of descriptors so that the | |
2983 | * total size of max desc * buf_len is not greater | |
642c680e | 2984 | * than 65536 |
bb5a9ad2 | 2985 | */ |
f800326d AD |
2986 | #if (PAGE_SIZE <= 8192) |
2987 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2988 | #elif (PAGE_SIZE <= 16384) | |
2989 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2990 | #else |
f800326d | 2991 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2992 | #endif |
7367096a | 2993 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2994 | } |
2995 | ||
9e10e045 AD |
2996 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2997 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2998 | struct ixgbe_ring *ring) | |
2999 | { | |
3000 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3001 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3002 | u32 rxdctl; | |
bf29ee6c | 3003 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
3004 | |
3005 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3006 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3007 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3008 | return; | |
3009 | ||
3010 | do { | |
032b4325 | 3011 | usleep_range(1000, 2000); |
9e10e045 AD |
3012 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3013 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3014 | ||
3015 | if (!wait_loop) { | |
3016 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3017 | "the polling period\n", reg_idx); | |
3018 | } | |
3019 | } | |
3020 | ||
2d39d576 YZ |
3021 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3022 | struct ixgbe_ring *ring) | |
3023 | { | |
3024 | struct ixgbe_hw *hw = &adapter->hw; | |
3025 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3026 | u32 rxdctl; | |
3027 | u8 reg_idx = ring->reg_idx; | |
3028 | ||
3029 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3030 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3031 | ||
3032 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3033 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3034 | ||
3035 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3036 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3037 | return; | |
3038 | ||
3039 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3040 | do { | |
3041 | udelay(10); | |
3042 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3043 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3044 | ||
3045 | if (!wait_loop) { | |
3046 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3047 | "the polling period\n", reg_idx); | |
3048 | } | |
3049 | } | |
3050 | ||
84418e3b AD |
3051 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3052 | struct ixgbe_ring *ring) | |
acd37177 AD |
3053 | { |
3054 | struct ixgbe_hw *hw = &adapter->hw; | |
3055 | u64 rdba = ring->dma; | |
9e10e045 | 3056 | u32 rxdctl; |
bf29ee6c | 3057 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3058 | |
9e10e045 AD |
3059 | /* disable queue to avoid issues while updating state */ |
3060 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3061 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3062 | |
acd37177 AD |
3063 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3064 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3065 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3066 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3067 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3068 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3069 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3070 | |
3071 | ixgbe_configure_srrctl(adapter, ring); | |
3072 | ixgbe_configure_rscctl(adapter, ring); | |
3073 | ||
e9f98072 GR |
3074 | /* If operating in IOV mode set RLPML for X540 */ |
3075 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3076 | hw->mac.type == ixgbe_mac_X540) { | |
3077 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3078 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3079 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3080 | } | |
3081 | ||
9e10e045 AD |
3082 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3083 | /* | |
3084 | * enable cache line friendly hardware writes: | |
3085 | * PTHRESH=32 descriptors (half the internal cache), | |
3086 | * this also removes ugly rx_no_buffer_count increment | |
3087 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3088 | * WTHRESH=8 burst writeback up to two cache lines | |
3089 | */ | |
3090 | rxdctl &= ~0x3FFFFF; | |
3091 | rxdctl |= 0x080420; | |
3092 | } | |
3093 | ||
3094 | /* enable receive descriptor ring */ | |
3095 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3096 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3097 | ||
3098 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3099 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3100 | } |
3101 | ||
48654521 AD |
3102 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3103 | { | |
3104 | struct ixgbe_hw *hw = &adapter->hw; | |
3105 | int p; | |
3106 | ||
3107 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3108 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3109 | IXGBE_PSRTYPE_UDPHDR | |
3110 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3111 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3112 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3113 | |
3114 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3115 | return; | |
3116 | ||
671c0adb AD |
3117 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
3118 | int rss_i = adapter->ring_feature[RING_F_RSS].indices; | |
3119 | if (rss_i > 3) | |
3120 | psrtype |= 2 << 29; | |
3121 | else if (rss_i > 1) | |
3122 | psrtype |= 1 << 29; | |
3123 | } | |
48654521 AD |
3124 | |
3125 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3126 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3127 | psrtype); | |
3128 | } | |
3129 | ||
f5b4a52e AD |
3130 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3131 | { | |
3132 | struct ixgbe_hw *hw = &adapter->hw; | |
f5b4a52e | 3133 | u32 reg_offset, vf_shift; |
435b19f6 | 3134 | u32 gcr_ext, vmdctl; |
de4c7f65 | 3135 | int i; |
f5b4a52e AD |
3136 | |
3137 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3138 | return; | |
3139 | ||
3140 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
435b19f6 AD |
3141 | vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; |
3142 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
3143 | vmdctl |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3144 | vmdctl |= IXGBE_VT_CTL_REPLEN; | |
3145 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
f5b4a52e AD |
3146 | |
3147 | vf_shift = adapter->num_vfs % 32; | |
4cd6923d | 3148 | reg_offset = (adapter->num_vfs >= 32) ? 1 : 0; |
f5b4a52e AD |
3149 | |
3150 | /* Enable only the PF's pool for Tx/Rx */ | |
435b19f6 AD |
3151 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); |
3152 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); | |
3153 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); | |
3154 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); | |
f5b4a52e AD |
3155 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); |
3156 | ||
3157 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3158 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3159 | ||
3160 | /* | |
3161 | * Set up VF register offsets for selected VT Mode, | |
3162 | * i.e. 32 or 64 VFs for SR-IOV | |
3163 | */ | |
73079ea0 AD |
3164 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { |
3165 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3166 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; | |
3167 | break; | |
3168 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3169 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; | |
3170 | break; | |
3171 | default: | |
3172 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; | |
3173 | break; | |
3174 | } | |
3175 | ||
f5b4a52e AD |
3176 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); |
3177 | ||
3178 | /* enable Tx loopback for VF/PF communication */ | |
3179 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
435b19f6 | 3180 | |
a985b6c3 | 3181 | /* Enable MAC Anti-Spoofing */ |
435b19f6 | 3182 | hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), |
a985b6c3 | 3183 | adapter->num_vfs); |
de4c7f65 GR |
3184 | /* For VFs that have spoof checking turned off */ |
3185 | for (i = 0; i < adapter->num_vfs; i++) { | |
3186 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3187 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3188 | } | |
f5b4a52e AD |
3189 | } |
3190 | ||
477de6ed | 3191 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3192 | { |
9a799d71 AK |
3193 | struct ixgbe_hw *hw = &adapter->hw; |
3194 | struct net_device *netdev = adapter->netdev; | |
3195 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3196 | struct ixgbe_ring *rx_ring; |
3197 | int i; | |
3198 | u32 mhadd, hlreg0; | |
48654521 | 3199 | |
63f39bd1 | 3200 | #ifdef IXGBE_FCOE |
477de6ed AD |
3201 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3202 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3203 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3204 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3205 | |
477de6ed AD |
3206 | #endif /* IXGBE_FCOE */ |
3207 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3208 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3209 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3210 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3211 | ||
3212 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3213 | } | |
3214 | ||
919e78a6 AD |
3215 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3216 | max_frame += VLAN_HLEN; | |
3217 | ||
477de6ed AD |
3218 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3219 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3220 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3221 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3222 | |
0cefafad JB |
3223 | /* |
3224 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3225 | * the Base and Length of the Rx Descriptor Ring | |
3226 | */ | |
9a799d71 | 3227 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3228 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3229 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3230 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3231 | else |
7d637bcc | 3232 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3233 | } |
477de6ed AD |
3234 | } |
3235 | ||
7367096a AD |
3236 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3237 | { | |
3238 | struct ixgbe_hw *hw = &adapter->hw; | |
3239 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3240 | ||
3241 | switch (hw->mac.type) { | |
3242 | case ixgbe_mac_82598EB: | |
3243 | /* | |
3244 | * For VMDq support of different descriptor types or | |
3245 | * buffer sizes through the use of multiple SRRCTL | |
3246 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3247 | * | |
3248 | * also, the manual doesn't mention it clearly but DCA hints | |
3249 | * will only use queue 0's tags unless this bit is set. Side | |
3250 | * effects of setting this bit are only that SRRCTL must be | |
3251 | * fully programmed [0..15] | |
3252 | */ | |
3253 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3254 | break; | |
3255 | case ixgbe_mac_82599EB: | |
b93a2226 | 3256 | case ixgbe_mac_X540: |
7367096a AD |
3257 | /* Disable RSC for ACK packets */ |
3258 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3259 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3260 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3261 | /* hardware requires some bits to be set by default */ | |
3262 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3263 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3264 | break; | |
3265 | default: | |
3266 | /* We should do nothing since we don't know this hardware */ | |
3267 | return; | |
3268 | } | |
3269 | ||
3270 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3271 | } | |
3272 | ||
477de6ed AD |
3273 | /** |
3274 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3275 | * @adapter: board private structure | |
3276 | * | |
3277 | * Configure the Rx unit of the MAC after a reset. | |
3278 | **/ | |
3279 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3280 | { | |
3281 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3282 | int i; |
3283 | u32 rxctrl; | |
477de6ed AD |
3284 | |
3285 | /* disable receives while setting up the descriptors */ | |
3286 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3287 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3288 | ||
3289 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3290 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3291 | |
9e10e045 | 3292 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3293 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3294 | |
477de6ed AD |
3295 | /* set_rx_buffer_len must be called before ring initialization */ |
3296 | ixgbe_set_rx_buffer_len(adapter); | |
3297 | ||
3298 | /* | |
3299 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3300 | * the Base and Length of the Rx Descriptor Ring | |
3301 | */ | |
9e10e045 AD |
3302 | for (i = 0; i < adapter->num_rx_queues; i++) |
3303 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3304 | |
9e10e045 AD |
3305 | /* disable drop enable for 82598 parts */ |
3306 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3307 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3308 | ||
3309 | /* enable all receives */ | |
3310 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3311 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3312 | } |
3313 | ||
8e586137 | 3314 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3315 | { |
3316 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3317 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3318 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3319 | |
3320 | /* add VID to filter table */ | |
1ada1b1b | 3321 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3322 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3323 | |
3324 | return 0; | |
068c89b0 DS |
3325 | } |
3326 | ||
8e586137 | 3327 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3328 | { |
3329 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3330 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3331 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3332 | |
068c89b0 | 3333 | /* remove VID from filter table */ |
1ada1b1b | 3334 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3335 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3336 | |
3337 | return 0; | |
068c89b0 DS |
3338 | } |
3339 | ||
5f6c0181 JB |
3340 | /** |
3341 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3342 | * @adapter: driver data | |
3343 | */ | |
3344 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3345 | { | |
3346 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3347 | u32 vlnctrl; |
3348 | ||
3349 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3350 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3351 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3352 | } | |
3353 | ||
3354 | /** | |
3355 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3356 | * @adapter: driver data | |
3357 | */ | |
3358 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3359 | { | |
3360 | struct ixgbe_hw *hw = &adapter->hw; | |
3361 | u32 vlnctrl; | |
3362 | ||
3363 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3364 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3365 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3366 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3367 | } | |
3368 | ||
3369 | /** | |
3370 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3371 | * @adapter: driver data | |
3372 | */ | |
3373 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3374 | { | |
3375 | struct ixgbe_hw *hw = &adapter->hw; | |
3376 | u32 vlnctrl; | |
5f6c0181 JB |
3377 | int i, j; |
3378 | ||
3379 | switch (hw->mac.type) { | |
3380 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3381 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3382 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3383 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3384 | break; | |
3385 | case ixgbe_mac_82599EB: | |
b93a2226 | 3386 | case ixgbe_mac_X540: |
5f6c0181 JB |
3387 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3388 | j = adapter->rx_ring[i]->reg_idx; | |
3389 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3390 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3391 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3392 | } | |
3393 | break; | |
3394 | default: | |
3395 | break; | |
3396 | } | |
3397 | } | |
3398 | ||
3399 | /** | |
f62bbb5e | 3400 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3401 | * @adapter: driver data |
3402 | */ | |
f62bbb5e | 3403 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3404 | { |
3405 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3406 | u32 vlnctrl; |
5f6c0181 JB |
3407 | int i, j; |
3408 | ||
3409 | switch (hw->mac.type) { | |
3410 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3411 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3412 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3413 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3414 | break; | |
3415 | case ixgbe_mac_82599EB: | |
b93a2226 | 3416 | case ixgbe_mac_X540: |
5f6c0181 JB |
3417 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3418 | j = adapter->rx_ring[i]->reg_idx; | |
3419 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3420 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3421 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3422 | } | |
3423 | break; | |
3424 | default: | |
3425 | break; | |
3426 | } | |
3427 | } | |
3428 | ||
9a799d71 AK |
3429 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3430 | { | |
f62bbb5e | 3431 | u16 vid; |
9a799d71 | 3432 | |
f62bbb5e JG |
3433 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3434 | ||
3435 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3436 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3437 | } |
3438 | ||
2850062a AD |
3439 | /** |
3440 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3441 | * @netdev: network interface device structure | |
3442 | * | |
3443 | * Writes unicast address list to the RAR table. | |
3444 | * Returns: -ENOMEM on failure/insufficient address space | |
3445 | * 0 on no addresses written | |
3446 | * X on writing X addresses to the RAR table | |
3447 | **/ | |
3448 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3449 | { | |
3450 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3451 | struct ixgbe_hw *hw = &adapter->hw; | |
3452 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3453 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3454 | int count = 0; |
3455 | ||
3456 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3457 | if (netdev_uc_count(netdev) > rar_entries) | |
3458 | return -ENOMEM; | |
3459 | ||
3460 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3461 | struct netdev_hw_addr *ha; | |
3462 | /* return error if we do not support writing to RAR table */ | |
3463 | if (!hw->mac.ops.set_rar) | |
3464 | return -ENOMEM; | |
3465 | ||
3466 | netdev_for_each_uc_addr(ha, netdev) { | |
3467 | if (!rar_entries) | |
3468 | break; | |
3469 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3470 | vfn, IXGBE_RAH_AV); | |
3471 | count++; | |
3472 | } | |
3473 | } | |
3474 | /* write the addresses in reverse order to avoid write combining */ | |
3475 | for (; rar_entries > 0 ; rar_entries--) | |
3476 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3477 | ||
3478 | return count; | |
3479 | } | |
3480 | ||
9a799d71 | 3481 | /** |
2c5645cf | 3482 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3483 | * @netdev: network interface device structure |
3484 | * | |
2c5645cf CL |
3485 | * The set_rx_method entry point is called whenever the unicast/multicast |
3486 | * address list or the network interface flags are updated. This routine is | |
3487 | * responsible for configuring the hardware for proper unicast, multicast and | |
3488 | * promiscuous mode. | |
9a799d71 | 3489 | **/ |
7f870475 | 3490 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3491 | { |
3492 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3493 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3494 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3495 | int count; | |
9a799d71 AK |
3496 | |
3497 | /* Check for Promiscuous and All Multicast modes */ | |
3498 | ||
3499 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3500 | ||
f5dc442b | 3501 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3502 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3503 | fctrl |= IXGBE_FCTRL_BAM; |
3504 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3505 | fctrl |= IXGBE_FCTRL_PMCF; | |
3506 | ||
2850062a AD |
3507 | /* clear the bits we are changing the status of */ |
3508 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3509 | ||
9a799d71 | 3510 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3511 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3512 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3513 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3514 | /* don't hardware filter vlans in promisc mode */ |
3515 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3516 | } else { |
746b9f02 PM |
3517 | if (netdev->flags & IFF_ALLMULTI) { |
3518 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3519 | vmolr |= IXGBE_VMOLR_MPE; |
3520 | } else { | |
3521 | /* | |
3522 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3523 | * then we should just turn on promiscuous mode so |
2850062a AD |
3524 | * that we can at least receive multicast traffic |
3525 | */ | |
3526 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3527 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3528 | } |
5f6c0181 | 3529 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3530 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
3531 | } |
3532 | ||
3533 | /* | |
3534 | * Write addresses to available RAR registers, if there is not | |
3535 | * sufficient space to store all the addresses then enable | |
3536 | * unicast promiscuous mode | |
3537 | */ | |
3538 | count = ixgbe_write_uc_addr_list(netdev); | |
3539 | if (count < 0) { | |
3540 | fctrl |= IXGBE_FCTRL_UPE; | |
3541 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
3542 | } |
3543 | ||
2850062a | 3544 | if (adapter->num_vfs) { |
1cdd1ec8 | 3545 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3546 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3547 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3548 | IXGBE_VMOLR_ROPE); | |
3549 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3550 | } | |
3551 | ||
3f2d1c0f BG |
3552 | /* This is useful for sniffing bad packets. */ |
3553 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3554 | /* UPE and MPE will be handled by normal PROMISC logic | |
3555 | * in e1000e_set_rx_mode */ | |
3556 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3557 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3558 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3559 | ||
3560 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3561 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3562 | } | |
3563 | ||
2850062a | 3564 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3565 | |
3566 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3567 | ixgbe_vlan_strip_enable(adapter); | |
3568 | else | |
3569 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3570 | } |
3571 | ||
021230d4 AV |
3572 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3573 | { | |
3574 | int q_idx; | |
021230d4 | 3575 | |
49c7ffbe AD |
3576 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3577 | napi_enable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3578 | } |
3579 | ||
3580 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3581 | { | |
3582 | int q_idx; | |
021230d4 | 3583 | |
49c7ffbe AD |
3584 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3585 | napi_disable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3586 | } |
3587 | ||
7a6b6f51 | 3588 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 3589 | /** |
2f90b865 AD |
3590 | * ixgbe_configure_dcb - Configure DCB hardware |
3591 | * @adapter: ixgbe adapter struct | |
3592 | * | |
3593 | * This is called by the driver on open to configure the DCB hardware. | |
3594 | * This is also called by the gennetlink interface when reconfiguring | |
3595 | * the DCB state. | |
3596 | */ | |
3597 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3598 | { | |
3599 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3600 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3601 | |
67ebd791 AD |
3602 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3603 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3604 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3605 | return; | |
3606 | } | |
3607 | ||
3608 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3609 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3610 | ||
2f90b865 | 3611 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3612 | |
971060b1 | 3613 | #ifdef IXGBE_FCOE |
b120818e JF |
3614 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3615 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3616 | #endif |
b120818e JF |
3617 | |
3618 | /* reconfigure the hardware */ | |
3619 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3620 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3621 | DCB_TX_CONFIG); | |
3622 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3623 | DCB_RX_CONFIG); | |
3624 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3625 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3626 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3627 | adapter->ixgbe_ieee_ets, | |
3628 | max_frame); | |
3629 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3630 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3631 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3632 | } |
8187cd48 JF |
3633 | |
3634 | /* Enable RSS Hash per TC */ | |
3635 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4ae63730 AD |
3636 | u32 msb = 0; |
3637 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; | |
8187cd48 | 3638 | |
d411a936 AD |
3639 | while (rss_i) { |
3640 | msb++; | |
3641 | rss_i >>= 1; | |
3642 | } | |
8187cd48 | 3643 | |
4ae63730 AD |
3644 | /* write msb to all 8 TCs in one write */ |
3645 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); | |
8187cd48 | 3646 | } |
2f90b865 | 3647 | } |
9da712d2 JF |
3648 | #endif |
3649 | ||
3650 | /* Additional bittime to account for IXGBE framing */ | |
3651 | #define IXGBE_ETH_FRAMING 20 | |
3652 | ||
49ce9c2c | 3653 | /** |
9da712d2 JF |
3654 | * ixgbe_hpbthresh - calculate high water mark for flow control |
3655 | * | |
3656 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3657 | * @pb: packet buffer to calculate |
9da712d2 JF |
3658 | */ |
3659 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3660 | { | |
3661 | struct ixgbe_hw *hw = &adapter->hw; | |
3662 | struct net_device *dev = adapter->netdev; | |
3663 | int link, tc, kb, marker; | |
3664 | u32 dv_id, rx_pba; | |
3665 | ||
3666 | /* Calculate max LAN frame size */ | |
3667 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3668 | ||
3669 | #ifdef IXGBE_FCOE | |
3670 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
3671 | if ((dev->features & NETIF_F_FCOE_MTU) && |
3672 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
3673 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
3674 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 JF |
3675 | |
3676 | #endif | |
9da712d2 JF |
3677 | /* Calculate delay value for device */ |
3678 | switch (hw->mac.type) { | |
3679 | case ixgbe_mac_X540: | |
3680 | dv_id = IXGBE_DV_X540(link, tc); | |
3681 | break; | |
3682 | default: | |
3683 | dv_id = IXGBE_DV(link, tc); | |
3684 | break; | |
3685 | } | |
3686 | ||
3687 | /* Loopback switch introduces additional latency */ | |
3688 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3689 | dv_id += IXGBE_B2BT(tc); | |
3690 | ||
3691 | /* Delay value is calculated in bit times convert to KB */ | |
3692 | kb = IXGBE_BT2KB(dv_id); | |
3693 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3694 | ||
3695 | marker = rx_pba - kb; | |
3696 | ||
3697 | /* It is possible that the packet buffer is not large enough | |
3698 | * to provide required headroom. In this case throw an error | |
3699 | * to user and a do the best we can. | |
3700 | */ | |
3701 | if (marker < 0) { | |
3702 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3703 | "headroom to support flow control." | |
3704 | "Decrease MTU or number of traffic classes\n", pb); | |
3705 | marker = tc + 1; | |
3706 | } | |
3707 | ||
3708 | return marker; | |
3709 | } | |
3710 | ||
49ce9c2c | 3711 | /** |
9da712d2 JF |
3712 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
3713 | * | |
3714 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3715 | * @pb: packet buffer to calculate |
9da712d2 JF |
3716 | */ |
3717 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3718 | { | |
3719 | struct ixgbe_hw *hw = &adapter->hw; | |
3720 | struct net_device *dev = adapter->netdev; | |
3721 | int tc; | |
3722 | u32 dv_id; | |
3723 | ||
3724 | /* Calculate max LAN frame size */ | |
3725 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3726 | ||
3727 | /* Calculate delay value for device */ | |
3728 | switch (hw->mac.type) { | |
3729 | case ixgbe_mac_X540: | |
3730 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3731 | break; | |
3732 | default: | |
3733 | dv_id = IXGBE_LOW_DV(tc); | |
3734 | break; | |
3735 | } | |
3736 | ||
3737 | /* Delay value is calculated in bit times convert to KB */ | |
3738 | return IXGBE_BT2KB(dv_id); | |
3739 | } | |
3740 | ||
3741 | /* | |
3742 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3743 | */ | |
3744 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3745 | { | |
3746 | struct ixgbe_hw *hw = &adapter->hw; | |
3747 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3748 | int i; | |
3749 | ||
3750 | if (!num_tc) | |
3751 | num_tc = 1; | |
3752 | ||
3753 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3754 | ||
3755 | for (i = 0; i < num_tc; i++) { | |
3756 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3757 | ||
3758 | /* Low water marks must not be larger than high water marks */ | |
3759 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3760 | hw->fc.low_water = 0; | |
3761 | } | |
3762 | } | |
3763 | ||
80605c65 JF |
3764 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3765 | { | |
80605c65 | 3766 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3767 | int hdrm; |
3768 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3769 | |
3770 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3771 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3772 | hdrm = 32 << adapter->fdir_pballoc; |
3773 | else | |
3774 | hdrm = 0; | |
80605c65 | 3775 | |
f7e1027f | 3776 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3777 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3778 | } |
3779 | ||
e4911d57 AD |
3780 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3781 | { | |
3782 | struct ixgbe_hw *hw = &adapter->hw; | |
3783 | struct hlist_node *node, *node2; | |
3784 | struct ixgbe_fdir_filter *filter; | |
3785 | ||
3786 | spin_lock(&adapter->fdir_perfect_lock); | |
3787 | ||
3788 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3789 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3790 | ||
3791 | hlist_for_each_entry_safe(filter, node, node2, | |
3792 | &adapter->fdir_filter_list, fdir_node) { | |
3793 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3794 | &filter->filter, |
3795 | filter->sw_idx, | |
3796 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3797 | IXGBE_FDIR_DROP_QUEUE : | |
3798 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3799 | } |
3800 | ||
3801 | spin_unlock(&adapter->fdir_perfect_lock); | |
3802 | } | |
3803 | ||
9a799d71 AK |
3804 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3805 | { | |
d2f5e7f3 AS |
3806 | struct ixgbe_hw *hw = &adapter->hw; |
3807 | ||
80605c65 | 3808 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3809 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3810 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3811 | #endif |
9a799d71 | 3812 | |
4c1d7b4b | 3813 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3814 | ixgbe_restore_vlan(adapter); |
3815 | ||
eacd73f7 YZ |
3816 | #ifdef IXGBE_FCOE |
3817 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3818 | ixgbe_configure_fcoe(adapter); | |
3819 | ||
3820 | #endif /* IXGBE_FCOE */ | |
d2f5e7f3 AS |
3821 | |
3822 | switch (hw->mac.type) { | |
3823 | case ixgbe_mac_82599EB: | |
3824 | case ixgbe_mac_X540: | |
3825 | hw->mac.ops.disable_rx_buff(hw); | |
3826 | break; | |
3827 | default: | |
3828 | break; | |
3829 | } | |
3830 | ||
c4cf55e5 | 3831 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3832 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3833 | adapter->fdir_pballoc); | |
e4911d57 AD |
3834 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3835 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3836 | adapter->fdir_pballoc); | |
3837 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3838 | } |
4c1d7b4b | 3839 | |
d2f5e7f3 AS |
3840 | switch (hw->mac.type) { |
3841 | case ixgbe_mac_82599EB: | |
3842 | case ixgbe_mac_X540: | |
3843 | hw->mac.ops.enable_rx_buff(hw); | |
3844 | break; | |
3845 | default: | |
3846 | break; | |
3847 | } | |
3848 | ||
933d41f1 | 3849 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3850 | |
9a799d71 AK |
3851 | ixgbe_configure_tx(adapter); |
3852 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3853 | } |
3854 | ||
e8e26350 PW |
3855 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3856 | { | |
3857 | switch (hw->phy.type) { | |
3858 | case ixgbe_phy_sfp_avago: | |
3859 | case ixgbe_phy_sfp_ftl: | |
3860 | case ixgbe_phy_sfp_intel: | |
3861 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3862 | case ixgbe_phy_sfp_passive_tyco: |
3863 | case ixgbe_phy_sfp_passive_unknown: | |
3864 | case ixgbe_phy_sfp_active_unknown: | |
3865 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3866 | return true; |
8917b447 AD |
3867 | case ixgbe_phy_nl: |
3868 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3869 | return true; | |
e8e26350 PW |
3870 | default: |
3871 | return false; | |
3872 | } | |
3873 | } | |
3874 | ||
0ecc061d | 3875 | /** |
e8e26350 PW |
3876 | * ixgbe_sfp_link_config - set up SFP+ link |
3877 | * @adapter: pointer to private adapter struct | |
3878 | **/ | |
3879 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3880 | { | |
7086400d | 3881 | /* |
52f33af8 | 3882 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3883 | * is that an SFP was inserted/removed after the reset |
3884 | * but before SFP detection was enabled. As such the best | |
3885 | * solution is to just start searching as soon as we start | |
3886 | */ | |
3887 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3888 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3889 | |
7086400d | 3890 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3891 | } |
3892 | ||
3893 | /** | |
3894 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3895 | * @hw: pointer to private hardware struct |
3896 | * | |
3897 | * Returns 0 on success, negative on failure | |
3898 | **/ | |
e8e26350 | 3899 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3900 | { |
3901 | u32 autoneg; | |
8620a103 | 3902 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3903 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3904 | ||
3905 | if (hw->mac.ops.check_link) | |
3906 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3907 | ||
3908 | if (ret) | |
3909 | goto link_cfg_out; | |
3910 | ||
0b0c2b31 ET |
3911 | autoneg = hw->phy.autoneg_advertised; |
3912 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3913 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3914 | &negotiation); | |
0ecc061d PWJ |
3915 | if (ret) |
3916 | goto link_cfg_out; | |
3917 | ||
8620a103 MC |
3918 | if (hw->mac.ops.setup_link) |
3919 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3920 | link_cfg_out: |
3921 | return ret; | |
3922 | } | |
3923 | ||
a34bcfff | 3924 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3925 | { |
9a799d71 | 3926 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3927 | u32 gpie = 0; |
9a799d71 | 3928 | |
9b471446 | 3929 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3930 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3931 | IXGBE_GPIE_OCD; | |
3932 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3933 | /* |
3934 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3935 | * this saves a register write for every interrupt | |
3936 | */ | |
3937 | switch (hw->mac.type) { | |
3938 | case ixgbe_mac_82598EB: | |
3939 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3940 | break; | |
9b471446 | 3941 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3942 | case ixgbe_mac_X540: |
3943 | default: | |
9b471446 JB |
3944 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3945 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3946 | break; | |
3947 | } | |
3948 | } else { | |
021230d4 AV |
3949 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3950 | * specifically only auto mask tx and rx interrupts */ | |
3951 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3952 | } | |
9a799d71 | 3953 | |
a34bcfff AD |
3954 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3955 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3956 | ||
3957 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3958 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
73079ea0 AD |
3959 | |
3960 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { | |
3961 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3962 | gpie |= IXGBE_GPIE_VTMODE_16; | |
3963 | break; | |
3964 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3965 | gpie |= IXGBE_GPIE_VTMODE_32; | |
3966 | break; | |
3967 | default: | |
3968 | gpie |= IXGBE_GPIE_VTMODE_64; | |
3969 | break; | |
3970 | } | |
119fc60a MC |
3971 | } |
3972 | ||
5fdd31f9 | 3973 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3974 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3975 | switch (adapter->hw.mac.type) { | |
3976 | case ixgbe_mac_82599EB: | |
3977 | gpie |= IXGBE_SDP0_GPIEN; | |
3978 | break; | |
3979 | case ixgbe_mac_X540: | |
3980 | gpie |= IXGBE_EIMS_TS; | |
3981 | break; | |
3982 | default: | |
3983 | break; | |
3984 | } | |
3985 | } | |
5fdd31f9 | 3986 | |
a34bcfff AD |
3987 | /* Enable fan failure interrupt */ |
3988 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3989 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3990 | |
2698b208 | 3991 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3992 | gpie |= IXGBE_SDP1_GPIEN; |
3993 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3994 | } |
a34bcfff AD |
3995 | |
3996 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3997 | } | |
3998 | ||
c7ccde0f | 3999 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
4000 | { |
4001 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 4002 | int err; |
a34bcfff AD |
4003 | u32 ctrl_ext; |
4004 | ||
4005 | ixgbe_get_hw_control(adapter); | |
4006 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 4007 | |
9a799d71 AK |
4008 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4009 | ixgbe_configure_msix(adapter); | |
4010 | else | |
4011 | ixgbe_configure_msi_and_legacy(adapter); | |
4012 | ||
c6ecf39a DS |
4013 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
4014 | if (hw->mac.ops.enable_tx_laser && | |
4015 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4016 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 4017 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
4018 | hw->mac.ops.enable_tx_laser(hw); |
4019 | ||
9a799d71 | 4020 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
4021 | ixgbe_napi_enable_all(adapter); |
4022 | ||
73c4b7cd AD |
4023 | if (ixgbe_is_sfp(hw)) { |
4024 | ixgbe_sfp_link_config(adapter); | |
4025 | } else { | |
4026 | err = ixgbe_non_sfp_link_config(hw); | |
4027 | if (err) | |
4028 | e_err(probe, "link_config FAILED %d\n", err); | |
4029 | } | |
4030 | ||
021230d4 AV |
4031 | /* clear any pending interrupts, may auto mask */ |
4032 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 4033 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 4034 | |
bf069c97 DS |
4035 | /* |
4036 | * If this adapter has a fan, check to see if we had a failure | |
4037 | * before we enabled the interrupt. | |
4038 | */ | |
4039 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
4040 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
4041 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 4042 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
4043 | } |
4044 | ||
1da100bb | 4045 | /* enable transmits */ |
477de6ed | 4046 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 4047 | |
9a799d71 AK |
4048 | /* bring the link up in the watchdog, this could race with our first |
4049 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
4050 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4051 | adapter->link_check_timeout = jiffies; | |
7086400d | 4052 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
4053 | |
4054 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
4055 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
4056 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
4057 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
4058 | } |
4059 | ||
d4f80882 AV |
4060 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
4061 | { | |
4062 | WARN_ON(in_interrupt()); | |
7086400d AD |
4063 | /* put off any impending NetWatchDogTimeout */ |
4064 | adapter->netdev->trans_start = jiffies; | |
4065 | ||
d4f80882 | 4066 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4067 | usleep_range(1000, 2000); |
d4f80882 | 4068 | ixgbe_down(adapter); |
5809a1ae GR |
4069 | /* |
4070 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4071 | * back up to give the VFs time to respond to the reset. The | |
4072 | * two second wait is based upon the watchdog timer cycle in | |
4073 | * the VF driver. | |
4074 | */ | |
4075 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4076 | msleep(2000); | |
d4f80882 AV |
4077 | ixgbe_up(adapter); |
4078 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4079 | } | |
4080 | ||
c7ccde0f | 4081 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4082 | { |
4083 | /* hardware has been reset, we need to reload some things */ | |
4084 | ixgbe_configure(adapter); | |
4085 | ||
c7ccde0f | 4086 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4087 | } |
4088 | ||
4089 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4090 | { | |
c44ade9e | 4091 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4092 | int err; |
4093 | ||
7086400d AD |
4094 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4095 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4096 | usleep_range(1000, 2000); | |
4097 | ||
4098 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4099 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4100 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4101 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4102 | ||
8ca783ab | 4103 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4104 | switch (err) { |
4105 | case 0: | |
4106 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4107 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4108 | break; |
4109 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4110 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4111 | break; |
794caeb2 PWJ |
4112 | case IXGBE_ERR_EEPROM_VERSION: |
4113 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4114 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4115 | "Please be aware there may be issues associated with " |
849c4542 ET |
4116 | "your hardware. If you are experiencing problems " |
4117 | "please contact your Intel or hardware " | |
4118 | "representative who provided you with this " | |
4119 | "hardware.\n"); | |
794caeb2 | 4120 | break; |
da4dd0f7 | 4121 | default: |
849c4542 | 4122 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4123 | } |
9a799d71 | 4124 | |
7086400d AD |
4125 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4126 | ||
9a799d71 | 4127 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
4128 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4129 | IXGBE_RAH_AV); | |
9a799d71 AK |
4130 | } |
4131 | ||
f800326d AD |
4132 | /** |
4133 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
4134 | * @rx_ring: ring to setup | |
4135 | * | |
4136 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
4137 | * results in each receive buffer starting in the same cache set. To help | |
4138 | * reduce the pressure on this cache set we can interleave the offsets so | |
4139 | * that only every other buffer will be in the same cache set. | |
4140 | **/ | |
4141 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4142 | { | |
4143 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4144 | u16 i; | |
4145 | ||
4146 | for (i = 0; i < rx_ring->count; i += 2) { | |
4147 | rx_buffer[0].page_offset = 0; | |
4148 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4149 | rx_buffer = &rx_buffer[2]; | |
4150 | } | |
4151 | } | |
4152 | ||
9a799d71 AK |
4153 | /** |
4154 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4155 | * @rx_ring: ring to free buffers from |
4156 | **/ | |
b6ec895e | 4157 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4158 | { |
b6ec895e | 4159 | struct device *dev = rx_ring->dev; |
9a799d71 | 4160 | unsigned long size; |
b6ec895e | 4161 | u16 i; |
9a799d71 | 4162 | |
84418e3b AD |
4163 | /* ring already cleared, nothing to do */ |
4164 | if (!rx_ring->rx_buffer_info) | |
4165 | return; | |
9a799d71 | 4166 | |
84418e3b | 4167 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4168 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4169 | struct ixgbe_rx_buffer *rx_buffer; |
4170 | ||
4171 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4172 | if (rx_buffer->skb) { | |
4173 | struct sk_buff *skb = rx_buffer->skb; | |
4174 | if (IXGBE_CB(skb)->page_released) { | |
4175 | dma_unmap_page(dev, | |
4176 | IXGBE_CB(skb)->dma, | |
4177 | ixgbe_rx_bufsz(rx_ring), | |
4178 | DMA_FROM_DEVICE); | |
4179 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4180 | } |
4181 | dev_kfree_skb(skb); | |
9a799d71 | 4182 | } |
f800326d AD |
4183 | rx_buffer->skb = NULL; |
4184 | if (rx_buffer->dma) | |
4185 | dma_unmap_page(dev, rx_buffer->dma, | |
4186 | ixgbe_rx_pg_size(rx_ring), | |
4187 | DMA_FROM_DEVICE); | |
4188 | rx_buffer->dma = 0; | |
4189 | if (rx_buffer->page) | |
dd411ec4 AD |
4190 | __free_pages(rx_buffer->page, |
4191 | ixgbe_rx_pg_order(rx_ring)); | |
f800326d | 4192 | rx_buffer->page = NULL; |
9a799d71 AK |
4193 | } |
4194 | ||
4195 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4196 | memset(rx_ring->rx_buffer_info, 0, size); | |
4197 | ||
f800326d AD |
4198 | ixgbe_init_rx_page_offset(rx_ring); |
4199 | ||
9a799d71 AK |
4200 | /* Zero out the descriptor ring */ |
4201 | memset(rx_ring->desc, 0, rx_ring->size); | |
4202 | ||
f800326d | 4203 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4204 | rx_ring->next_to_clean = 0; |
4205 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4206 | } |
4207 | ||
4208 | /** | |
4209 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4210 | * @tx_ring: ring to be cleaned |
4211 | **/ | |
b6ec895e | 4212 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4213 | { |
4214 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4215 | unsigned long size; | |
b6ec895e | 4216 | u16 i; |
9a799d71 | 4217 | |
84418e3b AD |
4218 | /* ring already cleared, nothing to do */ |
4219 | if (!tx_ring->tx_buffer_info) | |
4220 | return; | |
9a799d71 | 4221 | |
84418e3b | 4222 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4223 | for (i = 0; i < tx_ring->count; i++) { |
4224 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4225 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4226 | } |
4227 | ||
dad8a3b3 JF |
4228 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
4229 | ||
9a799d71 AK |
4230 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4231 | memset(tx_ring->tx_buffer_info, 0, size); | |
4232 | ||
4233 | /* Zero out the descriptor ring */ | |
4234 | memset(tx_ring->desc, 0, tx_ring->size); | |
4235 | ||
4236 | tx_ring->next_to_use = 0; | |
4237 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4238 | } |
4239 | ||
4240 | /** | |
021230d4 | 4241 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4242 | * @adapter: board private structure |
4243 | **/ | |
021230d4 | 4244 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4245 | { |
4246 | int i; | |
4247 | ||
021230d4 | 4248 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4249 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4250 | } |
4251 | ||
4252 | /** | |
021230d4 | 4253 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4254 | * @adapter: board private structure |
4255 | **/ | |
021230d4 | 4256 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4257 | { |
4258 | int i; | |
4259 | ||
021230d4 | 4260 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4261 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4262 | } |
4263 | ||
e4911d57 AD |
4264 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4265 | { | |
4266 | struct hlist_node *node, *node2; | |
4267 | struct ixgbe_fdir_filter *filter; | |
4268 | ||
4269 | spin_lock(&adapter->fdir_perfect_lock); | |
4270 | ||
4271 | hlist_for_each_entry_safe(filter, node, node2, | |
4272 | &adapter->fdir_filter_list, fdir_node) { | |
4273 | hlist_del(&filter->fdir_node); | |
4274 | kfree(filter); | |
4275 | } | |
4276 | adapter->fdir_filter_count = 0; | |
4277 | ||
4278 | spin_unlock(&adapter->fdir_perfect_lock); | |
4279 | } | |
4280 | ||
9a799d71 AK |
4281 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4282 | { | |
4283 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4284 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4285 | u32 rxctrl; |
bf29ee6c | 4286 | int i; |
9a799d71 AK |
4287 | |
4288 | /* signal that we are down to the interrupt handler */ | |
4289 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4290 | ||
4291 | /* disable receives */ | |
7f821875 JB |
4292 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4293 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4294 | |
2d39d576 YZ |
4295 | /* disable all enabled rx queues */ |
4296 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4297 | /* this call also flushes the previous write */ | |
4298 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4299 | ||
032b4325 | 4300 | usleep_range(10000, 20000); |
9a799d71 | 4301 | |
7f821875 JB |
4302 | netif_tx_stop_all_queues(netdev); |
4303 | ||
7086400d | 4304 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4305 | netif_carrier_off(netdev); |
4306 | netif_tx_disable(netdev); | |
4307 | ||
4308 | ixgbe_irq_disable(adapter); | |
4309 | ||
4310 | ixgbe_napi_disable_all(adapter); | |
4311 | ||
d034acf1 AD |
4312 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4313 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4314 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4315 | ||
4316 | del_timer_sync(&adapter->service_timer); | |
4317 | ||
34cecbbf | 4318 | if (adapter->num_vfs) { |
8e34d1aa AD |
4319 | /* Clear EITR Select mapping */ |
4320 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4321 | |
4322 | /* Mark all the VFs as inactive */ | |
4323 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4324 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4325 | |
34cecbbf AD |
4326 | /* ping all the active vfs to let them know we are going down */ |
4327 | ixgbe_ping_all_vfs(adapter); | |
4328 | ||
4329 | /* Disable all VFTE/VFRE TX/RX */ | |
4330 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4331 | } |
4332 | ||
7f821875 JB |
4333 | /* disable transmits in the hardware now that interrupts are off */ |
4334 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4335 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4336 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4337 | } |
34cecbbf AD |
4338 | |
4339 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4340 | switch (hw->mac.type) { |
4341 | case ixgbe_mac_82599EB: | |
b93a2226 | 4342 | case ixgbe_mac_X540: |
88512539 | 4343 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4344 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4345 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4346 | break; |
4347 | default: | |
4348 | break; | |
4349 | } | |
7f821875 | 4350 | |
6f4a0e45 PL |
4351 | if (!pci_channel_offline(adapter->pdev)) |
4352 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4353 | |
4354 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4355 | if (hw->mac.ops.disable_tx_laser && | |
4356 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4357 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4358 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4359 | hw->mac.ops.disable_tx_laser(hw); | |
4360 | ||
9a799d71 AK |
4361 | ixgbe_clean_all_tx_rings(adapter); |
4362 | ixgbe_clean_all_rx_rings(adapter); | |
4363 | ||
5dd2d332 | 4364 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4365 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4366 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4367 | #endif |
9a799d71 AK |
4368 | } |
4369 | ||
9a799d71 AK |
4370 | /** |
4371 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4372 | * @netdev: network interface device structure | |
4373 | **/ | |
4374 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4375 | { | |
4376 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4377 | ||
4378 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4379 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4380 | } |
4381 | ||
9a799d71 AK |
4382 | /** |
4383 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4384 | * @adapter: board private structure to initialize | |
4385 | * | |
4386 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4387 | * Fields are initialized based on PCI device information and | |
4388 | * OS network device settings (MTU size). | |
4389 | **/ | |
4390 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4391 | { | |
4392 | struct ixgbe_hw *hw = &adapter->hw; | |
4393 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4394 | unsigned int rss; |
7a6b6f51 | 4395 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4396 | int j; |
4397 | struct tc_configuration *tc; | |
4398 | #endif | |
021230d4 | 4399 | |
c44ade9e JB |
4400 | /* PCI config space info */ |
4401 | ||
4402 | hw->vendor_id = pdev->vendor; | |
4403 | hw->device_id = pdev->device; | |
4404 | hw->revision_id = pdev->revision; | |
4405 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4406 | hw->subsystem_device_id = pdev->subsystem_device; | |
4407 | ||
021230d4 | 4408 | /* Set capability flags */ |
3ed69d7e | 4409 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
c087663e | 4410 | adapter->ring_feature[RING_F_RSS].limit = rss; |
021230d4 | 4411 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; |
bd508178 AD |
4412 | switch (hw->mac.type) { |
4413 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4414 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4415 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
49c7ffbe | 4416 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
bd508178 | 4417 | break; |
b93a2226 | 4418 | case ixgbe_mac_X540: |
4f51bf70 JK |
4419 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
4420 | case ixgbe_mac_82599EB: | |
49c7ffbe | 4421 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
0c19d6af PWJ |
4422 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4423 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4424 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4425 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
4426 | /* Flow Director hash filters enabled */ |
4427 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4428 | adapter->atr_sample_rate = 20; | |
c087663e | 4429 | adapter->ring_feature[RING_F_FDIR].limit = |
e8e9f696 | 4430 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4431 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4432 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4433 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4434 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
61a0f421 | 4435 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4436 | /* Default traffic class to use for FCoE */ |
56075a98 | 4437 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4438 | #endif |
eacd73f7 | 4439 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4440 | break; |
4441 | default: | |
4442 | break; | |
f8212f97 | 4443 | } |
2f90b865 | 4444 | |
1fc5f038 AD |
4445 | /* n-tuple support exists, always init our spinlock */ |
4446 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4447 | ||
7a6b6f51 | 4448 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
4449 | switch (hw->mac.type) { |
4450 | case ixgbe_mac_X540: | |
4451 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
4452 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
4453 | break; | |
4454 | default: | |
4455 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
4456 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
4457 | break; | |
4458 | } | |
4459 | ||
2f90b865 AD |
4460 | /* Configure DCB traffic classes */ |
4461 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4462 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4463 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4464 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4465 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4466 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4467 | tc->dcb_pfc = pfc_disabled; | |
4468 | } | |
4de2a022 JF |
4469 | |
4470 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
4471 | tc = &adapter->dcb_cfg.tc_config[0]; | |
4472 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4473 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4474 | ||
2f90b865 AD |
4475 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
4476 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4477 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4478 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4479 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
f525c6d2 JF |
4480 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, |
4481 | sizeof(adapter->temp_dcb_cfg)); | |
2f90b865 AD |
4482 | |
4483 | #endif | |
9a799d71 AK |
4484 | |
4485 | /* default flow control settings */ | |
cd7664f6 | 4486 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4487 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 4488 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
4489 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4490 | hw->fc.send_xon = true; | |
71fd570b | 4491 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4492 | |
30efa5a3 | 4493 | /* enable itr by default in dynamic mode */ |
f7554a2b | 4494 | adapter->rx_itr_setting = 1; |
f7554a2b | 4495 | adapter->tx_itr_setting = 1; |
30efa5a3 | 4496 | |
30efa5a3 JB |
4497 | /* set default ring sizes */ |
4498 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4499 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4500 | ||
bd198058 | 4501 | /* set default work limits */ |
59224555 | 4502 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4503 | |
9a799d71 | 4504 | /* initialize eeprom parameters */ |
c44ade9e | 4505 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4506 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4507 | return -EIO; |
4508 | } | |
4509 | ||
9a799d71 AK |
4510 | set_bit(__IXGBE_DOWN, &adapter->state); |
4511 | ||
4512 | return 0; | |
4513 | } | |
4514 | ||
4515 | /** | |
4516 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4517 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4518 | * |
4519 | * Return 0 on success, negative on failure | |
4520 | **/ | |
b6ec895e | 4521 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4522 | { |
b6ec895e | 4523 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
4524 | int orig_node = dev_to_node(dev); |
4525 | int numa_node = -1; | |
9a799d71 AK |
4526 | int size; |
4527 | ||
3a581073 | 4528 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
4529 | |
4530 | if (tx_ring->q_vector) | |
4531 | numa_node = tx_ring->q_vector->numa_node; | |
4532 | ||
4533 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4534 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4535 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4536 | if (!tx_ring->tx_buffer_info) |
4537 | goto err; | |
9a799d71 AK |
4538 | |
4539 | /* round up to nearest 4K */ | |
12207e49 | 4540 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4541 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4542 | |
de88eeeb AD |
4543 | set_dev_node(dev, numa_node); |
4544 | tx_ring->desc = dma_alloc_coherent(dev, | |
4545 | tx_ring->size, | |
4546 | &tx_ring->dma, | |
4547 | GFP_KERNEL); | |
4548 | set_dev_node(dev, orig_node); | |
4549 | if (!tx_ring->desc) | |
4550 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
4551 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4552 | if (!tx_ring->desc) |
4553 | goto err; | |
9a799d71 | 4554 | |
3a581073 JB |
4555 | tx_ring->next_to_use = 0; |
4556 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4557 | return 0; |
e01c31a5 JB |
4558 | |
4559 | err: | |
4560 | vfree(tx_ring->tx_buffer_info); | |
4561 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4562 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4563 | return -ENOMEM; |
9a799d71 AK |
4564 | } |
4565 | ||
69888674 AD |
4566 | /** |
4567 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4568 | * @adapter: board private structure | |
4569 | * | |
4570 | * If this function returns with an error, then it's possible one or | |
4571 | * more of the rings is populated (while the rest are not). It is the | |
4572 | * callers duty to clean those orphaned rings. | |
4573 | * | |
4574 | * Return 0 on success, negative on failure | |
4575 | **/ | |
4576 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4577 | { | |
4578 | int i, err = 0; | |
4579 | ||
4580 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4581 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4582 | if (!err) |
4583 | continue; | |
de3d5b94 | 4584 | |
396e799c | 4585 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 4586 | goto err_setup_tx; |
69888674 AD |
4587 | } |
4588 | ||
de3d5b94 AD |
4589 | return 0; |
4590 | err_setup_tx: | |
4591 | /* rewind the index freeing the rings as we go */ | |
4592 | while (i--) | |
4593 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
4594 | return err; |
4595 | } | |
4596 | ||
9a799d71 AK |
4597 | /** |
4598 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4599 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4600 | * |
4601 | * Returns 0 on success, negative on failure | |
4602 | **/ | |
b6ec895e | 4603 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4604 | { |
b6ec895e | 4605 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
4606 | int orig_node = dev_to_node(dev); |
4607 | int numa_node = -1; | |
021230d4 | 4608 | int size; |
9a799d71 | 4609 | |
3a581073 | 4610 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
4611 | |
4612 | if (rx_ring->q_vector) | |
4613 | numa_node = rx_ring->q_vector->numa_node; | |
4614 | ||
4615 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4616 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 4617 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
4618 | if (!rx_ring->rx_buffer_info) |
4619 | goto err; | |
9a799d71 | 4620 | |
9a799d71 | 4621 | /* Round up to nearest 4K */ |
3a581073 JB |
4622 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4623 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4624 | |
de88eeeb AD |
4625 | set_dev_node(dev, numa_node); |
4626 | rx_ring->desc = dma_alloc_coherent(dev, | |
4627 | rx_ring->size, | |
4628 | &rx_ring->dma, | |
4629 | GFP_KERNEL); | |
4630 | set_dev_node(dev, orig_node); | |
4631 | if (!rx_ring->desc) | |
4632 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
4633 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
4634 | if (!rx_ring->desc) |
4635 | goto err; | |
9a799d71 | 4636 | |
3a581073 JB |
4637 | rx_ring->next_to_clean = 0; |
4638 | rx_ring->next_to_use = 0; | |
9a799d71 | 4639 | |
f800326d AD |
4640 | ixgbe_init_rx_page_offset(rx_ring); |
4641 | ||
9a799d71 | 4642 | return 0; |
b6ec895e AD |
4643 | err: |
4644 | vfree(rx_ring->rx_buffer_info); | |
4645 | rx_ring->rx_buffer_info = NULL; | |
4646 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 4647 | return -ENOMEM; |
9a799d71 AK |
4648 | } |
4649 | ||
69888674 AD |
4650 | /** |
4651 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4652 | * @adapter: board private structure | |
4653 | * | |
4654 | * If this function returns with an error, then it's possible one or | |
4655 | * more of the rings is populated (while the rest are not). It is the | |
4656 | * callers duty to clean those orphaned rings. | |
4657 | * | |
4658 | * Return 0 on success, negative on failure | |
4659 | **/ | |
69888674 AD |
4660 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
4661 | { | |
4662 | int i, err = 0; | |
4663 | ||
4664 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 4665 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
4666 | if (!err) |
4667 | continue; | |
de3d5b94 | 4668 | |
396e799c | 4669 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 4670 | goto err_setup_rx; |
69888674 AD |
4671 | } |
4672 | ||
de3d5b94 AD |
4673 | return 0; |
4674 | err_setup_rx: | |
4675 | /* rewind the index freeing the rings as we go */ | |
4676 | while (i--) | |
4677 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
4678 | return err; |
4679 | } | |
4680 | ||
9a799d71 AK |
4681 | /** |
4682 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
4683 | * @tx_ring: Tx descriptor ring for a specific queue |
4684 | * | |
4685 | * Free all transmit software resources | |
4686 | **/ | |
b6ec895e | 4687 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4688 | { |
b6ec895e | 4689 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
4690 | |
4691 | vfree(tx_ring->tx_buffer_info); | |
4692 | tx_ring->tx_buffer_info = NULL; | |
4693 | ||
b6ec895e AD |
4694 | /* if not set, then don't free */ |
4695 | if (!tx_ring->desc) | |
4696 | return; | |
4697 | ||
4698 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
4699 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
4700 | |
4701 | tx_ring->desc = NULL; | |
4702 | } | |
4703 | ||
4704 | /** | |
4705 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4706 | * @adapter: board private structure | |
4707 | * | |
4708 | * Free all transmit software resources | |
4709 | **/ | |
4710 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4711 | { | |
4712 | int i; | |
4713 | ||
4714 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4715 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 4716 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
4717 | } |
4718 | ||
4719 | /** | |
b4617240 | 4720 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4721 | * @rx_ring: ring to clean the resources from |
4722 | * | |
4723 | * Free all receive software resources | |
4724 | **/ | |
b6ec895e | 4725 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4726 | { |
b6ec895e | 4727 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
4728 | |
4729 | vfree(rx_ring->rx_buffer_info); | |
4730 | rx_ring->rx_buffer_info = NULL; | |
4731 | ||
b6ec895e AD |
4732 | /* if not set, then don't free */ |
4733 | if (!rx_ring->desc) | |
4734 | return; | |
4735 | ||
4736 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
4737 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
4738 | |
4739 | rx_ring->desc = NULL; | |
4740 | } | |
4741 | ||
4742 | /** | |
4743 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4744 | * @adapter: board private structure | |
4745 | * | |
4746 | * Free all receive software resources | |
4747 | **/ | |
4748 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4749 | { | |
4750 | int i; | |
4751 | ||
4752 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4753 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 4754 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
4755 | } |
4756 | ||
9a799d71 AK |
4757 | /** |
4758 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4759 | * @netdev: network interface device structure | |
4760 | * @new_mtu: new value for maximum frame size | |
4761 | * | |
4762 | * Returns 0 on success, negative on failure | |
4763 | **/ | |
4764 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4765 | { | |
4766 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4767 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4768 | ||
42c783c5 | 4769 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
4770 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
4771 | return -EINVAL; | |
4772 | ||
4773 | /* | |
4774 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
4775 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
4776 | * don't allocate and chain buffers correctly. | |
4777 | */ | |
4778 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
4779 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
4780 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 4781 | return -EINVAL; |
9a799d71 | 4782 | |
396e799c | 4783 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 4784 | |
021230d4 | 4785 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4786 | netdev->mtu = new_mtu; |
4787 | ||
d4f80882 AV |
4788 | if (netif_running(netdev)) |
4789 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4790 | |
4791 | return 0; | |
4792 | } | |
4793 | ||
4794 | /** | |
4795 | * ixgbe_open - Called when a network interface is made active | |
4796 | * @netdev: network interface device structure | |
4797 | * | |
4798 | * Returns 0 on success, negative value on failure | |
4799 | * | |
4800 | * The open entry point is called when a network interface is made | |
4801 | * active by the system (IFF_UP). At this point all resources needed | |
4802 | * for transmit and receive operations are allocated, the interrupt | |
4803 | * handler is registered with the OS, the watchdog timer is started, | |
4804 | * and the stack is notified that the interface is ready. | |
4805 | **/ | |
4806 | static int ixgbe_open(struct net_device *netdev) | |
4807 | { | |
4808 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4809 | int err; | |
4bebfaa5 AK |
4810 | |
4811 | /* disallow open during test */ | |
4812 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4813 | return -EBUSY; | |
9a799d71 | 4814 | |
54386467 JB |
4815 | netif_carrier_off(netdev); |
4816 | ||
9a799d71 AK |
4817 | /* allocate transmit descriptors */ |
4818 | err = ixgbe_setup_all_tx_resources(adapter); | |
4819 | if (err) | |
4820 | goto err_setup_tx; | |
4821 | ||
9a799d71 AK |
4822 | /* allocate receive descriptors */ |
4823 | err = ixgbe_setup_all_rx_resources(adapter); | |
4824 | if (err) | |
4825 | goto err_setup_rx; | |
4826 | ||
4827 | ixgbe_configure(adapter); | |
4828 | ||
021230d4 | 4829 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4830 | if (err) |
4831 | goto err_req_irq; | |
4832 | ||
ac802f5d AD |
4833 | /* Notify the stack of the actual queue counts. */ |
4834 | err = netif_set_real_num_tx_queues(netdev, | |
4835 | adapter->num_rx_pools > 1 ? 1 : | |
4836 | adapter->num_tx_queues); | |
4837 | if (err) | |
4838 | goto err_set_queues; | |
4839 | ||
4840 | ||
4841 | err = netif_set_real_num_rx_queues(netdev, | |
4842 | adapter->num_rx_pools > 1 ? 1 : | |
4843 | adapter->num_rx_queues); | |
4844 | if (err) | |
4845 | goto err_set_queues; | |
4846 | ||
c7ccde0f | 4847 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4848 | |
4849 | return 0; | |
4850 | ||
ac802f5d AD |
4851 | err_set_queues: |
4852 | ixgbe_free_irq(adapter); | |
9a799d71 | 4853 | err_req_irq: |
a20a1199 | 4854 | ixgbe_free_all_rx_resources(adapter); |
de3d5b94 | 4855 | err_setup_rx: |
a20a1199 | 4856 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 4857 | err_setup_tx: |
9a799d71 AK |
4858 | ixgbe_reset(adapter); |
4859 | ||
4860 | return err; | |
4861 | } | |
4862 | ||
4863 | /** | |
4864 | * ixgbe_close - Disables a network interface | |
4865 | * @netdev: network interface device structure | |
4866 | * | |
4867 | * Returns 0, this is not allowed to fail | |
4868 | * | |
4869 | * The close entry point is called when an interface is de-activated | |
4870 | * by the OS. The hardware is still under the drivers control, but | |
4871 | * needs to be disabled. A global MAC reset is issued to stop the | |
4872 | * hardware, and all transmit and receive resources are freed. | |
4873 | **/ | |
4874 | static int ixgbe_close(struct net_device *netdev) | |
4875 | { | |
4876 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4877 | |
4878 | ixgbe_down(adapter); | |
4879 | ixgbe_free_irq(adapter); | |
4880 | ||
e4911d57 AD |
4881 | ixgbe_fdir_filter_exit(adapter); |
4882 | ||
9a799d71 AK |
4883 | ixgbe_free_all_tx_resources(adapter); |
4884 | ixgbe_free_all_rx_resources(adapter); | |
4885 | ||
5eba3699 | 4886 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4887 | |
4888 | return 0; | |
4889 | } | |
4890 | ||
b3c8b4ba AD |
4891 | #ifdef CONFIG_PM |
4892 | static int ixgbe_resume(struct pci_dev *pdev) | |
4893 | { | |
c60fbb00 AD |
4894 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4895 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
4896 | u32 err; |
4897 | ||
4898 | pci_set_power_state(pdev, PCI_D0); | |
4899 | pci_restore_state(pdev); | |
656ab817 DS |
4900 | /* |
4901 | * pci_restore_state clears dev->state_saved so call | |
4902 | * pci_save_state to restore it. | |
4903 | */ | |
4904 | pci_save_state(pdev); | |
9ce77666 | 4905 | |
4906 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4907 | if (err) { |
849c4542 | 4908 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
4909 | return err; |
4910 | } | |
4911 | pci_set_master(pdev); | |
4912 | ||
dd4d8ca6 | 4913 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 4914 | |
b3c8b4ba AD |
4915 | ixgbe_reset(adapter); |
4916 | ||
495dce12 WJP |
4917 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4918 | ||
ac802f5d AD |
4919 | rtnl_lock(); |
4920 | err = ixgbe_init_interrupt_scheme(adapter); | |
4921 | if (!err && netif_running(netdev)) | |
c60fbb00 | 4922 | err = ixgbe_open(netdev); |
ac802f5d AD |
4923 | |
4924 | rtnl_unlock(); | |
4925 | ||
4926 | if (err) | |
4927 | return err; | |
b3c8b4ba AD |
4928 | |
4929 | netif_device_attach(netdev); | |
4930 | ||
4931 | return 0; | |
4932 | } | |
b3c8b4ba | 4933 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4934 | |
4935 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 4936 | { |
c60fbb00 AD |
4937 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4938 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
4939 | struct ixgbe_hw *hw = &adapter->hw; |
4940 | u32 ctrl, fctrl; | |
4941 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4942 | #ifdef CONFIG_PM |
4943 | int retval = 0; | |
4944 | #endif | |
4945 | ||
4946 | netif_device_detach(netdev); | |
4947 | ||
4948 | if (netif_running(netdev)) { | |
ab6039a7 | 4949 | rtnl_lock(); |
b3c8b4ba AD |
4950 | ixgbe_down(adapter); |
4951 | ixgbe_free_irq(adapter); | |
4952 | ixgbe_free_all_tx_resources(adapter); | |
4953 | ixgbe_free_all_rx_resources(adapter); | |
ab6039a7 | 4954 | rtnl_unlock(); |
b3c8b4ba | 4955 | } |
b3c8b4ba | 4956 | |
5f5ae6fc AD |
4957 | ixgbe_clear_interrupt_scheme(adapter); |
4958 | ||
b3c8b4ba AD |
4959 | #ifdef CONFIG_PM |
4960 | retval = pci_save_state(pdev); | |
4961 | if (retval) | |
4962 | return retval; | |
4df10466 | 4963 | |
b3c8b4ba | 4964 | #endif |
e8e26350 PW |
4965 | if (wufc) { |
4966 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4967 | |
c509e754 DS |
4968 | /* |
4969 | * enable the optics for both mult-speed fiber and | |
4970 | * 82599 SFP+ fiber as we can WoL. | |
4971 | */ | |
4972 | if (hw->mac.ops.enable_tx_laser && | |
4973 | (hw->phy.multispeed_fiber || | |
4974 | (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber && | |
4975 | hw->mac.type == ixgbe_mac_82599EB))) | |
4976 | hw->mac.ops.enable_tx_laser(hw); | |
4977 | ||
e8e26350 PW |
4978 | /* turn on all-multi mode if wake on multicast is enabled */ |
4979 | if (wufc & IXGBE_WUFC_MC) { | |
4980 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4981 | fctrl |= IXGBE_FCTRL_MPE; | |
4982 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4983 | } | |
4984 | ||
4985 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4986 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4987 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4988 | ||
4989 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4990 | } else { | |
4991 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4992 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4993 | } | |
4994 | ||
bd508178 AD |
4995 | switch (hw->mac.type) { |
4996 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 4997 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
4998 | break; |
4999 | case ixgbe_mac_82599EB: | |
b93a2226 | 5000 | case ixgbe_mac_X540: |
bd508178 AD |
5001 | pci_wake_from_d3(pdev, !!wufc); |
5002 | break; | |
5003 | default: | |
5004 | break; | |
5005 | } | |
b3c8b4ba | 5006 | |
9d8d05ae RW |
5007 | *enable_wake = !!wufc; |
5008 | ||
b3c8b4ba AD |
5009 | ixgbe_release_hw_control(adapter); |
5010 | ||
5011 | pci_disable_device(pdev); | |
5012 | ||
9d8d05ae RW |
5013 | return 0; |
5014 | } | |
5015 | ||
5016 | #ifdef CONFIG_PM | |
5017 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5018 | { | |
5019 | int retval; | |
5020 | bool wake; | |
5021 | ||
5022 | retval = __ixgbe_shutdown(pdev, &wake); | |
5023 | if (retval) | |
5024 | return retval; | |
5025 | ||
5026 | if (wake) { | |
5027 | pci_prepare_to_sleep(pdev); | |
5028 | } else { | |
5029 | pci_wake_from_d3(pdev, false); | |
5030 | pci_set_power_state(pdev, PCI_D3hot); | |
5031 | } | |
b3c8b4ba AD |
5032 | |
5033 | return 0; | |
5034 | } | |
9d8d05ae | 5035 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5036 | |
5037 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5038 | { | |
9d8d05ae RW |
5039 | bool wake; |
5040 | ||
5041 | __ixgbe_shutdown(pdev, &wake); | |
5042 | ||
5043 | if (system_state == SYSTEM_POWER_OFF) { | |
5044 | pci_wake_from_d3(pdev, wake); | |
5045 | pci_set_power_state(pdev, PCI_D3hot); | |
5046 | } | |
b3c8b4ba AD |
5047 | } |
5048 | ||
9a799d71 AK |
5049 | /** |
5050 | * ixgbe_update_stats - Update the board statistics counters. | |
5051 | * @adapter: board private structure | |
5052 | **/ | |
5053 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5054 | { | |
2d86f139 | 5055 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5056 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5057 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5058 | u64 total_mpc = 0; |
5059 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5060 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5061 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 5062 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
7b859ebc AH |
5063 | #ifdef IXGBE_FCOE |
5064 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
5065 | unsigned int cpu; | |
5066 | u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0; | |
5067 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 5068 | |
d08935c2 DS |
5069 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5070 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5071 | return; | |
5072 | ||
94b982b2 | 5073 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5074 | u64 rsc_count = 0; |
94b982b2 | 5075 | u64 rsc_flush = 0; |
94b982b2 | 5076 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5077 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5078 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5079 | } |
5080 | adapter->rsc_total_count = rsc_count; | |
5081 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5082 | } |
5083 | ||
5b7da515 AD |
5084 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5085 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5086 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5087 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5088 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5089 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5090 | bytes += rx_ring->stats.bytes; |
5091 | packets += rx_ring->stats.packets; | |
5092 | } | |
5093 | adapter->non_eop_descs = non_eop_descs; | |
5094 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5095 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5096 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5097 | netdev->stats.rx_bytes = bytes; |
5098 | netdev->stats.rx_packets = packets; | |
5099 | ||
5100 | bytes = 0; | |
5101 | packets = 0; | |
7ca3bc58 | 5102 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5103 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5104 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5105 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5106 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5107 | bytes += tx_ring->stats.bytes; | |
5108 | packets += tx_ring->stats.packets; | |
5109 | } | |
eb985f09 | 5110 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5111 | adapter->tx_busy = tx_busy; |
5112 | netdev->stats.tx_bytes = bytes; | |
5113 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5114 | |
7ca647bd | 5115 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5116 | |
5117 | /* 8 register reads */ | |
6f11eef7 AV |
5118 | for (i = 0; i < 8; i++) { |
5119 | /* for packet buffers not used, the register should read 0 */ | |
5120 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5121 | missed_rx += mpc; | |
7ca647bd JP |
5122 | hwstats->mpc[i] += mpc; |
5123 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5124 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5125 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5126 | switch (hw->mac.type) { |
5127 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5128 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5129 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5130 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5131 | hwstats->pxonrxc[i] += |
5132 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5133 | break; |
5134 | case ixgbe_mac_82599EB: | |
b93a2226 | 5135 | case ixgbe_mac_X540: |
bd508178 AD |
5136 | hwstats->pxonrxc[i] += |
5137 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5138 | break; |
5139 | default: | |
5140 | break; | |
e8e26350 | 5141 | } |
6f11eef7 | 5142 | } |
1a70db4b ET |
5143 | |
5144 | /*16 register reads */ | |
5145 | for (i = 0; i < 16; i++) { | |
5146 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5147 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5148 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5149 | (hw->mac.type == ixgbe_mac_X540)) { | |
5150 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5151 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5152 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5153 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5154 | } | |
5155 | } | |
5156 | ||
7ca647bd | 5157 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5158 | /* work around hardware counting issue */ |
7ca647bd | 5159 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5160 | |
c84d324c JF |
5161 | ixgbe_update_xoff_received(adapter); |
5162 | ||
6f11eef7 | 5163 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5164 | switch (hw->mac.type) { |
5165 | case ixgbe_mac_82598EB: | |
5166 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5167 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5168 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5169 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5170 | break; | |
b93a2226 | 5171 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5172 | /* OS2BMC stats are X540 only*/ |
5173 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5174 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5175 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5176 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5177 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
5178 | for (i = 0; i < 16; i++) |
5179 | adapter->hw_rx_no_dma_resources += | |
5180 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 5181 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5182 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5183 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5184 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5185 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5186 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5187 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5188 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5189 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5190 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5191 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5192 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5193 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5194 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5195 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5196 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc AH |
5197 | /* Add up per cpu counters for total ddp aloc fail */ |
5198 | if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) { | |
5199 | for_each_possible_cpu(cpu) { | |
5200 | fcoe_noddp_counts_sum += | |
5201 | *per_cpu_ptr(fcoe->pcpu_noddp, cpu); | |
5202 | fcoe_noddp_ext_buff_counts_sum += | |
5203 | *per_cpu_ptr(fcoe-> | |
5204 | pcpu_noddp_ext_buff, cpu); | |
5205 | } | |
5206 | } | |
5207 | hwstats->fcoe_noddp = fcoe_noddp_counts_sum; | |
5208 | hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum; | |
6d45522c | 5209 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5210 | break; |
5211 | default: | |
5212 | break; | |
e8e26350 | 5213 | } |
9a799d71 | 5214 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5215 | hwstats->bprc += bprc; |
5216 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5217 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5218 | hwstats->mprc -= bprc; |
5219 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5220 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5221 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5222 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5223 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5224 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5225 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5226 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5227 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5228 | hwstats->lxontxc += lxon; |
6f11eef7 | 5229 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5230 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5231 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5232 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5233 | /* |
5234 | * 82598 errata - tx of flow control packets is included in tx counters | |
5235 | */ | |
5236 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5237 | hwstats->gptc -= xon_off_tot; |
5238 | hwstats->mptc -= xon_off_tot; | |
5239 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5240 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5241 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5242 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5243 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5244 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5245 | hwstats->ptc64 -= xon_off_tot; | |
5246 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5247 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5248 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5249 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5250 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5251 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5252 | |
5253 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5254 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5255 | |
5256 | /* Rx Errors */ | |
7ca647bd | 5257 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5258 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5259 | netdev->stats.rx_length_errors = hwstats->rlec; |
5260 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5261 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5262 | } |
5263 | ||
5264 | /** | |
d034acf1 | 5265 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 5266 | * @adapter: pointer to the device adapter structure |
9a799d71 | 5267 | **/ |
d034acf1 | 5268 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5269 | { |
cf8280ee | 5270 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5271 | int i; |
cf8280ee | 5272 | |
d034acf1 AD |
5273 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5274 | return; | |
5275 | ||
5276 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5277 | |
d034acf1 | 5278 | /* if interface is down do nothing */ |
fe49f04a | 5279 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5280 | return; |
5281 | ||
5282 | /* do nothing if we are not using signature filters */ | |
5283 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5284 | return; | |
5285 | ||
5286 | adapter->fdir_overflow++; | |
5287 | ||
93c52dd0 AD |
5288 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5289 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5290 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5291 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5292 | /* re-enable flow director interrupts */ |
5293 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5294 | } else { |
5295 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5296 | "ignored adding FDIR ATR filters\n"); | |
5297 | } | |
93c52dd0 AD |
5298 | } |
5299 | ||
5300 | /** | |
5301 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 5302 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5303 | * |
5304 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 5305 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 5306 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 5307 | * determine if a hang has occurred. |
93c52dd0 AD |
5308 | */ |
5309 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5310 | { |
cf8280ee | 5311 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5312 | u64 eics = 0; |
5313 | int i; | |
cf8280ee | 5314 | |
93c52dd0 AD |
5315 | /* If we're down or resetting, just bail */ |
5316 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5317 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5318 | return; | |
22d5a71b | 5319 | |
93c52dd0 AD |
5320 | /* Force detection of hung controller */ |
5321 | if (netif_carrier_ok(adapter->netdev)) { | |
5322 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5323 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5324 | } | |
22d5a71b | 5325 | |
fe49f04a AD |
5326 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5327 | /* | |
5328 | * for legacy and MSI interrupts don't set any bits | |
5329 | * that are enabled for EIAM, because this operation | |
5330 | * would set *both* EIMS and EICS for any bit in EIAM | |
5331 | */ | |
5332 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5333 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5334 | } else { |
5335 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 5336 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 5337 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 5338 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5339 | eics |= ((u64)1 << i); |
5340 | } | |
cf8280ee | 5341 | } |
9a799d71 | 5342 | |
93c52dd0 | 5343 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5344 | ixgbe_irq_rearm_queues(adapter, eics); |
5345 | ||
cf8280ee JB |
5346 | } |
5347 | ||
e8e26350 | 5348 | /** |
93c52dd0 | 5349 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
5350 | * @adapter: pointer to the device adapter structure |
5351 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 5352 | **/ |
93c52dd0 | 5353 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5354 | { |
e8e26350 | 5355 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5356 | u32 link_speed = adapter->link_speed; |
5357 | bool link_up = adapter->link_up; | |
041441d0 | 5358 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 5359 | |
93c52dd0 AD |
5360 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5361 | return; | |
5362 | ||
5363 | if (hw->mac.ops.check_link) { | |
5364 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5365 | } else { |
93c52dd0 AD |
5366 | /* always assume link is up, if no check link function */ |
5367 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5368 | link_up = true; | |
c4cf55e5 | 5369 | } |
041441d0 AD |
5370 | |
5371 | if (adapter->ixgbe_ieee_pfc) | |
5372 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
5373 | ||
3ebe8fde | 5374 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 5375 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
5376 | ixgbe_set_rx_drop_en(adapter); |
5377 | } | |
93c52dd0 AD |
5378 | |
5379 | if (link_up || | |
5380 | time_after(jiffies, (adapter->link_check_timeout + | |
5381 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5382 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5383 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5384 | IXGBE_WRITE_FLUSH(hw); | |
5385 | } | |
5386 | ||
5387 | adapter->link_up = link_up; | |
5388 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5389 | } |
5390 | ||
5391 | /** | |
93c52dd0 AD |
5392 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5393 | * print link up message | |
49ce9c2c | 5394 | * @adapter: pointer to the device adapter structure |
e8e26350 | 5395 | **/ |
93c52dd0 | 5396 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5397 | { |
93c52dd0 | 5398 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5399 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5400 | u32 link_speed = adapter->link_speed; |
5401 | bool flow_rx, flow_tx; | |
e8e26350 | 5402 | |
93c52dd0 AD |
5403 | /* only continue if link was previously down */ |
5404 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5405 | return; |
63d6e1d8 | 5406 | |
93c52dd0 | 5407 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5408 | |
93c52dd0 AD |
5409 | switch (hw->mac.type) { |
5410 | case ixgbe_mac_82598EB: { | |
5411 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5412 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5413 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5414 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5415 | } | |
5416 | break; | |
5417 | case ixgbe_mac_X540: | |
5418 | case ixgbe_mac_82599EB: { | |
5419 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5420 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5421 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5422 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5423 | } | |
5424 | break; | |
5425 | default: | |
5426 | flow_tx = false; | |
5427 | flow_rx = false; | |
5428 | break; | |
e8e26350 | 5429 | } |
3a6a4eda JK |
5430 | |
5431 | #ifdef CONFIG_IXGBE_PTP | |
5432 | ixgbe_ptp_start_cyclecounter(adapter); | |
5433 | #endif | |
5434 | ||
93c52dd0 AD |
5435 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5436 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5437 | "10 Gbps" : | |
5438 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5439 | "1 Gbps" : | |
5440 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5441 | "100 Mbps" : | |
5442 | "unknown speed"))), | |
5443 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5444 | (flow_rx ? "RX" : | |
5445 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5446 | |
93c52dd0 | 5447 | netif_carrier_on(netdev); |
93c52dd0 | 5448 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 AD |
5449 | |
5450 | /* ping all the active vfs to let them know link has changed */ | |
5451 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
5452 | } |
5453 | ||
c4cf55e5 | 5454 | /** |
93c52dd0 AD |
5455 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5456 | * print link down message | |
49ce9c2c | 5457 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 5458 | **/ |
581330ba | 5459 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 5460 | { |
cf8280ee | 5461 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5462 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5463 | |
93c52dd0 AD |
5464 | adapter->link_up = false; |
5465 | adapter->link_speed = 0; | |
cf8280ee | 5466 | |
93c52dd0 AD |
5467 | /* only continue if link was up previously */ |
5468 | if (!netif_carrier_ok(netdev)) | |
5469 | return; | |
264857b8 | 5470 | |
93c52dd0 AD |
5471 | /* poll for SFP+ cable when link is down */ |
5472 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5473 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5474 | |
3a6a4eda JK |
5475 | #ifdef CONFIG_IXGBE_PTP |
5476 | ixgbe_ptp_start_cyclecounter(adapter); | |
5477 | #endif | |
5478 | ||
93c52dd0 AD |
5479 | e_info(drv, "NIC Link is Down\n"); |
5480 | netif_carrier_off(netdev); | |
befa2af7 AD |
5481 | |
5482 | /* ping all the active vfs to let them know link has changed */ | |
5483 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 5484 | } |
e8e26350 | 5485 | |
93c52dd0 AD |
5486 | /** |
5487 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 5488 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5489 | **/ |
5490 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5491 | { | |
c4cf55e5 | 5492 | int i; |
93c52dd0 | 5493 | int some_tx_pending = 0; |
c4cf55e5 | 5494 | |
93c52dd0 | 5495 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5496 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5497 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5498 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5499 | some_tx_pending = 1; | |
5500 | break; | |
5501 | } | |
5502 | } | |
5503 | ||
5504 | if (some_tx_pending) { | |
5505 | /* We've lost link, so the controller stops DMA, | |
5506 | * but we've got queued Tx work that's never going | |
5507 | * to get done, so reset controller to flush Tx. | |
5508 | * (Do the reset outside of interrupt context). | |
5509 | */ | |
c83c6cbd | 5510 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5511 | } |
c4cf55e5 | 5512 | } |
c4cf55e5 PWJ |
5513 | } |
5514 | ||
a985b6c3 GR |
5515 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5516 | { | |
5517 | u32 ssvpc; | |
5518 | ||
5519 | /* Do not perform spoof check for 82598 */ | |
5520 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5521 | return; | |
5522 | ||
5523 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5524 | ||
5525 | /* | |
5526 | * ssvpc register is cleared on read, if zero then no | |
5527 | * spoofed packets in the last interval. | |
5528 | */ | |
5529 | if (!ssvpc) | |
5530 | return; | |
5531 | ||
5532 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
5533 | } | |
5534 | ||
93c52dd0 AD |
5535 | /** |
5536 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 5537 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5538 | **/ |
5539 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5540 | { | |
5541 | /* if interface is down do nothing */ | |
7edebf9a ET |
5542 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5543 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
5544 | return; |
5545 | ||
5546 | ixgbe_watchdog_update_link(adapter); | |
5547 | ||
5548 | if (adapter->link_up) | |
5549 | ixgbe_watchdog_link_is_up(adapter); | |
5550 | else | |
5551 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5552 | |
a985b6c3 | 5553 | ixgbe_spoof_check(adapter); |
9a799d71 | 5554 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5555 | |
5556 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5557 | } |
10eec955 | 5558 | |
cf8280ee | 5559 | /** |
7086400d | 5560 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 5561 | * @adapter: the ixgbe adapter structure |
cf8280ee | 5562 | **/ |
7086400d | 5563 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5564 | { |
cf8280ee | 5565 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5566 | s32 err; |
cf8280ee | 5567 | |
7086400d AD |
5568 | /* not searching for SFP so there is nothing to do here */ |
5569 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5570 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5571 | return; | |
10eec955 | 5572 | |
7086400d AD |
5573 | /* someone else is in init, wait until next service event */ |
5574 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5575 | return; | |
cf8280ee | 5576 | |
7086400d AD |
5577 | err = hw->phy.ops.identify_sfp(hw); |
5578 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5579 | goto sfp_out; | |
264857b8 | 5580 | |
7086400d AD |
5581 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5582 | /* If no cable is present, then we need to reset | |
5583 | * the next time we find a good cable. */ | |
5584 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5585 | } |
9a799d71 | 5586 | |
7086400d AD |
5587 | /* exit on error */ |
5588 | if (err) | |
5589 | goto sfp_out; | |
e8e26350 | 5590 | |
7086400d AD |
5591 | /* exit if reset not needed */ |
5592 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5593 | goto sfp_out; | |
9a799d71 | 5594 | |
7086400d | 5595 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5596 | |
7086400d AD |
5597 | /* |
5598 | * A module may be identified correctly, but the EEPROM may not have | |
5599 | * support for that module. setup_sfp() will fail in that case, so | |
5600 | * we should not allow that module to load. | |
5601 | */ | |
5602 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5603 | err = hw->phy.ops.reset(hw); | |
5604 | else | |
5605 | err = hw->mac.ops.setup_sfp(hw); | |
5606 | ||
5607 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5608 | goto sfp_out; | |
5609 | ||
5610 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5611 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5612 | ||
5613 | sfp_out: | |
5614 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5615 | ||
5616 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5617 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5618 | e_dev_err("failed to initialize because an unsupported " | |
5619 | "SFP+ module type was detected.\n"); | |
5620 | e_dev_err("Reload the driver after installing a " | |
5621 | "supported module.\n"); | |
5622 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5623 | } |
7086400d | 5624 | } |
bc59fcda | 5625 | |
7086400d AD |
5626 | /** |
5627 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 5628 | * @adapter: the ixgbe adapter structure |
7086400d AD |
5629 | **/ |
5630 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5631 | { | |
5632 | struct ixgbe_hw *hw = &adapter->hw; | |
5633 | u32 autoneg; | |
5634 | bool negotiation; | |
5635 | ||
5636 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5637 | return; | |
5638 | ||
5639 | /* someone else is in init, wait until next service event */ | |
5640 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5641 | return; | |
5642 | ||
5643 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5644 | ||
5645 | autoneg = hw->phy.autoneg_advertised; | |
5646 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5647 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
5648 | if (hw->mac.ops.setup_link) |
5649 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5650 | ||
5651 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5652 | adapter->link_check_timeout = jiffies; | |
5653 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5654 | } | |
5655 | ||
83c61fa9 GR |
5656 | #ifdef CONFIG_PCI_IOV |
5657 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
5658 | { | |
5659 | int vf; | |
5660 | struct ixgbe_hw *hw = &adapter->hw; | |
5661 | struct net_device *netdev = adapter->netdev; | |
5662 | u32 gpc; | |
5663 | u32 ciaa, ciad; | |
5664 | ||
5665 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
5666 | if (gpc) /* If incrementing then no need for the check below */ | |
5667 | return; | |
5668 | /* | |
5669 | * Check to see if a bad DMA write target from an errant or | |
5670 | * malicious VF has caused a PCIe error. If so then we can | |
5671 | * issue a VFLR to the offending VF(s) and then resume without | |
5672 | * requesting a full slot reset. | |
5673 | */ | |
5674 | ||
5675 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
5676 | ciaa = (vf << 16) | 0x80000000; | |
5677 | /* 32 bit read so align, we really want status at offset 6 */ | |
5678 | ciaa |= PCI_COMMAND; | |
5679 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5680 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
5681 | ciaa &= 0x7FFFFFFF; | |
5682 | /* disable debug mode asap after reading data */ | |
5683 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5684 | /* Get the upper 16 bits which will be the PCI status reg */ | |
5685 | ciad >>= 16; | |
5686 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
5687 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
5688 | /* Issue VFLR */ | |
5689 | ciaa = (vf << 16) | 0x80000000; | |
5690 | ciaa |= 0xA8; | |
5691 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5692 | ciad = 0x00008000; /* VFLR */ | |
5693 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
5694 | ciaa &= 0x7FFFFFFF; | |
5695 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5696 | } | |
5697 | } | |
5698 | } | |
5699 | ||
5700 | #endif | |
7086400d AD |
5701 | /** |
5702 | * ixgbe_service_timer - Timer Call-back | |
5703 | * @data: pointer to adapter cast into an unsigned long | |
5704 | **/ | |
5705 | static void ixgbe_service_timer(unsigned long data) | |
5706 | { | |
5707 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5708 | unsigned long next_event_offset; | |
83c61fa9 | 5709 | bool ready = true; |
7086400d | 5710 | |
6bb78cfb AD |
5711 | /* poll faster when waiting for link */ |
5712 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5713 | next_event_offset = HZ / 10; | |
5714 | else | |
5715 | next_event_offset = HZ * 2; | |
83c61fa9 | 5716 | |
6bb78cfb | 5717 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
5718 | /* |
5719 | * don't bother with SR-IOV VF DMA hang check if there are | |
5720 | * no VFs or the link is down | |
5721 | */ | |
5722 | if (!adapter->num_vfs || | |
6bb78cfb | 5723 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 5724 | goto normal_timer_service; |
83c61fa9 GR |
5725 | |
5726 | /* If we have VFs allocated then we must check for DMA hangs */ | |
5727 | ixgbe_check_for_bad_vf(adapter); | |
5728 | next_event_offset = HZ / 50; | |
5729 | adapter->timer_event_accumulator++; | |
5730 | ||
6bb78cfb | 5731 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 5732 | adapter->timer_event_accumulator = 0; |
7086400d | 5733 | else |
6bb78cfb | 5734 | ready = false; |
7086400d | 5735 | |
6bb78cfb | 5736 | normal_timer_service: |
83c61fa9 | 5737 | #endif |
7086400d AD |
5738 | /* Reset the timer */ |
5739 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5740 | ||
83c61fa9 GR |
5741 | if (ready) |
5742 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
5743 | } |
5744 | ||
c83c6cbd AD |
5745 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5746 | { | |
5747 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5748 | return; | |
5749 | ||
5750 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
5751 | ||
5752 | /* If we're already down or resetting, just bail */ | |
5753 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5754 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5755 | return; | |
5756 | ||
5757 | ixgbe_dump(adapter); | |
5758 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
5759 | adapter->tx_timeout_count++; | |
5760 | ||
5761 | ixgbe_reinit_locked(adapter); | |
5762 | } | |
5763 | ||
7086400d AD |
5764 | /** |
5765 | * ixgbe_service_task - manages and runs subtasks | |
5766 | * @work: pointer to work_struct containing our data | |
5767 | **/ | |
5768 | static void ixgbe_service_task(struct work_struct *work) | |
5769 | { | |
5770 | struct ixgbe_adapter *adapter = container_of(work, | |
5771 | struct ixgbe_adapter, | |
5772 | service_task); | |
5773 | ||
c83c6cbd | 5774 | ixgbe_reset_subtask(adapter); |
7086400d AD |
5775 | ixgbe_sfp_detection_subtask(adapter); |
5776 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 5777 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 5778 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 5779 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 5780 | ixgbe_check_hang_subtask(adapter); |
3a6a4eda JK |
5781 | #ifdef CONFIG_IXGBE_PTP |
5782 | ixgbe_ptp_overflow_check(adapter); | |
5783 | #endif | |
7086400d AD |
5784 | |
5785 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
5786 | } |
5787 | ||
fd0db0ed AD |
5788 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
5789 | struct ixgbe_tx_buffer *first, | |
244e27ad | 5790 | u8 *hdr_len) |
897ab156 | 5791 | { |
fd0db0ed | 5792 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5793 | u32 vlan_macip_lens, type_tucmd; |
5794 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 5795 | |
897ab156 AD |
5796 | if (!skb_is_gso(skb)) |
5797 | return 0; | |
9a799d71 | 5798 | |
897ab156 | 5799 | if (skb_header_cloned(skb)) { |
244e27ad | 5800 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
5801 | if (err) |
5802 | return err; | |
9a799d71 | 5803 | } |
9a799d71 | 5804 | |
897ab156 AD |
5805 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
5806 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5807 | ||
244e27ad | 5808 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
5809 | struct iphdr *iph = ip_hdr(skb); |
5810 | iph->tot_len = 0; | |
5811 | iph->check = 0; | |
5812 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5813 | iph->daddr, 0, | |
5814 | IPPROTO_TCP, | |
5815 | 0); | |
5816 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
5817 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5818 | IXGBE_TX_FLAGS_CSUM | | |
5819 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
5820 | } else if (skb_is_gso_v6(skb)) { |
5821 | ipv6_hdr(skb)->payload_len = 0; | |
5822 | tcp_hdr(skb)->check = | |
5823 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
5824 | &ipv6_hdr(skb)->daddr, | |
5825 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
5826 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5827 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
5828 | } |
5829 | ||
091a6246 | 5830 | /* compute header lengths */ |
897ab156 AD |
5831 | l4len = tcp_hdrlen(skb); |
5832 | *hdr_len = skb_transport_offset(skb) + l4len; | |
5833 | ||
091a6246 AD |
5834 | /* update gso size and bytecount with header size */ |
5835 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
5836 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
5837 | ||
897ab156 AD |
5838 | /* mss_l4len_id: use 1 as index for TSO */ |
5839 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
5840 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
5841 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
5842 | ||
5843 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
5844 | vlan_macip_lens = skb_network_header_len(skb); | |
5845 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 5846 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
5847 | |
5848 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 5849 | mss_l4len_idx); |
897ab156 AD |
5850 | |
5851 | return 1; | |
5852 | } | |
5853 | ||
244e27ad AD |
5854 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
5855 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 5856 | { |
fd0db0ed | 5857 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5858 | u32 vlan_macip_lens = 0; |
5859 | u32 mss_l4len_idx = 0; | |
5860 | u32 type_tucmd = 0; | |
7ca647bd | 5861 | |
897ab156 | 5862 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
244e27ad AD |
5863 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
5864 | !(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
5865 | return; | |
897ab156 AD |
5866 | } else { |
5867 | u8 l4_hdr = 0; | |
244e27ad | 5868 | switch (first->protocol) { |
897ab156 AD |
5869 | case __constant_htons(ETH_P_IP): |
5870 | vlan_macip_lens |= skb_network_header_len(skb); | |
5871 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5872 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 5873 | break; |
897ab156 AD |
5874 | case __constant_htons(ETH_P_IPV6): |
5875 | vlan_macip_lens |= skb_network_header_len(skb); | |
5876 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
5877 | break; | |
5878 | default: | |
5879 | if (unlikely(net_ratelimit())) { | |
5880 | dev_warn(tx_ring->dev, | |
5881 | "partial checksum but proto=%x!\n", | |
244e27ad | 5882 | first->protocol); |
897ab156 | 5883 | } |
7ca647bd JP |
5884 | break; |
5885 | } | |
897ab156 AD |
5886 | |
5887 | switch (l4_hdr) { | |
7ca647bd | 5888 | case IPPROTO_TCP: |
897ab156 AD |
5889 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
5890 | mss_l4len_idx = tcp_hdrlen(skb) << | |
5891 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
5892 | break; |
5893 | case IPPROTO_SCTP: | |
897ab156 AD |
5894 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
5895 | mss_l4len_idx = sizeof(struct sctphdr) << | |
5896 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5897 | break; | |
5898 | case IPPROTO_UDP: | |
5899 | mss_l4len_idx = sizeof(struct udphdr) << | |
5900 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5901 | break; | |
5902 | default: | |
5903 | if (unlikely(net_ratelimit())) { | |
5904 | dev_warn(tx_ring->dev, | |
5905 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 5906 | l4_hdr); |
897ab156 | 5907 | } |
7ca647bd JP |
5908 | break; |
5909 | } | |
244e27ad AD |
5910 | |
5911 | /* update TX checksum flag */ | |
5912 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
5913 | } |
5914 | ||
244e27ad | 5915 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 5916 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 5917 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 5918 | |
897ab156 AD |
5919 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
5920 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
5921 | } |
5922 | ||
d3d00239 | 5923 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 5924 | { |
d3d00239 AD |
5925 | /* set type for advanced descriptor with frame checksum insertion */ |
5926 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
5927 | IXGBE_ADVTXD_DCMD_IFCS | | |
5928 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 5929 | |
d3d00239 | 5930 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 5931 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 5932 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 5933 | |
3a6a4eda JK |
5934 | #ifdef CONFIG_IXGBE_PTP |
5935 | if (tx_flags & IXGBE_TX_FLAGS_TSTAMP) | |
5936 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP); | |
5937 | #endif | |
5938 | ||
d3d00239 AD |
5939 | /* set segmentation enable bits for TSO/FSO */ |
5940 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 5941 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
5942 | #else |
5943 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
5944 | #endif | |
5945 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 5946 | |
d3d00239 AD |
5947 | return cmd_type; |
5948 | } | |
9a799d71 | 5949 | |
729739b7 AD |
5950 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
5951 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 5952 | { |
93f5b3c1 | 5953 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 5954 | |
d3d00239 AD |
5955 | /* enable L4 checksum for TSO and TX checksum offload */ |
5956 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5957 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 5958 | |
93f5b3c1 AD |
5959 | /* enble IPv4 checksum for TSO */ |
5960 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
5961 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 5962 | |
93f5b3c1 AD |
5963 | /* use index 1 context for TSO/FSO/FCOE */ |
5964 | #ifdef IXGBE_FCOE | |
5965 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
5966 | #else | |
5967 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 5968 | #endif |
93f5b3c1 AD |
5969 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
5970 | ||
7f9643fd AD |
5971 | /* |
5972 | * Check Context must be set if Tx switch is enabled, which it | |
5973 | * always is for case where virtual functions are running | |
5974 | */ | |
93f5b3c1 AD |
5975 | #ifdef IXGBE_FCOE |
5976 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
5977 | #else | |
7f9643fd | 5978 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 5979 | #endif |
7f9643fd AD |
5980 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
5981 | ||
729739b7 | 5982 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 5983 | } |
44df32c5 | 5984 | |
d3d00239 AD |
5985 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
5986 | IXGBE_TXD_CMD_RS) | |
5987 | ||
5988 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 5989 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
5990 | const u8 hdr_len) |
5991 | { | |
729739b7 | 5992 | dma_addr_t dma; |
fd0db0ed | 5993 | struct sk_buff *skb = first->skb; |
729739b7 | 5994 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 5995 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 5996 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
5997 | unsigned int data_len = skb->data_len; |
5998 | unsigned int size = skb_headlen(skb); | |
729739b7 | 5999 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 6000 | u32 tx_flags = first->tx_flags; |
729739b7 | 6001 | __le32 cmd_type; |
d3d00239 | 6002 | u16 i = tx_ring->next_to_use; |
d3d00239 | 6003 | |
729739b7 AD |
6004 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
6005 | ||
6006 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
6007 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
6008 | ||
d3d00239 AD |
6009 | #ifdef IXGBE_FCOE |
6010 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 6011 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
6012 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
6013 | data_len = 0; | |
729739b7 AD |
6014 | } else { |
6015 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
6016 | } |
6017 | } | |
44df32c5 | 6018 | |
d3d00239 | 6019 | #endif |
729739b7 AD |
6020 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
6021 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6022 | goto dma_error; |
8ad494b0 | 6023 | |
729739b7 AD |
6024 | /* record length, and DMA address */ |
6025 | dma_unmap_len_set(first, len, size); | |
6026 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 6027 | |
729739b7 | 6028 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 6029 | |
d3d00239 | 6030 | for (;;) { |
729739b7 | 6031 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
6032 | tx_desc->read.cmd_type_len = |
6033 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 6034 | |
d3d00239 | 6035 | i++; |
729739b7 | 6036 | tx_desc++; |
d3d00239 | 6037 | if (i == tx_ring->count) { |
e4f74028 | 6038 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6039 | i = 0; |
6040 | } | |
729739b7 AD |
6041 | |
6042 | dma += IXGBE_MAX_DATA_PER_TXD; | |
6043 | size -= IXGBE_MAX_DATA_PER_TXD; | |
6044 | ||
6045 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
6046 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 6047 | } |
e5a43549 | 6048 | |
729739b7 AD |
6049 | if (likely(!data_len)) |
6050 | break; | |
9a799d71 | 6051 | |
f43f313e BG |
6052 | if (unlikely(skb->no_fcs)) |
6053 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 | 6054 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 6055 | |
729739b7 AD |
6056 | i++; |
6057 | tx_desc++; | |
6058 | if (i == tx_ring->count) { | |
6059 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
6060 | i = 0; | |
6061 | } | |
9a799d71 | 6062 | |
d3d00239 | 6063 | #ifdef IXGBE_FCOE |
9e903e08 | 6064 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 6065 | #else |
9e903e08 | 6066 | size = skb_frag_size(frag); |
d3d00239 AD |
6067 | #endif |
6068 | data_len -= size; | |
9a799d71 | 6069 | |
729739b7 AD |
6070 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
6071 | DMA_TO_DEVICE); | |
6072 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6073 | goto dma_error; |
9a799d71 | 6074 | |
729739b7 AD |
6075 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6076 | dma_unmap_len_set(tx_buffer, len, size); | |
6077 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 6078 | |
729739b7 AD |
6079 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
6080 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 6081 | |
729739b7 AD |
6082 | frag++; |
6083 | } | |
9a799d71 | 6084 | |
729739b7 AD |
6085 | /* write last descriptor with RS and EOP bits */ |
6086 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
6087 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 6088 | |
091a6246 | 6089 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 6090 | |
d3d00239 AD |
6091 | /* set the timestamp */ |
6092 | first->time_stamp = jiffies; | |
9a799d71 AK |
6093 | |
6094 | /* | |
729739b7 AD |
6095 | * Force memory writes to complete before letting h/w know there |
6096 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
6097 | * memory model archs, such as IA-64). | |
6098 | * | |
6099 | * We also need this memory barrier to make certain all of the | |
6100 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
6101 | */ |
6102 | wmb(); | |
6103 | ||
d3d00239 AD |
6104 | /* set next_to_watch value indicating a packet is present */ |
6105 | first->next_to_watch = tx_desc; | |
6106 | ||
729739b7 AD |
6107 | i++; |
6108 | if (i == tx_ring->count) | |
6109 | i = 0; | |
6110 | ||
6111 | tx_ring->next_to_use = i; | |
6112 | ||
d3d00239 | 6113 | /* notify HW of packet */ |
84ea2591 | 6114 | writel(i, tx_ring->tail); |
d3d00239 AD |
6115 | |
6116 | return; | |
6117 | dma_error: | |
729739b7 | 6118 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
6119 | |
6120 | /* clear dma mappings for failed tx_buffer_info map */ | |
6121 | for (;;) { | |
729739b7 AD |
6122 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6123 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6124 | if (tx_buffer == first) | |
d3d00239 AD |
6125 | break; |
6126 | if (i == 0) | |
6127 | i = tx_ring->count; | |
6128 | i--; | |
6129 | } | |
6130 | ||
d3d00239 | 6131 | tx_ring->next_to_use = i; |
9a799d71 AK |
6132 | } |
6133 | ||
fd0db0ed | 6134 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6135 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6136 | { |
6137 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6138 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6139 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6140 | union { | |
6141 | unsigned char *network; | |
6142 | struct iphdr *ipv4; | |
6143 | struct ipv6hdr *ipv6; | |
6144 | } hdr; | |
ee9e0f0b | 6145 | struct tcphdr *th; |
905e4a41 | 6146 | __be16 vlan_id; |
c4cf55e5 | 6147 | |
69830529 AD |
6148 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6149 | if (!q_vector) | |
6150 | return; | |
6151 | ||
6152 | /* do nothing if sampling is disabled */ | |
6153 | if (!ring->atr_sample_rate) | |
d3ead241 | 6154 | return; |
c4cf55e5 | 6155 | |
69830529 | 6156 | ring->atr_count++; |
c4cf55e5 | 6157 | |
69830529 | 6158 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6159 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6160 | |
6161 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6162 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6163 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6164 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6165 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6166 | return; | |
ee9e0f0b | 6167 | |
fd0db0ed | 6168 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6169 | |
66f32a8b AD |
6170 | /* skip this packet since it is invalid or the socket is closing */ |
6171 | if (!th || th->fin) | |
69830529 AD |
6172 | return; |
6173 | ||
6174 | /* sample on all syn packets or once every atr sample count */ | |
6175 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6176 | return; | |
6177 | ||
6178 | /* reset sample count */ | |
6179 | ring->atr_count = 0; | |
6180 | ||
244e27ad | 6181 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6182 | |
6183 | /* | |
6184 | * src and dst are inverted, think how the receiver sees them | |
6185 | * | |
6186 | * The input is broken into two sections, a non-compressed section | |
6187 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6188 | * is XORed together and stored in the compressed dword. | |
6189 | */ | |
6190 | input.formatted.vlan_id = vlan_id; | |
6191 | ||
6192 | /* | |
6193 | * since src port and flex bytes occupy the same word XOR them together | |
6194 | * and write the value to source port portion of compressed dword | |
6195 | */ | |
244e27ad | 6196 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6197 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6198 | else | |
244e27ad | 6199 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6200 | common.port.dst ^= th->source; |
6201 | ||
244e27ad | 6202 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6203 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6204 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6205 | } else { | |
6206 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6207 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6208 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6209 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6210 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6211 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6212 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6213 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6214 | hdr.ipv6->daddr.s6_addr32[3]; | |
6215 | } | |
c4cf55e5 PWJ |
6216 | |
6217 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6218 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6219 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6220 | } |
6221 | ||
63544e9c | 6222 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6223 | { |
fc77dc3c | 6224 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6225 | /* Herbert's original patch had: |
6226 | * smp_mb__after_netif_stop_queue(); | |
6227 | * but since that doesn't exist yet, just open code it. */ | |
6228 | smp_mb(); | |
6229 | ||
6230 | /* We need to check again in a case another CPU has just | |
6231 | * made room available. */ | |
7d4987de | 6232 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6233 | return -EBUSY; |
6234 | ||
6235 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6236 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6237 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6238 | return 0; |
6239 | } | |
6240 | ||
82d4e46e | 6241 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6242 | { |
7d4987de | 6243 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6244 | return 0; |
fc77dc3c | 6245 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6246 | } |
6247 | ||
09a3b1f8 SH |
6248 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6249 | { | |
6250 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6251 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6252 | smp_processor_id(); | |
56075a98 | 6253 | #ifdef IXGBE_FCOE |
6440752c | 6254 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6255 | |
e5b64635 JF |
6256 | if (((protocol == htons(ETH_P_FCOE)) || |
6257 | (protocol == htons(ETH_P_FIP))) && | |
6258 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
c087663e AD |
6259 | struct ixgbe_ring_feature *f; |
6260 | ||
6261 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6262 | ||
6263 | while (txq >= f->indices) | |
6264 | txq -= f->indices; | |
e4b317e9 | 6265 | txq += adapter->ring_feature[RING_F_FCOE].offset; |
c087663e | 6266 | |
e5b64635 | 6267 | return txq; |
56075a98 JF |
6268 | } |
6269 | #endif | |
6270 | ||
fdd3d631 KK |
6271 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6272 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6273 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6274 | return txq; |
fdd3d631 | 6275 | } |
c4cf55e5 | 6276 | |
09a3b1f8 SH |
6277 | return skb_tx_hash(dev, skb); |
6278 | } | |
6279 | ||
fc77dc3c | 6280 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6281 | struct ixgbe_adapter *adapter, |
6282 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6283 | { |
d3d00239 | 6284 | struct ixgbe_tx_buffer *first; |
5f715823 | 6285 | int tso; |
d3d00239 | 6286 | u32 tx_flags = 0; |
a535c30e AD |
6287 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6288 | unsigned short f; | |
6289 | #endif | |
a535c30e | 6290 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6291 | __be16 protocol = skb->protocol; |
63544e9c | 6292 | u8 hdr_len = 0; |
5e09a105 | 6293 | |
a535c30e AD |
6294 | /* |
6295 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 6296 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
6297 | * + 2 desc gap to keep tail from touching head, |
6298 | * + 1 desc for context descriptor, | |
6299 | * otherwise try next time | |
6300 | */ | |
6301 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6302 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6303 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6304 | #else | |
6305 | count += skb_shinfo(skb)->nr_frags; | |
6306 | #endif | |
6307 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6308 | tx_ring->tx_stats.tx_busy++; | |
6309 | return NETDEV_TX_BUSY; | |
6310 | } | |
6311 | ||
fd0db0ed AD |
6312 | /* record the location of the first descriptor for this packet */ |
6313 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
6314 | first->skb = skb; | |
091a6246 AD |
6315 | first->bytecount = skb->len; |
6316 | first->gso_segs = 1; | |
fd0db0ed | 6317 | |
66f32a8b | 6318 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6319 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6320 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6321 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6322 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6323 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6324 | struct vlan_hdr *vhdr, _vhdr; | |
6325 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6326 | if (!vhdr) | |
6327 | goto out_drop; | |
6328 | ||
6329 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
6330 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
6331 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
6332 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
6333 | } | |
6334 | ||
aa7bd467 JK |
6335 | skb_tx_timestamp(skb); |
6336 | ||
3a6a4eda JK |
6337 | #ifdef CONFIG_IXGBE_PTP |
6338 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { | |
6339 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
6340 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
6341 | } | |
6342 | #endif | |
6343 | ||
9e0c5648 AD |
6344 | #ifdef CONFIG_PCI_IOV |
6345 | /* | |
6346 | * Use the l2switch_enable flag - would be false if the DMA | |
6347 | * Tx switch had been disabled. | |
6348 | */ | |
6349 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6350 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6351 | ||
6352 | #endif | |
32701dc2 | 6353 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 6354 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
6355 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6356 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 6357 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
6358 | tx_flags |= (skb->priority & 0x7) << |
6359 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
6360 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
6361 | struct vlan_ethhdr *vhdr; | |
6362 | if (skb_header_cloned(skb) && | |
6363 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6364 | goto out_drop; | |
6365 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6366 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6367 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6368 | } else { | |
6369 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6370 | } |
9a799d71 | 6371 | } |
eacd73f7 | 6372 | |
244e27ad AD |
6373 | /* record initial flags and protocol */ |
6374 | first->tx_flags = tx_flags; | |
6375 | first->protocol = protocol; | |
6376 | ||
eacd73f7 | 6377 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6378 | /* setup tx offload for FCoE */ |
6379 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
6380 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
244e27ad | 6381 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
6382 | if (tso < 0) |
6383 | goto out_drop; | |
9a799d71 | 6384 | |
66f32a8b | 6385 | goto xmit_fcoe; |
eacd73f7 | 6386 | } |
9a799d71 | 6387 | |
66f32a8b | 6388 | #endif /* IXGBE_FCOE */ |
244e27ad | 6389 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 6390 | if (tso < 0) |
897ab156 | 6391 | goto out_drop; |
244e27ad AD |
6392 | else if (!tso) |
6393 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
6394 | |
6395 | /* add the ATR filter if ATR is on */ | |
6396 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 6397 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
6398 | |
6399 | #ifdef IXGBE_FCOE | |
6400 | xmit_fcoe: | |
6401 | #endif /* IXGBE_FCOE */ | |
244e27ad | 6402 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
6403 | |
6404 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6405 | |
6406 | return NETDEV_TX_OK; | |
897ab156 AD |
6407 | |
6408 | out_drop: | |
fd0db0ed AD |
6409 | dev_kfree_skb_any(first->skb); |
6410 | first->skb = NULL; | |
6411 | ||
897ab156 | 6412 | return NETDEV_TX_OK; |
9a799d71 AK |
6413 | } |
6414 | ||
a50c29dd AD |
6415 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6416 | struct net_device *netdev) | |
84418e3b AD |
6417 | { |
6418 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6419 | struct ixgbe_ring *tx_ring; | |
6420 | ||
a50c29dd AD |
6421 | /* |
6422 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
6423 | * in order to meet this minimum size requirement. | |
6424 | */ | |
f73332fc SH |
6425 | if (unlikely(skb->len < 17)) { |
6426 | if (skb_pad(skb, 17 - skb->len)) | |
a50c29dd AD |
6427 | return NETDEV_TX_OK; |
6428 | skb->len = 17; | |
6429 | } | |
6430 | ||
84418e3b | 6431 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 6432 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6433 | } |
6434 | ||
9a799d71 AK |
6435 | /** |
6436 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6437 | * @netdev: network interface device structure | |
6438 | * @p: pointer to an address structure | |
6439 | * | |
6440 | * Returns 0 on success, negative on failure | |
6441 | **/ | |
6442 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6443 | { | |
6444 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6445 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6446 | struct sockaddr *addr = p; |
6447 | ||
6448 | if (!is_valid_ether_addr(addr->sa_data)) | |
6449 | return -EADDRNOTAVAIL; | |
6450 | ||
6451 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6452 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6453 | |
1cdd1ec8 GR |
6454 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6455 | IXGBE_RAH_AV); | |
9a799d71 AK |
6456 | |
6457 | return 0; | |
6458 | } | |
6459 | ||
6b73e10d BH |
6460 | static int |
6461 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6462 | { | |
6463 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6464 | struct ixgbe_hw *hw = &adapter->hw; | |
6465 | u16 value; | |
6466 | int rc; | |
6467 | ||
6468 | if (prtad != hw->phy.mdio.prtad) | |
6469 | return -EINVAL; | |
6470 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6471 | if (!rc) | |
6472 | rc = value; | |
6473 | return rc; | |
6474 | } | |
6475 | ||
6476 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6477 | u16 addr, u16 value) | |
6478 | { | |
6479 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6480 | struct ixgbe_hw *hw = &adapter->hw; | |
6481 | ||
6482 | if (prtad != hw->phy.mdio.prtad) | |
6483 | return -EINVAL; | |
6484 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6485 | } | |
6486 | ||
6487 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6488 | { | |
6489 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6490 | ||
3a6a4eda JK |
6491 | switch (cmd) { |
6492 | #ifdef CONFIG_IXGBE_PTP | |
6493 | case SIOCSHWTSTAMP: | |
6494 | return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd); | |
6495 | #endif | |
6496 | default: | |
6497 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6498 | } | |
6b73e10d BH |
6499 | } |
6500 | ||
0365e6e4 PW |
6501 | /** |
6502 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6503 | * netdev->dev_addrs |
0365e6e4 PW |
6504 | * @netdev: network interface device structure |
6505 | * | |
6506 | * Returns non-zero on failure | |
6507 | **/ | |
6508 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6509 | { | |
6510 | int err = 0; | |
6511 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6512 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6513 | ||
6514 | if (is_valid_ether_addr(mac->san_addr)) { | |
6515 | rtnl_lock(); | |
6516 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6517 | rtnl_unlock(); | |
6518 | } | |
6519 | return err; | |
6520 | } | |
6521 | ||
6522 | /** | |
6523 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6524 | * netdev->dev_addrs |
0365e6e4 PW |
6525 | * @netdev: network interface device structure |
6526 | * | |
6527 | * Returns non-zero on failure | |
6528 | **/ | |
6529 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6530 | { | |
6531 | int err = 0; | |
6532 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6533 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6534 | ||
6535 | if (is_valid_ether_addr(mac->san_addr)) { | |
6536 | rtnl_lock(); | |
6537 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6538 | rtnl_unlock(); | |
6539 | } | |
6540 | return err; | |
6541 | } | |
6542 | ||
9a799d71 AK |
6543 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6544 | /* | |
6545 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6546 | * without having to re-enable interrupts. It's not called while | |
6547 | * the interrupt routine is executing. | |
6548 | */ | |
6549 | static void ixgbe_netpoll(struct net_device *netdev) | |
6550 | { | |
6551 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6552 | int i; |
9a799d71 | 6553 | |
1a647bd2 AD |
6554 | /* if interface is down do nothing */ |
6555 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6556 | return; | |
6557 | ||
9a799d71 | 6558 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 | 6559 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
49c7ffbe AD |
6560 | for (i = 0; i < adapter->num_q_vectors; i++) |
6561 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
8f9a7167 PWJ |
6562 | } else { |
6563 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6564 | } | |
9a799d71 | 6565 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 6566 | } |
9a799d71 | 6567 | |
581330ba | 6568 | #endif |
de1036b1 ED |
6569 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6570 | struct rtnl_link_stats64 *stats) | |
6571 | { | |
6572 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6573 | int i; | |
6574 | ||
1a51502b | 6575 | rcu_read_lock(); |
de1036b1 | 6576 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6577 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6578 | u64 bytes, packets; |
6579 | unsigned int start; | |
6580 | ||
1a51502b ED |
6581 | if (ring) { |
6582 | do { | |
6583 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6584 | packets = ring->stats.packets; | |
6585 | bytes = ring->stats.bytes; | |
6586 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6587 | stats->rx_packets += packets; | |
6588 | stats->rx_bytes += bytes; | |
6589 | } | |
de1036b1 | 6590 | } |
1ac9ad13 ED |
6591 | |
6592 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6593 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6594 | u64 bytes, packets; | |
6595 | unsigned int start; | |
6596 | ||
6597 | if (ring) { | |
6598 | do { | |
6599 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6600 | packets = ring->stats.packets; | |
6601 | bytes = ring->stats.bytes; | |
6602 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6603 | stats->tx_packets += packets; | |
6604 | stats->tx_bytes += bytes; | |
6605 | } | |
6606 | } | |
1a51502b | 6607 | rcu_read_unlock(); |
de1036b1 ED |
6608 | /* following stats updated by ixgbe_watchdog_task() */ |
6609 | stats->multicast = netdev->stats.multicast; | |
6610 | stats->rx_errors = netdev->stats.rx_errors; | |
6611 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6612 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6613 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6614 | return stats; | |
6615 | } | |
6616 | ||
8af3c33f | 6617 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
6618 | /** |
6619 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
6620 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
6621 | * @tc: number of traffic classes currently enabled |
6622 | * | |
6623 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6624 | * 802.1Q priority maps to a packet buffer that exists. | |
6625 | */ | |
6626 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6627 | { | |
6628 | struct ixgbe_hw *hw = &adapter->hw; | |
6629 | u32 reg, rsave; | |
6630 | int i; | |
6631 | ||
6632 | /* 82598 have a static priority to TC mapping that can not | |
6633 | * be changed so no validation is needed. | |
6634 | */ | |
6635 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6636 | return; | |
6637 | ||
6638 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6639 | rsave = reg; | |
6640 | ||
6641 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6642 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6643 | ||
6644 | /* If up2tc is out of bounds default to zero */ | |
6645 | if (up2tc > tc) | |
6646 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6647 | } | |
6648 | ||
6649 | if (reg != rsave) | |
6650 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6651 | ||
6652 | return; | |
6653 | } | |
6654 | ||
02debdc9 AD |
6655 | /** |
6656 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
6657 | * @adapter: Pointer to adapter struct | |
6658 | * | |
6659 | * Populate the netdev user priority to tc map | |
6660 | */ | |
6661 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
6662 | { | |
6663 | struct net_device *dev = adapter->netdev; | |
6664 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
6665 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
6666 | u8 prio; | |
6667 | ||
6668 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
6669 | u8 tc = 0; | |
6670 | ||
6671 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
6672 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
6673 | else if (ets) | |
6674 | tc = ets->prio_tc[prio]; | |
6675 | ||
6676 | netdev_set_prio_tc_map(dev, prio, tc); | |
6677 | } | |
6678 | } | |
6679 | ||
49ce9c2c BH |
6680 | /** |
6681 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
6682 | * |
6683 | * @netdev: net device to configure | |
6684 | * @tc: number of traffic classes to enable | |
6685 | */ | |
6686 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6687 | { | |
8b1c0b24 JF |
6688 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6689 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6690 | |
e7589eab JF |
6691 | /* Multiple traffic classes requires multiple queues */ |
6692 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
6693 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
6694 | return -EINVAL; | |
6695 | } | |
8b1c0b24 JF |
6696 | |
6697 | /* Hardware supports up to 8 traffic classes */ | |
4de2a022 | 6698 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
6699 | (hw->mac.type == ixgbe_mac_82598EB && |
6700 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
6701 | return -EINVAL; |
6702 | ||
6703 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 6704 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
6705 | * hardware is not flexible enough to do this dynamically. |
6706 | */ | |
6707 | if (netif_running(dev)) | |
6708 | ixgbe_close(dev); | |
6709 | ixgbe_clear_interrupt_scheme(adapter); | |
6710 | ||
e7589eab | 6711 | if (tc) { |
8b1c0b24 | 6712 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
6713 | ixgbe_set_prio_tc_map(adapter); |
6714 | ||
e7589eab JF |
6715 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
6716 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6717 | ||
943561d3 AD |
6718 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
6719 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 6720 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 6721 | } |
e7589eab | 6722 | } else { |
8b1c0b24 | 6723 | netdev_reset_tc(dev); |
02debdc9 | 6724 | |
943561d3 AD |
6725 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
6726 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
6727 | |
6728 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
6729 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6730 | ||
6731 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6732 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6733 | } | |
6734 | ||
8b1c0b24 JF |
6735 | ixgbe_init_interrupt_scheme(adapter); |
6736 | ixgbe_validate_rtr(adapter, tc); | |
6737 | if (netif_running(dev)) | |
6738 | ixgbe_open(dev); | |
6739 | ||
6740 | return 0; | |
6741 | } | |
de1036b1 | 6742 | |
8af3c33f | 6743 | #endif /* CONFIG_IXGBE_DCB */ |
082757af DS |
6744 | void ixgbe_do_reset(struct net_device *netdev) |
6745 | { | |
6746 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6747 | ||
6748 | if (netif_running(netdev)) | |
6749 | ixgbe_reinit_locked(adapter); | |
6750 | else | |
6751 | ixgbe_reset(adapter); | |
6752 | } | |
6753 | ||
c8f44aff | 6754 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 6755 | netdev_features_t features) |
082757af DS |
6756 | { |
6757 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6758 | ||
082757af DS |
6759 | /* return error if RXHASH is being enabled when RSS is not supported */ |
6760 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
567d2de2 | 6761 | features &= ~NETIF_F_RXHASH; |
082757af DS |
6762 | |
6763 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
567d2de2 AD |
6764 | if (!(features & NETIF_F_RXCSUM)) |
6765 | features &= ~NETIF_F_LRO; | |
082757af | 6766 | |
567d2de2 AD |
6767 | /* Turn off LRO if not RSC capable */ |
6768 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
6769 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 6770 | |
567d2de2 | 6771 | return features; |
082757af DS |
6772 | } |
6773 | ||
c8f44aff | 6774 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 6775 | netdev_features_t features) |
082757af DS |
6776 | { |
6777 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 6778 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
6779 | bool need_reset = false; |
6780 | ||
082757af | 6781 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
6782 | if (!(features & NETIF_F_LRO)) { |
6783 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 6784 | need_reset = true; |
567d2de2 AD |
6785 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
6786 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
6787 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6788 | if (adapter->rx_itr_setting == 1 || | |
6789 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
6790 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
6791 | need_reset = true; | |
6792 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
6793 | e_info(probe, "rx-usecs set too low, " | |
6794 | "disabling RSC\n"); | |
082757af DS |
6795 | } |
6796 | } | |
6797 | ||
6798 | /* | |
6799 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
6800 | * the state changed, we need to reset. | |
6801 | */ | |
567d2de2 AD |
6802 | if (!(features & NETIF_F_NTUPLE)) { |
6803 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
6804 | /* turn off Flow Director, set ATR and reset */ | |
6805 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
6806 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
6807 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
6808 | need_reset = true; |
6809 | } | |
082757af | 6810 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; |
567d2de2 AD |
6811 | } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { |
6812 | /* turn off ATR, enable perfect filters and reset */ | |
6813 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6814 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
082757af DS |
6815 | need_reset = true; |
6816 | } | |
6817 | ||
146d4cc9 JF |
6818 | if (features & NETIF_F_HW_VLAN_RX) |
6819 | ixgbe_vlan_strip_enable(adapter); | |
6820 | else | |
6821 | ixgbe_vlan_strip_disable(adapter); | |
6822 | ||
3f2d1c0f BG |
6823 | if (changed & NETIF_F_RXALL) |
6824 | need_reset = true; | |
6825 | ||
567d2de2 | 6826 | netdev->features = features; |
082757af DS |
6827 | if (need_reset) |
6828 | ixgbe_do_reset(netdev); | |
6829 | ||
6830 | return 0; | |
082757af DS |
6831 | } |
6832 | ||
0f4b0add JF |
6833 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, |
6834 | struct net_device *dev, | |
6835 | unsigned char *addr, | |
6836 | u16 flags) | |
6837 | { | |
6838 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6839 | int err = -EOPNOTSUPP; | |
6840 | ||
6841 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6842 | pr_info("%s: FDB only supports static addresses\n", | |
6843 | ixgbe_driver_name); | |
6844 | return -EINVAL; | |
6845 | } | |
6846 | ||
6847 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6848 | if (is_unicast_ether_addr(addr)) | |
6849 | err = dev_uc_add_excl(dev, addr); | |
6850 | else if (is_multicast_ether_addr(addr)) | |
6851 | err = dev_mc_add_excl(dev, addr); | |
6852 | else | |
6853 | err = -EINVAL; | |
6854 | } | |
6855 | ||
6856 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
6857 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
6858 | err = 0; | |
6859 | ||
6860 | return err; | |
6861 | } | |
6862 | ||
6863 | static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, | |
6864 | struct net_device *dev, | |
6865 | unsigned char *addr) | |
6866 | { | |
6867 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6868 | int err = -EOPNOTSUPP; | |
6869 | ||
6870 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6871 | pr_info("%s: FDB only supports static addresses\n", | |
6872 | ixgbe_driver_name); | |
6873 | return -EINVAL; | |
6874 | } | |
6875 | ||
6876 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6877 | if (is_unicast_ether_addr(addr)) | |
6878 | err = dev_uc_del(dev, addr); | |
6879 | else if (is_multicast_ether_addr(addr)) | |
6880 | err = dev_mc_del(dev, addr); | |
6881 | else | |
6882 | err = -EINVAL; | |
6883 | } | |
6884 | ||
6885 | return err; | |
6886 | } | |
6887 | ||
6888 | static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, | |
6889 | struct netlink_callback *cb, | |
6890 | struct net_device *dev, | |
6891 | int idx) | |
6892 | { | |
6893 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6894 | ||
6895 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6896 | idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); | |
6897 | ||
6898 | return idx; | |
6899 | } | |
6900 | ||
0edc3527 | 6901 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6902 | .ndo_open = ixgbe_open, |
0edc3527 | 6903 | .ndo_stop = ixgbe_close, |
00829823 | 6904 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6905 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 6906 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6907 | .ndo_validate_addr = eth_validate_addr, |
6908 | .ndo_set_mac_address = ixgbe_set_mac, | |
6909 | .ndo_change_mtu = ixgbe_change_mtu, | |
6910 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6911 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6912 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6913 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6914 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6915 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6916 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 6917 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 6918 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 6919 | .ndo_get_stats64 = ixgbe_get_stats64, |
8af3c33f | 6920 | #ifdef CONFIG_IXGBE_DCB |
24095aa3 | 6921 | .ndo_setup_tc = ixgbe_setup_tc, |
8af3c33f | 6922 | #endif |
0edc3527 SH |
6923 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6924 | .ndo_poll_controller = ixgbe_netpoll, | |
6925 | #endif | |
332d4a7d YZ |
6926 | #ifdef IXGBE_FCOE |
6927 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 6928 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 6929 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
6930 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6931 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6932 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 6933 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 6934 | #endif /* IXGBE_FCOE */ |
082757af DS |
6935 | .ndo_set_features = ixgbe_set_features, |
6936 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add JF |
6937 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
6938 | .ndo_fdb_del = ixgbe_ndo_fdb_del, | |
6939 | .ndo_fdb_dump = ixgbe_ndo_fdb_dump, | |
0edc3527 SH |
6940 | }; |
6941 | ||
1cdd1ec8 | 6942 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
567d2de2 | 6943 | const struct ixgbe_info *ii) |
1cdd1ec8 GR |
6944 | { |
6945 | #ifdef CONFIG_PCI_IOV | |
6946 | struct ixgbe_hw *hw = &adapter->hw; | |
1cdd1ec8 | 6947 | |
c6bda30a | 6948 | if (hw->mac.type == ixgbe_mac_82598EB) |
1cdd1ec8 GR |
6949 | return; |
6950 | ||
6951 | /* The 82599 supports up to 64 VFs per physical function | |
6952 | * but this implementation limits allocation to 63 so that | |
6953 | * basic networking resources are still available to the | |
6b42a9c5 GR |
6954 | * physical function. If the user requests greater thn |
6955 | * 63 VFs then it is an error - reset to default of zero. | |
1cdd1ec8 | 6956 | */ |
6b42a9c5 | 6957 | adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs; |
c6bda30a | 6958 | ixgbe_enable_sriov(adapter, ii); |
1cdd1ec8 GR |
6959 | #endif /* CONFIG_PCI_IOV */ |
6960 | } | |
6961 | ||
8e2813f5 JK |
6962 | /** |
6963 | * ixgbe_wol_supported - Check whether device supports WoL | |
6964 | * @hw: hw specific details | |
6965 | * @device_id: the device ID | |
6966 | * @subdev_id: the subsystem device ID | |
6967 | * | |
6968 | * This function is used by probe and ethtool to determine | |
6969 | * which devices have WoL support | |
6970 | * | |
6971 | **/ | |
6972 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
6973 | u16 subdevice_id) | |
6974 | { | |
6975 | struct ixgbe_hw *hw = &adapter->hw; | |
6976 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
6977 | int is_wol_supported = 0; | |
6978 | ||
6979 | switch (device_id) { | |
6980 | case IXGBE_DEV_ID_82599_SFP: | |
6981 | /* Only these subdevices could supports WOL */ | |
6982 | switch (subdevice_id) { | |
6983 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
6984 | /* only support first port */ | |
6985 | if (hw->bus.func != 0) | |
6986 | break; | |
6987 | case IXGBE_SUBDEV_ID_82599_SFP: | |
6988 | is_wol_supported = 1; | |
6989 | break; | |
6990 | } | |
6991 | break; | |
6992 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: | |
6993 | /* All except this subdevice support WOL */ | |
6994 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
6995 | is_wol_supported = 1; | |
6996 | break; | |
6997 | case IXGBE_DEV_ID_82599_KX4: | |
6998 | is_wol_supported = 1; | |
6999 | break; | |
7000 | case IXGBE_DEV_ID_X540T: | |
7001 | /* check eeprom to see if enabled wol */ | |
7002 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
7003 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
7004 | (hw->bus.func == 0))) { | |
7005 | is_wol_supported = 1; | |
7006 | } | |
7007 | break; | |
7008 | } | |
7009 | ||
7010 | return is_wol_supported; | |
7011 | } | |
7012 | ||
9a799d71 AK |
7013 | /** |
7014 | * ixgbe_probe - Device Initialization Routine | |
7015 | * @pdev: PCI device information struct | |
7016 | * @ent: entry in ixgbe_pci_tbl | |
7017 | * | |
7018 | * Returns 0 on success, negative on failure | |
7019 | * | |
7020 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7021 | * The OS initialization, configuring of the adapter private structure, | |
7022 | * and a hardware reset occur. | |
7023 | **/ | |
7024 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7025 | const struct pci_device_id *ent) |
9a799d71 AK |
7026 | { |
7027 | struct net_device *netdev; | |
7028 | struct ixgbe_adapter *adapter = NULL; | |
7029 | struct ixgbe_hw *hw; | |
7030 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7031 | static int cards_found; |
7032 | int i, err, pci_using_dac; | |
289700db | 7033 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7034 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7035 | #ifdef IXGBE_FCOE |
7036 | u16 device_caps; | |
7037 | #endif | |
289700db | 7038 | u32 eec; |
9a799d71 | 7039 | |
bded64a7 AG |
7040 | /* Catch broken hardware that put the wrong VF device ID in |
7041 | * the PCIe SR-IOV capability. | |
7042 | */ | |
7043 | if (pdev->is_virtfn) { | |
7044 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7045 | pci_name(pdev), pdev->vendor, pdev->device); | |
7046 | return -EINVAL; | |
7047 | } | |
7048 | ||
9ce77666 | 7049 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7050 | if (err) |
7051 | return err; | |
7052 | ||
1b507730 NN |
7053 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7054 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7055 | pci_using_dac = 1; |
7056 | } else { | |
1b507730 | 7057 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7058 | if (err) { |
1b507730 NN |
7059 | err = dma_set_coherent_mask(&pdev->dev, |
7060 | DMA_BIT_MASK(32)); | |
9a799d71 | 7061 | if (err) { |
b8bc0421 DC |
7062 | dev_err(&pdev->dev, |
7063 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7064 | goto err_dma; |
7065 | } | |
7066 | } | |
7067 | pci_using_dac = 0; | |
7068 | } | |
7069 | ||
9ce77666 | 7070 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7071 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7072 | if (err) { |
b8bc0421 DC |
7073 | dev_err(&pdev->dev, |
7074 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7075 | goto err_pci_reg; |
7076 | } | |
7077 | ||
19d5afd4 | 7078 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7079 | |
9a799d71 | 7080 | pci_set_master(pdev); |
fb3b27bc | 7081 | pci_save_state(pdev); |
9a799d71 | 7082 | |
e901acd6 JF |
7083 | #ifdef CONFIG_IXGBE_DCB |
7084 | indices *= MAX_TRAFFIC_CLASS; | |
7085 | #endif | |
7086 | ||
c85a2618 | 7087 | if (ii->mac == ixgbe_mac_82598EB) |
d411a936 AD |
7088 | #ifdef CONFIG_IXGBE_DCB |
7089 | indices = min_t(unsigned int, indices, MAX_TRAFFIC_CLASS * 4); | |
7090 | #else | |
c85a2618 | 7091 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); |
d411a936 | 7092 | #endif |
c85a2618 JF |
7093 | else |
7094 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7095 | ||
e901acd6 | 7096 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7097 | indices += min_t(unsigned int, num_possible_cpus(), |
7098 | IXGBE_MAX_FCOE_INDICES); | |
7099 | #endif | |
c85a2618 | 7100 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7101 | if (!netdev) { |
7102 | err = -ENOMEM; | |
7103 | goto err_alloc_etherdev; | |
7104 | } | |
7105 | ||
9a799d71 AK |
7106 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7107 | ||
9a799d71 | 7108 | adapter = netdev_priv(netdev); |
c60fbb00 | 7109 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7110 | |
7111 | adapter->netdev = netdev; | |
7112 | adapter->pdev = pdev; | |
7113 | hw = &adapter->hw; | |
7114 | hw->back = adapter; | |
b3f4d599 | 7115 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 7116 | |
05857980 | 7117 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7118 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7119 | if (!hw->hw_addr) { |
7120 | err = -EIO; | |
7121 | goto err_ioremap; | |
7122 | } | |
7123 | ||
7124 | for (i = 1; i <= 5; i++) { | |
7125 | if (pci_resource_len(pdev, i) == 0) | |
7126 | continue; | |
7127 | } | |
7128 | ||
0edc3527 | 7129 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7130 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7131 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7132 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7133 | |
9a799d71 AK |
7134 | adapter->bd_number = cards_found; |
7135 | ||
9a799d71 AK |
7136 | /* Setup hw api */ |
7137 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7138 | hw->mac.type = ii->mac; |
9a799d71 | 7139 | |
c44ade9e JB |
7140 | /* EEPROM */ |
7141 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7142 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7143 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7144 | if (!(eec & (1 << 8))) | |
7145 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7146 | ||
7147 | /* PHY */ | |
7148 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7149 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7150 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7151 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7152 | hw->phy.mdio.mmds = 0; | |
7153 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7154 | hw->phy.mdio.dev = netdev; | |
7155 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7156 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7157 | |
8ca783ab | 7158 | ii->get_invariants(hw); |
9a799d71 AK |
7159 | |
7160 | /* setup the private structure */ | |
7161 | err = ixgbe_sw_init(adapter); | |
7162 | if (err) | |
7163 | goto err_sw_init; | |
7164 | ||
e86bff0e | 7165 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7166 | switch (adapter->hw.mac.type) { |
7167 | case ixgbe_mac_82599EB: | |
7168 | case ixgbe_mac_X540: | |
e86bff0e | 7169 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7170 | break; |
7171 | default: | |
7172 | break; | |
7173 | } | |
e86bff0e | 7174 | |
bf069c97 DS |
7175 | /* |
7176 | * If there is a fan on this device and it has failed log the | |
7177 | * failure. | |
7178 | */ | |
7179 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7180 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7181 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7182 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7183 | } |
7184 | ||
8ef78adc PWJ |
7185 | if (allow_unsupported_sfp) |
7186 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7187 | ||
c44ade9e | 7188 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7189 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7190 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7191 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7192 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7193 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7194 | err = 0; |
7195 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7196 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7197 | "module type was detected.\n"); |
7198 | e_dev_err("Reload the driver after installing a supported " | |
7199 | "module.\n"); | |
04f165ef PW |
7200 | goto err_sw_init; |
7201 | } else if (err) { | |
849c4542 | 7202 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7203 | goto err_sw_init; |
7204 | } | |
7205 | ||
1cdd1ec8 GR |
7206 | ixgbe_probe_vf(adapter, ii); |
7207 | ||
396e799c | 7208 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7209 | NETIF_F_IP_CSUM | |
082757af | 7210 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7211 | NETIF_F_HW_VLAN_TX | |
7212 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7213 | NETIF_F_HW_VLAN_FILTER | |
7214 | NETIF_F_TSO | | |
7215 | NETIF_F_TSO6 | | |
082757af DS |
7216 | NETIF_F_RXHASH | |
7217 | NETIF_F_RXCSUM; | |
9a799d71 | 7218 | |
082757af | 7219 | netdev->hw_features = netdev->features; |
ad31c402 | 7220 | |
58be7666 DS |
7221 | switch (adapter->hw.mac.type) { |
7222 | case ixgbe_mac_82599EB: | |
7223 | case ixgbe_mac_X540: | |
45a5ead0 | 7224 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7225 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7226 | NETIF_F_NTUPLE; | |
58be7666 DS |
7227 | break; |
7228 | default: | |
7229 | break; | |
7230 | } | |
45a5ead0 | 7231 | |
3f2d1c0f BG |
7232 | netdev->hw_features |= NETIF_F_RXALL; |
7233 | ||
ad31c402 JK |
7234 | netdev->vlan_features |= NETIF_F_TSO; |
7235 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7236 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7237 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7238 | netdev->vlan_features |= NETIF_F_SG; |
7239 | ||
01789349 | 7240 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7241 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7242 | |
7a6b6f51 | 7243 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7244 | netdev->dcbnl_ops = &dcbnl_ops; |
7245 | #endif | |
7246 | ||
eacd73f7 | 7247 | #ifdef IXGBE_FCOE |
0d551589 | 7248 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7249 | if (hw->mac.ops.get_device_caps) { |
7250 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7251 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7252 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7253 | } |
7254 | } | |
5e09d7f6 YZ |
7255 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7256 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7257 | netdev->vlan_features |= NETIF_F_FSO; | |
7258 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7259 | } | |
eacd73f7 | 7260 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7261 | if (pci_using_dac) { |
9a799d71 | 7262 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7263 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7264 | } | |
9a799d71 | 7265 | |
082757af DS |
7266 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7267 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7268 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7269 | netdev->features |= NETIF_F_LRO; |
7270 | ||
9a799d71 | 7271 | /* make sure the EEPROM is good */ |
c44ade9e | 7272 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7273 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7274 | err = -EIO; |
35937c05 | 7275 | goto err_sw_init; |
9a799d71 AK |
7276 | } |
7277 | ||
7278 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7279 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7280 | ||
c44ade9e | 7281 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7282 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7283 | err = -EIO; |
35937c05 | 7284 | goto err_sw_init; |
9a799d71 AK |
7285 | } |
7286 | ||
7086400d | 7287 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7288 | (unsigned long) adapter); |
9a799d71 | 7289 | |
7086400d AD |
7290 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7291 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7292 | |
021230d4 AV |
7293 | err = ixgbe_init_interrupt_scheme(adapter); |
7294 | if (err) | |
7295 | goto err_sw_init; | |
9a799d71 | 7296 | |
082757af DS |
7297 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7298 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7299 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7300 | } |
67a74ee2 | 7301 | |
8e2813f5 | 7302 | /* WOL not supported for all devices */ |
c23f5b6b | 7303 | adapter->wol = 0; |
8e2813f5 JK |
7304 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
7305 | if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device)) | |
9417c464 | 7306 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 7307 | |
e8e26350 PW |
7308 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7309 | ||
3a6a4eda JK |
7310 | #ifdef CONFIG_IXGBE_PTP |
7311 | ixgbe_ptp_init(adapter); | |
7312 | #endif /* CONFIG_IXGBE_PTP*/ | |
7313 | ||
15e5209f ET |
7314 | /* save off EEPROM version number */ |
7315 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7316 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7317 | ||
04f165ef PW |
7318 | /* pick up the PCI bus settings for reporting later */ |
7319 | hw->mac.ops.get_bus_info(hw); | |
7320 | ||
9a799d71 | 7321 | /* print bus type/speed/width info */ |
849c4542 | 7322 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7323 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7324 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7325 | "Unknown"), |
7326 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7327 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7328 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7329 | "Unknown"), | |
7330 | netdev->dev_addr); | |
289700db DS |
7331 | |
7332 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7333 | if (err) | |
9fe93afd | 7334 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7335 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7336 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7337 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7338 | part_str); |
e8e26350 | 7339 | else |
289700db DS |
7340 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7341 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7342 | |
e8e26350 | 7343 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7344 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7345 | "not sufficient for optimal performance.\n"); | |
7346 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7347 | "is required.\n"); | |
0c254d86 AK |
7348 | } |
7349 | ||
9a799d71 | 7350 | /* reset the hardware with the new settings */ |
794caeb2 | 7351 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7352 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7353 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7354 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7355 | "Please be aware there may be issues associated " | |
7356 | "with your hardware. If you are experiencing " | |
7357 | "problems please contact your Intel or hardware " | |
7358 | "representative who provided you with this " | |
7359 | "hardware.\n"); | |
794caeb2 | 7360 | } |
9a799d71 AK |
7361 | strcpy(netdev->name, "eth%d"); |
7362 | err = register_netdev(netdev); | |
7363 | if (err) | |
7364 | goto err_register; | |
7365 | ||
93d3ce8f ET |
7366 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7367 | if (hw->mac.ops.disable_tx_laser && | |
7368 | ((hw->phy.multispeed_fiber) || | |
7369 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
7370 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
7371 | hw->mac.ops.disable_tx_laser(hw); | |
7372 | ||
54386467 JB |
7373 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7374 | netif_carrier_off(netdev); | |
7375 | ||
5dd2d332 | 7376 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7377 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7378 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7379 | ixgbe_setup_dca(adapter); |
7380 | } | |
7381 | #endif | |
1cdd1ec8 | 7382 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7383 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7384 | for (i = 0; i < adapter->num_vfs; i++) |
7385 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7386 | } | |
7387 | ||
2466dd9c JK |
7388 | /* firmware requires driver version to be 0xFFFFFFFF |
7389 | * since os does not support feature | |
7390 | */ | |
9612de92 | 7391 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
7392 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
7393 | 0xFF); | |
9612de92 | 7394 | |
0365e6e4 PW |
7395 | /* add san mac addr to netdev */ |
7396 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7397 | |
ea81875a | 7398 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 | 7399 | cards_found++; |
3ca8bc6d | 7400 | |
1210982b | 7401 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
7402 | if (ixgbe_sysfs_init(adapter)) |
7403 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 7404 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7405 | |
9a799d71 AK |
7406 | return 0; |
7407 | ||
7408 | err_register: | |
5eba3699 | 7409 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7410 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 7411 | err_sw_init: |
1cdd1ec8 GR |
7412 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7413 | ixgbe_disable_sriov(adapter); | |
7086400d | 7414 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7415 | iounmap(hw->hw_addr); |
7416 | err_ioremap: | |
7417 | free_netdev(netdev); | |
7418 | err_alloc_etherdev: | |
e8e9f696 JP |
7419 | pci_release_selected_regions(pdev, |
7420 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7421 | err_pci_reg: |
7422 | err_dma: | |
7423 | pci_disable_device(pdev); | |
7424 | return err; | |
7425 | } | |
7426 | ||
7427 | /** | |
7428 | * ixgbe_remove - Device Removal Routine | |
7429 | * @pdev: PCI device information struct | |
7430 | * | |
7431 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7432 | * that it should release a PCI device. The could be caused by a | |
7433 | * Hot-Plug event, or because the driver is going to be removed from | |
7434 | * memory. | |
7435 | **/ | |
7436 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7437 | { | |
c60fbb00 AD |
7438 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7439 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7440 | |
7441 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7442 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7443 | |
3a6a4eda JK |
7444 | #ifdef CONFIG_IXGBE_PTP |
7445 | ixgbe_ptp_stop(adapter); | |
7446 | #endif | |
7447 | ||
5dd2d332 | 7448 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7449 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7450 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7451 | dca_remove_requester(&pdev->dev); | |
7452 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7453 | } | |
7454 | ||
7455 | #endif | |
1210982b | 7456 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 7457 | ixgbe_sysfs_exit(adapter); |
1210982b | 7458 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7459 | |
332d4a7d YZ |
7460 | #ifdef IXGBE_FCOE |
7461 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7462 | ixgbe_cleanup_fcoe(adapter); | |
7463 | ||
7464 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7465 | |
7466 | /* remove the added san mac */ | |
7467 | ixgbe_del_sanmac_netdev(netdev); | |
7468 | ||
c4900be0 DS |
7469 | if (netdev->reg_state == NETREG_REGISTERED) |
7470 | unregister_netdev(netdev); | |
9a799d71 | 7471 | |
c6bda30a GR |
7472 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
7473 | if (!(ixgbe_check_vf_assignment(adapter))) | |
7474 | ixgbe_disable_sriov(adapter); | |
7475 | else | |
7476 | e_dev_warn("Unloading driver while VFs are assigned " | |
7477 | "- VFs will not be deallocated\n"); | |
7478 | } | |
1cdd1ec8 | 7479 | |
7a921c93 | 7480 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7481 | |
021230d4 | 7482 | ixgbe_release_hw_control(adapter); |
9a799d71 | 7483 | |
2b1588c3 AD |
7484 | #ifdef CONFIG_DCB |
7485 | kfree(adapter->ixgbe_ieee_pfc); | |
7486 | kfree(adapter->ixgbe_ieee_ets); | |
7487 | ||
7488 | #endif | |
9a799d71 | 7489 | iounmap(adapter->hw.hw_addr); |
9ce77666 | 7490 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7491 | IORESOURCE_MEM)); |
9a799d71 | 7492 | |
849c4542 | 7493 | e_dev_info("complete\n"); |
021230d4 | 7494 | |
9a799d71 AK |
7495 | free_netdev(netdev); |
7496 | ||
19d5afd4 | 7497 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7498 | |
9a799d71 AK |
7499 | pci_disable_device(pdev); |
7500 | } | |
7501 | ||
7502 | /** | |
7503 | * ixgbe_io_error_detected - called when PCI error is detected | |
7504 | * @pdev: Pointer to PCI device | |
7505 | * @state: The current pci connection state | |
7506 | * | |
7507 | * This function is called after a PCI bus error affecting | |
7508 | * this device has been detected. | |
7509 | */ | |
7510 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7511 | pci_channel_state_t state) |
9a799d71 | 7512 | { |
c60fbb00 AD |
7513 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7514 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7515 | |
83c61fa9 GR |
7516 | #ifdef CONFIG_PCI_IOV |
7517 | struct pci_dev *bdev, *vfdev; | |
7518 | u32 dw0, dw1, dw2, dw3; | |
7519 | int vf, pos; | |
7520 | u16 req_id, pf_func; | |
7521 | ||
7522 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7523 | adapter->num_vfs == 0) | |
7524 | goto skip_bad_vf_detection; | |
7525 | ||
7526 | bdev = pdev->bus->self; | |
7527 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
7528 | bdev = bdev->bus->self; | |
7529 | ||
7530 | if (!bdev) | |
7531 | goto skip_bad_vf_detection; | |
7532 | ||
7533 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
7534 | if (!pos) | |
7535 | goto skip_bad_vf_detection; | |
7536 | ||
7537 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
7538 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
7539 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
7540 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
7541 | ||
7542 | req_id = dw1 >> 16; | |
7543 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
7544 | if (!(req_id & 0x0080)) | |
7545 | goto skip_bad_vf_detection; | |
7546 | ||
7547 | pf_func = req_id & 0x01; | |
7548 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
7549 | unsigned int device_id; | |
7550 | ||
7551 | vf = (req_id & 0x7F) >> 1; | |
7552 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
7553 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
7554 | "%8.8x\tdw3: %8.8x\n", | |
7555 | dw0, dw1, dw2, dw3); | |
7556 | switch (adapter->hw.mac.type) { | |
7557 | case ixgbe_mac_82599EB: | |
7558 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
7559 | break; | |
7560 | case ixgbe_mac_X540: | |
7561 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
7562 | break; | |
7563 | default: | |
7564 | device_id = 0; | |
7565 | break; | |
7566 | } | |
7567 | ||
7568 | /* Find the pci device of the offending VF */ | |
7569 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL); | |
7570 | while (vfdev) { | |
7571 | if (vfdev->devfn == (req_id & 0xFF)) | |
7572 | break; | |
7573 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, | |
7574 | device_id, vfdev); | |
7575 | } | |
7576 | /* | |
7577 | * There's a slim chance the VF could have been hot plugged, | |
7578 | * so if it is no longer present we don't need to issue the | |
7579 | * VFLR. Just clean up the AER in that case. | |
7580 | */ | |
7581 | if (vfdev) { | |
7582 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
7583 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
7584 | } | |
7585 | ||
7586 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
7587 | } | |
7588 | ||
7589 | /* | |
7590 | * Even though the error may have occurred on the other port | |
7591 | * we still need to increment the vf error reference count for | |
7592 | * both ports because the I/O resume function will be called | |
7593 | * for both of them. | |
7594 | */ | |
7595 | adapter->vferr_refcount++; | |
7596 | ||
7597 | return PCI_ERS_RESULT_RECOVERED; | |
7598 | ||
7599 | skip_bad_vf_detection: | |
7600 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
7601 | netif_device_detach(netdev); |
7602 | ||
3044b8d1 BL |
7603 | if (state == pci_channel_io_perm_failure) |
7604 | return PCI_ERS_RESULT_DISCONNECT; | |
7605 | ||
9a799d71 AK |
7606 | if (netif_running(netdev)) |
7607 | ixgbe_down(adapter); | |
7608 | pci_disable_device(pdev); | |
7609 | ||
b4617240 | 7610 | /* Request a slot reset. */ |
9a799d71 AK |
7611 | return PCI_ERS_RESULT_NEED_RESET; |
7612 | } | |
7613 | ||
7614 | /** | |
7615 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7616 | * @pdev: Pointer to PCI device | |
7617 | * | |
7618 | * Restart the card from scratch, as if from a cold-boot. | |
7619 | */ | |
7620 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7621 | { | |
c60fbb00 | 7622 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7623 | pci_ers_result_t result; |
7624 | int err; | |
9a799d71 | 7625 | |
9ce77666 | 7626 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7627 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7628 | result = PCI_ERS_RESULT_DISCONNECT; |
7629 | } else { | |
7630 | pci_set_master(pdev); | |
7631 | pci_restore_state(pdev); | |
c0e1f68b | 7632 | pci_save_state(pdev); |
9a799d71 | 7633 | |
dd4d8ca6 | 7634 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7635 | |
6fabd715 | 7636 | ixgbe_reset(adapter); |
88512539 | 7637 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7638 | result = PCI_ERS_RESULT_RECOVERED; |
7639 | } | |
7640 | ||
7641 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7642 | if (err) { | |
849c4542 ET |
7643 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7644 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7645 | /* non-fatal, continue */ |
7646 | } | |
9a799d71 | 7647 | |
6fabd715 | 7648 | return result; |
9a799d71 AK |
7649 | } |
7650 | ||
7651 | /** | |
7652 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7653 | * @pdev: Pointer to PCI device | |
7654 | * | |
7655 | * This callback is called when the error recovery driver tells us that | |
7656 | * its OK to resume normal operation. | |
7657 | */ | |
7658 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7659 | { | |
c60fbb00 AD |
7660 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7661 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7662 | |
83c61fa9 GR |
7663 | #ifdef CONFIG_PCI_IOV |
7664 | if (adapter->vferr_refcount) { | |
7665 | e_info(drv, "Resuming after VF err\n"); | |
7666 | adapter->vferr_refcount--; | |
7667 | return; | |
7668 | } | |
7669 | ||
7670 | #endif | |
c7ccde0f AD |
7671 | if (netif_running(netdev)) |
7672 | ixgbe_up(adapter); | |
9a799d71 AK |
7673 | |
7674 | netif_device_attach(netdev); | |
9a799d71 AK |
7675 | } |
7676 | ||
7677 | static struct pci_error_handlers ixgbe_err_handler = { | |
7678 | .error_detected = ixgbe_io_error_detected, | |
7679 | .slot_reset = ixgbe_io_slot_reset, | |
7680 | .resume = ixgbe_io_resume, | |
7681 | }; | |
7682 | ||
7683 | static struct pci_driver ixgbe_driver = { | |
7684 | .name = ixgbe_driver_name, | |
7685 | .id_table = ixgbe_pci_tbl, | |
7686 | .probe = ixgbe_probe, | |
7687 | .remove = __devexit_p(ixgbe_remove), | |
7688 | #ifdef CONFIG_PM | |
7689 | .suspend = ixgbe_suspend, | |
7690 | .resume = ixgbe_resume, | |
7691 | #endif | |
7692 | .shutdown = ixgbe_shutdown, | |
7693 | .err_handler = &ixgbe_err_handler | |
7694 | }; | |
7695 | ||
7696 | /** | |
7697 | * ixgbe_init_module - Driver Registration Routine | |
7698 | * | |
7699 | * ixgbe_init_module is the first routine called when the driver is | |
7700 | * loaded. All it does is register with the PCI subsystem. | |
7701 | **/ | |
7702 | static int __init ixgbe_init_module(void) | |
7703 | { | |
7704 | int ret; | |
c7689578 | 7705 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7706 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7707 | |
5dd2d332 | 7708 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7709 | dca_register_notify(&dca_notifier); |
bd0362dd | 7710 | #endif |
5dd2d332 | 7711 | |
9a799d71 AK |
7712 | ret = pci_register_driver(&ixgbe_driver); |
7713 | return ret; | |
7714 | } | |
b4617240 | 7715 | |
9a799d71 AK |
7716 | module_init(ixgbe_init_module); |
7717 | ||
7718 | /** | |
7719 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7720 | * | |
7721 | * ixgbe_exit_module is called just before the driver is removed | |
7722 | * from memory. | |
7723 | **/ | |
7724 | static void __exit ixgbe_exit_module(void) | |
7725 | { | |
5dd2d332 | 7726 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7727 | dca_unregister_notify(&dca_notifier); |
7728 | #endif | |
9a799d71 | 7729 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7730 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7731 | } |
bd0362dd | 7732 | |
5dd2d332 | 7733 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7734 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7735 | void *p) |
bd0362dd JC |
7736 | { |
7737 | int ret_val; | |
7738 | ||
7739 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7740 | __ixgbe_notify_dca); |
bd0362dd JC |
7741 | |
7742 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7743 | } | |
b453368d | 7744 | |
5dd2d332 | 7745 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7746 | |
9a799d71 AK |
7747 | module_exit(ixgbe_exit_module); |
7748 | ||
7749 | /* ixgbe_main.c */ |