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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
75e3d3c6 66#define MAJ 3
eef4560f
DS		 67#define MIN 9
68#define BUILD 15
75e3d3c6 69#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 70 __stringify(BUILD) "-k"
9c8eb720 71const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 72static const char ixgbe_copyright[] =
94971820 73 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 74
75static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 76 [board_82598] = &ixgbe_82598_info,
e8e26350 77 [board_82599] = &ixgbe_82599_info,
fe15e8e1 78 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 79};
80
81/* ixgbe_pci_tbl - PCI Device ID Table
82 *
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
85 *
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
88 */
a3aa1884 89static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 119 /* required last entry */
120 {0, }
121};
122MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
123
5dd2d332 124#ifdef CONFIG_IXGBE_DCA
bd0362dd 125static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 126 void *p);
bd0362dd
JC		 127static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
129 .next = NULL,
130 .priority = 0
131};
132#endif
133
1cdd1ec8
GR		 134#ifdef CONFIG_PCI_IOV
135static unsigned int max_vfs;
136module_param(max_vfs, uint, 0);
e8e9f696 137MODULE_PARM_DESC(max_vfs,
6b42a9c5 138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 139#endif /* CONFIG_PCI_IOV */
140
8ef78adc
PWJ		 141static unsigned int allow_unsupported_sfp;
142module_param(allow_unsupported_sfp, uint, 0);
143MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
145
b3f4d599 146#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147static int debug = -1;
148module_param(debug, int, 0);
149MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
150
9a799d71
AK		 151MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153MODULE_LICENSE("GPL");
154MODULE_VERSION(DRV_VERSION);
155
7086400d
AD		 156static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
157{
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
161}
162
163static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
164{
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
166
52f33af8 167 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
170}
171
dcd79aeb
TI		 172struct ixgbe_reg_info {
173 u32 ofs;
174 char *name;
175};
176
177static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
178
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
183
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
186
187 /* RX Registers */
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
196
197 /* TX Registers */
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
204
205 /* List Terminator */
206 {}
207};
208
209
210/*
211 * ixgbe_regdump - register printout routine
212 */
213static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
214{
215 int i = 0, j = 0;
216 char rname[16];
217 u32 regs[64];
218
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
223 break;
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
227 break;
228 case IXGBE_RDLEN(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
231 break;
232 case IXGBE_RDH(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
235 break;
236 case IXGBE_RDT(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
239 break;
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
243 break;
244 case IXGBE_RDBAL(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
247 break;
248 case IXGBE_RDBAH(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
251 break;
252 case IXGBE_TDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
255 break;
256 case IXGBE_TDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
259 break;
260 case IXGBE_TDLEN(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
263 break;
264 case IXGBE_TDH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
267 break;
268 case IXGBE_TDT(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
271 break;
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
275 break;
276 default:
c7689578 277 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 278 IXGBE_READ_REG(hw, reginfo->ofs));
279 return;
280 }
281
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 284 pr_err("%-15s", rname);
dcd79aeb 285 for (j = 0; j < 8; j++)
c7689578
JP		 286 pr_cont(" %08x", regs[i*8+j]);
287 pr_cont("\n");
dcd79aeb
TI		 288 }
289
290}
291
292/*
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
294 */
295static void ixgbe_dump(struct ixgbe_adapter *adapter)
296{
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
300 int n = 0;
301 struct ixgbe_ring *tx_ring;
729739b7 302 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
308 u32 staterr;
309 int i = 0;
310
311 if (!netif_msg_hw(adapter))
312 return;
313
314 /* Print netdevice Info */
315 if (netdev) {
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 317 pr_info("Device Name state "
dcd79aeb 318 "trans_start last_rx\n");
c7689578
JP		 319 pr_info("%-15s %016lX %016lX %016lX\n",
320 netdev->name,
321 netdev->state,
322 netdev->trans_start,
323 netdev->last_rx);
dcd79aeb
TI		 324 }
325
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 328 pr_info(" Register Name Value\n");
dcd79aeb
TI		 329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
332 }
333
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
336 goto exit;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 339 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 340 for (n = 0; n < adapter->num_tx_queues; n++) {
341 tx_ring = adapter->tx_ring[n];
729739b7 342 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 343 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 344 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 345 (u64)dma_unmap_addr(tx_buffer, dma),
346 dma_unmap_len(tx_buffer, len),
347 tx_buffer->next_to_watch,
348 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 349 }
350
351 /* Print TX Rings */
352 if (!netif_msg_tx_done(adapter))
353 goto rx_ring_summary;
354
355 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
356
357 /* Transmit Descriptor Formats
358 *
39ac868a 359 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 360 * +--------------------------------------------------------------+
361 * 0 | Buffer Address [63:0] |
362 * +--------------------------------------------------------------+
39ac868a 363 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 364 * +--------------------------------------------------------------+
365 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 366 *
367 * 82598 Advanced Transmit Descriptor (Write-Back Format)
368 * +--------------------------------------------------------------+
369 * 0 | RSV [63:0] |
370 * +--------------------------------------------------------------+
371 * 8 | RSV | STA | NXTSEQ |
372 * +--------------------------------------------------------------+
373 * 63 36 35 32 31 0
374 *
375 * 82599+ Advanced Transmit Descriptor
376 * +--------------------------------------------------------------+
377 * 0 | Buffer Address [63:0] |
378 * +--------------------------------------------------------------+
379 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
380 * +--------------------------------------------------------------+
381 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
382 *
383 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
384 * +--------------------------------------------------------------+
385 * 0 | RSV [63:0] |
386 * +--------------------------------------------------------------+
387 * 8 | RSV | STA | RSV |
388 * +--------------------------------------------------------------+
389 * 63 36 35 32 31 0
dcd79aeb
TI		 390 */
391
392 for (n = 0; n < adapter->num_tx_queues; n++) {
393 tx_ring = adapter->tx_ring[n];
c7689578
JP		 394 pr_info("------------------------------------\n");
395 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
396 pr_info("------------------------------------\n");
397 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 398 "[PlPOIdStDDt Ln] [bi->dma ] "
399 "leng ntw timestamp bi->skb\n");
400
401 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 402 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 403 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 404 u0 = (struct my_u0 *)tx_desc;
c7689578 405 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 406 " %04X %p %016llX %p", i,
dcd79aeb
TI		 407 le64_to_cpu(u0->a),
408 le64_to_cpu(u0->b),
729739b7
AD		 409 (u64)dma_unmap_addr(tx_buffer, dma),
410 dma_unmap_len(tx_buffer, len),
411 tx_buffer->next_to_watch,
412 (u64)tx_buffer->time_stamp,
413 tx_buffer->skb);
dcd79aeb
TI		 414 if (i == tx_ring->next_to_use &&
415 i == tx_ring->next_to_clean)
c7689578 416 pr_cont(" NTC/U\n");
dcd79aeb 417 else if (i == tx_ring->next_to_use)
c7689578 418 pr_cont(" NTU\n");
dcd79aeb 419 else if (i == tx_ring->next_to_clean)
c7689578 420 pr_cont(" NTC\n");
dcd79aeb 421 else
c7689578 422 pr_cont("\n");
dcd79aeb
TI		 423
424 if (netif_msg_pktdata(adapter) &&
9c50c035 425 tx_buffer->skb)
dcd79aeb
TI		 426 print_hex_dump(KERN_INFO, "",
427 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 428 tx_buffer->skb->data,
729739b7
AD		 429 dma_unmap_len(tx_buffer, len),
430 true);
dcd79aeb
TI		 431 }
432 }
433
434 /* Print RX Rings Summary */
435rx_ring_summary:
436 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 437 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 438 for (n = 0; n < adapter->num_rx_queues; n++) {
439 rx_ring = adapter->rx_ring[n];
c7689578
JP		 440 pr_info("%5d %5X %5X\n",
441 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 442 }
443
444 /* Print RX Rings */
445 if (!netif_msg_rx_status(adapter))
446 goto exit;
447
448 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
449
39ac868a
JH		 450 /* Receive Descriptor Formats
451 *
452 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 453 * 63 1 0
454 * +-----------------------------------------------------+
455 * 0 | Packet Buffer Address [63:1] |A0/NSE|
456 * +----------------------------------------------+------+
457 * 8 | Header Buffer Address [63:1] | DD |
458 * +-----------------------------------------------------+
459 *
460 *
39ac868a 461 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 462 *
463 * 63 48 47 32 31 30 21 20 16 15 4 3 0
464 * +------------------------------------------------------+
39ac868a
JH		 465 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
466 * | Packet | IP | | | | Type | Type |
467 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 468 * +------------------------------------------------------+
469 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
470 * +------------------------------------------------------+
471 * 63 48 47 32 31 20 19 0
39ac868a
JH		 472 *
473 * 82599+ Advanced Receive Descriptor (Read) Format
474 * 63 1 0
475 * +-----------------------------------------------------+
476 * 0 | Packet Buffer Address [63:1] |A0/NSE|
477 * +----------------------------------------------+------+
478 * 8 | Header Buffer Address [63:1] | DD |
479 * +-----------------------------------------------------+
480 *
481 *
482 * 82599+ Advanced Receive Descriptor (Write-Back) Format
483 *
484 * 63 48 47 32 31 30 21 20 17 16 4 3 0
485 * +------------------------------------------------------+
486 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
487 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
488 * |/ Flow Dir Flt ID | | | | | |
489 * +------------------------------------------------------+
490 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
491 * +------------------------------------------------------+
492 * 63 48 47 32 31 20 19 0
dcd79aeb 493 */
39ac868a 494
dcd79aeb
TI		 495 for (n = 0; n < adapter->num_rx_queues; n++) {
496 rx_ring = adapter->rx_ring[n];
c7689578
JP		 497 pr_info("------------------------------------\n");
498 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
499 pr_info("------------------------------------\n");
500 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 501 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
502 "<-- Adv Rx Read format\n");
c7689578 503 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 504 "[vl er S cks ln] ---------------- [bi->skb] "
505 "<-- Adv Rx Write-Back format\n");
506
507 for (i = 0; i < rx_ring->count; i++) {
508 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 509 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 if (staterr & IXGBE_RXD_STAT_DD) {
513 /* Descriptor Done */
c7689578 514 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 515 "%016llX ---------------- %p", i,
516 le64_to_cpu(u0->a),
517 le64_to_cpu(u0->b),
518 rx_buffer_info->skb);
519 } else {
c7689578 520 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 521 "%016llX %016llX %p", i,
522 le64_to_cpu(u0->a),
523 le64_to_cpu(u0->b),
524 (u64)rx_buffer_info->dma,
525 rx_buffer_info->skb);
526
9c50c035
ET		 527 if (netif_msg_pktdata(adapter) &&
528 rx_buffer_info->dma) {
dcd79aeb
TI		 529 print_hex_dump(KERN_INFO, "",
530 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 531 page_address(rx_buffer_info->page) +
532 rx_buffer_info->page_offset,
f800326d 533 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 534 }
535 }
536
537 if (i == rx_ring->next_to_use)
c7689578 538 pr_cont(" NTU\n");
dcd79aeb 539 else if (i == rx_ring->next_to_clean)
c7689578 540 pr_cont(" NTC\n");
dcd79aeb 541 else
c7689578 542 pr_cont("\n");
dcd79aeb
TI		 543
544 }
545 }
546
547exit:
548 return;
549}
550
5eba3699
AV		 551static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
552{
553 u32 ctrl_ext;
554
555 /* Let firmware take over control of h/w */
556 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 558 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 559}
560
561static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
562{
563 u32 ctrl_ext;
564
565 /* Let firmware know the driver has taken over */
566 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 568 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 569}
9a799d71 570
49ce9c2c 571/**
e8e26350
PW		 572 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
573 * @adapter: pointer to adapter struct
574 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
575 * @queue: queue to map the corresponding interrupt to
576 * @msix_vector: the vector to map to the corresponding queue
577 *
578 */
579static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 580 u8 queue, u8 msix_vector)
9a799d71
AK		 581{
582 u32 ivar, index;
e8e26350
PW		 583 struct ixgbe_hw *hw = &adapter->hw;
584 switch (hw->mac.type) {
585 case ixgbe_mac_82598EB:
586 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
587 if (direction == -1)
588 direction = 0;
589 index = (((direction * 64) + queue) >> 2) & 0x1F;
590 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
591 ivar &= ~(0xFF << (8 * (queue & 0x3)));
592 ivar |= (msix_vector << (8 * (queue & 0x3)));
593 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
594 break;
595 case ixgbe_mac_82599EB:
b93a2226 596 case ixgbe_mac_X540:
e8e26350
PW		 597 if (direction == -1) {
598 /* other causes */
599 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
600 index = ((queue & 1) * 8);
601 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
602 ivar &= ~(0xFF << index);
603 ivar |= (msix_vector << index);
604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
605 break;
606 } else {
607 /* tx or rx causes */
608 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
609 index = ((16 * (queue & 1)) + (8 * direction));
610 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
611 ivar &= ~(0xFF << index);
612 ivar |= (msix_vector << index);
613 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
614 break;
615 }
616 default:
617 break;
618 }
9a799d71
AK		 619}
620
fe49f04a 621static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 622 u64 qmask)
fe49f04a
AD		 623{
624 u32 mask;
625
bd508178
AD		 626 switch (adapter->hw.mac.type) {
627 case ixgbe_mac_82598EB:
fe49f04a
AD		 628 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 630 break;
631 case ixgbe_mac_82599EB:
b93a2226 632 case ixgbe_mac_X540:
fe49f04a
AD		 633 mask = (qmask & 0xFFFFFFFF);
634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
635 mask = (qmask >> 32);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 637 break;
638 default:
639 break;
fe49f04a
AD		 640 }
641}
642
729739b7
AD		 643void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
644 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 645{
729739b7
AD		 646 if (tx_buffer->skb) {
647 dev_kfree_skb_any(tx_buffer->skb);
648 if (dma_unmap_len(tx_buffer, len))
d3d00239 649 dma_unmap_single(ring->dev,
729739b7
AD		 650 dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 DMA_TO_DEVICE);
653 } else if (dma_unmap_len(tx_buffer, len)) {
654 dma_unmap_page(ring->dev,
655 dma_unmap_addr(tx_buffer, dma),
656 dma_unmap_len(tx_buffer, len),
657 DMA_TO_DEVICE);
e5a43549 658 }
729739b7
AD		 659 tx_buffer->next_to_watch = NULL;
660 tx_buffer->skb = NULL;
661 dma_unmap_len_set(tx_buffer, len, 0);
662 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 663}
664
943561d3 665static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 666{
667 struct ixgbe_hw *hw = &adapter->hw;
668 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 669 int i;
943561d3 670 u32 data;
c84d324c 671
943561d3
AD		 672 if ((hw->fc.current_mode != ixgbe_fc_full) &&
673 (hw->fc.current_mode != ixgbe_fc_rx_pause))
674 return;
c84d324c 675
943561d3
AD		 676 switch (hw->mac.type) {
677 case ixgbe_mac_82598EB:
678 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
679 break;
680 default:
681 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
682 }
683 hwstats->lxoffrxc += data;
c84d324c 684
943561d3
AD		 685 /* refill credits (no tx hang) if we received xoff */
686 if (!data)
c84d324c 687 return;
943561d3
AD		 688
689 for (i = 0; i < adapter->num_tx_queues; i++)
690 clear_bit(__IXGBE_HANG_CHECK_ARMED,
691 &adapter->tx_ring[i]->state);
692}
693
694static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
695{
696 struct ixgbe_hw *hw = &adapter->hw;
697 struct ixgbe_hw_stats *hwstats = &adapter->stats;
698 u32 xoff[8] = {0};
699 int i;
700 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
701
702 if (adapter->ixgbe_ieee_pfc)
703 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
704
705 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
706 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 707 return;
943561d3 708 }
c84d324c
JF		 709
710 /* update stats for each tc, only valid with PFC enabled */
711 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 715 break;
c84d324c
JF		 716 default:
717 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 718 }
c84d324c
JF		 719 hwstats->pxoffrxc[i] += xoff[i];
720 }
721
722 /* disarm tx queues that have received xoff frames */
723 for (i = 0; i < adapter->num_tx_queues; i++) {
724 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 725 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 726
727 if (xoff[tc])
728 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 729 }
26f23d82
YZ		 730}
731
c84d324c 732static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 733{
7d7ce682 734 return ring->stats.packets;
c84d324c
JF		 735}
736
737static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
738{
739 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 740 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 741
c84d324c
JF		 742 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
743 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
744
745 if (head != tail)
746 return (head < tail) ?
747 tail - head : (tail + ring->count - head);
748
749 return 0;
750}
751
752static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
753{
754 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
755 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
756 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
757 bool ret = false;
758
7d637bcc 759 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 760
761 /*
762 * Check for a hung queue, but be thorough. This verifies
763 * that a transmit has been completed since the previous
764 * check AND there is at least one packet pending. The
765 * ARMED bit is set to indicate a potential hang. The
766 * bit is cleared if a pause frame is received to remove
767 * false hang detection due to PFC or 802.3x frames. By
768 * requiring this to fail twice we avoid races with
769 * pfc clearing the ARMED bit and conditions where we
770 * run the check_tx_hang logic with a transmit completion
771 * pending but without time to complete it yet.
772 */
773 if ((tx_done_old == tx_done) && tx_pending) {
774 /* make sure it is true for two checks in a row */
775 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
776 &tx_ring->state);
777 } else {
778 /* update completed stats and continue */
779 tx_ring->tx_stats.tx_done_old = tx_done;
780 /* reset the countdown */
781 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 782 }
783
c84d324c 784 return ret;
9a799d71
AK		 785}
786
c83c6cbd
AD		 787/**
788 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
789 * @adapter: driver private struct
790 **/
791static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
792{
793
794 /* Do the reset outside of interrupt context */
795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
796 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
797 ixgbe_service_event_schedule(adapter);
798 }
799}
e01c31a5 800
9a799d71
AK		 801/**
802 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 803 * @q_vector: structure containing interrupt and ring information
e01c31a5 804 * @tx_ring: tx ring to clean
9a799d71 805 **/
fe49f04a 806static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 807 struct ixgbe_ring *tx_ring)
9a799d71 808{
fe49f04a 809 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 810 struct ixgbe_tx_buffer *tx_buffer;
811 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 812 unsigned int total_bytes = 0, total_packets = 0;
59224555 813 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 814 unsigned int i = tx_ring->next_to_clean;
815
816 if (test_bit(__IXGBE_DOWN, &adapter->state))
817 return true;
9a799d71 818
d3d00239 819 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 820 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 821 i -= tx_ring->count;
12207e49 822
729739b7 823 do {
d3d00239
AD		 824 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
825
826 /* if next_to_watch is not set then there is no work pending */
827 if (!eop_desc)
828 break;
829
7f83a9e6
AD		 830 /* prevent any other reads prior to eop_desc */
831 rmb();
832
d3d00239
AD		 833 /* if DD is not set pending work has not been completed */
834 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
835 break;
8ad494b0 836
d3d00239
AD		 837 /* clear next_to_watch to prevent false hangs */
838 tx_buffer->next_to_watch = NULL;
8ad494b0 839
091a6246
AD		 840 /* update the statistics for this packet */
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
843
0ede4a60
JK		 844 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
845 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
0ede4a60 846
fd0db0ed
AD		 847 /* free the skb */
848 dev_kfree_skb_any(tx_buffer->skb);
849
729739b7
AD		 850 /* unmap skb header data */
851 dma_unmap_single(tx_ring->dev,
852 dma_unmap_addr(tx_buffer, dma),
853 dma_unmap_len(tx_buffer, len),
854 DMA_TO_DEVICE);
855
fd0db0ed
AD		 856 /* clear tx_buffer data */
857 tx_buffer->skb = NULL;
729739b7 858 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 859
729739b7
AD		 860 /* unmap remaining buffers */
861 while (tx_desc != eop_desc) {
d3d00239
AD		 862 tx_buffer++;
863 tx_desc++;
8ad494b0 864 i++;
729739b7
AD		 865 if (unlikely(!i)) {
866 i -= tx_ring->count;
d3d00239 867 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 868 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 869 }
e01c31a5 870
729739b7
AD		 871 /* unmap any remaining paged data */
872 if (dma_unmap_len(tx_buffer, len)) {
873 dma_unmap_page(tx_ring->dev,
874 dma_unmap_addr(tx_buffer, dma),
875 dma_unmap_len(tx_buffer, len),
876 DMA_TO_DEVICE);
877 dma_unmap_len_set(tx_buffer, len, 0);
878 }
879 }
880
881 /* move us one more past the eop_desc for start of next pkt */
882 tx_buffer++;
883 tx_desc++;
884 i++;
885 if (unlikely(!i)) {
886 i -= tx_ring->count;
887 tx_buffer = tx_ring->tx_buffer_info;
888 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
889 }
890
891 /* issue prefetch for next Tx descriptor */
892 prefetch(tx_desc);
12207e49 893
729739b7
AD		 894 /* update budget accounting */
895 budget--;
896 } while (likely(budget));
897
898 i += tx_ring->count;
9a799d71 899 tx_ring->next_to_clean = i;
d3d00239 900 u64_stats_update_begin(&tx_ring->syncp);
b953799e 901 tx_ring->stats.bytes += total_bytes;
bd198058 902 tx_ring->stats.packets += total_packets;
d3d00239 903 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 904 q_vector->tx.total_bytes += total_bytes;
905 q_vector->tx.total_packets += total_packets;
b953799e 906
c84d324c
JF		 907 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
908 /* schedule immediate reset if we believe we hung */
909 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 910 e_err(drv, "Detected Tx Unit Hang\n"
911 " Tx Queue <%d>\n"
912 " TDH, TDT <%x>, <%x>\n"
913 " next_to_use <%x>\n"
914 " next_to_clean <%x>\n"
915 "tx_buffer_info[next_to_clean]\n"
916 " time_stamp <%lx>\n"
917 " jiffies <%lx>\n",
918 tx_ring->queue_index,
919 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
920 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 921 tx_ring->next_to_use, i,
922 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 923
924 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
925
926 e_info(probe,
927 "tx hang %d detected on queue %d, resetting adapter\n",
928 adapter->tx_timeout_count + 1, tx_ring->queue_index);
929
b953799e 930 /* schedule immediate reset if we believe we hung */
c83c6cbd 931 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 932
933 /* the adapter is about to reset, no point in enabling stuff */
59224555 934 return true;
b953799e 935 }
9a799d71 936
b2d96e0a
AD		 937 netdev_tx_completed_queue(txring_txq(tx_ring),
938 total_packets, total_bytes);
939
e092be60 940#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 941 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 942 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 943 /* Make sure that anybody stopping the queue after this
944 * sees the new next_to_clean.
945 */
946 smp_mb();
729739b7
AD		 947 if (__netif_subqueue_stopped(tx_ring->netdev,
948 tx_ring->queue_index)
949 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
950 netif_wake_subqueue(tx_ring->netdev,
951 tx_ring->queue_index);
5b7da515 952 ++tx_ring->tx_stats.restart_queue;
30eba97a 953 }
e092be60 954 }
9a799d71 955
59224555 956 return !!budget;
9a799d71
AK		 957}
958
5dd2d332 959#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 960static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
961 struct ixgbe_ring *tx_ring,
33cf09c9 962 int cpu)
bd0362dd 963{
33cf09c9 964 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 965 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
966 u16 reg_offset;
33cf09c9 967
33cf09c9
AD		 968 switch (hw->mac.type) {
969 case ixgbe_mac_82598EB:
bdda1a61 970 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 971 break;
972 case ixgbe_mac_82599EB:
b93a2226 973 case ixgbe_mac_X540:
bdda1a61
AD		 974 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
975 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 976 break;
977 default:
bdda1a61
AD		 978 /* for unknown hardware do not write register */
979 return;
bd0362dd 980 }
bdda1a61
AD		 981
982 /*
983 * We can enable relaxed ordering for reads, but not writes when
984 * DCA is enabled. This is due to a known issue in some chipsets
985 * which will cause the DCA tag to be cleared.
986 */
987 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
988 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
989 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
990
991 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 992}
993
bdda1a61
AD		 994static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
995 struct ixgbe_ring *rx_ring,
33cf09c9 996 int cpu)
bd0362dd 997{
33cf09c9 998 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 999 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1000 u8 reg_idx = rx_ring->reg_idx;
1001
33cf09c9
AD		 1002
1003 switch (hw->mac.type) {
33cf09c9 1004 case ixgbe_mac_82599EB:
b93a2226 1005 case ixgbe_mac_X540:
bdda1a61 1006 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1007 break;
1008 default:
1009 break;
1010 }
bdda1a61
AD		 1011
1012 /*
1013 * We can enable relaxed ordering for reads, but not writes when
1014 * DCA is enabled. This is due to a known issue in some chipsets
1015 * which will cause the DCA tag to be cleared.
1016 */
1017 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1018 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1019 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1020
1021 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1022}
1023
1024static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1025{
1026 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1027 struct ixgbe_ring *ring;
bd0362dd 1028 int cpu = get_cpu();
bd0362dd 1029
33cf09c9
AD		 1030 if (q_vector->cpu == cpu)
1031 goto out_no_update;
1032
a557928e 1033 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1034 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1035
a557928e 1036 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1037 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1038
1039 q_vector->cpu = cpu;
1040out_no_update:
bd0362dd
JC		 1041 put_cpu();
1042}
1043
1044static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1045{
1046 int i;
1047
1048 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1049 return;
1050
e35ec126
AD		 1051 /* always use CB2 mode, difference is masked in the CB driver */
1052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1053
49c7ffbe 1054 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1055 adapter->q_vector[i]->cpu = -1;
1056 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1057 }
1058}
1059
1060static int __ixgbe_notify_dca(struct device *dev, void *data)
1061{
c60fbb00 1062 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1063 unsigned long event = *(unsigned long *)data;
1064
2a72c31e 1065 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1066 return 0;
1067
bd0362dd
JC		 1068 switch (event) {
1069 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1070 /* if we're already enabled, don't do it again */
1071 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1072 break;
652f093f 1073 if (dca_add_requester(dev) == 0) {
96b0e0f6 1074 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1075 ixgbe_setup_dca(adapter);
1076 break;
1077 }
1078 /* Fall Through since DCA is disabled. */
1079 case DCA_PROVIDER_REMOVE:
1080 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1081 dca_remove_requester(dev);
1082 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1083 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1084 }
1085 break;
1086 }
1087
652f093f 1088 return 0;
bd0362dd 1089}
67a74ee2 1090
bdda1a61 1091#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1092static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1093 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1094 struct sk_buff *skb)
1095{
8a0da21b
AD		 1096 if (ring->netdev->features & NETIF_F_RXHASH)
1097 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1098}
1099
f800326d 1100#ifdef IXGBE_FCOE
ff886dfc
AD		 1101/**
1102 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1103 * @ring: structure containing ring specific data
ff886dfc
AD		 1104 * @rx_desc: advanced rx descriptor
1105 *
1106 * Returns : true if it is FCoE pkt
1107 */
57efd44c 1108static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1109 union ixgbe_adv_rx_desc *rx_desc)
1110{
1111 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1112
57efd44c 1113 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1114 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1115 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1116 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1117}
1118
f800326d 1119#endif /* IXGBE_FCOE */
e59bd25d
AV		 1120/**
1121 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1122 * @ring: structure containing ring specific data
1123 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1124 * @skb: skb currently being received and modified
1125 **/
8a0da21b 1126static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1127 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1128 struct sk_buff *skb)
9a799d71 1129{
8a0da21b 1130 skb_checksum_none_assert(skb);
9a799d71 1131
712744be 1132 /* Rx csum disabled */
8a0da21b 1133 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1134 return;
e59bd25d
AV		 1135
1136 /* if IP and error */
f56e0cb1
AD		 1137 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1138 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1139 ring->rx_stats.csum_err++;
9a799d71
AK		 1140 return;
1141 }
e59bd25d 1142
f56e0cb1 1143 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1144 return;
1145
f56e0cb1 1146 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1147 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1148
1149 /*
1150 * 82599 errata, UDP frames with a 0 checksum can be marked as
1151 * checksum errors.
1152 */
8a0da21b
AD		 1153 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1154 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1155 return;
1156
8a0da21b 1157 ring->rx_stats.csum_err++;
e59bd25d
AV		 1158 return;
1159 }
1160
9a799d71 1161 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1162 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1163}
1164
84ea2591 1165static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1166{
f56e0cb1 1167 rx_ring->next_to_use = val;
f800326d
AD		 1168
1169 /* update next to alloc since we have filled the ring */
1170 rx_ring->next_to_alloc = val;
e8e26350
PW		 1171 /*
1172 * Force memory writes to complete before letting h/w
1173 * know there are new descriptors to fetch. (Only
1174 * applicable for weak-ordered memory model archs,
1175 * such as IA-64).
1176 */
1177 wmb();
84ea2591 1178 writel(val, rx_ring->tail);
e8e26350
PW		 1179}
1180
f990b79b
AD		 1181static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1182 struct ixgbe_rx_buffer *bi)
1183{
1184 struct page *page = bi->page;
f800326d 1185 dma_addr_t dma = bi->dma;
f990b79b 1186
f800326d
AD		 1187 /* since we are recycling buffers we should seldom need to alloc */
1188 if (likely(dma))
f990b79b
AD		 1189 return true;
1190
f800326d
AD		 1191 /* alloc new page for storage */
1192 if (likely(!page)) {
0614002b
MG		 1193 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1194 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1195 if (unlikely(!page)) {
1196 rx_ring->rx_stats.alloc_rx_page_failed++;
1197 return false;
1198 }
f800326d 1199 bi->page = page;
f990b79b
AD		 1200 }
1201
f800326d
AD		 1202 /* map page for use */
1203 dma = dma_map_page(rx_ring->dev, page, 0,
1204 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1205
1206 /*
1207 * if mapping failed free memory back to system since
1208 * there isn't much point in holding memory we can't use
1209 */
1210 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1211 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1212 bi->page = NULL;
f990b79b 1213
f990b79b
AD		 1214 rx_ring->rx_stats.alloc_rx_page_failed++;
1215 return false;
1216 }
1217
f800326d 1218 bi->dma = dma;
afaa9459 1219 bi->page_offset = 0;
f800326d 1220
f990b79b
AD		 1221 return true;
1222}
1223
9a799d71 1224/**
f990b79b 1225 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1226 * @rx_ring: ring to place buffers on
1227 * @cleaned_count: number of buffers to replace
9a799d71 1228 **/
fc77dc3c 1229void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1230{
9a799d71 1231 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1232 struct ixgbe_rx_buffer *bi;
d5f398ed 1233 u16 i = rx_ring->next_to_use;
9a799d71 1234
f800326d
AD		 1235 /* nothing to do */
1236 if (!cleaned_count)
fc77dc3c
AD		 1237 return;
1238
e4f74028 1239 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1240 bi = &rx_ring->rx_buffer_info[i];
1241 i -= rx_ring->count;
9a799d71 1242
f800326d
AD		 1243 do {
1244 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1245 break;
d5f398ed 1246
f800326d
AD		 1247 /*
1248 * Refresh the desc even if buffer_addrs didn't change
1249 * because each write-back erases this info.
1250 */
1251 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1252
f990b79b
AD		 1253 rx_desc++;
1254 bi++;
9a799d71 1255 i++;
f990b79b 1256 if (unlikely(!i)) {
e4f74028 1257 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1258 bi = rx_ring->rx_buffer_info;
1259 i -= rx_ring->count;
1260 }
1261
1262 /* clear the hdr_addr for the next_to_use descriptor */
1263 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1264
1265 cleaned_count--;
1266 } while (cleaned_count);
7c6e0a43 1267
f990b79b
AD		 1268 i += rx_ring->count;
1269
f56e0cb1 1270 if (rx_ring->next_to_use != i)
84ea2591 1271 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1272}
1273
1d2024f6
AD		 1274/**
1275 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1276 * @data: pointer to the start of the headers
1277 * @max_len: total length of section to find headers in
1278 *
1279 * This function is meant to determine the length of headers that will
1280 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1281 * motivation of doing this is to only perform one pull for IPv4 TCP
1282 * packets so that we can do basic things like calculating the gso_size
1283 * based on the average data per packet.
1284 **/
1285static unsigned int ixgbe_get_headlen(unsigned char *data,
1286 unsigned int max_len)
1287{
1288 union {
1289 unsigned char *network;
1290 /* l2 headers */
1291 struct ethhdr *eth;
1292 struct vlan_hdr *vlan;
1293 /* l3 headers */
1294 struct iphdr *ipv4;
a048b40e 1295 struct ipv6hdr *ipv6;
1d2024f6
AD		 1296 } hdr;
1297 __be16 protocol;
1298 u8 nexthdr = 0; /* default to not TCP */
1299 u8 hlen;
1300
1301 /* this should never happen, but better safe than sorry */
1302 if (max_len < ETH_HLEN)
1303 return max_len;
1304
1305 /* initialize network frame pointer */
1306 hdr.network = data;
1307
1308 /* set first protocol and move network header forward */
1309 protocol = hdr.eth->h_proto;
1310 hdr.network += ETH_HLEN;
1311
1312 /* handle any vlan tag if present */
1313 if (protocol == __constant_htons(ETH_P_8021Q)) {
1314 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1315 return max_len;
1316
1317 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1318 hdr.network += VLAN_HLEN;
1319 }
1320
1321 /* handle L3 protocols */
1322 if (protocol == __constant_htons(ETH_P_IP)) {
1323 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1324 return max_len;
1325
1326 /* access ihl as a u8 to avoid unaligned access on ia64 */
1327 hlen = (hdr.network[0] & 0x0F) << 2;
1328
1329 /* verify hlen meets minimum size requirements */
1330 if (hlen < sizeof(struct iphdr))
1331 return hdr.network - data;
1332
1333 /* record next protocol */
1334 nexthdr = hdr.ipv4->protocol;
1335 hdr.network += hlen;
a048b40e
AD		 1336 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1337 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1338 return max_len;
1339
1340 /* record next protocol */
1341 nexthdr = hdr.ipv6->nexthdr;
1342 hdr.network += sizeof(struct ipv6hdr);
f800326d 1343#ifdef IXGBE_FCOE
1d2024f6
AD		 1344 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1345 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1346 return max_len;
1347 hdr.network += FCOE_HEADER_LEN;
1348#endif
1349 } else {
1350 return hdr.network - data;
1351 }
1352
a048b40e 1353 /* finally sort out TCP/UDP */
1d2024f6
AD		 1354 if (nexthdr == IPPROTO_TCP) {
1355 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1356 return max_len;
1357
1358 /* access doff as a u8 to avoid unaligned access on ia64 */
1359 hlen = (hdr.network[12] & 0xF0) >> 2;
1360
1361 /* verify hlen meets minimum size requirements */
1362 if (hlen < sizeof(struct tcphdr))
1363 return hdr.network - data;
1364
1365 hdr.network += hlen;
a048b40e
AD		 1366 } else if (nexthdr == IPPROTO_UDP) {
1367 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1368 return max_len;
1369
1370 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1371 }
1372
1373 /*
1374 * If everything has gone correctly hdr.network should be the
1375 * data section of the packet and will be the end of the header.
1376 * If not then it probably represents the end of the last recognized
1377 * header.
1378 */
1379 if ((hdr.network - data) < max_len)
1380 return hdr.network - data;
1381 else
1382 return max_len;
1383}
1384
1d2024f6
AD		 1385static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1386 struct sk_buff *skb)
1387{
f800326d 1388 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1389
1390 /* set gso_size to avoid messing up TCP MSS */
1391 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1392 IXGBE_CB(skb)->append_cnt);
1393}
1394
1395static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1396 struct sk_buff *skb)
1397{
1398 /* if append_cnt is 0 then frame is not RSC */
1399 if (!IXGBE_CB(skb)->append_cnt)
1400 return;
1401
1402 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1403 rx_ring->rx_stats.rsc_flush++;
1404
1405 ixgbe_set_rsc_gso_size(rx_ring, skb);
1406
1407 /* gso_size is computed using append_cnt so always clear it last */
1408 IXGBE_CB(skb)->append_cnt = 0;
1409}
1410
8a0da21b
AD		 1411/**
1412 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1413 * @rx_ring: rx descriptor ring packet is being transacted on
1414 * @rx_desc: pointer to the EOP Rx descriptor
1415 * @skb: pointer to current skb being populated
f8212f97 1416 *
8a0da21b
AD		 1417 * This function checks the ring, descriptor, and packet information in
1418 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1419 * other fields within the skb.
f8212f97 1420 **/
8a0da21b
AD		 1421static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1422 union ixgbe_adv_rx_desc *rx_desc,
1423 struct sk_buff *skb)
f8212f97 1424{
43e95f11
JF		 1425 struct net_device *dev = rx_ring->netdev;
1426
8a0da21b
AD		 1427 ixgbe_update_rsc_stats(rx_ring, skb);
1428
1429 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1430
8a0da21b
AD		 1431 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1432
1d1a79b5 1433 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda 1434
43e95f11
JF		 1435 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1436 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1437 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1438 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1439 }
1440
8a0da21b 1441 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1442
43e95f11 1443 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1444}
1445
8a0da21b
AD		 1446static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1447 struct sk_buff *skb)
aa80175a 1448{
8a0da21b
AD		 1449 struct ixgbe_adapter *adapter = q_vector->adapter;
1450
1451 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1452 napi_gro_receive(&q_vector->napi, skb);
1453 else
1454 netif_rx(skb);
aa80175a 1455}
43634e82 1456
f800326d
AD		 1457/**
1458 * ixgbe_is_non_eop - process handling of non-EOP buffers
1459 * @rx_ring: Rx ring being processed
1460 * @rx_desc: Rx descriptor for current buffer
1461 * @skb: Current socket buffer containing buffer in progress
1462 *
1463 * This function updates next to clean. If the buffer is an EOP buffer
1464 * this function exits returning false, otherwise it will place the
1465 * sk_buff in the next buffer to be chained and return true indicating
1466 * that this is in fact a non-EOP buffer.
1467 **/
1468static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1469 union ixgbe_adv_rx_desc *rx_desc,
1470 struct sk_buff *skb)
1471{
1472 u32 ntc = rx_ring->next_to_clean + 1;
1473
1474 /* fetch, update, and store next to clean */
1475 ntc = (ntc < rx_ring->count) ? ntc : 0;
1476 rx_ring->next_to_clean = ntc;
1477
1478 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1479
5a02cbd1
AD		 1480 /* update RSC append count if present */
1481 if (ring_is_rsc_enabled(rx_ring)) {
1482 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1483 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1484
1485 if (unlikely(rsc_enabled)) {
1486 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1487
1488 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1489 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1490
5a02cbd1
AD		 1491 /* update ntc based on RSC value */
1492 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1493 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1494 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1495 }
f800326d
AD		 1496 }
1497
5a02cbd1
AD		 1498 /* if we are the last buffer then there is nothing else to do */
1499 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1500 return false;
1501
f800326d
AD		 1502 /* place skb in next buffer to be received */
1503 rx_ring->rx_buffer_info[ntc].skb = skb;
1504 rx_ring->rx_stats.non_eop_descs++;
1505
1506 return true;
1507}
1508
19861ce2
AD		 1509/**
1510 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1511 * @rx_ring: rx descriptor ring packet is being transacted on
1512 * @skb: pointer to current skb being adjusted
1513 *
1514 * This function is an ixgbe specific version of __pskb_pull_tail. The
1515 * main difference between this version and the original function is that
1516 * this function can make several assumptions about the state of things
1517 * that allow for significant optimizations versus the standard function.
1518 * As a result we can do things like drop a frag and maintain an accurate
1519 * truesize for the skb.
1520 */
1521static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1522 struct sk_buff *skb)
1523{
1524 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1525 unsigned char *va;
1526 unsigned int pull_len;
1527
1528 /*
1529 * it is valid to use page_address instead of kmap since we are
1530 * working with pages allocated out of the lomem pool per
1531 * alloc_page(GFP_ATOMIC)
1532 */
1533 va = skb_frag_address(frag);
1534
1535 /*
1536 * we need the header to contain the greater of either ETH_HLEN or
1537 * 60 bytes if the skb->len is less than 60 for skb_pad.
1538 */
cf3fe7ac 1539 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1540
1541 /* align pull length to size of long to optimize memcpy performance */
1542 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1543
1544 /* update all of the pointers */
1545 skb_frag_size_sub(frag, pull_len);
1546 frag->page_offset += pull_len;
1547 skb->data_len -= pull_len;
1548 skb->tail += pull_len;
19861ce2
AD		 1549}
1550
42073d91
AD		 1551/**
1552 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1553 * @rx_ring: rx descriptor ring packet is being transacted on
1554 * @skb: pointer to current skb being updated
1555 *
1556 * This function provides a basic DMA sync up for the first fragment of an
1557 * skb. The reason for doing this is that the first fragment cannot be
1558 * unmapped until we have reached the end of packet descriptor for a buffer
1559 * chain.
1560 */
1561static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1562 struct sk_buff *skb)
1563{
1564 /* if the page was released unmap it, else just sync our portion */
1565 if (unlikely(IXGBE_CB(skb)->page_released)) {
1566 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1567 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1568 IXGBE_CB(skb)->page_released = false;
1569 } else {
1570 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1571
1572 dma_sync_single_range_for_cpu(rx_ring->dev,
1573 IXGBE_CB(skb)->dma,
1574 frag->page_offset,
1575 ixgbe_rx_bufsz(rx_ring),
1576 DMA_FROM_DEVICE);
1577 }
1578 IXGBE_CB(skb)->dma = 0;
1579}
1580
f800326d
AD		 1581/**
1582 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1583 * @rx_ring: rx descriptor ring packet is being transacted on
1584 * @rx_desc: pointer to the EOP Rx descriptor
1585 * @skb: pointer to current skb being fixed
1586 *
1587 * Check for corrupted packet headers caused by senders on the local L2
1588 * embedded NIC switch not setting up their Tx Descriptors right. These
1589 * should be very rare.
1590 *
1591 * Also address the case where we are pulling data in on pages only
1592 * and as such no data is present in the skb header.
1593 *
1594 * In addition if skb is not at least 60 bytes we need to pad it so that
1595 * it is large enough to qualify as a valid Ethernet frame.
1596 *
1597 * Returns true if an error was encountered and skb was freed.
1598 **/
1599static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1600 union ixgbe_adv_rx_desc *rx_desc,
1601 struct sk_buff *skb)
1602{
f800326d 1603 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1604
1605 /* verify that the packet does not have any known errors */
1606 if (unlikely(ixgbe_test_staterr(rx_desc,
1607 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1608 !(netdev->features & NETIF_F_RXALL))) {
1609 dev_kfree_skb_any(skb);
1610 return true;
1611 }
1612
19861ce2 1613 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1614 if (skb_is_nonlinear(skb))
1615 ixgbe_pull_tail(rx_ring, skb);
f800326d 1616
57efd44c
AD		 1617#ifdef IXGBE_FCOE
1618 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1619 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1620 return false;
1621
1622#endif
f800326d
AD		 1623 /* if skb_pad returns an error the skb was freed */
1624 if (unlikely(skb->len < 60)) {
1625 int pad_len = 60 - skb->len;
1626
1627 if (skb_pad(skb, pad_len))
1628 return true;
1629 __skb_put(skb, pad_len);
1630 }
1631
1632 return false;
1633}
1634
f800326d
AD		 1635/**
1636 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1637 * @rx_ring: rx descriptor ring to store buffers on
1638 * @old_buff: donor buffer to have page reused
1639 *
0549ae20 1640 * Synchronizes page for reuse by the adapter
f800326d
AD		 1641 **/
1642static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1643 struct ixgbe_rx_buffer *old_buff)
1644{
1645 struct ixgbe_rx_buffer *new_buff;
1646 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1647
1648 new_buff = &rx_ring->rx_buffer_info[nta];
1649
1650 /* update, and store next to alloc */
1651 nta++;
1652 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1653
1654 /* transfer page from old buffer to new buffer */
1655 new_buff->page = old_buff->page;
1656 new_buff->dma = old_buff->dma;
0549ae20 1657 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1658
1659 /* sync the buffer for use by the device */
1660 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1661 new_buff->page_offset,
1662 ixgbe_rx_bufsz(rx_ring),
f800326d 1663 DMA_FROM_DEVICE);
f800326d
AD		 1664}
1665
1666/**
1667 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1668 * @rx_ring: rx descriptor ring to transact packets on
1669 * @rx_buffer: buffer containing page to add
1670 * @rx_desc: descriptor containing length of buffer written by hardware
1671 * @skb: sk_buff to place the data into
1672 *
0549ae20
AD		 1673 * This function will add the data contained in rx_buffer->page to the skb.
1674 * This is done either through a direct copy if the data in the buffer is
1675 * less than the skb header size, otherwise it will just attach the page as
1676 * a frag to the skb.
1677 *
1678 * The function will then update the page offset if necessary and return
1679 * true if the buffer can be reused by the adapter.
f800326d 1680 **/
0549ae20 1681static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1682 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1683 union ixgbe_adv_rx_desc *rx_desc,
1684 struct sk_buff *skb)
f800326d 1685{
0549ae20
AD		 1686 struct page *page = rx_buffer->page;
1687 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1688#if (PAGE_SIZE < 8192)
0549ae20 1689 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1690#else
1691 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1692 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1693 ixgbe_rx_bufsz(rx_ring);
1694#endif
0549ae20 1695
cf3fe7ac
AD		 1696 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1697 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1698
1699 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1700
1701 /* we can reuse buffer as-is, just make sure it is local */
1702 if (likely(page_to_nid(page) == numa_node_id()))
1703 return true;
1704
1705 /* this page cannot be reused so discard it */
1706 put_page(page);
1707 return false;
1708 }
1709
0549ae20
AD		 1710 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1711 rx_buffer->page_offset, size, truesize);
1712
09816fbe
AD		 1713 /* avoid re-using remote pages */
1714 if (unlikely(page_to_nid(page) != numa_node_id()))
1715 return false;
1716
1717#if (PAGE_SIZE < 8192)
1718 /* if we are only owner of page we can reuse it */
1719 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1720 return false;
1721
1722 /* flip page offset to other buffer */
1723 rx_buffer->page_offset ^= truesize;
1724
09816fbe
AD		 1725 /*
1726 * since we are the only owner of the page and we need to
1727 * increment it, just set the value to 2 in order to avoid
1728 * an unecessary locked operation
1729 */
1730 atomic_set(&page->_count, 2);
1731#else
1732 /* move offset up to the next cache line */
1733 rx_buffer->page_offset += truesize;
1734
1735 if (rx_buffer->page_offset > last_offset)
1736 return false;
1737
0549ae20
AD		 1738 /* bump ref count on page before it is given to the stack */
1739 get_page(page);
09816fbe 1740#endif
0549ae20
AD		 1741
1742 return true;
f800326d
AD		 1743}
1744
18806c9e
AD		 1745static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1746 union ixgbe_adv_rx_desc *rx_desc)
1747{
1748 struct ixgbe_rx_buffer *rx_buffer;
1749 struct sk_buff *skb;
1750 struct page *page;
1751
1752 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1753 page = rx_buffer->page;
1754 prefetchw(page);
1755
1756 skb = rx_buffer->skb;
1757
1758 if (likely(!skb)) {
1759 void *page_addr = page_address(page) +
1760 rx_buffer->page_offset;
1761
1762 /* prefetch first cache line of first page */
1763 prefetch(page_addr);
1764#if L1_CACHE_BYTES < 128
1765 prefetch(page_addr + L1_CACHE_BYTES);
1766#endif
1767
1768 /* allocate a skb to store the frags */
1769 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1770 IXGBE_RX_HDR_SIZE);
1771 if (unlikely(!skb)) {
1772 rx_ring->rx_stats.alloc_rx_buff_failed++;
1773 return NULL;
1774 }
1775
1776 /*
1777 * we will be copying header into skb->data in
1778 * pskb_may_pull so it is in our interest to prefetch
1779 * it now to avoid a possible cache miss
1780 */
1781 prefetchw(skb->data);
1782
1783 /*
1784 * Delay unmapping of the first packet. It carries the
1785 * header information, HW may still access the header
1786 * after the writeback. Only unmap it when EOP is
1787 * reached
1788 */
1789 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1790 goto dma_sync;
1791
1792 IXGBE_CB(skb)->dma = rx_buffer->dma;
1793 } else {
1794 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1795 ixgbe_dma_sync_frag(rx_ring, skb);
1796
1797dma_sync:
1798 /* we are reusing so sync this buffer for CPU use */
1799 dma_sync_single_range_for_cpu(rx_ring->dev,
1800 rx_buffer->dma,
1801 rx_buffer->page_offset,
1802 ixgbe_rx_bufsz(rx_ring),
1803 DMA_FROM_DEVICE);
1804 }
1805
1806 /* pull page into skb */
1807 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1808 /* hand second half of page back to the ring */
1809 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1810 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1811 /* the page has been released from the ring */
1812 IXGBE_CB(skb)->page_released = true;
1813 } else {
1814 /* we are not reusing the buffer so unmap it */
1815 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1816 ixgbe_rx_pg_size(rx_ring),
1817 DMA_FROM_DEVICE);
1818 }
1819
1820 /* clear contents of buffer_info */
1821 rx_buffer->skb = NULL;
1822 rx_buffer->dma = 0;
1823 rx_buffer->page = NULL;
1824
1825 return skb;
f800326d
AD		 1826}
1827
1828/**
1829 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1830 * @q_vector: structure containing interrupt and ring information
1831 * @rx_ring: rx descriptor ring to transact packets on
1832 * @budget: Total limit on number of packets to process
1833 *
1834 * This function provides a "bounce buffer" approach to Rx interrupt
1835 * processing. The advantage to this is that on systems that have
1836 * expensive overhead for IOMMU access this provides a means of avoiding
1837 * it by maintaining the mapping of the page to the syste.
1838 *
1839 * Returns true if all work is completed without reaching budget
1840 **/
4ff7fb12 1841static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1842 struct ixgbe_ring *rx_ring,
f4de00ed 1843 const int budget)
9a799d71 1844{
d2f4fbe2 1845 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1846#ifdef IXGBE_FCOE
f800326d 1847 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1848 int ddp_bytes;
1849 unsigned int mss = 0;
3d8fd385 1850#endif /* IXGBE_FCOE */
f800326d 1851 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1852
f800326d 1853 do {
f800326d
AD		 1854 union ixgbe_adv_rx_desc *rx_desc;
1855 struct sk_buff *skb;
f800326d
AD		 1856
1857 /* return some buffers to hardware, one at a time is too slow */
1858 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1859 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1860 cleaned_count = 0;
1861 }
1862
18806c9e 1863 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1864
1865 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1866 break;
9a799d71 1867
f800326d
AD		 1868 /*
1869 * This memory barrier is needed to keep us from reading
1870 * any other fields out of the rx_desc until we know the
1871 * RXD_STAT_DD bit is set
1872 */
1873 rmb();
9a799d71 1874
18806c9e
AD		 1875 /* retrieve a buffer from the ring */
1876 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1877
18806c9e
AD		 1878 /* exit if we failed to retrieve a buffer */
1879 if (!skb)
1880 break;
9a799d71 1881
9a799d71 1882 cleaned_count++;
f8212f97 1883
f800326d
AD		 1884 /* place incomplete frames back on ring for completion */
1885 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1886 continue;
c267fc16 1887
f800326d
AD		 1888 /* verify the packet layout is correct */
1889 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1890 continue;
9a799d71 1891
d2f4fbe2
AV		 1892 /* probably a little skewed due to removing CRC */
1893 total_rx_bytes += skb->len;
d2f4fbe2 1894
8a0da21b
AD		 1895 /* populate checksum, timestamp, VLAN, and protocol */
1896 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1897
332d4a7d
YZ		 1898#ifdef IXGBE_FCOE
1899 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1900 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1901 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1902 /* include DDPed FCoE data */
1903 if (ddp_bytes > 0) {
1904 if (!mss) {
1905 mss = rx_ring->netdev->mtu -
1906 sizeof(struct fcoe_hdr) -
1907 sizeof(struct fc_frame_header) -
1908 sizeof(struct fcoe_crc_eof);
1909 if (mss > 512)
1910 mss &= ~511;
1911 }
1912 total_rx_bytes += ddp_bytes;
1913 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1914 mss);
1915 }
63d635b2
AD		 1916 if (!ddp_bytes) {
1917 dev_kfree_skb_any(skb);
f800326d 1918 continue;
63d635b2 1919 }
3d8fd385 1920 }
f800326d 1921
332d4a7d 1922#endif /* IXGBE_FCOE */
8a0da21b 1923 ixgbe_rx_skb(q_vector, skb);
9a799d71 1924
f800326d 1925 /* update budget accounting */
f4de00ed
AD		 1926 total_rx_packets++;
1927 } while (likely(total_rx_packets < budget));
9a799d71 1928
c267fc16
AD		 1929 u64_stats_update_begin(&rx_ring->syncp);
1930 rx_ring->stats.packets += total_rx_packets;
1931 rx_ring->stats.bytes += total_rx_bytes;
1932 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1933 q_vector->rx.total_packets += total_rx_packets;
1934 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1935
f800326d
AD		 1936 if (cleaned_count)
1937 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1938
f4de00ed 1939 return (total_rx_packets < budget);
9a799d71
AK		 1940}
1941
9a799d71
AK		 1942/**
1943 * ixgbe_configure_msix - Configure MSI-X hardware
1944 * @adapter: board private structure
1945 *
1946 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1947 * interrupts.
1948 **/
1949static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1950{
021230d4 1951 struct ixgbe_q_vector *q_vector;
49c7ffbe 1952 int v_idx;
021230d4 1953 u32 mask;
9a799d71 1954
8e34d1aa
AD		 1955 /* Populate MSIX to EITR Select */
1956 if (adapter->num_vfs > 32) {
1957 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1959 }
1960
4df10466
JB		 1961 /*
1962 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1963 * corresponding register.
1964 */
49c7ffbe 1965 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1966 struct ixgbe_ring *ring;
7a921c93 1967 q_vector = adapter->q_vector[v_idx];
021230d4 1968
a557928e 1969 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1970 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1971
a557928e 1972 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1973 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1974
d5bf4f67
ET		 1975 if (q_vector->tx.ring && !q_vector->rx.ring) {
1976 /* tx only vector */
1977 if (adapter->tx_itr_setting == 1)
1978 q_vector->itr = IXGBE_10K_ITR;
1979 else
1980 q_vector->itr = adapter->tx_itr_setting;
1981 } else {
1982 /* rx or rx/tx vector */
1983 if (adapter->rx_itr_setting == 1)
1984 q_vector->itr = IXGBE_20K_ITR;
1985 else
1986 q_vector->itr = adapter->rx_itr_setting;
1987 }
021230d4 1988
fe49f04a 1989 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1990 }
1991
bd508178
AD		 1992 switch (adapter->hw.mac.type) {
1993 case ixgbe_mac_82598EB:
e8e26350 1994 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1995 v_idx);
bd508178
AD		 1996 break;
1997 case ixgbe_mac_82599EB:
b93a2226 1998 case ixgbe_mac_X540:
e8e26350 1999 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2000 break;
bd508178
AD		 2001 default:
2002 break;
2003 }
021230d4
AV		 2004 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2005
41fb9248 2006 /* set up to autoclear timer, and the vectors */
021230d4 2007 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2008 mask &= ~(IXGBE_EIMS_OTHER |
2009 IXGBE_EIMS_MAILBOX |
2010 IXGBE_EIMS_LSC);
2011
021230d4 2012 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2013}
2014
f494e8fa
AV		 2015enum latency_range {
2016 lowest_latency = 0,
2017 low_latency = 1,
2018 bulk_latency = 2,
2019 latency_invalid = 255
2020};
2021
2022/**
2023 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2024 * @q_vector: structure containing interrupt and ring information
2025 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2026 *
2027 * Stores a new ITR value based on packets and byte
2028 * counts during the last interrupt. The advantage of per interrupt
2029 * computation is faster updates and more accurate ITR for the current
2030 * traffic pattern. Constants in this function were computed
2031 * based on theoretical maximum wire speed and thresholds were set based
2032 * on testing data as well as attempting to minimize response time
2033 * while increasing bulk throughput.
2034 * this functionality is controlled by the InterruptThrottleRate module
2035 * parameter (see ixgbe_param.c)
2036 **/
bd198058
AD		 2037static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2038 struct ixgbe_ring_container *ring_container)
f494e8fa 2039{
bd198058
AD		 2040 int bytes = ring_container->total_bytes;
2041 int packets = ring_container->total_packets;
2042 u32 timepassed_us;
621bd70e 2043 u64 bytes_perint;
bd198058 2044 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2045
2046 if (packets == 0)
bd198058 2047 return;
f494e8fa
AV		 2048
2049 /* simple throttlerate management
621bd70e
AD		 2050 * 0-10MB/s lowest (100000 ints/s)
2051 * 10-20MB/s low (20000 ints/s)
2052 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2053 */
2054 /* what was last interrupt timeslice? */
d5bf4f67 2055 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 2056 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2057
2058 switch (itr_setting) {
2059 case lowest_latency:
621bd70e 2060 if (bytes_perint > 10)
bd198058 2061 itr_setting = low_latency;
f494e8fa
AV		 2062 break;
2063 case low_latency:
621bd70e 2064 if (bytes_perint > 20)
bd198058 2065 itr_setting = bulk_latency;
621bd70e 2066 else if (bytes_perint <= 10)
bd198058 2067 itr_setting = lowest_latency;
f494e8fa
AV		 2068 break;
2069 case bulk_latency:
621bd70e 2070 if (bytes_perint <= 20)
bd198058 2071 itr_setting = low_latency;
f494e8fa
AV		 2072 break;
2073 }
2074
bd198058
AD		 2075 /* clear work counters since we have the values we need */
2076 ring_container->total_bytes = 0;
2077 ring_container->total_packets = 0;
2078
2079 /* write updated itr to ring container */
2080 ring_container->itr = itr_setting;
f494e8fa
AV		 2081}
2082
509ee935
JB		 2083/**
2084 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2085 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2086 *
2087 * This function is made to be called by ethtool and by the driver
2088 * when it needs to update EITR registers at runtime. Hardware
2089 * specific quirks/differences are taken care of here.
2090 */
fe49f04a 2091void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2092{
fe49f04a 2093 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2094 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2095 int v_idx = q_vector->v_idx;
5d967eb7 2096 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2097
bd508178
AD		 2098 switch (adapter->hw.mac.type) {
2099 case ixgbe_mac_82598EB:
509ee935
JB		 2100 /* must write high and low 16 bits to reset counter */
2101 itr_reg |= (itr_reg << 16);
bd508178
AD		 2102 break;
2103 case ixgbe_mac_82599EB:
b93a2226 2104 case ixgbe_mac_X540:
509ee935
JB		 2105 /*
2106 * set the WDIS bit to not clear the timer bits and cause an
2107 * immediate assertion of the interrupt
2108 */
2109 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2110 break;
2111 default:
2112 break;
509ee935
JB		 2113 }
2114 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2115}
2116
bd198058 2117static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2118{
d5bf4f67 2119 u32 new_itr = q_vector->itr;
bd198058 2120 u8 current_itr;
f494e8fa 2121
bd198058
AD		 2122 ixgbe_update_itr(q_vector, &q_vector->tx);
2123 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2124
08c8833b 2125 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2126
2127 switch (current_itr) {
2128 /* counts and packets in update_itr are dependent on these numbers */
2129 case lowest_latency:
d5bf4f67 2130 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2131 break;
2132 case low_latency:
d5bf4f67 2133 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2134 break;
2135 case bulk_latency:
d5bf4f67 2136 new_itr = IXGBE_8K_ITR;
f494e8fa 2137 break;
bd198058
AD		 2138 default:
2139 break;
f494e8fa
AV		 2140 }
2141
d5bf4f67 2142 if (new_itr != q_vector->itr) {
fe49f04a 2143 /* do an exponential smoothing */
d5bf4f67
ET		 2144 new_itr = (10 * new_itr * q_vector->itr) /
2145 ((9 * new_itr) + q_vector->itr);
509ee935 2146
bd198058 2147 /* save the algorithm value here */
5d967eb7 2148 q_vector->itr = new_itr;
fe49f04a
AD		 2149
2150 ixgbe_write_eitr(q_vector);
f494e8fa 2151 }
f494e8fa
AV		 2152}
2153
119fc60a 2154/**
de88eeeb 2155 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2156 * @adapter: pointer to adapter
119fc60a 2157 **/
f0f9778d 2158static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2159{
119fc60a
MC		 2160 struct ixgbe_hw *hw = &adapter->hw;
2161 u32 eicr = adapter->interrupt_event;
2162
f0f9778d 2163 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2164 return;
2165
f0f9778d
AD		 2166 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2167 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2168 return;
2169
2170 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2171
7ca647bd 2172 switch (hw->device_id) {
f0f9778d
AD		 2173 case IXGBE_DEV_ID_82599_T3_LOM:
2174 /*
2175 * Since the warning interrupt is for both ports
2176 * we don't have to check if:
2177 * - This interrupt wasn't for our port.
2178 * - We may have missed the interrupt so always have to
2179 * check if we got a LSC
2180 */
2181 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2182 !(eicr & IXGBE_EICR_LSC))
2183 return;
2184
2185 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2186 u32 autoneg;
2187 bool link_up = false;
7ca647bd 2188
7ca647bd
JP		 2189 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2190
f0f9778d
AD		 2191 if (link_up)
2192 return;
2193 }
2194
2195 /* Check if this is not due to overtemp */
2196 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2197 return;
2198
2199 break;
7ca647bd
JP		 2200 default:
2201 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2202 return;
7ca647bd 2203 break;
119fc60a 2204 }
7ca647bd
JP		 2205 e_crit(drv,
2206 "Network adapter has been stopped because it has over heated. "
2207 "Restart the computer. If the problem persists, "
2208 "power off the system and replace the adapter\n");
f0f9778d
AD		 2209
2210 adapter->interrupt_event = 0;
119fc60a
MC		 2211}
2212
0befdb3e
JB		 2213static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2214{
2215 struct ixgbe_hw *hw = &adapter->hw;
2216
2217 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2218 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2219 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2220 /* write to clear the interrupt */
2221 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2222 }
2223}
cf8280ee 2224
4f51bf70
JK		 2225static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2226{
2227 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2228 return;
2229
2230 switch (adapter->hw.mac.type) {
2231 case ixgbe_mac_82599EB:
2232 /*
2233 * Need to check link state so complete overtemp check
2234 * on service task
2235 */
2236 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2237 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2238 adapter->interrupt_event = eicr;
2239 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2240 ixgbe_service_event_schedule(adapter);
2241 return;
2242 }
2243 return;
2244 case ixgbe_mac_X540:
2245 if (!(eicr & IXGBE_EICR_TS))
2246 return;
2247 break;
2248 default:
2249 return;
2250 }
2251
2252 e_crit(drv,
2253 "Network adapter has been stopped because it has over heated. "
2254 "Restart the computer. If the problem persists, "
2255 "power off the system and replace the adapter\n");
2256}
2257
e8e26350
PW		 2258static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2259{
2260 struct ixgbe_hw *hw = &adapter->hw;
2261
73c4b7cd
AD		 2262 if (eicr & IXGBE_EICR_GPI_SDP2) {
2263 /* Clear the interrupt */
2264 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2265 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2266 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2267 ixgbe_service_event_schedule(adapter);
2268 }
73c4b7cd
AD		 2269 }
2270
e8e26350
PW		 2271 if (eicr & IXGBE_EICR_GPI_SDP1) {
2272 /* Clear the interrupt */
2273 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2274 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2275 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2276 ixgbe_service_event_schedule(adapter);
2277 }
e8e26350
PW		 2278 }
2279}
2280
cf8280ee
JB		 2281static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2282{
2283 struct ixgbe_hw *hw = &adapter->hw;
2284
2285 adapter->lsc_int++;
2286 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2287 adapter->link_check_timeout = jiffies;
2288 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2289 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2290 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2291 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2292 }
2293}
2294
fe49f04a
AD		 2295static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2296 u64 qmask)
2297{
2298 u32 mask;
bd508178 2299 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2300
bd508178
AD		 2301 switch (hw->mac.type) {
2302 case ixgbe_mac_82598EB:
fe49f04a 2303 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2304 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2305 break;
2306 case ixgbe_mac_82599EB:
b93a2226 2307 case ixgbe_mac_X540:
fe49f04a 2308 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2309 if (mask)
2310 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2311 mask = (qmask >> 32);
bd508178
AD		 2312 if (mask)
2313 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2314 break;
2315 default:
2316 break;
fe49f04a
AD		 2317 }
2318 /* skip the flush */
2319}
2320
2321static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2322 u64 qmask)
fe49f04a
AD		 2323{
2324 u32 mask;
bd508178 2325 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2326
bd508178
AD		 2327 switch (hw->mac.type) {
2328 case ixgbe_mac_82598EB:
fe49f04a 2329 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2330 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2331 break;
2332 case ixgbe_mac_82599EB:
b93a2226 2333 case ixgbe_mac_X540:
fe49f04a 2334 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2335 if (mask)
2336 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2337 mask = (qmask >> 32);
bd508178
AD		 2338 if (mask)
2339 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2340 break;
2341 default:
2342 break;
fe49f04a
AD		 2343 }
2344 /* skip the flush */
2345}
2346
021230d4 2347/**
2c4af694
AD		 2348 * ixgbe_irq_enable - Enable default interrupt generation settings
2349 * @adapter: board private structure
021230d4 2350 **/
2c4af694
AD		 2351static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2352 bool flush)
9a799d71 2353{
2c4af694 2354 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2355
2c4af694
AD		 2356 /* don't reenable LSC while waiting for link */
2357 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2358 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2359
2c4af694 2360 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2361 switch (adapter->hw.mac.type) {
2362 case ixgbe_mac_82599EB:
2363 mask |= IXGBE_EIMS_GPI_SDP0;
2364 break;
2365 case ixgbe_mac_X540:
2366 mask |= IXGBE_EIMS_TS;
2367 break;
2368 default:
2369 break;
2370 }
2c4af694
AD		 2371 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2372 mask |= IXGBE_EIMS_GPI_SDP1;
2373 switch (adapter->hw.mac.type) {
2374 case ixgbe_mac_82599EB:
2c4af694
AD		 2375 mask |= IXGBE_EIMS_GPI_SDP1;
2376 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2377 case ixgbe_mac_X540:
2378 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2379 mask |= IXGBE_EIMS_MAILBOX;
2380 break;
2381 default:
2382 break;
9a799d71 2383 }
db0677fa 2384
db0677fa
JK		 2385 if (adapter->hw.mac.type == ixgbe_mac_X540)
2386 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2387
2c4af694
AD		 2388 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2389 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2390 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2391
2c4af694
AD		 2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2393 if (queues)
2394 ixgbe_irq_enable_queues(adapter, ~0);
2395 if (flush)
2396 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2397}
2398
2c4af694 2399static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2400{
a65151ba 2401 struct ixgbe_adapter *adapter = data;
9a799d71 2402 struct ixgbe_hw *hw = &adapter->hw;
54037505 2403 u32 eicr;
91281fd3 2404
54037505
DS		 2405 /*
2406 * Workaround for Silicon errata. Use clear-by-write instead
2407 * of clear-by-read. Reading with EICS will return the
2408 * interrupt causes without clearing, which later be done
2409 * with the write to EICR.
2410 */
2411 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2412 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2413
cf8280ee
JB		 2414 if (eicr & IXGBE_EICR_LSC)
2415 ixgbe_check_lsc(adapter);
f0848276 2416
1cdd1ec8
GR		 2417 if (eicr & IXGBE_EICR_MAILBOX)
2418 ixgbe_msg_task(adapter);
efe3d3c8 2419
bd508178
AD		 2420 switch (hw->mac.type) {
2421 case ixgbe_mac_82599EB:
b93a2226 2422 case ixgbe_mac_X540:
2c4af694
AD		 2423 if (eicr & IXGBE_EICR_ECC)
2424 e_info(link, "Received unrecoverable ECC Err, please "
2425 "reboot\n");
c4cf55e5
PWJ		 2426 /* Handle Flow Director Full threshold interrupt */
2427 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2428 int reinit_count = 0;
c4cf55e5 2429 int i;
c4cf55e5 2430 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2431 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2432 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2433 &ring->state))
2434 reinit_count++;
2435 }
2436 if (reinit_count) {
2437 /* no more flow director interrupts until after init */
2438 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2439 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2440 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2441 }
2442 }
f0f9778d 2443 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2444 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2445 break;
2446 default:
2447 break;
c4cf55e5 2448 }
f0848276 2449
bd508178 2450 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2451
db0677fa
JK		 2452 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2453 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2454
7086400d 2455 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2456 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2457 ixgbe_irq_enable(adapter, false, false);
f0848276 2458
9a799d71 2459 return IRQ_HANDLED;
f0848276 2460}
91281fd3 2461
4ff7fb12 2462static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2463{
021230d4 2464 struct ixgbe_q_vector *q_vector = data;
91281fd3 2465
9b471446 2466 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2467
4ff7fb12
AD		 2468 if (q_vector->rx.ring || q_vector->tx.ring)
2469 napi_schedule(&q_vector->napi);
91281fd3 2470
9a799d71 2471 return IRQ_HANDLED;
91281fd3
AD		 2472}
2473
eb01b975
AD		 2474/**
2475 * ixgbe_poll - NAPI Rx polling callback
2476 * @napi: structure for representing this polling device
2477 * @budget: how many packets driver is allowed to clean
2478 *
2479 * This function is used for legacy and MSI, NAPI mode
2480 **/
8af3c33f 2481int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2482{
2483 struct ixgbe_q_vector *q_vector =
2484 container_of(napi, struct ixgbe_q_vector, napi);
2485 struct ixgbe_adapter *adapter = q_vector->adapter;
2486 struct ixgbe_ring *ring;
2487 int per_ring_budget;
2488 bool clean_complete = true;
2489
2490#ifdef CONFIG_IXGBE_DCA
2491 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2492 ixgbe_update_dca(q_vector);
2493#endif
2494
2495 ixgbe_for_each_ring(ring, q_vector->tx)
2496 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2497
2498 /* attempt to distribute budget to each queue fairly, but don't allow
2499 * the budget to go below 1 because we'll exit polling */
2500 if (q_vector->rx.count > 1)
2501 per_ring_budget = max(budget/q_vector->rx.count, 1);
2502 else
2503 per_ring_budget = budget;
2504
2505 ixgbe_for_each_ring(ring, q_vector->rx)
2506 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2507 per_ring_budget);
2508
2509 /* If all work not completed, return budget and keep polling */
2510 if (!clean_complete)
2511 return budget;
2512
2513 /* all work done, exit the polling mode */
2514 napi_complete(napi);
2515 if (adapter->rx_itr_setting & 1)
2516 ixgbe_set_itr(q_vector);
2517 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2518 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2519
2520 return 0;
2521}
2522
021230d4
AV		 2523/**
2524 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2525 * @adapter: board private structure
2526 *
2527 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2528 * interrupts from the kernel.
2529 **/
2530static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2531{
2532 struct net_device *netdev = adapter->netdev;
207867f5 2533 int vector, err;
e8e9f696 2534 int ri = 0, ti = 0;
021230d4 2535
49c7ffbe 2536 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2537 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2538 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2539
4ff7fb12 2540 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2541 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2542 "%s-%s-%d", netdev->name, "TxRx", ri++);
2543 ti++;
2544 } else if (q_vector->rx.ring) {
9fe93afd 2545 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2546 "%s-%s-%d", netdev->name, "rx", ri++);
2547 } else if (q_vector->tx.ring) {
9fe93afd 2548 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2549 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2550 } else {
2551 /* skip this unused q_vector */
2552 continue;
32aa77a4 2553 }
207867f5
AD		 2554 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2555 q_vector->name, q_vector);
9a799d71 2556 if (err) {
396e799c 2557 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2558 "Error: %d\n", err);
021230d4 2559 goto free_queue_irqs;
9a799d71 2560 }
207867f5
AD		 2561 /* If Flow Director is enabled, set interrupt affinity */
2562 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2563 /* assign the mask for this irq */
2564 irq_set_affinity_hint(entry->vector,
de88eeeb 2565 &q_vector->affinity_mask);
207867f5 2566 }
9a799d71
AK		 2567 }
2568
021230d4 2569 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2570 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2571 if (err) {
de88eeeb 2572 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2573 goto free_queue_irqs;
9a799d71
AK		 2574 }
2575
9a799d71
AK		 2576 return 0;
2577
021230d4 2578free_queue_irqs:
207867f5
AD		 2579 while (vector) {
2580 vector--;
2581 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2582 NULL);
2583 free_irq(adapter->msix_entries[vector].vector,
2584 adapter->q_vector[vector]);
2585 }
021230d4
AV		 2586 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2587 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2588 kfree(adapter->msix_entries);
2589 adapter->msix_entries = NULL;
9a799d71
AK		 2590 return err;
2591}
2592
2593/**
021230d4 2594 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2595 * @irq: interrupt number
2596 * @data: pointer to a network interface device structure
9a799d71
AK		 2597 **/
2598static irqreturn_t ixgbe_intr(int irq, void *data)
2599{
a65151ba 2600 struct ixgbe_adapter *adapter = data;
9a799d71 2601 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2602 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2603 u32 eicr;
2604
54037505 2605 /*
24ddd967 2606 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2607 * before the read of EICR.
2608 */
2609 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2610
021230d4 2611 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2612 * therefore no explicit interrupt disable is necessary */
021230d4 2613 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2614 if (!eicr) {
6af3b9eb
ET		 2615 /*
2616 * shared interrupt alert!
f47cf66e 2617 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2618 * have disabled interrupts due to EIAM
2619 * finish the workaround of silicon errata on 82598. Unmask
2620 * the interrupt that we masked before the EICR read.
2621 */
2622 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2623 ixgbe_irq_enable(adapter, true, true);
9a799d71 2624 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2625 }
9a799d71 2626
cf8280ee
JB		 2627 if (eicr & IXGBE_EICR_LSC)
2628 ixgbe_check_lsc(adapter);
021230d4 2629
bd508178
AD		 2630 switch (hw->mac.type) {
2631 case ixgbe_mac_82599EB:
e8e26350 2632 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2633 /* Fall through */
2634 case ixgbe_mac_X540:
2635 if (eicr & IXGBE_EICR_ECC)
2636 e_info(link, "Received unrecoverable ECC err, please "
2637 "reboot\n");
4f51bf70 2638 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2639 break;
2640 default:
2641 break;
2642 }
e8e26350 2643
0befdb3e 2644 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2645 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2646 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2647
b9f6ed2b
AD		 2648 /* would disable interrupts here but EIAM disabled it */
2649 napi_schedule(&q_vector->napi);
9a799d71 2650
6af3b9eb
ET		 2651 /*
2652 * re-enable link(maybe) and non-queue interrupts, no flush.
2653 * ixgbe_poll will re-enable the queue interrupts
2654 */
6af3b9eb
ET		 2655 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2656 ixgbe_irq_enable(adapter, false, false);
2657
9a799d71
AK		 2658 return IRQ_HANDLED;
2659}
2660
2661/**
2662 * ixgbe_request_irq - initialize interrupts
2663 * @adapter: board private structure
2664 *
2665 * Attempts to configure interrupts using the best available
2666 * capabilities of the hardware and kernel.
2667 **/
021230d4 2668static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2669{
2670 struct net_device *netdev = adapter->netdev;
021230d4 2671 int err;
9a799d71 2672
4cc6df29 2673 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2674 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2675 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2676 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2677 netdev->name, adapter);
4cc6df29 2678 else
a0607fd3 2679 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2680 netdev->name, adapter);
9a799d71 2681
de88eeeb 2682 if (err)
396e799c 2683 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2684
9a799d71
AK		 2685 return err;
2686}
2687
2688static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2689{
49c7ffbe 2690 int vector;
9a799d71 2691
49c7ffbe
AD		 2692 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2693 free_irq(adapter->pdev->irq, adapter);
2694 return;
2695 }
4cc6df29 2696
49c7ffbe
AD		 2697 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2698 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2699 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2700
49c7ffbe
AD		 2701 /* free only the irqs that were actually requested */
2702 if (!q_vector->rx.ring && !q_vector->tx.ring)
2703 continue;
207867f5 2704
49c7ffbe
AD		 2705 /* clear the affinity_mask in the IRQ descriptor */
2706 irq_set_affinity_hint(entry->vector, NULL);
2707
2708 free_irq(entry->vector, q_vector);
9a799d71 2709 }
49c7ffbe
AD		 2710
2711 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2712}
2713
22d5a71b
JB		 2714/**
2715 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2716 * @adapter: board private structure
2717 **/
2718static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2719{
bd508178
AD		 2720 switch (adapter->hw.mac.type) {
2721 case ixgbe_mac_82598EB:
835462fc 2722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2723 break;
2724 case ixgbe_mac_82599EB:
b93a2226 2725 case ixgbe_mac_X540:
835462fc
NS		 2726 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2727 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2729 break;
2730 default:
2731 break;
22d5a71b
JB		 2732 }
2733 IXGBE_WRITE_FLUSH(&adapter->hw);
2734 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2735 int vector;
2736
2737 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2738 synchronize_irq(adapter->msix_entries[vector].vector);
2739
2740 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2741 } else {
2742 synchronize_irq(adapter->pdev->irq);
2743 }
2744}
2745
9a799d71
AK		 2746/**
2747 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2748 *
2749 **/
2750static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2751{
d5bf4f67 2752 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2753
d5bf4f67
ET		 2754 /* rx/tx vector */
2755 if (adapter->rx_itr_setting == 1)
2756 q_vector->itr = IXGBE_20K_ITR;
2757 else
2758 q_vector->itr = adapter->rx_itr_setting;
2759
2760 ixgbe_write_eitr(q_vector);
9a799d71 2761
e8e26350
PW		 2762 ixgbe_set_ivar(adapter, 0, 0, 0);
2763 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2764
396e799c 2765 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2766}
2767
43e69bf0
AD		 2768/**
2769 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2770 * @adapter: board private structure
2771 * @ring: structure containing ring specific data
2772 *
2773 * Configure the Tx descriptor ring after a reset.
2774 **/
84418e3b
AD		 2775void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2776 struct ixgbe_ring *ring)
43e69bf0
AD		 2777{
2778 struct ixgbe_hw *hw = &adapter->hw;
2779 u64 tdba = ring->dma;
2f1860b8 2780 int wait_loop = 10;
b88c6de2 2781 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2782 u8 reg_idx = ring->reg_idx;
43e69bf0 2783
2f1860b8 2784 /* disable queue to avoid issues while updating state */
b88c6de2 2785 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2786 IXGBE_WRITE_FLUSH(hw);
2787
43e69bf0 2788 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2789 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2790 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2791 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2792 ring->count * sizeof(union ixgbe_adv_tx_desc));
2793 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2794 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2795 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2796
b88c6de2
AD		 2797 /*
2798 * set WTHRESH to encourage burst writeback, it should not be set
2799 * higher than 1 when ITR is 0 as it could cause false TX hangs
2800 *
2801 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2802 * to or less than the number of on chip descriptors, which is
2803 * currently 40.
2804 */
e954b374 2805 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2806 txdctl |= (1 << 16); /* WTHRESH = 1 */
2807 else
2808 txdctl |= (8 << 16); /* WTHRESH = 8 */
2809
e954b374
AD		 2810 /*
2811 * Setting PTHRESH to 32 both improves performance
2812 * and avoids a TX hang with DFP enabled
2813 */
b88c6de2
AD		 2814 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2815 32; /* PTHRESH = 32 */
2f1860b8
AD		 2816
2817 /* reinitialize flowdirector state */
39cb681b 2818 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2819 ring->atr_sample_rate = adapter->atr_sample_rate;
2820 ring->atr_count = 0;
2821 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2822 } else {
2823 ring->atr_sample_rate = 0;
2824 }
2f1860b8 2825
c84d324c
JF		 2826 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2827
2f1860b8 2828 /* enable queue */
2f1860b8
AD		 2829 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2830
2831 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2832 if (hw->mac.type == ixgbe_mac_82598EB &&
2833 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2834 return;
2835
2836 /* poll to verify queue is enabled */
2837 do {
032b4325 2838 usleep_range(1000, 2000);
2f1860b8
AD		 2839 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2840 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2841 if (!wait_loop)
2842 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2843}
2844
120ff942
AD		 2845static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2846{
2847 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2848 u32 rttdcs, mtqc;
8b1c0b24 2849 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2850
2851 if (hw->mac.type == ixgbe_mac_82598EB)
2852 return;
2853
2854 /* disable the arbiter while setting MTQC */
2855 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2856 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2857 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2858
2859 /* set transmit pool layout */
671c0adb
AD		 2860 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2861 mtqc = IXGBE_MTQC_VT_ENA;
2862 if (tcs > 4)
2863 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2864 else if (tcs > 1)
2865 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2866 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2867 mtqc |= IXGBE_MTQC_32VF;
2868 else
2869 mtqc |= IXGBE_MTQC_64VF;
2870 } else {
2871 if (tcs > 4)
2872 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2873 else if (tcs > 1)
2874 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2875 else
671c0adb
AD		 2876 mtqc = IXGBE_MTQC_64Q_1PB;
2877 }
120ff942 2878
671c0adb 2879 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2880
671c0adb
AD		 2881 /* Enable Security TX Buffer IFG for multiple pb */
2882 if (tcs) {
2883 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2884 sectx |= IXGBE_SECTX_DCB;
2885 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2886 }
2887
2888 /* re-enable the arbiter */
2889 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2890 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2891}
2892
9a799d71 2893/**
3a581073 2894 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2895 * @adapter: board private structure
2896 *
2897 * Configure the Tx unit of the MAC after a reset.
2898 **/
2899static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2900{
2f1860b8
AD		 2901 struct ixgbe_hw *hw = &adapter->hw;
2902 u32 dmatxctl;
43e69bf0 2903 u32 i;
9a799d71 2904
2f1860b8
AD		 2905 ixgbe_setup_mtqc(adapter);
2906
2907 if (hw->mac.type != ixgbe_mac_82598EB) {
2908 /* DMATXCTL.EN must be before Tx queues are enabled */
2909 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2910 dmatxctl |= IXGBE_DMATXCTL_TE;
2911 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2912 }
2913
9a799d71 2914 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2915 for (i = 0; i < adapter->num_tx_queues; i++)
2916 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2917}
2918
3ebe8fde
AD		 2919static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2920 struct ixgbe_ring *ring)
2921{
2922 struct ixgbe_hw *hw = &adapter->hw;
2923 u8 reg_idx = ring->reg_idx;
2924 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2925
2926 srrctl |= IXGBE_SRRCTL_DROP_EN;
2927
2928 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2929}
2930
2931static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2932 struct ixgbe_ring *ring)
2933{
2934 struct ixgbe_hw *hw = &adapter->hw;
2935 u8 reg_idx = ring->reg_idx;
2936 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2937
2938 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2939
2940 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2941}
2942
2943#ifdef CONFIG_IXGBE_DCB
2944void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2945#else
2946static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2947#endif
2948{
2949 int i;
2950 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2951
2952 if (adapter->ixgbe_ieee_pfc)
2953 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2954
2955 /*
2956 * We should set the drop enable bit if:
2957 * SR-IOV is enabled
2958 * or
2959 * Number of Rx queues > 1 and flow control is disabled
2960 *
2961 * This allows us to avoid head of line blocking for security
2962 * and performance reasons.
2963 */
2964 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2965 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2966 for (i = 0; i < adapter->num_rx_queues; i++)
2967 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2968 } else {
2969 for (i = 0; i < adapter->num_rx_queues; i++)
2970 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2971 }
2972}
2973
e8e26350 2974#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2975
a6616b42 2976static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2977 struct ixgbe_ring *rx_ring)
cc41ac7c 2978{
45e9baa5 2979 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2980 u32 srrctl;
bf29ee6c 2981 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2982
45e9baa5
AD		 2983 if (hw->mac.type == ixgbe_mac_82598EB) {
2984 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2985
45e9baa5
AD		 2986 /*
2987 * if VMDq is not active we must program one srrctl register
2988 * per RSS queue since we have enabled RDRXCTL.MVMEN
2989 */
2990 reg_idx &= mask;
2991 }
cc41ac7c 2992
45e9baa5
AD		 2993 /* configure header buffer length, needed for RSC */
2994 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2995
45e9baa5 2996 /* configure the packet buffer length */
f800326d 2997 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2998
2999 /* configure descriptor type */
f800326d 3000 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3001
45e9baa5 3002 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3003}
9a799d71 3004
05abb126 3005static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3006{
05abb126
AD		 3007 struct ixgbe_hw *hw = &adapter->hw;
3008 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3009 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3010 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3011 u32 mrqc = 0, reta = 0;
3012 u32 rxcsum;
3013 int i, j;
671c0adb
AD		 3014 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3015
671c0adb
AD		 3016 /*
3017 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3018 * make full use of any rings they may have. We will use the
3019 * PSRTYPE register to control how many rings we use within the PF.
3020 */
3021 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3022 rss_i = 2;
0cefafad 3023
05abb126
AD		 3024 /* Fill out hash function seeds */
3025 for (i = 0; i < 10; i++)
3026 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3027
3028 /* Fill out redirection table */
3029 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3030 if (j == rss_i)
05abb126
AD		 3031 j = 0;
3032 /* reta = 4-byte sliding window of
3033 * 0x00..(indices-1)(indices-1)00..etc. */
3034 reta = (reta << 8) | (j * 0x11);
3035 if ((i & 3) == 3)
3036 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3037 }
0cefafad 3038
05abb126
AD		 3039 /* Disable indicating checksum in descriptor, enables RSS hash */
3040 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3041 rxcsum |= IXGBE_RXCSUM_PCSD;
3042 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3043
671c0adb 3044 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3045 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3046 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3047 } else {
671c0adb
AD		 3048 u8 tcs = netdev_get_num_tc(adapter->netdev);
3049
3050 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3051 if (tcs > 4)
3052 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3053 else if (tcs > 1)
3054 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3055 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3056 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3057 else
671c0adb
AD		 3058 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3059 } else {
3060 if (tcs > 4)
8b1c0b24 3061 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3062 else if (tcs > 1)
3063 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3064 else
3065 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3066 }
0cefafad
JB		 3067 }
3068
05abb126 3069 /* Perform hash on these packet types */
671c0adb
AD		 3070 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3071 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3072 IXGBE_MRQC_RSS_FIELD_IPV6 |
3073 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3074
ef6afc0c
AD		 3075 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3076 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3077 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3078 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3079
05abb126 3080 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3081}
3082
bb5a9ad2
NS		 3083/**
3084 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3085 * @adapter: address of board private structure
3086 * @index: index of ring to set
bb5a9ad2 3087 **/
082757af 3088static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3089 struct ixgbe_ring *ring)
bb5a9ad2 3090{
bb5a9ad2 3091 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3092 u32 rscctrl;
bf29ee6c 3093 u8 reg_idx = ring->reg_idx;
7367096a 3094
7d637bcc 3095 if (!ring_is_rsc_enabled(ring))
7367096a 3096 return;
bb5a9ad2 3097
7367096a 3098 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3099 rscctrl |= IXGBE_RSCCTL_RSCEN;
3100 /*
3101 * we must limit the number of descriptors so that the
3102 * total size of max desc * buf_len is not greater
642c680e 3103 * than 65536
bb5a9ad2 3104 */
f800326d 3105 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3106 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3107}
3108
9e10e045
AD		 3109#define IXGBE_MAX_RX_DESC_POLL 10
3110static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3111 struct ixgbe_ring *ring)
3112{
3113 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3114 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3115 u32 rxdctl;
bf29ee6c 3116 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3117
3118 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3119 if (hw->mac.type == ixgbe_mac_82598EB &&
3120 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3121 return;
3122
3123 do {
032b4325 3124 usleep_range(1000, 2000);
9e10e045
AD		 3125 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3126 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3127
3128 if (!wait_loop) {
3129 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3130 "the polling period\n", reg_idx);
3131 }
3132}
3133
2d39d576
YZ		 3134void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3135 struct ixgbe_ring *ring)
3136{
3137 struct ixgbe_hw *hw = &adapter->hw;
3138 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3139 u32 rxdctl;
3140 u8 reg_idx = ring->reg_idx;
3141
3142 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3143 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3144
3145 /* write value back with RXDCTL.ENABLE bit cleared */
3146 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3147
3148 if (hw->mac.type == ixgbe_mac_82598EB &&
3149 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3150 return;
3151
3152 /* the hardware may take up to 100us to really disable the rx queue */
3153 do {
3154 udelay(10);
3155 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3156 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3157
3158 if (!wait_loop) {
3159 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3160 "the polling period\n", reg_idx);
3161 }
3162}
3163
84418e3b
AD		 3164void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3165 struct ixgbe_ring *ring)
acd37177
AD		 3166{
3167 struct ixgbe_hw *hw = &adapter->hw;
3168 u64 rdba = ring->dma;
9e10e045 3169 u32 rxdctl;
bf29ee6c 3170 u8 reg_idx = ring->reg_idx;
acd37177 3171
9e10e045
AD		 3172 /* disable queue to avoid issues while updating state */
3173 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3174 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3175
acd37177
AD		 3176 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3177 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3178 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3179 ring->count * sizeof(union ixgbe_adv_rx_desc));
3180 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3181 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3182 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3183
3184 ixgbe_configure_srrctl(adapter, ring);
3185 ixgbe_configure_rscctl(adapter, ring);
3186
e9f98072
GR		 3187 /* If operating in IOV mode set RLPML for X540 */
3188 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3189 hw->mac.type == ixgbe_mac_X540) {
3190 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3191 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3192 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3193 }
3194
9e10e045
AD		 3195 if (hw->mac.type == ixgbe_mac_82598EB) {
3196 /*
3197 * enable cache line friendly hardware writes:
3198 * PTHRESH=32 descriptors (half the internal cache),
3199 * this also removes ugly rx_no_buffer_count increment
3200 * HTHRESH=4 descriptors (to minimize latency on fetch)
3201 * WTHRESH=8 burst writeback up to two cache lines
3202 */
3203 rxdctl &= ~0x3FFFFF;
3204 rxdctl |= 0x080420;
3205 }
3206
3207 /* enable receive descriptor ring */
3208 rxdctl |= IXGBE_RXDCTL_ENABLE;
3209 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3210
3211 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3212 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3213}
3214
48654521
AD		 3215static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3216{
3217 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3218 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3219 int p;
3220
3221 /* PSRTYPE must be initialized in non 82598 adapters */
3222 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3223 IXGBE_PSRTYPE_UDPHDR |
3224 IXGBE_PSRTYPE_IPV4HDR |
48654521 3225 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3226 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3227
3228 if (hw->mac.type == ixgbe_mac_82598EB)
3229 return;
3230
fbe7ca7f
AD		 3231 if (rss_i > 3)
3232 psrtype |= 2 << 29;
3233 else if (rss_i > 1)
3234 psrtype |= 1 << 29;
48654521
AD		 3235
3236 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3237 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3238 psrtype);
3239}
3240
f5b4a52e
AD		 3241static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3242{
3243 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3244 u32 reg_offset, vf_shift;
435b19f6 3245 u32 gcr_ext, vmdctl;
de4c7f65 3246 int i;
f5b4a52e
AD		 3247
3248 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3249 return;
3250
3251 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3252 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3253 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3254 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3255 vmdctl |= IXGBE_VT_CTL_REPLEN;
3256 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3257
1d9c0bfd
AD		 3258 vf_shift = VMDQ_P(0) % 32;
3259 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3260
3261 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3262 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3263 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3264 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3265 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3266
3267 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3268 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3269
3270 /*
3271 * Set up VF register offsets for selected VT Mode,
3272 * i.e. 32 or 64 VFs for SR-IOV
3273 */
73079ea0
AD		 3274 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3275 case IXGBE_82599_VMDQ_8Q_MASK:
3276 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3277 break;
3278 case IXGBE_82599_VMDQ_4Q_MASK:
3279 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3280 break;
3281 default:
3282 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3283 break;
3284 }
3285
f5b4a52e
AD		 3286 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3287
435b19f6 3288
a985b6c3 3289 /* Enable MAC Anti-Spoofing */
435b19f6 3290 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3291 adapter->num_vfs);
de4c7f65
GR		 3292 /* For VFs that have spoof checking turned off */
3293 for (i = 0; i < adapter->num_vfs; i++) {
3294 if (!adapter->vfinfo[i].spoofchk_enabled)
3295 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3296 }
f5b4a52e
AD		 3297}
3298
477de6ed 3299static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3300{
9a799d71
AK		 3301 struct ixgbe_hw *hw = &adapter->hw;
3302 struct net_device *netdev = adapter->netdev;
3303 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3304 struct ixgbe_ring *rx_ring;
3305 int i;
3306 u32 mhadd, hlreg0;
48654521 3307
63f39bd1 3308#ifdef IXGBE_FCOE
477de6ed
AD		 3309 /* adjust max frame to be able to do baby jumbo for FCoE */
3310 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3311 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3312 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3313
477de6ed 3314#endif /* IXGBE_FCOE */
872844dd
AD		 3315
3316 /* adjust max frame to be at least the size of a standard frame */
3317 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3318 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3319
477de6ed
AD		 3320 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3321 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3322 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3323 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3324
3325 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3326 }
3327
3328 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3329 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3330 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3331 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3332
0cefafad
JB		 3333 /*
3334 * Setup the HW Rx Head and Tail Descriptor Pointers and
3335 * the Base and Length of the Rx Descriptor Ring
3336 */
9a799d71 3337 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3338 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3339 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3340 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3341 else
7d637bcc 3342 clear_ring_rsc_enabled(rx_ring);
477de6ed 3343 }
477de6ed
AD		 3344}
3345
7367096a
AD		 3346static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3347{
3348 struct ixgbe_hw *hw = &adapter->hw;
3349 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3350
3351 switch (hw->mac.type) {
3352 case ixgbe_mac_82598EB:
3353 /*
3354 * For VMDq support of different descriptor types or
3355 * buffer sizes through the use of multiple SRRCTL
3356 * registers, RDRXCTL.MVMEN must be set to 1
3357 *
3358 * also, the manual doesn't mention it clearly but DCA hints
3359 * will only use queue 0's tags unless this bit is set. Side
3360 * effects of setting this bit are only that SRRCTL must be
3361 * fully programmed [0..15]
3362 */
3363 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3364 break;
3365 case ixgbe_mac_82599EB:
b93a2226 3366 case ixgbe_mac_X540:
7367096a
AD		 3367 /* Disable RSC for ACK packets */
3368 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3369 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3370 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3371 /* hardware requires some bits to be set by default */
3372 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3373 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3374 break;
3375 default:
3376 /* We should do nothing since we don't know this hardware */
3377 return;
3378 }
3379
3380 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3381}
3382
477de6ed
AD		 3383/**
3384 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3385 * @adapter: board private structure
3386 *
3387 * Configure the Rx unit of the MAC after a reset.
3388 **/
3389static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3390{
3391 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3392 int i;
3393 u32 rxctrl;
477de6ed
AD		 3394
3395 /* disable receives while setting up the descriptors */
3396 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3397 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3398
3399 ixgbe_setup_psrtype(adapter);
7367096a 3400 ixgbe_setup_rdrxctl(adapter);
477de6ed 3401
9e10e045 3402 /* Program registers for the distribution of queues */
f5b4a52e 3403 ixgbe_setup_mrqc(adapter);
f5b4a52e 3404
477de6ed
AD		 3405 /* set_rx_buffer_len must be called before ring initialization */
3406 ixgbe_set_rx_buffer_len(adapter);
3407
3408 /*
3409 * Setup the HW Rx Head and Tail Descriptor Pointers and
3410 * the Base and Length of the Rx Descriptor Ring
3411 */
9e10e045
AD		 3412 for (i = 0; i < adapter->num_rx_queues; i++)
3413 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3414
9e10e045
AD		 3415 /* disable drop enable for 82598 parts */
3416 if (hw->mac.type == ixgbe_mac_82598EB)
3417 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3418
3419 /* enable all receives */
3420 rxctrl |= IXGBE_RXCTRL_RXEN;
3421 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3422}
3423
8e586137 3424static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3425{
3426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3427 struct ixgbe_hw *hw = &adapter->hw;
3428
3429 /* add VID to filter table */
1d9c0bfd 3430 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3431 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3432
3433 return 0;
068c89b0
DS		 3434}
3435
8e586137 3436static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3437{
3438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3439 struct ixgbe_hw *hw = &adapter->hw;
3440
068c89b0 3441 /* remove VID from filter table */
1d9c0bfd 3442 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3443 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3444
3445 return 0;
068c89b0
DS		 3446}
3447
5f6c0181
JB		 3448/**
3449 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3450 * @adapter: driver data
3451 */
3452static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3453{
3454 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3455 u32 vlnctrl;
3456
3457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3458 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3459 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3460}
3461
3462/**
3463 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3464 * @adapter: driver data
3465 */
3466static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3467{
3468 struct ixgbe_hw *hw = &adapter->hw;
3469 u32 vlnctrl;
3470
3471 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3472 vlnctrl |= IXGBE_VLNCTRL_VFE;
3473 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3474 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3475}
3476
3477/**
3478 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3479 * @adapter: driver data
3480 */
3481static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3482{
3483 struct ixgbe_hw *hw = &adapter->hw;
3484 u32 vlnctrl;
5f6c0181
JB		 3485 int i, j;
3486
3487 switch (hw->mac.type) {
3488 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3489 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3490 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3491 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3492 break;
3493 case ixgbe_mac_82599EB:
b93a2226 3494 case ixgbe_mac_X540:
5f6c0181
JB		 3495 for (i = 0; i < adapter->num_rx_queues; i++) {
3496 j = adapter->rx_ring[i]->reg_idx;
3497 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3498 vlnctrl &= ~IXGBE_RXDCTL_VME;
3499 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3500 }
3501 break;
3502 default:
3503 break;
3504 }
3505}
3506
3507/**
f62bbb5e 3508 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3509 * @adapter: driver data
3510 */
f62bbb5e 3511static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3512{
3513 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3514 u32 vlnctrl;
5f6c0181
JB		 3515 int i, j;
3516
3517 switch (hw->mac.type) {
3518 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3519 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3520 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3521 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3522 break;
3523 case ixgbe_mac_82599EB:
b93a2226 3524 case ixgbe_mac_X540:
5f6c0181
JB		 3525 for (i = 0; i < adapter->num_rx_queues; i++) {
3526 j = adapter->rx_ring[i]->reg_idx;
3527 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3528 vlnctrl |= IXGBE_RXDCTL_VME;
3529 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3530 }
3531 break;
3532 default:
3533 break;
3534 }
3535}
3536
9a799d71
AK		 3537static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3538{
f62bbb5e 3539 u16 vid;
9a799d71 3540
f62bbb5e
JG		 3541 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3542
3543 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3544 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3545}
3546
2850062a
AD		 3547/**
3548 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3549 * @netdev: network interface device structure
3550 *
3551 * Writes unicast address list to the RAR table.
3552 * Returns: -ENOMEM on failure/insufficient address space
3553 * 0 on no addresses written
3554 * X on writing X addresses to the RAR table
3555 **/
3556static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3557{
3558 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3559 struct ixgbe_hw *hw = &adapter->hw;
95447461 3560 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3561 int count = 0;
3562
95447461
JF		 3563 /* In SR-IOV mode significantly less RAR entries are available */
3564 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3565 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3566
2850062a
AD		 3567 /* return ENOMEM indicating insufficient memory for addresses */
3568 if (netdev_uc_count(netdev) > rar_entries)
3569 return -ENOMEM;
3570
95447461 3571 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3572 struct netdev_hw_addr *ha;
3573 /* return error if we do not support writing to RAR table */
3574 if (!hw->mac.ops.set_rar)
3575 return -ENOMEM;
3576
3577 netdev_for_each_uc_addr(ha, netdev) {
3578 if (!rar_entries)
3579 break;
3580 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3581 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3582 count++;
3583 }
3584 }
3585 /* write the addresses in reverse order to avoid write combining */
3586 for (; rar_entries > 0 ; rar_entries--)
3587 hw->mac.ops.clear_rar(hw, rar_entries);
3588
3589 return count;
3590}
3591
9a799d71 3592/**
2c5645cf 3593 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3594 * @netdev: network interface device structure
3595 *
2c5645cf
CL		 3596 * The set_rx_method entry point is called whenever the unicast/multicast
3597 * address list or the network interface flags are updated. This routine is
3598 * responsible for configuring the hardware for proper unicast, multicast and
3599 * promiscuous mode.
9a799d71 3600 **/
7f870475 3601void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3602{
3603 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3604 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3605 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3606 int count;
9a799d71
AK		 3607
3608 /* Check for Promiscuous and All Multicast modes */
3609
3610 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611
f5dc442b 3612 /* set all bits that we expect to always be set */
3f2d1c0f 3613 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3614 fctrl |= IXGBE_FCTRL_BAM;
3615 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3616 fctrl |= IXGBE_FCTRL_PMCF;
3617
2850062a
AD		 3618 /* clear the bits we are changing the status of */
3619 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3620
9a799d71 3621 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3622 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3623 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3624 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3625 /* don't hardware filter vlans in promisc mode */
3626 ixgbe_vlan_filter_disable(adapter);
9a799d71 3627 } else {
746b9f02
PM		 3628 if (netdev->flags & IFF_ALLMULTI) {
3629 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3630 vmolr |= IXGBE_VMOLR_MPE;
3631 } else {
3632 /*
3633 * Write addresses to the MTA, if the attempt fails
25985edc 3634 * then we should just turn on promiscuous mode so
2850062a
AD		 3635 * that we can at least receive multicast traffic
3636 */
3637 hw->mac.ops.update_mc_addr_list(hw, netdev);
3638 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3639 }
5f6c0181 3640 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3641 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3642 }
3643
3644 /*
3645 * Write addresses to available RAR registers, if there is not
3646 * sufficient space to store all the addresses then enable
3647 * unicast promiscuous mode
3648 */
3649 count = ixgbe_write_uc_addr_list(netdev);
3650 if (count < 0) {
3651 fctrl |= IXGBE_FCTRL_UPE;
3652 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3653 }
3654
1d9c0bfd 3655 if (adapter->num_vfs)
1cdd1ec8 3656 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3657
3658 if (hw->mac.type != ixgbe_mac_82598EB) {
3659 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3660 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3661 IXGBE_VMOLR_ROPE);
1d9c0bfd 3662 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3663 }
3664
3f2d1c0f
BG		 3665 /* This is useful for sniffing bad packets. */
3666 if (adapter->netdev->features & NETIF_F_RXALL) {
3667 /* UPE and MPE will be handled by normal PROMISC logic
3668 * in e1000e_set_rx_mode */
3669 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3670 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3671 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3672
3673 fctrl &= ~(IXGBE_FCTRL_DPF);
3674 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3675 }
3676
2850062a 3677 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3678
3679 if (netdev->features & NETIF_F_HW_VLAN_RX)
3680 ixgbe_vlan_strip_enable(adapter);
3681 else
3682 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3683}
3684
021230d4
AV		 3685static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3686{
3687 int q_idx;
021230d4 3688
49c7ffbe
AD		 3689 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3690 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3691}
3692
3693static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3694{
3695 int q_idx;
021230d4 3696
49c7ffbe
AD		 3697 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3698 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3699}
3700
7a6b6f51 3701#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3702/**
2f90b865
AD		 3703 * ixgbe_configure_dcb - Configure DCB hardware
3704 * @adapter: ixgbe adapter struct
3705 *
3706 * This is called by the driver on open to configure the DCB hardware.
3707 * This is also called by the gennetlink interface when reconfiguring
3708 * the DCB state.
3709 */
3710static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3711{
3712 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3713 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3714
67ebd791
AD		 3715 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3716 if (hw->mac.type == ixgbe_mac_82598EB)
3717 netif_set_gso_max_size(adapter->netdev, 65536);
3718 return;
3719 }
3720
3721 if (hw->mac.type == ixgbe_mac_82598EB)
3722 netif_set_gso_max_size(adapter->netdev, 32768);
3723
971060b1 3724#ifdef IXGBE_FCOE
b120818e
JF		 3725 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3726 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3727#endif
b120818e
JF		 3728
3729 /* reconfigure the hardware */
3730 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3731 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3732 DCB_TX_CONFIG);
3733 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3734 DCB_RX_CONFIG);
3735 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3736 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3737 ixgbe_dcb_hw_ets(&adapter->hw,
3738 adapter->ixgbe_ieee_ets,
3739 max_frame);
3740 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3741 adapter->ixgbe_ieee_pfc->pfc_en,
3742 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3743 }
8187cd48
JF		 3744
3745 /* Enable RSS Hash per TC */
3746 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3747 u32 msb = 0;
3748 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3749
d411a936
AD		 3750 while (rss_i) {
3751 msb++;
3752 rss_i >>= 1;
3753 }
8187cd48 3754
4ae63730
AD		 3755 /* write msb to all 8 TCs in one write */
3756 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3757 }
2f90b865 3758}
9da712d2
JF		 3759#endif
3760
3761/* Additional bittime to account for IXGBE framing */
3762#define IXGBE_ETH_FRAMING 20
3763
49ce9c2c 3764/**
9da712d2
JF		 3765 * ixgbe_hpbthresh - calculate high water mark for flow control
3766 *
3767 * @adapter: board private structure to calculate for
49ce9c2c 3768 * @pb: packet buffer to calculate
9da712d2
JF		 3769 */
3770static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3771{
3772 struct ixgbe_hw *hw = &adapter->hw;
3773 struct net_device *dev = adapter->netdev;
3774 int link, tc, kb, marker;
3775 u32 dv_id, rx_pba;
3776
3777 /* Calculate max LAN frame size */
3778 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3779
3780#ifdef IXGBE_FCOE
3781 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3782 if ((dev->features & NETIF_F_FCOE_MTU) &&
3783 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3784 (pb == ixgbe_fcoe_get_tc(adapter)))
3785 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3786
3787#endif
9da712d2
JF		 3788 /* Calculate delay value for device */
3789 switch (hw->mac.type) {
3790 case ixgbe_mac_X540:
3791 dv_id = IXGBE_DV_X540(link, tc);
3792 break;
3793 default:
3794 dv_id = IXGBE_DV(link, tc);
3795 break;
3796 }
3797
3798 /* Loopback switch introduces additional latency */
3799 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3800 dv_id += IXGBE_B2BT(tc);
3801
3802 /* Delay value is calculated in bit times convert to KB */
3803 kb = IXGBE_BT2KB(dv_id);
3804 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3805
3806 marker = rx_pba - kb;
3807
3808 /* It is possible that the packet buffer is not large enough
3809 * to provide required headroom. In this case throw an error
3810 * to user and a do the best we can.
3811 */
3812 if (marker < 0) {
3813 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3814 "headroom to support flow control."
3815 "Decrease MTU or number of traffic classes\n", pb);
3816 marker = tc + 1;
3817 }
3818
3819 return marker;
3820}
3821
49ce9c2c 3822/**
9da712d2
JF		 3823 * ixgbe_lpbthresh - calculate low water mark for for flow control
3824 *
3825 * @adapter: board private structure to calculate for
49ce9c2c 3826 * @pb: packet buffer to calculate
9da712d2
JF		 3827 */
3828static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3829{
3830 struct ixgbe_hw *hw = &adapter->hw;
3831 struct net_device *dev = adapter->netdev;
3832 int tc;
3833 u32 dv_id;
3834
3835 /* Calculate max LAN frame size */
3836 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3837
3838 /* Calculate delay value for device */
3839 switch (hw->mac.type) {
3840 case ixgbe_mac_X540:
3841 dv_id = IXGBE_LOW_DV_X540(tc);
3842 break;
3843 default:
3844 dv_id = IXGBE_LOW_DV(tc);
3845 break;
3846 }
3847
3848 /* Delay value is calculated in bit times convert to KB */
3849 return IXGBE_BT2KB(dv_id);
3850}
3851
3852/*
3853 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3854 */
3855static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3856{
3857 struct ixgbe_hw *hw = &adapter->hw;
3858 int num_tc = netdev_get_num_tc(adapter->netdev);
3859 int i;
3860
3861 if (!num_tc)
3862 num_tc = 1;
3863
3864 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3865
3866 for (i = 0; i < num_tc; i++) {
3867 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3868
3869 /* Low water marks must not be larger than high water marks */
3870 if (hw->fc.low_water > hw->fc.high_water[i])
3871 hw->fc.low_water = 0;
3872 }
3873}
3874
80605c65
JF		 3875static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3876{
80605c65 3877 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3878 int hdrm;
3879 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3880
3881 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3882 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3883 hdrm = 32 << adapter->fdir_pballoc;
3884 else
3885 hdrm = 0;
80605c65 3886
f7e1027f 3887 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3888 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3889}
3890
e4911d57
AD		 3891static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3892{
3893 struct ixgbe_hw *hw = &adapter->hw;
3894 struct hlist_node *node, *node2;
3895 struct ixgbe_fdir_filter *filter;
3896
3897 spin_lock(&adapter->fdir_perfect_lock);
3898
3899 if (!hlist_empty(&adapter->fdir_filter_list))
3900 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3901
3902 hlist_for_each_entry_safe(filter, node, node2,
3903 &adapter->fdir_filter_list, fdir_node) {
3904 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3905 &filter->filter,
3906 filter->sw_idx,
3907 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3908 IXGBE_FDIR_DROP_QUEUE :
3909 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3910 }
3911
3912 spin_unlock(&adapter->fdir_perfect_lock);
3913}
3914
9a799d71
AK		 3915static void ixgbe_configure(struct ixgbe_adapter *adapter)
3916{
d2f5e7f3
AS		 3917 struct ixgbe_hw *hw = &adapter->hw;
3918
80605c65 3919 ixgbe_configure_pb(adapter);
7a6b6f51 3920#ifdef CONFIG_IXGBE_DCB
67ebd791 3921 ixgbe_configure_dcb(adapter);
2f90b865 3922#endif
b35d4d42
AD		 3923 /*
3924 * We must restore virtualization before VLANs or else
3925 * the VLVF registers will not be populated
3926 */
3927 ixgbe_configure_virtualization(adapter);
9a799d71 3928
4c1d7b4b 3929 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3930 ixgbe_restore_vlan(adapter);
3931
d2f5e7f3
AS		 3932 switch (hw->mac.type) {
3933 case ixgbe_mac_82599EB:
3934 case ixgbe_mac_X540:
3935 hw->mac.ops.disable_rx_buff(hw);
3936 break;
3937 default:
3938 break;
3939 }
3940
c4cf55e5 3941 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3942 ixgbe_init_fdir_signature_82599(&adapter->hw,
3943 adapter->fdir_pballoc);
e4911d57
AD		 3944 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3945 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3946 adapter->fdir_pballoc);
3947 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3948 }
4c1d7b4b 3949
d2f5e7f3
AS		 3950 switch (hw->mac.type) {
3951 case ixgbe_mac_82599EB:
3952 case ixgbe_mac_X540:
3953 hw->mac.ops.enable_rx_buff(hw);
3954 break;
3955 default:
3956 break;
3957 }
3958
7c8ae65a
AD		 3959#ifdef IXGBE_FCOE
3960 /* configure FCoE L2 filters, redirection table, and Rx control */
3961 ixgbe_configure_fcoe(adapter);
3962
3963#endif /* IXGBE_FCOE */
9a799d71
AK		 3964 ixgbe_configure_tx(adapter);
3965 ixgbe_configure_rx(adapter);
9a799d71
AK		 3966}
3967
e8e26350
PW		 3968static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3969{
3970 switch (hw->phy.type) {
3971 case ixgbe_phy_sfp_avago:
3972 case ixgbe_phy_sfp_ftl:
3973 case ixgbe_phy_sfp_intel:
3974 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3975 case ixgbe_phy_sfp_passive_tyco:
3976 case ixgbe_phy_sfp_passive_unknown:
3977 case ixgbe_phy_sfp_active_unknown:
3978 case ixgbe_phy_sfp_ftl_active:
e8e26350 3979 return true;
8917b447
AD		 3980 case ixgbe_phy_nl:
3981 if (hw->mac.type == ixgbe_mac_82598EB)
3982 return true;
e8e26350
PW		 3983 default:
3984 return false;
3985 }
3986}
3987
0ecc061d 3988/**
e8e26350
PW		 3989 * ixgbe_sfp_link_config - set up SFP+ link
3990 * @adapter: pointer to private adapter struct
3991 **/
3992static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3993{
7086400d 3994 /*
52f33af8 3995 * We are assuming the worst case scenario here, and that
7086400d
AD		 3996 * is that an SFP was inserted/removed after the reset
3997 * but before SFP detection was enabled. As such the best
3998 * solution is to just start searching as soon as we start
3999 */
4000 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4001 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4002
7086400d 4003 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4004}
4005
4006/**
4007 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4008 * @hw: pointer to private hardware struct
4009 *
4010 * Returns 0 on success, negative on failure
4011 **/
e8e26350 4012static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 4013{
4014 u32 autoneg;
8620a103 4015 bool negotiation, link_up = false;
0ecc061d
PWJ		 4016 u32 ret = IXGBE_ERR_LINK_SETUP;
4017
4018 if (hw->mac.ops.check_link)
4019 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
4020
4021 if (ret)
4022 goto link_cfg_out;
4023
0b0c2b31
ET		 4024 autoneg = hw->phy.autoneg_advertised;
4025 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 4026 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4027 &negotiation);
0ecc061d
PWJ		 4028 if (ret)
4029 goto link_cfg_out;
4030
8620a103
MC		 4031 if (hw->mac.ops.setup_link)
4032 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 4033link_cfg_out:
4034 return ret;
4035}
4036
a34bcfff 4037static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4038{
9a799d71 4039 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4040 u32 gpie = 0;
9a799d71 4041
9b471446 4042 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4043 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4044 IXGBE_GPIE_OCD;
4045 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4046 /*
4047 * use EIAM to auto-mask when MSI-X interrupt is asserted
4048 * this saves a register write for every interrupt
4049 */
4050 switch (hw->mac.type) {
4051 case ixgbe_mac_82598EB:
4052 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4053 break;
9b471446 4054 case ixgbe_mac_82599EB:
b93a2226
DS		 4055 case ixgbe_mac_X540:
4056 default:
9b471446
JB		 4057 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4058 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4059 break;
4060 }
4061 } else {
021230d4
AV		 4062 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4063 * specifically only auto mask tx and rx interrupts */
4064 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4065 }
9a799d71 4066
a34bcfff
AD		 4067 /* XXX: to interrupt immediately for EICS writes, enable this */
4068 /* gpie |= IXGBE_GPIE_EIMEN; */
4069
4070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4071 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4072
4073 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4074 case IXGBE_82599_VMDQ_8Q_MASK:
4075 gpie |= IXGBE_GPIE_VTMODE_16;
4076 break;
4077 case IXGBE_82599_VMDQ_4Q_MASK:
4078 gpie |= IXGBE_GPIE_VTMODE_32;
4079 break;
4080 default:
4081 gpie |= IXGBE_GPIE_VTMODE_64;
4082 break;
4083 }
119fc60a
MC		 4084 }
4085
5fdd31f9 4086 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4087 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4088 switch (adapter->hw.mac.type) {
4089 case ixgbe_mac_82599EB:
4090 gpie |= IXGBE_SDP0_GPIEN;
4091 break;
4092 case ixgbe_mac_X540:
4093 gpie |= IXGBE_EIMS_TS;
4094 break;
4095 default:
4096 break;
4097 }
4098 }
5fdd31f9 4099
a34bcfff
AD		 4100 /* Enable fan failure interrupt */
4101 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4102 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4103
2698b208 4104 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4105 gpie |= IXGBE_SDP1_GPIEN;
4106 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4107 }
a34bcfff
AD		 4108
4109 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4110}
4111
c7ccde0f 4112static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4113{
4114 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4115 int err;
a34bcfff
AD		 4116 u32 ctrl_ext;
4117
4118 ixgbe_get_hw_control(adapter);
4119 ixgbe_setup_gpie(adapter);
e8e26350 4120
9a799d71
AK		 4121 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4122 ixgbe_configure_msix(adapter);
4123 else
4124 ixgbe_configure_msi_and_legacy(adapter);
4125
ec74a471
ET		 4126 /* enable the optics for 82599 SFP+ fiber */
4127 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4128 hw->mac.ops.enable_tx_laser(hw);
4129
9a799d71 4130 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4131 ixgbe_napi_enable_all(adapter);
4132
73c4b7cd
AD		 4133 if (ixgbe_is_sfp(hw)) {
4134 ixgbe_sfp_link_config(adapter);
4135 } else {
4136 err = ixgbe_non_sfp_link_config(hw);
4137 if (err)
4138 e_err(probe, "link_config FAILED %d\n", err);
4139 }
4140
021230d4
AV		 4141 /* clear any pending interrupts, may auto mask */
4142 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4143 ixgbe_irq_enable(adapter, true, true);
9a799d71 4144
bf069c97
DS		 4145 /*
4146 * If this adapter has a fan, check to see if we had a failure
4147 * before we enabled the interrupt.
4148 */
4149 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4150 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4151 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4152 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4153 }
4154
1da100bb 4155 /* enable transmits */
477de6ed 4156 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4157
9a799d71
AK		 4158 /* bring the link up in the watchdog, this could race with our first
4159 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4160 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4161 adapter->link_check_timeout = jiffies;
7086400d 4162 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4163
4164 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4165 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4166 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4167 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4168}
4169
d4f80882
AV		 4170void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4171{
4172 WARN_ON(in_interrupt());
7086400d
AD		 4173 /* put off any impending NetWatchDogTimeout */
4174 adapter->netdev->trans_start = jiffies;
4175
d4f80882 4176 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4177 usleep_range(1000, 2000);
d4f80882 4178 ixgbe_down(adapter);
5809a1ae
GR		 4179 /*
4180 * If SR-IOV enabled then wait a bit before bringing the adapter
4181 * back up to give the VFs time to respond to the reset. The
4182 * two second wait is based upon the watchdog timer cycle in
4183 * the VF driver.
4184 */
4185 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4186 msleep(2000);
d4f80882
AV		 4187 ixgbe_up(adapter);
4188 clear_bit(__IXGBE_RESETTING, &adapter->state);
4189}
4190
c7ccde0f 4191void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4192{
4193 /* hardware has been reset, we need to reload some things */
4194 ixgbe_configure(adapter);
4195
c7ccde0f 4196 ixgbe_up_complete(adapter);
9a799d71
AK		 4197}
4198
4199void ixgbe_reset(struct ixgbe_adapter *adapter)
4200{
c44ade9e 4201 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4202 int err;
4203
7086400d
AD		 4204 /* lock SFP init bit to prevent race conditions with the watchdog */
4205 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4206 usleep_range(1000, 2000);
4207
4208 /* clear all SFP and link config related flags while holding SFP_INIT */
4209 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4210 IXGBE_FLAG2_SFP_NEEDS_RESET);
4211 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4212
8ca783ab 4213 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4214 switch (err) {
4215 case 0:
4216 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4217 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4218 break;
4219 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4220 e_dev_err("master disable timed out\n");
da4dd0f7 4221 break;
794caeb2
PWJ		 4222 case IXGBE_ERR_EEPROM_VERSION:
4223 /* We are running on a pre-production device, log a warning */
849c4542 4224 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4225 "Please be aware there may be issues associated with "
849c4542
ET		 4226 "your hardware. If you are experiencing problems "
4227 "please contact your Intel or hardware "
4228 "representative who provided you with this "
4229 "hardware.\n");
794caeb2 4230 break;
da4dd0f7 4231 default:
849c4542 4232 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4233 }
9a799d71 4234
7086400d
AD		 4235 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4236
9a799d71 4237 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4238 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4239
4240 /* update SAN MAC vmdq pool selection */
4241 if (hw->mac.san_mac_rar_index)
4242 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4243
1a71ab24
JK		 4244 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4245 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4246}
4247
9a799d71
AK		 4248/**
4249 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4250 * @rx_ring: ring to free buffers from
4251 **/
b6ec895e 4252static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4253{
b6ec895e 4254 struct device *dev = rx_ring->dev;
9a799d71 4255 unsigned long size;
b6ec895e 4256 u16 i;
9a799d71 4257
84418e3b
AD		 4258 /* ring already cleared, nothing to do */
4259 if (!rx_ring->rx_buffer_info)
4260 return;
9a799d71 4261
84418e3b 4262 /* Free all the Rx ring sk_buffs */
9a799d71 4263 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4264 struct ixgbe_rx_buffer *rx_buffer;
4265
4266 rx_buffer = &rx_ring->rx_buffer_info[i];
4267 if (rx_buffer->skb) {
4268 struct sk_buff *skb = rx_buffer->skb;
4269 if (IXGBE_CB(skb)->page_released) {
4270 dma_unmap_page(dev,
4271 IXGBE_CB(skb)->dma,
4272 ixgbe_rx_bufsz(rx_ring),
4273 DMA_FROM_DEVICE);
4274 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4275 }
4276 dev_kfree_skb(skb);
9a799d71 4277 }
f800326d
AD		 4278 rx_buffer->skb = NULL;
4279 if (rx_buffer->dma)
4280 dma_unmap_page(dev, rx_buffer->dma,
4281 ixgbe_rx_pg_size(rx_ring),
4282 DMA_FROM_DEVICE);
4283 rx_buffer->dma = 0;
4284 if (rx_buffer->page)
dd411ec4
AD		 4285 __free_pages(rx_buffer->page,
4286 ixgbe_rx_pg_order(rx_ring));
f800326d 4287 rx_buffer->page = NULL;
9a799d71
AK		 4288 }
4289
4290 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4291 memset(rx_ring->rx_buffer_info, 0, size);
4292
4293 /* Zero out the descriptor ring */
4294 memset(rx_ring->desc, 0, rx_ring->size);
4295
f800326d 4296 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4297 rx_ring->next_to_clean = 0;
4298 rx_ring->next_to_use = 0;
9a799d71
AK		 4299}
4300
4301/**
4302 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4303 * @tx_ring: ring to be cleaned
4304 **/
b6ec895e 4305static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4306{
4307 struct ixgbe_tx_buffer *tx_buffer_info;
4308 unsigned long size;
b6ec895e 4309 u16 i;
9a799d71 4310
84418e3b
AD		 4311 /* ring already cleared, nothing to do */
4312 if (!tx_ring->tx_buffer_info)
4313 return;
9a799d71 4314
84418e3b 4315 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4316 for (i = 0; i < tx_ring->count; i++) {
4317 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4318 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4319 }
4320
dad8a3b3
JF		 4321 netdev_tx_reset_queue(txring_txq(tx_ring));
4322
9a799d71
AK		 4323 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4324 memset(tx_ring->tx_buffer_info, 0, size);
4325
4326 /* Zero out the descriptor ring */
4327 memset(tx_ring->desc, 0, tx_ring->size);
4328
4329 tx_ring->next_to_use = 0;
4330 tx_ring->next_to_clean = 0;
9a799d71
AK		 4331}
4332
4333/**
021230d4 4334 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4335 * @adapter: board private structure
4336 **/
021230d4 4337static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4338{
4339 int i;
4340
021230d4 4341 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4342 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4343}
4344
4345/**
021230d4 4346 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4347 * @adapter: board private structure
4348 **/
021230d4 4349static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4350{
4351 int i;
4352
021230d4 4353 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4354 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4355}
4356
e4911d57
AD		 4357static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4358{
4359 struct hlist_node *node, *node2;
4360 struct ixgbe_fdir_filter *filter;
4361
4362 spin_lock(&adapter->fdir_perfect_lock);
4363
4364 hlist_for_each_entry_safe(filter, node, node2,
4365 &adapter->fdir_filter_list, fdir_node) {
4366 hlist_del(&filter->fdir_node);
4367 kfree(filter);
4368 }
4369 adapter->fdir_filter_count = 0;
4370
4371 spin_unlock(&adapter->fdir_perfect_lock);
4372}
4373
9a799d71
AK		 4374void ixgbe_down(struct ixgbe_adapter *adapter)
4375{
4376 struct net_device *netdev = adapter->netdev;
7f821875 4377 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4378 u32 rxctrl;
bf29ee6c 4379 int i;
9a799d71
AK		 4380
4381 /* signal that we are down to the interrupt handler */
4382 set_bit(__IXGBE_DOWN, &adapter->state);
4383
4384 /* disable receives */
7f821875
JB		 4385 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4386 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4387
2d39d576
YZ		 4388 /* disable all enabled rx queues */
4389 for (i = 0; i < adapter->num_rx_queues; i++)
4390 /* this call also flushes the previous write */
4391 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4392
032b4325 4393 usleep_range(10000, 20000);
9a799d71 4394
7f821875
JB		 4395 netif_tx_stop_all_queues(netdev);
4396
7086400d 4397 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4398 netif_carrier_off(netdev);
4399 netif_tx_disable(netdev);
4400
4401 ixgbe_irq_disable(adapter);
4402
4403 ixgbe_napi_disable_all(adapter);
4404
d034acf1
AD		 4405 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4406 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4407 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4408
4409 del_timer_sync(&adapter->service_timer);
4410
34cecbbf 4411 if (adapter->num_vfs) {
8e34d1aa
AD		 4412 /* Clear EITR Select mapping */
4413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4414
4415 /* Mark all the VFs as inactive */
4416 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4417 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4418
34cecbbf
AD		 4419 /* ping all the active vfs to let them know we are going down */
4420 ixgbe_ping_all_vfs(adapter);
4421
4422 /* Disable all VFTE/VFRE TX/RX */
4423 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4424 }
4425
7f821875
JB		 4426 /* disable transmits in the hardware now that interrupts are off */
4427 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4428 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4429 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4430 }
34cecbbf
AD		 4431
4432 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4433 switch (hw->mac.type) {
4434 case ixgbe_mac_82599EB:
b93a2226 4435 case ixgbe_mac_X540:
88512539 4436 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4437 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4438 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4439 break;
4440 default:
4441 break;
4442 }
7f821875 4443
6f4a0e45
PL		 4444 if (!pci_channel_offline(adapter->pdev))
4445 ixgbe_reset(adapter);
c6ecf39a 4446
ec74a471
ET		 4447 /* power down the optics for 82599 SFP+ fiber */
4448 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4449 hw->mac.ops.disable_tx_laser(hw);
4450
9a799d71
AK		 4451 ixgbe_clean_all_tx_rings(adapter);
4452 ixgbe_clean_all_rx_rings(adapter);
4453
5dd2d332 4454#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4455 /* since we reset the hardware DCA settings were cleared */
e35ec126 4456 ixgbe_setup_dca(adapter);
96b0e0f6 4457#endif
9a799d71
AK		 4458}
4459
9a799d71
AK		 4460/**
4461 * ixgbe_tx_timeout - Respond to a Tx Hang
4462 * @netdev: network interface device structure
4463 **/
4464static void ixgbe_tx_timeout(struct net_device *netdev)
4465{
4466 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4467
4468 /* Do the reset outside of interrupt context */
c83c6cbd 4469 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4470}
4471
9a799d71
AK		 4472/**
4473 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4474 * @adapter: board private structure to initialize
4475 *
4476 * ixgbe_sw_init initializes the Adapter private data structure.
4477 * Fields are initialized based on PCI device information and
4478 * OS network device settings (MTU size).
4479 **/
4480static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4481{
4482 struct ixgbe_hw *hw = &adapter->hw;
4483 struct pci_dev *pdev = adapter->pdev;
021230d4 4484 unsigned int rss;
7a6b6f51 4485#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4486 int j;
4487 struct tc_configuration *tc;
4488#endif
021230d4 4489
c44ade9e
JB		 4490 /* PCI config space info */
4491
4492 hw->vendor_id = pdev->vendor;
4493 hw->device_id = pdev->device;
4494 hw->revision_id = pdev->revision;
4495 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4496 hw->subsystem_device_id = pdev->subsystem_device;
4497
021230d4 4498 /* Set capability flags */
3ed69d7e 4499 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4500 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4501 switch (hw->mac.type) {
4502 case ixgbe_mac_82598EB:
bf069c97
DS		 4503 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4504 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4505 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4506 break;
b93a2226 4507 case ixgbe_mac_X540:
4f51bf70
JK		 4508 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4509 case ixgbe_mac_82599EB:
49c7ffbe 4510 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4511 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4512 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4513 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4514 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4515 /* Flow Director hash filters enabled */
45b9f509 4516 adapter->atr_sample_rate = 20;
c087663e 4517 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4518 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4519 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4520#ifdef IXGBE_FCOE
0d551589
YZ		 4521 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4522 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4523#ifdef CONFIG_IXGBE_DCB
6ee16520 4524 /* Default traffic class to use for FCoE */
56075a98 4525 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4526#endif
eacd73f7 4527#endif /* IXGBE_FCOE */
bd508178
AD		 4528 break;
4529 default:
4530 break;
f8212f97 4531 }
2f90b865 4532
7c8ae65a
AD		 4533#ifdef IXGBE_FCOE
4534 /* FCoE support exists, always init the FCoE lock */
4535 spin_lock_init(&adapter->fcoe.lock);
4536
4537#endif
1fc5f038
AD		 4538 /* n-tuple support exists, always init our spinlock */
4539 spin_lock_init(&adapter->fdir_perfect_lock);
4540
7a6b6f51 4541#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4542 switch (hw->mac.type) {
4543 case ixgbe_mac_X540:
4544 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4545 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4546 break;
4547 default:
4548 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4549 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4550 break;
4551 }
4552
2f90b865
AD		 4553 /* Configure DCB traffic classes */
4554 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4555 tc = &adapter->dcb_cfg.tc_config[j];
4556 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4557 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4558 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4559 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4560 tc->dcb_pfc = pfc_disabled;
4561 }
4de2a022
JF		 4562
4563 /* Initialize default user to priority mapping, UPx->TC0 */
4564 tc = &adapter->dcb_cfg.tc_config[0];
4565 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4566 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4567
2f90b865
AD		 4568 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4569 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4570 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4571 adapter->dcb_set_bitmap = 0x00;
3032309b 4572 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4573 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4574 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4575
4576#endif
9a799d71
AK		 4577
4578 /* default flow control settings */
cd7664f6 4579 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4580 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4581 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4582 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4583 hw->fc.send_xon = true;
71fd570b 4584 hw->fc.disable_fc_autoneg = false;
9a799d71 4585
99d74487
AD		 4586#ifdef CONFIG_PCI_IOV
4587 /* assign number of SR-IOV VFs */
4588 if (hw->mac.type != ixgbe_mac_82598EB)
4589 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4590
4591#endif
30efa5a3 4592 /* enable itr by default in dynamic mode */
f7554a2b 4593 adapter->rx_itr_setting = 1;
f7554a2b 4594 adapter->tx_itr_setting = 1;
30efa5a3 4595
30efa5a3
JB		 4596 /* set default ring sizes */
4597 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4598 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4599
bd198058 4600 /* set default work limits */
59224555 4601 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4602
9a799d71 4603 /* initialize eeprom parameters */
c44ade9e 4604 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4605 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4606 return -EIO;
4607 }
4608
9a799d71
AK		 4609 set_bit(__IXGBE_DOWN, &adapter->state);
4610
4611 return 0;
4612}
4613
4614/**
4615 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4616 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4617 *
4618 * Return 0 on success, negative on failure
4619 **/
b6ec895e 4620int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4621{
b6ec895e 4622 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4623 int orig_node = dev_to_node(dev);
4624 int numa_node = -1;
9a799d71
AK		 4625 int size;
4626
3a581073 4627 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4628
4629 if (tx_ring->q_vector)
4630 numa_node = tx_ring->q_vector->numa_node;
4631
4632 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4633 if (!tx_ring->tx_buffer_info)
89bf67f1 4634 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4635 if (!tx_ring->tx_buffer_info)
4636 goto err;
9a799d71
AK		 4637
4638 /* round up to nearest 4K */
12207e49 4639 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4640 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4641
de88eeeb
AD		 4642 set_dev_node(dev, numa_node);
4643 tx_ring->desc = dma_alloc_coherent(dev,
4644 tx_ring->size,
4645 &tx_ring->dma,
4646 GFP_KERNEL);
4647 set_dev_node(dev, orig_node);
4648 if (!tx_ring->desc)
4649 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4650 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4651 if (!tx_ring->desc)
4652 goto err;
9a799d71 4653
3a581073
JB		 4654 tx_ring->next_to_use = 0;
4655 tx_ring->next_to_clean = 0;
9a799d71 4656 return 0;
e01c31a5
JB		 4657
4658err:
4659 vfree(tx_ring->tx_buffer_info);
4660 tx_ring->tx_buffer_info = NULL;
b6ec895e 4661 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4662 return -ENOMEM;
9a799d71
AK		 4663}
4664
69888674
AD		 4665/**
4666 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4667 * @adapter: board private structure
4668 *
4669 * If this function returns with an error, then it's possible one or
4670 * more of the rings is populated (while the rest are not). It is the
4671 * callers duty to clean those orphaned rings.
4672 *
4673 * Return 0 on success, negative on failure
4674 **/
4675static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4676{
4677 int i, err = 0;
4678
4679 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4680 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4681 if (!err)
4682 continue;
de3d5b94 4683
396e799c 4684 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4685 goto err_setup_tx;
69888674
AD		 4686 }
4687
de3d5b94
AD		 4688 return 0;
4689err_setup_tx:
4690 /* rewind the index freeing the rings as we go */
4691 while (i--)
4692 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4693 return err;
4694}
4695
9a799d71
AK		 4696/**
4697 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4698 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4699 *
4700 * Returns 0 on success, negative on failure
4701 **/
b6ec895e 4702int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4703{
b6ec895e 4704 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4705 int orig_node = dev_to_node(dev);
4706 int numa_node = -1;
021230d4 4707 int size;
9a799d71 4708
3a581073 4709 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4710
4711 if (rx_ring->q_vector)
4712 numa_node = rx_ring->q_vector->numa_node;
4713
4714 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4715 if (!rx_ring->rx_buffer_info)
89bf67f1 4716 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4717 if (!rx_ring->rx_buffer_info)
4718 goto err;
9a799d71 4719
9a799d71 4720 /* Round up to nearest 4K */
3a581073
JB		 4721 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4722 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4723
de88eeeb
AD		 4724 set_dev_node(dev, numa_node);
4725 rx_ring->desc = dma_alloc_coherent(dev,
4726 rx_ring->size,
4727 &rx_ring->dma,
4728 GFP_KERNEL);
4729 set_dev_node(dev, orig_node);
4730 if (!rx_ring->desc)
4731 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4732 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4733 if (!rx_ring->desc)
4734 goto err;
9a799d71 4735
3a581073
JB		 4736 rx_ring->next_to_clean = 0;
4737 rx_ring->next_to_use = 0;
9a799d71
AK		 4738
4739 return 0;
b6ec895e
AD		 4740err:
4741 vfree(rx_ring->rx_buffer_info);
4742 rx_ring->rx_buffer_info = NULL;
4743 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4744 return -ENOMEM;
9a799d71
AK		 4745}
4746
69888674
AD		 4747/**
4748 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4749 * @adapter: board private structure
4750 *
4751 * If this function returns with an error, then it's possible one or
4752 * more of the rings is populated (while the rest are not). It is the
4753 * callers duty to clean those orphaned rings.
4754 *
4755 * Return 0 on success, negative on failure
4756 **/
69888674
AD		 4757static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4758{
4759 int i, err = 0;
4760
4761 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4762 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4763 if (!err)
4764 continue;
de3d5b94 4765
396e799c 4766 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4767 goto err_setup_rx;
69888674
AD		 4768 }
4769
7c8ae65a
AD		 4770#ifdef IXGBE_FCOE
4771 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4772 if (!err)
4773#endif
4774 return 0;
de3d5b94
AD		 4775err_setup_rx:
4776 /* rewind the index freeing the rings as we go */
4777 while (i--)
4778 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4779 return err;
4780}
4781
9a799d71
AK		 4782/**
4783 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4784 * @tx_ring: Tx descriptor ring for a specific queue
4785 *
4786 * Free all transmit software resources
4787 **/
b6ec895e 4788void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4789{
b6ec895e 4790 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4791
4792 vfree(tx_ring->tx_buffer_info);
4793 tx_ring->tx_buffer_info = NULL;
4794
b6ec895e
AD		 4795 /* if not set, then don't free */
4796 if (!tx_ring->desc)
4797 return;
4798
4799 dma_free_coherent(tx_ring->dev, tx_ring->size,
4800 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4801
4802 tx_ring->desc = NULL;
4803}
4804
4805/**
4806 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4807 * @adapter: board private structure
4808 *
4809 * Free all transmit software resources
4810 **/
4811static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4812{
4813 int i;
4814
4815 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4816 if (adapter->tx_ring[i]->desc)
b6ec895e 4817 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4818}
4819
4820/**
b4617240 4821 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4822 * @rx_ring: ring to clean the resources from
4823 *
4824 * Free all receive software resources
4825 **/
b6ec895e 4826void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4827{
b6ec895e 4828 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4829
4830 vfree(rx_ring->rx_buffer_info);
4831 rx_ring->rx_buffer_info = NULL;
4832
b6ec895e
AD		 4833 /* if not set, then don't free */
4834 if (!rx_ring->desc)
4835 return;
4836
4837 dma_free_coherent(rx_ring->dev, rx_ring->size,
4838 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4839
4840 rx_ring->desc = NULL;
4841}
4842
4843/**
4844 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4845 * @adapter: board private structure
4846 *
4847 * Free all receive software resources
4848 **/
4849static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4850{
4851 int i;
4852
7c8ae65a
AD		 4853#ifdef IXGBE_FCOE
4854 ixgbe_free_fcoe_ddp_resources(adapter);
4855
4856#endif
9a799d71 4857 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4858 if (adapter->rx_ring[i]->desc)
b6ec895e 4859 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4860}
4861
9a799d71
AK		 4862/**
4863 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4864 * @netdev: network interface device structure
4865 * @new_mtu: new value for maximum frame size
4866 *
4867 * Returns 0 on success, negative on failure
4868 **/
4869static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4870{
4871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4872 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4873
42c783c5 4874 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4875 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4876 return -EINVAL;
4877
4878 /*
872844dd
AD		 4879 * For 82599EB we cannot allow legacy VFs to enable their receive
4880 * paths when MTU greater than 1500 is configured. So display a
4881 * warning that legacy VFs will be disabled.
655309e9
AD		 4882 */
4883 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4884 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4885 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
872844dd 4886 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 4887
396e799c 4888 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4889
021230d4 4890 /* must set new MTU before calling down or up */
9a799d71
AK		 4891 netdev->mtu = new_mtu;
4892
d4f80882
AV		 4893 if (netif_running(netdev))
4894 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4895
4896 return 0;
4897}
4898
4899/**
4900 * ixgbe_open - Called when a network interface is made active
4901 * @netdev: network interface device structure
4902 *
4903 * Returns 0 on success, negative value on failure
4904 *
4905 * The open entry point is called when a network interface is made
4906 * active by the system (IFF_UP). At this point all resources needed
4907 * for transmit and receive operations are allocated, the interrupt
4908 * handler is registered with the OS, the watchdog timer is started,
4909 * and the stack is notified that the interface is ready.
4910 **/
4911static int ixgbe_open(struct net_device *netdev)
4912{
4913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4914 int err;
4bebfaa5
AK		 4915
4916 /* disallow open during test */
4917 if (test_bit(__IXGBE_TESTING, &adapter->state))
4918 return -EBUSY;
9a799d71 4919
54386467
JB		 4920 netif_carrier_off(netdev);
4921
9a799d71
AK		 4922 /* allocate transmit descriptors */
4923 err = ixgbe_setup_all_tx_resources(adapter);
4924 if (err)
4925 goto err_setup_tx;
4926
9a799d71
AK		 4927 /* allocate receive descriptors */
4928 err = ixgbe_setup_all_rx_resources(adapter);
4929 if (err)
4930 goto err_setup_rx;
4931
4932 ixgbe_configure(adapter);
4933
021230d4 4934 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4935 if (err)
4936 goto err_req_irq;
4937
ac802f5d
AD		 4938 /* Notify the stack of the actual queue counts. */
4939 err = netif_set_real_num_tx_queues(netdev,
4940 adapter->num_rx_pools > 1 ? 1 :
4941 adapter->num_tx_queues);
4942 if (err)
4943 goto err_set_queues;
4944
4945
4946 err = netif_set_real_num_rx_queues(netdev,
4947 adapter->num_rx_pools > 1 ? 1 :
4948 adapter->num_rx_queues);
4949 if (err)
4950 goto err_set_queues;
4951
1a71ab24 4952 ixgbe_ptp_init(adapter);
1a71ab24 4953
c7ccde0f 4954 ixgbe_up_complete(adapter);
9a799d71
AK		 4955
4956 return 0;
4957
ac802f5d
AD		 4958err_set_queues:
4959 ixgbe_free_irq(adapter);
9a799d71 4960err_req_irq:
a20a1199 4961 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4962err_setup_rx:
a20a1199 4963 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4964err_setup_tx:
9a799d71
AK		 4965 ixgbe_reset(adapter);
4966
4967 return err;
4968}
4969
4970/**
4971 * ixgbe_close - Disables a network interface
4972 * @netdev: network interface device structure
4973 *
4974 * Returns 0, this is not allowed to fail
4975 *
4976 * The close entry point is called when an interface is de-activated
4977 * by the OS. The hardware is still under the drivers control, but
4978 * needs to be disabled. A global MAC reset is issued to stop the
4979 * hardware, and all transmit and receive resources are freed.
4980 **/
4981static int ixgbe_close(struct net_device *netdev)
4982{
4983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 4984
1a71ab24 4985 ixgbe_ptp_stop(adapter);
1a71ab24 4986
9a799d71
AK		 4987 ixgbe_down(adapter);
4988 ixgbe_free_irq(adapter);
4989
e4911d57
AD		 4990 ixgbe_fdir_filter_exit(adapter);
4991
9a799d71
AK		 4992 ixgbe_free_all_tx_resources(adapter);
4993 ixgbe_free_all_rx_resources(adapter);
4994
5eba3699 4995 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4996
4997 return 0;
4998}
4999
b3c8b4ba
AD		 5000#ifdef CONFIG_PM
5001static int ixgbe_resume(struct pci_dev *pdev)
5002{
c60fbb00
AD		 5003 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5004 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5005 u32 err;
5006
5007 pci_set_power_state(pdev, PCI_D0);
5008 pci_restore_state(pdev);
656ab817
DS		 5009 /*
5010 * pci_restore_state clears dev->state_saved so call
5011 * pci_save_state to restore it.
5012 */
5013 pci_save_state(pdev);
9ce77666 5014
5015 err = pci_enable_device_mem(pdev);
b3c8b4ba 5016 if (err) {
849c4542 5017 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5018 return err;
5019 }
5020 pci_set_master(pdev);
5021
dd4d8ca6 5022 pci_wake_from_d3(pdev, false);
b3c8b4ba 5023
b3c8b4ba
AD		 5024 ixgbe_reset(adapter);
5025
495dce12
WJP		 5026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5027
ac802f5d
AD		 5028 rtnl_lock();
5029 err = ixgbe_init_interrupt_scheme(adapter);
5030 if (!err && netif_running(netdev))
c60fbb00 5031 err = ixgbe_open(netdev);
ac802f5d
AD		 5032
5033 rtnl_unlock();
5034
5035 if (err)
5036 return err;
b3c8b4ba
AD		 5037
5038 netif_device_attach(netdev);
5039
5040 return 0;
5041}
b3c8b4ba 5042#endif /* CONFIG_PM */
9d8d05ae
RW		 5043
5044static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5045{
c60fbb00
AD		 5046 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5047 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5048 struct ixgbe_hw *hw = &adapter->hw;
5049 u32 ctrl, fctrl;
5050 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5051#ifdef CONFIG_PM
5052 int retval = 0;
5053#endif
5054
5055 netif_device_detach(netdev);
5056
5057 if (netif_running(netdev)) {
ab6039a7 5058 rtnl_lock();
b3c8b4ba
AD		 5059 ixgbe_down(adapter);
5060 ixgbe_free_irq(adapter);
5061 ixgbe_free_all_tx_resources(adapter);
5062 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5063 rtnl_unlock();
b3c8b4ba 5064 }
b3c8b4ba 5065
5f5ae6fc
AD		 5066 ixgbe_clear_interrupt_scheme(adapter);
5067
b3c8b4ba
AD		 5068#ifdef CONFIG_PM
5069 retval = pci_save_state(pdev);
5070 if (retval)
5071 return retval;
4df10466 5072
b3c8b4ba 5073#endif
e8e26350
PW		 5074 if (wufc) {
5075 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5076
ec74a471
ET		 5077 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5078 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5079 hw->mac.ops.enable_tx_laser(hw);
5080
e8e26350
PW		 5081 /* turn on all-multi mode if wake on multicast is enabled */
5082 if (wufc & IXGBE_WUFC_MC) {
5083 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5084 fctrl |= IXGBE_FCTRL_MPE;
5085 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5086 }
5087
5088 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5089 ctrl |= IXGBE_CTRL_GIO_DIS;
5090 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5091
5092 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5093 } else {
5094 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5095 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5096 }
5097
bd508178
AD		 5098 switch (hw->mac.type) {
5099 case ixgbe_mac_82598EB:
dd4d8ca6 5100 pci_wake_from_d3(pdev, false);
bd508178
AD		 5101 break;
5102 case ixgbe_mac_82599EB:
b93a2226 5103 case ixgbe_mac_X540:
bd508178
AD		 5104 pci_wake_from_d3(pdev, !!wufc);
5105 break;
5106 default:
5107 break;
5108 }
b3c8b4ba 5109
9d8d05ae
RW		 5110 *enable_wake = !!wufc;
5111
b3c8b4ba
AD		 5112 ixgbe_release_hw_control(adapter);
5113
5114 pci_disable_device(pdev);
5115
9d8d05ae
RW		 5116 return 0;
5117}
5118
5119#ifdef CONFIG_PM
5120static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5121{
5122 int retval;
5123 bool wake;
5124
5125 retval = __ixgbe_shutdown(pdev, &wake);
5126 if (retval)
5127 return retval;
5128
5129 if (wake) {
5130 pci_prepare_to_sleep(pdev);
5131 } else {
5132 pci_wake_from_d3(pdev, false);
5133 pci_set_power_state(pdev, PCI_D3hot);
5134 }
b3c8b4ba
AD		 5135
5136 return 0;
5137}
9d8d05ae 5138#endif /* CONFIG_PM */
b3c8b4ba
AD		 5139
5140static void ixgbe_shutdown(struct pci_dev *pdev)
5141{
9d8d05ae
RW		 5142 bool wake;
5143
5144 __ixgbe_shutdown(pdev, &wake);
5145
5146 if (system_state == SYSTEM_POWER_OFF) {
5147 pci_wake_from_d3(pdev, wake);
5148 pci_set_power_state(pdev, PCI_D3hot);
5149 }
b3c8b4ba
AD		 5150}
5151
9a799d71
AK		 5152/**
5153 * ixgbe_update_stats - Update the board statistics counters.
5154 * @adapter: board private structure
5155 **/
5156void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5157{
2d86f139 5158 struct net_device *netdev = adapter->netdev;
9a799d71 5159 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5160 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5161 u64 total_mpc = 0;
5162 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5163 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5164 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5165 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5166
d08935c2
DS		 5167 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5168 test_bit(__IXGBE_RESETTING, &adapter->state))
5169 return;
5170
94b982b2 5171 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5172 u64 rsc_count = 0;
94b982b2 5173 u64 rsc_flush = 0;
94b982b2 5174 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5175 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5176 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5177 }
5178 adapter->rsc_total_count = rsc_count;
5179 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5180 }
5181
5b7da515
AD		 5182 for (i = 0; i < adapter->num_rx_queues; i++) {
5183 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5184 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5185 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5186 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5187 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5188 bytes += rx_ring->stats.bytes;
5189 packets += rx_ring->stats.packets;
5190 }
5191 adapter->non_eop_descs = non_eop_descs;
5192 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5193 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5194 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5195 netdev->stats.rx_bytes = bytes;
5196 netdev->stats.rx_packets = packets;
5197
5198 bytes = 0;
5199 packets = 0;
7ca3bc58 5200 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5201 for (i = 0; i < adapter->num_tx_queues; i++) {
5202 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5203 restart_queue += tx_ring->tx_stats.restart_queue;
5204 tx_busy += tx_ring->tx_stats.tx_busy;
5205 bytes += tx_ring->stats.bytes;
5206 packets += tx_ring->stats.packets;
5207 }
eb985f09 5208 adapter->restart_queue = restart_queue;
5b7da515
AD		 5209 adapter->tx_busy = tx_busy;
5210 netdev->stats.tx_bytes = bytes;
5211 netdev->stats.tx_packets = packets;
7ca3bc58 5212
7ca647bd 5213 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5214
5215 /* 8 register reads */
6f11eef7
AV		 5216 for (i = 0; i < 8; i++) {
5217 /* for packet buffers not used, the register should read 0 */
5218 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5219 missed_rx += mpc;
7ca647bd
JP		 5220 hwstats->mpc[i] += mpc;
5221 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5222 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5223 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5224 switch (hw->mac.type) {
5225 case ixgbe_mac_82598EB:
1a70db4b
ET		 5226 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5227 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5228 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5229 hwstats->pxonrxc[i] +=
5230 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5231 break;
5232 case ixgbe_mac_82599EB:
b93a2226 5233 case ixgbe_mac_X540:
bd508178
AD		 5234 hwstats->pxonrxc[i] +=
5235 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5236 break;
5237 default:
5238 break;
e8e26350 5239 }
6f11eef7 5240 }
1a70db4b
ET		 5241
5242 /*16 register reads */
5243 for (i = 0; i < 16; i++) {
5244 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5245 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5246 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5247 (hw->mac.type == ixgbe_mac_X540)) {
5248 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5249 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5250 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5251 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5252 }
5253 }
5254
7ca647bd 5255 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5256 /* work around hardware counting issue */
7ca647bd 5257 hwstats->gprc -= missed_rx;
6f11eef7 5258
c84d324c
JF		 5259 ixgbe_update_xoff_received(adapter);
5260
6f11eef7 5261 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5262 switch (hw->mac.type) {
5263 case ixgbe_mac_82598EB:
5264 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5265 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5266 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5267 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5268 break;
b93a2226 5269 case ixgbe_mac_X540:
58f6bcf9
ET		 5270 /* OS2BMC stats are X540 only*/
5271 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5272 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5273 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5274 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5275 case ixgbe_mac_82599EB:
a4d4f629
AD		 5276 for (i = 0; i < 16; i++)
5277 adapter->hw_rx_no_dma_resources +=
5278 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5279 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5280 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5281 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5282 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5283 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5284 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5285 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5286 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5287 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5288#ifdef IXGBE_FCOE
7ca647bd
JP		 5289 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5290 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5291 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5292 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5293 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5294 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5295 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5296 if (adapter->fcoe.ddp_pool) {
5297 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5298 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5299 unsigned int cpu;
5300 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5301 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5302 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5303 noddp += ddp_pool->noddp;
5304 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5305 }
5a1ee270
AD		 5306 hwstats->fcoe_noddp = noddp;
5307 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5308 }
6d45522c 5309#endif /* IXGBE_FCOE */
bd508178
AD		 5310 break;
5311 default:
5312 break;
e8e26350 5313 }
9a799d71 5314 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5315 hwstats->bprc += bprc;
5316 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5317 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5318 hwstats->mprc -= bprc;
5319 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5320 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5321 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5322 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5323 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5324 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5325 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5326 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5327 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5328 hwstats->lxontxc += lxon;
6f11eef7 5329 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5330 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5331 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5332 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5333 /*
5334 * 82598 errata - tx of flow control packets is included in tx counters
5335 */
5336 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5337 hwstats->gptc -= xon_off_tot;
5338 hwstats->mptc -= xon_off_tot;
5339 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5340 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5341 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5342 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5343 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5344 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5345 hwstats->ptc64 -= xon_off_tot;
5346 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5347 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5348 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5349 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5350 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5351 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5352
5353 /* Fill out the OS statistics structure */
7ca647bd 5354 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5355
5356 /* Rx Errors */
7ca647bd 5357 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5358 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5359 netdev->stats.rx_length_errors = hwstats->rlec;
5360 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5361 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5362}
5363
5364/**
d034acf1 5365 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5366 * @adapter: pointer to the device adapter structure
9a799d71 5367 **/
d034acf1 5368static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5369{
cf8280ee 5370 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5371 int i;
cf8280ee 5372
d034acf1
AD		 5373 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5374 return;
5375
5376 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5377
d034acf1 5378 /* if interface is down do nothing */
fe49f04a 5379 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5380 return;
5381
5382 /* do nothing if we are not using signature filters */
5383 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5384 return;
5385
5386 adapter->fdir_overflow++;
5387
93c52dd0
AD		 5388 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5389 for (i = 0; i < adapter->num_tx_queues; i++)
5390 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5391 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5392 /* re-enable flow director interrupts */
5393 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5394 } else {
5395 e_err(probe, "failed to finish FDIR re-initialization, "
5396 "ignored adding FDIR ATR filters\n");
5397 }
93c52dd0
AD		 5398}
5399
5400/**
5401 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5402 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5403 *
5404 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5405 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5406 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5407 * determine if a hang has occurred.
93c52dd0
AD		 5408 */
5409static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5410{
cf8280ee 5411 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5412 u64 eics = 0;
5413 int i;
cf8280ee 5414
93c52dd0
AD		 5415 /* If we're down or resetting, just bail */
5416 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5417 test_bit(__IXGBE_RESETTING, &adapter->state))
5418 return;
22d5a71b 5419
93c52dd0
AD		 5420 /* Force detection of hung controller */
5421 if (netif_carrier_ok(adapter->netdev)) {
5422 for (i = 0; i < adapter->num_tx_queues; i++)
5423 set_check_for_tx_hang(adapter->tx_ring[i]);
5424 }
22d5a71b 5425
fe49f04a
AD		 5426 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5427 /*
5428 * for legacy and MSI interrupts don't set any bits
5429 * that are enabled for EIAM, because this operation
5430 * would set *both* EIMS and EICS for any bit in EIAM
5431 */
5432 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5433 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5434 } else {
5435 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5436 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5437 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5438 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5439 eics |= ((u64)1 << i);
5440 }
cf8280ee 5441 }
9a799d71 5442
93c52dd0 5443 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5444 ixgbe_irq_rearm_queues(adapter, eics);
5445
cf8280ee
JB		 5446}
5447
e8e26350 5448/**
93c52dd0 5449 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5450 * @adapter: pointer to the device adapter structure
5451 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5452 **/
93c52dd0 5453static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5454{
e8e26350 5455 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5456 u32 link_speed = adapter->link_speed;
5457 bool link_up = adapter->link_up;
041441d0 5458 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5459
93c52dd0
AD		 5460 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5461 return;
5462
5463 if (hw->mac.ops.check_link) {
5464 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5465 } else {
93c52dd0
AD		 5466 /* always assume link is up, if no check link function */
5467 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5468 link_up = true;
c4cf55e5 5469 }
041441d0
AD		 5470
5471 if (adapter->ixgbe_ieee_pfc)
5472 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5473
3ebe8fde 5474 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5475 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5476 ixgbe_set_rx_drop_en(adapter);
5477 }
93c52dd0
AD		 5478
5479 if (link_up ||
5480 time_after(jiffies, (adapter->link_check_timeout +
5481 IXGBE_TRY_LINK_TIMEOUT))) {
5482 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5483 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5484 IXGBE_WRITE_FLUSH(hw);
5485 }
5486
5487 adapter->link_up = link_up;
5488 adapter->link_speed = link_speed;
e8e26350
PW		 5489}
5490
107d3018
AD		 5491static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5492{
5493#ifdef CONFIG_IXGBE_DCB
5494 struct net_device *netdev = adapter->netdev;
5495 struct dcb_app app = {
5496 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5497 .protocol = 0,
5498 };
5499 u8 up = 0;
5500
5501 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5502 up = dcb_ieee_getapp_mask(netdev, &app);
5503
5504 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5505#endif
5506}
5507
e8e26350 5508/**
93c52dd0
AD		 5509 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5510 * print link up message
49ce9c2c 5511 * @adapter: pointer to the device adapter structure
e8e26350 5512 **/
93c52dd0 5513static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5514{
93c52dd0 5515 struct net_device *netdev = adapter->netdev;
e8e26350 5516 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5517 u32 link_speed = adapter->link_speed;
5518 bool flow_rx, flow_tx;
e8e26350 5519
93c52dd0
AD		 5520 /* only continue if link was previously down */
5521 if (netif_carrier_ok(netdev))
a985b6c3 5522 return;
63d6e1d8 5523
93c52dd0 5524 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5525
93c52dd0
AD		 5526 switch (hw->mac.type) {
5527 case ixgbe_mac_82598EB: {
5528 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5529 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5530 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5531 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5532 }
5533 break;
5534 case ixgbe_mac_X540:
5535 case ixgbe_mac_82599EB: {
5536 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5537 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5538 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5539 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5540 }
5541 break;
5542 default:
5543 flow_tx = false;
5544 flow_rx = false;
5545 break;
e8e26350 5546 }
3a6a4eda 5547
1a71ab24
JK		 5548 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5549 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5550
93c52dd0
AD		 5551 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5552 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5553 "10 Gbps" :
5554 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5555 "1 Gbps" :
5556 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5557 "100 Mbps" :
5558 "unknown speed"))),
5559 ((flow_rx && flow_tx) ? "RX/TX" :
5560 (flow_rx ? "RX" :
5561 (flow_tx ? "TX" : "None"))));
e8e26350 5562
93c52dd0 5563 netif_carrier_on(netdev);
93c52dd0 5564 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5565
107d3018
AD		 5566 /* update the default user priority for VFs */
5567 ixgbe_update_default_up(adapter);
5568
befa2af7
AD		 5569 /* ping all the active vfs to let them know link has changed */
5570 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5571}
5572
c4cf55e5 5573/**
93c52dd0
AD		 5574 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5575 * print link down message
49ce9c2c 5576 * @adapter: pointer to the adapter structure
c4cf55e5 5577 **/
581330ba 5578static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5579{
cf8280ee 5580 struct net_device *netdev = adapter->netdev;
c4cf55e5 5581 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5582
93c52dd0
AD		 5583 adapter->link_up = false;
5584 adapter->link_speed = 0;
cf8280ee 5585
93c52dd0
AD		 5586 /* only continue if link was up previously */
5587 if (!netif_carrier_ok(netdev))
5588 return;
264857b8 5589
93c52dd0
AD		 5590 /* poll for SFP+ cable when link is down */
5591 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5592 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5593
1a71ab24
JK		 5594 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5595 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5596
93c52dd0
AD		 5597 e_info(drv, "NIC Link is Down\n");
5598 netif_carrier_off(netdev);
befa2af7
AD		 5599
5600 /* ping all the active vfs to let them know link has changed */
5601 ixgbe_ping_all_vfs(adapter);
93c52dd0 5602}
e8e26350 5603
93c52dd0
AD		 5604/**
5605 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5606 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5607 **/
5608static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5609{
c4cf55e5 5610 int i;
93c52dd0 5611 int some_tx_pending = 0;
c4cf55e5 5612
93c52dd0 5613 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5614 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5615 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5616 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5617 some_tx_pending = 1;
5618 break;
5619 }
5620 }
5621
5622 if (some_tx_pending) {
5623 /* We've lost link, so the controller stops DMA,
5624 * but we've got queued Tx work that's never going
5625 * to get done, so reset controller to flush Tx.
5626 * (Do the reset outside of interrupt context).
5627 */
c83c6cbd 5628 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5629 }
c4cf55e5 5630 }
c4cf55e5
PWJ		 5631}
5632
a985b6c3
GR		 5633static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5634{
5635 u32 ssvpc;
5636
0584d999
GR		 5637 /* Do not perform spoof check for 82598 or if not in IOV mode */
5638 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5639 adapter->num_vfs == 0)
a985b6c3
GR		 5640 return;
5641
5642 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5643
5644 /*
5645 * ssvpc register is cleared on read, if zero then no
5646 * spoofed packets in the last interval.
5647 */
5648 if (!ssvpc)
5649 return;
5650
d6ea0754 5651 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5652}
5653
93c52dd0
AD		 5654/**
5655 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5656 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5657 **/
5658static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5659{
5660 /* if interface is down do nothing */
7edebf9a
ET		 5661 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5662 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5663 return;
5664
5665 ixgbe_watchdog_update_link(adapter);
5666
5667 if (adapter->link_up)
5668 ixgbe_watchdog_link_is_up(adapter);
5669 else
5670 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5671
a985b6c3 5672 ixgbe_spoof_check(adapter);
9a799d71 5673 ixgbe_update_stats(adapter);
93c52dd0
AD		 5674
5675 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5676}
10eec955 5677
cf8280ee 5678/**
7086400d 5679 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5680 * @adapter: the ixgbe adapter structure
cf8280ee 5681 **/
7086400d 5682static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5683{
cf8280ee 5684 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5685 s32 err;
cf8280ee 5686
7086400d
AD		 5687 /* not searching for SFP so there is nothing to do here */
5688 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5689 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5690 return;
10eec955 5691
7086400d
AD		 5692 /* someone else is in init, wait until next service event */
5693 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5694 return;
cf8280ee 5695
7086400d
AD		 5696 err = hw->phy.ops.identify_sfp(hw);
5697 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5698 goto sfp_out;
264857b8 5699
7086400d
AD		 5700 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5701 /* If no cable is present, then we need to reset
5702 * the next time we find a good cable. */
5703 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5704 }
9a799d71 5705
7086400d
AD		 5706 /* exit on error */
5707 if (err)
5708 goto sfp_out;
e8e26350 5709
7086400d
AD		 5710 /* exit if reset not needed */
5711 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5712 goto sfp_out;
9a799d71 5713
7086400d 5714 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5715
7086400d
AD		 5716 /*
5717 * A module may be identified correctly, but the EEPROM may not have
5718 * support for that module. setup_sfp() will fail in that case, so
5719 * we should not allow that module to load.
5720 */
5721 if (hw->mac.type == ixgbe_mac_82598EB)
5722 err = hw->phy.ops.reset(hw);
5723 else
5724 err = hw->mac.ops.setup_sfp(hw);
5725
5726 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5727 goto sfp_out;
5728
5729 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5730 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5731
5732sfp_out:
5733 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5734
5735 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5736 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5737 e_dev_err("failed to initialize because an unsupported "
5738 "SFP+ module type was detected.\n");
5739 e_dev_err("Reload the driver after installing a "
5740 "supported module.\n");
5741 unregister_netdev(adapter->netdev);
bc59fcda 5742 }
7086400d 5743}
bc59fcda 5744
7086400d
AD		 5745/**
5746 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5747 * @adapter: the ixgbe adapter structure
7086400d
AD		 5748 **/
5749static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5750{
5751 struct ixgbe_hw *hw = &adapter->hw;
5752 u32 autoneg;
5753 bool negotiation;
5754
5755 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5756 return;
5757
5758 /* someone else is in init, wait until next service event */
5759 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5760 return;
5761
5762 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5763
5764 autoneg = hw->phy.autoneg_advertised;
5765 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5766 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5767 if (hw->mac.ops.setup_link)
5768 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5769
5770 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5771 adapter->link_check_timeout = jiffies;
5772 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5773}
5774
83c61fa9
GR		 5775#ifdef CONFIG_PCI_IOV
5776static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5777{
5778 int vf;
5779 struct ixgbe_hw *hw = &adapter->hw;
5780 struct net_device *netdev = adapter->netdev;
5781 u32 gpc;
5782 u32 ciaa, ciad;
5783
5784 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5785 if (gpc) /* If incrementing then no need for the check below */
5786 return;
5787 /*
5788 * Check to see if a bad DMA write target from an errant or
5789 * malicious VF has caused a PCIe error. If so then we can
5790 * issue a VFLR to the offending VF(s) and then resume without
5791 * requesting a full slot reset.
5792 */
5793
5794 for (vf = 0; vf < adapter->num_vfs; vf++) {
5795 ciaa = (vf << 16) | 0x80000000;
5796 /* 32 bit read so align, we really want status at offset 6 */
5797 ciaa |= PCI_COMMAND;
5798 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5799 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5800 ciaa &= 0x7FFFFFFF;
5801 /* disable debug mode asap after reading data */
5802 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5803 /* Get the upper 16 bits which will be the PCI status reg */
5804 ciad >>= 16;
5805 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5806 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5807 /* Issue VFLR */
5808 ciaa = (vf << 16) | 0x80000000;
5809 ciaa |= 0xA8;
5810 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5811 ciad = 0x00008000; /* VFLR */
5812 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5813 ciaa &= 0x7FFFFFFF;
5814 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5815 }
5816 }
5817}
5818
5819#endif
7086400d
AD		 5820/**
5821 * ixgbe_service_timer - Timer Call-back
5822 * @data: pointer to adapter cast into an unsigned long
5823 **/
5824static void ixgbe_service_timer(unsigned long data)
5825{
5826 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5827 unsigned long next_event_offset;
83c61fa9 5828 bool ready = true;
7086400d 5829
6bb78cfb
AD		 5830 /* poll faster when waiting for link */
5831 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5832 next_event_offset = HZ / 10;
5833 else
5834 next_event_offset = HZ * 2;
83c61fa9 5835
6bb78cfb 5836#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5837 /*
5838 * don't bother with SR-IOV VF DMA hang check if there are
5839 * no VFs or the link is down
5840 */
5841 if (!adapter->num_vfs ||
6bb78cfb 5842 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5843 goto normal_timer_service;
83c61fa9
GR		 5844
5845 /* If we have VFs allocated then we must check for DMA hangs */
5846 ixgbe_check_for_bad_vf(adapter);
5847 next_event_offset = HZ / 50;
5848 adapter->timer_event_accumulator++;
5849
6bb78cfb 5850 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5851 adapter->timer_event_accumulator = 0;
7086400d 5852 else
6bb78cfb 5853 ready = false;
7086400d 5854
6bb78cfb 5855normal_timer_service:
83c61fa9 5856#endif
7086400d
AD		 5857 /* Reset the timer */
5858 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5859
83c61fa9
GR		 5860 if (ready)
5861 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5862}
5863
c83c6cbd
AD		 5864static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5865{
5866 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5867 return;
5868
5869 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5870
5871 /* If we're already down or resetting, just bail */
5872 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5873 test_bit(__IXGBE_RESETTING, &adapter->state))
5874 return;
5875
5876 ixgbe_dump(adapter);
5877 netdev_err(adapter->netdev, "Reset adapter\n");
5878 adapter->tx_timeout_count++;
5879
5880 ixgbe_reinit_locked(adapter);
5881}
5882
7086400d
AD		 5883/**
5884 * ixgbe_service_task - manages and runs subtasks
5885 * @work: pointer to work_struct containing our data
5886 **/
5887static void ixgbe_service_task(struct work_struct *work)
5888{
5889 struct ixgbe_adapter *adapter = container_of(work,
5890 struct ixgbe_adapter,
5891 service_task);
5892
c83c6cbd 5893 ixgbe_reset_subtask(adapter);
7086400d
AD		 5894 ixgbe_sfp_detection_subtask(adapter);
5895 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5896 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5897 ixgbe_watchdog_subtask(adapter);
d034acf1 5898 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5899 ixgbe_check_hang_subtask(adapter);
3a6a4eda 5900 ixgbe_ptp_overflow_check(adapter);
7086400d
AD		 5901
5902 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5903}
5904
fd0db0ed
AD		 5905static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5906 struct ixgbe_tx_buffer *first,
244e27ad 5907 u8 *hdr_len)
897ab156 5908{
fd0db0ed 5909 struct sk_buff *skb = first->skb;
897ab156
AD		 5910 u32 vlan_macip_lens, type_tucmd;
5911 u32 mss_l4len_idx, l4len;
9a799d71 5912
897ab156
AD		 5913 if (!skb_is_gso(skb))
5914 return 0;
9a799d71 5915
897ab156 5916 if (skb_header_cloned(skb)) {
244e27ad 5917 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5918 if (err)
5919 return err;
9a799d71 5920 }
9a799d71 5921
897ab156
AD		 5922 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5923 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5924
244e27ad 5925 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5926 struct iphdr *iph = ip_hdr(skb);
5927 iph->tot_len = 0;
5928 iph->check = 0;
5929 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5930 iph->daddr, 0,
5931 IPPROTO_TCP,
5932 0);
5933 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5934 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5935 IXGBE_TX_FLAGS_CSUM |
5936 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5937 } else if (skb_is_gso_v6(skb)) {
5938 ipv6_hdr(skb)->payload_len = 0;
5939 tcp_hdr(skb)->check =
5940 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5941 &ipv6_hdr(skb)->daddr,
5942 0, IPPROTO_TCP, 0);
244e27ad
AD		 5943 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5944 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5945 }
5946
091a6246 5947 /* compute header lengths */
897ab156
AD		 5948 l4len = tcp_hdrlen(skb);
5949 *hdr_len = skb_transport_offset(skb) + l4len;
5950
091a6246
AD		 5951 /* update gso size and bytecount with header size */
5952 first->gso_segs = skb_shinfo(skb)->gso_segs;
5953 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5954
897ab156
AD		 5955 /* mss_l4len_id: use 1 as index for TSO */
5956 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5957 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5958 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5959
5960 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5961 vlan_macip_lens = skb_network_header_len(skb);
5962 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5963 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5964
5965 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5966 mss_l4len_idx);
897ab156
AD		 5967
5968 return 1;
5969}
5970
244e27ad
AD		 5971static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5972 struct ixgbe_tx_buffer *first)
7ca647bd 5973{
fd0db0ed 5974 struct sk_buff *skb = first->skb;
897ab156
AD		 5975 u32 vlan_macip_lens = 0;
5976 u32 mss_l4len_idx = 0;
5977 u32 type_tucmd = 0;
7ca647bd 5978
897ab156 5979 if (skb->ip_summed != CHECKSUM_PARTIAL) {
62748b7b
AD		 5980 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5981 if (unlikely(skb->no_fcs))
5982 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5983 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5984 return;
5985 }
897ab156
AD		 5986 } else {
5987 u8 l4_hdr = 0;
244e27ad 5988 switch (first->protocol) {
897ab156
AD		 5989 case __constant_htons(ETH_P_IP):
5990 vlan_macip_lens |= skb_network_header_len(skb);
5991 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5992 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5993 break;
897ab156
AD		 5994 case __constant_htons(ETH_P_IPV6):
5995 vlan_macip_lens |= skb_network_header_len(skb);
5996 l4_hdr = ipv6_hdr(skb)->nexthdr;
5997 break;
5998 default:
5999 if (unlikely(net_ratelimit())) {
6000 dev_warn(tx_ring->dev,
6001 "partial checksum but proto=%x!\n",
244e27ad 6002 first->protocol);
897ab156 6003 }
7ca647bd
JP		 6004 break;
6005 }
897ab156
AD		 6006
6007 switch (l4_hdr) {
7ca647bd 6008 case IPPROTO_TCP:
897ab156
AD		 6009 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6010 mss_l4len_idx = tcp_hdrlen(skb) <<
6011 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6012 break;
6013 case IPPROTO_SCTP:
897ab156
AD		 6014 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6015 mss_l4len_idx = sizeof(struct sctphdr) <<
6016 IXGBE_ADVTXD_L4LEN_SHIFT;
6017 break;
6018 case IPPROTO_UDP:
6019 mss_l4len_idx = sizeof(struct udphdr) <<
6020 IXGBE_ADVTXD_L4LEN_SHIFT;
6021 break;
6022 default:
6023 if (unlikely(net_ratelimit())) {
6024 dev_warn(tx_ring->dev,
6025 "partial checksum but l4 proto=%x!\n",
244e27ad 6026 l4_hdr);
897ab156 6027 }
7ca647bd
JP		 6028 break;
6029 }
244e27ad
AD		 6030
6031 /* update TX checksum flag */
6032 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6033 }
6034
244e27ad 6035 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6036 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6037 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6038
897ab156
AD		 6039 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6040 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6041}
6042
d3d00239 6043static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6044{
d3d00239
AD		 6045 /* set type for advanced descriptor with frame checksum insertion */
6046 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
d3d00239 6047 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6048
d3d00239 6049 /* set HW vlan bit if vlan is present */
66f32a8b 6050 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6051 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6052
3a6a4eda
JK		 6053 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6054 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
3a6a4eda 6055
d3d00239
AD		 6056 /* set segmentation enable bits for TSO/FSO */
6057#ifdef IXGBE_FCOE
93f5b3c1 6058 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 6059#else
6060 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6061#endif
6062 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6063
62748b7b
AD		 6064 /* insert frame checksum */
6065 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6066 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6067
d3d00239
AD		 6068 return cmd_type;
6069}
9a799d71 6070
729739b7
AD		 6071static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6072 u32 tx_flags, unsigned int paylen)
d3d00239 6073{
93f5b3c1 6074 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 6075
d3d00239
AD		 6076 /* enable L4 checksum for TSO and TX checksum offload */
6077 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6078 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6079
93f5b3c1
AD		 6080 /* enble IPv4 checksum for TSO */
6081 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6082 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6083
93f5b3c1
AD		 6084 /* use index 1 context for TSO/FSO/FCOE */
6085#ifdef IXGBE_FCOE
6086 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6087#else
6088 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6089#endif
93f5b3c1
AD		 6090 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6091
7f9643fd
AD		 6092 /*
6093 * Check Context must be set if Tx switch is enabled, which it
6094 * always is for case where virtual functions are running
6095 */
93f5b3c1
AD		 6096#ifdef IXGBE_FCOE
6097 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6098#else
7f9643fd 6099 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6100#endif
7f9643fd
AD		 6101 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6102
729739b7 6103 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6104}
44df32c5 6105
d3d00239
AD		 6106#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6107 IXGBE_TXD_CMD_RS)
6108
6109static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6110 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6111 const u8 hdr_len)
6112{
729739b7 6113 dma_addr_t dma;
fd0db0ed 6114 struct sk_buff *skb = first->skb;
729739b7 6115 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6116 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6117 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6118 unsigned int data_len = skb->data_len;
6119 unsigned int size = skb_headlen(skb);
729739b7 6120 unsigned int paylen = skb->len - hdr_len;
244e27ad 6121 u32 tx_flags = first->tx_flags;
729739b7 6122 __le32 cmd_type;
d3d00239 6123 u16 i = tx_ring->next_to_use;
d3d00239 6124
729739b7
AD		 6125 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6126
6127 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6128 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6129
d3d00239
AD		 6130#ifdef IXGBE_FCOE
6131 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6132 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6133 size -= sizeof(struct fcoe_crc_eof) - data_len;
6134 data_len = 0;
729739b7
AD		 6135 } else {
6136 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6137 }
6138 }
44df32c5 6139
d3d00239 6140#endif
729739b7
AD		 6141 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6142 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6143 goto dma_error;
8ad494b0 6144
729739b7
AD		 6145 /* record length, and DMA address */
6146 dma_unmap_len_set(first, len, size);
6147 dma_unmap_addr_set(first, dma, dma);
9a799d71 6148
729739b7 6149 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6150
d3d00239 6151 for (;;) {
729739b7 6152 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6153 tx_desc->read.cmd_type_len =
6154 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6155
d3d00239 6156 i++;
729739b7 6157 tx_desc++;
d3d00239 6158 if (i == tx_ring->count) {
e4f74028 6159 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6160 i = 0;
6161 }
729739b7
AD		 6162
6163 dma += IXGBE_MAX_DATA_PER_TXD;
6164 size -= IXGBE_MAX_DATA_PER_TXD;
6165
6166 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6167 tx_desc->read.olinfo_status = 0;
d3d00239 6168 }
e5a43549 6169
729739b7
AD		 6170 if (likely(!data_len))
6171 break;
9a799d71 6172
d3d00239 6173 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6174
729739b7
AD		 6175 i++;
6176 tx_desc++;
6177 if (i == tx_ring->count) {
6178 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6179 i = 0;
6180 }
9a799d71 6181
d3d00239 6182#ifdef IXGBE_FCOE
9e903e08 6183 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6184#else
9e903e08 6185 size = skb_frag_size(frag);
d3d00239
AD		 6186#endif
6187 data_len -= size;
9a799d71 6188
729739b7
AD		 6189 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6190 DMA_TO_DEVICE);
6191 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6192 goto dma_error;
9a799d71 6193
729739b7
AD		 6194 tx_buffer = &tx_ring->tx_buffer_info[i];
6195 dma_unmap_len_set(tx_buffer, len, size);
6196 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6197
729739b7
AD		 6198 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6199 tx_desc->read.olinfo_status = 0;
9a799d71 6200
729739b7
AD		 6201 frag++;
6202 }
9a799d71 6203
729739b7
AD		 6204 /* write last descriptor with RS and EOP bits */
6205 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6206 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6207
091a6246 6208 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6209
d3d00239
AD		 6210 /* set the timestamp */
6211 first->time_stamp = jiffies;
9a799d71
AK		 6212
6213 /*
729739b7
AD		 6214 * Force memory writes to complete before letting h/w know there
6215 * are new descriptors to fetch. (Only applicable for weak-ordered
6216 * memory model archs, such as IA-64).
6217 *
6218 * We also need this memory barrier to make certain all of the
6219 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6220 */
6221 wmb();
6222
d3d00239
AD		 6223 /* set next_to_watch value indicating a packet is present */
6224 first->next_to_watch = tx_desc;
6225
729739b7
AD		 6226 i++;
6227 if (i == tx_ring->count)
6228 i = 0;
6229
6230 tx_ring->next_to_use = i;
6231
d3d00239 6232 /* notify HW of packet */
84ea2591 6233 writel(i, tx_ring->tail);
d3d00239
AD		 6234
6235 return;
6236dma_error:
729739b7 6237 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6238
6239 /* clear dma mappings for failed tx_buffer_info map */
6240 for (;;) {
729739b7
AD		 6241 tx_buffer = &tx_ring->tx_buffer_info[i];
6242 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6243 if (tx_buffer == first)
d3d00239
AD		 6244 break;
6245 if (i == 0)
6246 i = tx_ring->count;
6247 i--;
6248 }
6249
d3d00239 6250 tx_ring->next_to_use = i;
9a799d71
AK		 6251}
6252
fd0db0ed 6253static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6254 struct ixgbe_tx_buffer *first)
69830529
AD		 6255{
6256 struct ixgbe_q_vector *q_vector = ring->q_vector;
6257 union ixgbe_atr_hash_dword input = { .dword = 0 };
6258 union ixgbe_atr_hash_dword common = { .dword = 0 };
6259 union {
6260 unsigned char *network;
6261 struct iphdr *ipv4;
6262 struct ipv6hdr *ipv6;
6263 } hdr;
ee9e0f0b 6264 struct tcphdr *th;
905e4a41 6265 __be16 vlan_id;
c4cf55e5 6266
69830529
AD		 6267 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6268 if (!q_vector)
6269 return;
6270
6271 /* do nothing if sampling is disabled */
6272 if (!ring->atr_sample_rate)
d3ead241 6273 return;
c4cf55e5 6274
69830529 6275 ring->atr_count++;
c4cf55e5 6276
69830529 6277 /* snag network header to get L4 type and address */
fd0db0ed 6278 hdr.network = skb_network_header(first->skb);
69830529
AD		 6279
6280 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6281 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6282 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6283 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6284 hdr.ipv4->protocol != IPPROTO_TCP))
6285 return;
ee9e0f0b 6286
fd0db0ed 6287 th = tcp_hdr(first->skb);
c4cf55e5 6288
66f32a8b
AD		 6289 /* skip this packet since it is invalid or the socket is closing */
6290 if (!th || th->fin)
69830529
AD		 6291 return;
6292
6293 /* sample on all syn packets or once every atr sample count */
6294 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6295 return;
6296
6297 /* reset sample count */
6298 ring->atr_count = 0;
6299
244e27ad 6300 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6301
6302 /*
6303 * src and dst are inverted, think how the receiver sees them
6304 *
6305 * The input is broken into two sections, a non-compressed section
6306 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6307 * is XORed together and stored in the compressed dword.
6308 */
6309 input.formatted.vlan_id = vlan_id;
6310
6311 /*
6312 * since src port and flex bytes occupy the same word XOR them together
6313 * and write the value to source port portion of compressed dword
6314 */
244e27ad 6315 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6316 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6317 else
244e27ad 6318 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6319 common.port.dst ^= th->source;
6320
244e27ad 6321 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6322 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6323 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6324 } else {
6325 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6326 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6327 hdr.ipv6->saddr.s6_addr32[1] ^
6328 hdr.ipv6->saddr.s6_addr32[2] ^
6329 hdr.ipv6->saddr.s6_addr32[3] ^
6330 hdr.ipv6->daddr.s6_addr32[0] ^
6331 hdr.ipv6->daddr.s6_addr32[1] ^
6332 hdr.ipv6->daddr.s6_addr32[2] ^
6333 hdr.ipv6->daddr.s6_addr32[3];
6334 }
c4cf55e5
PWJ		 6335
6336 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6337 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6338 input, common, ring->queue_index);
c4cf55e5
PWJ		 6339}
6340
63544e9c 6341static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6342{
fc77dc3c 6343 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6344 /* Herbert's original patch had:
6345 * smp_mb__after_netif_stop_queue();
6346 * but since that doesn't exist yet, just open code it. */
6347 smp_mb();
6348
6349 /* We need to check again in a case another CPU has just
6350 * made room available. */
7d4987de 6351 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6352 return -EBUSY;
6353
6354 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6355 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6356 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6357 return 0;
6358}
6359
82d4e46e 6360static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6361{
7d4987de 6362 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6363 return 0;
fc77dc3c 6364 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6365}
6366
09a3b1f8
SH		 6367static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6368{
6369 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6370 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6371 smp_processor_id();
56075a98 6372#ifdef IXGBE_FCOE
6440752c 6373 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6374
e5b64635
JF		 6375 if (((protocol == htons(ETH_P_FCOE)) ||
6376 (protocol == htons(ETH_P_FIP))) &&
6377 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6378 struct ixgbe_ring_feature *f;
6379
6380 f = &adapter->ring_feature[RING_F_FCOE];
6381
6382 while (txq >= f->indices)
6383 txq -= f->indices;
e4b317e9 6384 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6385
e5b64635 6386 return txq;
56075a98
JF		 6387 }
6388#endif
6389
fdd3d631
KK		 6390 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6391 while (unlikely(txq >= dev->real_num_tx_queues))
6392 txq -= dev->real_num_tx_queues;
5f715823 6393 return txq;
fdd3d631 6394 }
c4cf55e5 6395
09a3b1f8
SH		 6396 return skb_tx_hash(dev, skb);
6397}
6398
fc77dc3c 6399netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6400 struct ixgbe_adapter *adapter,
6401 struct ixgbe_ring *tx_ring)
9a799d71 6402{
d3d00239 6403 struct ixgbe_tx_buffer *first;
5f715823 6404 int tso;
d3d00239 6405 u32 tx_flags = 0;
a535c30e
AD		 6406#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6407 unsigned short f;
6408#endif
a535c30e 6409 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6410 __be16 protocol = skb->protocol;
63544e9c 6411 u8 hdr_len = 0;
5e09a105 6412
a535c30e
AD		 6413 /*
6414 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6415 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6416 * + 2 desc gap to keep tail from touching head,
6417 * + 1 desc for context descriptor,
6418 * otherwise try next time
6419 */
6420#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6421 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6422 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6423#else
6424 count += skb_shinfo(skb)->nr_frags;
6425#endif
6426 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6427 tx_ring->tx_stats.tx_busy++;
6428 return NETDEV_TX_BUSY;
6429 }
6430
fd0db0ed
AD		 6431 /* record the location of the first descriptor for this packet */
6432 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6433 first->skb = skb;
091a6246
AD		 6434 first->bytecount = skb->len;
6435 first->gso_segs = 1;
fd0db0ed 6436
66f32a8b 6437 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6438 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6439 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6440 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6441 /* else if it is a SW VLAN check the next protocol and store the tag */
6442 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6443 struct vlan_hdr *vhdr, _vhdr;
6444 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6445 if (!vhdr)
6446 goto out_drop;
6447
6448 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6449 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6450 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6451 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6452 }
6453
aa7bd467
JK		 6454 skb_tx_timestamp(skb);
6455
3a6a4eda
JK		 6456 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6457 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6458 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6459 }
3a6a4eda 6460
9e0c5648
AD		 6461#ifdef CONFIG_PCI_IOV
6462 /*
6463 * Use the l2switch_enable flag - would be false if the DMA
6464 * Tx switch had been disabled.
6465 */
6466 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6467 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6468
6469#endif
32701dc2 6470 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6471 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6472 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6473 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6474 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6475 tx_flags |= (skb->priority & 0x7) <<
6476 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6477 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6478 struct vlan_ethhdr *vhdr;
6479 if (skb_header_cloned(skb) &&
6480 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6481 goto out_drop;
6482 vhdr = (struct vlan_ethhdr *)skb->data;
6483 vhdr->h_vlan_TCI = htons(tx_flags >>
6484 IXGBE_TX_FLAGS_VLAN_SHIFT);
6485 } else {
6486 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6487 }
9a799d71 6488 }
eacd73f7 6489
244e27ad
AD		 6490 /* record initial flags and protocol */
6491 first->tx_flags = tx_flags;
6492 first->protocol = protocol;
6493
eacd73f7 6494#ifdef IXGBE_FCOE
66f32a8b
AD		 6495 /* setup tx offload for FCoE */
6496 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6497 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6498 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6499 if (tso < 0)
6500 goto out_drop;
9a799d71 6501
66f32a8b 6502 goto xmit_fcoe;
eacd73f7 6503 }
9a799d71 6504
66f32a8b 6505#endif /* IXGBE_FCOE */
244e27ad 6506 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6507 if (tso < 0)
897ab156 6508 goto out_drop;
244e27ad
AD		 6509 else if (!tso)
6510 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6511
6512 /* add the ATR filter if ATR is on */
6513 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6514 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6515
6516#ifdef IXGBE_FCOE
6517xmit_fcoe:
6518#endif /* IXGBE_FCOE */
244e27ad 6519 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6520
6521 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6522
6523 return NETDEV_TX_OK;
897ab156
AD		 6524
6525out_drop:
fd0db0ed
AD		 6526 dev_kfree_skb_any(first->skb);
6527 first->skb = NULL;
6528
897ab156 6529 return NETDEV_TX_OK;
9a799d71
AK		 6530}
6531
a50c29dd
AD		 6532static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6533 struct net_device *netdev)
84418e3b
AD		 6534{
6535 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6536 struct ixgbe_ring *tx_ring;
6537
a50c29dd
AD		 6538 /*
6539 * The minimum packet size for olinfo paylen is 17 so pad the skb
6540 * in order to meet this minimum size requirement.
6541 */
f73332fc
SH		 6542 if (unlikely(skb->len < 17)) {
6543 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6544 return NETDEV_TX_OK;
6545 skb->len = 17;
71a49f77 6546 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6547 }
6548
84418e3b 6549 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6550 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6551}
6552
9a799d71
AK		 6553/**
6554 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6555 * @netdev: network interface device structure
6556 * @p: pointer to an address structure
6557 *
6558 * Returns 0 on success, negative on failure
6559 **/
6560static int ixgbe_set_mac(struct net_device *netdev, void *p)
6561{
6562 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6563 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6564 struct sockaddr *addr = p;
6565
6566 if (!is_valid_ether_addr(addr->sa_data))
6567 return -EADDRNOTAVAIL;
6568
6569 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6570 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6571
1d9c0bfd 6572 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6573
6574 return 0;
6575}
6576
6b73e10d
BH		 6577static int
6578ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6579{
6580 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6581 struct ixgbe_hw *hw = &adapter->hw;
6582 u16 value;
6583 int rc;
6584
6585 if (prtad != hw->phy.mdio.prtad)
6586 return -EINVAL;
6587 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6588 if (!rc)
6589 rc = value;
6590 return rc;
6591}
6592
6593static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6594 u16 addr, u16 value)
6595{
6596 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6597 struct ixgbe_hw *hw = &adapter->hw;
6598
6599 if (prtad != hw->phy.mdio.prtad)
6600 return -EINVAL;
6601 return hw->phy.ops.write_reg(hw, addr, devad, value);
6602}
6603
6604static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6605{
6606 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6607
3a6a4eda 6608 switch (cmd) {
3a6a4eda
JK		 6609 case SIOCSHWTSTAMP:
6610 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6611 default:
6612 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6613 }
6b73e10d
BH		 6614}
6615
0365e6e4
PW		 6616/**
6617 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6618 * netdev->dev_addrs
0365e6e4
PW		 6619 * @netdev: network interface device structure
6620 *
6621 * Returns non-zero on failure
6622 **/
6623static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6624{
6625 int err = 0;
6626 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6627 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6628
7fa7c9dc 6629 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6630 rtnl_lock();
7fa7c9dc 6631 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6632 rtnl_unlock();
7fa7c9dc
AD		 6633
6634 /* update SAN MAC vmdq pool selection */
6635 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6636 }
6637 return err;
6638}
6639
6640/**
6641 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6642 * netdev->dev_addrs
0365e6e4
PW		 6643 * @netdev: network interface device structure
6644 *
6645 * Returns non-zero on failure
6646 **/
6647static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6648{
6649 int err = 0;
6650 struct ixgbe_adapter *adapter = netdev_priv(dev);
6651 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6652
6653 if (is_valid_ether_addr(mac->san_addr)) {
6654 rtnl_lock();
6655 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6656 rtnl_unlock();
6657 }
6658 return err;
6659}
6660
9a799d71
AK		 6661#ifdef CONFIG_NET_POLL_CONTROLLER
6662/*
6663 * Polling 'interrupt' - used by things like netconsole to send skbs
6664 * without having to re-enable interrupts. It's not called while
6665 * the interrupt routine is executing.
6666 */
6667static void ixgbe_netpoll(struct net_device *netdev)
6668{
6669 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6670 int i;
9a799d71 6671
1a647bd2
AD		 6672 /* if interface is down do nothing */
6673 if (test_bit(__IXGBE_DOWN, &adapter->state))
6674 return;
6675
9a799d71 6676 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6677 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6678 for (i = 0; i < adapter->num_q_vectors; i++)
6679 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6680 } else {
6681 ixgbe_intr(adapter->pdev->irq, netdev);
6682 }
9a799d71 6683 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6684}
9a799d71 6685
581330ba 6686#endif
de1036b1
ED		 6687static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6688 struct rtnl_link_stats64 *stats)
6689{
6690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6691 int i;
6692
1a51502b 6693 rcu_read_lock();
de1036b1 6694 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6695 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6696 u64 bytes, packets;
6697 unsigned int start;
6698
1a51502b
ED		 6699 if (ring) {
6700 do {
6701 start = u64_stats_fetch_begin_bh(&ring->syncp);
6702 packets = ring->stats.packets;
6703 bytes = ring->stats.bytes;
6704 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6705 stats->rx_packets += packets;
6706 stats->rx_bytes += bytes;
6707 }
de1036b1 6708 }
1ac9ad13
ED		 6709
6710 for (i = 0; i < adapter->num_tx_queues; i++) {
6711 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6712 u64 bytes, packets;
6713 unsigned int start;
6714
6715 if (ring) {
6716 do {
6717 start = u64_stats_fetch_begin_bh(&ring->syncp);
6718 packets = ring->stats.packets;
6719 bytes = ring->stats.bytes;
6720 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6721 stats->tx_packets += packets;
6722 stats->tx_bytes += bytes;
6723 }
6724 }
1a51502b 6725 rcu_read_unlock();
de1036b1
ED		 6726 /* following stats updated by ixgbe_watchdog_task() */
6727 stats->multicast = netdev->stats.multicast;
6728 stats->rx_errors = netdev->stats.rx_errors;
6729 stats->rx_length_errors = netdev->stats.rx_length_errors;
6730 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6731 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6732 return stats;
6733}
6734
8af3c33f 6735#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6736/**
6737 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6738 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6739 * @tc: number of traffic classes currently enabled
6740 *
6741 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6742 * 802.1Q priority maps to a packet buffer that exists.
6743 */
6744static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6745{
6746 struct ixgbe_hw *hw = &adapter->hw;
6747 u32 reg, rsave;
6748 int i;
6749
6750 /* 82598 have a static priority to TC mapping that can not
6751 * be changed so no validation is needed.
6752 */
6753 if (hw->mac.type == ixgbe_mac_82598EB)
6754 return;
6755
6756 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6757 rsave = reg;
6758
6759 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6760 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6761
6762 /* If up2tc is out of bounds default to zero */
6763 if (up2tc > tc)
6764 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6765 }
6766
6767 if (reg != rsave)
6768 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6769
6770 return;
6771}
6772
02debdc9
AD		 6773/**
6774 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6775 * @adapter: Pointer to adapter struct
6776 *
6777 * Populate the netdev user priority to tc map
6778 */
6779static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6780{
6781 struct net_device *dev = adapter->netdev;
6782 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6783 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6784 u8 prio;
6785
6786 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6787 u8 tc = 0;
6788
6789 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6790 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6791 else if (ets)
6792 tc = ets->prio_tc[prio];
6793
6794 netdev_set_prio_tc_map(dev, prio, tc);
6795 }
6796}
6797
49ce9c2c
BH		 6798/**
6799 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6800 *
6801 * @netdev: net device to configure
6802 * @tc: number of traffic classes to enable
6803 */
6804int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6805{
8b1c0b24
JF		 6806 struct ixgbe_adapter *adapter = netdev_priv(dev);
6807 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6808
8b1c0b24 6809 /* Hardware supports up to 8 traffic classes */
4de2a022 6810 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6811 (hw->mac.type == ixgbe_mac_82598EB &&
6812 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6813 return -EINVAL;
6814
6815 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6816 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6817 * hardware is not flexible enough to do this dynamically.
6818 */
6819 if (netif_running(dev))
6820 ixgbe_close(dev);
6821 ixgbe_clear_interrupt_scheme(adapter);
6822
e7589eab 6823 if (tc) {
8b1c0b24 6824 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6825 ixgbe_set_prio_tc_map(adapter);
6826
e7589eab 6827 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6828
943561d3
AD		 6829 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6830 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6831 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6832 }
e7589eab 6833 } else {
8b1c0b24 6834 netdev_reset_tc(dev);
02debdc9 6835
943561d3
AD		 6836 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6837 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6838
6839 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6840
6841 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6842 adapter->dcb_cfg.pfc_mode_enable = false;
6843 }
6844
8b1c0b24
JF		 6845 ixgbe_init_interrupt_scheme(adapter);
6846 ixgbe_validate_rtr(adapter, tc);
6847 if (netif_running(dev))
6848 ixgbe_open(dev);
6849
6850 return 0;
6851}
de1036b1 6852
8af3c33f 6853#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6854void ixgbe_do_reset(struct net_device *netdev)
6855{
6856 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6857
6858 if (netif_running(netdev))
6859 ixgbe_reinit_locked(adapter);
6860 else
6861 ixgbe_reset(adapter);
6862}
6863
c8f44aff 6864static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6865 netdev_features_t features)
082757af
DS		 6866{
6867 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6868
082757af 6869 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6870 if (!(features & NETIF_F_RXCSUM))
6871 features &= ~NETIF_F_LRO;
082757af 6872
567d2de2
AD		 6873 /* Turn off LRO if not RSC capable */
6874 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6875 features &= ~NETIF_F_LRO;
8e2813f5 6876
567d2de2 6877 return features;
082757af
DS		 6878}
6879
c8f44aff 6880static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6881 netdev_features_t features)
082757af
DS		 6882{
6883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6884 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6885 bool need_reset = false;
6886
082757af 6887 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6888 if (!(features & NETIF_F_LRO)) {
6889 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6890 need_reset = true;
567d2de2
AD		 6891 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6892 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6893 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6894 if (adapter->rx_itr_setting == 1 ||
6895 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6896 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6897 need_reset = true;
6898 } else if ((changed ^ features) & NETIF_F_LRO) {
6899 e_info(probe, "rx-usecs set too low, "
6900 "disabling RSC\n");
082757af
DS		 6901 }
6902 }
6903
6904 /*
6905 * Check if Flow Director n-tuple support was enabled or disabled. If
6906 * the state changed, we need to reset.
6907 */
39cb681b
AD		 6908 switch (features & NETIF_F_NTUPLE) {
6909 case NETIF_F_NTUPLE:
567d2de2 6910 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6911 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6912 need_reset = true;
6913
567d2de2
AD		 6914 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6915 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6916 break;
6917 default:
6918 /* turn off perfect filters, enable ATR and reset */
6919 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6920 need_reset = true;
6921
6922 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6923
6924 /* We cannot enable ATR if SR-IOV is enabled */
6925 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6926 break;
6927
6928 /* We cannot enable ATR if we have 2 or more traffic classes */
6929 if (netdev_get_num_tc(netdev) > 1)
6930 break;
6931
6932 /* We cannot enable ATR if RSS is disabled */
6933 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6934 break;
6935
6936 /* A sample rate of 0 indicates ATR disabled */
6937 if (!adapter->atr_sample_rate)
6938 break;
6939
6940 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6941 break;
082757af
DS		 6942 }
6943
146d4cc9
JF		 6944 if (features & NETIF_F_HW_VLAN_RX)
6945 ixgbe_vlan_strip_enable(adapter);
6946 else
6947 ixgbe_vlan_strip_disable(adapter);
6948
3f2d1c0f
BG		 6949 if (changed & NETIF_F_RXALL)
6950 need_reset = true;
6951
567d2de2 6952 netdev->features = features;
082757af
DS		 6953 if (need_reset)
6954 ixgbe_do_reset(netdev);
6955
6956 return 0;
082757af
DS		 6957}
6958
edc7d573 6959static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 6960 struct net_device *dev,
6b6e2725 6961 const unsigned char *addr,
0f4b0add
JF		 6962 u16 flags)
6963{
6964 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6965 int err;
6966
6967 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6968 return -EOPNOTSUPP;
0f4b0add
JF		 6969
6970 if (ndm->ndm_state & NUD_PERMANENT) {
6971 pr_info("%s: FDB only supports static addresses\n",
6972 ixgbe_driver_name);
6973 return -EINVAL;
6974 }
6975
b3343a2a 6976 if (is_unicast_ether_addr(addr) || is_link_local(addr)) {
95447461
JF		 6977 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6978
6979 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6980 err = dev_uc_add_excl(dev, addr);
0f4b0add 6981 else
95447461
JF		 6982 err = -ENOMEM;
6983 } else if (is_multicast_ether_addr(addr)) {
6984 err = dev_mc_add_excl(dev, addr);
6985 } else {
6986 err = -EINVAL;
0f4b0add
JF		 6987 }
6988
6989 /* Only return duplicate errors if NLM_F_EXCL is set */
6990 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6991 err = 0;
6992
6993 return err;
6994}
6995
6996static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6997 struct net_device *dev,
6b6e2725 6998 const unsigned char *addr)
0f4b0add
JF		 6999{
7000 struct ixgbe_adapter *adapter = netdev_priv(dev);
7001 int err = -EOPNOTSUPP;
7002
7003 if (ndm->ndm_state & NUD_PERMANENT) {
7004 pr_info("%s: FDB only supports static addresses\n",
7005 ixgbe_driver_name);
7006 return -EINVAL;
7007 }
7008
7009 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7010 if (is_unicast_ether_addr(addr))
7011 err = dev_uc_del(dev, addr);
7012 else if (is_multicast_ether_addr(addr))
7013 err = dev_mc_del(dev, addr);
7014 else
7015 err = -EINVAL;
7016 }
7017
7018 return err;
7019}
7020
7021static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7022 struct netlink_callback *cb,
7023 struct net_device *dev,
7024 int idx)
7025{
7026 struct ixgbe_adapter *adapter = netdev_priv(dev);
7027
7028 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7029 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7030
7031 return idx;
7032}
7033
815cccbf
JF		 7034static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7035 struct nlmsghdr *nlh)
7036{
7037 struct ixgbe_adapter *adapter = netdev_priv(dev);
7038 struct nlattr *attr, *br_spec;
7039 int rem;
7040
7041 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7042 return -EOPNOTSUPP;
7043
7044 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7045
7046 nla_for_each_nested(attr, br_spec, rem) {
7047 __u16 mode;
7048 u32 reg = 0;
7049
7050 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7051 continue;
7052
7053 mode = nla_get_u16(attr);
7054 if (mode == BRIDGE_MODE_VEPA)
7055 reg = 0;
7056 else if (mode == BRIDGE_MODE_VEB)
7057 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7058 else
7059 return -EINVAL;
7060
7061 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7062
7063 e_info(drv, "enabling bridge mode: %s\n",
7064 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7065 }
7066
7067 return 0;
7068}
7069
7070static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7071 struct net_device *dev)
7072{
7073 struct ixgbe_adapter *adapter = netdev_priv(dev);
7074 u16 mode;
7075
7076 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7077 return 0;
7078
7079 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7080 mode = BRIDGE_MODE_VEB;
7081 else
7082 mode = BRIDGE_MODE_VEPA;
7083
7084 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7085}
7086
0edc3527 7087static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7088 .ndo_open = ixgbe_open,
0edc3527 7089 .ndo_stop = ixgbe_close,
00829823 7090 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7091 .ndo_select_queue = ixgbe_select_queue,
581330ba 7092 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7093 .ndo_validate_addr = eth_validate_addr,
7094 .ndo_set_mac_address = ixgbe_set_mac,
7095 .ndo_change_mtu = ixgbe_change_mtu,
7096 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7097 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7098 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7099 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7100 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7101 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7102 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7103 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7104 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7105 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7106#ifdef CONFIG_IXGBE_DCB
24095aa3 7107 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7108#endif
0edc3527
SH		 7109#ifdef CONFIG_NET_POLL_CONTROLLER
7110 .ndo_poll_controller = ixgbe_netpoll,
7111#endif
332d4a7d
YZ		 7112#ifdef IXGBE_FCOE
7113 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7114 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7115 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7116 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7117 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7118 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7119 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7120#endif /* IXGBE_FCOE */
082757af
DS		 7121 .ndo_set_features = ixgbe_set_features,
7122 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 7123 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7124 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7125 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
815cccbf
JF		 7126 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7127 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7128};
7129
8e2813f5
JK		 7130/**
7131 * ixgbe_wol_supported - Check whether device supports WoL
7132 * @hw: hw specific details
7133 * @device_id: the device ID
7134 * @subdev_id: the subsystem device ID
7135 *
7136 * This function is used by probe and ethtool to determine
7137 * which devices have WoL support
7138 *
7139 **/
7140int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7141 u16 subdevice_id)
7142{
7143 struct ixgbe_hw *hw = &adapter->hw;
7144 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7145 int is_wol_supported = 0;
7146
7147 switch (device_id) {
7148 case IXGBE_DEV_ID_82599_SFP:
7149 /* Only these subdevices could supports WOL */
7150 switch (subdevice_id) {
7151 case IXGBE_SUBDEV_ID_82599_560FLR:
7152 /* only support first port */
7153 if (hw->bus.func != 0)
7154 break;
7155 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7156 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7157 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8e2813f5
JK		 7158 is_wol_supported = 1;
7159 break;
7160 }
7161 break;
7162 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7163 /* All except this subdevice support WOL */
7164 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7165 is_wol_supported = 1;
7166 break;
7167 case IXGBE_DEV_ID_82599_KX4:
7168 is_wol_supported = 1;
7169 break;
7170 case IXGBE_DEV_ID_X540T:
df376f0d 7171 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7172 /* check eeprom to see if enabled wol */
7173 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7174 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7175 (hw->bus.func == 0))) {
7176 is_wol_supported = 1;
7177 }
7178 break;
7179 }
7180
7181 return is_wol_supported;
7182}
7183
9a799d71
AK		 7184/**
7185 * ixgbe_probe - Device Initialization Routine
7186 * @pdev: PCI device information struct
7187 * @ent: entry in ixgbe_pci_tbl
7188 *
7189 * Returns 0 on success, negative on failure
7190 *
7191 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7192 * The OS initialization, configuring of the adapter private structure,
7193 * and a hardware reset occur.
7194 **/
7195static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7196 const struct pci_device_id *ent)
9a799d71
AK		 7197{
7198 struct net_device *netdev;
7199 struct ixgbe_adapter *adapter = NULL;
7200 struct ixgbe_hw *hw;
7201 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7202 static int cards_found;
7203 int i, err, pci_using_dac;
289700db 7204 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7205 unsigned int indices = num_possible_cpus();
3f4a6f00 7206 unsigned int dcb_max = 0;
eacd73f7
YZ		 7207#ifdef IXGBE_FCOE
7208 u16 device_caps;
7209#endif
289700db 7210 u32 eec;
9a799d71 7211
bded64a7
AG		 7212 /* Catch broken hardware that put the wrong VF device ID in
7213 * the PCIe SR-IOV capability.
7214 */
7215 if (pdev->is_virtfn) {
7216 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7217 pci_name(pdev), pdev->vendor, pdev->device);
7218 return -EINVAL;
7219 }
7220
9ce77666 7221 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7222 if (err)
7223 return err;
7224
1b507730
NN		 7225 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7226 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7227 pci_using_dac = 1;
7228 } else {
1b507730 7229 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7230 if (err) {
1b507730
NN		 7231 err = dma_set_coherent_mask(&pdev->dev,
7232 DMA_BIT_MASK(32));
9a799d71 7233 if (err) {
b8bc0421
DC		 7234 dev_err(&pdev->dev,
7235 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7236 goto err_dma;
7237 }
7238 }
7239 pci_using_dac = 0;
7240 }
7241
9ce77666 7242 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7243 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7244 if (err) {
b8bc0421
DC		 7245 dev_err(&pdev->dev,
7246 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7247 goto err_pci_reg;
7248 }
7249
19d5afd4 7250 pci_enable_pcie_error_reporting(pdev);
6fabd715 7251
9a799d71 7252 pci_set_master(pdev);
fb3b27bc 7253 pci_save_state(pdev);
9a799d71 7254
e901acd6 7255#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7256 if (ii->mac == ixgbe_mac_82598EB)
7257 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7258 IXGBE_MAX_RSS_INDICES);
7259 else
7260 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7261 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7262#endif
7263
c85a2618
JF		 7264 if (ii->mac == ixgbe_mac_82598EB)
7265 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7266 else
7267 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7268
e901acd6 7269#ifdef IXGBE_FCOE
c85a2618
JF		 7270 indices += min_t(unsigned int, num_possible_cpus(),
7271 IXGBE_MAX_FCOE_INDICES);
7272#endif
3f4a6f00 7273 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7274 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7275 if (!netdev) {
7276 err = -ENOMEM;
7277 goto err_alloc_etherdev;
7278 }
7279
9a799d71
AK		 7280 SET_NETDEV_DEV(netdev, &pdev->dev);
7281
9a799d71 7282 adapter = netdev_priv(netdev);
c60fbb00 7283 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7284
7285 adapter->netdev = netdev;
7286 adapter->pdev = pdev;
7287 hw = &adapter->hw;
7288 hw->back = adapter;
b3f4d599 7289 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7290
05857980 7291 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7292 pci_resource_len(pdev, 0));
9a799d71
AK		 7293 if (!hw->hw_addr) {
7294 err = -EIO;
7295 goto err_ioremap;
7296 }
7297
0edc3527 7298 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7299 ixgbe_set_ethtool_ops(netdev);
9a799d71 7300 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7301 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7302
9a799d71
AK		 7303 adapter->bd_number = cards_found;
7304
9a799d71
AK		 7305 /* Setup hw api */
7306 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7307 hw->mac.type = ii->mac;
9a799d71 7308
c44ade9e
JB		 7309 /* EEPROM */
7310 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7311 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7312 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7313 if (!(eec & (1 << 8)))
7314 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7315
7316 /* PHY */
7317 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7318 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7319 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7320 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7321 hw->phy.mdio.mmds = 0;
7322 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7323 hw->phy.mdio.dev = netdev;
7324 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7325 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7326
8ca783ab 7327 ii->get_invariants(hw);
9a799d71
AK		 7328
7329 /* setup the private structure */
7330 err = ixgbe_sw_init(adapter);
7331 if (err)
7332 goto err_sw_init;
7333
e86bff0e 7334 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7335 switch (adapter->hw.mac.type) {
7336 case ixgbe_mac_82599EB:
7337 case ixgbe_mac_X540:
e86bff0e 7338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7339 break;
7340 default:
7341 break;
7342 }
e86bff0e 7343
bf069c97
DS		 7344 /*
7345 * If there is a fan on this device and it has failed log the
7346 * failure.
7347 */
7348 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7349 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7350 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7351 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7352 }
7353
8ef78adc
PWJ		 7354 if (allow_unsupported_sfp)
7355 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7356
c44ade9e 7357 /* reset_hw fills in the perm_addr as well */
119fc60a 7358 hw->phy.reset_if_overtemp = true;
c44ade9e 7359 err = hw->mac.ops.reset_hw(hw);
119fc60a 7360 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7361 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7362 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7363 err = 0;
7364 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7365 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7366 "module type was detected.\n");
7367 e_dev_err("Reload the driver after installing a supported "
7368 "module.\n");
04f165ef
PW		 7369 goto err_sw_init;
7370 } else if (err) {
849c4542 7371 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7372 goto err_sw_init;
7373 }
7374
99d74487
AD		 7375#ifdef CONFIG_PCI_IOV
7376 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7377
99d74487 7378#endif
396e799c 7379 netdev->features = NETIF_F_SG |
e8e9f696 7380 NETIF_F_IP_CSUM |
082757af 7381 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7382 NETIF_F_HW_VLAN_TX |
7383 NETIF_F_HW_VLAN_RX |
082757af
DS		 7384 NETIF_F_HW_VLAN_FILTER |
7385 NETIF_F_TSO |
7386 NETIF_F_TSO6 |
082757af
DS		 7387 NETIF_F_RXHASH |
7388 NETIF_F_RXCSUM;
9a799d71 7389
082757af 7390 netdev->hw_features = netdev->features;
ad31c402 7391
58be7666
DS		 7392 switch (adapter->hw.mac.type) {
7393 case ixgbe_mac_82599EB:
7394 case ixgbe_mac_X540:
45a5ead0 7395 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7396 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7397 NETIF_F_NTUPLE;
58be7666
DS		 7398 break;
7399 default:
7400 break;
7401 }
45a5ead0 7402
3f2d1c0f
BG		 7403 netdev->hw_features |= NETIF_F_RXALL;
7404
ad31c402
JK		 7405 netdev->vlan_features |= NETIF_F_TSO;
7406 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7407 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7408 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7409 netdev->vlan_features |= NETIF_F_SG;
7410
01789349 7411 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7412 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7413
7a6b6f51 7414#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7415 netdev->dcbnl_ops = &dcbnl_ops;
7416#endif
7417
eacd73f7 7418#ifdef IXGBE_FCOE
0d551589 7419 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7420 if (hw->mac.ops.get_device_caps) {
7421 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7422 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7423 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7424 }
7c8ae65a
AD		 7425
7426 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7427
a58915c7
AD		 7428 netdev->features |= NETIF_F_FSO |
7429 NETIF_F_FCOE_CRC;
7430
7c8ae65a
AD		 7431 netdev->vlan_features |= NETIF_F_FSO |
7432 NETIF_F_FCOE_CRC |
7433 NETIF_F_FCOE_MTU;
5e09d7f6 7434 }
eacd73f7 7435#endif /* IXGBE_FCOE */
7b872a55 7436 if (pci_using_dac) {
9a799d71 7437 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7438 netdev->vlan_features |= NETIF_F_HIGHDMA;
7439 }
9a799d71 7440
082757af
DS		 7441 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7442 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7443 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7444 netdev->features |= NETIF_F_LRO;
7445
9a799d71 7446 /* make sure the EEPROM is good */
c44ade9e 7447 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7448 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7449 err = -EIO;
35937c05 7450 goto err_sw_init;
9a799d71
AK		 7451 }
7452
7453 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7454 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7455
c44ade9e 7456 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7457 e_dev_err("invalid MAC address\n");
9a799d71 7458 err = -EIO;
35937c05 7459 goto err_sw_init;
9a799d71
AK		 7460 }
7461
7086400d 7462 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7463 (unsigned long) adapter);
9a799d71 7464
7086400d
AD		 7465 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7466 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7467
021230d4
AV		 7468 err = ixgbe_init_interrupt_scheme(adapter);
7469 if (err)
7470 goto err_sw_init;
9a799d71 7471
8e2813f5 7472 /* WOL not supported for all devices */
c23f5b6b 7473 adapter->wol = 0;
8e2813f5
JK		 7474 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7475 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7476 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7477
e8e26350
PW		 7478 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7479
15e5209f
ET		 7480 /* save off EEPROM version number */
7481 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7482 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7483
04f165ef
PW		 7484 /* pick up the PCI bus settings for reporting later */
7485 hw->mac.ops.get_bus_info(hw);
7486
9a799d71 7487 /* print bus type/speed/width info */
849c4542 7488 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7489 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7490 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7491 "Unknown"),
7492 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7493 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7494 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7495 "Unknown"),
7496 netdev->dev_addr);
289700db
DS		 7497
7498 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7499 if (err)
9fe93afd 7500 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7501 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7502 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7503 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7504 part_str);
e8e26350 7505 else
289700db
DS		 7506 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7507 hw->mac.type, hw->phy.type, part_str);
9a799d71 7508
e8e26350 7509 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7510 e_dev_warn("PCI-Express bandwidth available for this card is "
7511 "not sufficient for optimal performance.\n");
7512 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7513 "is required.\n");
0c254d86
AK		 7514 }
7515
9a799d71 7516 /* reset the hardware with the new settings */
794caeb2 7517 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7518 if (err == IXGBE_ERR_EEPROM_VERSION) {
7519 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7520 e_dev_warn("This device is a pre-production adapter/LOM. "
7521 "Please be aware there may be issues associated "
7522 "with your hardware. If you are experiencing "
7523 "problems please contact your Intel or hardware "
7524 "representative who provided you with this "
7525 "hardware.\n");
794caeb2 7526 }
9a799d71
AK		 7527 strcpy(netdev->name, "eth%d");
7528 err = register_netdev(netdev);
7529 if (err)
7530 goto err_register;
7531
ec74a471
ET		 7532 /* power down the optics for 82599 SFP+ fiber */
7533 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7534 hw->mac.ops.disable_tx_laser(hw);
7535
54386467
JB		 7536 /* carrier off reporting is important to ethtool even BEFORE open */
7537 netif_carrier_off(netdev);
7538
5dd2d332 7539#ifdef CONFIG_IXGBE_DCA
652f093f 7540 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7541 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7542 ixgbe_setup_dca(adapter);
7543 }
7544#endif
1cdd1ec8 7545 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7546 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7547 for (i = 0; i < adapter->num_vfs; i++)
7548 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7549 }
7550
2466dd9c
JK		 7551 /* firmware requires driver version to be 0xFFFFFFFF
7552 * since os does not support feature
7553 */
9612de92 7554 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7555 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7556 0xFF);
9612de92 7557
0365e6e4
PW		 7558 /* add san mac addr to netdev */
7559 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7560
ea81875a 7561 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7562 cards_found++;
3ca8bc6d 7563
1210982b 7564#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7565 if (ixgbe_sysfs_init(adapter))
7566 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7567#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7568
00949167
CS		 7569#ifdef CONFIG_DEBUG_FS
7570 ixgbe_dbg_adapter_init(adapter);
7571#endif /* CONFIG_DEBUG_FS */
7572
9a799d71
AK		 7573 return 0;
7574
7575err_register:
5eba3699 7576 ixgbe_release_hw_control(adapter);
7a921c93 7577 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7578err_sw_init:
99d74487 7579 ixgbe_disable_sriov(adapter);
7086400d 7580 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7581 iounmap(hw->hw_addr);
7582err_ioremap:
7583 free_netdev(netdev);
7584err_alloc_etherdev:
e8e9f696
JP		 7585 pci_release_selected_regions(pdev,
7586 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7587err_pci_reg:
7588err_dma:
7589 pci_disable_device(pdev);
7590 return err;
7591}
7592
7593/**
7594 * ixgbe_remove - Device Removal Routine
7595 * @pdev: PCI device information struct
7596 *
7597 * ixgbe_remove is called by the PCI subsystem to alert the driver
7598 * that it should release a PCI device. The could be caused by a
7599 * Hot-Plug event, or because the driver is going to be removed from
7600 * memory.
7601 **/
7602static void __devexit ixgbe_remove(struct pci_dev *pdev)
7603{
c60fbb00
AD		 7604 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7605 struct net_device *netdev = adapter->netdev;
9a799d71 7606
00949167
CS		 7607#ifdef CONFIG_DEBUG_FS
7608 ixgbe_dbg_adapter_exit(adapter);
7609#endif /*CONFIG_DEBUG_FS */
7610
9a799d71 7611 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7612 cancel_work_sync(&adapter->service_task);
9a799d71 7613
3a6a4eda 7614
5dd2d332 7615#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7616 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7617 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7618 dca_remove_requester(&pdev->dev);
7619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7620 }
7621
7622#endif
1210982b 7623#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7624 ixgbe_sysfs_exit(adapter);
1210982b 7625#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7626
0365e6e4
PW		 7627 /* remove the added san mac */
7628 ixgbe_del_sanmac_netdev(netdev);
7629
c4900be0
DS		 7630 if (netdev->reg_state == NETREG_REGISTERED)
7631 unregister_netdev(netdev);
9a799d71 7632
9297127b 7633 ixgbe_disable_sriov(adapter);
1cdd1ec8 7634
7a921c93 7635 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7636
021230d4 7637 ixgbe_release_hw_control(adapter);
9a799d71 7638
2b1588c3
AD		 7639#ifdef CONFIG_DCB
7640 kfree(adapter->ixgbe_ieee_pfc);
7641 kfree(adapter->ixgbe_ieee_ets);
7642
7643#endif
9a799d71 7644 iounmap(adapter->hw.hw_addr);
9ce77666 7645 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7646 IORESOURCE_MEM));
9a799d71 7647
849c4542 7648 e_dev_info("complete\n");
021230d4 7649
9a799d71
AK		 7650 free_netdev(netdev);
7651
19d5afd4 7652 pci_disable_pcie_error_reporting(pdev);
6fabd715 7653
9a799d71
AK		 7654 pci_disable_device(pdev);
7655}
7656
7657/**
7658 * ixgbe_io_error_detected - called when PCI error is detected
7659 * @pdev: Pointer to PCI device
7660 * @state: The current pci connection state
7661 *
7662 * This function is called after a PCI bus error affecting
7663 * this device has been detected.
7664 */
7665static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7666 pci_channel_state_t state)
9a799d71 7667{
c60fbb00
AD		 7668 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7669 struct net_device *netdev = adapter->netdev;
9a799d71 7670
83c61fa9
GR		 7671#ifdef CONFIG_PCI_IOV
7672 struct pci_dev *bdev, *vfdev;
7673 u32 dw0, dw1, dw2, dw3;
7674 int vf, pos;
7675 u16 req_id, pf_func;
7676
7677 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7678 adapter->num_vfs == 0)
7679 goto skip_bad_vf_detection;
7680
7681 bdev = pdev->bus->self;
62f87c0e 7682 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7683 bdev = bdev->bus->self;
7684
7685 if (!bdev)
7686 goto skip_bad_vf_detection;
7687
7688 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7689 if (!pos)
7690 goto skip_bad_vf_detection;
7691
7692 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7693 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7694 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7695 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7696
7697 req_id = dw1 >> 16;
7698 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7699 if (!(req_id & 0x0080))
7700 goto skip_bad_vf_detection;
7701
7702 pf_func = req_id & 0x01;
7703 if ((pf_func & 1) == (pdev->devfn & 1)) {
7704 unsigned int device_id;
7705
7706 vf = (req_id & 0x7F) >> 1;
7707 e_dev_err("VF %d has caused a PCIe error\n", vf);
7708 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7709 "%8.8x\tdw3: %8.8x\n",
7710 dw0, dw1, dw2, dw3);
7711 switch (adapter->hw.mac.type) {
7712 case ixgbe_mac_82599EB:
7713 device_id = IXGBE_82599_VF_DEVICE_ID;
7714 break;
7715 case ixgbe_mac_X540:
7716 device_id = IXGBE_X540_VF_DEVICE_ID;
7717 break;
7718 default:
7719 device_id = 0;
7720 break;
7721 }
7722
7723 /* Find the pci device of the offending VF */
36e90319 7724 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7725 while (vfdev) {
7726 if (vfdev->devfn == (req_id & 0xFF))
7727 break;
36e90319 7728 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7729 device_id, vfdev);
7730 }
7731 /*
7732 * There's a slim chance the VF could have been hot plugged,
7733 * so if it is no longer present we don't need to issue the
7734 * VFLR. Just clean up the AER in that case.
7735 */
7736 if (vfdev) {
7737 e_dev_err("Issuing VFLR to VF %d\n", vf);
7738 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7739 }
7740
7741 pci_cleanup_aer_uncorrect_error_status(pdev);
7742 }
7743
7744 /*
7745 * Even though the error may have occurred on the other port
7746 * we still need to increment the vf error reference count for
7747 * both ports because the I/O resume function will be called
7748 * for both of them.
7749 */
7750 adapter->vferr_refcount++;
7751
7752 return PCI_ERS_RESULT_RECOVERED;
7753
7754skip_bad_vf_detection:
7755#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7756 netif_device_detach(netdev);
7757
3044b8d1
BL		 7758 if (state == pci_channel_io_perm_failure)
7759 return PCI_ERS_RESULT_DISCONNECT;
7760
9a799d71
AK		 7761 if (netif_running(netdev))
7762 ixgbe_down(adapter);
7763 pci_disable_device(pdev);
7764
b4617240 7765 /* Request a slot reset. */
9a799d71
AK		 7766 return PCI_ERS_RESULT_NEED_RESET;
7767}
7768
7769/**
7770 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7771 * @pdev: Pointer to PCI device
7772 *
7773 * Restart the card from scratch, as if from a cold-boot.
7774 */
7775static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7776{
c60fbb00 7777 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7778 pci_ers_result_t result;
7779 int err;
9a799d71 7780
9ce77666 7781 if (pci_enable_device_mem(pdev)) {
396e799c 7782 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7783 result = PCI_ERS_RESULT_DISCONNECT;
7784 } else {
7785 pci_set_master(pdev);
7786 pci_restore_state(pdev);
c0e1f68b 7787 pci_save_state(pdev);
9a799d71 7788
dd4d8ca6 7789 pci_wake_from_d3(pdev, false);
9a799d71 7790
6fabd715 7791 ixgbe_reset(adapter);
88512539 7792 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7793 result = PCI_ERS_RESULT_RECOVERED;
7794 }
7795
7796 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7797 if (err) {
849c4542
ET		 7798 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7799 "failed 0x%0x\n", err);
6fabd715
PWJ		 7800 /* non-fatal, continue */
7801 }
9a799d71 7802
6fabd715 7803 return result;
9a799d71
AK		 7804}
7805
7806/**
7807 * ixgbe_io_resume - called when traffic can start flowing again.
7808 * @pdev: Pointer to PCI device
7809 *
7810 * This callback is called when the error recovery driver tells us that
7811 * its OK to resume normal operation.
7812 */
7813static void ixgbe_io_resume(struct pci_dev *pdev)
7814{
c60fbb00
AD		 7815 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7816 struct net_device *netdev = adapter->netdev;
9a799d71 7817
83c61fa9
GR		 7818#ifdef CONFIG_PCI_IOV
7819 if (adapter->vferr_refcount) {
7820 e_info(drv, "Resuming after VF err\n");
7821 adapter->vferr_refcount--;
7822 return;
7823 }
7824
7825#endif
c7ccde0f
AD		 7826 if (netif_running(netdev))
7827 ixgbe_up(adapter);
9a799d71
AK		 7828
7829 netif_device_attach(netdev);
9a799d71
AK		 7830}
7831
3646f0e5 7832static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7833 .error_detected = ixgbe_io_error_detected,
7834 .slot_reset = ixgbe_io_slot_reset,
7835 .resume = ixgbe_io_resume,
7836};
7837
7838static struct pci_driver ixgbe_driver = {
7839 .name = ixgbe_driver_name,
7840 .id_table = ixgbe_pci_tbl,
7841 .probe = ixgbe_probe,
7842 .remove = __devexit_p(ixgbe_remove),
7843#ifdef CONFIG_PM
7844 .suspend = ixgbe_suspend,
7845 .resume = ixgbe_resume,
7846#endif
7847 .shutdown = ixgbe_shutdown,
7848 .err_handler = &ixgbe_err_handler
7849};
7850
7851/**
7852 * ixgbe_init_module - Driver Registration Routine
7853 *
7854 * ixgbe_init_module is the first routine called when the driver is
7855 * loaded. All it does is register with the PCI subsystem.
7856 **/
7857static int __init ixgbe_init_module(void)
7858{
7859 int ret;
c7689578 7860 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7861 pr_info("%s\n", ixgbe_copyright);
9a799d71 7862
00949167
CS		 7863#ifdef CONFIG_DEBUG_FS
7864 ixgbe_dbg_init();
7865#endif /* CONFIG_DEBUG_FS */
7866
5dd2d332 7867#ifdef CONFIG_IXGBE_DCA
bd0362dd 7868 dca_register_notify(&dca_notifier);
bd0362dd 7869#endif
5dd2d332 7870
9a799d71
AK		 7871 ret = pci_register_driver(&ixgbe_driver);
7872 return ret;
7873}
b4617240 7874
9a799d71
AK		 7875module_init(ixgbe_init_module);
7876
7877/**
7878 * ixgbe_exit_module - Driver Exit Cleanup Routine
7879 *
7880 * ixgbe_exit_module is called just before the driver is removed
7881 * from memory.
7882 **/
7883static void __exit ixgbe_exit_module(void)
7884{
5dd2d332 7885#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7886 dca_unregister_notify(&dca_notifier);
7887#endif
9a799d71 7888 pci_unregister_driver(&ixgbe_driver);
00949167
CS		 7889
7890#ifdef CONFIG_DEBUG_FS
7891 ixgbe_dbg_exit();
7892#endif /* CONFIG_DEBUG_FS */
7893
1a51502b 7894 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7895}
bd0362dd 7896
5dd2d332 7897#ifdef CONFIG_IXGBE_DCA
bd0362dd 7898static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7899 void *p)
bd0362dd
JC		 7900{
7901 int ret_val;
7902
7903 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7904 __ixgbe_notify_dca);
bd0362dd
JC		 7905
7906 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7907}
b453368d 7908
5dd2d332 7909#endif /* CONFIG_IXGBE_DCA */
849c4542 7910
9a799d71
AK		 7911module_exit(ixgbe_exit_module);
7912
7913/* ixgbe_main.c */
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