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CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
21dd5601 79#define DRV_VERSION "4.2.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
67359c3c 82 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 83
f44e751b
DS		 84static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
9a799d71 86static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 92};
93
94/* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
9baa3c34 102static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
9a799d71
AK		 138 /* required last entry */
139 {0, }
140};
141MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
142
5dd2d332 143#ifdef CONFIG_IXGBE_DCA
bd0362dd 144static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 145 void *p);
bd0362dd
JC		 146static struct notifier_block dca_notifier = {
147 .notifier_call = ixgbe_notify_dca,
148 .next = NULL,
149 .priority = 0
150};
151#endif
152
1cdd1ec8
GR		 153#ifdef CONFIG_PCI_IOV
154static unsigned int max_vfs;
155module_param(max_vfs, uint, 0);
e8e9f696 156MODULE_PARM_DESC(max_vfs,
170e8543 157 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 158#endif /* CONFIG_PCI_IOV */
159
8ef78adc
PWJ		 160static unsigned int allow_unsupported_sfp;
161module_param(allow_unsupported_sfp, uint, 0);
162MODULE_PARM_DESC(allow_unsupported_sfp,
163 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
164
b3f4d599 165#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
166static int debug = -1;
167module_param(debug, int, 0);
168MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
169
9a799d71
AK		 170MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
171MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
172MODULE_LICENSE("GPL");
173MODULE_VERSION(DRV_VERSION);
174
780484d8
MR		 175static struct workqueue_struct *ixgbe_wq;
176
14438464
MR		 177static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
b8e82001
JK		 179static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181{
b8e82001
JK		 182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
c0798edf 193 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 194 return -1;
195
c0798edf 196 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
b8e82001
JK		 200 return 0;
201}
202
203static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204{
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224}
225
e027d1ae
JK		 226/**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236{
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 240 return true;
241 default:
242 return false;
243 }
244}
245
246static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248{
f9328bc6 249 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
f9328bc6
DS		 255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
56d1392f 262 /* determine whether to use the parent device */
e027d1ae
JK		 263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
9f0a433c 284 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 302 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311}
312
7086400d
AD		 313static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314{
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 318 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 319}
320
2a1a091c
MR		 321static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322{
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
58cf663f
MR		 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 331}
332
f8e2472f 333static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 334{
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350}
351
f8e2472f
MR		 352/**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366{
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376}
377
14438464
MR		 378static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379{
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388}
389
390u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391{
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402}
403
404#ifdef CONFIG_PCI_IOV
405static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406{
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417}
418#endif /* CONFIG_PCI_IOV */
419
ed19231c
JK		 420void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427}
428
7086400d
AD		 429static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430{
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
52f33af8 433 /* flush memory to make sure state is correct before next watchdog */
4e857c58 434 smp_mb__before_atomic();
7086400d
AD		 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436}
437
dcd79aeb
TI		 438struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441};
442
443static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
ca8dfe25 472 { .name = NULL }
dcd79aeb
TI		 473};
474
475
476/*
477 * ixgbe_regdump - register printout routine
478 */
479static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480{
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
c7689578 543 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 550 pr_err("%-15s", rname);
dcd79aeb 551 for (j = 0; j < 8; j++)
c7689578
JP		 552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
dcd79aeb
TI		 554 }
555
556}
557
558/*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561static void ixgbe_dump(struct ixgbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
729739b7 568 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 583 pr_info("Device Name state "
dcd79aeb 584 "trans_start last_rx\n");
c7689578
JP		 585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
dcd79aeb
TI		 590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 594 pr_info(" Register Name Value\n");
dcd79aeb
TI		 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
e90dd264 602 return;
dcd79aeb
TI		 603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
dcd79aeb
TI		 608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
729739b7 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
c7689578
JP		 662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 672 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 680 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
dcd79aeb
TI		 702 }
703 }
704
705 /* Print RX Rings Summary */
706rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 708 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
c7689578
JP		 711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
e90dd264 717 return;
dcd79aeb
TI		 718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
39ac868a
JH		 721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
39ac868a 732 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
39ac868a
JH		 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
39ac868a
JH		 743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
dcd79aeb 764 */
39ac868a 765
dcd79aeb
TI		 766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
c7689578
JP		 768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
8ad88e37
JH		 771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 774 "<-- Adv Rx Read format\n");
8ad88e37
JH		 775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
c7689578 787 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
c7689578 793 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
9c50c035
ET		 800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
dcd79aeb
TI		 802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
f800326d 806 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 807 }
808 }
809
810 if (i == rx_ring->next_to_use)
c7689578 811 pr_cont(" NTU\n");
dcd79aeb 812 else if (i == rx_ring->next_to_clean)
c7689578 813 pr_cont(" NTC\n");
dcd79aeb 814 else
c7689578 815 pr_cont("\n");
dcd79aeb
TI		 816
817 }
818 }
dcd79aeb
TI		 819}
820
5eba3699
AV		 821static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 829}
830
831static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832{
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 839}
9a799d71 840
49ce9c2c 841/**
e8e26350
PW		 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 850 u8 queue, u8 msix_vector)
9a799d71
AK		 851{
852 u32 ivar, index;
e8e26350
PW		 853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
9a75a1ac
DS		 867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
e8e26350
PW		 869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
9a799d71
AK		 891}
892
fe49f04a 893static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 894 u64 qmask)
fe49f04a
AD		 895{
896 u32 mask;
897
bd508178
AD		 898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
fe49f04a
AD		 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 902 break;
903 case ixgbe_mac_82599EB:
b93a2226 904 case ixgbe_mac_X540:
9a75a1ac
DS		 905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 911 break;
912 default:
913 break;
fe49f04a
AD		 914 }
915}
916
729739b7
AD		 917void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 919{
729739b7
AD		 920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
d3d00239 923 dma_unmap_single(ring->dev,
729739b7
AD		 924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
e5a43549 932 }
729739b7
AD		 933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 937}
938
943561d3 939static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 943 int i;
943561d3 944 u32 data;
c84d324c 945
943561d3
AD		 946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
c84d324c 949
943561d3
AD		 950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
c84d324c 958
943561d3
AD		 959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
c84d324c 961 return;
943561d3
AD		 962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966}
967
968static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969{
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
2afaa00d 973 u8 tc;
943561d3
AD		 974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 982 return;
943561d3 983 }
c84d324c
JF		 984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 987 u32 pxoffrxc;
988
c84d324c
JF		 989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
2afaa00d 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 992 break;
c84d324c 993 default:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 995 }
2afaa00d
PN		 996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
c84d324c
JF		 1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1005
2afaa00d 1006 tc = tx_ring->dcb_tc;
c84d324c
JF		 1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1009 }
26f23d82
YZ		 1010}
1011
c84d324c 1012static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1013{
7d7ce682 1014 return ring->stats.packets;
c84d324c
JF		 1015}
1016
1017static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018{
2a47fa45
JF		 1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
e01c31a5 1027
2a47fa45
JF		 1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037}
1038
1039static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040{
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1044
7d637bcc 1045 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
e90dd264 1059 if (tx_done_old == tx_done && tx_pending)
c84d324c 1060 /* make sure it is true for two checks in a row */
e90dd264
MR		 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1067
e90dd264 1068 return false;
9a799d71
AK		 1069}
1070
c83c6cbd
AD		 1071/**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076{
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1081 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1082 ixgbe_service_event_schedule(adapter);
1083 }
1084}
e01c31a5 1085
9a799d71
AK		 1086/**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1088 * @q_vector: structure containing interrupt and ring information
e01c31a5 1089 * @tx_ring: tx ring to clean
9a799d71 1090 **/
fe49f04a 1091static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1092 struct ixgbe_ring *tx_ring)
9a799d71 1093{
fe49f04a 1094 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1097 unsigned int total_bytes = 0, total_packets = 0;
59224555 1098 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
9a799d71 1103
d3d00239 1104 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1106 i -= tx_ring->count;
12207e49 1107
729739b7 1108 do {
d3d00239
AD		 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
7f83a9e6 1115 /* prevent any other reads prior to eop_desc */
7e63bf49 1116 read_barrier_depends();
7f83a9e6 1117
d3d00239
AD		 1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
8ad494b0 1121
d3d00239
AD		 1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
8ad494b0 1124
091a6246
AD		 1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
fd0db0ed 1129 /* free the skb */
fe1f2a97 1130 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
fd0db0ed
AD		 1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
729739b7 1140 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1141
729739b7
AD		 1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
d3d00239
AD		 1144 tx_buffer++;
1145 tx_desc++;
8ad494b0 1146 i++;
729739b7
AD		 1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
d3d00239 1149 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1151 }
e01c31a5 1152
729739b7
AD		 1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
12207e49 1175
729739b7
AD		 1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
9a799d71 1181 tx_ring->next_to_clean = i;
d3d00239 1182 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1183 tx_ring->stats.bytes += total_bytes;
bd198058 1184 tx_ring->stats.packets += total_packets;
d3d00239 1185 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
b953799e 1188
c84d324c
JF		 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
b953799e 1212 /* schedule immediate reset if we believe we hung */
c83c6cbd 1213 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1214
1215 /* the adapter is about to reset, no point in enabling stuff */
59224555 1216 return true;
b953799e 1217 }
9a799d71 1218
b2d96e0a
AD		 1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
e092be60 1222#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
729739b7
AD		 1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
5b7da515 1234 ++tx_ring->tx_stats.restart_queue;
30eba97a 1235 }
e092be60 1236 }
9a799d71 1237
59224555 1238 return !!budget;
9a799d71
AK		 1239}
1240
5dd2d332 1241#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1242static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
33cf09c9 1244 int cpu)
bd0362dd 1245{
33cf09c9 1246 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1247 u32 txctrl = 0;
bdda1a61 1248 u16 reg_offset;
33cf09c9 1249
9de7605e
MR		 1250 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1251 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1252
33cf09c9
AD		 1253 switch (hw->mac.type) {
1254 case ixgbe_mac_82598EB:
bdda1a61 1255 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1256 break;
1257 case ixgbe_mac_82599EB:
b93a2226 1258 case ixgbe_mac_X540:
bdda1a61
AD		 1259 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1260 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1261 break;
1262 default:
bdda1a61
AD		 1263 /* for unknown hardware do not write register */
1264 return;
bd0362dd 1265 }
bdda1a61
AD		 1266
1267 /*
1268 * We can enable relaxed ordering for reads, but not writes when
1269 * DCA is enabled. This is due to a known issue in some chipsets
1270 * which will cause the DCA tag to be cleared.
1271 */
1272 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1273 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1274 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1275
1276 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1277}
1278
bdda1a61
AD		 1279static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1280 struct ixgbe_ring *rx_ring,
33cf09c9 1281 int cpu)
bd0362dd 1282{
33cf09c9 1283 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1284 u32 rxctrl = 0;
bdda1a61
AD		 1285 u8 reg_idx = rx_ring->reg_idx;
1286
9de7605e
MR		 1287 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1288 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1289
1290 switch (hw->mac.type) {
33cf09c9 1291 case ixgbe_mac_82599EB:
b93a2226 1292 case ixgbe_mac_X540:
bdda1a61 1293 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1294 break;
1295 default:
1296 break;
1297 }
bdda1a61
AD		 1298
1299 /*
1300 * We can enable relaxed ordering for reads, but not writes when
1301 * DCA is enabled. This is due to a known issue in some chipsets
1302 * which will cause the DCA tag to be cleared.
1303 */
1304 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1305 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1306 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1307
1308 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1309}
1310
1311static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1312{
1313 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1314 struct ixgbe_ring *ring;
bd0362dd 1315 int cpu = get_cpu();
bd0362dd 1316
33cf09c9
AD		 1317 if (q_vector->cpu == cpu)
1318 goto out_no_update;
1319
a557928e 1320 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1321 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1322
a557928e 1323 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1324 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1325
1326 q_vector->cpu = cpu;
1327out_no_update:
bd0362dd
JC		 1328 put_cpu();
1329}
1330
1331static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1332{
1333 int i;
1334
e35ec126 1335 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1338 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1339 else
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1341 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1342
49c7ffbe 1343 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1344 adapter->q_vector[i]->cpu = -1;
1345 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1346 }
1347}
1348
1349static int __ixgbe_notify_dca(struct device *dev, void *data)
1350{
c60fbb00 1351 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1352 unsigned long event = *(unsigned long *)data;
1353
2a72c31e 1354 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1355 return 0;
1356
bd0362dd
JC		 1357 switch (event) {
1358 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1359 /* if we're already enabled, don't do it again */
1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1361 break;
652f093f 1362 if (dca_add_requester(dev) == 0) {
96b0e0f6 1363 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1365 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1366 break;
1367 }
1368 /* Fall Through since DCA is disabled. */
1369 case DCA_PROVIDER_REMOVE:
1370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1371 dca_remove_requester(dev);
1372 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1374 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1375 }
1376 break;
1377 }
1378
652f093f 1379 return 0;
bd0362dd 1380}
67a74ee2 1381
bdda1a61 1382#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1383
1384#define IXGBE_RSS_L4_TYPES_MASK \
1385 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1386 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1387 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1388 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1389
8a0da21b
AD		 1390static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1391 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1392 struct sk_buff *skb)
1393{
7edda4b8
FD		 1394 u16 rss_type;
1395
1396 if (!(ring->netdev->features & NETIF_F_RXHASH))
1397 return;
1398
1399 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1400 IXGBE_RXDADV_RSSTYPE_MASK;
1401
1402 if (!rss_type)
1403 return;
1404
1405 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1406 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1407 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1408}
1409
f800326d 1410#ifdef IXGBE_FCOE
ff886dfc
AD		 1411/**
1412 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1413 * @ring: structure containing ring specific data
ff886dfc
AD		 1414 * @rx_desc: advanced rx descriptor
1415 *
1416 * Returns : true if it is FCoE pkt
1417 */
57efd44c 1418static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1419 union ixgbe_adv_rx_desc *rx_desc)
1420{
1421 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1422
57efd44c 1423 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1424 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1425 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1426 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1427}
1428
f800326d 1429#endif /* IXGBE_FCOE */
e59bd25d
AV		 1430/**
1431 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1432 * @ring: structure containing ring specific data
1433 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1434 * @skb: skb currently being received and modified
1435 **/
8a0da21b 1436static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1437 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1438 struct sk_buff *skb)
9a799d71 1439{
3f207800
DS		 1440 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1441 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1442 bool encap_pkt = false;
1443
8a0da21b 1444 skb_checksum_none_assert(skb);
9a799d71 1445
712744be 1446 /* Rx csum disabled */
8a0da21b 1447 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1448 return;
e59bd25d 1449
3f207800
DS		 1450 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1451 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1452 encap_pkt = true;
1453 skb->encapsulation = 1;
3f207800
DS		 1454 }
1455
e59bd25d 1456 /* if IP and error */
f56e0cb1
AD		 1457 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1458 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1459 ring->rx_stats.csum_err++;
9a799d71
AK		 1460 return;
1461 }
e59bd25d 1462
f56e0cb1 1463 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1464 return;
1465
f56e0cb1 1466 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1467 /*
1468 * 82599 errata, UDP frames with a 0 checksum can be marked as
1469 * checksum errors.
1470 */
8a0da21b
AD		 1471 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1472 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1473 return;
1474
8a0da21b 1475 ring->rx_stats.csum_err++;
e59bd25d
AV		 1476 return;
1477 }
1478
9a799d71 1479 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1480 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1481 if (encap_pkt) {
1482 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1483 return;
1484
1485 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1486 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1487 return;
1488 }
1489 /* If we checked the outer header let the stack know */
1490 skb->csum_level = 1;
1491 }
9a799d71
AK		 1492}
1493
f990b79b
AD		 1494static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1495 struct ixgbe_rx_buffer *bi)
1496{
1497 struct page *page = bi->page;
18cb652a 1498 dma_addr_t dma;
f990b79b 1499
f800326d 1500 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1501 if (likely(page))
f990b79b
AD		 1502 return true;
1503
f800326d 1504 /* alloc new page for storage */
18cb652a
AD		 1505 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1506 if (unlikely(!page)) {
1507 rx_ring->rx_stats.alloc_rx_page_failed++;
1508 return false;
f990b79b
AD		 1509 }
1510
f800326d
AD		 1511 /* map page for use */
1512 dma = dma_map_page(rx_ring->dev, page, 0,
1513 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1514
1515 /*
1516 * if mapping failed free memory back to system since
1517 * there isn't much point in holding memory we can't use
1518 */
1519 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1520 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1521
f990b79b
AD		 1522 rx_ring->rx_stats.alloc_rx_page_failed++;
1523 return false;
1524 }
1525
f800326d 1526 bi->dma = dma;
18cb652a 1527 bi->page = page;
afaa9459 1528 bi->page_offset = 0;
f800326d 1529
f990b79b
AD		 1530 return true;
1531}
1532
9a799d71 1533/**
f990b79b 1534 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1535 * @rx_ring: ring to place buffers on
1536 * @cleaned_count: number of buffers to replace
9a799d71 1537 **/
fc77dc3c 1538void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1539{
9a799d71 1540 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1541 struct ixgbe_rx_buffer *bi;
d5f398ed 1542 u16 i = rx_ring->next_to_use;
9a799d71 1543
f800326d
AD		 1544 /* nothing to do */
1545 if (!cleaned_count)
fc77dc3c
AD		 1546 return;
1547
e4f74028 1548 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1549 bi = &rx_ring->rx_buffer_info[i];
1550 i -= rx_ring->count;
9a799d71 1551
f800326d
AD		 1552 do {
1553 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1554 break;
d5f398ed 1555
f800326d
AD		 1556 /*
1557 * Refresh the desc even if buffer_addrs didn't change
1558 * because each write-back erases this info.
1559 */
1560 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1561
f990b79b
AD		 1562 rx_desc++;
1563 bi++;
9a799d71 1564 i++;
f990b79b 1565 if (unlikely(!i)) {
e4f74028 1566 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1567 bi = rx_ring->rx_buffer_info;
1568 i -= rx_ring->count;
1569 }
1570
18cb652a
AD		 1571 /* clear the status bits for the next_to_use descriptor */
1572 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1573
1574 cleaned_count--;
1575 } while (cleaned_count);
7c6e0a43 1576
f990b79b
AD		 1577 i += rx_ring->count;
1578
ad435ec6
AD		 1579 if (rx_ring->next_to_use != i) {
1580 rx_ring->next_to_use = i;
1581
1582 /* update next to alloc since we have filled the ring */
1583 rx_ring->next_to_alloc = i;
1584
1585 /* Force memory writes to complete before letting h/w
1586 * know there are new descriptors to fetch. (Only
1587 * applicable for weak-ordered memory model archs,
1588 * such as IA-64).
1589 */
1590 wmb();
1591 writel(i, rx_ring->tail);
1592 }
9a799d71
AK		 1593}
1594
1d2024f6
AD		 1595static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1596 struct sk_buff *skb)
1597{
f800326d 1598 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1599
1600 /* set gso_size to avoid messing up TCP MSS */
1601 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1602 IXGBE_CB(skb)->append_cnt);
96be80ab 1603 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1604}
1605
1606static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1607 struct sk_buff *skb)
1608{
1609 /* if append_cnt is 0 then frame is not RSC */
1610 if (!IXGBE_CB(skb)->append_cnt)
1611 return;
1612
1613 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1614 rx_ring->rx_stats.rsc_flush++;
1615
1616 ixgbe_set_rsc_gso_size(rx_ring, skb);
1617
1618 /* gso_size is computed using append_cnt so always clear it last */
1619 IXGBE_CB(skb)->append_cnt = 0;
1620}
1621
8a0da21b
AD		 1622/**
1623 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1624 * @rx_ring: rx descriptor ring packet is being transacted on
1625 * @rx_desc: pointer to the EOP Rx descriptor
1626 * @skb: pointer to current skb being populated
f8212f97 1627 *
8a0da21b
AD		 1628 * This function checks the ring, descriptor, and packet information in
1629 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1630 * other fields within the skb.
f8212f97 1631 **/
8a0da21b
AD		 1632static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1633 union ixgbe_adv_rx_desc *rx_desc,
1634 struct sk_buff *skb)
f8212f97 1635{
43e95f11 1636 struct net_device *dev = rx_ring->netdev;
a9763f3c 1637 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1638
8a0da21b
AD		 1639 ixgbe_update_rsc_stats(rx_ring, skb);
1640
1641 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1642
8a0da21b
AD		 1643 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1644
a9763f3c
MR		 1645 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1646 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1647
f646968f 1648 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1649 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1650 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1652 }
1653
8a0da21b 1654 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1655
43e95f11 1656 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1657}
1658
8a0da21b
AD		 1659static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1660 struct sk_buff *skb)
aa80175a 1661{
93f93a44 1662 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1663 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1664 netif_receive_skb(skb);
8a0da21b 1665 else
856f606e 1666 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1667}
43634e82 1668
f800326d
AD		 1669/**
1670 * ixgbe_is_non_eop - process handling of non-EOP buffers
1671 * @rx_ring: Rx ring being processed
1672 * @rx_desc: Rx descriptor for current buffer
1673 * @skb: Current socket buffer containing buffer in progress
1674 *
1675 * This function updates next to clean. If the buffer is an EOP buffer
1676 * this function exits returning false, otherwise it will place the
1677 * sk_buff in the next buffer to be chained and return true indicating
1678 * that this is in fact a non-EOP buffer.
1679 **/
1680static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1681 union ixgbe_adv_rx_desc *rx_desc,
1682 struct sk_buff *skb)
1683{
1684 u32 ntc = rx_ring->next_to_clean + 1;
1685
1686 /* fetch, update, and store next to clean */
1687 ntc = (ntc < rx_ring->count) ? ntc : 0;
1688 rx_ring->next_to_clean = ntc;
1689
1690 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1691
5a02cbd1
AD		 1692 /* update RSC append count if present */
1693 if (ring_is_rsc_enabled(rx_ring)) {
1694 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1695 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1696
1697 if (unlikely(rsc_enabled)) {
1698 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1699
1700 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1701 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1702
5a02cbd1
AD		 1703 /* update ntc based on RSC value */
1704 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1705 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1706 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1707 }
f800326d
AD		 1708 }
1709
5a02cbd1
AD		 1710 /* if we are the last buffer then there is nothing else to do */
1711 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1712 return false;
1713
f800326d
AD		 1714 /* place skb in next buffer to be received */
1715 rx_ring->rx_buffer_info[ntc].skb = skb;
1716 rx_ring->rx_stats.non_eop_descs++;
1717
1718 return true;
1719}
1720
19861ce2
AD		 1721/**
1722 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1723 * @rx_ring: rx descriptor ring packet is being transacted on
1724 * @skb: pointer to current skb being adjusted
1725 *
1726 * This function is an ixgbe specific version of __pskb_pull_tail. The
1727 * main difference between this version and the original function is that
1728 * this function can make several assumptions about the state of things
1729 * that allow for significant optimizations versus the standard function.
1730 * As a result we can do things like drop a frag and maintain an accurate
1731 * truesize for the skb.
1732 */
1733static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1734 struct sk_buff *skb)
1735{
1736 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1737 unsigned char *va;
1738 unsigned int pull_len;
1739
1740 /*
1741 * it is valid to use page_address instead of kmap since we are
1742 * working with pages allocated out of the lomem pool per
1743 * alloc_page(GFP_ATOMIC)
1744 */
1745 va = skb_frag_address(frag);
1746
1747 /*
1748 * we need the header to contain the greater of either ETH_HLEN or
1749 * 60 bytes if the skb->len is less than 60 for skb_pad.
1750 */
8496e338 1751 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1752
1753 /* align pull length to size of long to optimize memcpy performance */
1754 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1755
1756 /* update all of the pointers */
1757 skb_frag_size_sub(frag, pull_len);
1758 frag->page_offset += pull_len;
1759 skb->data_len -= pull_len;
1760 skb->tail += pull_len;
19861ce2
AD		 1761}
1762
42073d91
AD		 1763/**
1764 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1765 * @rx_ring: rx descriptor ring packet is being transacted on
1766 * @skb: pointer to current skb being updated
1767 *
1768 * This function provides a basic DMA sync up for the first fragment of an
1769 * skb. The reason for doing this is that the first fragment cannot be
1770 * unmapped until we have reached the end of packet descriptor for a buffer
1771 * chain.
1772 */
1773static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1774 struct sk_buff *skb)
1775{
1776 /* if the page was released unmap it, else just sync our portion */
1777 if (unlikely(IXGBE_CB(skb)->page_released)) {
1778 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1779 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1780 IXGBE_CB(skb)->page_released = false;
1781 } else {
1782 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1783
1784 dma_sync_single_range_for_cpu(rx_ring->dev,
1785 IXGBE_CB(skb)->dma,
1786 frag->page_offset,
1787 ixgbe_rx_bufsz(rx_ring),
1788 DMA_FROM_DEVICE);
1789 }
1790 IXGBE_CB(skb)->dma = 0;
1791}
1792
f800326d
AD		 1793/**
1794 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1795 * @rx_ring: rx descriptor ring packet is being transacted on
1796 * @rx_desc: pointer to the EOP Rx descriptor
1797 * @skb: pointer to current skb being fixed
1798 *
1799 * Check for corrupted packet headers caused by senders on the local L2
1800 * embedded NIC switch not setting up their Tx Descriptors right. These
1801 * should be very rare.
1802 *
1803 * Also address the case where we are pulling data in on pages only
1804 * and as such no data is present in the skb header.
1805 *
1806 * In addition if skb is not at least 60 bytes we need to pad it so that
1807 * it is large enough to qualify as a valid Ethernet frame.
1808 *
1809 * Returns true if an error was encountered and skb was freed.
1810 **/
1811static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1812 union ixgbe_adv_rx_desc *rx_desc,
1813 struct sk_buff *skb)
1814{
f800326d 1815 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1816
1817 /* verify that the packet does not have any known errors */
1818 if (unlikely(ixgbe_test_staterr(rx_desc,
1819 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1820 !(netdev->features & NETIF_F_RXALL))) {
1821 dev_kfree_skb_any(skb);
1822 return true;
1823 }
1824
19861ce2 1825 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1826 if (skb_is_nonlinear(skb))
1827 ixgbe_pull_tail(rx_ring, skb);
f800326d 1828
57efd44c
AD		 1829#ifdef IXGBE_FCOE
1830 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1831 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1832 return false;
1833
1834#endif
a94d9e22
AD		 1835 /* if eth_skb_pad returns an error the skb was freed */
1836 if (eth_skb_pad(skb))
1837 return true;
f800326d
AD		 1838
1839 return false;
1840}
1841
f800326d
AD		 1842/**
1843 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1844 * @rx_ring: rx descriptor ring to store buffers on
1845 * @old_buff: donor buffer to have page reused
1846 *
0549ae20 1847 * Synchronizes page for reuse by the adapter
f800326d
AD		 1848 **/
1849static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1850 struct ixgbe_rx_buffer *old_buff)
1851{
1852 struct ixgbe_rx_buffer *new_buff;
1853 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1854
1855 new_buff = &rx_ring->rx_buffer_info[nta];
1856
1857 /* update, and store next to alloc */
1858 nta++;
1859 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1860
1861 /* transfer page from old buffer to new buffer */
18cb652a 1862 *new_buff = *old_buff;
f800326d
AD		 1863
1864 /* sync the buffer for use by the device */
1865 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1866 new_buff->page_offset,
1867 ixgbe_rx_bufsz(rx_ring),
f800326d 1868 DMA_FROM_DEVICE);
f800326d
AD		 1869}
1870
18cb652a
AD		 1871static inline bool ixgbe_page_is_reserved(struct page *page)
1872{
2f064f34 1873 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1874}
1875
f800326d
AD		 1876/**
1877 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1878 * @rx_ring: rx descriptor ring to transact packets on
1879 * @rx_buffer: buffer containing page to add
1880 * @rx_desc: descriptor containing length of buffer written by hardware
1881 * @skb: sk_buff to place the data into
1882 *
0549ae20
AD		 1883 * This function will add the data contained in rx_buffer->page to the skb.
1884 * This is done either through a direct copy if the data in the buffer is
1885 * less than the skb header size, otherwise it will just attach the page as
1886 * a frag to the skb.
1887 *
1888 * The function will then update the page offset if necessary and return
1889 * true if the buffer can be reused by the adapter.
f800326d 1890 **/
0549ae20 1891static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1892 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1893 union ixgbe_adv_rx_desc *rx_desc,
1894 struct sk_buff *skb)
f800326d 1895{
0549ae20
AD		 1896 struct page *page = rx_buffer->page;
1897 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1898#if (PAGE_SIZE < 8192)
0549ae20 1899 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1900#else
1901 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1902 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1903 ixgbe_rx_bufsz(rx_ring);
1904#endif
0549ae20 1905
cf3fe7ac
AD		 1906 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1907 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1908
1909 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1910
18cb652a
AD		 1911 /* page is not reserved, we can reuse buffer as-is */
1912 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1913 return true;
1914
1915 /* this page cannot be reused so discard it */
18cb652a 1916 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1917 return false;
1918 }
1919
0549ae20
AD		 1920 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1921 rx_buffer->page_offset, size, truesize);
1922
09816fbe 1923 /* avoid re-using remote pages */
18cb652a 1924 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1925 return false;
1926
1927#if (PAGE_SIZE < 8192)
1928 /* if we are only owner of page we can reuse it */
1929 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1930 return false;
1931
1932 /* flip page offset to other buffer */
1933 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1934#else
1935 /* move offset up to the next cache line */
1936 rx_buffer->page_offset += truesize;
1937
1938 if (rx_buffer->page_offset > last_offset)
1939 return false;
09816fbe 1940#endif
0549ae20 1941
18cb652a
AD		 1942 /* Even if we own the page, we are not allowed to use atomic_set()
1943 * This would break get_page_unless_zero() users.
1944 */
fe896d18 1945 page_ref_inc(page);
18cb652a 1946
0549ae20 1947 return true;
f800326d
AD		 1948}
1949
18806c9e
AD		 1950static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1951 union ixgbe_adv_rx_desc *rx_desc)
1952{
1953 struct ixgbe_rx_buffer *rx_buffer;
1954 struct sk_buff *skb;
1955 struct page *page;
1956
1957 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1958 page = rx_buffer->page;
1959 prefetchw(page);
1960
1961 skb = rx_buffer->skb;
1962
1963 if (likely(!skb)) {
1964 void *page_addr = page_address(page) +
1965 rx_buffer->page_offset;
1966
1967 /* prefetch first cache line of first page */
1968 prefetch(page_addr);
1969#if L1_CACHE_BYTES < 128
1970 prefetch(page_addr + L1_CACHE_BYTES);
1971#endif
1972
1973 /* allocate a skb to store the frags */
67fd893e
AD		 1974 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1975 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1976 if (unlikely(!skb)) {
1977 rx_ring->rx_stats.alloc_rx_buff_failed++;
1978 return NULL;
1979 }
1980
1981 /*
1982 * we will be copying header into skb->data in
1983 * pskb_may_pull so it is in our interest to prefetch
1984 * it now to avoid a possible cache miss
1985 */
1986 prefetchw(skb->data);
1987
1988 /*
1989 * Delay unmapping of the first packet. It carries the
1990 * header information, HW may still access the header
1991 * after the writeback. Only unmap it when EOP is
1992 * reached
1993 */
1994 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1995 goto dma_sync;
1996
1997 IXGBE_CB(skb)->dma = rx_buffer->dma;
1998 } else {
1999 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2000 ixgbe_dma_sync_frag(rx_ring, skb);
2001
2002dma_sync:
2003 /* we are reusing so sync this buffer for CPU use */
2004 dma_sync_single_range_for_cpu(rx_ring->dev,
2005 rx_buffer->dma,
2006 rx_buffer->page_offset,
2007 ixgbe_rx_bufsz(rx_ring),
2008 DMA_FROM_DEVICE);
18cb652a
AD		 2009
2010 rx_buffer->skb = NULL;
18806c9e
AD		 2011 }
2012
2013 /* pull page into skb */
2014 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2015 /* hand second half of page back to the ring */
2016 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2017 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2018 /* the page has been released from the ring */
2019 IXGBE_CB(skb)->page_released = true;
2020 } else {
2021 /* we are not reusing the buffer so unmap it */
2022 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2023 ixgbe_rx_pg_size(rx_ring),
2024 DMA_FROM_DEVICE);
2025 }
2026
2027 /* clear contents of buffer_info */
18806c9e
AD		 2028 rx_buffer->page = NULL;
2029
2030 return skb;
f800326d
AD		 2031}
2032
2033/**
2034 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2035 * @q_vector: structure containing interrupt and ring information
2036 * @rx_ring: rx descriptor ring to transact packets on
2037 * @budget: Total limit on number of packets to process
2038 *
2039 * This function provides a "bounce buffer" approach to Rx interrupt
2040 * processing. The advantage to this is that on systems that have
2041 * expensive overhead for IOMMU access this provides a means of avoiding
2042 * it by maintaining the mapping of the page to the syste.
2043 *
5a85e737 2044 * Returns amount of work completed
f800326d 2045 **/
5a85e737 2046static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2047 struct ixgbe_ring *rx_ring,
f4de00ed 2048 const int budget)
9a799d71 2049{
d2f4fbe2 2050 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2051#ifdef IXGBE_FCOE
f800326d 2052 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2053 int ddp_bytes;
2054 unsigned int mss = 0;
3d8fd385 2055#endif /* IXGBE_FCOE */
f800326d 2056 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2057
fdabfc8a 2058 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2059 union ixgbe_adv_rx_desc *rx_desc;
2060 struct sk_buff *skb;
f800326d
AD		 2061
2062 /* return some buffers to hardware, one at a time is too slow */
2063 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2064 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2065 cleaned_count = 0;
2066 }
2067
18806c9e 2068 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2069
124b74c1 2070 if (!rx_desc->wb.upper.status_error)
f800326d 2071 break;
9a799d71 2072
124b74c1 2073 /* This memory barrier is needed to keep us from reading
f800326d 2074 * any other fields out of the rx_desc until we know the
124b74c1 2075 * descriptor has been written back
f800326d 2076 */
124b74c1 2077 dma_rmb();
9a799d71 2078
18806c9e
AD		 2079 /* retrieve a buffer from the ring */
2080 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2081
18806c9e
AD		 2082 /* exit if we failed to retrieve a buffer */
2083 if (!skb)
2084 break;
9a799d71 2085
9a799d71 2086 cleaned_count++;
f8212f97 2087
f800326d
AD		 2088 /* place incomplete frames back on ring for completion */
2089 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2090 continue;
c267fc16 2091
f800326d
AD		 2092 /* verify the packet layout is correct */
2093 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2094 continue;
9a799d71 2095
d2f4fbe2
AV		 2096 /* probably a little skewed due to removing CRC */
2097 total_rx_bytes += skb->len;
d2f4fbe2 2098
8a0da21b
AD		 2099 /* populate checksum, timestamp, VLAN, and protocol */
2100 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2101
332d4a7d
YZ		 2102#ifdef IXGBE_FCOE
2103 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2104 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2105 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2106 /* include DDPed FCoE data */
2107 if (ddp_bytes > 0) {
2108 if (!mss) {
2109 mss = rx_ring->netdev->mtu -
2110 sizeof(struct fcoe_hdr) -
2111 sizeof(struct fc_frame_header) -
2112 sizeof(struct fcoe_crc_eof);
2113 if (mss > 512)
2114 mss &= ~511;
2115 }
2116 total_rx_bytes += ddp_bytes;
2117 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2118 mss);
2119 }
63d635b2
AD		 2120 if (!ddp_bytes) {
2121 dev_kfree_skb_any(skb);
f800326d 2122 continue;
63d635b2 2123 }
3d8fd385 2124 }
f800326d 2125
332d4a7d 2126#endif /* IXGBE_FCOE */
8a0da21b 2127 ixgbe_rx_skb(q_vector, skb);
9a799d71 2128
f800326d 2129 /* update budget accounting */
f4de00ed 2130 total_rx_packets++;
fdabfc8a 2131 }
9a799d71 2132
c267fc16
AD		 2133 u64_stats_update_begin(&rx_ring->syncp);
2134 rx_ring->stats.packets += total_rx_packets;
2135 rx_ring->stats.bytes += total_rx_bytes;
2136 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2137 q_vector->rx.total_packets += total_rx_packets;
2138 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2139
5a85e737 2140 return total_rx_packets;
9a799d71
AK		 2141}
2142
e0d1095a 2143#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2144/* must be called with local_bh_disable()d */
2145static int ixgbe_low_latency_recv(struct napi_struct *napi)
2146{
2147 struct ixgbe_q_vector *q_vector =
2148 container_of(napi, struct ixgbe_q_vector, napi);
2149 struct ixgbe_adapter *adapter = q_vector->adapter;
2150 struct ixgbe_ring *ring;
2151 int found = 0;
2152
2153 if (test_bit(__IXGBE_DOWN, &adapter->state))
2154 return LL_FLUSH_FAILED;
2155
2156 if (!ixgbe_qv_lock_poll(q_vector))
2157 return LL_FLUSH_BUSY;
2158
2159 ixgbe_for_each_ring(ring, q_vector->rx) {
2160 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2161#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2162 if (found)
2163 ring->stats.cleaned += found;
2164 else
2165 ring->stats.misses++;
2166#endif
5a85e737
ET		 2167 if (found)
2168 break;
2169 }
2170
2171 ixgbe_qv_unlock_poll(q_vector);
2172
2173 return found;
2174}
e0d1095a 2175#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2176
9a799d71
AK		 2177/**
2178 * ixgbe_configure_msix - Configure MSI-X hardware
2179 * @adapter: board private structure
2180 *
2181 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2182 * interrupts.
2183 **/
2184static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2185{
021230d4 2186 struct ixgbe_q_vector *q_vector;
49c7ffbe 2187 int v_idx;
021230d4 2188 u32 mask;
9a799d71 2189
8e34d1aa
AD		 2190 /* Populate MSIX to EITR Select */
2191 if (adapter->num_vfs > 32) {
2192 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2194 }
2195
4df10466
JB		 2196 /*
2197 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2198 * corresponding register.
2199 */
49c7ffbe 2200 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2201 struct ixgbe_ring *ring;
7a921c93 2202 q_vector = adapter->q_vector[v_idx];
021230d4 2203
a557928e 2204 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2205 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2206
a557928e 2207 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2208 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2209
fe49f04a 2210 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2211 }
2212
bd508178
AD		 2213 switch (adapter->hw.mac.type) {
2214 case ixgbe_mac_82598EB:
e8e26350 2215 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2216 v_idx);
bd508178
AD		 2217 break;
2218 case ixgbe_mac_82599EB:
b93a2226 2219 case ixgbe_mac_X540:
9a75a1ac
DS		 2220 case ixgbe_mac_X550:
2221 case ixgbe_mac_X550EM_x:
e8e26350 2222 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2223 break;
bd508178
AD		 2224 default:
2225 break;
2226 }
021230d4
AV		 2227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2228
41fb9248 2229 /* set up to autoclear timer, and the vectors */
021230d4 2230 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2231 mask &= ~(IXGBE_EIMS_OTHER |
2232 IXGBE_EIMS_MAILBOX |
2233 IXGBE_EIMS_LSC);
2234
021230d4 2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2236}
2237
f494e8fa
AV		 2238enum latency_range {
2239 lowest_latency = 0,
2240 low_latency = 1,
2241 bulk_latency = 2,
2242 latency_invalid = 255
2243};
2244
2245/**
2246 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2247 * @q_vector: structure containing interrupt and ring information
2248 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2249 *
2250 * Stores a new ITR value based on packets and byte
2251 * counts during the last interrupt. The advantage of per interrupt
2252 * computation is faster updates and more accurate ITR for the current
2253 * traffic pattern. Constants in this function were computed
2254 * based on theoretical maximum wire speed and thresholds were set based
2255 * on testing data as well as attempting to minimize response time
2256 * while increasing bulk throughput.
2257 * this functionality is controlled by the InterruptThrottleRate module
2258 * parameter (see ixgbe_param.c)
2259 **/
bd198058
AD		 2260static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2261 struct ixgbe_ring_container *ring_container)
f494e8fa 2262{
bd198058
AD		 2263 int bytes = ring_container->total_bytes;
2264 int packets = ring_container->total_packets;
2265 u32 timepassed_us;
621bd70e 2266 u64 bytes_perint;
bd198058 2267 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2268
2269 if (packets == 0)
bd198058 2270 return;
f494e8fa
AV		 2271
2272 /* simple throttlerate management
621bd70e
AD		 2273 * 0-10MB/s lowest (100000 ints/s)
2274 * 10-20MB/s low (20000 ints/s)
8ac34f10 2275 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2276 */
2277 /* what was last interrupt timeslice? */
d5bf4f67 2278 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2279 if (timepassed_us == 0)
2280 return;
2281
f494e8fa
AV		 2282 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2283
2284 switch (itr_setting) {
2285 case lowest_latency:
621bd70e 2286 if (bytes_perint > 10)
bd198058 2287 itr_setting = low_latency;
f494e8fa
AV		 2288 break;
2289 case low_latency:
621bd70e 2290 if (bytes_perint > 20)
bd198058 2291 itr_setting = bulk_latency;
621bd70e 2292 else if (bytes_perint <= 10)
bd198058 2293 itr_setting = lowest_latency;
f494e8fa
AV		 2294 break;
2295 case bulk_latency:
621bd70e 2296 if (bytes_perint <= 20)
bd198058 2297 itr_setting = low_latency;
f494e8fa
AV		 2298 break;
2299 }
2300
bd198058
AD		 2301 /* clear work counters since we have the values we need */
2302 ring_container->total_bytes = 0;
2303 ring_container->total_packets = 0;
2304
2305 /* write updated itr to ring container */
2306 ring_container->itr = itr_setting;
f494e8fa
AV		 2307}
2308
509ee935
JB		 2309/**
2310 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2311 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2312 *
2313 * This function is made to be called by ethtool and by the driver
2314 * when it needs to update EITR registers at runtime. Hardware
2315 * specific quirks/differences are taken care of here.
2316 */
fe49f04a 2317void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2318{
fe49f04a 2319 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2320 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2321 int v_idx = q_vector->v_idx;
5d967eb7 2322 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2323
bd508178
AD		 2324 switch (adapter->hw.mac.type) {
2325 case ixgbe_mac_82598EB:
509ee935
JB		 2326 /* must write high and low 16 bits to reset counter */
2327 itr_reg |= (itr_reg << 16);
bd508178
AD		 2328 break;
2329 case ixgbe_mac_82599EB:
b93a2226 2330 case ixgbe_mac_X540:
9a75a1ac
DS		 2331 case ixgbe_mac_X550:
2332 case ixgbe_mac_X550EM_x:
509ee935
JB		 2333 /*
2334 * set the WDIS bit to not clear the timer bits and cause an
2335 * immediate assertion of the interrupt
2336 */
2337 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2338 break;
2339 default:
2340 break;
509ee935
JB		 2341 }
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2343}
2344
bd198058 2345static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2346{
d5bf4f67 2347 u32 new_itr = q_vector->itr;
bd198058 2348 u8 current_itr;
f494e8fa 2349
bd198058
AD		 2350 ixgbe_update_itr(q_vector, &q_vector->tx);
2351 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2352
08c8833b 2353 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2354
2355 switch (current_itr) {
2356 /* counts and packets in update_itr are dependent on these numbers */
2357 case lowest_latency:
d5bf4f67 2358 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2359 break;
2360 case low_latency:
d5bf4f67 2361 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2362 break;
2363 case bulk_latency:
8ac34f10 2364 new_itr = IXGBE_12K_ITR;
f494e8fa 2365 break;
bd198058
AD		 2366 default:
2367 break;
f494e8fa
AV		 2368 }
2369
d5bf4f67 2370 if (new_itr != q_vector->itr) {
fe49f04a 2371 /* do an exponential smoothing */
d5bf4f67
ET		 2372 new_itr = (10 * new_itr * q_vector->itr) /
2373 ((9 * new_itr) + q_vector->itr);
509ee935 2374
bd198058 2375 /* save the algorithm value here */
5d967eb7 2376 q_vector->itr = new_itr;
fe49f04a
AD		 2377
2378 ixgbe_write_eitr(q_vector);
f494e8fa 2379 }
f494e8fa
AV		 2380}
2381
119fc60a 2382/**
de88eeeb 2383 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2384 * @adapter: pointer to adapter
119fc60a 2385 **/
f0f9778d 2386static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2387{
119fc60a
MC		 2388 struct ixgbe_hw *hw = &adapter->hw;
2389 u32 eicr = adapter->interrupt_event;
2390
f0f9778d 2391 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2392 return;
2393
f0f9778d
AD		 2394 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2395 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2396 return;
2397
2398 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2399
7ca647bd 2400 switch (hw->device_id) {
f0f9778d
AD		 2401 case IXGBE_DEV_ID_82599_T3_LOM:
2402 /*
2403 * Since the warning interrupt is for both ports
2404 * we don't have to check if:
2405 * - This interrupt wasn't for our port.
2406 * - We may have missed the interrupt so always have to
2407 * check if we got a LSC
2408 */
9a900eca 2409 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2410 !(eicr & IXGBE_EICR_LSC))
2411 return;
2412
2413 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2414 u32 speed;
f0f9778d 2415 bool link_up = false;
7ca647bd 2416
3d292265 2417 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2418
f0f9778d
AD		 2419 if (link_up)
2420 return;
2421 }
2422
2423 /* Check if this is not due to overtemp */
2424 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2425 return;
2426
2427 break;
7ca647bd 2428 default:
597f22d6
DS		 2429 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2430 return;
9a900eca 2431 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2432 return;
7ca647bd 2433 break;
119fc60a 2434 }
f44e751b 2435 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2436
2437 adapter->interrupt_event = 0;
119fc60a
MC		 2438}
2439
0befdb3e
JB		 2440static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2441{
2442 struct ixgbe_hw *hw = &adapter->hw;
2443
2444 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2445 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2446 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2447 /* write to clear the interrupt */
9a900eca 2448 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2449 }
2450}
cf8280ee 2451
4f51bf70
JK		 2452static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2453{
9a900eca
DS		 2454 struct ixgbe_hw *hw = &adapter->hw;
2455
4f51bf70
JK		 2456 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2457 return;
2458
2459 switch (adapter->hw.mac.type) {
2460 case ixgbe_mac_82599EB:
2461 /*
2462 * Need to check link state so complete overtemp check
2463 * on service task
2464 */
9a900eca
DS		 2465 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2466 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2467 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2468 adapter->interrupt_event = eicr;
2469 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2470 ixgbe_service_event_schedule(adapter);
2471 return;
2472 }
2473 return;
2474 case ixgbe_mac_X540:
2475 if (!(eicr & IXGBE_EICR_TS))
2476 return;
2477 break;
2478 default:
2479 return;
2480 }
2481
f44e751b 2482 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2483}
2484
45788d2a
DS		 2485static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2486{
2487 switch (hw->mac.type) {
2488 case ixgbe_mac_82598EB:
2489 if (hw->phy.type == ixgbe_phy_nl)
2490 return true;
2491 return false;
2492 case ixgbe_mac_82599EB:
2493 case ixgbe_mac_X550EM_x:
2494 switch (hw->mac.ops.get_media_type(hw)) {
2495 case ixgbe_media_type_fiber:
2496 case ixgbe_media_type_fiber_qsfp:
2497 return true;
2498 default:
2499 return false;
2500 }
2501 default:
2502 return false;
2503 }
2504}
2505
e8e26350
PW		 2506static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507{
2508 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2509 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2510
4ccc650c
DS		 2511 if (!ixgbe_is_sfp(hw))
2512 return;
2513
2514 /* Later MAC's use different SDP */
2515 if (hw->mac.type >= ixgbe_mac_X540)
2516 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2517
2518 if (eicr & eicr_mask) {
73c4b7cd 2519 /* Clear the interrupt */
4ccc650c 2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2523 adapter->sfp_poll_time = 0;
7086400d
AD		 2524 ixgbe_service_event_schedule(adapter);
2525 }
73c4b7cd
AD		 2526 }
2527
4ccc650c
DS		 2528 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2529 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2530 /* Clear the interrupt */
9a900eca 2531 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2532 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2534 ixgbe_service_event_schedule(adapter);
2535 }
e8e26350
PW		 2536 }
2537}
2538
cf8280ee
JB		 2539static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2540{
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
2543 adapter->lsc_int++;
2544 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2545 adapter->link_check_timeout = jiffies;
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2548 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2549 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2550 }
2551}
2552
fe49f04a
AD		 2553static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2554 u64 qmask)
2555{
2556 u32 mask;
bd508178 2557 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2558
bd508178
AD		 2559 switch (hw->mac.type) {
2560 case ixgbe_mac_82598EB:
fe49f04a 2561 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2563 break;
2564 case ixgbe_mac_82599EB:
b93a2226 2565 case ixgbe_mac_X540:
9a75a1ac
DS		 2566 case ixgbe_mac_X550:
2567 case ixgbe_mac_X550EM_x:
fe49f04a 2568 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2571 mask = (qmask >> 32);
bd508178
AD		 2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2574 break;
2575 default:
2576 break;
fe49f04a
AD		 2577 }
2578 /* skip the flush */
2579}
2580
2581static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2582 u64 qmask)
fe49f04a
AD		 2583{
2584 u32 mask;
bd508178 2585 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2586
bd508178
AD		 2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
fe49f04a 2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
b93a2226 2593 case ixgbe_mac_X540:
9a75a1ac
DS		 2594 case ixgbe_mac_X550:
2595 case ixgbe_mac_X550EM_x:
fe49f04a 2596 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2599 mask = (qmask >> 32);
bd508178
AD		 2600 if (mask)
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2602 break;
2603 default:
2604 break;
fe49f04a
AD		 2605 }
2606 /* skip the flush */
2607}
2608
021230d4 2609/**
2c4af694
AD		 2610 * ixgbe_irq_enable - Enable default interrupt generation settings
2611 * @adapter: board private structure
021230d4 2612 **/
2c4af694
AD		 2613static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2614 bool flush)
9a799d71 2615{
9a900eca 2616 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2617 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2618
2c4af694
AD		 2619 /* don't reenable LSC while waiting for link */
2620 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2621 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2622
2c4af694 2623 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82599EB:
9a900eca 2626 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2627 break;
2628 case ixgbe_mac_X540:
9a75a1ac
DS		 2629 case ixgbe_mac_X550:
2630 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2631 mask |= IXGBE_EIMS_TS;
2632 break;
2633 default:
2634 break;
2635 }
2c4af694 2636 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2638 switch (adapter->hw.mac.type) {
2639 case ixgbe_mac_82599EB:
9a900eca
DS		 2640 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2641 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2642 /* fall through */
858bc081 2643 case ixgbe_mac_X540:
9a75a1ac
DS		 2644 case ixgbe_mac_X550:
2645 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2646 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2647 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2648 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2649 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2650 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2651 mask |= IXGBE_EIMS_MAILBOX;
2652 break;
2653 default:
2654 break;
9a799d71 2655 }
db0677fa 2656
2c4af694
AD		 2657 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2658 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2659 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2660
2c4af694
AD		 2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2662 if (queues)
2663 ixgbe_irq_enable_queues(adapter, ~0);
2664 if (flush)
2665 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2666}
2667
2c4af694 2668static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2669{
a65151ba 2670 struct ixgbe_adapter *adapter = data;
9a799d71 2671 struct ixgbe_hw *hw = &adapter->hw;
54037505 2672 u32 eicr;
91281fd3 2673
54037505
DS		 2674 /*
2675 * Workaround for Silicon errata. Use clear-by-write instead
2676 * of clear-by-read. Reading with EICS will return the
2677 * interrupt causes without clearing, which later be done
2678 * with the write to EICR.
2679 */
2680 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2681
2682 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2683 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2684 * the bits are high when ixgbe_msix_other is called. There is a race
2685 * condition otherwise which results in possible performance loss
2686 * especially if the ixgbe_msix_other interrupt is triggering
2687 * consistently (as it would when PPS is turned on for the X540 device)
2688 */
2689 eicr &= 0xFFFF0000;
2690
54037505 2691 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2692
cf8280ee
JB		 2693 if (eicr & IXGBE_EICR_LSC)
2694 ixgbe_check_lsc(adapter);
f0848276 2695
1cdd1ec8
GR		 2696 if (eicr & IXGBE_EICR_MAILBOX)
2697 ixgbe_msg_task(adapter);
efe3d3c8 2698
bd508178
AD		 2699 switch (hw->mac.type) {
2700 case ixgbe_mac_82599EB:
b93a2226 2701 case ixgbe_mac_X540:
9a75a1ac
DS		 2702 case ixgbe_mac_X550:
2703 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2704 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2705 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2706 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2707 ixgbe_service_event_schedule(adapter);
2708 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2709 IXGBE_EICR_GPI_SDP0_X540);
2710 }
d773ce2d
DS		 2711 if (eicr & IXGBE_EICR_ECC) {
2712 e_info(link, "Received ECC Err, initiating reset\n");
2713 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2714 ixgbe_service_event_schedule(adapter);
2715 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2716 }
c4cf55e5
PWJ		 2717 /* Handle Flow Director Full threshold interrupt */
2718 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2719 int reinit_count = 0;
c4cf55e5 2720 int i;
c4cf55e5 2721 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2722 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2723 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2724 &ring->state))
2725 reinit_count++;
2726 }
2727 if (reinit_count) {
2728 /* no more flow director interrupts until after init */
2729 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2730 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2731 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2732 }
2733 }
f0f9778d 2734 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2735 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2736 break;
2737 default:
2738 break;
c4cf55e5 2739 }
f0848276 2740
bd508178 2741 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2742
db0677fa 2743 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2744 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2745
7086400d 2746 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2747 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2748 ixgbe_irq_enable(adapter, false, false);
f0848276 2749
9a799d71 2750 return IRQ_HANDLED;
f0848276 2751}
91281fd3 2752
4ff7fb12 2753static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2754{
021230d4 2755 struct ixgbe_q_vector *q_vector = data;
91281fd3 2756
9b471446 2757 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2758
4ff7fb12 2759 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2760 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2761
9a799d71 2762 return IRQ_HANDLED;
91281fd3
AD		 2763}
2764
eb01b975
AD		 2765/**
2766 * ixgbe_poll - NAPI Rx polling callback
2767 * @napi: structure for representing this polling device
2768 * @budget: how many packets driver is allowed to clean
2769 *
2770 * This function is used for legacy and MSI, NAPI mode
2771 **/
8af3c33f 2772int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2773{
2774 struct ixgbe_q_vector *q_vector =
2775 container_of(napi, struct ixgbe_q_vector, napi);
2776 struct ixgbe_adapter *adapter = q_vector->adapter;
2777 struct ixgbe_ring *ring;
32b3e08f 2778 int per_ring_budget, work_done = 0;
eb01b975
AD		 2779 bool clean_complete = true;
2780
2781#ifdef CONFIG_IXGBE_DCA
2782 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2783 ixgbe_update_dca(q_vector);
2784#endif
2785
2786 ixgbe_for_each_ring(ring, q_vector->tx)
2787 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2788
5d6002b7
AD		 2789 /* Exit if we are called by netpoll or busy polling is active */
2790 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2791 return budget;
2792
eb01b975
AD		 2793 /* attempt to distribute budget to each queue fairly, but don't allow
2794 * the budget to go below 1 because we'll exit polling */
2795 if (q_vector->rx.count > 1)
2796 per_ring_budget = max(budget/q_vector->rx.count, 1);
2797 else
2798 per_ring_budget = budget;
2799
32b3e08f
JB		 2800 ixgbe_for_each_ring(ring, q_vector->rx) {
2801 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2802 per_ring_budget);
2803
2804 work_done += cleaned;
2805 clean_complete &= (cleaned < per_ring_budget);
2806 }
eb01b975 2807
5a85e737 2808 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2809 /* If all work not completed, return budget and keep polling */
2810 if (!clean_complete)
2811 return budget;
2812
2813 /* all work done, exit the polling mode */
32b3e08f 2814 napi_complete_done(napi, work_done);
eb01b975
AD		 2815 if (adapter->rx_itr_setting & 1)
2816 ixgbe_set_itr(q_vector);
2817 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2818 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2819
2820 return 0;
2821}
2822
021230d4
AV		 2823/**
2824 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2825 * @adapter: board private structure
2826 *
2827 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2828 * interrupts from the kernel.
2829 **/
2830static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2831{
2832 struct net_device *netdev = adapter->netdev;
207867f5 2833 int vector, err;
e8e9f696 2834 int ri = 0, ti = 0;
021230d4 2835
49c7ffbe 2836 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2837 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2838 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2839
4ff7fb12 2840 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2841 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2842 "%s-%s-%d", netdev->name, "TxRx", ri++);
2843 ti++;
2844 } else if (q_vector->rx.ring) {
9fe93afd 2845 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2846 "%s-%s-%d", netdev->name, "rx", ri++);
2847 } else if (q_vector->tx.ring) {
9fe93afd 2848 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2849 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2850 } else {
2851 /* skip this unused q_vector */
2852 continue;
32aa77a4 2853 }
207867f5
AD		 2854 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2855 q_vector->name, q_vector);
9a799d71 2856 if (err) {
396e799c 2857 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2858 "Error: %d\n", err);
021230d4 2859 goto free_queue_irqs;
9a799d71 2860 }
207867f5
AD		 2861 /* If Flow Director is enabled, set interrupt affinity */
2862 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2863 /* assign the mask for this irq */
2864 irq_set_affinity_hint(entry->vector,
de88eeeb 2865 &q_vector->affinity_mask);
207867f5 2866 }
9a799d71
AK		 2867 }
2868
021230d4 2869 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2870 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2871 if (err) {
de88eeeb 2872 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2873 goto free_queue_irqs;
9a799d71
AK		 2874 }
2875
9a799d71
AK		 2876 return 0;
2877
021230d4 2878free_queue_irqs:
207867f5
AD		 2879 while (vector) {
2880 vector--;
2881 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2882 NULL);
2883 free_irq(adapter->msix_entries[vector].vector,
2884 adapter->q_vector[vector]);
2885 }
021230d4
AV		 2886 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2887 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2888 kfree(adapter->msix_entries);
2889 adapter->msix_entries = NULL;
9a799d71
AK		 2890 return err;
2891}
2892
2893/**
021230d4 2894 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2895 * @irq: interrupt number
2896 * @data: pointer to a network interface device structure
9a799d71
AK		 2897 **/
2898static irqreturn_t ixgbe_intr(int irq, void *data)
2899{
a65151ba 2900 struct ixgbe_adapter *adapter = data;
9a799d71 2901 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2902 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2903 u32 eicr;
2904
54037505 2905 /*
24ddd967 2906 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2907 * before the read of EICR.
2908 */
2909 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2910
021230d4 2911 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2912 * therefore no explicit interrupt disable is necessary */
021230d4 2913 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2914 if (!eicr) {
6af3b9eb
ET		 2915 /*
2916 * shared interrupt alert!
f47cf66e 2917 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2918 * have disabled interrupts due to EIAM
2919 * finish the workaround of silicon errata on 82598. Unmask
2920 * the interrupt that we masked before the EICR read.
2921 */
2922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2923 ixgbe_irq_enable(adapter, true, true);
9a799d71 2924 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2925 }
9a799d71 2926
cf8280ee
JB		 2927 if (eicr & IXGBE_EICR_LSC)
2928 ixgbe_check_lsc(adapter);
021230d4 2929
bd508178
AD		 2930 switch (hw->mac.type) {
2931 case ixgbe_mac_82599EB:
e8e26350 2932 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2933 /* Fall through */
2934 case ixgbe_mac_X540:
9a75a1ac
DS		 2935 case ixgbe_mac_X550:
2936 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2937 if (eicr & IXGBE_EICR_ECC) {
2938 e_info(link, "Received ECC Err, initiating reset\n");
2939 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2940 ixgbe_service_event_schedule(adapter);
2941 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2942 }
4f51bf70 2943 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2944 break;
2945 default:
2946 break;
2947 }
e8e26350 2948
0befdb3e 2949 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2950 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2951 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 2952
b9f6ed2b 2953 /* would disable interrupts here but EIAM disabled it */
ef2662b2 2954 napi_schedule_irqoff(&q_vector->napi);
9a799d71 2955
6af3b9eb
ET		 2956 /*
2957 * re-enable link(maybe) and non-queue interrupts, no flush.
2958 * ixgbe_poll will re-enable the queue interrupts
2959 */
6af3b9eb
ET		 2960 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2961 ixgbe_irq_enable(adapter, false, false);
2962
9a799d71
AK		 2963 return IRQ_HANDLED;
2964}
2965
2966/**
2967 * ixgbe_request_irq - initialize interrupts
2968 * @adapter: board private structure
2969 *
2970 * Attempts to configure interrupts using the best available
2971 * capabilities of the hardware and kernel.
2972 **/
021230d4 2973static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2974{
2975 struct net_device *netdev = adapter->netdev;
021230d4 2976 int err;
9a799d71 2977
4cc6df29 2978 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2979 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2980 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2981 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2982 netdev->name, adapter);
4cc6df29 2983 else
a0607fd3 2984 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2985 netdev->name, adapter);
9a799d71 2986
de88eeeb 2987 if (err)
396e799c 2988 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2989
9a799d71
AK		 2990 return err;
2991}
2992
2993static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2994{
49c7ffbe 2995 int vector;
9a799d71 2996
49c7ffbe
AD		 2997 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2998 free_irq(adapter->pdev->irq, adapter);
2999 return;
3000 }
4cc6df29 3001
49c7ffbe
AD		 3002 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3003 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3004 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3005
49c7ffbe
AD		 3006 /* free only the irqs that were actually requested */
3007 if (!q_vector->rx.ring && !q_vector->tx.ring)
3008 continue;
207867f5 3009
49c7ffbe
AD		 3010 /* clear the affinity_mask in the IRQ descriptor */
3011 irq_set_affinity_hint(entry->vector, NULL);
3012
3013 free_irq(entry->vector, q_vector);
9a799d71 3014 }
49c7ffbe
AD		 3015
3016 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3017}
3018
22d5a71b
JB		 3019/**
3020 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3021 * @adapter: board private structure
3022 **/
3023static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3024{
bd508178
AD		 3025 switch (adapter->hw.mac.type) {
3026 case ixgbe_mac_82598EB:
835462fc 3027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3028 break;
3029 case ixgbe_mac_82599EB:
b93a2226 3030 case ixgbe_mac_X540:
9a75a1ac
DS		 3031 case ixgbe_mac_X550:
3032 case ixgbe_mac_X550EM_x:
835462fc
NS		 3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3036 break;
3037 default:
3038 break;
22d5a71b
JB		 3039 }
3040 IXGBE_WRITE_FLUSH(&adapter->hw);
3041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3042 int vector;
3043
3044 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3045 synchronize_irq(adapter->msix_entries[vector].vector);
3046
3047 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3048 } else {
3049 synchronize_irq(adapter->pdev->irq);
3050 }
3051}
3052
9a799d71
AK		 3053/**
3054 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3055 *
3056 **/
3057static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3058{
d5bf4f67 3059 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3060
d5bf4f67 3061 ixgbe_write_eitr(q_vector);
9a799d71 3062
e8e26350
PW		 3063 ixgbe_set_ivar(adapter, 0, 0, 0);
3064 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3065
396e799c 3066 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3067}
3068
43e69bf0
AD		 3069/**
3070 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3071 * @adapter: board private structure
3072 * @ring: structure containing ring specific data
3073 *
3074 * Configure the Tx descriptor ring after a reset.
3075 **/
84418e3b
AD		 3076void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3077 struct ixgbe_ring *ring)
43e69bf0
AD		 3078{
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u64 tdba = ring->dma;
2f1860b8 3081 int wait_loop = 10;
b88c6de2 3082 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3083 u8 reg_idx = ring->reg_idx;
43e69bf0 3084
2f1860b8 3085 /* disable queue to avoid issues while updating state */
b88c6de2 3086 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3087 IXGBE_WRITE_FLUSH(hw);
3088
43e69bf0 3089 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3090 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3091 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3092 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3093 ring->count * sizeof(union ixgbe_adv_tx_desc));
3094 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3095 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3096 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3097
b88c6de2
AD		 3098 /*
3099 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3100 * higher than 1 when:
3101 * - ITR is 0 as it could cause false TX hangs
3102 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3103 *
3104 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3105 * to or less than the number of on chip descriptors, which is
3106 * currently 40.
3107 */
67da097e 3108 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3109 txdctl |= (1 << 16); /* WTHRESH = 1 */
3110 else
3111 txdctl |= (8 << 16); /* WTHRESH = 8 */
3112
e954b374
AD		 3113 /*
3114 * Setting PTHRESH to 32 both improves performance
3115 * and avoids a TX hang with DFP enabled
3116 */
b88c6de2
AD		 3117 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3118 32; /* PTHRESH = 32 */
2f1860b8
AD		 3119
3120 /* reinitialize flowdirector state */
39cb681b 3121 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3122 ring->atr_sample_rate = adapter->atr_sample_rate;
3123 ring->atr_count = 0;
3124 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3125 } else {
3126 ring->atr_sample_rate = 0;
3127 }
2f1860b8 3128
fd786b7b
AD		 3129 /* initialize XPS */
3130 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3131 struct ixgbe_q_vector *q_vector = ring->q_vector;
3132
3133 if (q_vector)
2a47fa45 3134 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3135 &q_vector->affinity_mask,
3136 ring->queue_index);
3137 }
3138
c84d324c
JF		 3139 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3140
2f1860b8 3141 /* enable queue */
2f1860b8
AD		 3142 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3143
3144 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3145 if (hw->mac.type == ixgbe_mac_82598EB &&
3146 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3147 return;
3148
3149 /* poll to verify queue is enabled */
3150 do {
032b4325 3151 usleep_range(1000, 2000);
2f1860b8
AD		 3152 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3153 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3154 if (!wait_loop)
3155 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3156}
3157
120ff942
AD		 3158static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3159{
3160 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3161 u32 rttdcs, mtqc;
8b1c0b24 3162 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3163
3164 if (hw->mac.type == ixgbe_mac_82598EB)
3165 return;
3166
3167 /* disable the arbiter while setting MTQC */
3168 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3169 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3170 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3171
3172 /* set transmit pool layout */
671c0adb
AD		 3173 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3174 mtqc = IXGBE_MTQC_VT_ENA;
3175 if (tcs > 4)
3176 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3177 else if (tcs > 1)
3178 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3179 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3180 mtqc |= IXGBE_MTQC_32VF;
3181 else
3182 mtqc |= IXGBE_MTQC_64VF;
3183 } else {
3184 if (tcs > 4)
3185 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3186 else if (tcs > 1)
3187 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3188 else
671c0adb
AD		 3189 mtqc = IXGBE_MTQC_64Q_1PB;
3190 }
120ff942 3191
671c0adb 3192 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3193
671c0adb
AD		 3194 /* Enable Security TX Buffer IFG for multiple pb */
3195 if (tcs) {
3196 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3197 sectx |= IXGBE_SECTX_DCB;
3198 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3199 }
3200
3201 /* re-enable the arbiter */
3202 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3203 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3204}
3205
9a799d71 3206/**
3a581073 3207 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3208 * @adapter: board private structure
3209 *
3210 * Configure the Tx unit of the MAC after a reset.
3211 **/
3212static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3213{
2f1860b8
AD		 3214 struct ixgbe_hw *hw = &adapter->hw;
3215 u32 dmatxctl;
43e69bf0 3216 u32 i;
9a799d71 3217
2f1860b8
AD		 3218 ixgbe_setup_mtqc(adapter);
3219
3220 if (hw->mac.type != ixgbe_mac_82598EB) {
3221 /* DMATXCTL.EN must be before Tx queues are enabled */
3222 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3223 dmatxctl |= IXGBE_DMATXCTL_TE;
3224 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3225 }
3226
9a799d71 3227 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3228 for (i = 0; i < adapter->num_tx_queues; i++)
3229 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3230}
3231
3ebe8fde
AD		 3232static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3233 struct ixgbe_ring *ring)
3234{
3235 struct ixgbe_hw *hw = &adapter->hw;
3236 u8 reg_idx = ring->reg_idx;
3237 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3238
3239 srrctl |= IXGBE_SRRCTL_DROP_EN;
3240
3241 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3242}
3243
3244static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3245 struct ixgbe_ring *ring)
3246{
3247 struct ixgbe_hw *hw = &adapter->hw;
3248 u8 reg_idx = ring->reg_idx;
3249 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3250
3251 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3252
3253 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3254}
3255
3256#ifdef CONFIG_IXGBE_DCB
3257void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3258#else
3259static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3260#endif
3261{
3262 int i;
3263 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3264
3265 if (adapter->ixgbe_ieee_pfc)
3266 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3267
3268 /*
3269 * We should set the drop enable bit if:
3270 * SR-IOV is enabled
3271 * or
3272 * Number of Rx queues > 1 and flow control is disabled
3273 *
3274 * This allows us to avoid head of line blocking for security
3275 * and performance reasons.
3276 */
3277 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3278 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3279 for (i = 0; i < adapter->num_rx_queues; i++)
3280 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3281 } else {
3282 for (i = 0; i < adapter->num_rx_queues; i++)
3283 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3284 }
3285}
3286
e8e26350 3287#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3288
a6616b42 3289static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3290 struct ixgbe_ring *rx_ring)
cc41ac7c 3291{
45e9baa5 3292 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3293 u32 srrctl;
bf29ee6c 3294 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3295
45e9baa5
AD		 3296 if (hw->mac.type == ixgbe_mac_82598EB) {
3297 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3298
45e9baa5
AD		 3299 /*
3300 * if VMDq is not active we must program one srrctl register
3301 * per RSS queue since we have enabled RDRXCTL.MVMEN
3302 */
3303 reg_idx &= mask;
3304 }
cc41ac7c 3305
45e9baa5
AD		 3306 /* configure header buffer length, needed for RSC */
3307 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3308
45e9baa5 3309 /* configure the packet buffer length */
f800326d 3310 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3311
3312 /* configure descriptor type */
f800326d 3313 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3314
45e9baa5 3315 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3316}
9a799d71 3317
dfaf891d 3318/**
a897a2ad 3319 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3320 * @adapter: device handle
3321 *
3322 * - 82598/82599/X540: 128
3323 * - X550(non-SRIOV mode): 512
3324 * - X550(SRIOV mode): 64
3325 */
7f276efb 3326u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3327{
3328 if (adapter->hw.mac.type < ixgbe_mac_X550)
3329 return 128;
3330 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3331 return 64;
3332 else
3333 return 512;
3334}
3335
3336/**
a897a2ad 3337 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3338 * @adapter: device handle
3339 *
3340 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3341 */
1c7cf078 3342void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3343{
dfaf891d 3344 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3345 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3346 u32 reta = 0;
dfaf891d
VZ		 3347 u32 indices_multi;
3348 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3349
0f9b232b 3350 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3351 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3352 * indices.
3353 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3354 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3355 */
3356 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3357 indices_multi = 0x11;
3358 else
3359 indices_multi = 0x1;
3360
dfaf891d
VZ		 3361 /* Write redirection table to HW */
3362 for (i = 0; i < reta_entries; i++) {
3363 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3364 if ((i & 3) == 3) {
3365 if (i < 128)
3366 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3367 else
3368 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3369 reta);
dfaf891d 3370 reta = 0;
0f9b232b
DS		 3371 }
3372 }
3373}
3374
dfaf891d 3375/**
a897a2ad 3376 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3377 * @adapter: device handle
3378 *
3379 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3380 */
3381static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3382{
dfaf891d 3383 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3384 struct ixgbe_hw *hw = &adapter->hw;
3385 u32 vfreta = 0;
dfaf891d
VZ		 3386 unsigned int pf_pool = adapter->num_vfs;
3387
3388 /* Write redirection table to HW */
3389 for (i = 0; i < reta_entries; i++) {
3390 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3391 if ((i & 3) == 3) {
3392 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3393 vfreta);
3394 vfreta = 0;
3395 }
3396 }
3397}
3398
3399static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3400{
3401 struct ixgbe_hw *hw = &adapter->hw;
3402 u32 i, j;
3403 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3404 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3405
3406 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3407 * make full use of any rings they may have. We will use the
3408 * PSRTYPE register to control how many rings we use within the PF.
3409 */
3410 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3411 rss_i = 2;
3412
3413 /* Fill out hash function seeds */
3414 for (i = 0; i < 10; i++)
3415 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3416
3417 /* Fill out redirection table */
3418 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3419
3420 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3421 if (j == rss_i)
3422 j = 0;
3423
3424 adapter->rss_indir_tbl[i] = j;
3425 }
3426
3427 ixgbe_store_reta(adapter);
3428}
3429
3430static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3431{
3432 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3433 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3434 unsigned int pf_pool = adapter->num_vfs;
3435 int i, j;
3436
3437 /* Fill out hash function seeds */
3438 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3439 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3440 adapter->rss_key[i]);
0f9b232b
DS		 3441
3442 /* Fill out the redirection table */
3443 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3444 if (j == rss_i)
05abb126 3445 j = 0;
dfaf891d
VZ		 3446
3447 adapter->rss_indir_tbl[i] = j;
05abb126 3448 }
dfaf891d
VZ		 3449
3450 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3451}
3452
3453static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3454{
3455 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3456 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3457 u32 rxcsum;
0cefafad 3458
05abb126
AD		 3459 /* Disable indicating checksum in descriptor, enables RSS hash */
3460 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3461 rxcsum |= IXGBE_RXCSUM_PCSD;
3462 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3463
671c0adb 3464 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3465 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3466 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3467 } else {
671c0adb
AD		 3468 u8 tcs = netdev_get_num_tc(adapter->netdev);
3469
3470 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3471 if (tcs > 4)
3472 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3473 else if (tcs > 1)
3474 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3475 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3476 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3477 else
671c0adb
AD		 3478 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3479 } else {
3480 if (tcs > 4)
8b1c0b24 3481 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3482 else if (tcs > 1)
3483 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3484 else
3485 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3486 }
0cefafad
JB		 3487 }
3488
05abb126 3489 /* Perform hash on these packet types */
d1b849b9
DS		 3490 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3491 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3492 IXGBE_MRQC_RSS_FIELD_IPV6 |
3493 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3494
ef6afc0c 3495 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3496 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3497 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3498 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3499
dfaf891d 3500 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3501 if ((hw->mac.type >= ixgbe_mac_X550) &&
3502 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3503 unsigned int pf_pool = adapter->num_vfs;
3504
3505 /* Enable VF RSS mode */
3506 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3507 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3508
3509 /* Setup RSS through the VF registers */
dfaf891d 3510 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3511 vfmrqc = IXGBE_MRQC_RSSEN;
3512 vfmrqc |= rss_field;
3513 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3514 } else {
dfaf891d 3515 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3516 mrqc |= rss_field;
3517 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3518 }
0cefafad
JB		 3519}
3520
bb5a9ad2
NS		 3521/**
3522 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3523 * @adapter: address of board private structure
3524 * @index: index of ring to set
bb5a9ad2 3525 **/
082757af 3526static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3527 struct ixgbe_ring *ring)
bb5a9ad2 3528{
bb5a9ad2 3529 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3530 u32 rscctrl;
bf29ee6c 3531 u8 reg_idx = ring->reg_idx;
7367096a 3532
7d637bcc 3533 if (!ring_is_rsc_enabled(ring))
7367096a 3534 return;
bb5a9ad2 3535
7367096a 3536 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3537 rscctrl |= IXGBE_RSCCTL_RSCEN;
3538 /*
3539 * we must limit the number of descriptors so that the
3540 * total size of max desc * buf_len is not greater
642c680e 3541 * than 65536
bb5a9ad2 3542 */
f800326d 3543 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3544 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3545}
3546
9e10e045
AD		 3547#define IXGBE_MAX_RX_DESC_POLL 10
3548static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3549 struct ixgbe_ring *ring)
3550{
3551 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3552 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3553 u32 rxdctl;
bf29ee6c 3554 u8 reg_idx = ring->reg_idx;
9e10e045 3555
b0483c8f
MR		 3556 if (ixgbe_removed(hw->hw_addr))
3557 return;
9e10e045
AD		 3558 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3559 if (hw->mac.type == ixgbe_mac_82598EB &&
3560 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3561 return;
3562
3563 do {
032b4325 3564 usleep_range(1000, 2000);
9e10e045
AD		 3565 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3566 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3567
3568 if (!wait_loop) {
3569 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3570 "the polling period\n", reg_idx);
3571 }
3572}
3573
2d39d576
YZ		 3574void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3575 struct ixgbe_ring *ring)
3576{
3577 struct ixgbe_hw *hw = &adapter->hw;
3578 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3579 u32 rxdctl;
3580 u8 reg_idx = ring->reg_idx;
3581
b0483c8f
MR		 3582 if (ixgbe_removed(hw->hw_addr))
3583 return;
2d39d576
YZ		 3584 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3585 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3586
3587 /* write value back with RXDCTL.ENABLE bit cleared */
3588 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3589
3590 if (hw->mac.type == ixgbe_mac_82598EB &&
3591 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3592 return;
3593
3594 /* the hardware may take up to 100us to really disable the rx queue */
3595 do {
3596 udelay(10);
3597 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3598 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3599
3600 if (!wait_loop) {
3601 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3602 "the polling period\n", reg_idx);
3603 }
3604}
3605
84418e3b
AD		 3606void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3607 struct ixgbe_ring *ring)
acd37177
AD		 3608{
3609 struct ixgbe_hw *hw = &adapter->hw;
3610 u64 rdba = ring->dma;
9e10e045 3611 u32 rxdctl;
bf29ee6c 3612 u8 reg_idx = ring->reg_idx;
acd37177 3613
9e10e045
AD		 3614 /* disable queue to avoid issues while updating state */
3615 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3616 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3617
acd37177
AD		 3618 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3619 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3620 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3621 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3622 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3623 IXGBE_WRITE_FLUSH(hw);
3624
acd37177
AD		 3625 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3626 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3627 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3628
3629 ixgbe_configure_srrctl(adapter, ring);
3630 ixgbe_configure_rscctl(adapter, ring);
3631
3632 if (hw->mac.type == ixgbe_mac_82598EB) {
3633 /*
3634 * enable cache line friendly hardware writes:
3635 * PTHRESH=32 descriptors (half the internal cache),
3636 * this also removes ugly rx_no_buffer_count increment
3637 * HTHRESH=4 descriptors (to minimize latency on fetch)
3638 * WTHRESH=8 burst writeback up to two cache lines
3639 */
3640 rxdctl &= ~0x3FFFFF;
3641 rxdctl |= 0x080420;
3642 }
3643
3644 /* enable receive descriptor ring */
3645 rxdctl |= IXGBE_RXDCTL_ENABLE;
3646 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3647
3648 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3649 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3650}
3651
48654521
AD		 3652static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3653{
3654 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3655 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3656 u16 pool;
48654521
AD		 3657
3658 /* PSRTYPE must be initialized in non 82598 adapters */
3659 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3660 IXGBE_PSRTYPE_UDPHDR |
3661 IXGBE_PSRTYPE_IPV4HDR |
48654521 3662 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3663 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3664
3665 if (hw->mac.type == ixgbe_mac_82598EB)
3666 return;
3667
fbe7ca7f
AD		 3668 if (rss_i > 3)
3669 psrtype |= 2 << 29;
3670 else if (rss_i > 1)
3671 psrtype |= 1 << 29;
48654521 3672
2a47fa45
JF		 3673 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3674 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3675}
3676
f5b4a52e
AD		 3677static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3678{
3679 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3680 u32 reg_offset, vf_shift;
435b19f6 3681 u32 gcr_ext, vmdctl;
de4c7f65 3682 int i;
f5b4a52e
AD		 3683
3684 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3685 return;
3686
3687 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3688 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3689 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3690 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3691 vmdctl |= IXGBE_VT_CTL_REPLEN;
3692 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3693
1d9c0bfd
AD		 3694 vf_shift = VMDQ_P(0) % 32;
3695 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3696
3697 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3698 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3699 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3700 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3701 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3702 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3703 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3704
3705 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3706 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3707
16369564
AD		 3708 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3709 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3710
f5b4a52e
AD		 3711 /*
3712 * Set up VF register offsets for selected VT Mode,
3713 * i.e. 32 or 64 VFs for SR-IOV
3714 */
73079ea0
AD		 3715 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3716 case IXGBE_82599_VMDQ_8Q_MASK:
3717 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3718 break;
3719 case IXGBE_82599_VMDQ_4Q_MASK:
3720 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3721 break;
3722 default:
3723 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3724 break;
3725 }
3726
f5b4a52e
AD		 3727 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3728
435b19f6 3729
a985b6c3 3730 /* Enable MAC Anti-Spoofing */
435b19f6 3731 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3732 adapter->num_vfs);
5b7f000f 3733
f079fa00 3734 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
5b7f000f
DS		 3735 * calling set_ethertype_anti_spoofing for each VF in loop below
3736 */
f079fa00 3737 if (hw->mac.ops.set_ethertype_anti_spoofing) {
5b7f000f 3738 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
f079fa00
ET		 3739 (IXGBE_ETQF_FILTER_EN |
3740 IXGBE_ETQF_TX_ANTISPOOF |
3741 IXGBE_ETH_P_LLDP));
3742
3743 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3744 (IXGBE_ETQF_FILTER_EN |
3745 IXGBE_ETQF_TX_ANTISPOOF |
3746 ETH_P_PAUSE));
3747 }
5b7f000f 3748
de4c7f65
GR		 3749 /* For VFs that have spoof checking turned off */
3750 for (i = 0; i < adapter->num_vfs; i++) {
3751 if (!adapter->vfinfo[i].spoofchk_enabled)
3752 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3753
3754 /* enable ethertype anti spoofing if hw supports it */
3755 if (hw->mac.ops.set_ethertype_anti_spoofing)
3756 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3757
3758 /* Enable/Disable RSS query feature */
3759 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3760 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3761 }
f5b4a52e
AD		 3762}
3763
477de6ed 3764static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3765{
9a799d71
AK		 3766 struct ixgbe_hw *hw = &adapter->hw;
3767 struct net_device *netdev = adapter->netdev;
3768 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3769 struct ixgbe_ring *rx_ring;
3770 int i;
3771 u32 mhadd, hlreg0;
48654521 3772
63f39bd1 3773#ifdef IXGBE_FCOE
477de6ed
AD		 3774 /* adjust max frame to be able to do baby jumbo for FCoE */
3775 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3776 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3777 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3778
477de6ed 3779#endif /* IXGBE_FCOE */
872844dd
AD		 3780
3781 /* adjust max frame to be at least the size of a standard frame */
3782 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3783 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3784
477de6ed
AD		 3785 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3786 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3787 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3788 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3789
3790 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3791 }
3792
3793 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3794 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3795 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3796 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3797
0cefafad
JB		 3798 /*
3799 * Setup the HW Rx Head and Tail Descriptor Pointers and
3800 * the Base and Length of the Rx Descriptor Ring
3801 */
9a799d71 3802 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3803 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3804 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3805 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3806 else
7d637bcc 3807 clear_ring_rsc_enabled(rx_ring);
477de6ed 3808 }
477de6ed
AD		 3809}
3810
7367096a
AD		 3811static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3812{
3813 struct ixgbe_hw *hw = &adapter->hw;
3814 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3815
3816 switch (hw->mac.type) {
3817 case ixgbe_mac_82598EB:
3818 /*
3819 * For VMDq support of different descriptor types or
3820 * buffer sizes through the use of multiple SRRCTL
3821 * registers, RDRXCTL.MVMEN must be set to 1
3822 *
3823 * also, the manual doesn't mention it clearly but DCA hints
3824 * will only use queue 0's tags unless this bit is set. Side
3825 * effects of setting this bit are only that SRRCTL must be
3826 * fully programmed [0..15]
3827 */
3828 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3829 break;
052a1a72
MR		 3830 case ixgbe_mac_X550:
3831 case ixgbe_mac_X550EM_x:
f961ddae
MR		 3832 if (adapter->num_vfs)
3833 rdrxctl |= IXGBE_RDRXCTL_PSP;
3834 /* fall through for older HW */
7367096a 3835 case ixgbe_mac_82599EB:
b93a2226 3836 case ixgbe_mac_X540:
7367096a
AD		 3837 /* Disable RSC for ACK packets */
3838 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3839 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3840 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3841 /* hardware requires some bits to be set by default */
3842 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3843 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3844 break;
3845 default:
3846 /* We should do nothing since we don't know this hardware */
3847 return;
3848 }
3849
3850 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3851}
3852
477de6ed
AD		 3853/**
3854 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3855 * @adapter: board private structure
3856 *
3857 * Configure the Rx unit of the MAC after a reset.
3858 **/
3859static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3860{
3861 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3862 int i;
6dcc28b9 3863 u32 rxctrl, rfctl;
477de6ed
AD		 3864
3865 /* disable receives while setting up the descriptors */
1f9ac57c 3866 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3867
3868 ixgbe_setup_psrtype(adapter);
7367096a 3869 ixgbe_setup_rdrxctl(adapter);
477de6ed 3870
6dcc28b9
JK		 3871 /* RSC Setup */
3872 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3873 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3874 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3875 rfctl |= IXGBE_RFCTL_RSC_DIS;
3876 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3877
9e10e045 3878 /* Program registers for the distribution of queues */
f5b4a52e 3879 ixgbe_setup_mrqc(adapter);
f5b4a52e 3880
477de6ed
AD		 3881 /* set_rx_buffer_len must be called before ring initialization */
3882 ixgbe_set_rx_buffer_len(adapter);
3883
3884 /*
3885 * Setup the HW Rx Head and Tail Descriptor Pointers and
3886 * the Base and Length of the Rx Descriptor Ring
3887 */
9e10e045
AD		 3888 for (i = 0; i < adapter->num_rx_queues; i++)
3889 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3890
1f9ac57c 3891 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3892 /* disable drop enable for 82598 parts */
3893 if (hw->mac.type == ixgbe_mac_82598EB)
3894 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3895
3896 /* enable all receives */
3897 rxctrl |= IXGBE_RXCTRL_RXEN;
3898 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3899}
3900
80d5c368
PM		 3901static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3902 __be16 proto, u16 vid)
068c89b0
DS		 3903{
3904 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3905 struct ixgbe_hw *hw = &adapter->hw;
3906
3907 /* add VID to filter table */
b6488b66 3908 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, true);
f62bbb5e 3909 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3910
3911 return 0;
068c89b0
DS		 3912}
3913
e1d0a2af
AD		 3914static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3915{
3916 u32 vlvf;
3917 int idx;
3918
3919 /* short cut the special case */
3920 if (vlan == 0)
3921 return 0;
3922
3923 /* Search for the vlan id in the VLVF entries */
3924 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3925 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3926 if ((vlvf & VLAN_VID_MASK) == vlan)
3927 break;
3928 }
3929
3930 return idx;
3931}
3932
3933void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3934{
3935 struct ixgbe_hw *hw = &adapter->hw;
3936 u32 bits, word;
3937 int idx;
3938
3939 idx = ixgbe_find_vlvf_entry(hw, vid);
3940 if (!idx)
3941 return;
3942
3943 /* See if any other pools are set for this VLAN filter
3944 * entry other than the PF.
3945 */
3946 word = idx * 2 + (VMDQ_P(0) / 32);
3947 bits = ~(1 << (VMDQ_P(0)) % 32);
3948 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3949
3950 /* Disable the filter so this falls into the default pool. */
3951 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
3952 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3953 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
3954 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
3955 }
3956}
3957
80d5c368
PM		 3958static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3959 __be16 proto, u16 vid)
068c89b0
DS		 3960{
3961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3962 struct ixgbe_hw *hw = &adapter->hw;
3963
068c89b0 3964 /* remove VID from filter table */
e1d0a2af
AD		 3965 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
3966 ixgbe_update_pf_promisc_vlvf(adapter, vid);
3967 else
3968 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
3969
f62bbb5e 3970 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3971
3972 return 0;
068c89b0
DS		 3973}
3974
f62bbb5e
JG		 3975/**
3976 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3977 * @adapter: driver data
3978 */
3979static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3980{
3981 struct ixgbe_hw *hw = &adapter->hw;
3982 u32 vlnctrl;
5f6c0181
JB		 3983 int i, j;
3984
3985 switch (hw->mac.type) {
3986 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3987 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3988 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3989 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3990 break;
3991 case ixgbe_mac_82599EB:
b93a2226 3992 case ixgbe_mac_X540:
9a75a1ac
DS		 3993 case ixgbe_mac_X550:
3994 case ixgbe_mac_X550EM_x:
5f6c0181 3995 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3996 struct ixgbe_ring *ring = adapter->rx_ring[i];
3997
3998 if (ring->l2_accel_priv)
3999 continue;
4000 j = ring->reg_idx;
5f6c0181
JB		 4001 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4002 vlnctrl &= ~IXGBE_RXDCTL_VME;
4003 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4004 }
4005 break;
4006 default:
4007 break;
4008 }
4009}
4010
4011/**
f62bbb5e 4012 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4013 * @adapter: driver data
4014 */
f62bbb5e 4015static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4016{
4017 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4018 u32 vlnctrl;
5f6c0181
JB		 4019 int i, j;
4020
4021 switch (hw->mac.type) {
4022 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4023 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4024 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4025 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4026 break;
4027 case ixgbe_mac_82599EB:
b93a2226 4028 case ixgbe_mac_X540:
9a75a1ac
DS		 4029 case ixgbe_mac_X550:
4030 case ixgbe_mac_X550EM_x:
5f6c0181 4031 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4032 struct ixgbe_ring *ring = adapter->rx_ring[i];
4033
4034 if (ring->l2_accel_priv)
4035 continue;
4036 j = ring->reg_idx;
5f6c0181
JB		 4037 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4038 vlnctrl |= IXGBE_RXDCTL_VME;
4039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4040 }
4041 break;
4042 default:
4043 break;
4044 }
4045}
4046
16369564
AD		 4047static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4048{
4049 struct ixgbe_hw *hw = &adapter->hw;
4050 u32 vlnctrl, i;
4051
4052 switch (hw->mac.type) {
4053 case ixgbe_mac_82599EB:
4054 case ixgbe_mac_X540:
4055 case ixgbe_mac_X550:
4056 case ixgbe_mac_X550EM_x:
4057 default:
4058 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4059 break;
4060 /* fall through */
4061 case ixgbe_mac_82598EB:
4062 /* legacy case, we can just disable VLAN filtering */
4063 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4064 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4065 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4066 return;
4067 }
4068
4069 /* We are already in VLAN promisc, nothing to do */
4070 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4071 return;
4072
4073 /* Set flag so we don't redo unnecessary work */
4074 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4075
4076 /* Add PF to all active pools */
4077 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4078 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4079 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4080
4081 vlvfb |= 1 << (VMDQ_P(0) % 32);
4082 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4083 }
4084
4085 /* Set all bits in the VLAN filter table array */
4086 for (i = hw->mac.vft_size; i--;)
4087 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4088}
4089
4090#define VFTA_BLOCK_SIZE 8
4091static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4092{
4093 struct ixgbe_hw *hw = &adapter->hw;
4094 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4095 u32 vid_start = vfta_offset * 32;
4096 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4097 u32 i, vid, word, bits;
4098
4099 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4100 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4101
4102 /* pull VLAN ID from VLVF */
4103 vid = vlvf & VLAN_VID_MASK;
4104
4105 /* only concern outselves with a certain range */
4106 if (vid < vid_start || vid >= vid_end)
4107 continue;
4108
4109 if (vlvf) {
4110 /* record VLAN ID in VFTA */
4111 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4112
4113 /* if PF is part of this then continue */
4114 if (test_bit(vid, adapter->active_vlans))
4115 continue;
4116 }
4117
4118 /* remove PF from the pool */
4119 word = i * 2 + VMDQ_P(0) / 32;
4120 bits = ~(1 << (VMDQ_P(0) % 32));
4121 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4122 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4123 }
4124
4125 /* extract values from active_vlans and write back to VFTA */
4126 for (i = VFTA_BLOCK_SIZE; i--;) {
4127 vid = (vfta_offset + i) * 32;
4128 word = vid / BITS_PER_LONG;
4129 bits = vid % BITS_PER_LONG;
4130
4131 vfta[i] |= adapter->active_vlans[word] >> bits;
4132
4133 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4134 }
4135}
4136
4137static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4138{
4139 struct ixgbe_hw *hw = &adapter->hw;
4140 u32 vlnctrl, i;
4141
4142 switch (hw->mac.type) {
4143 case ixgbe_mac_82599EB:
4144 case ixgbe_mac_X540:
4145 case ixgbe_mac_X550:
4146 case ixgbe_mac_X550EM_x:
4147 default:
4148 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4149 break;
4150 /* fall through */
4151 case ixgbe_mac_82598EB:
4152 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4153 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4154 vlnctrl |= IXGBE_VLNCTRL_VFE;
4155 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4156 return;
4157 }
4158
4159 /* We are not in VLAN promisc, nothing to do */
4160 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4161 return;
4162
4163 /* Set flag so we don't redo unnecessary work */
4164 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4165
4166 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4167 ixgbe_scrub_vfta(adapter, i);
4168}
4169
9a799d71
AK		 4170static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4171{
f62bbb5e 4172 u16 vid;
9a799d71 4173
80d5c368 4174 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 4175
4176 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4177 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4178}
4179
b335e75b
JK		 4180/**
4181 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4182 * @netdev: network interface device structure
4183 *
4184 * Writes multicast address list to the MTA hash table.
4185 * Returns: -ENOMEM on failure
4186 * 0 on no addresses written
4187 * X on writing X addresses to MTA
4188 **/
4189static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4190{
4191 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4192 struct ixgbe_hw *hw = &adapter->hw;
4193
4194 if (!netif_running(netdev))
4195 return 0;
4196
4197 if (hw->mac.ops.update_mc_addr_list)
4198 hw->mac.ops.update_mc_addr_list(hw, netdev);
4199 else
4200 return -ENOMEM;
4201
4202#ifdef CONFIG_PCI_IOV
5d7daa35 4203 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4204#endif
4205
4206 return netdev_mc_count(netdev);
4207}
4208
5d7daa35
JK		 4209#ifdef CONFIG_PCI_IOV
4210void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4211{
c9f53e63 4212 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4213 struct ixgbe_hw *hw = &adapter->hw;
4214 int i;
c9f53e63
AD		 4215
4216 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4217 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4218
4219 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4220 hw->mac.ops.set_rar(hw, i,
4221 mac_table->addr,
4222 mac_table->pool,
5d7daa35
JK		 4223 IXGBE_RAH_AV);
4224 else
4225 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4226 }
4227}
5d7daa35 4228
c9f53e63 4229#endif
5d7daa35
JK		 4230static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4231{
c9f53e63 4232 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4233 struct ixgbe_hw *hw = &adapter->hw;
4234 int i;
5d7daa35 4235
c9f53e63
AD		 4236 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4237 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4238 continue;
4239
4240 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4241
4242 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4243 hw->mac.ops.set_rar(hw, i,
4244 mac_table->addr,
4245 mac_table->pool,
4246 IXGBE_RAH_AV);
4247 else
4248 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4249 }
4250}
4251
4252static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4253{
c9f53e63 4254 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4255 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4256 int i;
5d7daa35 4257
c9f53e63
AD		 4258 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4259 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4260 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4261 }
c9f53e63 4262
5d7daa35
JK		 4263 ixgbe_sync_mac_table(adapter);
4264}
4265
c9f53e63 4266static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4267{
c9f53e63 4268 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4269 struct ixgbe_hw *hw = &adapter->hw;
4270 int i, count = 0;
4271
c9f53e63
AD		 4272 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4273 /* do not count default RAR as available */
4274 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4275 continue;
4276
4277 /* only count unused and addresses that belong to us */
4278 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4279 if (mac_table->pool != pool)
4280 continue;
4281 }
4282
4283 count++;
5d7daa35 4284 }
c9f53e63 4285
5d7daa35
JK		 4286 return count;
4287}
4288
4289/* this function destroys the first RAR entry */
c9f53e63 4290static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4291{
c9f53e63 4292 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4293 struct ixgbe_hw *hw = &adapter->hw;
4294
c9f53e63
AD		 4295 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4296 mac_table->pool = VMDQ_P(0);
4297
4298 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4299
4300 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4301 IXGBE_RAH_AV);
4302}
4303
c9f53e63
AD		 4304int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4305 const u8 *addr, u16 pool)
5d7daa35 4306{
c9f53e63 4307 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4308 struct ixgbe_hw *hw = &adapter->hw;
4309 int i;
4310
4311 if (is_zero_ether_addr(addr))
4312 return -EINVAL;
4313
c9f53e63
AD		 4314 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4315 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4316 continue;
c9f53e63
AD		 4317
4318 ether_addr_copy(mac_table->addr, addr);
4319 mac_table->pool = pool;
4320
4321 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4322 IXGBE_MAC_STATE_IN_USE;
4323
5d7daa35 4324 ixgbe_sync_mac_table(adapter);
c9f53e63 4325
5d7daa35
JK		 4326 return i;
4327 }
c9f53e63 4328
5d7daa35
JK		 4329 return -ENOMEM;
4330}
4331
c9f53e63
AD		 4332int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4333 const u8 *addr, u16 pool)
5d7daa35 4334{
c9f53e63 4335 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4336 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4337 int i;
5d7daa35
JK		 4338
4339 if (is_zero_ether_addr(addr))
4340 return -EINVAL;
4341
c9f53e63
AD		 4342 /* search table for addr, if found clear IN_USE flag and sync */
4343 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4344 /* we can only delete an entry if it is in use */
4345 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4346 continue;
4347 /* we only care about entries that belong to the given pool */
4348 if (mac_table->pool != pool)
4349 continue;
4350 /* we only care about a specific MAC address */
4351 if (!ether_addr_equal(addr, mac_table->addr))
4352 continue;
4353
4354 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4355 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4356
4357 ixgbe_sync_mac_table(adapter);
4358
4359 return 0;
5d7daa35 4360 }
c9f53e63 4361
5d7daa35
JK		 4362 return -ENOMEM;
4363}
2850062a
AD		 4364/**
4365 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4366 * @netdev: network interface device structure
4367 *
4368 * Writes unicast address list to the RAR table.
4369 * Returns: -ENOMEM on failure/insufficient address space
4370 * 0 on no addresses written
4371 * X on writing X addresses to the RAR table
4372 **/
5d7daa35 4373static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4374{
4375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4376 int count = 0;
4377
4378 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4379 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4380 return -ENOMEM;
4381
95447461 4382 if (!netdev_uc_empty(netdev)) {
2850062a 4383 struct netdev_hw_addr *ha;
2850062a 4384 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4385 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4386 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4387 count++;
4388 }
4389 }
2850062a
AD		 4390 return count;
4391}
4392
0f079d22
AD		 4393static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4394{
4395 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4396 int ret;
4397
4398 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4399
4400 return min_t(int, ret, 0);
4401}
4402
4403static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4404{
4405 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4406
4407 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4408
4409 return 0;
4410}
4411
9a799d71 4412/**
2c5645cf 4413 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4414 * @netdev: network interface device structure
4415 *
2c5645cf
CL		 4416 * The set_rx_method entry point is called whenever the unicast/multicast
4417 * address list or the network interface flags are updated. This routine is
4418 * responsible for configuring the hardware for proper unicast, multicast and
4419 * promiscuous mode.
9a799d71 4420 **/
7f870475 4421void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4422{
4423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4424 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 4425 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4426 int count;
9a799d71
AK		 4427
4428 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4429 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4430
f5dc442b 4431 /* set all bits that we expect to always be set */
3f2d1c0f 4432 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4433 fctrl |= IXGBE_FCTRL_BAM;
4434 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4435 fctrl |= IXGBE_FCTRL_PMCF;
4436
2850062a
AD		 4437 /* clear the bits we are changing the status of */
4438 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4439 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4440 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4441 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4442 vmolr |= IXGBE_VMOLR_MPE;
16369564 4443 ixgbe_vlan_promisc_enable(adapter);
9a799d71 4444 } else {
746b9f02
PM		 4445 if (netdev->flags & IFF_ALLMULTI) {
4446 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4447 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4448 }
e433ea1f 4449 hw->addr_ctrl.user_set_promisc = false;
16369564 4450 ixgbe_vlan_promisc_disable(adapter);
9dcb373c
JF		 4451 }
4452
4453 /*
4454 * Write addresses to available RAR registers, if there is not
4455 * sufficient space to store all the addresses then enable
4456 * unicast promiscuous mode
4457 */
0f079d22 4458 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4459 fctrl |= IXGBE_FCTRL_UPE;
4460 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4461 }
4462
cf78959c
ET		 4463 /* Write addresses to the MTA, if the attempt fails
4464 * then we should just turn on promiscuous mode so
4465 * that we can at least receive multicast traffic
4466 */
b335e75b
JK		 4467 count = ixgbe_write_mc_addr_list(netdev);
4468 if (count < 0) {
4469 fctrl |= IXGBE_FCTRL_MPE;
4470 vmolr |= IXGBE_VMOLR_MPE;
4471 } else if (count) {
4472 vmolr |= IXGBE_VMOLR_ROMPE;
4473 }
1d9c0bfd
AD		 4474
4475 if (hw->mac.type != ixgbe_mac_82598EB) {
4476 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4477 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4478 IXGBE_VMOLR_ROPE);
1d9c0bfd 4479 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4480 }
4481
3f2d1c0f
BG		 4482 /* This is useful for sniffing bad packets. */
4483 if (adapter->netdev->features & NETIF_F_RXALL) {
4484 /* UPE and MPE will be handled by normal PROMISC logic
4485 * in e1000e_set_rx_mode */
4486 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4487 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4488 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4489
4490 fctrl &= ~(IXGBE_FCTRL_DPF);
4491 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4492 }
4493
2850062a 4494 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4495
f646968f 4496 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4497 ixgbe_vlan_strip_enable(adapter);
4498 else
4499 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4500}
4501
021230d4
AV		 4502static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4503{
4504 int q_idx;
021230d4 4505
5a85e737
ET		 4506 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4507 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4508 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4509 }
021230d4
AV		 4510}
4511
4512static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4513{
4514 int q_idx;
021230d4 4515
5a85e737 4516 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4517 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4518 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4519 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4520 usleep_range(1000, 20000);
5a85e737
ET		 4521 }
4522 }
021230d4
AV		 4523}
4524
67359c3c
MR		 4525static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4526{
4527 switch (adapter->hw.mac.type) {
4528 case ixgbe_mac_X550:
4529 case ixgbe_mac_X550EM_x:
4530 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4531#ifdef CONFIG_IXGBE_VXLAN
4532 adapter->vxlan_port = 0;
4533#endif
4534 break;
4535 default:
4536 break;
4537 }
4538}
4539
7a6b6f51 4540#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4541/**
2f90b865
AD		 4542 * ixgbe_configure_dcb - Configure DCB hardware
4543 * @adapter: ixgbe adapter struct
4544 *
4545 * This is called by the driver on open to configure the DCB hardware.
4546 * This is also called by the gennetlink interface when reconfiguring
4547 * the DCB state.
4548 */
4549static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4550{
4551 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4552 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4553
67ebd791
AD		 4554 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4555 if (hw->mac.type == ixgbe_mac_82598EB)
4556 netif_set_gso_max_size(adapter->netdev, 65536);
4557 return;
4558 }
4559
4560 if (hw->mac.type == ixgbe_mac_82598EB)
4561 netif_set_gso_max_size(adapter->netdev, 32768);
4562
971060b1 4563#ifdef IXGBE_FCOE
b120818e
JF		 4564 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4565 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4566#endif
b120818e
JF		 4567
4568 /* reconfigure the hardware */
4569 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4570 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4571 DCB_TX_CONFIG);
4572 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4573 DCB_RX_CONFIG);
4574 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4575 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4576 ixgbe_dcb_hw_ets(&adapter->hw,
4577 adapter->ixgbe_ieee_ets,
4578 max_frame);
4579 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4580 adapter->ixgbe_ieee_pfc->pfc_en,
4581 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4582 }
8187cd48
JF		 4583
4584 /* Enable RSS Hash per TC */
4585 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4586 u32 msb = 0;
4587 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4588
d411a936
AD		 4589 while (rss_i) {
4590 msb++;
4591 rss_i >>= 1;
4592 }
8187cd48 4593
4ae63730
AD		 4594 /* write msb to all 8 TCs in one write */
4595 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4596 }
2f90b865 4597}
9da712d2
JF		 4598#endif
4599
4600/* Additional bittime to account for IXGBE framing */
4601#define IXGBE_ETH_FRAMING 20
4602
49ce9c2c 4603/**
9da712d2
JF		 4604 * ixgbe_hpbthresh - calculate high water mark for flow control
4605 *
4606 * @adapter: board private structure to calculate for
49ce9c2c 4607 * @pb: packet buffer to calculate
9da712d2
JF		 4608 */
4609static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4610{
4611 struct ixgbe_hw *hw = &adapter->hw;
4612 struct net_device *dev = adapter->netdev;
4613 int link, tc, kb, marker;
4614 u32 dv_id, rx_pba;
4615
4616 /* Calculate max LAN frame size */
4617 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4618
4619#ifdef IXGBE_FCOE
4620 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4621 if ((dev->features & NETIF_F_FCOE_MTU) &&
4622 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4623 (pb == ixgbe_fcoe_get_tc(adapter)))
4624 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4625#endif
e5776620 4626
9da712d2
JF		 4627 /* Calculate delay value for device */
4628 switch (hw->mac.type) {
4629 case ixgbe_mac_X540:
9a75a1ac
DS		 4630 case ixgbe_mac_X550:
4631 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4632 dv_id = IXGBE_DV_X540(link, tc);
4633 break;
4634 default:
4635 dv_id = IXGBE_DV(link, tc);
4636 break;
4637 }
4638
4639 /* Loopback switch introduces additional latency */
4640 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4641 dv_id += IXGBE_B2BT(tc);
4642
4643 /* Delay value is calculated in bit times convert to KB */
4644 kb = IXGBE_BT2KB(dv_id);
4645 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4646
4647 marker = rx_pba - kb;
4648
4649 /* It is possible that the packet buffer is not large enough
4650 * to provide required headroom. In this case throw an error
4651 * to user and a do the best we can.
4652 */
4653 if (marker < 0) {
4654 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4655 "headroom to support flow control."
4656 "Decrease MTU or number of traffic classes\n", pb);
4657 marker = tc + 1;
4658 }
4659
4660 return marker;
4661}
4662
49ce9c2c 4663/**
9da712d2
JF		 4664 * ixgbe_lpbthresh - calculate low water mark for for flow control
4665 *
4666 * @adapter: board private structure to calculate for
49ce9c2c 4667 * @pb: packet buffer to calculate
9da712d2 4668 */
e5776620 4669static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4670{
4671 struct ixgbe_hw *hw = &adapter->hw;
4672 struct net_device *dev = adapter->netdev;
4673 int tc;
4674 u32 dv_id;
4675
4676 /* Calculate max LAN frame size */
4677 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4678
e5776620
JK		 4679#ifdef IXGBE_FCOE
4680 /* FCoE traffic class uses FCOE jumbo frames */
4681 if ((dev->features & NETIF_F_FCOE_MTU) &&
4682 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4683 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4684 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4685#endif
4686
9da712d2
JF		 4687 /* Calculate delay value for device */
4688 switch (hw->mac.type) {
4689 case ixgbe_mac_X540:
9a75a1ac
DS		 4690 case ixgbe_mac_X550:
4691 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4692 dv_id = IXGBE_LOW_DV_X540(tc);
4693 break;
4694 default:
4695 dv_id = IXGBE_LOW_DV(tc);
4696 break;
4697 }
4698
4699 /* Delay value is calculated in bit times convert to KB */
4700 return IXGBE_BT2KB(dv_id);
4701}
4702
4703/*
4704 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4705 */
4706static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4707{
4708 struct ixgbe_hw *hw = &adapter->hw;
4709 int num_tc = netdev_get_num_tc(adapter->netdev);
4710 int i;
4711
4712 if (!num_tc)
4713 num_tc = 1;
4714
9da712d2
JF		 4715 for (i = 0; i < num_tc; i++) {
4716 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4717 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4718
4719 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4720 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4721 hw->fc.low_water[i] = 0;
9da712d2 4722 }
e5776620
JK		 4723
4724 for (; i < MAX_TRAFFIC_CLASS; i++)
4725 hw->fc.high_water[i] = 0;
9da712d2
JF		 4726}
4727
80605c65
JF		 4728static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4729{
80605c65 4730 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4731 int hdrm;
4732 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4733
4734 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4735 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4736 hdrm = 32 << adapter->fdir_pballoc;
4737 else
4738 hdrm = 0;
80605c65 4739
f7e1027f 4740 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4741 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4742}
4743
e4911d57
AD		 4744static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4745{
4746 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4747 struct hlist_node *node2;
e4911d57
AD		 4748 struct ixgbe_fdir_filter *filter;
4749
4750 spin_lock(&adapter->fdir_perfect_lock);
4751
4752 if (!hlist_empty(&adapter->fdir_filter_list))
4753 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4754
b67bfe0d 4755 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4756 &adapter->fdir_filter_list, fdir_node) {
4757 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4758 &filter->filter,
4759 filter->sw_idx,
4760 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4761 IXGBE_FDIR_DROP_QUEUE :
4762 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4763 }
4764
4765 spin_unlock(&adapter->fdir_perfect_lock);
4766}
4767
2a47fa45
JF		 4768static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4769 struct ixgbe_adapter *adapter)
4770{
4771 struct ixgbe_hw *hw = &adapter->hw;
4772 u32 vmolr;
4773
4774 /* No unicast promiscuous support for VMDQ devices. */
4775 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4776 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4777
4778 /* clear the affected bit */
4779 vmolr &= ~IXGBE_VMOLR_MPE;
4780
4781 if (dev->flags & IFF_ALLMULTI) {
4782 vmolr |= IXGBE_VMOLR_MPE;
4783 } else {
4784 vmolr |= IXGBE_VMOLR_ROMPE;
4785 hw->mac.ops.update_mc_addr_list(hw, dev);
4786 }
5d7daa35 4787 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4788 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4789}
4790
2a47fa45
JF		 4791static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4792{
4793 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4794 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4795 struct ixgbe_hw *hw = &adapter->hw;
4796 u16 pool = vadapter->pool;
4797 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4798 IXGBE_PSRTYPE_UDPHDR |
4799 IXGBE_PSRTYPE_IPV4HDR |
4800 IXGBE_PSRTYPE_L2HDR |
4801 IXGBE_PSRTYPE_IPV6HDR;
4802
4803 if (hw->mac.type == ixgbe_mac_82598EB)
4804 return;
4805
4806 if (rss_i > 3)
4807 psrtype |= 2 << 29;
4808 else if (rss_i > 1)
4809 psrtype |= 1 << 29;
4810
4811 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4812}
4813
4814/**
4815 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4816 * @rx_ring: ring to free buffers from
4817 **/
4818static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4819{
4820 struct device *dev = rx_ring->dev;
4821 unsigned long size;
4822 u16 i;
4823
4824 /* ring already cleared, nothing to do */
4825 if (!rx_ring->rx_buffer_info)
4826 return;
4827
4828 /* Free all the Rx ring sk_buffs */
4829 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4830 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4831
2a47fa45
JF		 4832 if (rx_buffer->skb) {
4833 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4834 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4835 dma_unmap_page(dev,
4836 IXGBE_CB(skb)->dma,
4837 ixgbe_rx_bufsz(rx_ring),
4838 DMA_FROM_DEVICE);
2a47fa45 4839 dev_kfree_skb(skb);
4d2fcfbc 4840 rx_buffer->skb = NULL;
2a47fa45 4841 }
18cb652a
AD		 4842
4843 if (!rx_buffer->page)
4844 continue;
4845
4846 dma_unmap_page(dev, rx_buffer->dma,
4847 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4848 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4849
2a47fa45
JF		 4850 rx_buffer->page = NULL;
4851 }
4852
4853 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4854 memset(rx_ring->rx_buffer_info, 0, size);
4855
4856 /* Zero out the descriptor ring */
4857 memset(rx_ring->desc, 0, rx_ring->size);
4858
4859 rx_ring->next_to_alloc = 0;
4860 rx_ring->next_to_clean = 0;
4861 rx_ring->next_to_use = 0;
4862}
4863
4864static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4865 struct ixgbe_ring *rx_ring)
4866{
4867 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4868 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4869
4870 /* shutdown specific queue receive and wait for dma to settle */
4871 ixgbe_disable_rx_queue(adapter, rx_ring);
4872 usleep_range(10000, 20000);
4873 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4874 ixgbe_clean_rx_ring(rx_ring);
4875 rx_ring->l2_accel_priv = NULL;
4876}
4877
ae72c8d0
JF		 4878static int ixgbe_fwd_ring_down(struct net_device *vdev,
4879 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4880{
4881 struct ixgbe_adapter *adapter = accel->real_adapter;
4882 unsigned int rxbase = accel->rx_base_queue;
4883 unsigned int txbase = accel->tx_base_queue;
4884 int i;
4885
4886 netif_tx_stop_all_queues(vdev);
4887
4888 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4889 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4890 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4891 }
4892
4893 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4894 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4895 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4896 }
4897
4898
4899 return 0;
4900}
4901
4902static int ixgbe_fwd_ring_up(struct net_device *vdev,
4903 struct ixgbe_fwd_adapter *accel)
4904{
4905 struct ixgbe_adapter *adapter = accel->real_adapter;
4906 unsigned int rxbase, txbase, queues;
4907 int i, baseq, err = 0;
4908
4909 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4910 return 0;
4911
4912 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4913 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4914 accel->pool, adapter->num_rx_pools,
4915 baseq, baseq + adapter->num_rx_queues_per_pool,
4916 adapter->fwd_bitmask);
4917
4918 accel->netdev = vdev;
4919 accel->rx_base_queue = rxbase = baseq;
4920 accel->tx_base_queue = txbase = baseq;
4921
4922 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4923 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4924
4925 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4926 adapter->rx_ring[rxbase + i]->netdev = vdev;
4927 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4928 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4929 }
4930
4931 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4932 adapter->tx_ring[txbase + i]->netdev = vdev;
4933 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4934 }
4935
4936 queues = min_t(unsigned int,
4937 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4938 err = netif_set_real_num_tx_queues(vdev, queues);
4939 if (err)
4940 goto fwd_queue_err;
4941
2a47fa45
JF		 4942 err = netif_set_real_num_rx_queues(vdev, queues);
4943 if (err)
4944 goto fwd_queue_err;
4945
4946 if (is_valid_ether_addr(vdev->dev_addr))
4947 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4948
4949 ixgbe_fwd_psrtype(accel);
4950 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4951 return err;
4952fwd_queue_err:
4953 ixgbe_fwd_ring_down(vdev, accel);
4954 return err;
4955}
4956
4957static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4958{
4959 struct net_device *upper;
4960 struct list_head *iter;
4961 int err;
4962
4963 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4964 if (netif_is_macvlan(upper)) {
4965 struct macvlan_dev *dfwd = netdev_priv(upper);
4966 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4967
4968 if (dfwd->fwd_priv) {
4969 err = ixgbe_fwd_ring_up(upper, vadapter);
4970 if (err)
4971 continue;
4972 }
4973 }
4974 }
4975}
4976
9a799d71
AK		 4977static void ixgbe_configure(struct ixgbe_adapter *adapter)
4978{
d2f5e7f3
AS		 4979 struct ixgbe_hw *hw = &adapter->hw;
4980
80605c65 4981 ixgbe_configure_pb(adapter);
7a6b6f51 4982#ifdef CONFIG_IXGBE_DCB
67ebd791 4983 ixgbe_configure_dcb(adapter);
2f90b865 4984#endif
b35d4d42
AD		 4985 /*
4986 * We must restore virtualization before VLANs or else
4987 * the VLVF registers will not be populated
4988 */
4989 ixgbe_configure_virtualization(adapter);
9a799d71 4990
4c1d7b4b 4991 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4992 ixgbe_restore_vlan(adapter);
4993
d2f5e7f3
AS		 4994 switch (hw->mac.type) {
4995 case ixgbe_mac_82599EB:
4996 case ixgbe_mac_X540:
4997 hw->mac.ops.disable_rx_buff(hw);
4998 break;
4999 default:
5000 break;
5001 }
5002
c4cf55e5 5003 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5004 ixgbe_init_fdir_signature_82599(&adapter->hw,
5005 adapter->fdir_pballoc);
e4911d57
AD		 5006 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5007 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5008 adapter->fdir_pballoc);
5009 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5010 }
4c1d7b4b 5011
d2f5e7f3
AS		 5012 switch (hw->mac.type) {
5013 case ixgbe_mac_82599EB:
5014 case ixgbe_mac_X540:
5015 hw->mac.ops.enable_rx_buff(hw);
5016 break;
5017 default:
5018 break;
5019 }
5020
9de7605e
MR		 5021#ifdef CONFIG_IXGBE_DCA
5022 /* configure DCA */
5023 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5024 ixgbe_setup_dca(adapter);
5025#endif /* CONFIG_IXGBE_DCA */
5026
7c8ae65a
AD		 5027#ifdef IXGBE_FCOE
5028 /* configure FCoE L2 filters, redirection table, and Rx control */
5029 ixgbe_configure_fcoe(adapter);
5030
5031#endif /* IXGBE_FCOE */
9a799d71
AK		 5032 ixgbe_configure_tx(adapter);
5033 ixgbe_configure_rx(adapter);
2a47fa45 5034 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5035}
5036
0ecc061d 5037/**
e8e26350
PW		 5038 * ixgbe_sfp_link_config - set up SFP+ link
5039 * @adapter: pointer to private adapter struct
5040 **/
5041static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5042{
7086400d 5043 /*
52f33af8 5044 * We are assuming the worst case scenario here, and that
7086400d
AD		 5045 * is that an SFP was inserted/removed after the reset
5046 * but before SFP detection was enabled. As such the best
5047 * solution is to just start searching as soon as we start
5048 */
5049 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5050 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5051
7086400d 5052 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5053 adapter->sfp_poll_time = 0;
e8e26350
PW		 5054}
5055
5056/**
5057 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5058 * @hw: pointer to private hardware struct
5059 *
5060 * Returns 0 on success, negative on failure
5061 **/
e8e26350 5062static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5063{
3d292265
JH		 5064 u32 speed;
5065 bool autoneg, link_up = false;
a1e869de 5066 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5067
5068 if (hw->mac.ops.check_link)
3d292265 5069 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5070
5071 if (ret)
e90dd264 5072 return ret;
0ecc061d 5073
3d292265
JH		 5074 speed = hw->phy.autoneg_advertised;
5075 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5076 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5077 &autoneg);
0ecc061d 5078 if (ret)
e90dd264 5079 return ret;
0ecc061d 5080
8620a103 5081 if (hw->mac.ops.setup_link)
fd0326f2 5082 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5083
0ecc061d
PWJ		 5084 return ret;
5085}
5086
a34bcfff 5087static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5088{
9a799d71 5089 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5090 u32 gpie = 0;
9a799d71 5091
9b471446 5092 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5093 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5094 IXGBE_GPIE_OCD;
5095 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5096 /*
5097 * use EIAM to auto-mask when MSI-X interrupt is asserted
5098 * this saves a register write for every interrupt
5099 */
5100 switch (hw->mac.type) {
5101 case ixgbe_mac_82598EB:
5102 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5103 break;
9b471446 5104 case ixgbe_mac_82599EB:
b93a2226 5105 case ixgbe_mac_X540:
9a75a1ac
DS		 5106 case ixgbe_mac_X550:
5107 case ixgbe_mac_X550EM_x:
b93a2226 5108 default:
9b471446
JB		 5109 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5110 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5111 break;
5112 }
5113 } else {
021230d4
AV		 5114 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5115 * specifically only auto mask tx and rx interrupts */
5116 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5117 }
9a799d71 5118
a34bcfff
AD		 5119 /* XXX: to interrupt immediately for EICS writes, enable this */
5120 /* gpie |= IXGBE_GPIE_EIMEN; */
5121
5122 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5123 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5124
5125 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5126 case IXGBE_82599_VMDQ_8Q_MASK:
5127 gpie |= IXGBE_GPIE_VTMODE_16;
5128 break;
5129 case IXGBE_82599_VMDQ_4Q_MASK:
5130 gpie |= IXGBE_GPIE_VTMODE_32;
5131 break;
5132 default:
5133 gpie |= IXGBE_GPIE_VTMODE_64;
5134 break;
5135 }
119fc60a
MC		 5136 }
5137
5fdd31f9 5138 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5139 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5140 switch (adapter->hw.mac.type) {
5141 case ixgbe_mac_82599EB:
9a900eca 5142 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5143 break;
f3df98ec
DS		 5144 default:
5145 break;
5146 }
5147 }
5fdd31f9 5148
a34bcfff
AD		 5149 /* Enable fan failure interrupt */
5150 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5151 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5152
a023bbd0
DS		 5153 switch (hw->mac.type) {
5154 case ixgbe_mac_82599EB:
5155 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5156 break;
5157 case ixgbe_mac_X550EM_x:
5158 gpie |= IXGBE_SDP0_GPIEN_X540;
5159 break;
5160 default:
5161 break;
2698b208 5162 }
a34bcfff
AD		 5163
5164 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5165}
5166
c7ccde0f 5167static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5168{
5169 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5170 int err;
a34bcfff
AD		 5171 u32 ctrl_ext;
5172
5173 ixgbe_get_hw_control(adapter);
5174 ixgbe_setup_gpie(adapter);
e8e26350 5175
9a799d71
AK		 5176 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5177 ixgbe_configure_msix(adapter);
5178 else
5179 ixgbe_configure_msi_and_legacy(adapter);
5180
ec74a471
ET		 5181 /* enable the optics for 82599 SFP+ fiber */
5182 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5183 hw->mac.ops.enable_tx_laser(hw);
5184
961fac88
DS		 5185 if (hw->phy.ops.set_phy_power)
5186 hw->phy.ops.set_phy_power(hw, true);
5187
4e857c58 5188 smp_mb__before_atomic();
9a799d71 5189 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5190 ixgbe_napi_enable_all(adapter);
5191
73c4b7cd
AD		 5192 if (ixgbe_is_sfp(hw)) {
5193 ixgbe_sfp_link_config(adapter);
5194 } else {
5195 err = ixgbe_non_sfp_link_config(hw);
5196 if (err)
5197 e_err(probe, "link_config FAILED %d\n", err);
5198 }
5199
021230d4
AV		 5200 /* clear any pending interrupts, may auto mask */
5201 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5202 ixgbe_irq_enable(adapter, true, true);
9a799d71 5203
bf069c97
DS		 5204 /*
5205 * If this adapter has a fan, check to see if we had a failure
5206 * before we enabled the interrupt.
5207 */
5208 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5209 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5210 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5211 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5212 }
5213
9a799d71
AK		 5214 /* bring the link up in the watchdog, this could race with our first
5215 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5216 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5217 adapter->link_check_timeout = jiffies;
7086400d 5218 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5219
5220 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5221 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5222 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5223 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5224}
5225
d4f80882
AV		 5226void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5227{
5228 WARN_ON(in_interrupt());
7086400d
AD		 5229 /* put off any impending NetWatchDogTimeout */
5230 adapter->netdev->trans_start = jiffies;
5231
d4f80882 5232 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5233 usleep_range(1000, 2000);
d4f80882 5234 ixgbe_down(adapter);
5809a1ae
GR		 5235 /*
5236 * If SR-IOV enabled then wait a bit before bringing the adapter
5237 * back up to give the VFs time to respond to the reset. The
5238 * two second wait is based upon the watchdog timer cycle in
5239 * the VF driver.
5240 */
5241 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5242 msleep(2000);
d4f80882
AV		 5243 ixgbe_up(adapter);
5244 clear_bit(__IXGBE_RESETTING, &adapter->state);
5245}
5246
c7ccde0f 5247void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5248{
5249 /* hardware has been reset, we need to reload some things */
5250 ixgbe_configure(adapter);
5251
c7ccde0f 5252 ixgbe_up_complete(adapter);
9a799d71
AK		 5253}
5254
5255void ixgbe_reset(struct ixgbe_adapter *adapter)
5256{
c44ade9e 5257 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5258 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5259 int err;
5260
b0483c8f
MR		 5261 if (ixgbe_removed(hw->hw_addr))
5262 return;
7086400d
AD		 5263 /* lock SFP init bit to prevent race conditions with the watchdog */
5264 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5265 usleep_range(1000, 2000);
5266
5267 /* clear all SFP and link config related flags while holding SFP_INIT */
5268 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5269 IXGBE_FLAG2_SFP_NEEDS_RESET);
5270 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5271
8ca783ab 5272 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5273 switch (err) {
5274 case 0:
5275 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5276 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5277 break;
5278 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5279 e_dev_err("master disable timed out\n");
da4dd0f7 5280 break;
794caeb2
PWJ		 5281 case IXGBE_ERR_EEPROM_VERSION:
5282 /* We are running on a pre-production device, log a warning */
849c4542 5283 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5284 "Please be aware there may be issues associated with "
849c4542
ET		 5285 "your hardware. If you are experiencing problems "
5286 "please contact your Intel or hardware "
5287 "representative who provided you with this "
5288 "hardware.\n");
794caeb2 5289 break;
da4dd0f7 5290 default:
849c4542 5291 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5292 }
9a799d71 5293
7086400d 5294 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5295
5296 /* flush entries out of MAC table */
5d7daa35 5297 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5298 __dev_uc_unsync(netdev, NULL);
5299
5300 /* do not flush user set addresses */
c9f53e63 5301 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5302
5303 /* update SAN MAC vmdq pool selection */
5304 if (hw->mac.san_mac_rar_index)
5305 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5306
8fecf67c 5307 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5308 ixgbe_ptp_reset(adapter);
961fac88
DS		 5309
5310 if (hw->phy.ops.set_phy_power) {
5311 if (!netif_running(adapter->netdev) && !adapter->wol)
5312 hw->phy.ops.set_phy_power(hw, false);
5313 else
5314 hw->phy.ops.set_phy_power(hw, true);
5315 }
9a799d71
AK		 5316}
5317
9a799d71
AK		 5318/**
5319 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5320 * @tx_ring: ring to be cleaned
5321 **/
b6ec895e 5322static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5323{
5324 struct ixgbe_tx_buffer *tx_buffer_info;
5325 unsigned long size;
b6ec895e 5326 u16 i;
9a799d71 5327
84418e3b
AD		 5328 /* ring already cleared, nothing to do */
5329 if (!tx_ring->tx_buffer_info)
5330 return;
9a799d71 5331
84418e3b 5332 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5333 for (i = 0; i < tx_ring->count; i++) {
5334 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5335 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5336 }
5337
dad8a3b3
JF		 5338 netdev_tx_reset_queue(txring_txq(tx_ring));
5339
9a799d71
AK		 5340 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5341 memset(tx_ring->tx_buffer_info, 0, size);
5342
5343 /* Zero out the descriptor ring */
5344 memset(tx_ring->desc, 0, tx_ring->size);
5345
5346 tx_ring->next_to_use = 0;
5347 tx_ring->next_to_clean = 0;
9a799d71
AK		 5348}
5349
5350/**
021230d4 5351 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5352 * @adapter: board private structure
5353 **/
021230d4 5354static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5355{
5356 int i;
5357
021230d4 5358 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5359 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5360}
5361
5362/**
021230d4 5363 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5364 * @adapter: board private structure
5365 **/
021230d4 5366static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5367{
5368 int i;
5369
021230d4 5370 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5371 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5372}
5373
e4911d57
AD		 5374static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5375{
b67bfe0d 5376 struct hlist_node *node2;
e4911d57
AD		 5377 struct ixgbe_fdir_filter *filter;
5378
5379 spin_lock(&adapter->fdir_perfect_lock);
5380
b67bfe0d 5381 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5382 &adapter->fdir_filter_list, fdir_node) {
5383 hlist_del(&filter->fdir_node);
5384 kfree(filter);
5385 }
5386 adapter->fdir_filter_count = 0;
5387
5388 spin_unlock(&adapter->fdir_perfect_lock);
5389}
5390
9a799d71
AK		 5391void ixgbe_down(struct ixgbe_adapter *adapter)
5392{
5393 struct net_device *netdev = adapter->netdev;
7f821875 5394 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5395 struct net_device *upper;
5396 struct list_head *iter;
bf29ee6c 5397 int i;
9a799d71
AK		 5398
5399 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5400 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5401 return; /* do nothing if already down */
9a799d71
AK		 5402
5403 /* disable receives */
1f9ac57c 5404 hw->mac.ops.disable_rx(hw);
9a799d71 5405
2d39d576
YZ		 5406 /* disable all enabled rx queues */
5407 for (i = 0; i < adapter->num_rx_queues; i++)
5408 /* this call also flushes the previous write */
5409 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5410
032b4325 5411 usleep_range(10000, 20000);
9a799d71 5412
7f821875
JB		 5413 netif_tx_stop_all_queues(netdev);
5414
7086400d 5415 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5416 netif_carrier_off(netdev);
5417 netif_tx_disable(netdev);
5418
2a47fa45
JF		 5419 /* disable any upper devices */
5420 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5421 if (netif_is_macvlan(upper)) {
5422 struct macvlan_dev *vlan = netdev_priv(upper);
5423
5424 if (vlan->fwd_priv) {
5425 netif_tx_stop_all_queues(upper);
5426 netif_carrier_off(upper);
5427 netif_tx_disable(upper);
5428 }
5429 }
5430 }
5431
c0dfb90e
JF		 5432 ixgbe_irq_disable(adapter);
5433
5434 ixgbe_napi_disable_all(adapter);
5435
d034acf1
AD		 5436 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5437 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5438 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5439
5440 del_timer_sync(&adapter->service_timer);
5441
34cecbbf 5442 if (adapter->num_vfs) {
8e34d1aa
AD		 5443 /* Clear EITR Select mapping */
5444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5445
5446 /* Mark all the VFs as inactive */
5447 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5448 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5449
34cecbbf
AD		 5450 /* ping all the active vfs to let them know we are going down */
5451 ixgbe_ping_all_vfs(adapter);
5452
5453 /* Disable all VFTE/VFRE TX/RX */
5454 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5455 }
5456
7f821875
JB		 5457 /* disable transmits in the hardware now that interrupts are off */
5458 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5459 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5460 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5461 }
34cecbbf 5462
9a75a1ac 5463 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5464 switch (hw->mac.type) {
5465 case ixgbe_mac_82599EB:
b93a2226 5466 case ixgbe_mac_X540:
9a75a1ac
DS		 5467 case ixgbe_mac_X550:
5468 case ixgbe_mac_X550EM_x:
88512539 5469 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5470 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5471 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5472 break;
5473 default:
5474 break;
5475 }
7f821875 5476
6f4a0e45
PL		 5477 if (!pci_channel_offline(adapter->pdev))
5478 ixgbe_reset(adapter);
c6ecf39a 5479
ec74a471
ET		 5480 /* power down the optics for 82599 SFP+ fiber */
5481 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5482 hw->mac.ops.disable_tx_laser(hw);
5483
9a799d71
AK		 5484 ixgbe_clean_all_tx_rings(adapter);
5485 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5486}
5487
9a799d71
AK		 5488/**
5489 * ixgbe_tx_timeout - Respond to a Tx Hang
5490 * @netdev: network interface device structure
5491 **/
5492static void ixgbe_tx_timeout(struct net_device *netdev)
5493{
5494 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5495
5496 /* Do the reset outside of interrupt context */
c83c6cbd 5497 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5498}
5499
9a799d71
AK		 5500/**
5501 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5502 * @adapter: board private structure to initialize
5503 *
5504 * ixgbe_sw_init initializes the Adapter private data structure.
5505 * Fields are initialized based on PCI device information and
5506 * OS network device settings (MTU size).
5507 **/
9f9a12f8 5508static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5509{
5510 struct ixgbe_hw *hw = &adapter->hw;
5511 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5512 unsigned int rss, fdir;
cb6d0f5e 5513 u32 fwsm;
7a6b6f51 5514#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5515 int j;
5516 struct tc_configuration *tc;
5517#endif
021230d4 5518
c44ade9e
JB		 5519 /* PCI config space info */
5520
5521 hw->vendor_id = pdev->vendor;
5522 hw->device_id = pdev->device;
5523 hw->revision_id = pdev->revision;
5524 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5525 hw->subsystem_device_id = pdev->subsystem_device;
5526
8fc3bb6d 5527 /* Set common capability flags and settings */
0f9b232b 5528 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5529 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5530 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5531 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5532 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5533 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5534 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5535 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5536#ifdef CONFIG_IXGBE_DCA
5537 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5538#endif
5539#ifdef IXGBE_FCOE
5540 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5541 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5542#ifdef CONFIG_IXGBE_DCB
5543 /* Default traffic class to use for FCoE */
5544 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5545#endif /* CONFIG_IXGBE_DCB */
5546#endif /* IXGBE_FCOE */
5547
5d7daa35
JK		 5548 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5549 hw->mac.num_rar_entries,
5550 GFP_ATOMIC);
530fd82a
AD		 5551 if (!adapter->mac_table)
5552 return -ENOMEM;
5d7daa35 5553
8fc3bb6d 5554 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5555 switch (hw->mac.type) {
5556 case ixgbe_mac_82598EB:
8fc3bb6d 5557 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5558
bf069c97
DS		 5559 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5560 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5561
49c7ffbe 5562 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5563 adapter->ring_feature[RING_F_FDIR].limit = 0;
5564 adapter->atr_sample_rate = 0;
5565 adapter->fdir_pballoc = 0;
5566#ifdef IXGBE_FCOE
5567 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5568 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5569#ifdef CONFIG_IXGBE_DCB
5570 adapter->fcoe.up = 0;
5571#endif /* IXGBE_DCB */
5572#endif /* IXGBE_FCOE */
5573 break;
5574 case ixgbe_mac_82599EB:
5575 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5576 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5577 break;
b93a2226 5578 case ixgbe_mac_X540:
9a900eca 5579 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5580 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5581 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5582 break;
9a75a1ac
DS		 5583 case ixgbe_mac_X550EM_x:
5584 case ixgbe_mac_X550:
5585#ifdef CONFIG_IXGBE_DCA
5586 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5587#endif
5588#ifdef CONFIG_IXGBE_VXLAN
5589 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5590#endif
5591 break;
bd508178
AD		 5592 default:
5593 break;
f8212f97 5594 }
2f90b865 5595
7c8ae65a
AD		 5596#ifdef IXGBE_FCOE
5597 /* FCoE support exists, always init the FCoE lock */
5598 spin_lock_init(&adapter->fcoe.lock);
5599
5600#endif
1fc5f038
AD		 5601 /* n-tuple support exists, always init our spinlock */
5602 spin_lock_init(&adapter->fdir_perfect_lock);
5603
7a6b6f51 5604#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5605 switch (hw->mac.type) {
5606 case ixgbe_mac_X540:
9a75a1ac
DS		 5607 case ixgbe_mac_X550:
5608 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5609 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5610 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5611 break;
5612 default:
5613 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5614 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5615 break;
5616 }
5617
2f90b865
AD		 5618 /* Configure DCB traffic classes */
5619 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5620 tc = &adapter->dcb_cfg.tc_config[j];
5621 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5622 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5623 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5624 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5625 tc->dcb_pfc = pfc_disabled;
5626 }
4de2a022
JF		 5627
5628 /* Initialize default user to priority mapping, UPx->TC0 */
5629 tc = &adapter->dcb_cfg.tc_config[0];
5630 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5631 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5632
2f90b865
AD		 5633 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5634 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5635 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5636 adapter->dcb_set_bitmap = 0x00;
3032309b 5637 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5638 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5639 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5640
5641#endif
9a799d71
AK		 5642
5643 /* default flow control settings */
cd7664f6 5644 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5645 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5646 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5647 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5648 hw->fc.send_xon = true;
73d80953 5649 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5650
99d74487 5651#ifdef CONFIG_PCI_IOV
170e8543
JK		 5652 if (max_vfs > 0)
5653 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5654
99d74487 5655 /* assign number of SR-IOV VFs */
170e8543 5656 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5657 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5658 adapter->num_vfs = 0;
5659 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5660 } else {
5661 adapter->num_vfs = max_vfs;
5662 }
5663 }
5664#endif /* CONFIG_PCI_IOV */
99d74487 5665
30efa5a3 5666 /* enable itr by default in dynamic mode */
f7554a2b 5667 adapter->rx_itr_setting = 1;
f7554a2b 5668 adapter->tx_itr_setting = 1;
30efa5a3 5669
30efa5a3
JB		 5670 /* set default ring sizes */
5671 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5672 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5673
bd198058 5674 /* set default work limits */
59224555 5675 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5676
9a799d71 5677 /* initialize eeprom parameters */
c44ade9e 5678 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5679 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5680 return -EIO;
5681 }
5682
2a47fa45
JF		 5683 /* PF holds first pool slot */
5684 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5685 set_bit(__IXGBE_DOWN, &adapter->state);
5686
5687 return 0;
5688}
5689
5690/**
5691 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5692 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5693 *
5694 * Return 0 on success, negative on failure
5695 **/
b6ec895e 5696int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5697{
b6ec895e 5698 struct device *dev = tx_ring->dev;
de88eeeb 5699 int orig_node = dev_to_node(dev);
ca8dfe25 5700 int ring_node = -1;
9a799d71
AK		 5701 int size;
5702
3a581073 5703 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5704
5705 if (tx_ring->q_vector)
ca8dfe25 5706 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5707
ca8dfe25 5708 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5709 if (!tx_ring->tx_buffer_info)
89bf67f1 5710 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5711 if (!tx_ring->tx_buffer_info)
5712 goto err;
9a799d71 5713
827da44c
JS		 5714 u64_stats_init(&tx_ring->syncp);
5715
9a799d71 5716 /* round up to nearest 4K */
12207e49 5717 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5718 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5719
ca8dfe25 5720 set_dev_node(dev, ring_node);
de88eeeb
AD		 5721 tx_ring->desc = dma_alloc_coherent(dev,
5722 tx_ring->size,
5723 &tx_ring->dma,
5724 GFP_KERNEL);
5725 set_dev_node(dev, orig_node);
5726 if (!tx_ring->desc)
5727 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5728 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5729 if (!tx_ring->desc)
5730 goto err;
9a799d71 5731
3a581073
JB		 5732 tx_ring->next_to_use = 0;
5733 tx_ring->next_to_clean = 0;
9a799d71 5734 return 0;
e01c31a5
JB		 5735
5736err:
5737 vfree(tx_ring->tx_buffer_info);
5738 tx_ring->tx_buffer_info = NULL;
b6ec895e 5739 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5740 return -ENOMEM;
9a799d71
AK		 5741}
5742
69888674
AD		 5743/**
5744 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5745 * @adapter: board private structure
5746 *
5747 * If this function returns with an error, then it's possible one or
5748 * more of the rings is populated (while the rest are not). It is the
5749 * callers duty to clean those orphaned rings.
5750 *
5751 * Return 0 on success, negative on failure
5752 **/
5753static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5754{
5755 int i, err = 0;
5756
5757 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5758 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5759 if (!err)
5760 continue;
de3d5b94 5761
396e799c 5762 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5763 goto err_setup_tx;
69888674
AD		 5764 }
5765
de3d5b94
AD		 5766 return 0;
5767err_setup_tx:
5768 /* rewind the index freeing the rings as we go */
5769 while (i--)
5770 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5771 return err;
5772}
5773
9a799d71
AK		 5774/**
5775 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5776 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5777 *
5778 * Returns 0 on success, negative on failure
5779 **/
b6ec895e 5780int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5781{
b6ec895e 5782 struct device *dev = rx_ring->dev;
de88eeeb 5783 int orig_node = dev_to_node(dev);
ca8dfe25 5784 int ring_node = -1;
021230d4 5785 int size;
9a799d71 5786
3a581073 5787 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5788
5789 if (rx_ring->q_vector)
ca8dfe25 5790 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5791
ca8dfe25 5792 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5793 if (!rx_ring->rx_buffer_info)
89bf67f1 5794 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5795 if (!rx_ring->rx_buffer_info)
5796 goto err;
9a799d71 5797
827da44c
JS		 5798 u64_stats_init(&rx_ring->syncp);
5799
9a799d71 5800 /* Round up to nearest 4K */
3a581073
JB		 5801 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5802 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5803
ca8dfe25 5804 set_dev_node(dev, ring_node);
de88eeeb
AD		 5805 rx_ring->desc = dma_alloc_coherent(dev,
5806 rx_ring->size,
5807 &rx_ring->dma,
5808 GFP_KERNEL);
5809 set_dev_node(dev, orig_node);
5810 if (!rx_ring->desc)
5811 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5812 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5813 if (!rx_ring->desc)
5814 goto err;
9a799d71 5815
3a581073
JB		 5816 rx_ring->next_to_clean = 0;
5817 rx_ring->next_to_use = 0;
9a799d71
AK		 5818
5819 return 0;
b6ec895e
AD		 5820err:
5821 vfree(rx_ring->rx_buffer_info);
5822 rx_ring->rx_buffer_info = NULL;
5823 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5824 return -ENOMEM;
9a799d71
AK		 5825}
5826
69888674
AD		 5827/**
5828 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5829 * @adapter: board private structure
5830 *
5831 * If this function returns with an error, then it's possible one or
5832 * more of the rings is populated (while the rest are not). It is the
5833 * callers duty to clean those orphaned rings.
5834 *
5835 * Return 0 on success, negative on failure
5836 **/
69888674
AD		 5837static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5838{
5839 int i, err = 0;
5840
5841 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5842 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5843 if (!err)
5844 continue;
de3d5b94 5845
396e799c 5846 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5847 goto err_setup_rx;
69888674
AD		 5848 }
5849
7c8ae65a
AD		 5850#ifdef IXGBE_FCOE
5851 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5852 if (!err)
5853#endif
5854 return 0;
de3d5b94
AD		 5855err_setup_rx:
5856 /* rewind the index freeing the rings as we go */
5857 while (i--)
5858 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5859 return err;
5860}
5861
9a799d71
AK		 5862/**
5863 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5864 * @tx_ring: Tx descriptor ring for a specific queue
5865 *
5866 * Free all transmit software resources
5867 **/
b6ec895e 5868void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5869{
b6ec895e 5870 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5871
5872 vfree(tx_ring->tx_buffer_info);
5873 tx_ring->tx_buffer_info = NULL;
5874
b6ec895e
AD		 5875 /* if not set, then don't free */
5876 if (!tx_ring->desc)
5877 return;
5878
5879 dma_free_coherent(tx_ring->dev, tx_ring->size,
5880 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5881
5882 tx_ring->desc = NULL;
5883}
5884
5885/**
5886 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5887 * @adapter: board private structure
5888 *
5889 * Free all transmit software resources
5890 **/
5891static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5892{
5893 int i;
5894
5895 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5896 if (adapter->tx_ring[i]->desc)
b6ec895e 5897 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5898}
5899
5900/**
b4617240 5901 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5902 * @rx_ring: ring to clean the resources from
5903 *
5904 * Free all receive software resources
5905 **/
b6ec895e 5906void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5907{
b6ec895e 5908 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5909
5910 vfree(rx_ring->rx_buffer_info);
5911 rx_ring->rx_buffer_info = NULL;
5912
b6ec895e
AD		 5913 /* if not set, then don't free */
5914 if (!rx_ring->desc)
5915 return;
5916
5917 dma_free_coherent(rx_ring->dev, rx_ring->size,
5918 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5919
5920 rx_ring->desc = NULL;
5921}
5922
5923/**
5924 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5925 * @adapter: board private structure
5926 *
5927 * Free all receive software resources
5928 **/
5929static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5930{
5931 int i;
5932
7c8ae65a
AD		 5933#ifdef IXGBE_FCOE
5934 ixgbe_free_fcoe_ddp_resources(adapter);
5935
5936#endif
9a799d71 5937 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5938 if (adapter->rx_ring[i]->desc)
b6ec895e 5939 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5940}
5941
9a799d71
AK		 5942/**
5943 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5944 * @netdev: network interface device structure
5945 * @new_mtu: new value for maximum frame size
5946 *
5947 * Returns 0 on success, negative on failure
5948 **/
5949static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5950{
5951 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5952 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5953
42c783c5 5954 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5955 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5956 return -EINVAL;
5957
5958 /*
872844dd
AD		 5959 * For 82599EB we cannot allow legacy VFs to enable their receive
5960 * paths when MTU greater than 1500 is configured. So display a
5961 * warning that legacy VFs will be disabled.
655309e9
AD		 5962 */
5963 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5964 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5965 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5966 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5967
396e799c 5968 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5969
021230d4 5970 /* must set new MTU before calling down or up */
9a799d71
AK		 5971 netdev->mtu = new_mtu;
5972
d4f80882
AV		 5973 if (netif_running(netdev))
5974 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5975
5976 return 0;
5977}
5978
5979/**
5980 * ixgbe_open - Called when a network interface is made active
5981 * @netdev: network interface device structure
5982 *
5983 * Returns 0 on success, negative value on failure
5984 *
5985 * The open entry point is called when a network interface is made
5986 * active by the system (IFF_UP). At this point all resources needed
5987 * for transmit and receive operations are allocated, the interrupt
5988 * handler is registered with the OS, the watchdog timer is started,
5989 * and the stack is notified that the interface is ready.
5990 **/
5991static int ixgbe_open(struct net_device *netdev)
5992{
5993 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5994 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5995 int err, queues;
4bebfaa5
AK		 5996
5997 /* disallow open during test */
5998 if (test_bit(__IXGBE_TESTING, &adapter->state))
5999 return -EBUSY;
9a799d71 6000
54386467
JB		 6001 netif_carrier_off(netdev);
6002
9a799d71
AK		 6003 /* allocate transmit descriptors */
6004 err = ixgbe_setup_all_tx_resources(adapter);
6005 if (err)
6006 goto err_setup_tx;
6007
9a799d71
AK		 6008 /* allocate receive descriptors */
6009 err = ixgbe_setup_all_rx_resources(adapter);
6010 if (err)
6011 goto err_setup_rx;
6012
6013 ixgbe_configure(adapter);
6014
021230d4 6015 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6016 if (err)
6017 goto err_req_irq;
6018
ac802f5d 6019 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6020 if (adapter->num_rx_pools > 1)
6021 queues = adapter->num_rx_queues_per_pool;
6022 else
6023 queues = adapter->num_tx_queues;
6024
6025 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6026 if (err)
6027 goto err_set_queues;
6028
2a47fa45
JF		 6029 if (adapter->num_rx_pools > 1 &&
6030 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6031 queues = IXGBE_MAX_L2A_QUEUES;
6032 else
6033 queues = adapter->num_rx_queues;
6034 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6035 if (err)
6036 goto err_set_queues;
6037
1a71ab24 6038 ixgbe_ptp_init(adapter);
1a71ab24 6039
c7ccde0f 6040 ixgbe_up_complete(adapter);
9a799d71 6041
67359c3c
MR		 6042 ixgbe_clear_vxlan_port(adapter);
6043#ifdef CONFIG_IXGBE_VXLAN
3f207800 6044 vxlan_get_rx_port(netdev);
3f207800 6045#endif
67359c3c 6046
9a799d71
AK		 6047 return 0;
6048
ac802f5d
AD		 6049err_set_queues:
6050 ixgbe_free_irq(adapter);
9a799d71 6051err_req_irq:
a20a1199 6052 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6053 if (hw->phy.ops.set_phy_power && !adapter->wol)
6054 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6055err_setup_rx:
a20a1199 6056 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6057err_setup_tx:
9a799d71
AK		 6058 ixgbe_reset(adapter);
6059
6060 return err;
6061}
6062
a0cccce2
JK		 6063static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6064{
6065 ixgbe_ptp_suspend(adapter);
6066
6ac74394
DS		 6067 if (adapter->hw.phy.ops.enter_lplu) {
6068 adapter->hw.phy.reset_disable = true;
6069 ixgbe_down(adapter);
6070 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6071 adapter->hw.phy.reset_disable = false;
6072 } else {
6073 ixgbe_down(adapter);
6074 }
6075
a0cccce2
JK		 6076 ixgbe_free_irq(adapter);
6077
6078 ixgbe_free_all_tx_resources(adapter);
6079 ixgbe_free_all_rx_resources(adapter);
6080}
6081
9a799d71
AK		 6082/**
6083 * ixgbe_close - Disables a network interface
6084 * @netdev: network interface device structure
6085 *
6086 * Returns 0, this is not allowed to fail
6087 *
6088 * The close entry point is called when an interface is de-activated
6089 * by the OS. The hardware is still under the drivers control, but
6090 * needs to be disabled. A global MAC reset is issued to stop the
6091 * hardware, and all transmit and receive resources are freed.
6092 **/
6093static int ixgbe_close(struct net_device *netdev)
6094{
6095 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6096
1a71ab24 6097 ixgbe_ptp_stop(adapter);
1a71ab24 6098
a0cccce2 6099 ixgbe_close_suspend(adapter);
9a799d71 6100
e4911d57
AD		 6101 ixgbe_fdir_filter_exit(adapter);
6102
5eba3699 6103 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6104
6105 return 0;
6106}
6107
b3c8b4ba
AD		 6108#ifdef CONFIG_PM
6109static int ixgbe_resume(struct pci_dev *pdev)
6110{
c60fbb00
AD		 6111 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6112 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6113 u32 err;
6114
0391bbe3 6115 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6116 pci_set_power_state(pdev, PCI_D0);
6117 pci_restore_state(pdev);
656ab817
DS		 6118 /*
6119 * pci_restore_state clears dev->state_saved so call
6120 * pci_save_state to restore it.
6121 */
6122 pci_save_state(pdev);
9ce77666 6123
6124 err = pci_enable_device_mem(pdev);
b3c8b4ba 6125 if (err) {
849c4542 6126 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6127 return err;
6128 }
4e857c58 6129 smp_mb__before_atomic();
41c62843 6130 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6131 pci_set_master(pdev);
6132
dd4d8ca6 6133 pci_wake_from_d3(pdev, false);
b3c8b4ba 6134
b3c8b4ba
AD		 6135 ixgbe_reset(adapter);
6136
495dce12
WJP		 6137 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6138
ac802f5d
AD		 6139 rtnl_lock();
6140 err = ixgbe_init_interrupt_scheme(adapter);
6141 if (!err && netif_running(netdev))
c60fbb00 6142 err = ixgbe_open(netdev);
ac802f5d
AD		 6143
6144 rtnl_unlock();
6145
6146 if (err)
6147 return err;
b3c8b4ba
AD		 6148
6149 netif_device_attach(netdev);
6150
6151 return 0;
6152}
b3c8b4ba 6153#endif /* CONFIG_PM */
9d8d05ae
RW		 6154
6155static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6156{
c60fbb00
AD		 6157 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6158 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6159 struct ixgbe_hw *hw = &adapter->hw;
6160 u32 ctrl, fctrl;
6161 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6162#ifdef CONFIG_PM
6163 int retval = 0;
6164#endif
6165
6166 netif_device_detach(netdev);
6167
499ab5cc 6168 rtnl_lock();
a0cccce2
JK		 6169 if (netif_running(netdev))
6170 ixgbe_close_suspend(adapter);
499ab5cc 6171 rtnl_unlock();
b3c8b4ba 6172
5f5ae6fc
AD		 6173 ixgbe_clear_interrupt_scheme(adapter);
6174
b3c8b4ba
AD		 6175#ifdef CONFIG_PM
6176 retval = pci_save_state(pdev);
6177 if (retval)
6178 return retval;
4df10466 6179
b3c8b4ba 6180#endif
f4f1040a
JK		 6181 if (hw->mac.ops.stop_link_on_d3)
6182 hw->mac.ops.stop_link_on_d3(hw);
6183
e8e26350
PW		 6184 if (wufc) {
6185 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6186
ec74a471
ET		 6187 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6188 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6189 hw->mac.ops.enable_tx_laser(hw);
6190
e8e26350
PW		 6191 /* turn on all-multi mode if wake on multicast is enabled */
6192 if (wufc & IXGBE_WUFC_MC) {
6193 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6194 fctrl |= IXGBE_FCTRL_MPE;
6195 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6196 }
6197
6198 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6199 ctrl |= IXGBE_CTRL_GIO_DIS;
6200 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6201
6202 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6203 } else {
6204 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6205 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6206 }
6207
bd508178
AD		 6208 switch (hw->mac.type) {
6209 case ixgbe_mac_82598EB:
dd4d8ca6 6210 pci_wake_from_d3(pdev, false);
bd508178
AD		 6211 break;
6212 case ixgbe_mac_82599EB:
b93a2226 6213 case ixgbe_mac_X540:
9a75a1ac
DS		 6214 case ixgbe_mac_X550:
6215 case ixgbe_mac_X550EM_x:
bd508178
AD		 6216 pci_wake_from_d3(pdev, !!wufc);
6217 break;
6218 default:
6219 break;
6220 }
b3c8b4ba 6221
9d8d05ae 6222 *enable_wake = !!wufc;
961fac88
DS		 6223 if (hw->phy.ops.set_phy_power && !*enable_wake)
6224 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6225
b3c8b4ba
AD		 6226 ixgbe_release_hw_control(adapter);
6227
41c62843
MR		 6228 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6229 pci_disable_device(pdev);
b3c8b4ba 6230
9d8d05ae
RW		 6231 return 0;
6232}
6233
6234#ifdef CONFIG_PM
6235static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6236{
6237 int retval;
6238 bool wake;
6239
6240 retval = __ixgbe_shutdown(pdev, &wake);
6241 if (retval)
6242 return retval;
6243
6244 if (wake) {
6245 pci_prepare_to_sleep(pdev);
6246 } else {
6247 pci_wake_from_d3(pdev, false);
6248 pci_set_power_state(pdev, PCI_D3hot);
6249 }
b3c8b4ba
AD		 6250
6251 return 0;
6252}
9d8d05ae 6253#endif /* CONFIG_PM */
b3c8b4ba
AD		 6254
6255static void ixgbe_shutdown(struct pci_dev *pdev)
6256{
9d8d05ae
RW		 6257 bool wake;
6258
6259 __ixgbe_shutdown(pdev, &wake);
6260
6261 if (system_state == SYSTEM_POWER_OFF) {
6262 pci_wake_from_d3(pdev, wake);
6263 pci_set_power_state(pdev, PCI_D3hot);
6264 }
b3c8b4ba
AD		 6265}
6266
9a799d71
AK		 6267/**
6268 * ixgbe_update_stats - Update the board statistics counters.
6269 * @adapter: board private structure
6270 **/
6271void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6272{
2d86f139 6273 struct net_device *netdev = adapter->netdev;
9a799d71 6274 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6275 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6276 u64 total_mpc = 0;
6277 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6278 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6279 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6280 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6281
d08935c2
DS		 6282 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6283 test_bit(__IXGBE_RESETTING, &adapter->state))
6284 return;
6285
94b982b2 6286 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6287 u64 rsc_count = 0;
94b982b2 6288 u64 rsc_flush = 0;
94b982b2 6289 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6290 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6291 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6292 }
6293 adapter->rsc_total_count = rsc_count;
6294 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6295 }
6296
5b7da515
AD		 6297 for (i = 0; i < adapter->num_rx_queues; i++) {
6298 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6299 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6300 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6301 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6302 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6303 bytes += rx_ring->stats.bytes;
6304 packets += rx_ring->stats.packets;
6305 }
6306 adapter->non_eop_descs = non_eop_descs;
6307 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6308 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6309 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6310 netdev->stats.rx_bytes = bytes;
6311 netdev->stats.rx_packets = packets;
6312
6313 bytes = 0;
6314 packets = 0;
7ca3bc58 6315 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6316 for (i = 0; i < adapter->num_tx_queues; i++) {
6317 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6318 restart_queue += tx_ring->tx_stats.restart_queue;
6319 tx_busy += tx_ring->tx_stats.tx_busy;
6320 bytes += tx_ring->stats.bytes;
6321 packets += tx_ring->stats.packets;
6322 }
eb985f09 6323 adapter->restart_queue = restart_queue;
5b7da515
AD		 6324 adapter->tx_busy = tx_busy;
6325 netdev->stats.tx_bytes = bytes;
6326 netdev->stats.tx_packets = packets;
7ca3bc58 6327
7ca647bd 6328 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6329
6330 /* 8 register reads */
6f11eef7
AV		 6331 for (i = 0; i < 8; i++) {
6332 /* for packet buffers not used, the register should read 0 */
6333 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6334 missed_rx += mpc;
7ca647bd
JP		 6335 hwstats->mpc[i] += mpc;
6336 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6337 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6338 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6339 switch (hw->mac.type) {
6340 case ixgbe_mac_82598EB:
1a70db4b
ET		 6341 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6342 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6343 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6344 hwstats->pxonrxc[i] +=
6345 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6346 break;
6347 case ixgbe_mac_82599EB:
b93a2226 6348 case ixgbe_mac_X540:
9a75a1ac
DS		 6349 case ixgbe_mac_X550:
6350 case ixgbe_mac_X550EM_x:
bd508178
AD		 6351 hwstats->pxonrxc[i] +=
6352 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6353 break;
6354 default:
6355 break;
e8e26350 6356 }
6f11eef7 6357 }
1a70db4b
ET		 6358
6359 /*16 register reads */
6360 for (i = 0; i < 16; i++) {
6361 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6362 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6363 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6364 (hw->mac.type == ixgbe_mac_X540) ||
6365 (hw->mac.type == ixgbe_mac_X550) ||
6366 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6367 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6368 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6369 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6370 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6371 }
6372 }
6373
7ca647bd 6374 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6375 /* work around hardware counting issue */
7ca647bd 6376 hwstats->gprc -= missed_rx;
6f11eef7 6377
c84d324c
JF		 6378 ixgbe_update_xoff_received(adapter);
6379
6f11eef7 6380 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6381 switch (hw->mac.type) {
6382 case ixgbe_mac_82598EB:
6383 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6384 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6385 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6386 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6387 break;
b93a2226 6388 case ixgbe_mac_X540:
9a75a1ac
DS		 6389 case ixgbe_mac_X550:
6390 case ixgbe_mac_X550EM_x:
6391 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6392 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6393 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6394 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6395 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6396 case ixgbe_mac_82599EB:
a4d4f629
AD		 6397 for (i = 0; i < 16; i++)
6398 adapter->hw_rx_no_dma_resources +=
6399 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6400 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6401 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6402 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6403 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6404 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6405 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6406 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6407 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6408 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6409#ifdef IXGBE_FCOE
7ca647bd
JP		 6410 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6411 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6412 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6413 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6414 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6415 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6416 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6417 if (adapter->fcoe.ddp_pool) {
6418 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6419 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6420 unsigned int cpu;
6421 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6422 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6423 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6424 noddp += ddp_pool->noddp;
6425 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6426 }
5a1ee270
AD		 6427 hwstats->fcoe_noddp = noddp;
6428 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6429 }
6d45522c 6430#endif /* IXGBE_FCOE */
bd508178
AD		 6431 break;
6432 default:
6433 break;
e8e26350 6434 }
9a799d71 6435 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6436 hwstats->bprc += bprc;
6437 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6438 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6439 hwstats->mprc -= bprc;
6440 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6441 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6442 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6443 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6444 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6445 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6446 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6447 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6448 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6449 hwstats->lxontxc += lxon;
6f11eef7 6450 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6451 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6452 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6453 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6454 /*
6455 * 82598 errata - tx of flow control packets is included in tx counters
6456 */
6457 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6458 hwstats->gptc -= xon_off_tot;
6459 hwstats->mptc -= xon_off_tot;
6460 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6461 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6462 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6463 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6464 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6465 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6466 hwstats->ptc64 -= xon_off_tot;
6467 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6468 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6469 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6470 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6471 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6472 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6473
6474 /* Fill out the OS statistics structure */
7ca647bd 6475 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6476
6477 /* Rx Errors */
7ca647bd 6478 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6479 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6480 netdev->stats.rx_length_errors = hwstats->rlec;
6481 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6482 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6483}
6484
6485/**
d034acf1 6486 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6487 * @adapter: pointer to the device adapter structure
9a799d71 6488 **/
d034acf1 6489static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6490{
cf8280ee 6491 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6492 int i;
cf8280ee 6493
d034acf1
AD		 6494 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6495 return;
6496
6497 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6498
d034acf1 6499 /* if interface is down do nothing */
fe49f04a 6500 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6501 return;
6502
6503 /* do nothing if we are not using signature filters */
6504 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6505 return;
6506
6507 adapter->fdir_overflow++;
6508
93c52dd0
AD		 6509 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6510 for (i = 0; i < adapter->num_tx_queues; i++)
6511 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6512 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6513 /* re-enable flow director interrupts */
6514 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6515 } else {
6516 e_err(probe, "failed to finish FDIR re-initialization, "
6517 "ignored adding FDIR ATR filters\n");
6518 }
93c52dd0
AD		 6519}
6520
6521/**
6522 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6523 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6524 *
6525 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6526 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6527 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6528 * determine if a hang has occurred.
93c52dd0
AD		 6529 */
6530static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6531{
cf8280ee 6532 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6533 u64 eics = 0;
6534 int i;
cf8280ee 6535
09f40aed 6536 /* If we're down, removing or resetting, just bail */
93c52dd0 6537 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6538 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6539 test_bit(__IXGBE_RESETTING, &adapter->state))
6540 return;
22d5a71b 6541
93c52dd0
AD		 6542 /* Force detection of hung controller */
6543 if (netif_carrier_ok(adapter->netdev)) {
6544 for (i = 0; i < adapter->num_tx_queues; i++)
6545 set_check_for_tx_hang(adapter->tx_ring[i]);
6546 }
22d5a71b 6547
fe49f04a
AD		 6548 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6549 /*
6550 * for legacy and MSI interrupts don't set any bits
6551 * that are enabled for EIAM, because this operation
6552 * would set *both* EIMS and EICS for any bit in EIAM
6553 */
6554 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6555 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6556 } else {
6557 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6558 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6559 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6560 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6561 eics |= ((u64)1 << i);
6562 }
cf8280ee 6563 }
9a799d71 6564
93c52dd0 6565 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6566 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6567}
6568
e8e26350 6569/**
93c52dd0 6570 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6571 * @adapter: pointer to the device adapter structure
6572 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6573 **/
93c52dd0 6574static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6575{
e8e26350 6576 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6577 u32 link_speed = adapter->link_speed;
6578 bool link_up = adapter->link_up;
041441d0 6579 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6580
93c52dd0
AD		 6581 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6582 return;
6583
6584 if (hw->mac.ops.check_link) {
6585 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6586 } else {
93c52dd0
AD		 6587 /* always assume link is up, if no check link function */
6588 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6589 link_up = true;
c4cf55e5 6590 }
041441d0
AD		 6591
6592 if (adapter->ixgbe_ieee_pfc)
6593 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6594
3ebe8fde 6595 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6596 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6597 ixgbe_set_rx_drop_en(adapter);
6598 }
93c52dd0
AD		 6599
6600 if (link_up ||
6601 time_after(jiffies, (adapter->link_check_timeout +
6602 IXGBE_TRY_LINK_TIMEOUT))) {
6603 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6604 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6605 IXGBE_WRITE_FLUSH(hw);
6606 }
6607
6608 adapter->link_up = link_up;
6609 adapter->link_speed = link_speed;
e8e26350
PW		 6610}
6611
107d3018
AD		 6612static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6613{
6614#ifdef CONFIG_IXGBE_DCB
6615 struct net_device *netdev = adapter->netdev;
6616 struct dcb_app app = {
6617 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6618 .protocol = 0,
6619 };
6620 u8 up = 0;
6621
6622 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6623 up = dcb_ieee_getapp_mask(netdev, &app);
6624
6625 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6626#endif
6627}
6628
e8e26350 6629/**
93c52dd0
AD		 6630 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6631 * print link up message
49ce9c2c 6632 * @adapter: pointer to the device adapter structure
e8e26350 6633 **/
93c52dd0 6634static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6635{
93c52dd0 6636 struct net_device *netdev = adapter->netdev;
e8e26350 6637 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6638 struct net_device *upper;
6639 struct list_head *iter;
93c52dd0 6640 u32 link_speed = adapter->link_speed;
454adb00 6641 const char *speed_str;
93c52dd0 6642 bool flow_rx, flow_tx;
e8e26350 6643
93c52dd0
AD		 6644 /* only continue if link was previously down */
6645 if (netif_carrier_ok(netdev))
a985b6c3 6646 return;
63d6e1d8 6647
93c52dd0 6648 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6649
93c52dd0
AD		 6650 switch (hw->mac.type) {
6651 case ixgbe_mac_82598EB: {
6652 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6653 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6654 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6655 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6656 }
6657 break;
6658 case ixgbe_mac_X540:
9a75a1ac
DS		 6659 case ixgbe_mac_X550:
6660 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6661 case ixgbe_mac_82599EB: {
6662 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6663 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6664 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6665 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6666 }
6667 break;
6668 default:
6669 flow_tx = false;
6670 flow_rx = false;
6671 break;
e8e26350 6672 }
3a6a4eda 6673
6cb562d6
JK		 6674 adapter->last_rx_ptp_check = jiffies;
6675
8fecf67c 6676 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6677 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6678
454adb00
MR		 6679 switch (link_speed) {
6680 case IXGBE_LINK_SPEED_10GB_FULL:
6681 speed_str = "10 Gbps";
6682 break;
6683 case IXGBE_LINK_SPEED_2_5GB_FULL:
6684 speed_str = "2.5 Gbps";
6685 break;
6686 case IXGBE_LINK_SPEED_1GB_FULL:
6687 speed_str = "1 Gbps";
6688 break;
6689 case IXGBE_LINK_SPEED_100_FULL:
6690 speed_str = "100 Mbps";
6691 break;
6692 default:
6693 speed_str = "unknown speed";
6694 break;
6695 }
6696 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6697 ((flow_rx && flow_tx) ? "RX/TX" :
6698 (flow_rx ? "RX" :
6699 (flow_tx ? "TX" : "None"))));
e8e26350 6700
93c52dd0 6701 netif_carrier_on(netdev);
93c52dd0 6702 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6703
cdc04dcc
ET		 6704 /* enable transmits */
6705 netif_tx_wake_all_queues(adapter->netdev);
6706
6707 /* enable any upper devices */
6708 rtnl_lock();
6709 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6710 if (netif_is_macvlan(upper)) {
6711 struct macvlan_dev *vlan = netdev_priv(upper);
6712
6713 if (vlan->fwd_priv)
6714 netif_tx_wake_all_queues(upper);
6715 }
6716 }
6717 rtnl_unlock();
6718
107d3018
AD		 6719 /* update the default user priority for VFs */
6720 ixgbe_update_default_up(adapter);
6721
befa2af7
AD		 6722 /* ping all the active vfs to let them know link has changed */
6723 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6724}
6725
c4cf55e5 6726/**
93c52dd0
AD		 6727 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6728 * print link down message
49ce9c2c 6729 * @adapter: pointer to the adapter structure
c4cf55e5 6730 **/
581330ba 6731static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6732{
cf8280ee 6733 struct net_device *netdev = adapter->netdev;
c4cf55e5 6734 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6735
93c52dd0
AD		 6736 adapter->link_up = false;
6737 adapter->link_speed = 0;
cf8280ee 6738
93c52dd0
AD		 6739 /* only continue if link was up previously */
6740 if (!netif_carrier_ok(netdev))
6741 return;
264857b8 6742
93c52dd0
AD		 6743 /* poll for SFP+ cable when link is down */
6744 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6745 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6746
8fecf67c 6747 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6748 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6749
93c52dd0
AD		 6750 e_info(drv, "NIC Link is Down\n");
6751 netif_carrier_off(netdev);
befa2af7
AD		 6752
6753 /* ping all the active vfs to let them know link has changed */
6754 ixgbe_ping_all_vfs(adapter);
93c52dd0 6755}
e8e26350 6756
07923c17
ET		 6757static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6758{
6759 int i;
6760
6761 for (i = 0; i < adapter->num_tx_queues; i++) {
6762 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6763
6764 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6765 return true;
6766 }
6767
6768 return false;
6769}
6770
6771static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6772{
6773 struct ixgbe_hw *hw = &adapter->hw;
6774 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6775 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6776
6777 int i, j;
6778
6779 if (!adapter->num_vfs)
6780 return false;
6781
9a75a1ac
DS		 6782 /* resetting the PF is only needed for MAC before X550 */
6783 if (hw->mac.type >= ixgbe_mac_X550)
6784 return false;
6785
07923c17
ET		 6786 for (i = 0; i < adapter->num_vfs; i++) {
6787 for (j = 0; j < q_per_pool; j++) {
6788 u32 h, t;
6789
6790 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6791 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6792
6793 if (h != t)
6794 return true;
6795 }
6796 }
6797
6798 return false;
6799}
6800
93c52dd0
AD		 6801/**
6802 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6803 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6804 **/
6805static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6806{
93c52dd0 6807 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6808 if (ixgbe_ring_tx_pending(adapter) ||
6809 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6810 /* We've lost link, so the controller stops DMA,
6811 * but we've got queued Tx work that's never going
6812 * to get done, so reset controller to flush Tx.
6813 * (Do the reset outside of interrupt context).
6814 */
12ff3f3b 6815 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6816 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6817 }
c4cf55e5 6818 }
c4cf55e5
PWJ		 6819}
6820
9079e416
ET		 6821#ifdef CONFIG_PCI_IOV
6822static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6823 struct pci_dev *vfdev)
6824{
6825 if (!pci_wait_for_pending_transaction(vfdev))
6826 e_dev_warn("Issuing VFLR with pending transactions\n");
6827
6828 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6829 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6830
6831 msleep(100);
6832}
6833
6834static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6835{
6836 struct ixgbe_hw *hw = &adapter->hw;
6837 struct pci_dev *pdev = adapter->pdev;
988d1307 6838 unsigned int vf;
9079e416 6839 u32 gpc;
9079e416
ET		 6840
6841 if (!(netif_carrier_ok(adapter->netdev)))
6842 return;
6843
6844 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6845 if (gpc) /* If incrementing then no need for the check below */
6846 return;
6847 /* Check to see if a bad DMA write target from an errant or
6848 * malicious VF has caused a PCIe error. If so then we can
6849 * issue a VFLR to the offending VF(s) and then resume without
6850 * requesting a full slot reset.
6851 */
6852
6853 if (!pdev)
6854 return;
6855
9079e416 6856 /* check status reg for all VFs owned by this PF */
988d1307
MR		 6857 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6858 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6859 u16 status_reg;
9079e416 6860
988d1307
MR		 6861 if (!vfdev)
6862 continue;
6863 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6864 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6865 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6866 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 6867 }
6868}
6869
a985b6c3
GR		 6870static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6871{
6872 u32 ssvpc;
6873
0584d999
GR		 6874 /* Do not perform spoof check for 82598 or if not in IOV mode */
6875 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6876 adapter->num_vfs == 0)
a985b6c3
GR		 6877 return;
6878
6879 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6880
6881 /*
6882 * ssvpc register is cleared on read, if zero then no
6883 * spoofed packets in the last interval.
6884 */
6885 if (!ssvpc)
6886 return;
6887
d6ea0754 6888 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6889}
9079e416
ET		 6890#else
6891static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6892{
6893}
6894
6895static void
6896ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6897{
6898}
6899#endif /* CONFIG_PCI_IOV */
6900
a985b6c3 6901
93c52dd0
AD		 6902/**
6903 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6904 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6905 **/
6906static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6907{
09f40aed 6908 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6909 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6910 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6911 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6912 return;
6913
6914 ixgbe_watchdog_update_link(adapter);
6915
6916 if (adapter->link_up)
6917 ixgbe_watchdog_link_is_up(adapter);
6918 else
6919 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6920
9079e416 6921 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6922 ixgbe_spoof_check(adapter);
9a799d71 6923 ixgbe_update_stats(adapter);
93c52dd0
AD		 6924
6925 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6926}
10eec955 6927
cf8280ee 6928/**
7086400d 6929 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6930 * @adapter: the ixgbe adapter structure
cf8280ee 6931 **/
7086400d 6932static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6933{
cf8280ee 6934 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6935 s32 err;
cf8280ee 6936
7086400d
AD		 6937 /* not searching for SFP so there is nothing to do here */
6938 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6939 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6940 return;
10eec955 6941
58e7cd24
MR		 6942 if (adapter->sfp_poll_time &&
6943 time_after(adapter->sfp_poll_time, jiffies))
6944 return; /* If not yet time to poll for SFP */
6945
7086400d
AD		 6946 /* someone else is in init, wait until next service event */
6947 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6948 return;
cf8280ee 6949
58e7cd24
MR		 6950 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6951
7086400d
AD		 6952 err = hw->phy.ops.identify_sfp(hw);
6953 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6954 goto sfp_out;
264857b8 6955
7086400d
AD		 6956 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6957 /* If no cable is present, then we need to reset
6958 * the next time we find a good cable. */
6959 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6960 }
9a799d71 6961
7086400d
AD		 6962 /* exit on error */
6963 if (err)
6964 goto sfp_out;
e8e26350 6965
7086400d
AD		 6966 /* exit if reset not needed */
6967 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6968 goto sfp_out;
9a799d71 6969
7086400d 6970 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6971
7086400d
AD		 6972 /*
6973 * A module may be identified correctly, but the EEPROM may not have
6974 * support for that module. setup_sfp() will fail in that case, so
6975 * we should not allow that module to load.
6976 */
6977 if (hw->mac.type == ixgbe_mac_82598EB)
6978 err = hw->phy.ops.reset(hw);
6979 else
6980 err = hw->mac.ops.setup_sfp(hw);
6981
6982 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6983 goto sfp_out;
6984
6985 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6986 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6987
6988sfp_out:
6989 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6990
6991 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6992 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6993 e_dev_err("failed to initialize because an unsupported "
6994 "SFP+ module type was detected.\n");
6995 e_dev_err("Reload the driver after installing a "
6996 "supported module.\n");
6997 unregister_netdev(adapter->netdev);
bc59fcda 6998 }
7086400d 6999}
bc59fcda 7000
7086400d
AD		 7001/**
7002 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7003 * @adapter: the ixgbe adapter structure
7086400d
AD		 7004 **/
7005static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7006{
7007 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7008 u32 speed;
7009 bool autoneg = false;
7086400d
AD		 7010
7011 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7012 return;
7013
7014 /* someone else is in init, wait until next service event */
7015 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7016 return;
7017
7018 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7019
3d292265 7020 speed = hw->phy.autoneg_advertised;
ed33ff66 7021 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7022 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7023
7024 /* setup the highest link when no autoneg */
7025 if (!autoneg) {
7026 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7027 speed = IXGBE_LINK_SPEED_10GB_FULL;
7028 }
7029 }
7030
7086400d 7031 if (hw->mac.ops.setup_link)
fd0326f2 7032 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7033
7034 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7035 adapter->link_check_timeout = jiffies;
7036 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7037}
7038
7039/**
7040 * ixgbe_service_timer - Timer Call-back
7041 * @data: pointer to adapter cast into an unsigned long
7042 **/
7043static void ixgbe_service_timer(unsigned long data)
7044{
7045 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7046 unsigned long next_event_offset;
7047
6bb78cfb
AD		 7048 /* poll faster when waiting for link */
7049 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7050 next_event_offset = HZ / 10;
7051 else
7052 next_event_offset = HZ * 2;
83c61fa9 7053
7086400d
AD		 7054 /* Reset the timer */
7055 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7056
9079e416 7057 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7058}
7059
597f22d6
DS		 7060static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7061{
7062 struct ixgbe_hw *hw = &adapter->hw;
7063 u32 status;
7064
7065 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7066 return;
7067
7068 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7069
7070 if (!hw->phy.ops.handle_lasi)
7071 return;
7072
7073 status = hw->phy.ops.handle_lasi(&adapter->hw);
7074 if (status != IXGBE_ERR_OVERTEMP)
7075 return;
7076
7077 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7078}
7079
c83c6cbd
AD		 7080static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7081{
7082 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7083 return;
7084
7085 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7086
09f40aed 7087 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7088 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7089 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7090 test_bit(__IXGBE_RESETTING, &adapter->state))
7091 return;
7092
7093 ixgbe_dump(adapter);
7094 netdev_err(adapter->netdev, "Reset adapter\n");
7095 adapter->tx_timeout_count++;
7096
8f4c5c9f 7097 rtnl_lock();
c83c6cbd 7098 ixgbe_reinit_locked(adapter);
8f4c5c9f 7099 rtnl_unlock();
c83c6cbd
AD		 7100}
7101
7086400d
AD		 7102/**
7103 * ixgbe_service_task - manages and runs subtasks
7104 * @work: pointer to work_struct containing our data
7105 **/
7106static void ixgbe_service_task(struct work_struct *work)
7107{
7108 struct ixgbe_adapter *adapter = container_of(work,
7109 struct ixgbe_adapter,
7110 service_task);
b0483c8f
MR		 7111 if (ixgbe_removed(adapter->hw.hw_addr)) {
7112 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7113 rtnl_lock();
7114 ixgbe_down(adapter);
7115 rtnl_unlock();
7116 }
7117 ixgbe_service_event_complete(adapter);
7118 return;
7119 }
67359c3c
MR		 7120#ifdef CONFIG_IXGBE_VXLAN
7121 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7122 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7123 vxlan_get_rx_port(adapter->netdev);
7124 }
7125#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 7126 ixgbe_reset_subtask(adapter);
597f22d6 7127 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7128 ixgbe_sfp_detection_subtask(adapter);
7129 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7130 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7131 ixgbe_watchdog_subtask(adapter);
d034acf1 7132 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7133 ixgbe_check_hang_subtask(adapter);
891dc082 7134
8fecf67c 7135 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7136 ixgbe_ptp_overflow_check(adapter);
7137 ixgbe_ptp_rx_hang(adapter);
7138 }
7086400d
AD		 7139
7140 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7141}
7142
fd0db0ed
AD		 7143static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7144 struct ixgbe_tx_buffer *first,
244e27ad 7145 u8 *hdr_len)
897ab156 7146{
fd0db0ed 7147 struct sk_buff *skb = first->skb;
897ab156
AD		 7148 u32 vlan_macip_lens, type_tucmd;
7149 u32 mss_l4len_idx, l4len;
2049e1f6 7150 int err;
9a799d71 7151
8f4fbb9b
AD		 7152 if (skb->ip_summed != CHECKSUM_PARTIAL)
7153 return 0;
7154
897ab156
AD		 7155 if (!skb_is_gso(skb))
7156 return 0;
9a799d71 7157
2049e1f6
FR		 7158 err = skb_cow_head(skb, 0);
7159 if (err < 0)
7160 return err;
9a799d71 7161
897ab156
AD		 7162 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7163 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7164
a1108ffd 7165 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 7166 struct iphdr *iph = ip_hdr(skb);
7167 iph->tot_len = 0;
7168 iph->check = 0;
7169 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7170 iph->daddr, 0,
7171 IPPROTO_TCP,
7172 0);
7173 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 7174 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7175 IXGBE_TX_FLAGS_CSUM |
7176 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 7177 } else if (skb_is_gso_v6(skb)) {
7178 ipv6_hdr(skb)->payload_len = 0;
7179 tcp_hdr(skb)->check =
7180 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7181 &ipv6_hdr(skb)->daddr,
7182 0, IPPROTO_TCP, 0);
244e27ad
AD		 7183 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7184 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7185 }
7186
091a6246 7187 /* compute header lengths */
897ab156
AD		 7188 l4len = tcp_hdrlen(skb);
7189 *hdr_len = skb_transport_offset(skb) + l4len;
7190
091a6246
AD		 7191 /* update gso size and bytecount with header size */
7192 first->gso_segs = skb_shinfo(skb)->gso_segs;
7193 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7194
c44f5f51 7195 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 7196 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7197 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7198
7199 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7200 vlan_macip_lens = skb_network_header_len(skb);
7201 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7202 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7203
7204 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7205 mss_l4len_idx);
897ab156
AD		 7206
7207 return 1;
7208}
7209
244e27ad
AD		 7210static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7211 struct ixgbe_tx_buffer *first)
7ca647bd 7212{
fd0db0ed 7213 struct sk_buff *skb = first->skb;
897ab156
AD		 7214 u32 vlan_macip_lens = 0;
7215 u32 mss_l4len_idx = 0;
7216 u32 type_tucmd = 0;
7ca647bd 7217
897ab156 7218 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 7219 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7220 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7221 return;
f467bc06
MR		 7222 vlan_macip_lens = skb_network_offset(skb) <<
7223 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 7224 } else {
7225 u8 l4_hdr = 0;
f467bc06
MR		 7226 union {
7227 struct iphdr *ipv4;
7228 struct ipv6hdr *ipv6;
7229 u8 *raw;
7230 } network_hdr;
7231 union {
7232 struct tcphdr *tcphdr;
7233 u8 *raw;
7234 } transport_hdr;
36a92d71 7235 __be16 frag_off;
f467bc06
MR		 7236
7237 if (skb->encapsulation) {
7238 network_hdr.raw = skb_inner_network_header(skb);
7239 transport_hdr.raw = skb_inner_transport_header(skb);
7240 vlan_macip_lens = skb_inner_network_offset(skb) <<
7241 IXGBE_ADVTXD_MACLEN_SHIFT;
7242 } else {
7243 network_hdr.raw = skb_network_header(skb);
7244 transport_hdr.raw = skb_transport_header(skb);
7245 vlan_macip_lens = skb_network_offset(skb) <<
7246 IXGBE_ADVTXD_MACLEN_SHIFT;
7247 }
7248
7249 /* use first 4 bits to determine IP version */
7250 switch (network_hdr.ipv4->version) {
7251 case IPVERSION:
7252 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7253 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7254 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7255 break;
f467bc06
MR		 7256 case 6:
7257 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7258 l4_hdr = network_hdr.ipv6->nexthdr;
36a92d71
MR		 7259 if (likely((transport_hdr.raw - network_hdr.raw) ==
7260 sizeof(struct ipv6hdr)))
7261 break;
7262 ipv6_skip_exthdr(skb, network_hdr.raw - skb->data +
7263 sizeof(struct ipv6hdr),
7264 &l4_hdr, &frag_off);
7265 if (unlikely(frag_off))
7266 l4_hdr = NEXTHDR_FRAGMENT;
897ab156
AD		 7267 break;
7268 default:
36a92d71 7269 break;
7ca647bd 7270 }
897ab156
AD		 7271
7272 switch (l4_hdr) {
7ca647bd 7273 case IPPROTO_TCP:
897ab156 7274 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7275 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7276 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7277 break;
7278 case IPPROTO_SCTP:
897ab156
AD		 7279 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7280 mss_l4len_idx = sizeof(struct sctphdr) <<
7281 IXGBE_ADVTXD_L4LEN_SHIFT;
7282 break;
7283 case IPPROTO_UDP:
7284 mss_l4len_idx = sizeof(struct udphdr) <<
7285 IXGBE_ADVTXD_L4LEN_SHIFT;
7286 break;
7287 default:
7288 if (unlikely(net_ratelimit())) {
7289 dev_warn(tx_ring->dev,
36a92d71
MR		 7290 "partial checksum, version=%d, l4 proto=%x\n",
7291 network_hdr.ipv4->version, l4_hdr);
897ab156 7292 }
36a92d71
MR		 7293 skb_checksum_help(skb);
7294 goto no_csum;
7ca647bd 7295 }
244e27ad
AD		 7296
7297 /* update TX checksum flag */
7298 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7299 }
7300
36a92d71 7301no_csum:
244e27ad 7302 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7303 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7304
897ab156
AD		 7305 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7306 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7307}
7308
472148c3
AD		 7309#define IXGBE_SET_FLAG(_input, _flag, _result) \
7310 ((_flag <= _result) ? \
7311 ((u32)(_input & _flag) * (_result / _flag)) : \
7312 ((u32)(_input & _flag) / (_flag / _result)))
7313
7314static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7315{
d3d00239 7316 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7317 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7318 IXGBE_ADVTXD_DCMD_DEXT |
7319 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7320
d3d00239 7321 /* set HW vlan bit if vlan is present */
472148c3
AD		 7322 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7323 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7324
d3d00239 7325 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7326 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7327 IXGBE_ADVTXD_DCMD_TSE);
7328
7329 /* set timestamp bit if present */
7330 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7331 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7332
62748b7b 7333 /* insert frame checksum */
472148c3 7334 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7335
d3d00239
AD		 7336 return cmd_type;
7337}
9a799d71 7338
729739b7
AD		 7339static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7340 u32 tx_flags, unsigned int paylen)
d3d00239 7341{
472148c3 7342 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7343
d3d00239 7344 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7345 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7346 IXGBE_TX_FLAGS_CSUM,
7347 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7348
93f5b3c1 7349 /* enble IPv4 checksum for TSO */
472148c3
AD		 7350 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7351 IXGBE_TX_FLAGS_IPV4,
7352 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7353
7f9643fd
AD		 7354 /*
7355 * Check Context must be set if Tx switch is enabled, which it
7356 * always is for case where virtual functions are running
7357 */
472148c3
AD		 7358 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7359 IXGBE_TX_FLAGS_CC,
7360 IXGBE_ADVTXD_CC);
7f9643fd 7361
472148c3 7362 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7363}
44df32c5 7364
2367a173
DB		 7365static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7366{
7367 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7368
7369 /* Herbert's original patch had:
7370 * smp_mb__after_netif_stop_queue();
7371 * but since that doesn't exist yet, just open code it.
7372 */
7373 smp_mb();
7374
7375 /* We need to check again in a case another CPU has just
7376 * made room available.
7377 */
7378 if (likely(ixgbe_desc_unused(tx_ring) < size))
7379 return -EBUSY;
7380
7381 /* A reprieve! - use start_queue because it doesn't call schedule */
7382 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7383 ++tx_ring->tx_stats.restart_queue;
7384 return 0;
7385}
7386
7387static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7388{
7389 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7390 return 0;
7391
7392 return __ixgbe_maybe_stop_tx(tx_ring, size);
7393}
7394
d3d00239
AD		 7395#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7396 IXGBE_TXD_CMD_RS)
7397
7398static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7399 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7400 const u8 hdr_len)
7401{
fd0db0ed 7402 struct sk_buff *skb = first->skb;
729739b7 7403 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7404 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7405 struct skb_frag_struct *frag;
7406 dma_addr_t dma;
7407 unsigned int data_len, size;
244e27ad 7408 u32 tx_flags = first->tx_flags;
472148c3 7409 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7410 u16 i = tx_ring->next_to_use;
d3d00239 7411
729739b7
AD		 7412 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7413
ec718254
AD		 7414 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7415
7416 size = skb_headlen(skb);
7417 data_len = skb->data_len;
729739b7 7418
d3d00239
AD		 7419#ifdef IXGBE_FCOE
7420 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7421 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7422 size -= sizeof(struct fcoe_crc_eof) - data_len;
7423 data_len = 0;
729739b7
AD		 7424 } else {
7425 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7426 }
7427 }
44df32c5 7428
d3d00239 7429#endif
729739b7 7430 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7431
ec718254 7432 tx_buffer = first;
9a799d71 7433
ec718254
AD		 7434 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7435 if (dma_mapping_error(tx_ring->dev, dma))
7436 goto dma_error;
7437
7438 /* record length, and DMA address */
7439 dma_unmap_len_set(tx_buffer, len, size);
7440 dma_unmap_addr_set(tx_buffer, dma, dma);
7441
7442 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7443
729739b7 7444 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7445 tx_desc->read.cmd_type_len =
472148c3 7446 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7447
d3d00239 7448 i++;
729739b7 7449 tx_desc++;
d3d00239 7450 if (i == tx_ring->count) {
e4f74028 7451 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7452 i = 0;
7453 }
ec718254 7454 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7455
7456 dma += IXGBE_MAX_DATA_PER_TXD;
7457 size -= IXGBE_MAX_DATA_PER_TXD;
7458
7459 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7460 }
e5a43549 7461
729739b7
AD		 7462 if (likely(!data_len))
7463 break;
9a799d71 7464
472148c3 7465 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7466
729739b7
AD		 7467 i++;
7468 tx_desc++;
7469 if (i == tx_ring->count) {
7470 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7471 i = 0;
7472 }
ec718254 7473 tx_desc->read.olinfo_status = 0;
9a799d71 7474
d3d00239 7475#ifdef IXGBE_FCOE
9e903e08 7476 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7477#else
9e903e08 7478 size = skb_frag_size(frag);
d3d00239
AD		 7479#endif
7480 data_len -= size;
9a799d71 7481
729739b7
AD		 7482 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7483 DMA_TO_DEVICE);
9a799d71 7484
729739b7 7485 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7486 }
9a799d71 7487
729739b7 7488 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7489 cmd_type |= size | IXGBE_TXD_CMD;
7490 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7491
091a6246 7492 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7493
d3d00239
AD		 7494 /* set the timestamp */
7495 first->time_stamp = jiffies;
9a799d71
AK		 7496
7497 /*
729739b7
AD		 7498 * Force memory writes to complete before letting h/w know there
7499 * are new descriptors to fetch. (Only applicable for weak-ordered
7500 * memory model archs, such as IA-64).
7501 *
7502 * We also need this memory barrier to make certain all of the
7503 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7504 */
7505 wmb();
7506
d3d00239
AD		 7507 /* set next_to_watch value indicating a packet is present */
7508 first->next_to_watch = tx_desc;
7509
729739b7
AD		 7510 i++;
7511 if (i == tx_ring->count)
7512 i = 0;
7513
7514 tx_ring->next_to_use = i;
7515
2367a173
DB		 7516 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7517
7518 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7519 writel(i, tx_ring->tail);
7520
7521 /* we need this if more than one processor can write to our tail
7522 * at a time, it synchronizes IO on IA64/Altix systems
7523 */
7524 mmiowb();
9c938cdd 7525 }
2367a173 7526
d3d00239
AD		 7527 return;
7528dma_error:
729739b7 7529 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7530
7531 /* clear dma mappings for failed tx_buffer_info map */
7532 for (;;) {
729739b7
AD		 7533 tx_buffer = &tx_ring->tx_buffer_info[i];
7534 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7535 if (tx_buffer == first)
d3d00239
AD		 7536 break;
7537 if (i == 0)
7538 i = tx_ring->count;
7539 i--;
7540 }
7541
d3d00239 7542 tx_ring->next_to_use = i;
9a799d71
AK		 7543}
7544
fd0db0ed 7545static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7546 struct ixgbe_tx_buffer *first)
69830529
AD		 7547{
7548 struct ixgbe_q_vector *q_vector = ring->q_vector;
7549 union ixgbe_atr_hash_dword input = { .dword = 0 };
7550 union ixgbe_atr_hash_dword common = { .dword = 0 };
7551 union {
7552 unsigned char *network;
7553 struct iphdr *ipv4;
7554 struct ipv6hdr *ipv6;
7555 } hdr;
ee9e0f0b 7556 struct tcphdr *th;
67359c3c
MR		 7557 struct sk_buff *skb;
7558#ifdef CONFIG_IXGBE_VXLAN
7559 u8 encap = false;
7560#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7561 __be16 vlan_id;
c4cf55e5 7562
69830529
AD		 7563 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7564 if (!q_vector)
7565 return;
7566
7567 /* do nothing if sampling is disabled */
7568 if (!ring->atr_sample_rate)
d3ead241 7569 return;
c4cf55e5 7570
69830529 7571 ring->atr_count++;
c4cf55e5 7572
69830529 7573 /* snag network header to get L4 type and address */
67359c3c
MR		 7574 skb = first->skb;
7575 hdr.network = skb_network_header(skb);
e19dcdeb
MR		 7576 if (!skb->encapsulation) {
7577 th = tcp_hdr(skb);
7578 } else {
67359c3c
MR		 7579#ifdef CONFIG_IXGBE_VXLAN
7580 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7581
67359c3c
MR		 7582 if (!adapter->vxlan_port)
7583 return;
7584 if (first->protocol != htons(ETH_P_IP) ||
7585 hdr.ipv4->version != IPVERSION ||
7586 hdr.ipv4->protocol != IPPROTO_UDP) {
7587 return;
7588 }
7589 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7590 return;
7591 encap = true;
7592 hdr.network = skb_inner_network_header(skb);
7593 th = inner_tcp_hdr(skb);
7594#else
69830529 7595 return;
67359c3c 7596#endif /* CONFIG_IXGBE_VXLAN */
e19dcdeb
MR		 7597 }
7598
7599 /* Currently only IPv4/IPv6 with TCP is supported */
7600 switch (hdr.ipv4->version) {
7601 case IPVERSION:
7602 if (hdr.ipv4->protocol != IPPROTO_TCP)
67359c3c 7603 return;
e19dcdeb
MR		 7604 break;
7605 case 6:
7606 if (likely((unsigned char *)th - hdr.network ==
7607 sizeof(struct ipv6hdr))) {
7608 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
7609 return;
7610 } else {
7611 __be16 frag_off;
7612 u8 l4_hdr;
7613
7614 ipv6_skip_exthdr(skb, hdr.network - skb->data +
7615 sizeof(struct ipv6hdr),
7616 &l4_hdr, &frag_off);
7617 if (unlikely(frag_off))
7618 return;
7619 if (l4_hdr != IPPROTO_TCP)
7620 return;
7621 }
7622 break;
7623 default:
7624 return;
67359c3c 7625 }
c4cf55e5 7626
66f32a8b
AD		 7627 /* skip this packet since it is invalid or the socket is closing */
7628 if (!th || th->fin)
69830529
AD		 7629 return;
7630
7631 /* sample on all syn packets or once every atr sample count */
7632 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7633 return;
7634
7635 /* reset sample count */
7636 ring->atr_count = 0;
7637
244e27ad 7638 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7639
7640 /*
7641 * src and dst are inverted, think how the receiver sees them
7642 *
7643 * The input is broken into two sections, a non-compressed section
7644 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7645 * is XORed together and stored in the compressed dword.
7646 */
7647 input.formatted.vlan_id = vlan_id;
7648
7649 /*
7650 * since src port and flex bytes occupy the same word XOR them together
7651 * and write the value to source port portion of compressed dword
7652 */
244e27ad 7653 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7654 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7655 else
244e27ad 7656 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7657 common.port.dst ^= th->source;
7658
e19dcdeb
MR		 7659 switch (hdr.ipv4->version) {
7660 case IPVERSION:
69830529
AD		 7661 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7662 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 7663 break;
7664 case 6:
69830529
AD		 7665 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7666 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7667 hdr.ipv6->saddr.s6_addr32[1] ^
7668 hdr.ipv6->saddr.s6_addr32[2] ^
7669 hdr.ipv6->saddr.s6_addr32[3] ^
7670 hdr.ipv6->daddr.s6_addr32[0] ^
7671 hdr.ipv6->daddr.s6_addr32[1] ^
7672 hdr.ipv6->daddr.s6_addr32[2] ^
7673 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 7674 break;
7675 default:
7676 break;
69830529 7677 }
c4cf55e5 7678
67359c3c
MR		 7679#ifdef CONFIG_IXGBE_VXLAN
7680 if (encap)
7681 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7682#endif /* CONFIG_IXGBE_VXLAN */
7683
c4cf55e5 7684 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7685 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7686 input, common, ring->queue_index);
c4cf55e5
PWJ		 7687}
7688
f663dd9a 7689static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7690 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7691{
f663dd9a
JW		 7692 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7693#ifdef IXGBE_FCOE
97488bd1
AD		 7694 struct ixgbe_adapter *adapter;
7695 struct ixgbe_ring_feature *f;
7696 int txq;
f663dd9a
JW		 7697#endif
7698
7699 if (fwd_adapter)
7700 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7701
7702#ifdef IXGBE_FCOE
5e09a105 7703
97488bd1
AD		 7704 /*
7705 * only execute the code below if protocol is FCoE
7706 * or FIP and we have FCoE enabled on the adapter
7707 */
7708 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7709 case htons(ETH_P_FCOE):
7710 case htons(ETH_P_FIP):
97488bd1 7711 adapter = netdev_priv(dev);
c087663e 7712
97488bd1
AD		 7713 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7714 break;
7715 default:
99932d4f 7716 return fallback(dev, skb);
97488bd1 7717 }
c087663e 7718
97488bd1 7719 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7720
97488bd1
AD		 7721 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7722 smp_processor_id();
56075a98 7723
97488bd1
AD		 7724 while (txq >= f->indices)
7725 txq -= f->indices;
c4cf55e5 7726
97488bd1 7727 return txq + f->offset;
f663dd9a 7728#else
99932d4f 7729 return fallback(dev, skb);
f663dd9a 7730#endif
09a3b1f8
SH		 7731}
7732
fc77dc3c 7733netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7734 struct ixgbe_adapter *adapter,
7735 struct ixgbe_ring *tx_ring)
9a799d71 7736{
d3d00239 7737 struct ixgbe_tx_buffer *first;
5f715823 7738 int tso;
d3d00239 7739 u32 tx_flags = 0;
a535c30e 7740 unsigned short f;
a535c30e 7741 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7742 __be16 protocol = skb->protocol;
63544e9c 7743 u8 hdr_len = 0;
5e09a105 7744
a535c30e
AD		 7745 /*
7746 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7747 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7748 * + 2 desc gap to keep tail from touching head,
7749 * + 1 desc for context descriptor,
7750 * otherwise try next time
7751 */
a535c30e
AD		 7752 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7753 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7754
a535c30e
AD		 7755 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7756 tx_ring->tx_stats.tx_busy++;
7757 return NETDEV_TX_BUSY;
7758 }
7759
fd0db0ed
AD		 7760 /* record the location of the first descriptor for this packet */
7761 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7762 first->skb = skb;
091a6246
AD		 7763 first->bytecount = skb->len;
7764 first->gso_segs = 1;
fd0db0ed 7765
66f32a8b 7766 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7767 if (skb_vlan_tag_present(skb)) {
7768 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7769 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7770 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7771 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7772 struct vlan_hdr *vhdr, _vhdr;
7773 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7774 if (!vhdr)
7775 goto out_drop;
7776
9e0c5648
AD		 7777 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7778 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7779 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7780 }
0213668f 7781 protocol = vlan_get_protocol(skb);
66f32a8b 7782
d5234933
MR		 7783 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7784 adapter->ptp_clock &&
7785 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7786 &adapter->state)) {
3a6a4eda
JK		 7787 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7788 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7789
7790 /* schedule check for Tx timestamp */
7791 adapter->ptp_tx_skb = skb_get(skb);
7792 adapter->ptp_tx_start = jiffies;
7793 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7794 }
3a6a4eda 7795
ff29a86e
JK		 7796 skb_tx_timestamp(skb);
7797
9e0c5648
AD		 7798#ifdef CONFIG_PCI_IOV
7799 /*
7800 * Use the l2switch_enable flag - would be false if the DMA
7801 * Tx switch had been disabled.
7802 */
7803 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7804 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7805
7806#endif
32701dc2 7807 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7808 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7809 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7810 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7811 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7812 tx_flags |= (skb->priority & 0x7) <<
7813 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7814 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7815 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7816
7817 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7818 goto out_drop;
7819 vhdr = (struct vlan_ethhdr *)skb->data;
7820 vhdr->h_vlan_TCI = htons(tx_flags >>
7821 IXGBE_TX_FLAGS_VLAN_SHIFT);
7822 } else {
7823 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7824 }
9a799d71 7825 }
eacd73f7 7826
244e27ad
AD		 7827 /* record initial flags and protocol */
7828 first->tx_flags = tx_flags;
7829 first->protocol = protocol;
7830
eacd73f7 7831#ifdef IXGBE_FCOE
66f32a8b 7832 /* setup tx offload for FCoE */
a1108ffd 7833 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7834 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7835 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7836 if (tso < 0)
7837 goto out_drop;
9a799d71 7838
66f32a8b 7839 goto xmit_fcoe;
eacd73f7 7840 }
9a799d71 7841
66f32a8b 7842#endif /* IXGBE_FCOE */
244e27ad 7843 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7844 if (tso < 0)
897ab156 7845 goto out_drop;
244e27ad
AD		 7846 else if (!tso)
7847 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7848
7849 /* add the ATR filter if ATR is on */
7850 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7851 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7852
7853#ifdef IXGBE_FCOE
7854xmit_fcoe:
7855#endif /* IXGBE_FCOE */
244e27ad 7856 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7857
9a799d71 7858 return NETDEV_TX_OK;
897ab156
AD		 7859
7860out_drop:
fd0db0ed
AD		 7861 dev_kfree_skb_any(first->skb);
7862 first->skb = NULL;
7863
897ab156 7864 return NETDEV_TX_OK;
9a799d71
AK		 7865}
7866
2a47fa45
JF		 7867static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7868 struct net_device *netdev,
7869 struct ixgbe_ring *ring)
84418e3b
AD		 7870{
7871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7872 struct ixgbe_ring *tx_ring;
7873
a50c29dd
AD		 7874 /*
7875 * The minimum packet size for olinfo paylen is 17 so pad the skb
7876 * in order to meet this minimum size requirement.
7877 */
a94d9e22
AD		 7878 if (skb_put_padto(skb, 17))
7879 return NETDEV_TX_OK;
a50c29dd 7880
2a47fa45
JF		 7881 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7882
fc77dc3c 7883 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7884}
7885
2a47fa45
JF		 7886static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7887 struct net_device *netdev)
7888{
7889 return __ixgbe_xmit_frame(skb, netdev, NULL);
7890}
7891
9a799d71
AK		 7892/**
7893 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7894 * @netdev: network interface device structure
7895 * @p: pointer to an address structure
7896 *
7897 * Returns 0 on success, negative on failure
7898 **/
7899static int ixgbe_set_mac(struct net_device *netdev, void *p)
7900{
7901 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7902 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7903 struct sockaddr *addr = p;
7904
7905 if (!is_valid_ether_addr(addr->sa_data))
7906 return -EADDRNOTAVAIL;
7907
7908 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7909 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7910
c9f53e63
AD		 7911 ixgbe_mac_set_default_filter(adapter);
7912
7913 return 0;
9a799d71
AK		 7914}
7915
6b73e10d
BH		 7916static int
7917ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7918{
7919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7920 struct ixgbe_hw *hw = &adapter->hw;
7921 u16 value;
7922 int rc;
7923
7924 if (prtad != hw->phy.mdio.prtad)
7925 return -EINVAL;
7926 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7927 if (!rc)
7928 rc = value;
7929 return rc;
7930}
7931
7932static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7933 u16 addr, u16 value)
7934{
7935 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7936 struct ixgbe_hw *hw = &adapter->hw;
7937
7938 if (prtad != hw->phy.mdio.prtad)
7939 return -EINVAL;
7940 return hw->phy.ops.write_reg(hw, addr, devad, value);
7941}
7942
7943static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7944{
7945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7946
3a6a4eda 7947 switch (cmd) {
3a6a4eda 7948 case SIOCSHWTSTAMP:
93501d48
JK		 7949 return ixgbe_ptp_set_ts_config(adapter, req);
7950 case SIOCGHWTSTAMP:
7951 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7952 default:
7953 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7954 }
6b73e10d
BH		 7955}
7956
0365e6e4
PW		 7957/**
7958 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7959 * netdev->dev_addrs
0365e6e4
PW		 7960 * @netdev: network interface device structure
7961 *
7962 * Returns non-zero on failure
7963 **/
7964static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7965{
7966 int err = 0;
7967 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7968 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7969
7fa7c9dc 7970 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7971 rtnl_lock();
7fa7c9dc 7972 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7973 rtnl_unlock();
7fa7c9dc
AD		 7974
7975 /* update SAN MAC vmdq pool selection */
7976 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7977 }
7978 return err;
7979}
7980
7981/**
7982 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7983 * netdev->dev_addrs
0365e6e4
PW		 7984 * @netdev: network interface device structure
7985 *
7986 * Returns non-zero on failure
7987 **/
7988static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7989{
7990 int err = 0;
7991 struct ixgbe_adapter *adapter = netdev_priv(dev);
7992 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7993
7994 if (is_valid_ether_addr(mac->san_addr)) {
7995 rtnl_lock();
7996 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7997 rtnl_unlock();
7998 }
7999 return err;
8000}
8001
9a799d71
AK		 8002#ifdef CONFIG_NET_POLL_CONTROLLER
8003/*
8004 * Polling 'interrupt' - used by things like netconsole to send skbs
8005 * without having to re-enable interrupts. It's not called while
8006 * the interrupt routine is executing.
8007 */
8008static void ixgbe_netpoll(struct net_device *netdev)
8009{
8010 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8011 int i;
9a799d71 8012
1a647bd2
AD		 8013 /* if interface is down do nothing */
8014 if (test_bit(__IXGBE_DOWN, &adapter->state))
8015 return;
8016
856f606e
AD		 8017 /* loop through and schedule all active queues */
8018 for (i = 0; i < adapter->num_q_vectors; i++)
8019 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8020}
9a799d71 8021
581330ba 8022#endif
de1036b1
ED		 8023static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8024 struct rtnl_link_stats64 *stats)
8025{
8026 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8027 int i;
8028
1a51502b 8029 rcu_read_lock();
de1036b1 8030 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8031 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8032 u64 bytes, packets;
8033 unsigned int start;
8034
1a51502b
ED		 8035 if (ring) {
8036 do {
57a7744e 8037 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8038 packets = ring->stats.packets;
8039 bytes = ring->stats.bytes;
57a7744e 8040 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8041 stats->rx_packets += packets;
8042 stats->rx_bytes += bytes;
8043 }
de1036b1 8044 }
1ac9ad13
ED		 8045
8046 for (i = 0; i < adapter->num_tx_queues; i++) {
8047 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8048 u64 bytes, packets;
8049 unsigned int start;
8050
8051 if (ring) {
8052 do {
57a7744e 8053 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8054 packets = ring->stats.packets;
8055 bytes = ring->stats.bytes;
57a7744e 8056 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8057 stats->tx_packets += packets;
8058 stats->tx_bytes += bytes;
8059 }
8060 }
1a51502b 8061 rcu_read_unlock();
de1036b1
ED		 8062 /* following stats updated by ixgbe_watchdog_task() */
8063 stats->multicast = netdev->stats.multicast;
8064 stats->rx_errors = netdev->stats.rx_errors;
8065 stats->rx_length_errors = netdev->stats.rx_length_errors;
8066 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8067 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8068 return stats;
8069}
8070
8af3c33f 8071#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8072/**
8073 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8074 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8075 * @tc: number of traffic classes currently enabled
8076 *
8077 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8078 * 802.1Q priority maps to a packet buffer that exists.
8079 */
8080static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8081{
8082 struct ixgbe_hw *hw = &adapter->hw;
8083 u32 reg, rsave;
8084 int i;
8085
8086 /* 82598 have a static priority to TC mapping that can not
8087 * be changed so no validation is needed.
8088 */
8089 if (hw->mac.type == ixgbe_mac_82598EB)
8090 return;
8091
8092 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8093 rsave = reg;
8094
8095 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8096 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8097
8098 /* If up2tc is out of bounds default to zero */
8099 if (up2tc > tc)
8100 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8101 }
8102
8103 if (reg != rsave)
8104 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8105
8106 return;
8107}
8108
02debdc9
AD		 8109/**
8110 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8111 * @adapter: Pointer to adapter struct
8112 *
8113 * Populate the netdev user priority to tc map
8114 */
8115static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8116{
8117 struct net_device *dev = adapter->netdev;
8118 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8119 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8120 u8 prio;
8121
8122 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8123 u8 tc = 0;
8124
8125 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8126 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8127 else if (ets)
8128 tc = ets->prio_tc[prio];
8129
8130 netdev_set_prio_tc_map(dev, prio, tc);
8131 }
8132}
8133
cca73c59 8134#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8135/**
8136 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8137 *
8138 * @netdev: net device to configure
8139 * @tc: number of traffic classes to enable
8140 */
8141int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8142{
8b1c0b24
JF		 8143 struct ixgbe_adapter *adapter = netdev_priv(dev);
8144 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8145 bool pools;
8b1c0b24 8146
8b1c0b24 8147 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8148 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8149 return -EINVAL;
8150
8151 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8152 return -EINVAL;
8153
2a47fa45
JF		 8154 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8155 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8156 return -EBUSY;
8157
8b1c0b24 8158 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8159 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8160 * hardware is not flexible enough to do this dynamically.
8161 */
8162 if (netif_running(dev))
8163 ixgbe_close(dev);
bf4d67d9
AD		 8164 else
8165 ixgbe_reset(adapter);
8166
8b1c0b24
JF		 8167 ixgbe_clear_interrupt_scheme(adapter);
8168
cca73c59 8169#ifdef CONFIG_IXGBE_DCB
e7589eab 8170 if (tc) {
8b1c0b24 8171 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8172 ixgbe_set_prio_tc_map(adapter);
8173
e7589eab 8174 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8175
943561d3
AD		 8176 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8177 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8178 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8179 }
e7589eab 8180 } else {
8b1c0b24 8181 netdev_reset_tc(dev);
02debdc9 8182
943561d3
AD		 8183 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8184 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8185
8186 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8187
8188 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8189 adapter->dcb_cfg.pfc_mode_enable = false;
8190 }
8191
8b1c0b24 8192 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8193
8194#endif /* CONFIG_IXGBE_DCB */
8195 ixgbe_init_interrupt_scheme(adapter);
8196
8b1c0b24 8197 if (netif_running(dev))
cca73c59 8198 return ixgbe_open(dev);
8b1c0b24
JF		 8199
8200 return 0;
8201}
de1036b1 8202
da36b647
GR		 8203#ifdef CONFIG_PCI_IOV
8204void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8205{
8206 struct net_device *netdev = adapter->netdev;
8207
8208 rtnl_lock();
da36b647 8209 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8210 rtnl_unlock();
8211}
8212
8213#endif
082757af
DS		 8214void ixgbe_do_reset(struct net_device *netdev)
8215{
8216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8217
8218 if (netif_running(netdev))
8219 ixgbe_reinit_locked(adapter);
8220 else
8221 ixgbe_reset(adapter);
8222}
8223
c8f44aff 8224static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8225 netdev_features_t features)
082757af
DS		 8226{
8227 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8228
082757af 8229 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8230 if (!(features & NETIF_F_RXCSUM))
8231 features &= ~NETIF_F_LRO;
082757af 8232
567d2de2
AD		 8233 /* Turn off LRO if not RSC capable */
8234 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8235 features &= ~NETIF_F_LRO;
8e2813f5 8236
567d2de2 8237 return features;
082757af
DS		 8238}
8239
c8f44aff 8240static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8241 netdev_features_t features)
082757af
DS		 8242{
8243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8244 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8245 bool need_reset = false;
8246
082757af 8247 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8248 if (!(features & NETIF_F_LRO)) {
8249 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8250 need_reset = true;
567d2de2
AD		 8251 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8252 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8253 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8254 if (adapter->rx_itr_setting == 1 ||
8255 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8256 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8257 need_reset = true;
8258 } else if ((changed ^ features) & NETIF_F_LRO) {
8259 e_info(probe, "rx-usecs set too low, "
8260 "disabling RSC\n");
082757af
DS		 8261 }
8262 }
8263
8264 /*
8265 * Check if Flow Director n-tuple support was enabled or disabled. If
8266 * the state changed, we need to reset.
8267 */
39cb681b
AD		 8268 switch (features & NETIF_F_NTUPLE) {
8269 case NETIF_F_NTUPLE:
567d2de2 8270 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8271 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8272 need_reset = true;
8273
567d2de2
AD		 8274 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8275 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 8276 break;
8277 default:
8278 /* turn off perfect filters, enable ATR and reset */
8279 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8280 need_reset = true;
8281
8282 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8283
8284 /* We cannot enable ATR if SR-IOV is enabled */
8285 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8286 break;
8287
8288 /* We cannot enable ATR if we have 2 or more traffic classes */
8289 if (netdev_get_num_tc(netdev) > 1)
8290 break;
8291
8292 /* We cannot enable ATR if RSS is disabled */
8293 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8294 break;
8295
8296 /* A sample rate of 0 indicates ATR disabled */
8297 if (!adapter->atr_sample_rate)
8298 break;
8299
8300 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8301 break;
082757af
DS		 8302 }
8303
f646968f 8304 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8305 ixgbe_vlan_strip_enable(adapter);
8306 else
8307 ixgbe_vlan_strip_disable(adapter);
8308
3f2d1c0f
BG		 8309 if (changed & NETIF_F_RXALL)
8310 need_reset = true;
8311
567d2de2 8312 netdev->features = features;
67359c3c
MR		 8313
8314#ifdef CONFIG_IXGBE_VXLAN
8315 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8316 if (features & NETIF_F_RXCSUM)
8317 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8318 else
8319 ixgbe_clear_vxlan_port(adapter);
8320 }
8321#endif /* CONFIG_IXGBE_VXLAN */
8322
082757af
DS		 8323 if (need_reset)
8324 ixgbe_do_reset(netdev);
8325
8326 return 0;
082757af
DS		 8327}
8328
67359c3c 8329#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8330/**
8331 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8332 * @dev: The port's netdev
8333 * @sa_family: Socket Family that VXLAN is notifiying us about
8334 * @port: New UDP port number that VXLAN started listening to
8335 **/
8336static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8337 __be16 port)
8338{
8339 struct ixgbe_adapter *adapter = netdev_priv(dev);
8340 struct ixgbe_hw *hw = &adapter->hw;
8341 u16 new_port = ntohs(port);
8342
67359c3c
MR		 8343 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8344 return;
8345
3f207800
DS		 8346 if (sa_family == AF_INET6)
8347 return;
8348
67359c3c 8349 if (adapter->vxlan_port == new_port)
3f207800 8350 return;
3f207800
DS		 8351
8352 if (adapter->vxlan_port) {
8353 netdev_info(dev,
67359c3c 8354 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8355 new_port);
8356 return;
8357 }
8358
8359 adapter->vxlan_port = new_port;
8360 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8361}
8362
8363/**
8364 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8365 * @dev: The port's netdev
8366 * @sa_family: Socket Family that VXLAN is notifying us about
8367 * @port: UDP port number that VXLAN stopped listening to
8368 **/
8369static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8370 __be16 port)
8371{
8372 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8373 u16 new_port = ntohs(port);
8374
67359c3c
MR		 8375 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8376 return;
8377
3f207800
DS		 8378 if (sa_family == AF_INET6)
8379 return;
8380
8381 if (adapter->vxlan_port != new_port) {
8382 netdev_info(dev, "Port %d was not found, not deleting\n",
8383 new_port);
8384 return;
8385 }
8386
67359c3c
MR		 8387 ixgbe_clear_vxlan_port(adapter);
8388 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8389}
67359c3c 8390#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8391
edc7d573 8392static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8393 struct net_device *dev,
f6f6424b 8394 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8395 u16 flags)
8396{
bcfd3432 8397 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8398 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 8399 struct ixgbe_adapter *adapter = netdev_priv(dev);
8400 u16 pool = VMDQ_P(0);
8401
8402 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 8403 return -ENOMEM;
0f4b0add
JF		 8404 }
8405
f6f6424b 8406 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8407}
8408
219efe97
DS		 8409/**
8410 * ixgbe_configure_bridge_mode - set various bridge modes
8411 * @adapter - the private structure
8412 * @mode - requested bridge mode
8413 *
8414 * Configure some settings require for various bridge modes.
8415 **/
8416static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8417 __u16 mode)
8418{
6d4c96ad
DS		 8419 struct ixgbe_hw *hw = &adapter->hw;
8420 unsigned int p, num_pools;
8421 u32 vmdctl;
8422
219efe97
DS		 8423 switch (mode) {
8424 case BRIDGE_MODE_VEPA:
6d4c96ad 8425 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8427
8428 /* must enable Rx switching replication to allow multicast
8429 * packet reception on all VFs, and to enable source address
8430 * pruning.
8431 */
8432 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8433 vmdctl |= IXGBE_VT_CTL_REPLEN;
8434 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8435
8436 /* enable Rx source address pruning. Note, this requires
8437 * replication to be enabled or else it does nothing.
8438 */
8439 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8440 for (p = 0; p < num_pools; p++) {
8441 if (hw->mac.ops.set_source_address_pruning)
8442 hw->mac.ops.set_source_address_pruning(hw,
8443 true,
8444 p);
8445 }
219efe97
DS		 8446 break;
8447 case BRIDGE_MODE_VEB:
6d4c96ad 8448 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8449 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8450 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8451
8452 /* disable Rx switching replication unless we have SR-IOV
8453 * virtual functions
8454 */
8455 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8456 if (!adapter->num_vfs)
8457 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8458 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8459
8460 /* disable Rx source address pruning, since we don't expect to
8461 * be receiving external loopback of our transmitted frames.
8462 */
8463 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8464 for (p = 0; p < num_pools; p++) {
8465 if (hw->mac.ops.set_source_address_pruning)
8466 hw->mac.ops.set_source_address_pruning(hw,
8467 false,
8468 p);
8469 }
219efe97
DS		 8470 break;
8471 default:
8472 return -EINVAL;
8473 }
8474
8475 adapter->bridge_mode = mode;
8476
8477 e_info(drv, "enabling bridge mode: %s\n",
8478 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8479
8480 return 0;
8481}
8482
815cccbf 8483static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8484 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8485{
8486 struct ixgbe_adapter *adapter = netdev_priv(dev);
8487 struct nlattr *attr, *br_spec;
8488 int rem;
8489
8490 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8491 return -EOPNOTSUPP;
8492
8493 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8494 if (!br_spec)
8495 return -EINVAL;
815cccbf
JF		 8496
8497 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8498 int status;
815cccbf 8499 __u16 mode;
815cccbf
JF		 8500
8501 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8502 continue;
8503
b7c1a314
TG		 8504 if (nla_len(attr) < sizeof(mode))
8505 return -EINVAL;
8506
815cccbf 8507 mode = nla_get_u16(attr);
219efe97
DS		 8508 status = ixgbe_configure_bridge_mode(adapter, mode);
8509 if (status)
8510 return status;
aa2bacb6
DS		 8511
8512 break;
815cccbf
JF		 8513 }
8514
8515 return 0;
8516}
8517
8518static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8519 struct net_device *dev,
46c264da 8520 u32 filter_mask, int nlflags)
815cccbf
JF		 8521{
8522 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8523
8524 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8525 return 0;
8526
aa2bacb6 8527 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8528 adapter->bridge_mode, 0, 0, nlflags,
8529 filter_mask, NULL);
815cccbf
JF		 8530}
8531
2a47fa45
JF		 8532static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8533{
8534 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8535 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8536 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8537 unsigned int limit;
2a47fa45
JF		 8538 int pool, err;
8539
aac2f1bf
JK		 8540 /* Hardware has a limited number of available pools. Each VF, and the
8541 * PF require a pool. Check to ensure we don't attempt to use more
8542 * then the available number of pools.
8543 */
8544 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8545 return ERR_PTR(-EINVAL);
8546
219354d4
JF		 8547#ifdef CONFIG_RPS
8548 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8549 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8550 vdev->name);
8551 return ERR_PTR(-EINVAL);
8552 }
8553#endif
2a47fa45 8554 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8555 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8556 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8557 netdev_info(pdev,
8558 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8559 pdev->name);
8560 return ERR_PTR(-EINVAL);
8561 }
8562
8563 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8564 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8565 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8566 return ERR_PTR(-EBUSY);
8567
bc52f951 8568 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8569 if (!fwd_adapter)
8570 return ERR_PTR(-ENOMEM);
8571
8572 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8573 adapter->num_rx_pools++;
8574 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8575 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8576
8577 /* Enable VMDq flag so device will be set in VM mode */
8578 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8579 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8580 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8581
8582 /* Force reinit of ring allocation with VMDQ enabled */
8583 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8584 if (err)
8585 goto fwd_add_err;
8586 fwd_adapter->pool = pool;
8587 fwd_adapter->real_adapter = adapter;
8588 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8589 if (err)
8590 goto fwd_add_err;
8591 netif_tx_start_all_queues(vdev);
8592 return fwd_adapter;
8593fwd_add_err:
8594 /* unwind counter and free adapter struct */
8595 netdev_info(pdev,
8596 "%s: dfwd hardware acceleration failed\n", vdev->name);
8597 clear_bit(pool, &adapter->fwd_bitmask);
8598 adapter->num_rx_pools--;
8599 kfree(fwd_adapter);
8600 return ERR_PTR(err);
8601}
8602
8603static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8604{
8605 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8606 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8607 unsigned int limit;
2a47fa45
JF		 8608
8609 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8610 adapter->num_rx_pools--;
8611
51f3773b
JF		 8612 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8613 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8614 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8615 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8616 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8617 fwd_adapter->pool, adapter->num_rx_pools,
8618 fwd_adapter->rx_base_queue,
8619 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8620 adapter->fwd_bitmask);
8621 kfree(fwd_adapter);
8622}
8623
f467bc06
MR		 8624#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8625static netdev_features_t
8626ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8627 netdev_features_t features)
8628{
8629 if (!skb->encapsulation)
8630 return features;
8631
8632 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8633 IXGBE_MAX_TUNNEL_HDR_LEN))
a188222b 8634 return features & ~NETIF_F_CSUM_MASK;
f467bc06
MR		 8635
8636 return features;
8637}
8638
0edc3527 8639static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8640 .ndo_open = ixgbe_open,
0edc3527 8641 .ndo_stop = ixgbe_close,
00829823 8642 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8643 .ndo_select_queue = ixgbe_select_queue,
581330ba 8644 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8645 .ndo_validate_addr = eth_validate_addr,
8646 .ndo_set_mac_address = ixgbe_set_mac,
8647 .ndo_change_mtu = ixgbe_change_mtu,
8648 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8649 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8650 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8651 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8652 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8653 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8654 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8655 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8656 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8657 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8658 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8659 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8660#ifdef CONFIG_IXGBE_DCB
24095aa3 8661 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8662#endif
0edc3527
SH		 8663#ifdef CONFIG_NET_POLL_CONTROLLER
8664 .ndo_poll_controller = ixgbe_netpoll,
8665#endif
e0d1095a 8666#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8667 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8668#endif
332d4a7d
YZ		 8669#ifdef IXGBE_FCOE
8670 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8671 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8672 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8673 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8674 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8675 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8676 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8677#endif /* IXGBE_FCOE */
082757af
DS		 8678 .ndo_set_features = ixgbe_set_features,
8679 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8680 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8681 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8682 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8683 .ndo_dfwd_add_station = ixgbe_fwd_add,
8684 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8685#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8686 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8687 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8688#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8689 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8690};
8691
e027d1ae
JK		 8692/**
8693 * ixgbe_enumerate_functions - Get the number of ports this device has
8694 * @adapter: adapter structure
8695 *
8696 * This function enumerates the phsyical functions co-located on a single slot,
8697 * in order to determine how many ports a device has. This is most useful in
8698 * determining the required GT/s of PCIe bandwidth necessary for optimal
8699 * performance.
8700 **/
8701static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8702{
caafb95d 8703 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8704 int physfns = 0;
8705
f1f96579
JK		 8706 /* Some cards can not use the generic count PCIe functions method,
8707 * because they are behind a parent switch, so we hardcode these with
8708 * the correct number of functions.
e027d1ae 8709 */
8818970d 8710 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8711 physfns = 4;
8818970d
JK		 8712
8713 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8714 /* don't count virtual functions */
caafb95d
JK		 8715 if (entry->is_virtfn)
8716 continue;
8717
8718 /* When the devices on the bus don't all match our device ID,
8719 * we can't reliably determine the correct number of
8720 * functions. This can occur if a function has been direct
8721 * attached to a virtual machine using VT-d, for example. In
8722 * this case, simply return -1 to indicate this.
8723 */
8724 if ((entry->vendor != pdev->vendor) ||
8725 (entry->device != pdev->device))
8726 return -1;
8727
8728 physfns++;
e027d1ae
JK		 8729 }
8730
8731 return physfns;
8732}
8733
8e2813f5
JK		 8734/**
8735 * ixgbe_wol_supported - Check whether device supports WoL
8736 * @hw: hw specific details
8737 * @device_id: the device ID
8738 * @subdev_id: the subsystem device ID
8739 *
8740 * This function is used by probe and ethtool to determine
8741 * which devices have WoL support
8742 *
8743 **/
8744int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8745 u16 subdevice_id)
8746{
8747 struct ixgbe_hw *hw = &adapter->hw;
8748 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8749 int is_wol_supported = 0;
8750
8751 switch (device_id) {
8752 case IXGBE_DEV_ID_82599_SFP:
8753 /* Only these subdevices could supports WOL */
8754 switch (subdevice_id) {
87557440 8755 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8756 case IXGBE_SUBDEV_ID_82599_560FLR:
8757 /* only support first port */
8758 if (hw->bus.func != 0)
8759 break;
5700ff26 8760 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8761 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8762 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8763 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8764 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8765 is_wol_supported = 1;
8766 break;
8767 }
8768 break;
5daebbb0
DS		 8769 case IXGBE_DEV_ID_82599EN_SFP:
8770 /* Only this subdevice supports WOL */
8771 switch (subdevice_id) {
8772 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8773 is_wol_supported = 1;
8774 break;
8775 }
8776 break;
8e2813f5
JK		 8777 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8778 /* All except this subdevice support WOL */
8779 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8780 is_wol_supported = 1;
8781 break;
8782 case IXGBE_DEV_ID_82599_KX4:
8783 is_wol_supported = 1;
8784 break;
8785 case IXGBE_DEV_ID_X540T:
df376f0d 8786 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8787 case IXGBE_DEV_ID_X550T:
8788 case IXGBE_DEV_ID_X550EM_X_KX4:
8789 case IXGBE_DEV_ID_X550EM_X_KR:
8790 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8791 /* check eeprom to see if enabled wol */
8792 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8793 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8794 (hw->bus.func == 0))) {
8795 is_wol_supported = 1;
8796 }
8797 break;
8798 }
8799
8800 return is_wol_supported;
8801}
8802
c762dff2
MP		 8803/**
8804 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8805 * @adapter: Pointer to adapter struct
8806 */
8807static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8808{
8809#ifdef CONFIG_OF
8810 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8811 struct ixgbe_hw *hw = &adapter->hw;
8812 const unsigned char *addr;
8813
8814 addr = of_get_mac_address(dp);
8815 if (addr) {
8816 ether_addr_copy(hw->mac.perm_addr, addr);
8817 return;
8818 }
8819#endif /* CONFIG_OF */
8820
8821#ifdef CONFIG_SPARC
8822 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8823#endif /* CONFIG_SPARC */
8824}
8825
9a799d71
AK		 8826/**
8827 * ixgbe_probe - Device Initialization Routine
8828 * @pdev: PCI device information struct
8829 * @ent: entry in ixgbe_pci_tbl
8830 *
8831 * Returns 0 on success, negative on failure
8832 *
8833 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8834 * The OS initialization, configuring of the adapter private structure,
8835 * and a hardware reset occur.
8836 **/
1dd06ae8 8837static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8838{
8839 struct net_device *netdev;
8840 struct ixgbe_adapter *adapter = NULL;
8841 struct ixgbe_hw *hw;
8842 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8843 int i, err, pci_using_dac, expected_gts;
d3cb9869 8844 unsigned int indices = MAX_TX_QUEUES;
289700db 8845 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8846 bool disable_dev = false;
eacd73f7
YZ		 8847#ifdef IXGBE_FCOE
8848 u16 device_caps;
8849#endif
289700db 8850 u32 eec;
9a799d71 8851
bded64a7
AG		 8852 /* Catch broken hardware that put the wrong VF device ID in
8853 * the PCIe SR-IOV capability.
8854 */
8855 if (pdev->is_virtfn) {
8856 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8857 pci_name(pdev), pdev->vendor, pdev->device);
8858 return -EINVAL;
8859 }
8860
9ce77666 8861 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8862 if (err)
8863 return err;
8864
f5f2eda8 8865 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8866 pci_using_dac = 1;
8867 } else {
f5f2eda8 8868 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8869 if (err) {
f5f2eda8
RK		 8870 dev_err(&pdev->dev,
8871 "No usable DMA configuration, aborting\n");
8872 goto err_dma;
9a799d71
AK		 8873 }
8874 pci_using_dac = 0;
8875 }
8876
9ce77666 8877 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8878 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8879 if (err) {
b8bc0421
DC		 8880 dev_err(&pdev->dev,
8881 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8882 goto err_pci_reg;
8883 }
8884
19d5afd4 8885 pci_enable_pcie_error_reporting(pdev);
6fabd715 8886
9a799d71 8887 pci_set_master(pdev);
fb3b27bc 8888 pci_save_state(pdev);
9a799d71 8889
d3cb9869 8890 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8891#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8892 /* 8 TC w/ 4 queues per TC */
8893 indices = 4 * MAX_TRAFFIC_CLASS;
8894#else
8895 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8896#endif
d3cb9869 8897 }
e901acd6 8898
c85a2618 8899 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8900 if (!netdev) {
8901 err = -ENOMEM;
8902 goto err_alloc_etherdev;
8903 }
8904
9a799d71
AK		 8905 SET_NETDEV_DEV(netdev, &pdev->dev);
8906
9a799d71
AK		 8907 adapter = netdev_priv(netdev);
8908
8909 adapter->netdev = netdev;
8910 adapter->pdev = pdev;
8911 hw = &adapter->hw;
8912 hw->back = adapter;
b3f4d599 8913 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8914
05857980 8915 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8916 pci_resource_len(pdev, 0));
2a1a091c 8917 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8918 if (!hw->hw_addr) {
8919 err = -EIO;
8920 goto err_ioremap;
8921 }
8922
0edc3527 8923 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8924 ixgbe_set_ethtool_ops(netdev);
9a799d71 8925 netdev->watchdog_timeo = 5 * HZ;
339de30f 8926 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8927
9a799d71
AK		 8928 /* Setup hw api */
8929 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8930 hw->mac.type = ii->mac;
9a900eca 8931 hw->mvals = ii->mvals;
9a799d71 8932
c44ade9e
JB		 8933 /* EEPROM */
8934 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8935 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8936 if (ixgbe_removed(hw->hw_addr)) {
8937 err = -EIO;
8938 goto err_ioremap;
8939 }
c44ade9e
JB		 8940 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8941 if (!(eec & (1 << 8)))
8942 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8943
8944 /* PHY */
8945 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8946 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8947 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8948 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8949 hw->phy.mdio.mmds = 0;
8950 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8951 hw->phy.mdio.dev = netdev;
8952 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8953 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8954
8ca783ab 8955 ii->get_invariants(hw);
9a799d71
AK		 8956
8957 /* setup the private structure */
8958 err = ixgbe_sw_init(adapter);
8959 if (err)
8960 goto err_sw_init;
8961
e86bff0e 8962 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8963 switch (adapter->hw.mac.type) {
8964 case ixgbe_mac_82599EB:
8965 case ixgbe_mac_X540:
9a75a1ac
DS		 8966 case ixgbe_mac_X550:
8967 case ixgbe_mac_X550EM_x:
e86bff0e 8968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8969 break;
8970 default:
8971 break;
8972 }
e86bff0e 8973
bf069c97
DS		 8974 /*
8975 * If there is a fan on this device and it has failed log the
8976 * failure.
8977 */
8978 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8979 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8980 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8981 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8982 }
8983
8ef78adc
PWJ		 8984 if (allow_unsupported_sfp)
8985 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8986
c44ade9e 8987 /* reset_hw fills in the perm_addr as well */
119fc60a 8988 hw->phy.reset_if_overtemp = true;
c44ade9e 8989 err = hw->mac.ops.reset_hw(hw);
119fc60a 8990 hw->phy.reset_if_overtemp = false;
29a8dca1 8991 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 8992 err = 0;
8993 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8994 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8995 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8996 goto err_sw_init;
8997 } else if (err) {
849c4542 8998 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8999 goto err_sw_init;
9000 }
9001
99d74487 9002#ifdef CONFIG_PCI_IOV
60a1a680
GR		 9003 /* SR-IOV not supported on the 82598 */
9004 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9005 goto skip_sriov;
9006 /* Mailbox */
9007 ixgbe_init_mbx_params_pf(hw);
9008 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 9009 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 9010 ixgbe_enable_sriov(adapter);
60a1a680 9011skip_sriov:
1cdd1ec8 9012
99d74487 9013#endif
396e799c 9014 netdev->features = NETIF_F_SG |
e8e9f696 9015 NETIF_F_IP_CSUM |
082757af 9016 NETIF_F_IPV6_CSUM |
f646968f
PM		 9017 NETIF_F_HW_VLAN_CTAG_TX |
9018 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 9019 NETIF_F_TSO |
9020 NETIF_F_TSO6 |
082757af 9021 NETIF_F_RXHASH |
8bf1264d 9022 NETIF_F_RXCSUM;
9a799d71 9023
8bf1264d 9024 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 9025
58be7666
DS		 9026 switch (adapter->hw.mac.type) {
9027 case ixgbe_mac_82599EB:
9028 case ixgbe_mac_X540:
9a75a1ac
DS		 9029 case ixgbe_mac_X550:
9030 case ixgbe_mac_X550EM_x:
53692b1d
TH		 9031 netdev->features |= NETIF_F_SCTP_CRC;
9032 netdev->hw_features |= NETIF_F_SCTP_CRC |
082757af 9033 NETIF_F_NTUPLE;
58be7666
DS		 9034 break;
9035 default:
9036 break;
9037 }
45a5ead0 9038
3f2d1c0f 9039 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 9040 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 9041
ad31c402
JK		 9042 netdev->vlan_features |= NETIF_F_TSO;
9043 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 9044 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 9045 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 9046 netdev->vlan_features |= NETIF_F_SG;
9047
fb8ad4a5 9048 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
f467bc06 9049
01789349 9050 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9051 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9052
67359c3c 9053#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 9054 switch (adapter->hw.mac.type) {
9055 case ixgbe_mac_X550:
9056 case ixgbe_mac_X550EM_x:
fb8ad4a5 9057 netdev->hw_enc_features |= NETIF_F_RXCSUM;
3f207800
DS		 9058 break;
9059 default:
9060 break;
9061 }
67359c3c 9062#endif /* CONFIG_IXGBE_VXLAN */
3f207800 9063
7a6b6f51 9064#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 9065 netdev->dcbnl_ops = &dcbnl_ops;
9066#endif
9067
eacd73f7 9068#ifdef IXGBE_FCOE
0d551589 9069 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9070 unsigned int fcoe_l;
9071
eacd73f7
YZ		 9072 if (hw->mac.ops.get_device_caps) {
9073 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9074 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9075 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9076 }
7c8ae65a 9077
d3cb9869
AD		 9078
9079 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9080 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9081
a58915c7
AD		 9082 netdev->features |= NETIF_F_FSO |
9083 NETIF_F_FCOE_CRC;
9084
7c8ae65a
AD		 9085 netdev->vlan_features |= NETIF_F_FSO |
9086 NETIF_F_FCOE_CRC |
9087 NETIF_F_FCOE_MTU;
5e09d7f6 9088 }
eacd73f7 9089#endif /* IXGBE_FCOE */
7b872a55 9090 if (pci_using_dac) {
9a799d71 9091 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 9092 netdev->vlan_features |= NETIF_F_HIGHDMA;
9093 }
9a799d71 9094
082757af
DS		 9095 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9096 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9097 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9098 netdev->features |= NETIF_F_LRO;
9099
9a799d71 9100 /* make sure the EEPROM is good */
c44ade9e 9101 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9102 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9103 err = -EIO;
35937c05 9104 goto err_sw_init;
9a799d71
AK		 9105 }
9106
c762dff2
MP		 9107 ixgbe_get_platform_mac_addr(adapter);
9108
9a799d71 9109 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9110
aaeb6cdf 9111 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9112 e_dev_err("invalid MAC address\n");
9a799d71 9113 err = -EIO;
35937c05 9114 goto err_sw_init;
9a799d71
AK		 9115 }
9116
c9f53e63 9117 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9118
7086400d 9119 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9120 (unsigned long) adapter);
9a799d71 9121
58cf663f
MR		 9122 if (ixgbe_removed(hw->hw_addr)) {
9123 err = -EIO;
9124 goto err_sw_init;
9125 }
7086400d 9126 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9127 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9128 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9129
021230d4
AV		 9130 err = ixgbe_init_interrupt_scheme(adapter);
9131 if (err)
9132 goto err_sw_init;
9a799d71 9133
8e2813f5 9134 /* WOL not supported for all devices */
c23f5b6b 9135 adapter->wol = 0;
8e2813f5 9136 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9137 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9138 pdev->subsystem_device);
6b92b0ba 9139 if (hw->wol_enabled)
9417c464 9140 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9141
e8e26350
PW		 9142 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9143
15e5209f
ET		 9144 /* save off EEPROM version number */
9145 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9146 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9147
04f165ef 9148 /* pick up the PCI bus settings for reporting later */
e027d1ae 9149 if (ixgbe_pcie_from_parent(hw))
b8e82001 9150 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9151 else
9152 hw->mac.ops.get_bus_info(hw);
04f165ef 9153
e027d1ae
JK		 9154 /* calculate the expected PCIe bandwidth required for optimal
9155 * performance. Note that some older parts will never have enough
9156 * bandwidth due to being older generation PCIe parts. We clamp these
9157 * parts to ensure no warning is displayed if it can't be fixed.
9158 */
9159 switch (hw->mac.type) {
9160 case ixgbe_mac_82598EB:
9161 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9162 break;
9163 default:
9164 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9165 break;
0c254d86 9166 }
caafb95d
JK		 9167
9168 /* don't check link if we failed to enumerate functions */
9169 if (expected_gts > 0)
9170 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9171
339de30f 9172 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9173 if (err)
339de30f 9174 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9175 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9176 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9177 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9178 part_str);
6a2aae5a
JK		 9179 else
9180 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9181 hw->mac.type, hw->phy.type, part_str);
9182
9183 e_dev_info("%pM\n", netdev->dev_addr);
9184
9a799d71 9185 /* reset the hardware with the new settings */
794caeb2 9186 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9187 if (err == IXGBE_ERR_EEPROM_VERSION) {
9188 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9189 e_dev_warn("This device is a pre-production adapter/LOM. "
9190 "Please be aware there may be issues associated "
9191 "with your hardware. If you are experiencing "
9192 "problems please contact your Intel or hardware "
9193 "representative who provided you with this "
9194 "hardware.\n");
794caeb2 9195 }
9a799d71
AK		 9196 strcpy(netdev->name, "eth%d");
9197 err = register_netdev(netdev);
9198 if (err)
9199 goto err_register;
9200
0fb6a55c
ET		 9201 pci_set_drvdata(pdev, adapter);
9202
ec74a471
ET		 9203 /* power down the optics for 82599 SFP+ fiber */
9204 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9205 hw->mac.ops.disable_tx_laser(hw);
9206
54386467
JB		 9207 /* carrier off reporting is important to ethtool even BEFORE open */
9208 netif_carrier_off(netdev);
9209
5dd2d332 9210#ifdef CONFIG_IXGBE_DCA
652f093f 9211 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9212 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9213 ixgbe_setup_dca(adapter);
9214 }
9215#endif
1cdd1ec8 9216 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9217 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9218 for (i = 0; i < adapter->num_vfs; i++)
9219 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9220 }
9221
2466dd9c
JK		 9222 /* firmware requires driver version to be 0xFFFFFFFF
9223 * since os does not support feature
9224 */
9612de92 9225 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9226 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9227 0xFF);
9612de92 9228
0365e6e4
PW		 9229 /* add san mac addr to netdev */
9230 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9231
ea81875a 9232 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9233
1210982b 9234#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9235 if (ixgbe_sysfs_init(adapter))
9236 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9237#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9238
00949167 9239 ixgbe_dbg_adapter_init(adapter);
00949167 9240
d1a35ee2
ET		 9241 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9242 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9243 hw->mac.ops.setup_link(hw,
9244 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9245 true);
9246
9a799d71
AK		 9247 return 0;
9248
9249err_register:
5eba3699 9250 ixgbe_release_hw_control(adapter);
7a921c93 9251 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9252err_sw_init:
99d74487 9253 ixgbe_disable_sriov(adapter);
7086400d 9254 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9255 iounmap(adapter->io_addr);
5d7daa35 9256 kfree(adapter->mac_table);
9a799d71 9257err_ioremap:
b5b2ffc0 9258 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9259 free_netdev(netdev);
9260err_alloc_etherdev:
e8e9f696
JP		 9261 pci_release_selected_regions(pdev,
9262 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9263err_pci_reg:
9264err_dma:
b5b2ffc0 9265 if (!adapter || disable_dev)
41c62843 9266 pci_disable_device(pdev);
9a799d71
AK		 9267 return err;
9268}
9269
9270/**
9271 * ixgbe_remove - Device Removal Routine
9272 * @pdev: PCI device information struct
9273 *
9274 * ixgbe_remove is called by the PCI subsystem to alert the driver
9275 * that it should release a PCI device. The could be caused by a
9276 * Hot-Plug event, or because the driver is going to be removed from
9277 * memory.
9278 **/
9f9a12f8 9279static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9280{
c60fbb00 9281 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9282 struct net_device *netdev;
b5b2ffc0 9283 bool disable_dev;
9a799d71 9284
0fb6a55c
ET		 9285 /* if !adapter then we already cleaned up in probe */
9286 if (!adapter)
9287 return;
9288
9289 netdev = adapter->netdev;
00949167 9290 ixgbe_dbg_adapter_exit(adapter);
00949167 9291
09f40aed 9292 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9293 cancel_work_sync(&adapter->service_task);
9a799d71 9294
3a6a4eda 9295
5dd2d332 9296#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9297 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9298 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9299 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9301 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9302 }
9303
9304#endif
1210982b 9305#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9306 ixgbe_sysfs_exit(adapter);
1210982b 9307#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9308
0365e6e4
PW		 9309 /* remove the added san mac */
9310 ixgbe_del_sanmac_netdev(netdev);
9311
da36b647 9312#ifdef CONFIG_PCI_IOV
7837e286 9313 ixgbe_disable_sriov(adapter);
da36b647 9314#endif
6b010e9b
AW		 9315 if (netdev->reg_state == NETREG_REGISTERED)
9316 unregister_netdev(netdev);
9317
7a921c93 9318 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9319
021230d4 9320 ixgbe_release_hw_control(adapter);
9a799d71 9321
2b1588c3
AD		 9322#ifdef CONFIG_DCB
9323 kfree(adapter->ixgbe_ieee_pfc);
9324 kfree(adapter->ixgbe_ieee_ets);
9325
9326#endif
2a1a091c 9327 iounmap(adapter->io_addr);
9ce77666 9328 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9329 IORESOURCE_MEM));
9a799d71 9330
849c4542 9331 e_dev_info("complete\n");
021230d4 9332
5d7daa35 9333 kfree(adapter->mac_table);
b5b2ffc0 9334 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9335 free_netdev(netdev);
9336
19d5afd4 9337 pci_disable_pcie_error_reporting(pdev);
6fabd715 9338
b5b2ffc0 9339 if (disable_dev)
41c62843 9340 pci_disable_device(pdev);
9a799d71
AK		 9341}
9342
9343/**
9344 * ixgbe_io_error_detected - called when PCI error is detected
9345 * @pdev: Pointer to PCI device
9346 * @state: The current pci connection state
9347 *
9348 * This function is called after a PCI bus error affecting
9349 * this device has been detected.
9350 */
9351static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9352 pci_channel_state_t state)
9a799d71 9353{
c60fbb00
AD		 9354 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9355 struct net_device *netdev = adapter->netdev;
9a799d71 9356
83c61fa9 9357#ifdef CONFIG_PCI_IOV
14438464 9358 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9359 struct pci_dev *bdev, *vfdev;
9360 u32 dw0, dw1, dw2, dw3;
9361 int vf, pos;
9362 u16 req_id, pf_func;
9363
9364 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9365 adapter->num_vfs == 0)
9366 goto skip_bad_vf_detection;
9367
9368 bdev = pdev->bus->self;
62f87c0e 9369 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9370 bdev = bdev->bus->self;
9371
9372 if (!bdev)
9373 goto skip_bad_vf_detection;
9374
9375 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9376 if (!pos)
9377 goto skip_bad_vf_detection;
9378
14438464
MR		 9379 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9380 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9381 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9382 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9383 if (ixgbe_removed(hw->hw_addr))
9384 goto skip_bad_vf_detection;
83c61fa9
GR		 9385
9386 req_id = dw1 >> 16;
9387 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9388 if (!(req_id & 0x0080))
9389 goto skip_bad_vf_detection;
9390
9391 pf_func = req_id & 0x01;
9392 if ((pf_func & 1) == (pdev->devfn & 1)) {
9393 unsigned int device_id;
9394
9395 vf = (req_id & 0x7F) >> 1;
9396 e_dev_err("VF %d has caused a PCIe error\n", vf);
9397 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9398 "%8.8x\tdw3: %8.8x\n",
9399 dw0, dw1, dw2, dw3);
9400 switch (adapter->hw.mac.type) {
9401 case ixgbe_mac_82599EB:
9402 device_id = IXGBE_82599_VF_DEVICE_ID;
9403 break;
9404 case ixgbe_mac_X540:
9405 device_id = IXGBE_X540_VF_DEVICE_ID;
9406 break;
9a75a1ac
DS		 9407 case ixgbe_mac_X550:
9408 device_id = IXGBE_DEV_ID_X550_VF;
9409 break;
9410 case ixgbe_mac_X550EM_x:
9411 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9412 break;
83c61fa9
GR		 9413 default:
9414 device_id = 0;
9415 break;
9416 }
9417
9418 /* Find the pci device of the offending VF */
36e90319 9419 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9420 while (vfdev) {
9421 if (vfdev->devfn == (req_id & 0xFF))
9422 break;
36e90319 9423 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9424 device_id, vfdev);
9425 }
9426 /*
9427 * There's a slim chance the VF could have been hot plugged,
9428 * so if it is no longer present we don't need to issue the
9429 * VFLR. Just clean up the AER in that case.
9430 */
9431 if (vfdev) {
9079e416 9432 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9433 /* Free device reference count */
9434 pci_dev_put(vfdev);
83c61fa9
GR		 9435 }
9436
9437 pci_cleanup_aer_uncorrect_error_status(pdev);
9438 }
9439
9440 /*
9441 * Even though the error may have occurred on the other port
9442 * we still need to increment the vf error reference count for
9443 * both ports because the I/O resume function will be called
9444 * for both of them.
9445 */
9446 adapter->vferr_refcount++;
9447
9448 return PCI_ERS_RESULT_RECOVERED;
9449
9450skip_bad_vf_detection:
9451#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9452 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9453 return PCI_ERS_RESULT_DISCONNECT;
9454
41c62843 9455 rtnl_lock();
9a799d71
AK		 9456 netif_device_detach(netdev);
9457
41c62843
MR		 9458 if (state == pci_channel_io_perm_failure) {
9459 rtnl_unlock();
3044b8d1 9460 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9461 }
3044b8d1 9462
9a799d71
AK		 9463 if (netif_running(netdev))
9464 ixgbe_down(adapter);
41c62843
MR		 9465
9466 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9467 pci_disable_device(pdev);
9468 rtnl_unlock();
9a799d71 9469
b4617240 9470 /* Request a slot reset. */
9a799d71
AK		 9471 return PCI_ERS_RESULT_NEED_RESET;
9472}
9473
9474/**
9475 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9476 * @pdev: Pointer to PCI device
9477 *
9478 * Restart the card from scratch, as if from a cold-boot.
9479 */
9480static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9481{
c60fbb00 9482 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9483 pci_ers_result_t result;
9484 int err;
9a799d71 9485
9ce77666 9486 if (pci_enable_device_mem(pdev)) {
396e799c 9487 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9488 result = PCI_ERS_RESULT_DISCONNECT;
9489 } else {
4e857c58 9490 smp_mb__before_atomic();
41c62843 9491 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9492 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9493 pci_set_master(pdev);
9494 pci_restore_state(pdev);
c0e1f68b 9495 pci_save_state(pdev);
9a799d71 9496
dd4d8ca6 9497 pci_wake_from_d3(pdev, false);
9a799d71 9498
6fabd715 9499 ixgbe_reset(adapter);
88512539 9500 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9501 result = PCI_ERS_RESULT_RECOVERED;
9502 }
9503
9504 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9505 if (err) {
849c4542
ET		 9506 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9507 "failed 0x%0x\n", err);
6fabd715
PWJ		 9508 /* non-fatal, continue */
9509 }
9a799d71 9510
6fabd715 9511 return result;
9a799d71
AK		 9512}
9513
9514/**
9515 * ixgbe_io_resume - called when traffic can start flowing again.
9516 * @pdev: Pointer to PCI device
9517 *
9518 * This callback is called when the error recovery driver tells us that
9519 * its OK to resume normal operation.
9520 */
9521static void ixgbe_io_resume(struct pci_dev *pdev)
9522{
c60fbb00
AD		 9523 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9524 struct net_device *netdev = adapter->netdev;
9a799d71 9525
83c61fa9
GR		 9526#ifdef CONFIG_PCI_IOV
9527 if (adapter->vferr_refcount) {
9528 e_info(drv, "Resuming after VF err\n");
9529 adapter->vferr_refcount--;
9530 return;
9531 }
9532
9533#endif
c7ccde0f
AD		 9534 if (netif_running(netdev))
9535 ixgbe_up(adapter);
9a799d71
AK		 9536
9537 netif_device_attach(netdev);
9a799d71
AK		 9538}
9539
3646f0e5 9540static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9541 .error_detected = ixgbe_io_error_detected,
9542 .slot_reset = ixgbe_io_slot_reset,
9543 .resume = ixgbe_io_resume,
9544};
9545
9546static struct pci_driver ixgbe_driver = {
9547 .name = ixgbe_driver_name,
9548 .id_table = ixgbe_pci_tbl,
9549 .probe = ixgbe_probe,
9f9a12f8 9550 .remove = ixgbe_remove,
9a799d71
AK		 9551#ifdef CONFIG_PM
9552 .suspend = ixgbe_suspend,
9553 .resume = ixgbe_resume,
9554#endif
9555 .shutdown = ixgbe_shutdown,
da36b647 9556 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9557 .err_handler = &ixgbe_err_handler
9558};
9559
9560/**
9561 * ixgbe_init_module - Driver Registration Routine
9562 *
9563 * ixgbe_init_module is the first routine called when the driver is
9564 * loaded. All it does is register with the PCI subsystem.
9565 **/
9566static int __init ixgbe_init_module(void)
9567{
9568 int ret;
c7689578 9569 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9570 pr_info("%s\n", ixgbe_copyright);
9a799d71 9571
780484d8
MR		 9572 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9573 if (!ixgbe_wq) {
9574 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9575 return -ENOMEM;
9576 }
9577
00949167 9578 ixgbe_dbg_init();
00949167 9579
f01fc1a8
JK		 9580 ret = pci_register_driver(&ixgbe_driver);
9581 if (ret) {
f01fc1a8 9582 ixgbe_dbg_exit();
f01fc1a8
JK		 9583 return ret;
9584 }
9585
5dd2d332 9586#ifdef CONFIG_IXGBE_DCA
bd0362dd 9587 dca_register_notify(&dca_notifier);
bd0362dd 9588#endif
5dd2d332 9589
f01fc1a8 9590 return 0;
9a799d71 9591}
b4617240 9592
9a799d71
AK		 9593module_init(ixgbe_init_module);
9594
9595/**
9596 * ixgbe_exit_module - Driver Exit Cleanup Routine
9597 *
9598 * ixgbe_exit_module is called just before the driver is removed
9599 * from memory.
9600 **/
9601static void __exit ixgbe_exit_module(void)
9602{
5dd2d332 9603#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9604 dca_unregister_notify(&dca_notifier);
9605#endif
9a799d71 9606 pci_unregister_driver(&ixgbe_driver);
00949167 9607
00949167 9608 ixgbe_dbg_exit();
780484d8
MR		 9609 if (ixgbe_wq) {
9610 destroy_workqueue(ixgbe_wq);
9611 ixgbe_wq = NULL;
9612 }
9a799d71 9613}
bd0362dd 9614
5dd2d332 9615#ifdef CONFIG_IXGBE_DCA
bd0362dd 9616static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9617 void *p)
bd0362dd
JC		 9618{
9619 int ret_val;
9620
9621 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9622 __ixgbe_notify_dca);
bd0362dd
JC		 9623
9624 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9625}
b453368d 9626
5dd2d332 9627#endif /* CONFIG_IXGBE_DCA */
849c4542 9628
9a799d71
AK		 9629module_exit(ixgbe_exit_module);
9630
9631/* ixgbe_main.c */
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