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6a14ee0c DS |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel 10 Gigabit PCI Express Linux driver | |
4 | * Copyright(c) 1999 - 2014 Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * The full GNU General Public License is included in this distribution in | |
16 | * the file called "COPYING". | |
17 | * | |
18 | * Contact Information: | |
19 | * Linux NICS <linux.nics@intel.com> | |
20 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
21 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
22 | * | |
23 | ******************************************************************************/ | |
24 | #include "ixgbe_x540.h" | |
25 | #include "ixgbe_type.h" | |
26 | #include "ixgbe_common.h" | |
27 | #include "ixgbe_phy.h" | |
28 | ||
29 | /** ixgbe_identify_phy_x550em - Get PHY type based on device id | |
30 | * @hw: pointer to hardware structure | |
31 | * | |
32 | * Returns error code | |
33 | */ | |
34 | static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) | |
35 | { | |
36 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
37 | ||
38 | switch (hw->device_id) { | |
39 | case IXGBE_DEV_ID_X550EM_X_SFP: | |
40 | /* set up for CS4227 usage */ | |
41 | hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | |
42 | if (hw->bus.lan_id) { | |
43 | esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); | |
44 | esdp |= IXGBE_ESDP_SDP1_DIR; | |
45 | } | |
46 | esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); | |
47 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); | |
48 | ||
49 | return ixgbe_identify_module_generic(hw); | |
50 | case IXGBE_DEV_ID_X550EM_X_KX4: | |
51 | hw->phy.type = ixgbe_phy_x550em_kx4; | |
52 | break; | |
53 | case IXGBE_DEV_ID_X550EM_X_KR: | |
54 | hw->phy.type = ixgbe_phy_x550em_kr; | |
55 | break; | |
56 | case IXGBE_DEV_ID_X550EM_X_1G_T: | |
57 | case IXGBE_DEV_ID_X550EM_X_10G_T: | |
58 | return ixgbe_identify_phy_generic(hw); | |
59 | default: | |
60 | break; | |
61 | } | |
62 | return 0; | |
63 | } | |
64 | ||
65 | static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, | |
66 | u32 device_type, u16 *phy_data) | |
67 | { | |
68 | return IXGBE_NOT_IMPLEMENTED; | |
69 | } | |
70 | ||
71 | static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, | |
72 | u32 device_type, u16 phy_data) | |
73 | { | |
74 | return IXGBE_NOT_IMPLEMENTED; | |
75 | } | |
76 | ||
77 | /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params | |
78 | * @hw: pointer to hardware structure | |
79 | * | |
80 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
81 | * ixgbe_hw struct in order to set up EEPROM access. | |
82 | **/ | |
7ddbde3f | 83 | static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) |
6a14ee0c DS |
84 | { |
85 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
86 | u32 eec; | |
87 | u16 eeprom_size; | |
88 | ||
89 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
90 | eeprom->semaphore_delay = 10; | |
91 | eeprom->type = ixgbe_flash; | |
92 | ||
93 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
94 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
95 | IXGBE_EEC_SIZE_SHIFT); | |
96 | eeprom->word_size = 1 << (eeprom_size + | |
97 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
98 | ||
99 | hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", | |
100 | eeprom->type, eeprom->word_size); | |
101 | } | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
ae14a1d8 MR |
106 | /** |
107 | * ixgbe_iosf_wait - Wait for IOSF command completion | |
108 | * @hw: pointer to hardware structure | |
109 | * @ctrl: pointer to location to receive final IOSF control value | |
110 | * | |
111 | * Return: failing status on timeout | |
112 | * | |
113 | * Note: ctrl can be NULL if the IOSF control register value is not needed | |
114 | */ | |
115 | static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) | |
116 | { | |
117 | u32 i, command; | |
118 | ||
119 | /* Check every 10 usec to see if the address cycle completed. | |
120 | * The SB IOSF BUSY bit will clear when the operation is | |
121 | * complete. | |
122 | */ | |
123 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | |
124 | command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); | |
125 | if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) | |
126 | break; | |
127 | usleep_range(10, 20); | |
128 | } | |
129 | if (ctrl) | |
130 | *ctrl = command; | |
131 | if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { | |
132 | hw_dbg(hw, "IOSF wait timed out\n"); | |
133 | return IXGBE_ERR_PHY; | |
134 | } | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
6a14ee0c DS |
139 | /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the |
140 | * IOSF device | |
141 | * @hw: pointer to hardware structure | |
142 | * @reg_addr: 32 bit PHY register to write | |
143 | * @device_type: 3 bit device type | |
144 | * @phy_data: Pointer to read data from the register | |
145 | **/ | |
7ddbde3f DS |
146 | static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, |
147 | u32 device_type, u32 *data) | |
6a14ee0c | 148 | { |
ae14a1d8 MR |
149 | u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; |
150 | u32 command, error; | |
151 | s32 ret; | |
152 | ||
153 | ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); | |
154 | if (ret) | |
155 | return ret; | |
156 | ||
157 | ret = ixgbe_iosf_wait(hw, NULL); | |
158 | if (ret) | |
159 | goto out; | |
6a14ee0c DS |
160 | |
161 | command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | | |
162 | (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); | |
163 | ||
164 | /* Write IOSF control register */ | |
165 | IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); | |
166 | ||
ae14a1d8 | 167 | ret = ixgbe_iosf_wait(hw, &command); |
6a14ee0c DS |
168 | |
169 | if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { | |
170 | error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> | |
171 | IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; | |
172 | hw_dbg(hw, "Failed to read, error %x\n", error); | |
173 | return IXGBE_ERR_PHY; | |
174 | } | |
175 | ||
ae14a1d8 MR |
176 | if (!ret) |
177 | *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); | |
6a14ee0c | 178 | |
ae14a1d8 MR |
179 | out: |
180 | hw->mac.ops.release_swfw_sync(hw, gssr); | |
181 | return ret; | |
6a14ee0c DS |
182 | } |
183 | ||
184 | /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface | |
185 | * command assuming that the semaphore is already obtained. | |
186 | * @hw: pointer to hardware structure | |
187 | * @offset: offset of word in the EEPROM to read | |
188 | * @data: word read from the EEPROM | |
189 | * | |
190 | * Reads a 16 bit word from the EEPROM using the hostif. | |
191 | **/ | |
7ddbde3f DS |
192 | static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, |
193 | u16 *data) | |
6a14ee0c DS |
194 | { |
195 | s32 status; | |
196 | struct ixgbe_hic_read_shadow_ram buffer; | |
197 | ||
198 | buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; | |
199 | buffer.hdr.req.buf_lenh = 0; | |
200 | buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; | |
201 | buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | |
202 | ||
203 | /* convert offset from words to bytes */ | |
204 | buffer.address = cpu_to_be32(offset * 2); | |
205 | /* one word */ | |
206 | buffer.length = cpu_to_be16(sizeof(u16)); | |
207 | ||
208 | status = ixgbe_host_interface_command(hw, (u32 *)&buffer, | |
209 | sizeof(buffer), | |
210 | IXGBE_HI_COMMAND_TIMEOUT, false); | |
211 | if (status) | |
212 | return status; | |
213 | ||
214 | *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, | |
215 | FW_NVM_DATA_OFFSET); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif | |
221 | * @hw: pointer to hardware structure | |
222 | * @offset: offset of word in the EEPROM to read | |
223 | * @words: number of words | |
224 | * @data: word(s) read from the EEPROM | |
225 | * | |
226 | * Reads a 16 bit word(s) from the EEPROM using the hostif. | |
227 | **/ | |
7ddbde3f DS |
228 | static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, |
229 | u16 offset, u16 words, u16 *data) | |
6a14ee0c DS |
230 | { |
231 | struct ixgbe_hic_read_shadow_ram buffer; | |
232 | u32 current_word = 0; | |
233 | u16 words_to_read; | |
234 | s32 status; | |
235 | u32 i; | |
236 | ||
237 | /* Take semaphore for the entire operation. */ | |
238 | status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
239 | if (status) { | |
240 | hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); | |
241 | return status; | |
242 | } | |
243 | ||
244 | while (words) { | |
245 | if (words > FW_MAX_READ_BUFFER_SIZE / 2) | |
246 | words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; | |
247 | else | |
248 | words_to_read = words; | |
249 | ||
250 | buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; | |
251 | buffer.hdr.req.buf_lenh = 0; | |
252 | buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; | |
253 | buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | |
254 | ||
255 | /* convert offset from words to bytes */ | |
256 | buffer.address = cpu_to_be32((offset + current_word) * 2); | |
257 | buffer.length = cpu_to_be16(words_to_read * 2); | |
258 | ||
259 | status = ixgbe_host_interface_command(hw, (u32 *)&buffer, | |
260 | sizeof(buffer), | |
261 | IXGBE_HI_COMMAND_TIMEOUT, | |
262 | false); | |
263 | if (status) { | |
264 | hw_dbg(hw, "Host interface command failed\n"); | |
265 | goto out; | |
266 | } | |
267 | ||
268 | for (i = 0; i < words_to_read; i++) { | |
269 | u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + | |
270 | 2 * i; | |
271 | u32 value = IXGBE_READ_REG(hw, reg); | |
272 | ||
273 | data[current_word] = (u16)(value & 0xffff); | |
274 | current_word++; | |
275 | i++; | |
276 | if (i < words_to_read) { | |
277 | value >>= 16; | |
278 | data[current_word] = (u16)(value & 0xffff); | |
279 | current_word++; | |
280 | } | |
281 | } | |
282 | words -= words_to_read; | |
283 | } | |
284 | ||
285 | out: | |
286 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
287 | return status; | |
288 | } | |
289 | ||
290 | /** ixgbe_checksum_ptr_x550 - Checksum one pointer region | |
291 | * @hw: pointer to hardware structure | |
292 | * @ptr: pointer offset in eeprom | |
293 | * @size: size of section pointed by ptr, if 0 first word will be used as size | |
294 | * @csum: address of checksum to update | |
295 | * | |
296 | * Returns error status for any failure | |
297 | **/ | |
298 | static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, | |
299 | u16 size, u16 *csum, u16 *buffer, | |
300 | u32 buffer_size) | |
301 | { | |
302 | u16 buf[256]; | |
303 | s32 status; | |
304 | u16 length, bufsz, i, start; | |
305 | u16 *local_buffer; | |
306 | ||
307 | bufsz = sizeof(buf) / sizeof(buf[0]); | |
308 | ||
309 | /* Read a chunk at the pointer location */ | |
310 | if (!buffer) { | |
311 | status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); | |
312 | if (status) { | |
313 | hw_dbg(hw, "Failed to read EEPROM image\n"); | |
314 | return status; | |
315 | } | |
316 | local_buffer = buf; | |
317 | } else { | |
318 | if (buffer_size < ptr) | |
319 | return IXGBE_ERR_PARAM; | |
320 | local_buffer = &buffer[ptr]; | |
321 | } | |
322 | ||
323 | if (size) { | |
324 | start = 0; | |
325 | length = size; | |
326 | } else { | |
327 | start = 1; | |
328 | length = local_buffer[0]; | |
329 | ||
330 | /* Skip pointer section if length is invalid. */ | |
331 | if (length == 0xFFFF || length == 0 || | |
332 | (ptr + length) >= hw->eeprom.word_size) | |
333 | return 0; | |
334 | } | |
335 | ||
336 | if (buffer && ((u32)start + (u32)length > buffer_size)) | |
337 | return IXGBE_ERR_PARAM; | |
338 | ||
339 | for (i = start; length; i++, length--) { | |
340 | if (i == bufsz && !buffer) { | |
341 | ptr += bufsz; | |
342 | i = 0; | |
343 | if (length < bufsz) | |
344 | bufsz = length; | |
345 | ||
346 | /* Read a chunk at the pointer location */ | |
347 | status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, | |
348 | bufsz, buf); | |
349 | if (status) { | |
350 | hw_dbg(hw, "Failed to read EEPROM image\n"); | |
351 | return status; | |
352 | } | |
353 | } | |
354 | *csum += local_buffer[i]; | |
355 | } | |
356 | return 0; | |
357 | } | |
358 | ||
359 | /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum | |
360 | * @hw: pointer to hardware structure | |
361 | * @buffer: pointer to buffer containing calculated checksum | |
362 | * @buffer_size: size of buffer | |
363 | * | |
364 | * Returns a negative error code on error, or the 16-bit checksum | |
365 | **/ | |
7ddbde3f DS |
366 | static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, |
367 | u32 buffer_size) | |
6a14ee0c DS |
368 | { |
369 | u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; | |
370 | u16 *local_buffer; | |
371 | s32 status; | |
372 | u16 checksum = 0; | |
373 | u16 pointer, i, size; | |
374 | ||
375 | hw->eeprom.ops.init_params(hw); | |
376 | ||
377 | if (!buffer) { | |
378 | /* Read pointer area */ | |
379 | status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, | |
380 | IXGBE_EEPROM_LAST_WORD + 1, | |
381 | eeprom_ptrs); | |
382 | if (status) { | |
383 | hw_dbg(hw, "Failed to read EEPROM image\n"); | |
384 | return status; | |
385 | } | |
386 | local_buffer = eeprom_ptrs; | |
387 | } else { | |
388 | if (buffer_size < IXGBE_EEPROM_LAST_WORD) | |
389 | return IXGBE_ERR_PARAM; | |
390 | local_buffer = buffer; | |
391 | } | |
392 | ||
393 | /* For X550 hardware include 0x0-0x41 in the checksum, skip the | |
394 | * checksum word itself | |
395 | */ | |
396 | for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) | |
397 | if (i != IXGBE_EEPROM_CHECKSUM) | |
398 | checksum += local_buffer[i]; | |
399 | ||
400 | /* Include all data from pointers 0x3, 0x6-0xE. This excludes the | |
401 | * FW, PHY module, and PCIe Expansion/Option ROM pointers. | |
402 | */ | |
403 | for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { | |
404 | if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) | |
405 | continue; | |
406 | ||
407 | pointer = local_buffer[i]; | |
408 | ||
409 | /* Skip pointer section if the pointer is invalid. */ | |
410 | if (pointer == 0xFFFF || pointer == 0 || | |
411 | pointer >= hw->eeprom.word_size) | |
412 | continue; | |
413 | ||
414 | switch (i) { | |
415 | case IXGBE_PCIE_GENERAL_PTR: | |
416 | size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; | |
417 | break; | |
418 | case IXGBE_PCIE_CONFIG0_PTR: | |
419 | case IXGBE_PCIE_CONFIG1_PTR: | |
420 | size = IXGBE_PCIE_CONFIG_SIZE; | |
421 | break; | |
422 | default: | |
423 | size = 0; | |
424 | break; | |
425 | } | |
426 | ||
427 | status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, | |
428 | buffer, buffer_size); | |
429 | if (status) | |
430 | return status; | |
431 | } | |
432 | ||
433 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
434 | ||
435 | return (s32)checksum; | |
436 | } | |
437 | ||
438 | /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum | |
439 | * @hw: pointer to hardware structure | |
440 | * | |
441 | * Returns a negative error code on error, or the 16-bit checksum | |
442 | **/ | |
7ddbde3f | 443 | static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) |
6a14ee0c DS |
444 | { |
445 | return ixgbe_calc_checksum_X550(hw, NULL, 0); | |
446 | } | |
447 | ||
448 | /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command | |
449 | * @hw: pointer to hardware structure | |
450 | * @offset: offset of word in the EEPROM to read | |
451 | * @data: word read from the EEPROM | |
452 | * | |
453 | * Reads a 16 bit word from the EEPROM using the hostif. | |
454 | **/ | |
7ddbde3f | 455 | static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) |
6a14ee0c DS |
456 | { |
457 | s32 status = 0; | |
458 | ||
459 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { | |
460 | status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); | |
461 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
462 | } else { | |
463 | status = IXGBE_ERR_SWFW_SYNC; | |
464 | } | |
465 | ||
466 | return status; | |
467 | } | |
468 | ||
469 | /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum | |
470 | * @hw: pointer to hardware structure | |
471 | * @checksum_val: calculated checksum | |
472 | * | |
473 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
474 | * caller does not need checksum_val, the value can be NULL. | |
475 | **/ | |
7ddbde3f DS |
476 | static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, |
477 | u16 *checksum_val) | |
6a14ee0c DS |
478 | { |
479 | s32 status; | |
480 | u16 checksum; | |
481 | u16 read_checksum = 0; | |
482 | ||
483 | /* Read the first word from the EEPROM. If this times out or fails, do | |
484 | * not continue or we could be in for a very long wait while every | |
485 | * EEPROM read fails | |
486 | */ | |
487 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
488 | if (status) { | |
489 | hw_dbg(hw, "EEPROM read failed\n"); | |
490 | return status; | |
491 | } | |
492 | ||
493 | status = hw->eeprom.ops.calc_checksum(hw); | |
494 | if (status < 0) | |
495 | return status; | |
496 | ||
497 | checksum = (u16)(status & 0xffff); | |
498 | ||
499 | status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, | |
500 | &read_checksum); | |
501 | if (status) | |
502 | return status; | |
503 | ||
504 | /* Verify read checksum from EEPROM is the same as | |
505 | * calculated checksum | |
506 | */ | |
507 | if (read_checksum != checksum) { | |
508 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
509 | hw_dbg(hw, "Invalid EEPROM checksum"); | |
510 | } | |
511 | ||
512 | /* If the user cares, return the calculated checksum */ | |
513 | if (checksum_val) | |
514 | *checksum_val = checksum; | |
515 | ||
516 | return status; | |
517 | } | |
518 | ||
519 | /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif | |
520 | * @hw: pointer to hardware structure | |
521 | * @offset: offset of word in the EEPROM to write | |
522 | * @data: word write to the EEPROM | |
523 | * | |
524 | * Write a 16 bit word to the EEPROM using the hostif. | |
525 | **/ | |
7ddbde3f DS |
526 | static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, |
527 | u16 data) | |
6a14ee0c DS |
528 | { |
529 | s32 status; | |
530 | struct ixgbe_hic_write_shadow_ram buffer; | |
531 | ||
532 | buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; | |
533 | buffer.hdr.req.buf_lenh = 0; | |
534 | buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; | |
535 | buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | |
536 | ||
537 | /* one word */ | |
538 | buffer.length = cpu_to_be16(sizeof(u16)); | |
539 | buffer.data = data; | |
540 | buffer.address = cpu_to_be32(offset * 2); | |
541 | ||
542 | status = ixgbe_host_interface_command(hw, (u32 *)&buffer, | |
543 | sizeof(buffer), | |
544 | IXGBE_HI_COMMAND_TIMEOUT, false); | |
545 | return status; | |
546 | } | |
547 | ||
548 | /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif | |
549 | * @hw: pointer to hardware structure | |
550 | * @offset: offset of word in the EEPROM to write | |
551 | * @data: word write to the EEPROM | |
552 | * | |
553 | * Write a 16 bit word to the EEPROM using the hostif. | |
554 | **/ | |
7ddbde3f | 555 | static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) |
6a14ee0c DS |
556 | { |
557 | s32 status = 0; | |
558 | ||
559 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { | |
560 | status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); | |
561 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
562 | } else { | |
563 | hw_dbg(hw, "write ee hostif failed to get semaphore"); | |
564 | status = IXGBE_ERR_SWFW_SYNC; | |
565 | } | |
566 | ||
567 | return status; | |
568 | } | |
569 | ||
570 | /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device | |
571 | * @hw: pointer to hardware structure | |
572 | * | |
573 | * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. | |
574 | **/ | |
7ddbde3f | 575 | static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) |
6a14ee0c DS |
576 | { |
577 | s32 status = 0; | |
578 | union ixgbe_hic_hdr2 buffer; | |
579 | ||
580 | buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; | |
581 | buffer.req.buf_lenh = 0; | |
582 | buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; | |
583 | buffer.req.checksum = FW_DEFAULT_CHECKSUM; | |
584 | ||
585 | status = ixgbe_host_interface_command(hw, (u32 *)&buffer, | |
586 | sizeof(buffer), | |
587 | IXGBE_HI_COMMAND_TIMEOUT, false); | |
588 | return status; | |
589 | } | |
590 | ||
1f9ac57c DS |
591 | /** ixgbe_disable_rx_x550 - Disable RX unit |
592 | * | |
593 | * Enables the Rx DMA unit for x550 | |
594 | **/ | |
595 | static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) | |
596 | { | |
597 | u32 rxctrl, pfdtxgswc; | |
598 | s32 status; | |
599 | struct ixgbe_hic_disable_rxen fw_cmd; | |
600 | ||
601 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
602 | if (rxctrl & IXGBE_RXCTRL_RXEN) { | |
603 | pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); | |
604 | if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { | |
605 | pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; | |
606 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); | |
607 | hw->mac.set_lben = true; | |
608 | } else { | |
609 | hw->mac.set_lben = false; | |
610 | } | |
611 | ||
612 | fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; | |
613 | fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; | |
614 | fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; | |
615 | fw_cmd.port_number = (u8)hw->bus.lan_id; | |
616 | ||
617 | status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, | |
618 | sizeof(struct ixgbe_hic_disable_rxen), | |
619 | IXGBE_HI_COMMAND_TIMEOUT, true); | |
620 | ||
621 | /* If we fail - disable RX using register write */ | |
622 | if (status) { | |
623 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
624 | if (rxctrl & IXGBE_RXCTRL_RXEN) { | |
625 | rxctrl &= ~IXGBE_RXCTRL_RXEN; | |
626 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); | |
627 | } | |
628 | } | |
629 | } | |
630 | } | |
631 | ||
6a14ee0c DS |
632 | /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash |
633 | * @hw: pointer to hardware structure | |
634 | * | |
635 | * After writing EEPROM to shadow RAM using EEWR register, software calculates | |
636 | * checksum and updates the EEPROM and instructs the hardware to update | |
637 | * the flash. | |
638 | **/ | |
7ddbde3f | 639 | static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) |
6a14ee0c DS |
640 | { |
641 | s32 status; | |
642 | u16 checksum = 0; | |
643 | ||
644 | /* Read the first word from the EEPROM. If this times out or fails, do | |
645 | * not continue or we could be in for a very long wait while every | |
646 | * EEPROM read fails | |
647 | */ | |
648 | status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); | |
649 | if (status) { | |
650 | hw_dbg(hw, "EEPROM read failed\n"); | |
651 | return status; | |
652 | } | |
653 | ||
654 | status = ixgbe_calc_eeprom_checksum_X550(hw); | |
655 | if (status < 0) | |
656 | return status; | |
657 | ||
658 | checksum = (u16)(status & 0xffff); | |
659 | ||
660 | status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, | |
661 | checksum); | |
662 | if (status) | |
663 | return status; | |
664 | ||
665 | status = ixgbe_update_flash_X550(hw); | |
666 | ||
667 | return status; | |
668 | } | |
669 | ||
670 | /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif | |
671 | * @hw: pointer to hardware structure | |
672 | * @offset: offset of word in the EEPROM to write | |
673 | * @words: number of words | |
674 | * @data: word(s) write to the EEPROM | |
675 | * | |
676 | * | |
677 | * Write a 16 bit word(s) to the EEPROM using the hostif. | |
678 | **/ | |
7ddbde3f DS |
679 | static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, |
680 | u16 offset, u16 words, | |
681 | u16 *data) | |
6a14ee0c DS |
682 | { |
683 | s32 status = 0; | |
684 | u32 i = 0; | |
685 | ||
686 | /* Take semaphore for the entire operation. */ | |
687 | status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
688 | if (status) { | |
689 | hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); | |
690 | return status; | |
691 | } | |
692 | ||
693 | for (i = 0; i < words; i++) { | |
694 | status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, | |
695 | data[i]); | |
696 | if (status) { | |
697 | hw_dbg(hw, "Eeprom buffered write failed\n"); | |
698 | break; | |
699 | } | |
700 | } | |
701 | ||
702 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
703 | ||
704 | return status; | |
705 | } | |
706 | ||
707 | /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers | |
708 | * @hw: pointer to hardware structure | |
709 | **/ | |
7ddbde3f | 710 | static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
711 | { |
712 | struct ixgbe_mac_info *mac = &hw->mac; | |
713 | ||
714 | /* CS4227 does not support autoneg, so disable the laser control | |
715 | * functions for SFP+ fiber | |
716 | */ | |
717 | if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) { | |
718 | mac->ops.disable_tx_laser = NULL; | |
719 | mac->ops.enable_tx_laser = NULL; | |
720 | mac->ops.flap_tx_laser = NULL; | |
721 | } | |
722 | } | |
723 | ||
724 | /** ixgbe_setup_sfp_modules_X550em - Setup SFP module | |
725 | * @hw: pointer to hardware structure | |
726 | */ | |
7ddbde3f | 727 | static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
728 | { |
729 | bool setup_linear; | |
730 | u16 reg_slice, edc_mode; | |
731 | s32 ret_val; | |
732 | ||
733 | switch (hw->phy.sfp_type) { | |
734 | case ixgbe_sfp_type_unknown: | |
735 | return 0; | |
736 | case ixgbe_sfp_type_not_present: | |
737 | return IXGBE_ERR_SFP_NOT_PRESENT; | |
738 | case ixgbe_sfp_type_da_cu_core0: | |
739 | case ixgbe_sfp_type_da_cu_core1: | |
740 | setup_linear = true; | |
741 | break; | |
742 | case ixgbe_sfp_type_srlr_core0: | |
743 | case ixgbe_sfp_type_srlr_core1: | |
744 | case ixgbe_sfp_type_da_act_lmt_core0: | |
745 | case ixgbe_sfp_type_da_act_lmt_core1: | |
746 | case ixgbe_sfp_type_1g_sx_core0: | |
747 | case ixgbe_sfp_type_1g_sx_core1: | |
748 | setup_linear = false; | |
749 | break; | |
750 | default: | |
751 | return IXGBE_ERR_SFP_NOT_SUPPORTED; | |
752 | } | |
753 | ||
754 | ixgbe_init_mac_link_ops_X550em(hw); | |
755 | hw->phy.ops.reset = NULL; | |
756 | ||
757 | /* The CS4227 slice address is the base address + the port-pair reg | |
758 | * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0. | |
759 | */ | |
760 | reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12); | |
761 | ||
762 | if (setup_linear) | |
763 | edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; | |
764 | else | |
765 | edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; | |
766 | ||
767 | /* Configure CS4227 for connection type. */ | |
768 | ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice, | |
769 | edc_mode); | |
770 | ||
771 | if (ret_val) | |
772 | ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice, | |
773 | edc_mode); | |
774 | ||
775 | return ret_val; | |
776 | } | |
777 | ||
778 | /** ixgbe_get_link_capabilities_x550em - Determines link capabilities | |
779 | * @hw: pointer to hardware structure | |
780 | * @speed: pointer to link speed | |
781 | * @autoneg: true when autoneg or autotry is enabled | |
782 | **/ | |
7ddbde3f DS |
783 | static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, |
784 | ixgbe_link_speed *speed, | |
785 | bool *autoneg) | |
6a14ee0c DS |
786 | { |
787 | /* SFP */ | |
788 | if (hw->phy.media_type == ixgbe_media_type_fiber) { | |
789 | /* CS4227 SFP must not enable auto-negotiation */ | |
790 | *autoneg = false; | |
791 | ||
792 | if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || | |
793 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { | |
794 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
795 | return 0; | |
796 | } | |
797 | ||
798 | /* Link capabilities are based on SFP */ | |
799 | if (hw->phy.multispeed_fiber) | |
800 | *speed = IXGBE_LINK_SPEED_10GB_FULL | | |
801 | IXGBE_LINK_SPEED_1GB_FULL; | |
802 | else | |
803 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
804 | } else { | |
805 | *speed = IXGBE_LINK_SPEED_10GB_FULL | | |
806 | IXGBE_LINK_SPEED_1GB_FULL; | |
807 | *autoneg = true; | |
808 | } | |
809 | return 0; | |
810 | } | |
811 | ||
812 | /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the | |
813 | * IOSF device | |
814 | * | |
815 | * @hw: pointer to hardware structure | |
816 | * @reg_addr: 32 bit PHY register to write | |
817 | * @device_type: 3 bit device type | |
818 | * @data: Data to write to the register | |
819 | **/ | |
7ddbde3f DS |
820 | static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, |
821 | u32 device_type, u32 data) | |
6a14ee0c | 822 | { |
ae14a1d8 MR |
823 | u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; |
824 | u32 command, error; | |
825 | s32 ret; | |
826 | ||
827 | ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); | |
828 | if (ret) | |
829 | return ret; | |
830 | ||
831 | ret = ixgbe_iosf_wait(hw, NULL); | |
832 | if (ret) | |
833 | goto out; | |
6a14ee0c DS |
834 | |
835 | command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | | |
836 | (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); | |
837 | ||
838 | /* Write IOSF control register */ | |
839 | IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); | |
840 | ||
841 | /* Write IOSF data register */ | |
842 | IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); | |
843 | ||
ae14a1d8 | 844 | ret = ixgbe_iosf_wait(hw, &command); |
6a14ee0c DS |
845 | |
846 | if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { | |
847 | error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> | |
848 | IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; | |
849 | hw_dbg(hw, "Failed to write, error %x\n", error); | |
850 | return IXGBE_ERR_PHY; | |
851 | } | |
852 | ||
ae14a1d8 MR |
853 | out: |
854 | hw->mac.ops.release_swfw_sync(hw, gssr); | |
855 | return ret; | |
6a14ee0c DS |
856 | } |
857 | ||
858 | /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. | |
859 | * @hw: pointer to hardware structure | |
860 | * @speed: the link speed to force | |
861 | * | |
862 | * Configures the integrated KR PHY to use iXFI mode. Used to connect an | |
863 | * internal and external PHY at a specific speed, without autonegotiation. | |
864 | **/ | |
865 | static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) | |
866 | { | |
867 | s32 status; | |
868 | u32 reg_val; | |
869 | ||
870 | /* Disable AN and force speed to 10G Serial. */ | |
871 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
872 | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | |
873 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
874 | if (status) | |
875 | return status; | |
876 | ||
877 | reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; | |
878 | reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; | |
879 | ||
880 | /* Select forced link speed for internal PHY. */ | |
881 | switch (*speed) { | |
882 | case IXGBE_LINK_SPEED_10GB_FULL: | |
883 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; | |
884 | break; | |
885 | case IXGBE_LINK_SPEED_1GB_FULL: | |
886 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; | |
887 | break; | |
888 | default: | |
889 | /* Other link speeds are not supported by internal KR PHY. */ | |
890 | return IXGBE_ERR_LINK_SETUP; | |
891 | } | |
892 | ||
893 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
894 | IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), | |
895 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
896 | if (status) | |
897 | return status; | |
898 | ||
899 | /* Disable training protocol FSM. */ | |
900 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
901 | IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), | |
902 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
903 | if (status) | |
904 | return status; | |
905 | ||
906 | reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; | |
907 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
908 | IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), | |
909 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
910 | if (status) | |
911 | return status; | |
912 | ||
913 | /* Disable Flex from training TXFFE. */ | |
914 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
915 | IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), | |
916 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
917 | if (status) | |
918 | return status; | |
919 | ||
920 | reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; | |
921 | reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; | |
922 | reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; | |
923 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
924 | IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), | |
925 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
926 | if (status) | |
927 | return status; | |
928 | ||
929 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
930 | IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), | |
931 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
932 | if (status) | |
933 | return status; | |
934 | ||
935 | reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; | |
936 | reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; | |
937 | reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; | |
938 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
939 | IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), | |
940 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
941 | if (status) | |
942 | return status; | |
943 | ||
944 | /* Enable override for coefficients. */ | |
945 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
946 | IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), | |
947 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
948 | if (status) | |
949 | return status; | |
950 | ||
951 | reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; | |
952 | reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; | |
953 | reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; | |
954 | reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; | |
955 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
956 | IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), | |
957 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
958 | if (status) | |
959 | return status; | |
960 | ||
961 | /* Toggle port SW reset by AN reset. */ | |
962 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
963 | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | |
964 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
965 | if (status) | |
966 | return status; | |
967 | ||
968 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; | |
969 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
970 | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | |
971 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
972 | ||
973 | return status; | |
974 | } | |
975 | ||
976 | /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY. | |
977 | * @hw: pointer to hardware structure | |
978 | * | |
979 | * Configures the integrated KX4 PHY. | |
980 | **/ | |
7ddbde3f | 981 | static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
982 | { |
983 | s32 status; | |
984 | u32 reg_val; | |
985 | ||
986 | status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, | |
987 | IXGBE_SB_IOSF_TARGET_KX4_PCS0 + | |
988 | hw->bus.lan_id, ®_val); | |
989 | if (status) | |
990 | return status; | |
991 | ||
992 | reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | | |
993 | IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); | |
994 | ||
995 | reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; | |
996 | ||
997 | /* Advertise 10G support. */ | |
998 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) | |
999 | reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; | |
1000 | ||
1001 | /* Advertise 1G support. */ | |
1002 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | |
1003 | reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; | |
1004 | ||
1005 | /* Restart auto-negotiation. */ | |
1006 | reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; | |
1007 | status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, | |
1008 | IXGBE_SB_IOSF_TARGET_KX4_PCS0 + | |
1009 | hw->bus.lan_id, reg_val); | |
1010 | ||
1011 | return status; | |
1012 | } | |
1013 | ||
1014 | /** ixgbe_setup_kr_x550em - Configure the KR PHY. | |
1015 | * @hw: pointer to hardware structure | |
1016 | * | |
1017 | * Configures the integrated KR PHY. | |
1018 | **/ | |
7ddbde3f | 1019 | static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
1020 | { |
1021 | s32 status; | |
1022 | u32 reg_val; | |
1023 | ||
1024 | status = ixgbe_read_iosf_sb_reg_x550(hw, | |
1025 | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | |
1026 | IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); | |
1027 | if (status) | |
1028 | return status; | |
1029 | ||
1030 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; | |
1031 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ; | |
1032 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; | |
1033 | reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | | |
1034 | IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); | |
1035 | ||
1036 | /* Advertise 10G support. */ | |
1037 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) | |
1038 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; | |
1039 | ||
1040 | /* Advertise 1G support. */ | |
1041 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | |
1042 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; | |
1043 | ||
1044 | /* Restart auto-negotiation. */ | |
1045 | reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; | |
1046 | status = ixgbe_write_iosf_sb_reg_x550(hw, | |
1047 | IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), | |
1048 | IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); | |
1049 | ||
1050 | return status; | |
1051 | } | |
1052 | ||
1053 | /** ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY | |
1054 | * @hw: point to hardware structure | |
1055 | * | |
1056 | * Configures the integrated KR PHY to talk to the external PHY. The base | |
1057 | * driver will call this function when it gets notification via interrupt from | |
1058 | * the external PHY. This function forces the internal PHY into iXFI mode at | |
1059 | * the correct speed. | |
1060 | * | |
1061 | * A return of a non-zero value indicates an error, and the base driver should | |
1062 | * not report link up. | |
1063 | **/ | |
7ddbde3f | 1064 | static s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw) |
6a14ee0c | 1065 | { |
a1e869de | 1066 | s32 status; |
6a14ee0c DS |
1067 | u16 lasi, autoneg_status, speed; |
1068 | ixgbe_link_speed force_speed; | |
1069 | ||
1070 | /* Verify that the external link status has changed */ | |
1071 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS, | |
1072 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, &lasi); | |
1073 | if (status) | |
1074 | return status; | |
1075 | ||
1076 | /* If there was no change in link status, we can just exit */ | |
1077 | if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM)) | |
1078 | return 0; | |
1079 | ||
1080 | /* we read this twice back to back to indicate current status */ | |
1081 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, | |
1082 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, | |
1083 | &autoneg_status); | |
1084 | if (status) | |
1085 | return status; | |
1086 | ||
1087 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, | |
1088 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, | |
1089 | &autoneg_status); | |
1090 | if (status) | |
1091 | return status; | |
1092 | ||
1093 | /* If link is not up return an error indicating treat link as down */ | |
1094 | if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) | |
1095 | return IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1096 | ||
1097 | status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, | |
1098 | IXGBE_MDIO_AUTO_NEG_DEV_TYPE, | |
1099 | &speed); | |
1100 | ||
1101 | /* clear everything but the speed and duplex bits */ | |
1102 | speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; | |
1103 | ||
1104 | switch (speed) { | |
1105 | case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: | |
1106 | force_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
1107 | break; | |
1108 | case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: | |
1109 | force_speed = IXGBE_LINK_SPEED_1GB_FULL; | |
1110 | break; | |
1111 | default: | |
1112 | /* Internal PHY does not support anything else */ | |
1113 | return IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1114 | } | |
1115 | ||
1116 | return ixgbe_setup_ixfi_x550em(hw, &force_speed); | |
1117 | } | |
1118 | ||
1119 | /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init | |
1120 | * @hw: pointer to hardware structure | |
1121 | * | |
1122 | * Initialize any function pointers that were not able to be | |
1123 | * set during init_shared_code because the PHY/SFP type was | |
1124 | * not known. Perform the SFP init if necessary. | |
1125 | **/ | |
7ddbde3f | 1126 | static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
1127 | { |
1128 | struct ixgbe_phy_info *phy = &hw->phy; | |
1129 | s32 ret_val; | |
1130 | u32 esdp; | |
1131 | ||
1132 | if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) { | |
1133 | esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
1134 | phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | |
1135 | ||
1136 | if (hw->bus.lan_id) { | |
1137 | esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); | |
1138 | esdp |= IXGBE_ESDP_SDP1_DIR; | |
1139 | } | |
1140 | esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); | |
1141 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); | |
1142 | } | |
1143 | ||
1144 | /* Identify the PHY or SFP module */ | |
1145 | ret_val = phy->ops.identify(hw); | |
1146 | ||
1147 | /* Setup function pointers based on detected SFP module and speeds */ | |
1148 | ixgbe_init_mac_link_ops_X550em(hw); | |
1149 | if (phy->sfp_type != ixgbe_sfp_type_unknown) | |
1150 | phy->ops.reset = NULL; | |
1151 | ||
1152 | /* Set functions pointers based on phy type */ | |
1153 | switch (hw->phy.type) { | |
1154 | case ixgbe_phy_x550em_kx4: | |
1155 | phy->ops.setup_link = ixgbe_setup_kx4_x550em; | |
1156 | phy->ops.read_reg = ixgbe_read_phy_reg_x550em; | |
1157 | phy->ops.write_reg = ixgbe_write_phy_reg_x550em; | |
1158 | break; | |
1159 | case ixgbe_phy_x550em_kr: | |
1160 | phy->ops.setup_link = ixgbe_setup_kr_x550em; | |
1161 | phy->ops.read_reg = ixgbe_read_phy_reg_x550em; | |
1162 | phy->ops.write_reg = ixgbe_write_phy_reg_x550em; | |
1163 | break; | |
1164 | case ixgbe_phy_x550em_ext_t: | |
1165 | phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em; | |
1166 | break; | |
1167 | default: | |
1168 | break; | |
1169 | } | |
1170 | return ret_val; | |
1171 | } | |
1172 | ||
1173 | /** ixgbe_get_media_type_X550em - Get media type | |
1174 | * @hw: pointer to hardware structure | |
1175 | * | |
1176 | * Returns the media type (fiber, copper, backplane) | |
1177 | * | |
1178 | */ | |
7ddbde3f | 1179 | static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
1180 | { |
1181 | enum ixgbe_media_type media_type; | |
1182 | ||
1183 | /* Detect if there is a copper PHY attached. */ | |
1184 | switch (hw->device_id) { | |
1185 | case IXGBE_DEV_ID_X550EM_X_KR: | |
1186 | case IXGBE_DEV_ID_X550EM_X_KX4: | |
1187 | media_type = ixgbe_media_type_backplane; | |
1188 | break; | |
1189 | case IXGBE_DEV_ID_X550EM_X_SFP: | |
1190 | media_type = ixgbe_media_type_fiber; | |
1191 | break; | |
1192 | case IXGBE_DEV_ID_X550EM_X_1G_T: | |
1193 | case IXGBE_DEV_ID_X550EM_X_10G_T: | |
1194 | media_type = ixgbe_media_type_copper; | |
1195 | break; | |
1196 | default: | |
1197 | media_type = ixgbe_media_type_unknown; | |
1198 | break; | |
1199 | } | |
1200 | return media_type; | |
1201 | } | |
1202 | ||
1203 | /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. | |
1204 | ** @hw: pointer to hardware structure | |
1205 | **/ | |
7ddbde3f | 1206 | static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) |
6a14ee0c | 1207 | { |
a1e869de | 1208 | s32 status; |
6a14ee0c DS |
1209 | u16 reg; |
1210 | u32 retries = 2; | |
1211 | ||
1212 | do { | |
1213 | /* decrement retries counter and exit if we hit 0 */ | |
1214 | if (retries < 1) { | |
1215 | hw_dbg(hw, "External PHY not yet finished resetting."); | |
1216 | return IXGBE_ERR_PHY; | |
1217 | } | |
1218 | retries--; | |
1219 | ||
1220 | status = hw->phy.ops.read_reg(hw, | |
1221 | IXGBE_MDIO_TX_VENDOR_ALARMS_3, | |
1222 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, | |
1223 | ®); | |
1224 | if (status) | |
1225 | return status; | |
1226 | ||
1227 | /* Verify PHY FW reset has completed */ | |
1228 | } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1); | |
1229 | ||
1230 | /* Set port to low power mode */ | |
1231 | status = hw->phy.ops.read_reg(hw, | |
1232 | IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, | |
1233 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, | |
1234 | ®); | |
1235 | if (status) | |
1236 | return status; | |
1237 | ||
1238 | /* Enable the transmitter */ | |
1239 | status = hw->phy.ops.read_reg(hw, | |
1240 | IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR, | |
1241 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, | |
1242 | ®); | |
1243 | if (status) | |
1244 | return status; | |
1245 | ||
1246 | reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE; | |
1247 | ||
1248 | status = hw->phy.ops.write_reg(hw, | |
1249 | IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR, | |
1250 | IXGBE_MDIO_PMA_PMD_DEV_TYPE, | |
1251 | reg); | |
1252 | if (status) | |
1253 | return status; | |
1254 | ||
1255 | /* Un-stall the PHY FW */ | |
1256 | status = hw->phy.ops.read_reg(hw, | |
1257 | IXGBE_MDIO_GLOBAL_RES_PR_10, | |
1258 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, | |
1259 | ®); | |
1260 | if (status) | |
1261 | return status; | |
1262 | ||
1263 | reg &= ~IXGBE_MDIO_POWER_UP_STALL; | |
1264 | ||
1265 | status = hw->phy.ops.write_reg(hw, | |
1266 | IXGBE_MDIO_GLOBAL_RES_PR_10, | |
1267 | IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, | |
1268 | reg); | |
1269 | return status; | |
1270 | } | |
1271 | ||
1272 | /** ixgbe_reset_hw_X550em - Perform hardware reset | |
1273 | ** @hw: pointer to hardware structure | |
1274 | ** | |
1275 | ** Resets the hardware by resetting the transmit and receive units, masks | |
1276 | ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) | |
1277 | ** reset. | |
1278 | **/ | |
7ddbde3f | 1279 | static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) |
6a14ee0c DS |
1280 | { |
1281 | ixgbe_link_speed link_speed; | |
1282 | s32 status; | |
1283 | u32 ctrl = 0; | |
1284 | u32 i; | |
1285 | bool link_up = false; | |
1286 | ||
1287 | /* Call adapter stop to disable Tx/Rx and clear interrupts */ | |
1288 | status = hw->mac.ops.stop_adapter(hw); | |
1289 | if (status) | |
1290 | return status; | |
1291 | ||
1292 | /* flush pending Tx transactions */ | |
1293 | ixgbe_clear_tx_pending(hw); | |
1294 | ||
1295 | /* PHY ops must be identified and initialized prior to reset */ | |
1296 | ||
1297 | /* Identify PHY and related function pointers */ | |
1298 | status = hw->phy.ops.init(hw); | |
1299 | ||
1300 | /* start the external PHY */ | |
1301 | if (hw->phy.type == ixgbe_phy_x550em_ext_t) { | |
1302 | status = ixgbe_init_ext_t_x550em(hw); | |
1303 | if (status) | |
1304 | return status; | |
1305 | } | |
1306 | ||
1307 | /* Setup SFP module if there is one present. */ | |
1308 | if (hw->phy.sfp_setup_needed) { | |
1309 | status = hw->mac.ops.setup_sfp(hw); | |
1310 | hw->phy.sfp_setup_needed = false; | |
1311 | } | |
1312 | ||
1313 | /* Reset PHY */ | |
1314 | if (!hw->phy.reset_disable && hw->phy.ops.reset) | |
1315 | hw->phy.ops.reset(hw); | |
1316 | ||
1317 | mac_reset_top: | |
1318 | /* Issue global reset to the MAC. Needs to be SW reset if link is up. | |
1319 | * If link reset is used when link is up, it might reset the PHY when | |
1320 | * mng is using it. If link is down or the flag to force full link | |
1321 | * reset is set, then perform link reset. | |
1322 | */ | |
1323 | ctrl = IXGBE_CTRL_LNK_RST; | |
1324 | ||
1325 | if (!hw->force_full_reset) { | |
1326 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
1327 | if (link_up) | |
1328 | ctrl = IXGBE_CTRL_RST; | |
1329 | } | |
1330 | ||
1331 | ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); | |
1332 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
1333 | IXGBE_WRITE_FLUSH(hw); | |
1334 | ||
1335 | /* Poll for reset bit to self-clear meaning reset is complete */ | |
1336 | for (i = 0; i < 10; i++) { | |
1337 | udelay(1); | |
1338 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
1339 | if (!(ctrl & IXGBE_CTRL_RST_MASK)) | |
1340 | break; | |
1341 | } | |
1342 | ||
1343 | if (ctrl & IXGBE_CTRL_RST_MASK) { | |
1344 | status = IXGBE_ERR_RESET_FAILED; | |
1345 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
1346 | } | |
1347 | ||
1348 | msleep(50); | |
1349 | ||
1350 | /* Double resets are required for recovery from certain error | |
1351 | * clear the multicast table. Also reset num_rar_entries to 128, | |
1352 | * since we modify this value when programming the SAN MAC address. | |
1353 | */ | |
1354 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
1355 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
1356 | goto mac_reset_top; | |
1357 | } | |
1358 | ||
1359 | /* Store the permanent mac address */ | |
1360 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
1361 | ||
1362 | /* Store MAC address from RAR0, clear receive address registers, and | |
1363 | * clear the multicast table. Also reset num_rar_entries to 128, | |
1364 | * since we modify this value when programming the SAN MAC address. | |
1365 | */ | |
1366 | hw->mac.num_rar_entries = 128; | |
1367 | hw->mac.ops.init_rx_addrs(hw); | |
1368 | ||
1369 | return status; | |
1370 | } | |
1371 | ||
5b7f000f DS |
1372 | /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype |
1373 | * anti-spoofing | |
1374 | * @hw: pointer to hardware structure | |
1375 | * @enable: enable or disable switch for Ethertype anti-spoofing | |
1376 | * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing | |
1377 | **/ | |
bc035fc5 DS |
1378 | static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, |
1379 | bool enable, int vf) | |
5b7f000f DS |
1380 | { |
1381 | int vf_target_reg = vf >> 3; | |
1382 | int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; | |
1383 | u32 pfvfspoof; | |
1384 | ||
1385 | pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); | |
1386 | if (enable) | |
1387 | pfvfspoof |= (1 << vf_target_shift); | |
1388 | else | |
1389 | pfvfspoof &= ~(1 << vf_target_shift); | |
1390 | ||
1391 | IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); | |
1392 | } | |
1393 | ||
6d4c96ad DS |
1394 | /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning |
1395 | * @hw: pointer to hardware structure | |
1396 | * @enable: enable or disable source address pruning | |
1397 | * @pool: Rx pool to set source address pruning for | |
1398 | **/ | |
1399 | static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, | |
1400 | bool enable, | |
1401 | unsigned int pool) | |
1402 | { | |
1403 | u64 pfflp; | |
1404 | ||
1405 | /* max rx pool is 63 */ | |
1406 | if (pool > 63) | |
1407 | return; | |
1408 | ||
1409 | pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); | |
1410 | pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; | |
1411 | ||
1412 | if (enable) | |
1413 | pfflp |= (1ULL << pool); | |
1414 | else | |
1415 | pfflp &= ~(1ULL << pool); | |
1416 | ||
1417 | IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); | |
1418 | IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); | |
1419 | } | |
1420 | ||
6a14ee0c DS |
1421 | #define X550_COMMON_MAC \ |
1422 | .init_hw = &ixgbe_init_hw_generic, \ | |
1423 | .start_hw = &ixgbe_start_hw_X540, \ | |
1424 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ | |
1425 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ | |
1426 | .get_mac_addr = &ixgbe_get_mac_addr_generic, \ | |
1427 | .get_device_caps = &ixgbe_get_device_caps_generic, \ | |
1428 | .stop_adapter = &ixgbe_stop_adapter_generic, \ | |
1429 | .get_bus_info = &ixgbe_get_bus_info_generic, \ | |
1430 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ | |
1431 | .read_analog_reg8 = NULL, \ | |
1432 | .write_analog_reg8 = NULL, \ | |
1433 | .set_rxpba = &ixgbe_set_rxpba_generic, \ | |
1434 | .check_link = &ixgbe_check_mac_link_generic, \ | |
1435 | .led_on = &ixgbe_led_on_generic, \ | |
1436 | .led_off = &ixgbe_led_off_generic, \ | |
1437 | .blink_led_start = &ixgbe_blink_led_start_X540, \ | |
1438 | .blink_led_stop = &ixgbe_blink_led_stop_X540, \ | |
1439 | .set_rar = &ixgbe_set_rar_generic, \ | |
1440 | .clear_rar = &ixgbe_clear_rar_generic, \ | |
1441 | .set_vmdq = &ixgbe_set_vmdq_generic, \ | |
1442 | .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ | |
1443 | .clear_vmdq = &ixgbe_clear_vmdq_generic, \ | |
1444 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ | |
1445 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ | |
1446 | .enable_mc = &ixgbe_enable_mc_generic, \ | |
1447 | .disable_mc = &ixgbe_disable_mc_generic, \ | |
1448 | .clear_vfta = &ixgbe_clear_vfta_generic, \ | |
1449 | .set_vfta = &ixgbe_set_vfta_generic, \ | |
1450 | .fc_enable = &ixgbe_fc_enable_generic, \ | |
1451 | .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \ | |
1452 | .init_uta_tables = &ixgbe_init_uta_tables_generic, \ | |
1453 | .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ | |
1454 | .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ | |
6d4c96ad DS |
1455 | .set_source_address_pruning = \ |
1456 | &ixgbe_set_source_address_pruning_X550, \ | |
5b7f000f DS |
1457 | .set_ethertype_anti_spoofing = \ |
1458 | &ixgbe_set_ethertype_anti_spoofing_X550, \ | |
6a14ee0c DS |
1459 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, \ |
1460 | .release_swfw_sync = &ixgbe_release_swfw_sync_X540, \ | |
1461 | .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ | |
1462 | .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ | |
1463 | .get_thermal_sensor_data = NULL, \ | |
1464 | .init_thermal_sensor_thresh = NULL, \ | |
1465 | .prot_autoc_read = &prot_autoc_read_generic, \ | |
1466 | .prot_autoc_write = &prot_autoc_write_generic, \ | |
1f9ac57c DS |
1467 | .enable_rx = &ixgbe_enable_rx_generic, \ |
1468 | .disable_rx = &ixgbe_disable_rx_x550, \ | |
6a14ee0c DS |
1469 | |
1470 | static struct ixgbe_mac_operations mac_ops_X550 = { | |
1471 | X550_COMMON_MAC | |
1472 | .reset_hw = &ixgbe_reset_hw_X540, | |
1473 | .get_media_type = &ixgbe_get_media_type_X540, | |
1474 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, | |
1475 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, | |
1476 | .setup_link = &ixgbe_setup_mac_link_X540, | |
6a14ee0c DS |
1477 | .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, |
1478 | .setup_sfp = NULL, | |
1479 | }; | |
1480 | ||
1481 | static struct ixgbe_mac_operations mac_ops_X550EM_x = { | |
1482 | X550_COMMON_MAC | |
1483 | .reset_hw = &ixgbe_reset_hw_X550em, | |
1484 | .get_media_type = &ixgbe_get_media_type_X550em, | |
1485 | .get_san_mac_addr = NULL, | |
1486 | .get_wwn_prefix = NULL, | |
1487 | .setup_link = NULL, /* defined later */ | |
1488 | .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, | |
1489 | .setup_sfp = ixgbe_setup_sfp_modules_X550em, | |
1490 | ||
1491 | }; | |
1492 | ||
1493 | #define X550_COMMON_EEP \ | |
1494 | .read = &ixgbe_read_ee_hostif_X550, \ | |
1495 | .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ | |
1496 | .write = &ixgbe_write_ee_hostif_X550, \ | |
1497 | .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ | |
1498 | .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ | |
1499 | .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ | |
1500 | .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ | |
1501 | ||
1502 | static struct ixgbe_eeprom_operations eeprom_ops_X550 = { | |
1503 | X550_COMMON_EEP | |
1504 | .init_params = &ixgbe_init_eeprom_params_X550, | |
1505 | }; | |
1506 | ||
1507 | static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { | |
1508 | X550_COMMON_EEP | |
1509 | .init_params = &ixgbe_init_eeprom_params_X540, | |
1510 | }; | |
1511 | ||
1512 | #define X550_COMMON_PHY \ | |
1513 | .identify_sfp = &ixgbe_identify_module_generic, \ | |
1514 | .reset = NULL, \ | |
1515 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ | |
1516 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ | |
1517 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ | |
1518 | .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ | |
1519 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ | |
1520 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ | |
1521 | .check_overtemp = &ixgbe_tn_check_overtemp, \ | |
1522 | .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, | |
1523 | ||
1524 | static struct ixgbe_phy_operations phy_ops_X550 = { | |
1525 | X550_COMMON_PHY | |
1526 | .init = NULL, | |
1527 | .identify = &ixgbe_identify_phy_generic, | |
1528 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1529 | .write_reg = &ixgbe_write_phy_reg_generic, | |
1530 | .setup_link = &ixgbe_setup_phy_link_generic, | |
1531 | .read_i2c_combined = &ixgbe_read_i2c_combined_generic, | |
1532 | .write_i2c_combined = &ixgbe_write_i2c_combined_generic, | |
1533 | }; | |
1534 | ||
1535 | static struct ixgbe_phy_operations phy_ops_X550EM_x = { | |
1536 | X550_COMMON_PHY | |
1537 | .init = &ixgbe_init_phy_ops_X550em, | |
1538 | .identify = &ixgbe_identify_phy_x550em, | |
1539 | .read_reg = NULL, /* defined later */ | |
1540 | .write_reg = NULL, /* defined later */ | |
1541 | .setup_link = NULL, /* defined later */ | |
1542 | }; | |
1543 | ||
1544 | struct ixgbe_info ixgbe_X550_info = { | |
1545 | .mac = ixgbe_mac_X550, | |
1546 | .get_invariants = &ixgbe_get_invariants_X540, | |
1547 | .mac_ops = &mac_ops_X550, | |
1548 | .eeprom_ops = &eeprom_ops_X550, | |
1549 | .phy_ops = &phy_ops_X550, | |
1550 | .mbx_ops = &mbx_ops_generic, | |
1551 | }; | |
1552 | ||
1553 | struct ixgbe_info ixgbe_X550EM_x_info = { | |
1554 | .mac = ixgbe_mac_X550EM_x, | |
1555 | .get_invariants = &ixgbe_get_invariants_X540, | |
1556 | .mac_ops = &mac_ops_X550EM_x, | |
1557 | .eeprom_ops = &eeprom_ops_X550EM_x, | |
1558 | .phy_ops = &phy_ops_X550EM_x, | |
1559 | .mbx_ops = &mbx_ops_generic, | |
1560 | }; |