[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbevf / ixgbevf.h

/*******************************************************************************

  Intel 82599 Virtual Function driver
  Copyright(c) 1999 - 2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBEVF_H_
#define _IXGBEVF_H_

#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#include <linux/u64_stats_sync.h>

#include "vf.h"

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbevf_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
	u16 mapped_as_page;
};

struct ixgbevf_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
};

struct ixgbevf_ring {
	struct ixgbevf_ring *next;
	struct net_device *netdev;
	struct device *dev;
	struct ixgbevf_adapter *adapter;  /* backlink */
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbevf_tx_buffer *tx_buffer_info;
		struct ixgbevf_rx_buffer *rx_buffer_info;
	};

	u64			total_bytes;
	u64			total_packets;
	struct u64_stats_sync	syncp;

	u16 head;
	u16 tail;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCB and RSS modes */

	u16 rx_buf_len;
};

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBEVF_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES

#define IXGBEVF_DEFAULT_TXD   1024
#define IXGBEVF_DEFAULT_RXD   512
#define IXGBEVF_MAX_TXD       4096
#define IXGBEVF_MIN_TXD       64
#define IXGBEVF_MAX_RXD       4096
#define IXGBEVF_MIN_RXD       64

/* Supported Rx Buffer Sizes */
#define IXGBEVF_RXBUFFER_256   256    /* Used for packet split */
#define IXGBEVF_RXBUFFER_3K    3072
#define IXGBEVF_RXBUFFER_7K    7168
#define IXGBEVF_RXBUFFER_15K   15360
#define IXGBEVF_MAX_RXBUFFER   16384  /* largest size for single descriptor */

#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_FCOE		(u32)(1 << 4)
#define IXGBE_TX_FLAGS_FSO		(u32)(1 << 5)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK	0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

struct ixgbevf_ring_container {
	struct ixgbevf_ring *ring;	/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u8 count;			/* total number of rings in vector */
	u8 itr;				/* current ITR setting for ring */
};

/* iterator for handling rings in ring container */
#define ixgbevf_for_each_ring(pos, head) \
	for (pos = (head).ring; pos != NULL; pos = pos->next)

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbevf_q_vector {
	struct ixgbevf_adapter *adapter;
	u16 v_idx;		/* index of q_vector within array, also used for
				 * finding the bit in EICR and friends that
				 * represents the vector for this ring */
	u16 itr;		/* Interrupt throttle rate written to EITR */
	struct napi_struct napi;
	struct ixgbevf_ring_container rx, tx;
	char name[IFNAMSIZ + 9];
};

/*
 * microsecond values for various ITR rates shifted by 2 to fit itr register
 * with the first 3 bits reserved 0
 */
#define IXGBE_MIN_RSC_ITR	24
#define IXGBE_100K_ITR		40
#define IXGBE_20K_ITR		200
#define IXGBE_10K_ITR		400
#define IXGBE_8K_ITR		500

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.  The lowest value
 * supported by all of the ixgbe hardware is 8.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBEVF_RX_DESC(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
#define IXGBEVF_TX_DESC(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
#define IXGBEVF_TX_CTXTDESC(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE	9728 /* Maximum Supported Size 9.5KB */

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_Q_VECTORS 2

#define MIN_MSIX_Q_VECTORS 1
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbevf_adapter {
	struct timer_list watchdog_timer;
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];

	/* Interrupt Throttle Rate */
	u16 rx_itr_setting;
	u16 tx_itr_setting;

	/* interrupt masks */
	u32 eims_enable_mask;
	u32 eims_other;

	/* TX */
	struct ixgbevf_ring *tx_ring;	/* One per active queue */
	int num_tx_queues;
	u64 restart_queue;
	u64 hw_csum_tx_good;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;

	/* RX */
	struct ixgbevf_ring *rx_ring;	/* One per active queue */
	int num_rx_queues;
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_msix_vectors;
	struct msix_entry *msix_entries;

	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;

	/* structs defined in ixgbe_vf.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbevf_hw_stats stats;
	u64 zero_base;
	/* Interrupt Throttle Rate */
	u32 eitr_param;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;

	struct work_struct watchdog_task;

	spinlock_t mbx_lock;
};

enum ixbgevf_state_t {
	__IXGBEVF_TESTING,
	__IXGBEVF_RESETTING,
	__IXGBEVF_DOWN
};

struct ixgbevf_cb {
	struct sk_buff *prev;
};
#define IXGBE_CB(skb) ((struct ixgbevf_cb *)(skb)->cb)

enum ixgbevf_boards {
	board_82599_vf,
	board_X540_vf,
};

extern const struct ixgbevf_info ixgbevf_82599_vf_info;
extern const struct ixgbevf_info ixgbevf_X540_vf_info;
extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;

/* needed by ethtool.c */
extern const char ixgbevf_driver_name[];
extern const char ixgbevf_driver_version[];

extern void ixgbevf_up(struct ixgbevf_adapter *adapter);
extern void ixgbevf_down(struct ixgbevf_adapter *adapter);
extern void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
extern void ixgbevf_reset(struct ixgbevf_adapter *adapter);
extern void ixgbevf_set_ethtool_ops(struct net_device *netdev);
extern int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *,
				      struct ixgbevf_ring *);
extern int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *,
				      struct ixgbevf_ring *);
extern void ixgbevf_free_rx_resources(struct ixgbevf_adapter *,
				      struct ixgbevf_ring *);
extern void ixgbevf_free_tx_resources(struct ixgbevf_adapter *,
				      struct ixgbevf_ring *);
extern void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
extern int ethtool_ioctl(struct ifreq *ifr);

extern void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
extern void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);

#ifdef DEBUG
extern char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
#define hw_dbg(hw, format, arg...) \
	printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
#else
#define hw_dbg(hw, format, arg...) do {} while (0)
#endif

#endif /* _IXGBEVF_H_ */
Commit	Line	Data
92915f71 GR	1	/*******************************************************************************
	2
	3	Intel 82599 Virtual Function driver
5c47a2b6	4	Copyright(c) 1999 - 2012 Intel Corporation.
92915f71 GR	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBEVF_H_
	29	#define _IXGBEVF_H_
	30
	31	#include <linux/types.h>
dadcd65f	32	#include <linux/bitops.h>
92915f71 GR	33	#include <linux/timer.h>
	34	#include <linux/io.h>
	35	#include <linux/netdevice.h>
dadcd65f	36	#include <linux/if_vlan.h>
4197aa7b	37	#include <linux/u64_stats_sync.h>
92915f71 GR	38
	39	#include "vf.h"
	40
	41	/* wrapper around a pointer to a socket buffer,
	42	* so a DMA handle can be stored along with the buffer */
	43	struct ixgbevf_tx_buffer {
	44	struct sk_buff *skb;
	45	dma_addr_t dma;
	46	unsigned long time_stamp;
	47	u16 length;
	48	u16 next_to_watch;
	49	u16 mapped_as_page;
	50	};
	51
	52	struct ixgbevf_rx_buffer {
	53	struct sk_buff *skb;
	54	dma_addr_t dma;
92915f71 GR	55	};
	56
	57	struct ixgbevf_ring {
6b43c446	58	struct ixgbevf_ring *next;
fb40195c AD	59	struct net_device *netdev;
fb40195c AD	60	struct device *dev;
92915f71 GR	61	struct ixgbevf_adapter adapter; / backlink */
	62	void desc; / descriptor ring memory */
	63	dma_addr_t dma; /* phys. address of descriptor ring */
	64	unsigned int size; /* length in bytes */
	65	unsigned int count; /* amount of descriptors */
	66	unsigned int next_to_use;
	67	unsigned int next_to_clean;
	68
	69	int queue_index; /* needed for multiqueue queue management */
	70	union {
	71	struct ixgbevf_tx_buffer *tx_buffer_info;
	72	struct ixgbevf_rx_buffer *rx_buffer_info;
	73	};
	74
4197aa7b ED	75	u64 total_bytes;
	76	u64 total_packets;
	77	struct u64_stats_sync syncp;
	78
92915f71 GR	79	u16 head;
	80	u16 tail;
	81
92915f71 GR	82	u16 reg_idx; /* holds the special value that gets the hardware register
	83	* offset associated with this ring, which is different
	84	* for DCB and RSS modes */
	85
92915f71 GR	86	u16 rx_buf_len;
	87	};
	88
92915f71 GR	89	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	90	#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	91
56e94095 AD	92	#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
56e94095 AD	93	#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
92915f71 GR	94
	95	#define IXGBEVF_DEFAULT_TXD 1024
	96	#define IXGBEVF_DEFAULT_RXD 512
	97	#define IXGBEVF_MAX_TXD 4096
	98	#define IXGBEVF_MIN_TXD 64
	99	#define IXGBEVF_MAX_RXD 4096
	100	#define IXGBEVF_MIN_RXD 64
	101
	102	/* Supported Rx Buffer Sizes */
92915f71	103	#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
dd1fe113 AD	104	#define IXGBEVF_RXBUFFER_3K 3072
	105	#define IXGBEVF_RXBUFFER_7K 7168
	106	#define IXGBEVF_RXBUFFER_15K 15360
92915f71 GR	107	#define IXGBEVF_MAX_RXBUFFER 16384 /* largest size for single descriptor */
	108
	109	#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
	110
	111	#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
	112
	113	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	114	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	115	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	116	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
	117	#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
	118	#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
	119	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
	120	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
	121	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	122
6b43c446 AD	123	struct ixgbevf_ring_container {
6b43c446 AD	124	struct ixgbevf_ring ring; / pointer to linked list of rings */
5f3600eb AD	125	unsigned int total_bytes; /* total bytes processed this int */
5f3600eb AD	126	unsigned int total_packets; /* total packets processed this int */
6b43c446 AD	127	u8 count; /* total number of rings in vector */
	128	u8 itr; /* current ITR setting for ring */
	129	};
	130
	131	/* iterator for handling rings in ring container */
	132	#define ixgbevf_for_each_ring(pos, head) \
	133	for (pos = (head).ring; pos != NULL; pos = pos->next)
	134
92915f71 GR	135	/* MAX_MSIX_Q_VECTORS of these are allocated,
	136	* but we only use one per queue-specific vector.
	137	*/
	138	struct ixgbevf_q_vector {
	139	struct ixgbevf_adapter *adapter;
5f3600eb AD	140	u16 v_idx; /* index of q_vector within array, also used for
	141	* finding the bit in EICR and friends that
	142	* represents the vector for this ring */
	143	u16 itr; /* Interrupt throttle rate written to EITR */
92915f71	144	struct napi_struct napi;
6b43c446	145	struct ixgbevf_ring_container rx, tx;
fa71ae27	146	char name[IFNAMSIZ + 9];
92915f71 GR	147	};
92915f71 GR	148
5f3600eb AD	149	/*
	150	* microsecond values for various ITR rates shifted by 2 to fit itr register
	151	* with the first 3 bits reserved 0
	152	*/
	153	#define IXGBE_MIN_RSC_ITR 24
	154	#define IXGBE_100K_ITR 40
	155	#define IXGBE_20K_ITR 200
	156	#define IXGBE_10K_ITR 400
	157	#define IXGBE_8K_ITR 500
	158
92915f71 GR	159	/* Helper macros to switch between ints/sec and what the register uses.
	160	* And yes, it's the same math going both ways. The lowest value
	161	* supported by all of the ixgbe hardware is 8.
	162	*/
	163	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	164	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
	165	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	166
	167	#define IXGBE_DESC_UNUSED(R) \
	168	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	169	(R)->next_to_clean - (R)->next_to_use - 1)
	170
908421f6 AD	171	#define IXGBEVF_RX_DESC(R, i) \
	172	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
	173	#define IXGBEVF_TX_DESC(R, i) \
	174	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
	175	#define IXGBEVF_TX_CTXTDESC(R, i) \
	176	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
92915f71	177
c88887e0	178	#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
92915f71 GR	179
	180	#define OTHER_VECTOR 1
	181	#define NON_Q_VECTORS (OTHER_VECTOR)
	182
	183	#define MAX_MSIX_Q_VECTORS 2
92915f71	184
fa71ae27	185	#define MIN_MSIX_Q_VECTORS 1
92915f71 GR	186	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
	187
	188	/* board specific private data structure */
	189	struct ixgbevf_adapter {
	190	struct timer_list watchdog_timer;
dadcd65f	191	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
92915f71 GR	192	u16 bd_number;
	193	struct work_struct reset_task;
	194	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
92915f71 GR	195
92915f71 GR	196	/* Interrupt Throttle Rate */
5f3600eb AD	197	u16 rx_itr_setting;
	198	u16 tx_itr_setting;
	199
	200	/* interrupt masks */
	201	u32 eims_enable_mask;
	202	u32 eims_other;
92915f71 GR	203
	204	/* TX */
	205	struct ixgbevf_ring tx_ring; / One per active queue */
	206	int num_tx_queues;
	207	u64 restart_queue;
	208	u64 hw_csum_tx_good;
	209	u64 lsc_int;
	210	u64 hw_tso_ctxt;
	211	u64 hw_tso6_ctxt;
	212	u32 tx_timeout_count;
92915f71 GR	213
	214	/* RX */
	215	struct ixgbevf_ring rx_ring; / One per active queue */
	216	int num_rx_queues;
92915f71 GR	217	u64 hw_csum_rx_error;
	218	u64 hw_rx_no_dma_resources;
	219	u64 hw_csum_rx_good;
	220	u64 non_eop_descs;
	221	int num_msix_vectors;
92915f71 GR	222	struct msix_entry *msix_entries;
92915f71 GR	223
92915f71 GR	224	u32 alloc_rx_page_failed;
	225	u32 alloc_rx_buff_failed;
	226
	227	/* Some features need tri-state capability,
	228	* thus the additional *_CAPABLE flags.
	229	*/
	230	u32 flags;
525a940c	231	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1)
77d5dfca	232
92915f71 GR	233	/* OS defined structs */
	234	struct net_device *netdev;
	235	struct pci_dev *pdev;
92915f71 GR	236
	237	/* structs defined in ixgbe_vf.h */
	238	struct ixgbe_hw hw;
	239	u16 msg_enable;
	240	struct ixgbevf_hw_stats stats;
	241	u64 zero_base;
	242	/* Interrupt Throttle Rate */
	243	u32 eitr_param;
	244
	245	unsigned long state;
92915f71 GR	246	u64 tx_busy;
	247	unsigned int tx_ring_count;
	248	unsigned int rx_ring_count;
	249
	250	u32 link_speed;
	251	bool link_up;
92915f71 GR	252
92915f71 GR	253	struct work_struct watchdog_task;
1c55ed76 AD	254
1c55ed76 AD	255	spinlock_t mbx_lock;
92915f71 GR	256	};
	257
	258	enum ixbgevf_state_t {
	259	__IXGBEVF_TESTING,
	260	__IXGBEVF_RESETTING,
	261	__IXGBEVF_DOWN
	262	};
	263
5c60f81a AD	264	struct ixgbevf_cb {
	265	struct sk_buff *prev;
	266	};
	267	#define IXGBE_CB(skb) ((struct ixgbevf_cb *)(skb)->cb)
	268
92915f71 GR	269	enum ixgbevf_boards {
92915f71 GR	270	board_82599_vf,
2316aa2a	271	board_X540_vf,
92915f71 GR	272	};
92915f71 GR	273
3d8fe98f SH	274	extern const struct ixgbevf_info ixgbevf_82599_vf_info;
3d8fe98f SH	275	extern const struct ixgbevf_info ixgbevf_X540_vf_info;
b5417bf8	276	extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
92915f71 GR	277
92915f71 GR	278	/* needed by ethtool.c */
3d8fe98f	279	extern const char ixgbevf_driver_name[];
92915f71 GR	280	extern const char ixgbevf_driver_version[];
92915f71 GR	281
795180d8	282	extern void ixgbevf_up(struct ixgbevf_adapter *adapter);
92915f71 GR	283	extern void ixgbevf_down(struct ixgbevf_adapter *adapter);
	284	extern void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
	285	extern void ixgbevf_reset(struct ixgbevf_adapter *adapter);
	286	extern void ixgbevf_set_ethtool_ops(struct net_device *netdev);
	287	extern int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *,
	288	struct ixgbevf_ring *);
	289	extern int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *,
	290	struct ixgbevf_ring *);
	291	extern void ixgbevf_free_rx_resources(struct ixgbevf_adapter *,
	292	struct ixgbevf_ring *);
	293	extern void ixgbevf_free_tx_resources(struct ixgbevf_adapter *,
	294	struct ixgbevf_ring *);
	295	extern void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
92915f71 GR	296	extern int ethtool_ioctl(struct ifreq *ifr);
92915f71 GR	297
92915f71 GR	298	extern void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
	299	extern void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
	300
	301	#ifdef DEBUG
	302	extern char ixgbevf_get_hw_dev_name(struct ixgbe_hw hw);
	303	#define hw_dbg(hw, format, arg...) \
	304	printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
	305	#else
	306	#define hw_dbg(hw, format, arg...) do {} while (0)
	307	#endif
	308
	309	#endif /* _IXGBEVF_H_ */