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ixgbevf: have clean_rx_irq return total_rx_packets cleaned
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / intel / ixgbevf / ixgbevf_main.c
CommitLineData
92915f71
GR		 1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
5c47a2b6 4 Copyright(c) 1999 - 2012 Intel Corporation.
92915f71
GR		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/******************************************************************************
30 Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
31******************************************************************************/
dbd9636e
JK		 32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
92915f71 35#include <linux/types.h>
dadcd65f 36#include <linux/bitops.h>
92915f71
GR		 37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/vmalloc.h>
41#include <linux/string.h>
42#include <linux/in.h>
43#include <linux/ip.h>
44#include <linux/tcp.h>
70a10e25 45#include <linux/sctp.h>
92915f71 46#include <linux/ipv6.h>
5a0e3ad6 47#include <linux/slab.h>
92915f71
GR		 48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
01789349 51#include <linux/if.h>
92915f71 52#include <linux/if_vlan.h>
70c71606 53#include <linux/prefetch.h>
92915f71
GR		 54
55#include "ixgbevf.h"
56
3d8fe98f 57const char ixgbevf_driver_name[] = "ixgbevf";
92915f71 58static const char ixgbevf_driver_string[] =
422e05d1 59 "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver";
92915f71 60
9e6fcae7 61#define DRV_VERSION "2.11.3-k"
92915f71 62const char ixgbevf_driver_version[] = DRV_VERSION;
66c87bd5 63static char ixgbevf_copyright[] =
5c47a2b6 64 "Copyright (c) 2009 - 2012 Intel Corporation.";
92915f71
GR		 65
66static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
2316aa2a
GR		 67 [board_82599_vf] = &ixgbevf_82599_vf_info,
68 [board_X540_vf] = &ixgbevf_X540_vf_info,
92915f71
GR		 69};
70
71/* ixgbevf_pci_tbl - PCI Device ID Table
72 *
73 * Wildcard entries (PCI_ANY_ID) should come last
74 * Last entry must be all 0s
75 *
76 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
77 * Class, Class Mask, private data (not used) }
78 */
39ba22b4
SH		 79static DEFINE_PCI_DEVICE_TABLE(ixgbevf_pci_tbl) = {
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF), board_82599_vf },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF), board_X540_vf },
92915f71
GR		 82 /* required last entry */
83 {0, }
84};
85MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl);
86
87MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
88MODULE_DESCRIPTION("Intel(R) 82599 Virtual Function Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
b3f4d599 92#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
93static int debug = -1;
94module_param(debug, int, 0);
95MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92915f71
GR		 96
97/* forward decls */
fa71ae27 98static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector);
56e94095 99static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter);
92915f71
GR		 100
101static inline void ixgbevf_release_rx_desc(struct ixgbe_hw *hw,
102 struct ixgbevf_ring *rx_ring,
103 u32 val)
104{
105 /*
106 * Force memory writes to complete before letting h/w
107 * know there are new descriptors to fetch. (Only
108 * applicable for weak-ordered memory model archs,
109 * such as IA-64).
110 */
111 wmb();
112 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rx_ring->reg_idx), val);
113}
114
49ce9c2c 115/**
65d676c8 116 * ixgbevf_set_ivar - set IVAR registers - maps interrupt causes to vectors
92915f71
GR		 117 * @adapter: pointer to adapter struct
118 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
119 * @queue: queue to map the corresponding interrupt to
120 * @msix_vector: the vector to map to the corresponding queue
92915f71
GR		 121 */
122static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction,
123 u8 queue, u8 msix_vector)
124{
125 u32 ivar, index;
126 struct ixgbe_hw *hw = &adapter->hw;
127 if (direction == -1) {
128 /* other causes */
129 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
130 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
131 ivar &= ~0xFF;
132 ivar |= msix_vector;
133 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar);
134 } else {
135 /* tx or rx causes */
136 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
137 index = ((16 * (queue & 1)) + (8 * direction));
138 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
139 ivar &= ~(0xFF << index);
140 ivar |= (msix_vector << index);
141 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar);
142 }
143}
144
70a10e25 145static void ixgbevf_unmap_and_free_tx_resource(struct ixgbevf_ring *tx_ring,
92915f71
GR		 146 struct ixgbevf_tx_buffer
147 *tx_buffer_info)
148{
149 if (tx_buffer_info->dma) {
150 if (tx_buffer_info->mapped_as_page)
70a10e25 151 dma_unmap_page(tx_ring->dev,
92915f71
GR		 152 tx_buffer_info->dma,
153 tx_buffer_info->length,
2a1f8794 154 DMA_TO_DEVICE);
92915f71 155 else
70a10e25 156 dma_unmap_single(tx_ring->dev,
92915f71
GR		 157 tx_buffer_info->dma,
158 tx_buffer_info->length,
2a1f8794 159 DMA_TO_DEVICE);
92915f71
GR		 160 tx_buffer_info->dma = 0;
161 }
162 if (tx_buffer_info->skb) {
163 dev_kfree_skb_any(tx_buffer_info->skb);
164 tx_buffer_info->skb = NULL;
165 }
166 tx_buffer_info->time_stamp = 0;
167 /* tx_buffer_info must be completely set up in the transmit path */
168}
169
92915f71
GR		 170#define IXGBE_MAX_TXD_PWR 14
171#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
172
173/* Tx Descriptors needed, worst case */
3595990a
AD		 174#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
175#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
92915f71
GR		 176
177static void ixgbevf_tx_timeout(struct net_device *netdev);
178
179/**
180 * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes
fa71ae27 181 * @q_vector: board private structure
92915f71
GR		 182 * @tx_ring: tx ring to clean
183 **/
fa71ae27 184static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector,
92915f71
GR		 185 struct ixgbevf_ring *tx_ring)
186{
fa71ae27 187 struct ixgbevf_adapter *adapter = q_vector->adapter;
92915f71
GR		 188 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
189 struct ixgbevf_tx_buffer *tx_buffer_info;
e757e3e1 190 unsigned int i, count = 0;
92915f71
GR		 191 unsigned int total_bytes = 0, total_packets = 0;
192
10cc1bdd
AD		 193 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
194 return true;
195
92915f71 196 i = tx_ring->next_to_clean;
e757e3e1
AD		 197 tx_buffer_info = &tx_ring->tx_buffer_info[i];
198 eop_desc = tx_buffer_info->next_to_watch;
92915f71 199
e757e3e1 200 do {
92915f71 201 bool cleaned = false;
e757e3e1
AD		 202
203 /* if next_to_watch is not set then there is no work pending */
204 if (!eop_desc)
205 break;
206
207 /* prevent any other reads prior to eop_desc */
208 read_barrier_depends();
209
210 /* if DD is not set pending work has not been completed */
211 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
212 break;
213
214 /* clear next_to_watch to prevent false hangs */
215 tx_buffer_info->next_to_watch = NULL;
216
92915f71
GR		 217 for ( ; !cleaned; count++) {
218 struct sk_buff *skb;
908421f6 219 tx_desc = IXGBEVF_TX_DESC(tx_ring, i);
e757e3e1 220 cleaned = (tx_desc == eop_desc);
92915f71
GR		 221 skb = tx_buffer_info->skb;
222
223 if (cleaned && skb) {
224 unsigned int segs, bytecount;
225
226 /* gso_segs is currently only valid for tcp */
227 segs = skb_shinfo(skb)->gso_segs ?: 1;
228 /* multiply data chunks by size of headers */
229 bytecount = ((segs - 1) * skb_headlen(skb)) +
230 skb->len;
231 total_packets += segs;
232 total_bytes += bytecount;
233 }
234
70a10e25 235 ixgbevf_unmap_and_free_tx_resource(tx_ring,
92915f71
GR		 236 tx_buffer_info);
237
238 tx_desc->wb.status = 0;
239
240 i++;
241 if (i == tx_ring->count)
242 i = 0;
e757e3e1
AD		 243
244 tx_buffer_info = &tx_ring->tx_buffer_info[i];
92915f71
GR		 245 }
246
e757e3e1
AD		 247 eop_desc = tx_buffer_info->next_to_watch;
248 } while (count < tx_ring->count);
92915f71
GR		 249
250 tx_ring->next_to_clean = i;
251
252#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fb40195c 253 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
92915f71
GR		 254 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
255 /* Make sure that anybody stopping the queue after this
256 * sees the new next_to_clean.
257 */
258 smp_mb();
fb40195c
AD		 259 if (__netif_subqueue_stopped(tx_ring->netdev,
260 tx_ring->queue_index) &&
92915f71 261 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
fb40195c
AD		 262 netif_wake_subqueue(tx_ring->netdev,
263 tx_ring->queue_index);
92915f71
GR		 264 ++adapter->restart_queue;
265 }
92915f71
GR		 266 }
267
4197aa7b 268 u64_stats_update_begin(&tx_ring->syncp);
92915f71
GR		 269 tx_ring->total_bytes += total_bytes;
270 tx_ring->total_packets += total_packets;
4197aa7b 271 u64_stats_update_end(&tx_ring->syncp);
ac6ed8f0
GR		 272 q_vector->tx.total_bytes += total_bytes;
273 q_vector->tx.total_packets += total_packets;
92915f71 274
fa71ae27 275 return count < tx_ring->count;
92915f71
GR		 276}
277
278/**
279 * ixgbevf_receive_skb - Send a completed packet up the stack
280 * @q_vector: structure containing interrupt and ring information
281 * @skb: packet to send up
282 * @status: hardware indication of status of receive
92915f71
GR		 283 * @rx_desc: rx descriptor
284 **/
285static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
286 struct sk_buff *skb, u8 status,
92915f71
GR		 287 union ixgbe_adv_rx_desc *rx_desc)
288{
289 struct ixgbevf_adapter *adapter = q_vector->adapter;
290 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
dd1ed3b7 291 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
92915f71 292
5d9a533b 293 if (is_vlan && test_bit(tag & VLAN_VID_MASK, adapter->active_vlans))
86a9bad3 294 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
dadcd65f 295
366c1099
GR		 296 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
297 napi_gro_receive(&q_vector->napi, skb);
298 else
299 netif_rx(skb);
92915f71
GR		 300}
301
08681618
JK		 302/**
303 * ixgbevf_rx_skb - Helper function to determine proper Rx method
304 * @q_vector: structure containing interrupt and ring information
305 * @skb: packet to send up
306 * @status: hardware indication of status of receive
307 * @rx_desc: rx descriptor
308 **/
309static void ixgbevf_rx_skb(struct ixgbevf_q_vector *q_vector,
310 struct sk_buff *skb, u8 status,
311 union ixgbe_adv_rx_desc *rx_desc)
312{
313 ixgbevf_receive_skb(q_vector, skb, status, rx_desc);
314}
315
92915f71
GR		 316/**
317 * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum
55fb277c 318 * @ring: pointer to Rx descriptor ring structure
92915f71
GR		 319 * @status_err: hardware indication of status of receive
320 * @skb: skb currently being received and modified
321 **/
55fb277c 322static inline void ixgbevf_rx_checksum(struct ixgbevf_ring *ring,
92915f71
GR		 323 u32 status_err, struct sk_buff *skb)
324{
bc8acf2c 325 skb_checksum_none_assert(skb);
92915f71
GR		 326
327 /* Rx csum disabled */
fb40195c 328 if (!(ring->netdev->features & NETIF_F_RXCSUM))
92915f71
GR		 329 return;
330
331 /* if IP and error */
332 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
333 (status_err & IXGBE_RXDADV_ERR_IPE)) {
55fb277c 334 ring->hw_csum_rx_error++;
92915f71
GR		 335 return;
336 }
337
338 if (!(status_err & IXGBE_RXD_STAT_L4CS))
339 return;
340
341 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
55fb277c 342 ring->hw_csum_rx_error++;
92915f71
GR		 343 return;
344 }
345
346 /* It must be a TCP or UDP packet with a valid checksum */
347 skb->ip_summed = CHECKSUM_UNNECESSARY;
55fb277c 348 ring->hw_csum_rx_good++;
92915f71
GR		 349}
350
351/**
352 * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split
353 * @adapter: address of board private structure
354 **/
355static void ixgbevf_alloc_rx_buffers(struct ixgbevf_adapter *adapter,
356 struct ixgbevf_ring *rx_ring,
357 int cleaned_count)
358{
359 struct pci_dev *pdev = adapter->pdev;
360 union ixgbe_adv_rx_desc *rx_desc;
361 struct ixgbevf_rx_buffer *bi;
fb40195c 362 unsigned int i = rx_ring->next_to_use;
92915f71 363
92915f71
GR		 364 bi = &rx_ring->rx_buffer_info[i];
365
366 while (cleaned_count--) {
908421f6 367 rx_desc = IXGBEVF_RX_DESC(rx_ring, i);
b9dd245b
GR		 368
369 if (!bi->skb) {
370 struct sk_buff *skb;
371
fb40195c
AD		 372 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
373 rx_ring->rx_buf_len);
92915f71
GR		 374 if (!skb) {
375 adapter->alloc_rx_buff_failed++;
376 goto no_buffers;
377 }
92915f71 378 bi->skb = skb;
b9dd245b 379
2a1f8794 380 bi->dma = dma_map_single(&pdev->dev, skb->data,
92915f71 381 rx_ring->rx_buf_len,
2a1f8794 382 DMA_FROM_DEVICE);
6132ee8a
GR		 383 if (dma_mapping_error(&pdev->dev, bi->dma)) {
384 dev_kfree_skb(skb);
385 bi->skb = NULL;
386 dev_err(&pdev->dev, "RX DMA map failed\n");
387 break;
388 }
92915f71 389 }
77d5dfca 390 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
92915f71
GR		 391
392 i++;
393 if (i == rx_ring->count)
394 i = 0;
395 bi = &rx_ring->rx_buffer_info[i];
396 }
397
398no_buffers:
399 if (rx_ring->next_to_use != i) {
400 rx_ring->next_to_use = i;
92915f71
GR		 401 ixgbevf_release_rx_desc(&adapter->hw, rx_ring, i);
402 }
403}
404
405static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter,
5f3600eb 406 u32 qmask)
92915f71 407{
92915f71
GR		 408 struct ixgbe_hw *hw = &adapter->hw;
409
5f3600eb 410 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, qmask);
92915f71
GR		 411}
412
08e50a20
JK		 413static int ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector,
414 struct ixgbevf_ring *rx_ring,
415 int budget)
92915f71
GR		 416{
417 struct ixgbevf_adapter *adapter = q_vector->adapter;
418 struct pci_dev *pdev = adapter->pdev;
419 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
420 struct ixgbevf_rx_buffer *rx_buffer_info, *next_buffer;
421 struct sk_buff *skb;
422 unsigned int i;
423 u32 len, staterr;
92915f71
GR		 424 int cleaned_count = 0;
425 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
426
427 i = rx_ring->next_to_clean;
908421f6 428 rx_desc = IXGBEVF_RX_DESC(rx_ring, i);
92915f71
GR		 429 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
430 rx_buffer_info = &rx_ring->rx_buffer_info[i];
431
432 while (staterr & IXGBE_RXD_STAT_DD) {
fa71ae27 433 if (!budget)
92915f71 434 break;
fa71ae27 435 budget--;
92915f71 436
2d0bb1c1 437 rmb(); /* read descriptor and rx_buffer_info after status DD */
77d5dfca 438 len = le16_to_cpu(rx_desc->wb.upper.length);
92915f71
GR		 439 skb = rx_buffer_info->skb;
440 prefetch(skb->data - NET_IP_ALIGN);
441 rx_buffer_info->skb = NULL;
442
443 if (rx_buffer_info->dma) {
2a1f8794 444 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
92915f71 445 rx_ring->rx_buf_len,
2a1f8794 446 DMA_FROM_DEVICE);
92915f71
GR		 447 rx_buffer_info->dma = 0;
448 skb_put(skb, len);
449 }
450
92915f71
GR		 451 i++;
452 if (i == rx_ring->count)
453 i = 0;
454
908421f6 455 next_rxd = IXGBEVF_RX_DESC(rx_ring, i);
92915f71
GR		 456 prefetch(next_rxd);
457 cleaned_count++;
458
459 next_buffer = &rx_ring->rx_buffer_info[i];
460
461 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
77d5dfca 462 skb->next = next_buffer->skb;
5c60f81a 463 IXGBE_CB(skb->next)->prev = skb;
92915f71
GR		 464 adapter->non_eop_descs++;
465 goto next_desc;
466 }
467
5c60f81a
AD		 468 /* we should not be chaining buffers, if we did drop the skb */
469 if (IXGBE_CB(skb)->prev) {
470 do {
471 struct sk_buff *this = skb;
472 skb = IXGBE_CB(skb)->prev;
473 dev_kfree_skb(this);
474 } while (skb);
475 goto next_desc;
476 }
477
92915f71
GR		 478 /* ERR_MASK will only have valid bits if EOP set */
479 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
480 dev_kfree_skb_irq(skb);
481 goto next_desc;
482 }
483
55fb277c 484 ixgbevf_rx_checksum(rx_ring, staterr, skb);
92915f71
GR		 485
486 /* probably a little skewed due to removing CRC */
487 total_rx_bytes += skb->len;
488 total_rx_packets++;
489
490 /*
491 * Work around issue of some types of VM to VM loop back
492 * packets not getting split correctly
493 */
494 if (staterr & IXGBE_RXD_STAT_LB) {
e743d313 495 u32 header_fixup_len = skb_headlen(skb);
92915f71
GR		 496 if (header_fixup_len < 14)
497 skb_push(skb, header_fixup_len);
498 }
fb40195c 499 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
92915f71 500
815cccbf
JF		 501 /* Workaround hardware that can't do proper VEPA multicast
502 * source pruning.
503 */
504 if ((skb->pkt_type & (PACKET_BROADCAST | PACKET_MULTICAST)) &&
7367d0b5
JP		 505 ether_addr_equal(adapter->netdev->dev_addr,
506 eth_hdr(skb)->h_source)) {
815cccbf
JF		 507 dev_kfree_skb_irq(skb);
508 goto next_desc;
509 }
510
08681618 511 ixgbevf_rx_skb(q_vector, skb, staterr, rx_desc);
92915f71
GR		 512
513next_desc:
514 rx_desc->wb.upper.status_error = 0;
515
516 /* return some buffers to hardware, one at a time is too slow */
517 if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) {
518 ixgbevf_alloc_rx_buffers(adapter, rx_ring,
519 cleaned_count);
520 cleaned_count = 0;
521 }
522
523 /* use prefetched values */
524 rx_desc = next_rxd;
525 rx_buffer_info = &rx_ring->rx_buffer_info[i];
526
527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
528 }
529
530 rx_ring->next_to_clean = i;
531 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
532
533 if (cleaned_count)
534 ixgbevf_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
535
4197aa7b 536 u64_stats_update_begin(&rx_ring->syncp);
92915f71
GR		 537 rx_ring->total_packets += total_rx_packets;
538 rx_ring->total_bytes += total_rx_bytes;
4197aa7b 539 u64_stats_update_end(&rx_ring->syncp);
ac6ed8f0
GR		 540 q_vector->rx.total_packets += total_rx_packets;
541 q_vector->rx.total_bytes += total_rx_bytes;
92915f71 542
08e50a20 543 return total_rx_packets;
92915f71
GR		 544}
545
546/**
fa71ae27 547 * ixgbevf_poll - NAPI polling calback
92915f71
GR		 548 * @napi: napi struct with our devices info in it
549 * @budget: amount of work driver is allowed to do this pass, in packets
550 *
fa71ae27 551 * This function will clean more than one or more rings associated with a
92915f71
GR		 552 * q_vector.
553 **/
fa71ae27 554static int ixgbevf_poll(struct napi_struct *napi, int budget)
92915f71
GR		 555{
556 struct ixgbevf_q_vector *q_vector =
557 container_of(napi, struct ixgbevf_q_vector, napi);
558 struct ixgbevf_adapter *adapter = q_vector->adapter;
fa71ae27
AD		 559 struct ixgbevf_ring *ring;
560 int per_ring_budget;
561 bool clean_complete = true;
562
563 ixgbevf_for_each_ring(ring, q_vector->tx)
564 clean_complete &= ixgbevf_clean_tx_irq(q_vector, ring);
92915f71
GR		 565
566 /* attempt to distribute budget to each queue fairly, but don't allow
567 * the budget to go below 1 because we'll exit polling */
fa71ae27
AD		 568 if (q_vector->rx.count > 1)
569 per_ring_budget = max(budget/q_vector->rx.count, 1);
570 else
571 per_ring_budget = budget;
572
366c1099 573 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
fa71ae27 574 ixgbevf_for_each_ring(ring, q_vector->rx)
08e50a20
JK		 575 clean_complete &= (ixgbevf_clean_rx_irq(q_vector, ring,
576 per_ring_budget)
577 < per_ring_budget);
366c1099 578 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
fa71ae27
AD		 579
580 /* If all work not completed, return budget and keep polling */
581 if (!clean_complete)
582 return budget;
583 /* all work done, exit the polling mode */
584 napi_complete(napi);
585 if (adapter->rx_itr_setting & 1)
586 ixgbevf_set_itr(q_vector);
587 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
588 ixgbevf_irq_enable_queues(adapter,
589 1 << q_vector->v_idx);
92915f71 590
fa71ae27 591 return 0;
92915f71
GR		 592}
593
ce422606
GR		 594/**
595 * ixgbevf_write_eitr - write VTEITR register in hardware specific way
596 * @q_vector: structure containing interrupt and ring information
597 */
3849623e 598void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector)
ce422606
GR		 599{
600 struct ixgbevf_adapter *adapter = q_vector->adapter;
601 struct ixgbe_hw *hw = &adapter->hw;
602 int v_idx = q_vector->v_idx;
603 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
604
605 /*
606 * set the WDIS bit to not clear the timer bits and cause an
607 * immediate assertion of the interrupt
608 */
609 itr_reg |= IXGBE_EITR_CNT_WDIS;
610
611 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg);
612}
92915f71
GR		 613
614/**
615 * ixgbevf_configure_msix - Configure MSI-X hardware
616 * @adapter: board private structure
617 *
618 * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X
619 * interrupts.
620 **/
621static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter)
622{
623 struct ixgbevf_q_vector *q_vector;
6b43c446 624 int q_vectors, v_idx;
92915f71
GR		 625
626 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5f3600eb 627 adapter->eims_enable_mask = 0;
92915f71
GR		 628
629 /*
630 * Populate the IVAR table and set the ITR values to the
631 * corresponding register.
632 */
633 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
6b43c446 634 struct ixgbevf_ring *ring;
92915f71 635 q_vector = adapter->q_vector[v_idx];
6b43c446
AD		 636
637 ixgbevf_for_each_ring(ring, q_vector->rx)
638 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx);
639
640 ixgbevf_for_each_ring(ring, q_vector->tx)
641 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx);
92915f71 642
5f3600eb
AD		 643 if (q_vector->tx.ring && !q_vector->rx.ring) {
644 /* tx only vector */
645 if (adapter->tx_itr_setting == 1)
646 q_vector->itr = IXGBE_10K_ITR;
647 else
648 q_vector->itr = adapter->tx_itr_setting;
649 } else {
650 /* rx or rx/tx vector */
651 if (adapter->rx_itr_setting == 1)
652 q_vector->itr = IXGBE_20K_ITR;
653 else
654 q_vector->itr = adapter->rx_itr_setting;
655 }
656
657 /* add q_vector eims value to global eims_enable_mask */
658 adapter->eims_enable_mask |= 1 << v_idx;
92915f71 659
5f3600eb 660 ixgbevf_write_eitr(q_vector);
92915f71
GR		 661 }
662
663 ixgbevf_set_ivar(adapter, -1, 1, v_idx);
5f3600eb
AD		 664 /* setup eims_other and add value to global eims_enable_mask */
665 adapter->eims_other = 1 << v_idx;
666 adapter->eims_enable_mask |= adapter->eims_other;
92915f71
GR		 667}
668
669enum latency_range {
670 lowest_latency = 0,
671 low_latency = 1,
672 bulk_latency = 2,
673 latency_invalid = 255
674};
675
676/**
677 * ixgbevf_update_itr - update the dynamic ITR value based on statistics
5f3600eb
AD		 678 * @q_vector: structure containing interrupt and ring information
679 * @ring_container: structure containing ring performance data
92915f71
GR		 680 *
681 * Stores a new ITR value based on packets and byte
682 * counts during the last interrupt. The advantage of per interrupt
683 * computation is faster updates and more accurate ITR for the current
684 * traffic pattern. Constants in this function were computed
685 * based on theoretical maximum wire speed and thresholds were set based
686 * on testing data as well as attempting to minimize response time
687 * while increasing bulk throughput.
688 **/
5f3600eb
AD		 689static void ixgbevf_update_itr(struct ixgbevf_q_vector *q_vector,
690 struct ixgbevf_ring_container *ring_container)
92915f71 691{
5f3600eb
AD		 692 int bytes = ring_container->total_bytes;
693 int packets = ring_container->total_packets;
92915f71
GR		 694 u32 timepassed_us;
695 u64 bytes_perint;
5f3600eb 696 u8 itr_setting = ring_container->itr;
92915f71
GR		 697
698 if (packets == 0)
5f3600eb 699 return;
92915f71
GR		 700
701 /* simple throttlerate management
702 * 0-20MB/s lowest (100000 ints/s)
703 * 20-100MB/s low (20000 ints/s)
704 * 100-1249MB/s bulk (8000 ints/s)
705 */
706 /* what was last interrupt timeslice? */
5f3600eb 707 timepassed_us = q_vector->itr >> 2;
92915f71
GR		 708 bytes_perint = bytes / timepassed_us; /* bytes/usec */
709
710 switch (itr_setting) {
711 case lowest_latency:
e2c28ce7 712 if (bytes_perint > 10)
5f3600eb 713 itr_setting = low_latency;
92915f71
GR		 714 break;
715 case low_latency:
e2c28ce7 716 if (bytes_perint > 20)
5f3600eb 717 itr_setting = bulk_latency;
e2c28ce7 718 else if (bytes_perint <= 10)
5f3600eb 719 itr_setting = lowest_latency;
92915f71
GR		 720 break;
721 case bulk_latency:
e2c28ce7 722 if (bytes_perint <= 20)
5f3600eb 723 itr_setting = low_latency;
92915f71
GR		 724 break;
725 }
726
5f3600eb
AD		 727 /* clear work counters since we have the values we need */
728 ring_container->total_bytes = 0;
729 ring_container->total_packets = 0;
730
731 /* write updated itr to ring container */
732 ring_container->itr = itr_setting;
92915f71
GR		 733}
734
fa71ae27 735static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector)
92915f71 736{
5f3600eb
AD		 737 u32 new_itr = q_vector->itr;
738 u8 current_itr;
92915f71 739
5f3600eb
AD		 740 ixgbevf_update_itr(q_vector, &q_vector->tx);
741 ixgbevf_update_itr(q_vector, &q_vector->rx);
92915f71 742
6b43c446 743 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
92915f71
GR		 744
745 switch (current_itr) {
746 /* counts and packets in update_itr are dependent on these numbers */
747 case lowest_latency:
5f3600eb 748 new_itr = IXGBE_100K_ITR;
92915f71
GR		 749 break;
750 case low_latency:
5f3600eb 751 new_itr = IXGBE_20K_ITR;
92915f71
GR		 752 break;
753 case bulk_latency:
754 default:
5f3600eb 755 new_itr = IXGBE_8K_ITR;
92915f71
GR		 756 break;
757 }
758
5f3600eb 759 if (new_itr != q_vector->itr) {
92915f71 760 /* do an exponential smoothing */
5f3600eb
AD		 761 new_itr = (10 * new_itr * q_vector->itr) /
762 ((9 * new_itr) + q_vector->itr);
763
764 /* save the algorithm value here */
765 q_vector->itr = new_itr;
766
767 ixgbevf_write_eitr(q_vector);
92915f71 768 }
92915f71
GR		 769}
770
4b2cd27f 771static irqreturn_t ixgbevf_msix_other(int irq, void *data)
92915f71 772{
fa71ae27 773 struct ixgbevf_adapter *adapter = data;
92915f71 774 struct ixgbe_hw *hw = &adapter->hw;
08259594 775
4b2cd27f 776 hw->mac.get_link_status = 1;
1e72bfc3 777
c7bb417d
DS		 778 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
779 mod_timer(&adapter->watchdog_timer, jiffies);
3a2c4033 780
5f3600eb
AD		 781 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_other);
782
92915f71
GR		 783 return IRQ_HANDLED;
784}
785
92915f71 786/**
fa71ae27 787 * ixgbevf_msix_clean_rings - single unshared vector rx clean (all queues)
92915f71
GR		 788 * @irq: unused
789 * @data: pointer to our q_vector struct for this interrupt vector
790 **/
fa71ae27 791static irqreturn_t ixgbevf_msix_clean_rings(int irq, void *data)
92915f71
GR		 792{
793 struct ixgbevf_q_vector *q_vector = data;
92915f71 794
5f3600eb 795 /* EIAM disabled interrupts (on this vector) for us */
fa71ae27
AD		 796 if (q_vector->rx.ring || q_vector->tx.ring)
797 napi_schedule(&q_vector->napi);
92915f71
GR		 798
799 return IRQ_HANDLED;
800}
801
802static inline void map_vector_to_rxq(struct ixgbevf_adapter *a, int v_idx,
803 int r_idx)
804{
805 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
806
6b43c446
AD		 807 a->rx_ring[r_idx].next = q_vector->rx.ring;
808 q_vector->rx.ring = &a->rx_ring[r_idx];
809 q_vector->rx.count++;
92915f71
GR		 810}
811
812static inline void map_vector_to_txq(struct ixgbevf_adapter *a, int v_idx,
813 int t_idx)
814{
815 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
816
6b43c446
AD		 817 a->tx_ring[t_idx].next = q_vector->tx.ring;
818 q_vector->tx.ring = &a->tx_ring[t_idx];
819 q_vector->tx.count++;
92915f71
GR		 820}
821
822/**
823 * ixgbevf_map_rings_to_vectors - Maps descriptor rings to vectors
824 * @adapter: board private structure to initialize
825 *
826 * This function maps descriptor rings to the queue-specific vectors
827 * we were allotted through the MSI-X enabling code. Ideally, we'd have
828 * one vector per ring/queue, but on a constrained vector budget, we
829 * group the rings as "efficiently" as possible. You would add new
830 * mapping configurations in here.
831 **/
832static int ixgbevf_map_rings_to_vectors(struct ixgbevf_adapter *adapter)
833{
834 int q_vectors;
835 int v_start = 0;
836 int rxr_idx = 0, txr_idx = 0;
837 int rxr_remaining = adapter->num_rx_queues;
838 int txr_remaining = adapter->num_tx_queues;
839 int i, j;
840 int rqpv, tqpv;
841 int err = 0;
842
843 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
844
845 /*
846 * The ideal configuration...
847 * We have enough vectors to map one per queue.
848 */
849 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
850 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
851 map_vector_to_rxq(adapter, v_start, rxr_idx);
852
853 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
854 map_vector_to_txq(adapter, v_start, txr_idx);
855 goto out;
856 }
857
858 /*
859 * If we don't have enough vectors for a 1-to-1
860 * mapping, we'll have to group them so there are
861 * multiple queues per vector.
862 */
863 /* Re-adjusting *qpv takes care of the remainder. */
864 for (i = v_start; i < q_vectors; i++) {
865 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
866 for (j = 0; j < rqpv; j++) {
867 map_vector_to_rxq(adapter, i, rxr_idx);
868 rxr_idx++;
869 rxr_remaining--;
870 }
871 }
872 for (i = v_start; i < q_vectors; i++) {
873 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
874 for (j = 0; j < tqpv; j++) {
875 map_vector_to_txq(adapter, i, txr_idx);
876 txr_idx++;
877 txr_remaining--;
878 }
879 }
880
881out:
882 return err;
883}
884
885/**
886 * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts
887 * @adapter: board private structure
888 *
889 * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests
890 * interrupts from the kernel.
891 **/
892static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter)
893{
894 struct net_device *netdev = adapter->netdev;
fa71ae27
AD		 895 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
896 int vector, err;
92915f71
GR		 897 int ri = 0, ti = 0;
898
92915f71 899 for (vector = 0; vector < q_vectors; vector++) {
fa71ae27
AD		 900 struct ixgbevf_q_vector *q_vector = adapter->q_vector[vector];
901 struct msix_entry *entry = &adapter->msix_entries[vector];
902
903 if (q_vector->tx.ring && q_vector->rx.ring) {
904 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
905 "%s-%s-%d", netdev->name, "TxRx", ri++);
906 ti++;
907 } else if (q_vector->rx.ring) {
908 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
909 "%s-%s-%d", netdev->name, "rx", ri++);
910 } else if (q_vector->tx.ring) {
911 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
912 "%s-%s-%d", netdev->name, "tx", ti++);
92915f71
GR		 913 } else {
914 /* skip this unused q_vector */
915 continue;
916 }
fa71ae27
AD		 917 err = request_irq(entry->vector, &ixgbevf_msix_clean_rings, 0,
918 q_vector->name, q_vector);
92915f71
GR		 919 if (err) {
920 hw_dbg(&adapter->hw,
921 "request_irq failed for MSIX interrupt "
922 "Error: %d\n", err);
923 goto free_queue_irqs;
924 }
925 }
926
92915f71 927 err = request_irq(adapter->msix_entries[vector].vector,
4b2cd27f 928 &ixgbevf_msix_other, 0, netdev->name, adapter);
92915f71
GR		 929 if (err) {
930 hw_dbg(&adapter->hw,
4b2cd27f 931 "request_irq for msix_other failed: %d\n", err);
92915f71
GR		 932 goto free_queue_irqs;
933 }
934
935 return 0;
936
937free_queue_irqs:
fa71ae27
AD		 938 while (vector) {
939 vector--;
940 free_irq(adapter->msix_entries[vector].vector,
941 adapter->q_vector[vector]);
942 }
a1f6c6b1 943 /* This failure is non-recoverable - it indicates the system is
944 * out of MSIX vector resources and the VF driver cannot run
945 * without them. Set the number of msix vectors to zero
946 * indicating that not enough can be allocated. The error
947 * will be returned to the user indicating device open failed.
948 * Any further attempts to force the driver to open will also
949 * fail. The only way to recover is to unload the driver and
950 * reload it again. If the system has recovered some MSIX
951 * vectors then it may succeed.
952 */
953 adapter->num_msix_vectors = 0;
92915f71
GR		 954 return err;
955}
956
957static inline void ixgbevf_reset_q_vectors(struct ixgbevf_adapter *adapter)
958{
959 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
960
961 for (i = 0; i < q_vectors; i++) {
962 struct ixgbevf_q_vector *q_vector = adapter->q_vector[i];
6b43c446
AD		 963 q_vector->rx.ring = NULL;
964 q_vector->tx.ring = NULL;
965 q_vector->rx.count = 0;
966 q_vector->tx.count = 0;
92915f71
GR		 967 }
968}
969
970/**
971 * ixgbevf_request_irq - initialize interrupts
972 * @adapter: board private structure
973 *
974 * Attempts to configure interrupts using the best available
975 * capabilities of the hardware and kernel.
976 **/
977static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter)
978{
979 int err = 0;
980
981 err = ixgbevf_request_msix_irqs(adapter);
982
983 if (err)
984 hw_dbg(&adapter->hw,
985 "request_irq failed, Error %d\n", err);
986
987 return err;
988}
989
990static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter)
991{
92915f71
GR		 992 int i, q_vectors;
993
994 q_vectors = adapter->num_msix_vectors;
92915f71
GR		 995 i = q_vectors - 1;
996
fa71ae27 997 free_irq(adapter->msix_entries[i].vector, adapter);
92915f71
GR		 998 i--;
999
1000 for (; i >= 0; i--) {
fa71ae27
AD		 1001 /* free only the irqs that were actually requested */
1002 if (!adapter->q_vector[i]->rx.ring &&
1003 !adapter->q_vector[i]->tx.ring)
1004 continue;
1005
92915f71
GR		 1006 free_irq(adapter->msix_entries[i].vector,
1007 adapter->q_vector[i]);
1008 }
1009
1010 ixgbevf_reset_q_vectors(adapter);
1011}
1012
1013/**
1014 * ixgbevf_irq_disable - Mask off interrupt generation on the NIC
1015 * @adapter: board private structure
1016 **/
1017static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter)
1018{
92915f71 1019 struct ixgbe_hw *hw = &adapter->hw;
5f3600eb 1020 int i;
92915f71 1021
5f3600eb 1022 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, 0);
92915f71 1023 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0);
5f3600eb 1024 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, 0);
92915f71
GR		 1025
1026 IXGBE_WRITE_FLUSH(hw);
1027
1028 for (i = 0; i < adapter->num_msix_vectors; i++)
1029 synchronize_irq(adapter->msix_entries[i].vector);
1030}
1031
1032/**
1033 * ixgbevf_irq_enable - Enable default interrupt generation settings
1034 * @adapter: board private structure
1035 **/
5f3600eb 1036static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter)
92915f71
GR		 1037{
1038 struct ixgbe_hw *hw = &adapter->hw;
92915f71 1039
5f3600eb
AD		 1040 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, adapter->eims_enable_mask);
1041 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, adapter->eims_enable_mask);
1042 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_enable_mask);
92915f71
GR		 1043}
1044
1045/**
1046 * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset
1047 * @adapter: board private structure
1048 *
1049 * Configure the Tx unit of the MAC after a reset.
1050 **/
1051static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter)
1052{
1053 u64 tdba;
1054 struct ixgbe_hw *hw = &adapter->hw;
1055 u32 i, j, tdlen, txctrl;
1056
1057 /* Setup the HW Tx Head and Tail descriptor pointers */
1058 for (i = 0; i < adapter->num_tx_queues; i++) {
1059 struct ixgbevf_ring *ring = &adapter->tx_ring[i];
1060 j = ring->reg_idx;
1061 tdba = ring->dma;
1062 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1063 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j),
1064 (tdba & DMA_BIT_MASK(32)));
1065 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32));
1066 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j), tdlen);
1067 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(j), 0);
1068 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(j), 0);
1069 adapter->tx_ring[i].head = IXGBE_VFTDH(j);
1070 adapter->tx_ring[i].tail = IXGBE_VFTDT(j);
1071 /* Disable Tx Head Writeback RO bit, since this hoses
1072 * bookkeeping if things aren't delivered in order.
1073 */
1074 txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(j));
1075 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1076 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(j), txctrl);
1077 }
1078}
1079
1080#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1081
1082static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, int index)
1083{
1084 struct ixgbevf_ring *rx_ring;
1085 struct ixgbe_hw *hw = &adapter->hw;
1086 u32 srrctl;
1087
1088 rx_ring = &adapter->rx_ring[index];
1089
1090 srrctl = IXGBE_SRRCTL_DROP_EN;
1091
77d5dfca 1092 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
92915f71 1093
dd1fe113
AD		 1094 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1095 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1096
92915f71
GR		 1097 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl);
1098}
1099
1bb9c639
DS		 1100static void ixgbevf_setup_psrtype(struct ixgbevf_adapter *adapter)
1101{
1102 struct ixgbe_hw *hw = &adapter->hw;
1103
1104 /* PSRTYPE must be initialized in 82599 */
1105 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
1106 IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR |
1107 IXGBE_PSRTYPE_L2HDR;
1108
1109 if (adapter->num_rx_queues > 1)
1110 psrtype |= 1 << 29;
1111
1112 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
1113}
1114
dd1fe113
AD		 1115static void ixgbevf_set_rx_buffer_len(struct ixgbevf_adapter *adapter)
1116{
1117 struct ixgbe_hw *hw = &adapter->hw;
1118 struct net_device *netdev = adapter->netdev;
1119 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1120 int i;
1121 u16 rx_buf_len;
1122
1123 /* notify the PF of our intent to use this size of frame */
1124 ixgbevf_rlpml_set_vf(hw, max_frame);
1125
1126 /* PF will allow an extra 4 bytes past for vlan tagged frames */
1127 max_frame += VLAN_HLEN;
1128
1129 /*
85624caf
GR		 1130 * Allocate buffer sizes that fit well into 32K and
1131 * take into account max frame size of 9.5K
dd1fe113
AD		 1132 */
1133 if ((hw->mac.type == ixgbe_mac_X540_vf) &&
1134 (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE))
1135 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85624caf
GR		 1136 else if (max_frame <= IXGBEVF_RXBUFFER_2K)
1137 rx_buf_len = IXGBEVF_RXBUFFER_2K;
1138 else if (max_frame <= IXGBEVF_RXBUFFER_4K)
1139 rx_buf_len = IXGBEVF_RXBUFFER_4K;
1140 else if (max_frame <= IXGBEVF_RXBUFFER_8K)
1141 rx_buf_len = IXGBEVF_RXBUFFER_8K;
dd1fe113 1142 else
85624caf 1143 rx_buf_len = IXGBEVF_RXBUFFER_10K;
dd1fe113
AD		 1144
1145 for (i = 0; i < adapter->num_rx_queues; i++)
1146 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1147}
1148
92915f71
GR		 1149/**
1150 * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset
1151 * @adapter: board private structure
1152 *
1153 * Configure the Rx unit of the MAC after a reset.
1154 **/
1155static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter)
1156{
1157 u64 rdba;
1158 struct ixgbe_hw *hw = &adapter->hw;
92915f71
GR		 1159 int i, j;
1160 u32 rdlen;
92915f71 1161
1bb9c639 1162 ixgbevf_setup_psrtype(adapter);
dd1fe113
AD		 1163
1164 /* set_rx_buffer_len must be called before ring initialization */
1165 ixgbevf_set_rx_buffer_len(adapter);
92915f71
GR		 1166
1167 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1168 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1169 * the Base and Length of the Rx Descriptor Ring */
1170 for (i = 0; i < adapter->num_rx_queues; i++) {
1171 rdba = adapter->rx_ring[i].dma;
1172 j = adapter->rx_ring[i].reg_idx;
1173 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(j),
1174 (rdba & DMA_BIT_MASK(32)));
1175 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(j), (rdba >> 32));
1176 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(j), rdlen);
1177 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(j), 0);
1178 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(j), 0);
1179 adapter->rx_ring[i].head = IXGBE_VFRDH(j);
1180 adapter->rx_ring[i].tail = IXGBE_VFRDT(j);
92915f71
GR		 1181
1182 ixgbevf_configure_srrctl(adapter, j);
1183 }
1184}
1185
80d5c368
PM		 1186static int ixgbevf_vlan_rx_add_vid(struct net_device *netdev,
1187 __be16 proto, u16 vid)
92915f71
GR		 1188{
1189 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1190 struct ixgbe_hw *hw = &adapter->hw;
2ddc7fe1
AD		 1191 int err;
1192
55fdd45b 1193 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1194
92915f71 1195 /* add VID to filter table */
2ddc7fe1 1196 err = hw->mac.ops.set_vfta(hw, vid, 0, true);
1c55ed76 1197
55fdd45b 1198 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 1199
2ddc7fe1
AD		 1200 /* translate error return types so error makes sense */
1201 if (err == IXGBE_ERR_MBX)
1202 return -EIO;
1203
1204 if (err == IXGBE_ERR_INVALID_ARGUMENT)
1205 return -EACCES;
1206
dadcd65f 1207 set_bit(vid, adapter->active_vlans);
8e586137 1208
2ddc7fe1 1209 return err;
92915f71
GR		 1210}
1211
80d5c368
PM		 1212static int ixgbevf_vlan_rx_kill_vid(struct net_device *netdev,
1213 __be16 proto, u16 vid)
92915f71
GR		 1214{
1215 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1216 struct ixgbe_hw *hw = &adapter->hw;
2ddc7fe1 1217 int err = -EOPNOTSUPP;
92915f71 1218
55fdd45b 1219 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1220
92915f71 1221 /* remove VID from filter table */
92fe0bf7 1222 err = hw->mac.ops.set_vfta(hw, vid, 0, false);
1c55ed76 1223
55fdd45b 1224 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 1225
dadcd65f 1226 clear_bit(vid, adapter->active_vlans);
8e586137 1227
2ddc7fe1 1228 return err;
92915f71
GR		 1229}
1230
1231static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter)
1232{
dadcd65f 1233 u16 vid;
92915f71 1234
dadcd65f 1235 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368
PM		 1236 ixgbevf_vlan_rx_add_vid(adapter->netdev,
1237 htons(ETH_P_8021Q), vid);
92915f71
GR		 1238}
1239
46ec20ff
GR		 1240static int ixgbevf_write_uc_addr_list(struct net_device *netdev)
1241{
1242 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1243 struct ixgbe_hw *hw = &adapter->hw;
1244 int count = 0;
1245
1246 if ((netdev_uc_count(netdev)) > 10) {
dbd9636e 1247 pr_err("Too many unicast filters - No Space\n");
46ec20ff
GR		 1248 return -ENOSPC;
1249 }
1250
1251 if (!netdev_uc_empty(netdev)) {
1252 struct netdev_hw_addr *ha;
1253 netdev_for_each_uc_addr(ha, netdev) {
1254 hw->mac.ops.set_uc_addr(hw, ++count, ha->addr);
1255 udelay(200);
1256 }
1257 } else {
1258 /*
1259 * If the list is empty then send message to PF driver to
1260 * clear all macvlans on this VF.
1261 */
1262 hw->mac.ops.set_uc_addr(hw, 0, NULL);
1263 }
1264
1265 return count;
1266}
1267
92915f71 1268/**
dee847f5 1269 * ixgbevf_set_rx_mode - Multicast and unicast set
92915f71
GR		 1270 * @netdev: network interface device structure
1271 *
1272 * The set_rx_method entry point is called whenever the multicast address
dee847f5
GR		 1273 * list, unicast address list or the network interface flags are updated.
1274 * This routine is responsible for configuring the hardware for proper
1275 * multicast mode and configuring requested unicast filters.
92915f71
GR		 1276 **/
1277static void ixgbevf_set_rx_mode(struct net_device *netdev)
1278{
1279 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1280 struct ixgbe_hw *hw = &adapter->hw;
92915f71 1281
55fdd45b 1282 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1283
92915f71 1284 /* reprogram multicast list */
92fe0bf7 1285 hw->mac.ops.update_mc_addr_list(hw, netdev);
46ec20ff
GR		 1286
1287 ixgbevf_write_uc_addr_list(netdev);
1c55ed76 1288
55fdd45b 1289 spin_unlock_bh(&adapter->mbx_lock);
92915f71
GR		 1290}
1291
1292static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter)
1293{
1294 int q_idx;
1295 struct ixgbevf_q_vector *q_vector;
1296 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1297
1298 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
92915f71 1299 q_vector = adapter->q_vector[q_idx];
fa71ae27 1300 napi_enable(&q_vector->napi);
92915f71
GR		 1301 }
1302}
1303
1304static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter)
1305{
1306 int q_idx;
1307 struct ixgbevf_q_vector *q_vector;
1308 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1309
1310 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1311 q_vector = adapter->q_vector[q_idx];
92915f71
GR		 1312 napi_disable(&q_vector->napi);
1313 }
1314}
1315
1316static void ixgbevf_configure(struct ixgbevf_adapter *adapter)
1317{
1318 struct net_device *netdev = adapter->netdev;
1319 int i;
1320
1321 ixgbevf_set_rx_mode(netdev);
1322
1323 ixgbevf_restore_vlan(adapter);
1324
1325 ixgbevf_configure_tx(adapter);
1326 ixgbevf_configure_rx(adapter);
1327 for (i = 0; i < adapter->num_rx_queues; i++) {
1328 struct ixgbevf_ring *ring = &adapter->rx_ring[i];
18c63089
AD		 1329 ixgbevf_alloc_rx_buffers(adapter, ring,
1330 IXGBE_DESC_UNUSED(ring));
92915f71
GR		 1331 }
1332}
1333
858c3dda
DS		 1334#define IXGBEVF_MAX_RX_DESC_POLL 10
1335static void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter,
1336 int rxr)
92915f71
GR		 1337{
1338 struct ixgbe_hw *hw = &adapter->hw;
858c3dda
DS		 1339 int wait_loop = IXGBEVF_MAX_RX_DESC_POLL;
1340 u32 rxdctl;
92915f71 1341 int j = adapter->rx_ring[rxr].reg_idx;
92915f71 1342
858c3dda
DS		 1343 do {
1344 usleep_range(1000, 2000);
1345 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j));
1346 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
1347
1348 if (!wait_loop)
1349 hw_dbg(hw, "RXDCTL.ENABLE queue %d not set while polling\n",
1350 rxr);
1351
1352 ixgbevf_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
1353 (adapter->rx_ring[rxr].count - 1));
1354}
92915f71 1355
858c3dda
DS		 1356static void ixgbevf_disable_rx_queue(struct ixgbevf_adapter *adapter,
1357 struct ixgbevf_ring *ring)
1358{
1359 struct ixgbe_hw *hw = &adapter->hw;
1360 int wait_loop = IXGBEVF_MAX_RX_DESC_POLL;
1361 u32 rxdctl;
1362 u8 reg_idx = ring->reg_idx;
1363
1364 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));
1365 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
1366
1367 /* write value back with RXDCTL.ENABLE bit cleared */
1368 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl);
1369
1370 /* the hardware may take up to 100us to really disable the rx queue */
1371 do {
1372 udelay(10);
1373 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));
1374 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
1375
1376 if (!wait_loop)
1377 hw_dbg(hw, "RXDCTL.ENABLE queue %d not cleared while polling\n",
1378 reg_idx);
92915f71
GR		 1379}
1380
33bd9f60
GR		 1381static void ixgbevf_save_reset_stats(struct ixgbevf_adapter *adapter)
1382{
1383 /* Only save pre-reset stats if there are some */
1384 if (adapter->stats.vfgprc || adapter->stats.vfgptc) {
1385 adapter->stats.saved_reset_vfgprc += adapter->stats.vfgprc -
1386 adapter->stats.base_vfgprc;
1387 adapter->stats.saved_reset_vfgptc += adapter->stats.vfgptc -
1388 adapter->stats.base_vfgptc;
1389 adapter->stats.saved_reset_vfgorc += adapter->stats.vfgorc -
1390 adapter->stats.base_vfgorc;
1391 adapter->stats.saved_reset_vfgotc += adapter->stats.vfgotc -
1392 adapter->stats.base_vfgotc;
1393 adapter->stats.saved_reset_vfmprc += adapter->stats.vfmprc -
1394 adapter->stats.base_vfmprc;
1395 }
1396}
1397
1398static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter)
1399{
1400 struct ixgbe_hw *hw = &adapter->hw;
1401
1402 adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC);
1403 adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB);
1404 adapter->stats.last_vfgorc |=
1405 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32);
1406 adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC);
1407 adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB);
1408 adapter->stats.last_vfgotc |=
1409 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32);
1410 adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC);
1411
1412 adapter->stats.base_vfgprc = adapter->stats.last_vfgprc;
1413 adapter->stats.base_vfgorc = adapter->stats.last_vfgorc;
1414 adapter->stats.base_vfgptc = adapter->stats.last_vfgptc;
1415 adapter->stats.base_vfgotc = adapter->stats.last_vfgotc;
1416 adapter->stats.base_vfmprc = adapter->stats.last_vfmprc;
1417}
1418
31186785
AD		 1419static void ixgbevf_negotiate_api(struct ixgbevf_adapter *adapter)
1420{
1421 struct ixgbe_hw *hw = &adapter->hw;
56e94095
AD		 1422 int api[] = { ixgbe_mbox_api_11,
1423 ixgbe_mbox_api_10,
31186785
AD		 1424 ixgbe_mbox_api_unknown };
1425 int err = 0, idx = 0;
1426
55fdd45b 1427 spin_lock_bh(&adapter->mbx_lock);
31186785
AD		 1428
1429 while (api[idx] != ixgbe_mbox_api_unknown) {
1430 err = ixgbevf_negotiate_api_version(hw, api[idx]);
1431 if (!err)
1432 break;
1433 idx++;
1434 }
1435
55fdd45b 1436 spin_unlock_bh(&adapter->mbx_lock);
31186785
AD		 1437}
1438
795180d8 1439static void ixgbevf_up_complete(struct ixgbevf_adapter *adapter)
92915f71
GR		 1440{
1441 struct net_device *netdev = adapter->netdev;
1442 struct ixgbe_hw *hw = &adapter->hw;
1443 int i, j = 0;
1444 int num_rx_rings = adapter->num_rx_queues;
1445 u32 txdctl, rxdctl;
1446
1447 for (i = 0; i < adapter->num_tx_queues; i++) {
1448 j = adapter->tx_ring[i].reg_idx;
1449 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1450 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1451 txdctl |= (8 << 16);
1452 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1453 }
1454
1455 for (i = 0; i < adapter->num_tx_queues; i++) {
1456 j = adapter->tx_ring[i].reg_idx;
1457 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1458 txdctl |= IXGBE_TXDCTL_ENABLE;
1459 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1460 }
1461
1462 for (i = 0; i < num_rx_rings; i++) {
1463 j = adapter->rx_ring[i].reg_idx;
1464 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j));
dadcd65f 1465 rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME;
69bfbec4
GR		 1466 if (hw->mac.type == ixgbe_mac_X540_vf) {
1467 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
1468 rxdctl |= ((netdev->mtu + ETH_HLEN + ETH_FCS_LEN) |
1469 IXGBE_RXDCTL_RLPML_EN);
1470 }
92915f71
GR		 1471 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(j), rxdctl);
1472 ixgbevf_rx_desc_queue_enable(adapter, i);
1473 }
1474
1475 ixgbevf_configure_msix(adapter);
1476
55fdd45b 1477 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1478
92fe0bf7
GR		 1479 if (is_valid_ether_addr(hw->mac.addr))
1480 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
1481 else
1482 hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0);
92915f71 1483
55fdd45b 1484 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 1485
92915f71
GR		 1486 clear_bit(__IXGBEVF_DOWN, &adapter->state);
1487 ixgbevf_napi_enable_all(adapter);
1488
1489 /* enable transmits */
1490 netif_tx_start_all_queues(netdev);
1491
33bd9f60
GR		 1492 ixgbevf_save_reset_stats(adapter);
1493 ixgbevf_init_last_counter_stats(adapter);
1494
4b2cd27f 1495 hw->mac.get_link_status = 1;
92915f71 1496 mod_timer(&adapter->watchdog_timer, jiffies);
92915f71
GR		 1497}
1498
56e94095
AD		 1499static int ixgbevf_reset_queues(struct ixgbevf_adapter *adapter)
1500{
1501 struct ixgbe_hw *hw = &adapter->hw;
1502 struct ixgbevf_ring *rx_ring;
1503 unsigned int def_q = 0;
1504 unsigned int num_tcs = 0;
1505 unsigned int num_rx_queues = 1;
1506 int err, i;
1507
55fdd45b 1508 spin_lock_bh(&adapter->mbx_lock);
56e94095
AD		 1509
1510 /* fetch queue configuration from the PF */
1511 err = ixgbevf_get_queues(hw, &num_tcs, &def_q);
1512
55fdd45b 1513 spin_unlock_bh(&adapter->mbx_lock);
56e94095
AD		 1514
1515 if (err)
1516 return err;
1517
1518 if (num_tcs > 1) {
1519 /* update default Tx ring register index */
1520 adapter->tx_ring[0].reg_idx = def_q;
1521
1522 /* we need as many queues as traffic classes */
1523 num_rx_queues = num_tcs;
1524 }
1525
1526 /* nothing to do if we have the correct number of queues */
1527 if (adapter->num_rx_queues == num_rx_queues)
1528 return 0;
1529
1530 /* allocate new rings */
1531 rx_ring = kcalloc(num_rx_queues,
1532 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1533 if (!rx_ring)
1534 return -ENOMEM;
1535
1536 /* setup ring fields */
1537 for (i = 0; i < num_rx_queues; i++) {
1538 rx_ring[i].count = adapter->rx_ring_count;
1539 rx_ring[i].queue_index = i;
1540 rx_ring[i].reg_idx = i;
1541 rx_ring[i].dev = &adapter->pdev->dev;
1542 rx_ring[i].netdev = adapter->netdev;
1543
1544 /* allocate resources on the ring */
1545 err = ixgbevf_setup_rx_resources(adapter, &rx_ring[i]);
1546 if (err) {
1547 while (i) {
1548 i--;
1549 ixgbevf_free_rx_resources(adapter, &rx_ring[i]);
1550 }
1551 kfree(rx_ring);
1552 return err;
1553 }
1554 }
1555
1556 /* free the existing rings and queues */
1557 ixgbevf_free_all_rx_resources(adapter);
1558 adapter->num_rx_queues = 0;
1559 kfree(adapter->rx_ring);
1560
1561 /* move new rings into position on the adapter struct */
1562 adapter->rx_ring = rx_ring;
1563 adapter->num_rx_queues = num_rx_queues;
1564
1565 /* reset ring to vector mapping */
1566 ixgbevf_reset_q_vectors(adapter);
1567 ixgbevf_map_rings_to_vectors(adapter);
1568
1569 return 0;
1570}
1571
795180d8 1572void ixgbevf_up(struct ixgbevf_adapter *adapter)
92915f71 1573{
92915f71
GR		 1574 struct ixgbe_hw *hw = &adapter->hw;
1575
56e94095
AD		 1576 ixgbevf_reset_queues(adapter);
1577
92915f71
GR		 1578 ixgbevf_configure(adapter);
1579
795180d8 1580 ixgbevf_up_complete(adapter);
92915f71
GR		 1581
1582 /* clear any pending interrupts, may auto mask */
1583 IXGBE_READ_REG(hw, IXGBE_VTEICR);
1584
5f3600eb 1585 ixgbevf_irq_enable(adapter);
92915f71
GR		 1586}
1587
1588/**
1589 * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue
1590 * @adapter: board private structure
1591 * @rx_ring: ring to free buffers from
1592 **/
1593static void ixgbevf_clean_rx_ring(struct ixgbevf_adapter *adapter,
1594 struct ixgbevf_ring *rx_ring)
1595{
1596 struct pci_dev *pdev = adapter->pdev;
1597 unsigned long size;
1598 unsigned int i;
1599
c0456c23
GR		 1600 if (!rx_ring->rx_buffer_info)
1601 return;
92915f71 1602
c0456c23 1603 /* Free all the Rx ring sk_buffs */
92915f71
GR		 1604 for (i = 0; i < rx_ring->count; i++) {
1605 struct ixgbevf_rx_buffer *rx_buffer_info;
1606
1607 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1608 if (rx_buffer_info->dma) {
2a1f8794 1609 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
92915f71 1610 rx_ring->rx_buf_len,
2a1f8794 1611 DMA_FROM_DEVICE);
92915f71
GR		 1612 rx_buffer_info->dma = 0;
1613 }
1614 if (rx_buffer_info->skb) {
1615 struct sk_buff *skb = rx_buffer_info->skb;
1616 rx_buffer_info->skb = NULL;
1617 do {
1618 struct sk_buff *this = skb;
5c60f81a 1619 skb = IXGBE_CB(skb)->prev;
92915f71
GR		 1620 dev_kfree_skb(this);
1621 } while (skb);
1622 }
92915f71
GR		 1623 }
1624
1625 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
1626 memset(rx_ring->rx_buffer_info, 0, size);
1627
1628 /* Zero out the descriptor ring */
1629 memset(rx_ring->desc, 0, rx_ring->size);
1630
1631 rx_ring->next_to_clean = 0;
1632 rx_ring->next_to_use = 0;
1633
1634 if (rx_ring->head)
1635 writel(0, adapter->hw.hw_addr + rx_ring->head);
1636 if (rx_ring->tail)
1637 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1638}
1639
1640/**
1641 * ixgbevf_clean_tx_ring - Free Tx Buffers
1642 * @adapter: board private structure
1643 * @tx_ring: ring to be cleaned
1644 **/
1645static void ixgbevf_clean_tx_ring(struct ixgbevf_adapter *adapter,
1646 struct ixgbevf_ring *tx_ring)
1647{
1648 struct ixgbevf_tx_buffer *tx_buffer_info;
1649 unsigned long size;
1650 unsigned int i;
1651
c0456c23
GR		 1652 if (!tx_ring->tx_buffer_info)
1653 return;
1654
92915f71 1655 /* Free all the Tx ring sk_buffs */
92915f71
GR		 1656 for (i = 0; i < tx_ring->count; i++) {
1657 tx_buffer_info = &tx_ring->tx_buffer_info[i];
70a10e25 1658 ixgbevf_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
92915f71
GR		 1659 }
1660
1661 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
1662 memset(tx_ring->tx_buffer_info, 0, size);
1663
1664 memset(tx_ring->desc, 0, tx_ring->size);
1665
1666 tx_ring->next_to_use = 0;
1667 tx_ring->next_to_clean = 0;
1668
1669 if (tx_ring->head)
1670 writel(0, adapter->hw.hw_addr + tx_ring->head);
1671 if (tx_ring->tail)
1672 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1673}
1674
1675/**
1676 * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues
1677 * @adapter: board private structure
1678 **/
1679static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter)
1680{
1681 int i;
1682
1683 for (i = 0; i < adapter->num_rx_queues; i++)
1684 ixgbevf_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1685}
1686
1687/**
1688 * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues
1689 * @adapter: board private structure
1690 **/
1691static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter)
1692{
1693 int i;
1694
1695 for (i = 0; i < adapter->num_tx_queues; i++)
1696 ixgbevf_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1697}
1698
1699void ixgbevf_down(struct ixgbevf_adapter *adapter)
1700{
1701 struct net_device *netdev = adapter->netdev;
1702 struct ixgbe_hw *hw = &adapter->hw;
1703 u32 txdctl;
1704 int i, j;
1705
1706 /* signal that we are down to the interrupt handler */
1707 set_bit(__IXGBEVF_DOWN, &adapter->state);
858c3dda
DS		 1708
1709 /* disable all enabled rx queues */
1710 for (i = 0; i < adapter->num_rx_queues; i++)
1711 ixgbevf_disable_rx_queue(adapter, &adapter->rx_ring[i]);
92915f71
GR		 1712
1713 netif_tx_disable(netdev);
1714
1715 msleep(10);
1716
1717 netif_tx_stop_all_queues(netdev);
1718
1719 ixgbevf_irq_disable(adapter);
1720
1721 ixgbevf_napi_disable_all(adapter);
1722
1723 del_timer_sync(&adapter->watchdog_timer);
1724 /* can't call flush scheduled work here because it can deadlock
1725 * if linkwatch_event tries to acquire the rtnl_lock which we are
1726 * holding */
1727 while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK)
1728 msleep(1);
1729
1730 /* disable transmits in the hardware now that interrupts are off */
1731 for (i = 0; i < adapter->num_tx_queues; i++) {
1732 j = adapter->tx_ring[i].reg_idx;
1733 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1734 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j),
1735 (txdctl & ~IXGBE_TXDCTL_ENABLE));
1736 }
1737
1738 netif_carrier_off(netdev);
1739
1740 if (!pci_channel_offline(adapter->pdev))
1741 ixgbevf_reset(adapter);
1742
1743 ixgbevf_clean_all_tx_rings(adapter);
1744 ixgbevf_clean_all_rx_rings(adapter);
1745}
1746
1747void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter)
1748{
1749 WARN_ON(in_interrupt());
c0456c23 1750
92915f71
GR		 1751 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
1752 msleep(1);
1753
4b2cd27f
AD		 1754 ixgbevf_down(adapter);
1755 ixgbevf_up(adapter);
92915f71
GR		 1756
1757 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
1758}
1759
1760void ixgbevf_reset(struct ixgbevf_adapter *adapter)
1761{
1762 struct ixgbe_hw *hw = &adapter->hw;
1763 struct net_device *netdev = adapter->netdev;
1764
798e381a 1765 if (hw->mac.ops.reset_hw(hw)) {
92915f71 1766 hw_dbg(hw, "PF still resetting\n");
798e381a 1767 } else {
92915f71 1768 hw->mac.ops.init_hw(hw);
798e381a
DS		 1769 ixgbevf_negotiate_api(adapter);
1770 }
92915f71
GR		 1771
1772 if (is_valid_ether_addr(adapter->hw.mac.addr)) {
1773 memcpy(netdev->dev_addr, adapter->hw.mac.addr,
1774 netdev->addr_len);
1775 memcpy(netdev->perm_addr, adapter->hw.mac.addr,
1776 netdev->addr_len);
1777 }
1778}
1779
e45dd5fe
JK		 1780static int ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter,
1781 int vectors)
92915f71 1782{
a5f9337b
ET		 1783 int err = 0;
1784 int vector_threshold;
92915f71 1785
fa71ae27
AD		 1786 /* We'll want at least 2 (vector_threshold):
1787 * 1) TxQ[0] + RxQ[0] handler
1788 * 2) Other (Link Status Change, etc.)
92915f71
GR		 1789 */
1790 vector_threshold = MIN_MSIX_COUNT;
1791
1792 /* The more we get, the more we will assign to Tx/Rx Cleanup
1793 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1794 * Right now, we simply care about how many we'll get; we'll
1795 * set them up later while requesting irq's.
1796 */
1797 while (vectors >= vector_threshold) {
1798 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1799 vectors);
e45dd5fe 1800 if (!err || err < 0) /* Success or a nasty failure. */
92915f71 1801 break;
92915f71
GR		 1802 else /* err == number of vectors we should try again with */
1803 vectors = err;
1804 }
1805
e45dd5fe
JK		 1806 if (vectors < vector_threshold)
1807 err = -ENOMEM;
1808
1809 if (err) {
1810 dev_err(&adapter->pdev->dev,
1811 "Unable to allocate MSI-X interrupts\n");
92915f71
GR		 1812 kfree(adapter->msix_entries);
1813 adapter->msix_entries = NULL;
1814 } else {
1815 /*
1816 * Adjust for only the vectors we'll use, which is minimum
1817 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
1818 * vectors we were allocated.
1819 */
1820 adapter->num_msix_vectors = vectors;
1821 }
dee847f5 1822
e45dd5fe 1823 return err;
92915f71
GR		 1824}
1825
49ce9c2c
BH		 1826/**
1827 * ixgbevf_set_num_queues - Allocate queues for device, feature dependent
92915f71
GR		 1828 * @adapter: board private structure to initialize
1829 *
1830 * This is the top level queue allocation routine. The order here is very
1831 * important, starting with the "most" number of features turned on at once,
1832 * and ending with the smallest set of features. This way large combinations
1833 * can be allocated if they're turned on, and smaller combinations are the
1834 * fallthrough conditions.
1835 *
1836 **/
1837static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter)
1838{
1839 /* Start with base case */
1840 adapter->num_rx_queues = 1;
1841 adapter->num_tx_queues = 1;
92915f71
GR		 1842}
1843
1844/**
1845 * ixgbevf_alloc_queues - Allocate memory for all rings
1846 * @adapter: board private structure to initialize
1847 *
1848 * We allocate one ring per queue at run-time since we don't know the
1849 * number of queues at compile-time. The polling_netdev array is
1850 * intended for Multiqueue, but should work fine with a single queue.
1851 **/
1852static int ixgbevf_alloc_queues(struct ixgbevf_adapter *adapter)
1853{
1854 int i;
1855
1856 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1857 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1858 if (!adapter->tx_ring)
1859 goto err_tx_ring_allocation;
1860
1861 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1862 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1863 if (!adapter->rx_ring)
1864 goto err_rx_ring_allocation;
1865
1866 for (i = 0; i < adapter->num_tx_queues; i++) {
1867 adapter->tx_ring[i].count = adapter->tx_ring_count;
1868 adapter->tx_ring[i].queue_index = i;
56e94095 1869 /* reg_idx may be remapped later by DCB config */
92915f71 1870 adapter->tx_ring[i].reg_idx = i;
fb40195c
AD		 1871 adapter->tx_ring[i].dev = &adapter->pdev->dev;
1872 adapter->tx_ring[i].netdev = adapter->netdev;
92915f71
GR		 1873 }
1874
1875 for (i = 0; i < adapter->num_rx_queues; i++) {
1876 adapter->rx_ring[i].count = adapter->rx_ring_count;
1877 adapter->rx_ring[i].queue_index = i;
1878 adapter->rx_ring[i].reg_idx = i;
fb40195c
AD		 1879 adapter->rx_ring[i].dev = &adapter->pdev->dev;
1880 adapter->rx_ring[i].netdev = adapter->netdev;
92915f71
GR		 1881 }
1882
1883 return 0;
1884
1885err_rx_ring_allocation:
1886 kfree(adapter->tx_ring);
1887err_tx_ring_allocation:
1888 return -ENOMEM;
1889}
1890
1891/**
1892 * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported
1893 * @adapter: board private structure to initialize
1894 *
1895 * Attempt to configure the interrupts using the best available
1896 * capabilities of the hardware and the kernel.
1897 **/
1898static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter)
1899{
91e2b89b 1900 struct net_device *netdev = adapter->netdev;
92915f71
GR		 1901 int err = 0;
1902 int vector, v_budget;
1903
1904 /*
1905 * It's easy to be greedy for MSI-X vectors, but it really
1906 * doesn't do us much good if we have a lot more vectors
1907 * than CPU's. So let's be conservative and only ask for
fa71ae27
AD		 1908 * (roughly) the same number of vectors as there are CPU's.
1909 * The default is to use pairs of vectors.
92915f71 1910 */
fa71ae27
AD		 1911 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
1912 v_budget = min_t(int, v_budget, num_online_cpus());
1913 v_budget += NON_Q_VECTORS;
92915f71
GR		 1914
1915 /* A failure in MSI-X entry allocation isn't fatal, but it does
1916 * mean we disable MSI-X capabilities of the adapter. */
1917 adapter->msix_entries = kcalloc(v_budget,
1918 sizeof(struct msix_entry), GFP_KERNEL);
1919 if (!adapter->msix_entries) {
1920 err = -ENOMEM;
1921 goto out;
1922 }
1923
1924 for (vector = 0; vector < v_budget; vector++)
1925 adapter->msix_entries[vector].entry = vector;
1926
e45dd5fe
JK		 1927 err = ixgbevf_acquire_msix_vectors(adapter, v_budget);
1928 if (err)
1929 goto out;
92915f71 1930
91e2b89b
GR		 1931 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues);
1932 if (err)
1933 goto out;
1934
1935 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues);
1936
92915f71
GR		 1937out:
1938 return err;
1939}
1940
1941/**
1942 * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors
1943 * @adapter: board private structure to initialize
1944 *
1945 * We allocate one q_vector per queue interrupt. If allocation fails we
1946 * return -ENOMEM.
1947 **/
1948static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter)
1949{
1950 int q_idx, num_q_vectors;
1951 struct ixgbevf_q_vector *q_vector;
92915f71
GR		 1952
1953 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
92915f71
GR		 1954
1955 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1956 q_vector = kzalloc(sizeof(struct ixgbevf_q_vector), GFP_KERNEL);
1957 if (!q_vector)
1958 goto err_out;
1959 q_vector->adapter = adapter;
1960 q_vector->v_idx = q_idx;
fa71ae27
AD		 1961 netif_napi_add(adapter->netdev, &q_vector->napi,
1962 ixgbevf_poll, 64);
92915f71
GR		 1963 adapter->q_vector[q_idx] = q_vector;
1964 }
1965
1966 return 0;
1967
1968err_out:
1969 while (q_idx) {
1970 q_idx--;
1971 q_vector = adapter->q_vector[q_idx];
1972 netif_napi_del(&q_vector->napi);
1973 kfree(q_vector);
1974 adapter->q_vector[q_idx] = NULL;
1975 }
1976 return -ENOMEM;
1977}
1978
1979/**
1980 * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors
1981 * @adapter: board private structure to initialize
1982 *
1983 * This function frees the memory allocated to the q_vectors. In addition if
1984 * NAPI is enabled it will delete any references to the NAPI struct prior
1985 * to freeing the q_vector.
1986 **/
1987static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter)
1988{
f4477702 1989 int q_idx, num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
92915f71
GR		 1990
1991 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1992 struct ixgbevf_q_vector *q_vector = adapter->q_vector[q_idx];
1993
1994 adapter->q_vector[q_idx] = NULL;
f4477702 1995 netif_napi_del(&q_vector->napi);
92915f71
GR		 1996 kfree(q_vector);
1997 }
1998}
1999
2000/**
2001 * ixgbevf_reset_interrupt_capability - Reset MSIX setup
2002 * @adapter: board private structure
2003 *
2004 **/
2005static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter)
2006{
2007 pci_disable_msix(adapter->pdev);
2008 kfree(adapter->msix_entries);
2009 adapter->msix_entries = NULL;
92915f71
GR		 2010}
2011
2012/**
2013 * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init
2014 * @adapter: board private structure to initialize
2015 *
2016 **/
2017static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter)
2018{
2019 int err;
2020
2021 /* Number of supported queues */
2022 ixgbevf_set_num_queues(adapter);
2023
2024 err = ixgbevf_set_interrupt_capability(adapter);
2025 if (err) {
2026 hw_dbg(&adapter->hw,
2027 "Unable to setup interrupt capabilities\n");
2028 goto err_set_interrupt;
2029 }
2030
2031 err = ixgbevf_alloc_q_vectors(adapter);
2032 if (err) {
2033 hw_dbg(&adapter->hw, "Unable to allocate memory for queue "
2034 "vectors\n");
2035 goto err_alloc_q_vectors;
2036 }
2037
2038 err = ixgbevf_alloc_queues(adapter);
2039 if (err) {
dbd9636e 2040 pr_err("Unable to allocate memory for queues\n");
92915f71
GR		 2041 goto err_alloc_queues;
2042 }
2043
2044 hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, "
2045 "Tx Queue count = %u\n",
2046 (adapter->num_rx_queues > 1) ? "Enabled" :
2047 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2048
2049 set_bit(__IXGBEVF_DOWN, &adapter->state);
2050
2051 return 0;
2052err_alloc_queues:
2053 ixgbevf_free_q_vectors(adapter);
2054err_alloc_q_vectors:
2055 ixgbevf_reset_interrupt_capability(adapter);
2056err_set_interrupt:
2057 return err;
2058}
2059
0ac1e8ce
AD		 2060/**
2061 * ixgbevf_clear_interrupt_scheme - Clear the current interrupt scheme settings
2062 * @adapter: board private structure to clear interrupt scheme on
2063 *
2064 * We go through and clear interrupt specific resources and reset the structure
2065 * to pre-load conditions
2066 **/
2067static void ixgbevf_clear_interrupt_scheme(struct ixgbevf_adapter *adapter)
2068{
2069 adapter->num_tx_queues = 0;
2070 adapter->num_rx_queues = 0;
2071
2072 ixgbevf_free_q_vectors(adapter);
2073 ixgbevf_reset_interrupt_capability(adapter);
2074}
2075
92915f71
GR		 2076/**
2077 * ixgbevf_sw_init - Initialize general software structures
2078 * (struct ixgbevf_adapter)
2079 * @adapter: board private structure to initialize
2080 *
2081 * ixgbevf_sw_init initializes the Adapter private data structure.
2082 * Fields are initialized based on PCI device information and
2083 * OS network device settings (MTU size).
2084 **/
9f9a12f8 2085static int ixgbevf_sw_init(struct ixgbevf_adapter *adapter)
92915f71
GR		 2086{
2087 struct ixgbe_hw *hw = &adapter->hw;
2088 struct pci_dev *pdev = adapter->pdev;
e1941a74 2089 struct net_device *netdev = adapter->netdev;
92915f71
GR		 2090 int err;
2091
2092 /* PCI config space info */
2093
2094 hw->vendor_id = pdev->vendor;
2095 hw->device_id = pdev->device;
ff938e43 2096 hw->revision_id = pdev->revision;
92915f71
GR		 2097 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2098 hw->subsystem_device_id = pdev->subsystem_device;
2099
2100 hw->mbx.ops.init_params(hw);
56e94095
AD		 2101
2102 /* assume legacy case in which PF would only give VF 2 queues */
2103 hw->mac.max_tx_queues = 2;
2104 hw->mac.max_rx_queues = 2;
2105
798e381a
DS		 2106 /* lock to protect mailbox accesses */
2107 spin_lock_init(&adapter->mbx_lock);
2108
92915f71
GR		 2109 err = hw->mac.ops.reset_hw(hw);
2110 if (err) {
2111 dev_info(&pdev->dev,
e1941a74 2112 "PF still in reset state. Is the PF interface up?\n");
92915f71
GR		 2113 } else {
2114 err = hw->mac.ops.init_hw(hw);
2115 if (err) {
dbd9636e 2116 pr_err("init_shared_code failed: %d\n", err);
92915f71
GR		 2117 goto out;
2118 }
798e381a 2119 ixgbevf_negotiate_api(adapter);
e1941a74
GR		 2120 err = hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2121 if (err)
2122 dev_info(&pdev->dev, "Error reading MAC address\n");
2123 else if (is_zero_ether_addr(adapter->hw.mac.addr))
2124 dev_info(&pdev->dev,
2125 "MAC address not assigned by administrator.\n");
2126 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2127 }
2128
2129 if (!is_valid_ether_addr(netdev->dev_addr)) {
2130 dev_info(&pdev->dev, "Assigning random MAC address\n");
2131 eth_hw_addr_random(netdev);
2132 memcpy(hw->mac.addr, netdev->dev_addr, netdev->addr_len);
92915f71
GR		 2133 }
2134
2135 /* Enable dynamic interrupt throttling rates */
5f3600eb
AD		 2136 adapter->rx_itr_setting = 1;
2137 adapter->tx_itr_setting = 1;
92915f71 2138
92915f71
GR		 2139 /* set default ring sizes */
2140 adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD;
2141 adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD;
2142
92915f71 2143 set_bit(__IXGBEVF_DOWN, &adapter->state);
1a0d6ae5 2144 return 0;
92915f71
GR		 2145
2146out:
2147 return err;
2148}
2149
92915f71
GR		 2150#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
2151 { \
2152 u32 current_counter = IXGBE_READ_REG(hw, reg); \
2153 if (current_counter < last_counter) \
2154 counter += 0x100000000LL; \
2155 last_counter = current_counter; \
2156 counter &= 0xFFFFFFFF00000000LL; \
2157 counter |= current_counter; \
2158 }
2159
2160#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2161 { \
2162 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
2163 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
2164 u64 current_counter = (current_counter_msb << 32) | \
2165 current_counter_lsb; \
2166 if (current_counter < last_counter) \
2167 counter += 0x1000000000LL; \
2168 last_counter = current_counter; \
2169 counter &= 0xFFFFFFF000000000LL; \
2170 counter |= current_counter; \
2171 }
2172/**
2173 * ixgbevf_update_stats - Update the board statistics counters.
2174 * @adapter: board private structure
2175 **/
2176void ixgbevf_update_stats(struct ixgbevf_adapter *adapter)
2177{
2178 struct ixgbe_hw *hw = &adapter->hw;
55fb277c 2179 int i;
92915f71 2180
088245a3
GR		 2181 if (!adapter->link_up)
2182 return;
2183
92915f71
GR		 2184 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc,
2185 adapter->stats.vfgprc);
2186 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc,
2187 adapter->stats.vfgptc);
2188 UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2189 adapter->stats.last_vfgorc,
2190 adapter->stats.vfgorc);
2191 UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2192 adapter->stats.last_vfgotc,
2193 adapter->stats.vfgotc);
2194 UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc,
2195 adapter->stats.vfmprc);
55fb277c
GR		 2196
2197 for (i = 0; i < adapter->num_rx_queues; i++) {
2198 adapter->hw_csum_rx_error +=
2199 adapter->rx_ring[i].hw_csum_rx_error;
2200 adapter->hw_csum_rx_good +=
2201 adapter->rx_ring[i].hw_csum_rx_good;
2202 adapter->rx_ring[i].hw_csum_rx_error = 0;
2203 adapter->rx_ring[i].hw_csum_rx_good = 0;
2204 }
92915f71
GR		 2205}
2206
2207/**
2208 * ixgbevf_watchdog - Timer Call-back
2209 * @data: pointer to adapter cast into an unsigned long
2210 **/
2211static void ixgbevf_watchdog(unsigned long data)
2212{
2213 struct ixgbevf_adapter *adapter = (struct ixgbevf_adapter *)data;
2214 struct ixgbe_hw *hw = &adapter->hw;
5f3600eb 2215 u32 eics = 0;
92915f71
GR		 2216 int i;
2217
2218 /*
2219 * Do the watchdog outside of interrupt context due to the lovely
2220 * delays that some of the newer hardware requires
2221 */
2222
2223 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
2224 goto watchdog_short_circuit;
2225
2226 /* get one bit for every active tx/rx interrupt vector */
2227 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
2228 struct ixgbevf_q_vector *qv = adapter->q_vector[i];
6b43c446 2229 if (qv->rx.ring || qv->tx.ring)
5f3600eb 2230 eics |= 1 << i;
92915f71
GR		 2231 }
2232
5f3600eb 2233 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, eics);
92915f71
GR		 2234
2235watchdog_short_circuit:
2236 schedule_work(&adapter->watchdog_task);
2237}
2238
2239/**
2240 * ixgbevf_tx_timeout - Respond to a Tx Hang
2241 * @netdev: network interface device structure
2242 **/
2243static void ixgbevf_tx_timeout(struct net_device *netdev)
2244{
2245 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2246
2247 /* Do the reset outside of interrupt context */
2248 schedule_work(&adapter->reset_task);
2249}
2250
2251static void ixgbevf_reset_task(struct work_struct *work)
2252{
2253 struct ixgbevf_adapter *adapter;
2254 adapter = container_of(work, struct ixgbevf_adapter, reset_task);
2255
2256 /* If we're already down or resetting, just bail */
2257 if (test_bit(__IXGBEVF_DOWN, &adapter->state) ||
2258 test_bit(__IXGBEVF_RESETTING, &adapter->state))
2259 return;
2260
2261 adapter->tx_timeout_count++;
2262
2263 ixgbevf_reinit_locked(adapter);
2264}
2265
2266/**
2267 * ixgbevf_watchdog_task - worker thread to bring link up
2268 * @work: pointer to work_struct containing our data
2269 **/
2270static void ixgbevf_watchdog_task(struct work_struct *work)
2271{
2272 struct ixgbevf_adapter *adapter = container_of(work,
2273 struct ixgbevf_adapter,
2274 watchdog_task);
2275 struct net_device *netdev = adapter->netdev;
2276 struct ixgbe_hw *hw = &adapter->hw;
2277 u32 link_speed = adapter->link_speed;
2278 bool link_up = adapter->link_up;
92fe0bf7 2279 s32 need_reset;
92915f71
GR		 2280
2281 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
2282
2283 /*
2284 * Always check the link on the watchdog because we have
2285 * no LSC interrupt
2286 */
92fe0bf7 2287 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 2288
92fe0bf7 2289 need_reset = hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1c55ed76 2290
92fe0bf7 2291 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 2292
92fe0bf7
GR		 2293 if (need_reset) {
2294 adapter->link_up = link_up;
2295 adapter->link_speed = link_speed;
2296 netif_carrier_off(netdev);
2297 netif_tx_stop_all_queues(netdev);
2298 schedule_work(&adapter->reset_task);
2299 goto pf_has_reset;
92915f71
GR		 2300 }
2301 adapter->link_up = link_up;
2302 adapter->link_speed = link_speed;
2303
2304 if (link_up) {
2305 if (!netif_carrier_ok(netdev)) {
b876a744
GR		 2306 char *link_speed_string;
2307 switch (link_speed) {
2308 case IXGBE_LINK_SPEED_10GB_FULL:
2309 link_speed_string = "10 Gbps";
2310 break;
2311 case IXGBE_LINK_SPEED_1GB_FULL:
2312 link_speed_string = "1 Gbps";
2313 break;
2314 case IXGBE_LINK_SPEED_100_FULL:
2315 link_speed_string = "100 Mbps";
2316 break;
2317 default:
2318 link_speed_string = "unknown speed";
2319 break;
2320 }
6fe59675 2321 dev_info(&adapter->pdev->dev,
b876a744 2322 "NIC Link is Up, %s\n", link_speed_string);
92915f71
GR		 2323 netif_carrier_on(netdev);
2324 netif_tx_wake_all_queues(netdev);
92915f71
GR		 2325 }
2326 } else {
2327 adapter->link_up = false;
2328 adapter->link_speed = 0;
2329 if (netif_carrier_ok(netdev)) {
6fe59675 2330 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
92915f71
GR		 2331 netif_carrier_off(netdev);
2332 netif_tx_stop_all_queues(netdev);
2333 }
2334 }
2335
92915f71
GR		 2336 ixgbevf_update_stats(adapter);
2337
33bd9f60 2338pf_has_reset:
92915f71
GR		 2339 /* Reset the timer */
2340 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
2341 mod_timer(&adapter->watchdog_timer,
2342 round_jiffies(jiffies + (2 * HZ)));
2343
2344 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
2345}
2346
2347/**
2348 * ixgbevf_free_tx_resources - Free Tx Resources per Queue
2349 * @adapter: board private structure
2350 * @tx_ring: Tx descriptor ring for a specific queue
2351 *
2352 * Free all transmit software resources
2353 **/
2354void ixgbevf_free_tx_resources(struct ixgbevf_adapter *adapter,
2355 struct ixgbevf_ring *tx_ring)
2356{
2357 struct pci_dev *pdev = adapter->pdev;
2358
92915f71
GR		 2359 ixgbevf_clean_tx_ring(adapter, tx_ring);
2360
2361 vfree(tx_ring->tx_buffer_info);
2362 tx_ring->tx_buffer_info = NULL;
2363
2a1f8794
NN		 2364 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2365 tx_ring->dma);
92915f71
GR		 2366
2367 tx_ring->desc = NULL;
2368}
2369
2370/**
2371 * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues
2372 * @adapter: board private structure
2373 *
2374 * Free all transmit software resources
2375 **/
2376static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter)
2377{
2378 int i;
2379
2380 for (i = 0; i < adapter->num_tx_queues; i++)
2381 if (adapter->tx_ring[i].desc)
2382 ixgbevf_free_tx_resources(adapter,
2383 &adapter->tx_ring[i]);
2384
2385}
2386
2387/**
2388 * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors)
2389 * @adapter: board private structure
2390 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2391 *
2392 * Return 0 on success, negative on failure
2393 **/
2394int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *adapter,
2395 struct ixgbevf_ring *tx_ring)
2396{
2397 struct pci_dev *pdev = adapter->pdev;
2398 int size;
2399
2400 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
89bf67f1 2401 tx_ring->tx_buffer_info = vzalloc(size);
92915f71
GR		 2402 if (!tx_ring->tx_buffer_info)
2403 goto err;
92915f71
GR		 2404
2405 /* round up to nearest 4K */
2406 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2407 tx_ring->size = ALIGN(tx_ring->size, 4096);
2408
2a1f8794
NN		 2409 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
2410 &tx_ring->dma, GFP_KERNEL);
92915f71
GR		 2411 if (!tx_ring->desc)
2412 goto err;
2413
2414 tx_ring->next_to_use = 0;
2415 tx_ring->next_to_clean = 0;
92915f71
GR		 2416 return 0;
2417
2418err:
2419 vfree(tx_ring->tx_buffer_info);
2420 tx_ring->tx_buffer_info = NULL;
2421 hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit "
2422 "descriptor ring\n");
2423 return -ENOMEM;
2424}
2425
2426/**
2427 * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources
2428 * @adapter: board private structure
2429 *
2430 * If this function returns with an error, then it's possible one or
2431 * more of the rings is populated (while the rest are not). It is the
2432 * callers duty to clean those orphaned rings.
2433 *
2434 * Return 0 on success, negative on failure
2435 **/
2436static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter)
2437{
2438 int i, err = 0;
2439
2440 for (i = 0; i < adapter->num_tx_queues; i++) {
2441 err = ixgbevf_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2442 if (!err)
2443 continue;
2444 hw_dbg(&adapter->hw,
2445 "Allocation for Tx Queue %u failed\n", i);
2446 break;
2447 }
2448
2449 return err;
2450}
2451
2452/**
2453 * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors)
2454 * @adapter: board private structure
2455 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2456 *
2457 * Returns 0 on success, negative on failure
2458 **/
2459int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
2460 struct ixgbevf_ring *rx_ring)
2461{
2462 struct pci_dev *pdev = adapter->pdev;
2463 int size;
2464
2465 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
89bf67f1 2466 rx_ring->rx_buffer_info = vzalloc(size);
e404decb 2467 if (!rx_ring->rx_buffer_info)
92915f71 2468 goto alloc_failed;
92915f71
GR		 2469
2470 /* Round up to nearest 4K */
2471 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2472 rx_ring->size = ALIGN(rx_ring->size, 4096);
2473
2a1f8794
NN		 2474 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
2475 &rx_ring->dma, GFP_KERNEL);
92915f71
GR		 2476
2477 if (!rx_ring->desc) {
92915f71
GR		 2478 vfree(rx_ring->rx_buffer_info);
2479 rx_ring->rx_buffer_info = NULL;
2480 goto alloc_failed;
2481 }
2482
2483 rx_ring->next_to_clean = 0;
2484 rx_ring->next_to_use = 0;
2485
2486 return 0;
2487alloc_failed:
2488 return -ENOMEM;
2489}
2490
2491/**
2492 * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources
2493 * @adapter: board private structure
2494 *
2495 * If this function returns with an error, then it's possible one or
2496 * more of the rings is populated (while the rest are not). It is the
2497 * callers duty to clean those orphaned rings.
2498 *
2499 * Return 0 on success, negative on failure
2500 **/
2501static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter)
2502{
2503 int i, err = 0;
2504
2505 for (i = 0; i < adapter->num_rx_queues; i++) {
2506 err = ixgbevf_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2507 if (!err)
2508 continue;
2509 hw_dbg(&adapter->hw,
2510 "Allocation for Rx Queue %u failed\n", i);
2511 break;
2512 }
2513 return err;
2514}
2515
2516/**
2517 * ixgbevf_free_rx_resources - Free Rx Resources
2518 * @adapter: board private structure
2519 * @rx_ring: ring to clean the resources from
2520 *
2521 * Free all receive software resources
2522 **/
2523void ixgbevf_free_rx_resources(struct ixgbevf_adapter *adapter,
2524 struct ixgbevf_ring *rx_ring)
2525{
2526 struct pci_dev *pdev = adapter->pdev;
2527
2528 ixgbevf_clean_rx_ring(adapter, rx_ring);
2529
2530 vfree(rx_ring->rx_buffer_info);
2531 rx_ring->rx_buffer_info = NULL;
2532
2a1f8794
NN		 2533 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2534 rx_ring->dma);
92915f71
GR		 2535
2536 rx_ring->desc = NULL;
2537}
2538
2539/**
2540 * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues
2541 * @adapter: board private structure
2542 *
2543 * Free all receive software resources
2544 **/
2545static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter)
2546{
2547 int i;
2548
2549 for (i = 0; i < adapter->num_rx_queues; i++)
2550 if (adapter->rx_ring[i].desc)
2551 ixgbevf_free_rx_resources(adapter,
2552 &adapter->rx_ring[i]);
2553}
2554
56e94095
AD		 2555static int ixgbevf_setup_queues(struct ixgbevf_adapter *adapter)
2556{
2557 struct ixgbe_hw *hw = &adapter->hw;
2558 struct ixgbevf_ring *rx_ring;
2559 unsigned int def_q = 0;
2560 unsigned int num_tcs = 0;
2561 unsigned int num_rx_queues = 1;
2562 int err, i;
2563
55fdd45b 2564 spin_lock_bh(&adapter->mbx_lock);
56e94095
AD		 2565
2566 /* fetch queue configuration from the PF */
2567 err = ixgbevf_get_queues(hw, &num_tcs, &def_q);
2568
55fdd45b 2569 spin_unlock_bh(&adapter->mbx_lock);
56e94095
AD		 2570
2571 if (err)
2572 return err;
2573
2574 if (num_tcs > 1) {
2575 /* update default Tx ring register index */
2576 adapter->tx_ring[0].reg_idx = def_q;
2577
2578 /* we need as many queues as traffic classes */
2579 num_rx_queues = num_tcs;
2580 }
2581
2582 /* nothing to do if we have the correct number of queues */
2583 if (adapter->num_rx_queues == num_rx_queues)
2584 return 0;
2585
2586 /* allocate new rings */
2587 rx_ring = kcalloc(num_rx_queues,
2588 sizeof(struct ixgbevf_ring), GFP_KERNEL);
2589 if (!rx_ring)
2590 return -ENOMEM;
2591
2592 /* setup ring fields */
2593 for (i = 0; i < num_rx_queues; i++) {
2594 rx_ring[i].count = adapter->rx_ring_count;
2595 rx_ring[i].queue_index = i;
2596 rx_ring[i].reg_idx = i;
2597 rx_ring[i].dev = &adapter->pdev->dev;
2598 rx_ring[i].netdev = adapter->netdev;
2599 }
2600
2601 /* free the existing ring and queues */
2602 adapter->num_rx_queues = 0;
2603 kfree(adapter->rx_ring);
2604
2605 /* move new rings into position on the adapter struct */
2606 adapter->rx_ring = rx_ring;
2607 adapter->num_rx_queues = num_rx_queues;
2608
2609 return 0;
2610}
2611
92915f71
GR		 2612/**
2613 * ixgbevf_open - Called when a network interface is made active
2614 * @netdev: network interface device structure
2615 *
2616 * Returns 0 on success, negative value on failure
2617 *
2618 * The open entry point is called when a network interface is made
2619 * active by the system (IFF_UP). At this point all resources needed
2620 * for transmit and receive operations are allocated, the interrupt
2621 * handler is registered with the OS, the watchdog timer is started,
2622 * and the stack is notified that the interface is ready.
2623 **/
2624static int ixgbevf_open(struct net_device *netdev)
2625{
2626 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2627 struct ixgbe_hw *hw = &adapter->hw;
2628 int err;
2629
a1f6c6b1 2630 /* A previous failure to open the device because of a lack of
2631 * available MSIX vector resources may have reset the number
2632 * of msix vectors variable to zero. The only way to recover
2633 * is to unload/reload the driver and hope that the system has
2634 * been able to recover some MSIX vector resources.
2635 */
2636 if (!adapter->num_msix_vectors)
2637 return -ENOMEM;
2638
92915f71
GR		 2639 /* disallow open during test */
2640 if (test_bit(__IXGBEVF_TESTING, &adapter->state))
2641 return -EBUSY;
2642
2643 if (hw->adapter_stopped) {
2644 ixgbevf_reset(adapter);
2645 /* if adapter is still stopped then PF isn't up and
2646 * the vf can't start. */
2647 if (hw->adapter_stopped) {
2648 err = IXGBE_ERR_MBX;
dbd9636e
JK		 2649 pr_err("Unable to start - perhaps the PF Driver isn't "
2650 "up yet\n");
92915f71
GR		 2651 goto err_setup_reset;
2652 }
2653 }
2654
56e94095
AD		 2655 /* setup queue reg_idx and Rx queue count */
2656 err = ixgbevf_setup_queues(adapter);
2657 if (err)
2658 goto err_setup_queues;
2659
92915f71
GR		 2660 /* allocate transmit descriptors */
2661 err = ixgbevf_setup_all_tx_resources(adapter);
2662 if (err)
2663 goto err_setup_tx;
2664
2665 /* allocate receive descriptors */
2666 err = ixgbevf_setup_all_rx_resources(adapter);
2667 if (err)
2668 goto err_setup_rx;
2669
2670 ixgbevf_configure(adapter);
2671
2672 /*
2673 * Map the Tx/Rx rings to the vectors we were allotted.
2674 * if request_irq will be called in this function map_rings
2675 * must be called *before* up_complete
2676 */
2677 ixgbevf_map_rings_to_vectors(adapter);
2678
795180d8 2679 ixgbevf_up_complete(adapter);
92915f71
GR		 2680
2681 /* clear any pending interrupts, may auto mask */
2682 IXGBE_READ_REG(hw, IXGBE_VTEICR);
2683 err = ixgbevf_request_irq(adapter);
2684 if (err)
2685 goto err_req_irq;
2686
5f3600eb 2687 ixgbevf_irq_enable(adapter);
92915f71
GR		 2688
2689 return 0;
2690
2691err_req_irq:
2692 ixgbevf_down(adapter);
92915f71
GR		 2693err_setup_rx:
2694 ixgbevf_free_all_rx_resources(adapter);
2695err_setup_tx:
2696 ixgbevf_free_all_tx_resources(adapter);
56e94095 2697err_setup_queues:
92915f71
GR		 2698 ixgbevf_reset(adapter);
2699
2700err_setup_reset:
2701
2702 return err;
2703}
2704
2705/**
2706 * ixgbevf_close - Disables a network interface
2707 * @netdev: network interface device structure
2708 *
2709 * Returns 0, this is not allowed to fail
2710 *
2711 * The close entry point is called when an interface is de-activated
2712 * by the OS. The hardware is still under the drivers control, but
2713 * needs to be disabled. A global MAC reset is issued to stop the
2714 * hardware, and all transmit and receive resources are freed.
2715 **/
2716static int ixgbevf_close(struct net_device *netdev)
2717{
2718 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2719
2720 ixgbevf_down(adapter);
2721 ixgbevf_free_irq(adapter);
2722
2723 ixgbevf_free_all_tx_resources(adapter);
2724 ixgbevf_free_all_rx_resources(adapter);
2725
2726 return 0;
2727}
2728
70a10e25
AD		 2729static void ixgbevf_tx_ctxtdesc(struct ixgbevf_ring *tx_ring,
2730 u32 vlan_macip_lens, u32 type_tucmd,
2731 u32 mss_l4len_idx)
92915f71
GR		 2732{
2733 struct ixgbe_adv_tx_context_desc *context_desc;
70a10e25 2734 u16 i = tx_ring->next_to_use;
92915f71 2735
70a10e25 2736 context_desc = IXGBEVF_TX_CTXTDESC(tx_ring, i);
92915f71 2737
70a10e25
AD		 2738 i++;
2739 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
92915f71 2740
70a10e25
AD		 2741 /* set bits to identify this as an advanced context descriptor */
2742 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
92915f71 2743
70a10e25
AD		 2744 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2745 context_desc->seqnum_seed = 0;
2746 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
2747 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2748}
2749
2750static int ixgbevf_tso(struct ixgbevf_ring *tx_ring,
2751 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2752{
2753 u32 vlan_macip_lens, type_tucmd;
2754 u32 mss_l4len_idx, l4len;
2755
2756 if (!skb_is_gso(skb))
2757 return 0;
92915f71 2758
70a10e25
AD		 2759 if (skb_header_cloned(skb)) {
2760 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2761 if (err)
2762 return err;
92915f71
GR		 2763 }
2764
70a10e25
AD		 2765 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2766 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
2767
2768 if (skb->protocol == htons(ETH_P_IP)) {
2769 struct iphdr *iph = ip_hdr(skb);
2770 iph->tot_len = 0;
2771 iph->check = 0;
2772 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2773 iph->daddr, 0,
2774 IPPROTO_TCP,
2775 0);
2776 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
2777 } else if (skb_is_gso_v6(skb)) {
2778 ipv6_hdr(skb)->payload_len = 0;
2779 tcp_hdr(skb)->check =
2780 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2781 &ipv6_hdr(skb)->daddr,
2782 0, IPPROTO_TCP, 0);
2783 }
2784
2785 /* compute header lengths */
2786 l4len = tcp_hdrlen(skb);
2787 *hdr_len += l4len;
2788 *hdr_len = skb_transport_offset(skb) + l4len;
2789
2790 /* mss_l4len_id: use 1 as index for TSO */
2791 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
2792 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
2793 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
2794
2795 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
2796 vlan_macip_lens = skb_network_header_len(skb);
2797 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
2798 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
2799
2800 ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens,
2801 type_tucmd, mss_l4len_idx);
2802
2803 return 1;
92915f71
GR		 2804}
2805
70a10e25 2806static bool ixgbevf_tx_csum(struct ixgbevf_ring *tx_ring,
92915f71
GR		 2807 struct sk_buff *skb, u32 tx_flags)
2808{
70a10e25
AD		 2809 u32 vlan_macip_lens = 0;
2810 u32 mss_l4len_idx = 0;
2811 u32 type_tucmd = 0;
92915f71 2812
70a10e25
AD		 2813 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2814 u8 l4_hdr = 0;
2815 switch (skb->protocol) {
2816 case __constant_htons(ETH_P_IP):
2817 vlan_macip_lens |= skb_network_header_len(skb);
2818 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
2819 l4_hdr = ip_hdr(skb)->protocol;
2820 break;
2821 case __constant_htons(ETH_P_IPV6):
2822 vlan_macip_lens |= skb_network_header_len(skb);
2823 l4_hdr = ipv6_hdr(skb)->nexthdr;
2824 break;
2825 default:
2826 if (unlikely(net_ratelimit())) {
2827 dev_warn(tx_ring->dev,
2828 "partial checksum but proto=%x!\n",
2829 skb->protocol);
2830 }
2831 break;
2832 }
92915f71 2833
70a10e25
AD		 2834 switch (l4_hdr) {
2835 case IPPROTO_TCP:
2836 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2837 mss_l4len_idx = tcp_hdrlen(skb) <<
2838 IXGBE_ADVTXD_L4LEN_SHIFT;
2839 break;
2840 case IPPROTO_SCTP:
2841 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
2842 mss_l4len_idx = sizeof(struct sctphdr) <<
2843 IXGBE_ADVTXD_L4LEN_SHIFT;
2844 break;
2845 case IPPROTO_UDP:
2846 mss_l4len_idx = sizeof(struct udphdr) <<
2847 IXGBE_ADVTXD_L4LEN_SHIFT;
2848 break;
2849 default:
2850 if (unlikely(net_ratelimit())) {
2851 dev_warn(tx_ring->dev,
2852 "partial checksum but l4 proto=%x!\n",
2853 l4_hdr);
2854 }
2855 break;
2856 }
92915f71
GR		 2857 }
2858
70a10e25
AD		 2859 /* vlan_macip_lens: MACLEN, VLAN tag */
2860 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
2861 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
2862
2863 ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens,
2864 type_tucmd, mss_l4len_idx);
2865
2866 return (skb->ip_summed == CHECKSUM_PARTIAL);
92915f71
GR		 2867}
2868
70a10e25 2869static int ixgbevf_tx_map(struct ixgbevf_ring *tx_ring,
e757e3e1 2870 struct sk_buff *skb, u32 tx_flags)
92915f71 2871{
92915f71
GR		 2872 struct ixgbevf_tx_buffer *tx_buffer_info;
2873 unsigned int len;
2874 unsigned int total = skb->len;
2540ddb5
KV		 2875 unsigned int offset = 0, size;
2876 int count = 0;
92915f71
GR		 2877 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2878 unsigned int f;
65deeed7 2879 int i;
92915f71
GR		 2880
2881 i = tx_ring->next_to_use;
2882
2883 len = min(skb_headlen(skb), total);
2884 while (len) {
2885 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2886 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2887
2888 tx_buffer_info->length = size;
2889 tx_buffer_info->mapped_as_page = false;
70a10e25 2890 tx_buffer_info->dma = dma_map_single(tx_ring->dev,
92915f71 2891 skb->data + offset,
2a1f8794 2892 size, DMA_TO_DEVICE);
70a10e25 2893 if (dma_mapping_error(tx_ring->dev, tx_buffer_info->dma))
92915f71 2894 goto dma_error;
92915f71
GR		 2895
2896 len -= size;
2897 total -= size;
2898 offset += size;
2899 count++;
2900 i++;
2901 if (i == tx_ring->count)
2902 i = 0;
2903 }
2904
2905 for (f = 0; f < nr_frags; f++) {
9e903e08 2906 const struct skb_frag_struct *frag;
92915f71
GR		 2907
2908 frag = &skb_shinfo(skb)->frags[f];
9e903e08 2909 len = min((unsigned int)skb_frag_size(frag), total);
877749bf 2910 offset = 0;
92915f71
GR		 2911
2912 while (len) {
2913 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2914 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2915
2916 tx_buffer_info->length = size;
877749bf 2917 tx_buffer_info->dma =
70a10e25 2918 skb_frag_dma_map(tx_ring->dev, frag,
877749bf 2919 offset, size, DMA_TO_DEVICE);
70a10e25
AD		 2920 if (dma_mapping_error(tx_ring->dev,
2921 tx_buffer_info->dma))
92915f71 2922 goto dma_error;
6132ee8a 2923 tx_buffer_info->mapped_as_page = true;
92915f71
GR		 2924
2925 len -= size;
2926 total -= size;
2927 offset += size;
2928 count++;
2929 i++;
2930 if (i == tx_ring->count)
2931 i = 0;
2932 }
2933 if (total == 0)
2934 break;
2935 }
2936
2937 if (i == 0)
2938 i = tx_ring->count - 1;
2939 else
2940 i = i - 1;
2941 tx_ring->tx_buffer_info[i].skb = skb;
92915f71
GR		 2942
2943 return count;
2944
2945dma_error:
70a10e25 2946 dev_err(tx_ring->dev, "TX DMA map failed\n");
92915f71
GR		 2947
2948 /* clear timestamp and dma mappings for failed tx_buffer_info map */
2949 tx_buffer_info->dma = 0;
92915f71
GR		 2950 count--;
2951
2952 /* clear timestamp and dma mappings for remaining portion of packet */
2953 while (count >= 0) {
2954 count--;
2955 i--;
2956 if (i < 0)
2957 i += tx_ring->count;
2958 tx_buffer_info = &tx_ring->tx_buffer_info[i];
70a10e25 2959 ixgbevf_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
92915f71
GR		 2960 }
2961
2962 return count;
2963}
2964
70a10e25 2965static void ixgbevf_tx_queue(struct ixgbevf_ring *tx_ring, int tx_flags,
e757e3e1
AD		 2966 int count, unsigned int first, u32 paylen,
2967 u8 hdr_len)
92915f71
GR		 2968{
2969 union ixgbe_adv_tx_desc *tx_desc = NULL;
2970 struct ixgbevf_tx_buffer *tx_buffer_info;
2971 u32 olinfo_status = 0, cmd_type_len = 0;
2972 unsigned int i;
2973
2974 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
2975
2976 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
2977
2978 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
2979
2980 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2981 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
2982
70a10e25
AD		 2983 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
2984 olinfo_status |= IXGBE_ADVTXD_POPTS_TXSM;
2985
92915f71
GR		 2986 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
2987 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
2988
92915f71
GR		 2989 /* use index 1 context for tso */
2990 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
2991 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
70a10e25 2992 olinfo_status |= IXGBE_ADVTXD_POPTS_IXSM;
70a10e25 2993 }
92915f71 2994
70a10e25
AD		 2995 /*
2996 * Check Context must be set if Tx switch is enabled, which it
2997 * always is for case where virtual functions are running
2998 */
2999 olinfo_status |= IXGBE_ADVTXD_CC;
92915f71
GR		 3000
3001 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3002
3003 i = tx_ring->next_to_use;
3004 while (count--) {
3005 tx_buffer_info = &tx_ring->tx_buffer_info[i];
908421f6 3006 tx_desc = IXGBEVF_TX_DESC(tx_ring, i);
92915f71
GR		 3007 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3008 tx_desc->read.cmd_type_len =
3009 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3010 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3011 i++;
3012 if (i == tx_ring->count)
3013 i = 0;
3014 }
3015
3016 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3017
e757e3e1
AD		 3018 tx_ring->tx_buffer_info[first].time_stamp = jiffies;
3019
3020 /* Force memory writes to complete before letting h/w
3021 * know there are new descriptors to fetch. (Only
3022 * applicable for weak-ordered memory model archs,
3023 * such as IA-64).
3024 */
3025 wmb();
3026
3027 tx_ring->tx_buffer_info[first].next_to_watch = tx_desc;
92915f71 3028 tx_ring->next_to_use = i;
92915f71
GR		 3029}
3030
fb40195c 3031static int __ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size)
92915f71 3032{
fb40195c 3033 struct ixgbevf_adapter *adapter = netdev_priv(tx_ring->netdev);
92915f71 3034
fb40195c 3035 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
92915f71
GR		 3036 /* Herbert's original patch had:
3037 * smp_mb__after_netif_stop_queue();
3038 * but since that doesn't exist yet, just open code it. */
3039 smp_mb();
3040
3041 /* We need to check again in a case another CPU has just
3042 * made room available. */
3043 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3044 return -EBUSY;
3045
3046 /* A reprieve! - use start_queue because it doesn't call schedule */
fb40195c 3047 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
92915f71
GR		 3048 ++adapter->restart_queue;
3049 return 0;
3050}
3051
fb40195c 3052static int ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size)
92915f71
GR		 3053{
3054 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3055 return 0;
fb40195c 3056 return __ixgbevf_maybe_stop_tx(tx_ring, size);
92915f71
GR		 3057}
3058
3059static int ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3060{
3061 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3062 struct ixgbevf_ring *tx_ring;
3063 unsigned int first;
3064 unsigned int tx_flags = 0;
3065 u8 hdr_len = 0;
3066 int r_idx = 0, tso;
3595990a
AD		 3067 u16 count = TXD_USE_COUNT(skb_headlen(skb));
3068#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
3069 unsigned short f;
3070#endif
f9d08f16 3071 u8 *dst_mac = skb_header_pointer(skb, 0, 0, NULL);
46acc460 3072 if (!dst_mac || is_link_local_ether_addr(dst_mac)) {
f9d08f16
GR		 3073 dev_kfree_skb(skb);
3074 return NETDEV_TX_OK;
3075 }
92915f71
GR		 3076
3077 tx_ring = &adapter->tx_ring[r_idx];
3078
3595990a
AD		 3079 /*
3080 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
3081 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
3082 * + 2 desc gap to keep tail from touching head,
3083 * + 1 desc for context descriptor,
3084 * otherwise try next time
3085 */
3086#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
3087 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3088 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3089#else
3090 count += skb_shinfo(skb)->nr_frags;
3091#endif
fb40195c 3092 if (ixgbevf_maybe_stop_tx(tx_ring, count + 3)) {
3595990a
AD		 3093 adapter->tx_busy++;
3094 return NETDEV_TX_BUSY;
3095 }
3096
eab6d18d 3097 if (vlan_tx_tag_present(skb)) {
92915f71
GR		 3098 tx_flags |= vlan_tx_tag_get(skb);
3099 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3100 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3101 }
3102
92915f71
GR		 3103 first = tx_ring->next_to_use;
3104
3105 if (skb->protocol == htons(ETH_P_IP))
3106 tx_flags |= IXGBE_TX_FLAGS_IPV4;
70a10e25 3107 tso = ixgbevf_tso(tx_ring, skb, tx_flags, &hdr_len);
92915f71
GR		 3108 if (tso < 0) {
3109 dev_kfree_skb_any(skb);
3110 return NETDEV_TX_OK;
3111 }
3112
3113 if (tso)
70a10e25
AD		 3114 tx_flags |= IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_CSUM;
3115 else if (ixgbevf_tx_csum(tx_ring, skb, tx_flags))
92915f71
GR		 3116 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3117
70a10e25 3118 ixgbevf_tx_queue(tx_ring, tx_flags,
e757e3e1
AD		 3119 ixgbevf_tx_map(tx_ring, skb, tx_flags),
3120 first, skb->len, hdr_len);
70a10e25
AD		 3121
3122 writel(tx_ring->next_to_use, adapter->hw.hw_addr + tx_ring->tail);
92915f71 3123
fb40195c 3124 ixgbevf_maybe_stop_tx(tx_ring, DESC_NEEDED);
92915f71
GR		 3125
3126 return NETDEV_TX_OK;
3127}
3128
92915f71
GR		 3129/**
3130 * ixgbevf_set_mac - Change the Ethernet Address of the NIC
3131 * @netdev: network interface device structure
3132 * @p: pointer to an address structure
3133 *
3134 * Returns 0 on success, negative on failure
3135 **/
3136static int ixgbevf_set_mac(struct net_device *netdev, void *p)
3137{
3138 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3139 struct ixgbe_hw *hw = &adapter->hw;
3140 struct sockaddr *addr = p;
3141
3142 if (!is_valid_ether_addr(addr->sa_data))
3143 return -EADDRNOTAVAIL;
3144
3145 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3146 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3147
55fdd45b 3148 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 3149
92fe0bf7 3150 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
92915f71 3151
55fdd45b 3152 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 3153
92915f71
GR		 3154 return 0;
3155}
3156
3157/**
3158 * ixgbevf_change_mtu - Change the Maximum Transfer Unit
3159 * @netdev: network interface device structure
3160 * @new_mtu: new value for maximum frame size
3161 *
3162 * Returns 0 on success, negative on failure
3163 **/
3164static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu)
3165{
3166 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3167 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
69bfbec4 3168 int max_possible_frame = MAXIMUM_ETHERNET_VLAN_SIZE;
69bfbec4 3169
56e94095
AD		 3170 switch (adapter->hw.api_version) {
3171 case ixgbe_mbox_api_11:
69bfbec4 3172 max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE;
56e94095
AD		 3173 break;
3174 default:
3175 if (adapter->hw.mac.type == ixgbe_mac_X540_vf)
3176 max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE;
3177 break;
3178 }
92915f71
GR		 3179
3180 /* MTU < 68 is an error and causes problems on some kernels */
69bfbec4 3181 if ((new_mtu < 68) || (max_frame > max_possible_frame))
92915f71
GR		 3182 return -EINVAL;
3183
3184 hw_dbg(&adapter->hw, "changing MTU from %d to %d\n",
3185 netdev->mtu, new_mtu);
3186 /* must set new MTU before calling down or up */
3187 netdev->mtu = new_mtu;
3188
3189 if (netif_running(netdev))
3190 ixgbevf_reinit_locked(adapter);
3191
3192 return 0;
3193}
3194
0ac1e8ce 3195static int ixgbevf_suspend(struct pci_dev *pdev, pm_message_t state)
92915f71
GR		 3196{
3197 struct net_device *netdev = pci_get_drvdata(pdev);
3198 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
0ac1e8ce
AD		 3199#ifdef CONFIG_PM
3200 int retval = 0;
3201#endif
92915f71
GR		 3202
3203 netif_device_detach(netdev);
3204
3205 if (netif_running(netdev)) {
0ac1e8ce 3206 rtnl_lock();
92915f71
GR		 3207 ixgbevf_down(adapter);
3208 ixgbevf_free_irq(adapter);
3209 ixgbevf_free_all_tx_resources(adapter);
3210 ixgbevf_free_all_rx_resources(adapter);
0ac1e8ce 3211 rtnl_unlock();
92915f71
GR		 3212 }
3213
0ac1e8ce 3214 ixgbevf_clear_interrupt_scheme(adapter);
92915f71 3215
0ac1e8ce
AD		 3216#ifdef CONFIG_PM
3217 retval = pci_save_state(pdev);
3218 if (retval)
3219 return retval;
92915f71 3220
0ac1e8ce 3221#endif
92915f71 3222 pci_disable_device(pdev);
0ac1e8ce
AD		 3223
3224 return 0;
3225}
3226
3227#ifdef CONFIG_PM
3228static int ixgbevf_resume(struct pci_dev *pdev)
3229{
3230 struct ixgbevf_adapter *adapter = pci_get_drvdata(pdev);
3231 struct net_device *netdev = adapter->netdev;
3232 u32 err;
3233
3234 pci_set_power_state(pdev, PCI_D0);
3235 pci_restore_state(pdev);
3236 /*
3237 * pci_restore_state clears dev->state_saved so call
3238 * pci_save_state to restore it.
3239 */
3240 pci_save_state(pdev);
3241
3242 err = pci_enable_device_mem(pdev);
3243 if (err) {
3244 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
3245 return err;
3246 }
3247 pci_set_master(pdev);
3248
798e381a
DS		 3249 ixgbevf_reset(adapter);
3250
0ac1e8ce
AD		 3251 rtnl_lock();
3252 err = ixgbevf_init_interrupt_scheme(adapter);
3253 rtnl_unlock();
3254 if (err) {
3255 dev_err(&pdev->dev, "Cannot initialize interrupts\n");
3256 return err;
3257 }
3258
0ac1e8ce
AD		 3259 if (netif_running(netdev)) {
3260 err = ixgbevf_open(netdev);
3261 if (err)
3262 return err;
3263 }
3264
3265 netif_device_attach(netdev);
3266
3267 return err;
3268}
3269
3270#endif /* CONFIG_PM */
3271static void ixgbevf_shutdown(struct pci_dev *pdev)
3272{
3273 ixgbevf_suspend(pdev, PMSG_SUSPEND);
92915f71
GR		 3274}
3275
4197aa7b
ED		 3276static struct rtnl_link_stats64 *ixgbevf_get_stats(struct net_device *netdev,
3277 struct rtnl_link_stats64 *stats)
3278{
3279 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3280 unsigned int start;
3281 u64 bytes, packets;
3282 const struct ixgbevf_ring *ring;
3283 int i;
3284
3285 ixgbevf_update_stats(adapter);
3286
3287 stats->multicast = adapter->stats.vfmprc - adapter->stats.base_vfmprc;
3288
3289 for (i = 0; i < adapter->num_rx_queues; i++) {
3290 ring = &adapter->rx_ring[i];
3291 do {
3292 start = u64_stats_fetch_begin_bh(&ring->syncp);
3293 bytes = ring->total_bytes;
3294 packets = ring->total_packets;
3295 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
3296 stats->rx_bytes += bytes;
3297 stats->rx_packets += packets;
3298 }
3299
3300 for (i = 0; i < adapter->num_tx_queues; i++) {
3301 ring = &adapter->tx_ring[i];
3302 do {
3303 start = u64_stats_fetch_begin_bh(&ring->syncp);
3304 bytes = ring->total_bytes;
3305 packets = ring->total_packets;
3306 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
3307 stats->tx_bytes += bytes;
3308 stats->tx_packets += packets;
3309 }
3310
3311 return stats;
3312}
3313
0ac1e8ce 3314static const struct net_device_ops ixgbevf_netdev_ops = {
c12db769
SH		 3315 .ndo_open = ixgbevf_open,
3316 .ndo_stop = ixgbevf_close,
3317 .ndo_start_xmit = ixgbevf_xmit_frame,
3318 .ndo_set_rx_mode = ixgbevf_set_rx_mode,
4197aa7b 3319 .ndo_get_stats64 = ixgbevf_get_stats,
92915f71 3320 .ndo_validate_addr = eth_validate_addr,
c12db769
SH		 3321 .ndo_set_mac_address = ixgbevf_set_mac,
3322 .ndo_change_mtu = ixgbevf_change_mtu,
3323 .ndo_tx_timeout = ixgbevf_tx_timeout,
c12db769
SH		 3324 .ndo_vlan_rx_add_vid = ixgbevf_vlan_rx_add_vid,
3325 .ndo_vlan_rx_kill_vid = ixgbevf_vlan_rx_kill_vid,
92915f71 3326};
92915f71
GR		 3327
3328static void ixgbevf_assign_netdev_ops(struct net_device *dev)
3329{
0ac1e8ce 3330 dev->netdev_ops = &ixgbevf_netdev_ops;
92915f71
GR		 3331 ixgbevf_set_ethtool_ops(dev);
3332 dev->watchdog_timeo = 5 * HZ;
3333}
3334
3335/**
3336 * ixgbevf_probe - Device Initialization Routine
3337 * @pdev: PCI device information struct
3338 * @ent: entry in ixgbevf_pci_tbl
3339 *
3340 * Returns 0 on success, negative on failure
3341 *
3342 * ixgbevf_probe initializes an adapter identified by a pci_dev structure.
3343 * The OS initialization, configuring of the adapter private structure,
3344 * and a hardware reset occur.
3345 **/
1dd06ae8 3346static int ixgbevf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
92915f71
GR		 3347{
3348 struct net_device *netdev;
3349 struct ixgbevf_adapter *adapter = NULL;
3350 struct ixgbe_hw *hw = NULL;
3351 const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data];
3352 static int cards_found;
3353 int err, pci_using_dac;
3354
3355 err = pci_enable_device(pdev);
3356 if (err)
3357 return err;
3358
2a1f8794
NN		 3359 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
3360 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
92915f71
GR		 3361 pci_using_dac = 1;
3362 } else {
2a1f8794 3363 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
92915f71 3364 if (err) {
2a1f8794
NN		 3365 err = dma_set_coherent_mask(&pdev->dev,
3366 DMA_BIT_MASK(32));
92915f71
GR		 3367 if (err) {
3368 dev_err(&pdev->dev, "No usable DMA "
3369 "configuration, aborting\n");
3370 goto err_dma;
3371 }
3372 }
3373 pci_using_dac = 0;
3374 }
3375
3376 err = pci_request_regions(pdev, ixgbevf_driver_name);
3377 if (err) {
3378 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3379 goto err_pci_reg;
3380 }
3381
3382 pci_set_master(pdev);
3383
92915f71
GR		 3384 netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter),
3385 MAX_TX_QUEUES);
92915f71
GR		 3386 if (!netdev) {
3387 err = -ENOMEM;
3388 goto err_alloc_etherdev;
3389 }
3390
3391 SET_NETDEV_DEV(netdev, &pdev->dev);
3392
3393 pci_set_drvdata(pdev, netdev);
3394 adapter = netdev_priv(netdev);
3395
3396 adapter->netdev = netdev;
3397 adapter->pdev = pdev;
3398 hw = &adapter->hw;
3399 hw->back = adapter;
b3f4d599 3400 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
92915f71
GR		 3401
3402 /*
3403 * call save state here in standalone driver because it relies on
3404 * adapter struct to exist, and needs to call netdev_priv
3405 */
3406 pci_save_state(pdev);
3407
3408 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3409 pci_resource_len(pdev, 0));
3410 if (!hw->hw_addr) {
3411 err = -EIO;
3412 goto err_ioremap;
3413 }
3414
3415 ixgbevf_assign_netdev_ops(netdev);
3416
3417 adapter->bd_number = cards_found;
3418
3419 /* Setup hw api */
3420 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3421 hw->mac.type = ii->mac;
3422
3423 memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops,
f416dfc0 3424 sizeof(struct ixgbe_mbx_operations));
92915f71 3425
92915f71
GR		 3426 /* setup the private structure */
3427 err = ixgbevf_sw_init(adapter);
1a0d6ae5
DK		 3428 if (err)
3429 goto err_sw_init;
3430
3431 /* The HW MAC address was set and/or determined in sw_init */
1a0d6ae5
DK		 3432 if (!is_valid_ether_addr(netdev->dev_addr)) {
3433 pr_err("invalid MAC address\n");
3434 err = -EIO;
3435 goto err_sw_init;
3436 }
92915f71 3437
471a76de 3438 netdev->hw_features = NETIF_F_SG |
92915f71 3439 NETIF_F_IP_CSUM |
471a76de
MM		 3440 NETIF_F_IPV6_CSUM |
3441 NETIF_F_TSO |
3442 NETIF_F_TSO6 |
3443 NETIF_F_RXCSUM;
3444
3445 netdev->features = netdev->hw_features |
f646968f
PM		 3446 NETIF_F_HW_VLAN_CTAG_TX |
3447 NETIF_F_HW_VLAN_CTAG_RX |
3448 NETIF_F_HW_VLAN_CTAG_FILTER;
92915f71 3449
92915f71
GR		 3450 netdev->vlan_features |= NETIF_F_TSO;
3451 netdev->vlan_features |= NETIF_F_TSO6;
3452 netdev->vlan_features |= NETIF_F_IP_CSUM;
3bfacf96 3453 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
92915f71
GR		 3454 netdev->vlan_features |= NETIF_F_SG;
3455
3456 if (pci_using_dac)
3457 netdev->features |= NETIF_F_HIGHDMA;
3458
01789349
JP		 3459 netdev->priv_flags |= IFF_UNICAST_FLT;
3460
92915f71 3461 init_timer(&adapter->watchdog_timer);
c061b18d 3462 adapter->watchdog_timer.function = ixgbevf_watchdog;
92915f71
GR		 3463 adapter->watchdog_timer.data = (unsigned long)adapter;
3464
3465 INIT_WORK(&adapter->reset_task, ixgbevf_reset_task);
3466 INIT_WORK(&adapter->watchdog_task, ixgbevf_watchdog_task);
3467
3468 err = ixgbevf_init_interrupt_scheme(adapter);
3469 if (err)
3470 goto err_sw_init;
3471
92915f71
GR		 3472 strcpy(netdev->name, "eth%d");
3473
3474 err = register_netdev(netdev);
3475 if (err)
3476 goto err_register;
3477
5d426ad1
GR		 3478 netif_carrier_off(netdev);
3479
33bd9f60
GR		 3480 ixgbevf_init_last_counter_stats(adapter);
3481
92915f71 3482 /* print the MAC address */
f794e7ef 3483 hw_dbg(hw, "%pM\n", netdev->dev_addr);
92915f71
GR		 3484
3485 hw_dbg(hw, "MAC: %d\n", hw->mac.type);
3486
92915f71
GR		 3487 hw_dbg(hw, "Intel(R) 82599 Virtual Function\n");
3488 cards_found++;
3489 return 0;
3490
3491err_register:
0ac1e8ce 3492 ixgbevf_clear_interrupt_scheme(adapter);
92915f71
GR		 3493err_sw_init:
3494 ixgbevf_reset_interrupt_capability(adapter);
3495 iounmap(hw->hw_addr);
3496err_ioremap:
3497 free_netdev(netdev);
3498err_alloc_etherdev:
3499 pci_release_regions(pdev);
3500err_pci_reg:
3501err_dma:
3502 pci_disable_device(pdev);
3503 return err;
3504}
3505
3506/**
3507 * ixgbevf_remove - Device Removal Routine
3508 * @pdev: PCI device information struct
3509 *
3510 * ixgbevf_remove is called by the PCI subsystem to alert the driver
3511 * that it should release a PCI device. The could be caused by a
3512 * Hot-Plug event, or because the driver is going to be removed from
3513 * memory.
3514 **/
9f9a12f8 3515static void ixgbevf_remove(struct pci_dev *pdev)
92915f71
GR		 3516{
3517 struct net_device *netdev = pci_get_drvdata(pdev);
3518 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3519
3520 set_bit(__IXGBEVF_DOWN, &adapter->state);
3521
3522 del_timer_sync(&adapter->watchdog_timer);
3523
23f333a2 3524 cancel_work_sync(&adapter->reset_task);
92915f71
GR		 3525 cancel_work_sync(&adapter->watchdog_task);
3526
fd13a9ab 3527 if (netdev->reg_state == NETREG_REGISTERED)
92915f71 3528 unregister_netdev(netdev);
92915f71 3529
0ac1e8ce 3530 ixgbevf_clear_interrupt_scheme(adapter);
92915f71
GR		 3531 ixgbevf_reset_interrupt_capability(adapter);
3532
3533 iounmap(adapter->hw.hw_addr);
3534 pci_release_regions(pdev);
3535
3536 hw_dbg(&adapter->hw, "Remove complete\n");
3537
3538 kfree(adapter->tx_ring);
3539 kfree(adapter->rx_ring);
3540
3541 free_netdev(netdev);
3542
3543 pci_disable_device(pdev);
3544}
3545
9f19f31d
AD		 3546/**
3547 * ixgbevf_io_error_detected - called when PCI error is detected
3548 * @pdev: Pointer to PCI device
3549 * @state: The current pci connection state
3550 *
3551 * This function is called after a PCI bus error affecting
3552 * this device has been detected.
3553 */
3554static pci_ers_result_t ixgbevf_io_error_detected(struct pci_dev *pdev,
3555 pci_channel_state_t state)
3556{
3557 struct net_device *netdev = pci_get_drvdata(pdev);
3558 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3559
3560 netif_device_detach(netdev);
3561
3562 if (state == pci_channel_io_perm_failure)
3563 return PCI_ERS_RESULT_DISCONNECT;
3564
3565 if (netif_running(netdev))
3566 ixgbevf_down(adapter);
3567
3568 pci_disable_device(pdev);
3569
3570 /* Request a slot slot reset. */
3571 return PCI_ERS_RESULT_NEED_RESET;
3572}
3573
3574/**
3575 * ixgbevf_io_slot_reset - called after the pci bus has been reset.
3576 * @pdev: Pointer to PCI device
3577 *
3578 * Restart the card from scratch, as if from a cold-boot. Implementation
3579 * resembles the first-half of the ixgbevf_resume routine.
3580 */
3581static pci_ers_result_t ixgbevf_io_slot_reset(struct pci_dev *pdev)
3582{
3583 struct net_device *netdev = pci_get_drvdata(pdev);
3584 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3585
3586 if (pci_enable_device_mem(pdev)) {
3587 dev_err(&pdev->dev,
3588 "Cannot re-enable PCI device after reset.\n");
3589 return PCI_ERS_RESULT_DISCONNECT;
3590 }
3591
3592 pci_set_master(pdev);
3593
3594 ixgbevf_reset(adapter);
3595
3596 return PCI_ERS_RESULT_RECOVERED;
3597}
3598
3599/**
3600 * ixgbevf_io_resume - called when traffic can start flowing again.
3601 * @pdev: Pointer to PCI device
3602 *
3603 * This callback is called when the error recovery driver tells us that
3604 * its OK to resume normal operation. Implementation resembles the
3605 * second-half of the ixgbevf_resume routine.
3606 */
3607static void ixgbevf_io_resume(struct pci_dev *pdev)
3608{
3609 struct net_device *netdev = pci_get_drvdata(pdev);
3610 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3611
3612 if (netif_running(netdev))
3613 ixgbevf_up(adapter);
3614
3615 netif_device_attach(netdev);
3616}
3617
3618/* PCI Error Recovery (ERS) */
3646f0e5 3619static const struct pci_error_handlers ixgbevf_err_handler = {
9f19f31d
AD		 3620 .error_detected = ixgbevf_io_error_detected,
3621 .slot_reset = ixgbevf_io_slot_reset,
3622 .resume = ixgbevf_io_resume,
3623};
3624
92915f71
GR		 3625static struct pci_driver ixgbevf_driver = {
3626 .name = ixgbevf_driver_name,
3627 .id_table = ixgbevf_pci_tbl,
3628 .probe = ixgbevf_probe,
9f9a12f8 3629 .remove = ixgbevf_remove,
0ac1e8ce
AD		 3630#ifdef CONFIG_PM
3631 /* Power Management Hooks */
3632 .suspend = ixgbevf_suspend,
3633 .resume = ixgbevf_resume,
3634#endif
92915f71 3635 .shutdown = ixgbevf_shutdown,
9f19f31d 3636 .err_handler = &ixgbevf_err_handler
92915f71
GR		 3637};
3638
3639/**
65d676c8 3640 * ixgbevf_init_module - Driver Registration Routine
92915f71 3641 *
65d676c8 3642 * ixgbevf_init_module is the first routine called when the driver is
92915f71
GR		 3643 * loaded. All it does is register with the PCI subsystem.
3644 **/
3645static int __init ixgbevf_init_module(void)
3646{
3647 int ret;
dbd9636e
JK		 3648 pr_info("%s - version %s\n", ixgbevf_driver_string,
3649 ixgbevf_driver_version);
92915f71 3650
dbd9636e 3651 pr_info("%s\n", ixgbevf_copyright);
92915f71
GR		 3652
3653 ret = pci_register_driver(&ixgbevf_driver);
3654 return ret;
3655}
3656
3657module_init(ixgbevf_init_module);
3658
3659/**
65d676c8 3660 * ixgbevf_exit_module - Driver Exit Cleanup Routine
92915f71 3661 *
65d676c8 3662 * ixgbevf_exit_module is called just before the driver is removed
92915f71
GR		 3663 * from memory.
3664 **/
3665static void __exit ixgbevf_exit_module(void)
3666{
3667 pci_unregister_driver(&ixgbevf_driver);
3668}
3669
3670#ifdef DEBUG
3671/**
65d676c8 3672 * ixgbevf_get_hw_dev_name - return device name string
92915f71
GR		 3673 * used by hardware layer to print debugging information
3674 **/
3675char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw)
3676{
3677 struct ixgbevf_adapter *adapter = hw->back;
3678 return adapter->netdev->name;
3679}
3680
3681#endif
3682module_exit(ixgbevf_exit_module);
3683
3684/* ixgbevf_main.c */
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