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CommitLineData
92915f71
GR
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
5c47a2b6 4 Copyright(c) 1999 - 2012 Intel Corporation.
92915f71
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5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/******************************************************************************
30 Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
31******************************************************************************/
dbd9636e
JK
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
92915f71 35#include <linux/types.h>
dadcd65f 36#include <linux/bitops.h>
92915f71
GR
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/vmalloc.h>
41#include <linux/string.h>
42#include <linux/in.h>
43#include <linux/ip.h>
44#include <linux/tcp.h>
70a10e25 45#include <linux/sctp.h>
92915f71 46#include <linux/ipv6.h>
5a0e3ad6 47#include <linux/slab.h>
92915f71
GR
48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
01789349 51#include <linux/if.h>
92915f71 52#include <linux/if_vlan.h>
70c71606 53#include <linux/prefetch.h>
92915f71
GR
54
55#include "ixgbevf.h"
56
3d8fe98f 57const char ixgbevf_driver_name[] = "ixgbevf";
92915f71 58static const char ixgbevf_driver_string[] =
422e05d1 59 "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver";
92915f71 60
86f359f6 61#define DRV_VERSION "2.12.1-k"
92915f71 62const char ixgbevf_driver_version[] = DRV_VERSION;
66c87bd5 63static char ixgbevf_copyright[] =
5c47a2b6 64 "Copyright (c) 2009 - 2012 Intel Corporation.";
92915f71
GR
65
66static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
2316aa2a
GR
67 [board_82599_vf] = &ixgbevf_82599_vf_info,
68 [board_X540_vf] = &ixgbevf_X540_vf_info,
92915f71
GR
69};
70
71/* ixgbevf_pci_tbl - PCI Device ID Table
72 *
73 * Wildcard entries (PCI_ANY_ID) should come last
74 * Last entry must be all 0s
75 *
76 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
77 * Class, Class Mask, private data (not used) }
78 */
39ba22b4
SH
79static DEFINE_PCI_DEVICE_TABLE(ixgbevf_pci_tbl) = {
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF), board_82599_vf },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF), board_X540_vf },
92915f71
GR
82 /* required last entry */
83 {0, }
84};
85MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl);
86
87MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
88MODULE_DESCRIPTION("Intel(R) 82599 Virtual Function Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
b3f4d599 92#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
93static int debug = -1;
94module_param(debug, int, 0);
95MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92915f71
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96
97/* forward decls */
220fe050 98static void ixgbevf_queue_reset_subtask(struct ixgbevf_adapter *adapter);
fa71ae27 99static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector);
56e94095 100static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter);
92915f71 101
5cdab2f6 102static inline void ixgbevf_release_rx_desc(struct ixgbevf_ring *rx_ring,
92915f71
GR
103 u32 val)
104{
5cdab2f6
DS
105 rx_ring->next_to_use = val;
106
92915f71
GR
107 /*
108 * Force memory writes to complete before letting h/w
109 * know there are new descriptors to fetch. (Only
110 * applicable for weak-ordered memory model archs,
111 * such as IA-64).
112 */
113 wmb();
5cdab2f6 114 writel(val, rx_ring->tail);
92915f71
GR
115}
116
49ce9c2c 117/**
65d676c8 118 * ixgbevf_set_ivar - set IVAR registers - maps interrupt causes to vectors
92915f71
GR
119 * @adapter: pointer to adapter struct
120 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
121 * @queue: queue to map the corresponding interrupt to
122 * @msix_vector: the vector to map to the corresponding queue
92915f71
GR
123 */
124static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction,
125 u8 queue, u8 msix_vector)
126{
127 u32 ivar, index;
128 struct ixgbe_hw *hw = &adapter->hw;
129 if (direction == -1) {
130 /* other causes */
131 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
132 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
133 ivar &= ~0xFF;
134 ivar |= msix_vector;
135 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar);
136 } else {
137 /* tx or rx causes */
138 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
139 index = ((16 * (queue & 1)) + (8 * direction));
140 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
141 ivar &= ~(0xFF << index);
142 ivar |= (msix_vector << index);
143 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar);
144 }
145}
146
70a10e25 147static void ixgbevf_unmap_and_free_tx_resource(struct ixgbevf_ring *tx_ring,
9bdfefd2
ET
148 struct ixgbevf_tx_buffer *tx_buffer)
149{
150 if (tx_buffer->skb) {
151 dev_kfree_skb_any(tx_buffer->skb);
152 if (dma_unmap_len(tx_buffer, len))
70a10e25 153 dma_unmap_single(tx_ring->dev,
9bdfefd2
ET
154 dma_unmap_addr(tx_buffer, dma),
155 dma_unmap_len(tx_buffer, len),
2a1f8794 156 DMA_TO_DEVICE);
9bdfefd2
ET
157 } else if (dma_unmap_len(tx_buffer, len)) {
158 dma_unmap_page(tx_ring->dev,
159 dma_unmap_addr(tx_buffer, dma),
160 dma_unmap_len(tx_buffer, len),
161 DMA_TO_DEVICE);
92915f71 162 }
9bdfefd2
ET
163 tx_buffer->next_to_watch = NULL;
164 tx_buffer->skb = NULL;
165 dma_unmap_len_set(tx_buffer, len, 0);
166 /* tx_buffer must be completely set up in the transmit path */
92915f71
GR
167}
168
92915f71
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169#define IXGBE_MAX_TXD_PWR 14
170#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
171
172/* Tx Descriptors needed, worst case */
3595990a
AD
173#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
174#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
92915f71
GR
175
176static void ixgbevf_tx_timeout(struct net_device *netdev);
177
178/**
179 * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes
fa71ae27 180 * @q_vector: board private structure
92915f71
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181 * @tx_ring: tx ring to clean
182 **/
fa71ae27 183static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector,
92915f71
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184 struct ixgbevf_ring *tx_ring)
185{
fa71ae27 186 struct ixgbevf_adapter *adapter = q_vector->adapter;
7ad1a093
ET
187 struct ixgbevf_tx_buffer *tx_buffer;
188 union ixgbe_adv_tx_desc *tx_desc;
92915f71 189 unsigned int total_bytes = 0, total_packets = 0;
7ad1a093
ET
190 unsigned int budget = tx_ring->count / 2;
191 unsigned int i = tx_ring->next_to_clean;
92915f71 192
10cc1bdd
AD
193 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
194 return true;
195
7ad1a093
ET
196 tx_buffer = &tx_ring->tx_buffer_info[i];
197 tx_desc = IXGBEVF_TX_DESC(tx_ring, i);
198 i -= tx_ring->count;
92915f71 199
e757e3e1 200 do {
7ad1a093 201 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
e757e3e1
AD
202
203 /* if next_to_watch is not set then there is no work pending */
204 if (!eop_desc)
205 break;
206
207 /* prevent any other reads prior to eop_desc */
208 read_barrier_depends();
209
210 /* if DD is not set pending work has not been completed */
211 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
212 break;
213
214 /* clear next_to_watch to prevent false hangs */
7ad1a093 215 tx_buffer->next_to_watch = NULL;
e757e3e1 216
7ad1a093
ET
217 /* update the statistics for this packet */
218 total_bytes += tx_buffer->bytecount;
219 total_packets += tx_buffer->gso_segs;
92915f71 220
9bdfefd2
ET
221 /* free the skb */
222 dev_kfree_skb_any(tx_buffer->skb);
223
224 /* unmap skb header data */
225 dma_unmap_single(tx_ring->dev,
226 dma_unmap_addr(tx_buffer, dma),
227 dma_unmap_len(tx_buffer, len),
228 DMA_TO_DEVICE);
229
7ad1a093 230 /* clear tx_buffer data */
9bdfefd2
ET
231 tx_buffer->skb = NULL;
232 dma_unmap_len_set(tx_buffer, len, 0);
92915f71 233
7ad1a093
ET
234 /* unmap remaining buffers */
235 while (tx_desc != eop_desc) {
7ad1a093
ET
236 tx_buffer++;
237 tx_desc++;
92915f71 238 i++;
7ad1a093
ET
239 if (unlikely(!i)) {
240 i -= tx_ring->count;
241 tx_buffer = tx_ring->tx_buffer_info;
242 tx_desc = IXGBEVF_TX_DESC(tx_ring, 0);
243 }
e757e3e1 244
9bdfefd2
ET
245 /* unmap any remaining paged data */
246 if (dma_unmap_len(tx_buffer, len)) {
247 dma_unmap_page(tx_ring->dev,
248 dma_unmap_addr(tx_buffer, dma),
249 dma_unmap_len(tx_buffer, len),
250 DMA_TO_DEVICE);
251 dma_unmap_len_set(tx_buffer, len, 0);
252 }
92915f71
GR
253 }
254
7ad1a093
ET
255 /* move us one more past the eop_desc for start of next pkt */
256 tx_buffer++;
257 tx_desc++;
258 i++;
259 if (unlikely(!i)) {
260 i -= tx_ring->count;
261 tx_buffer = tx_ring->tx_buffer_info;
262 tx_desc = IXGBEVF_TX_DESC(tx_ring, 0);
263 }
264
265 /* issue prefetch for next Tx descriptor */
266 prefetch(tx_desc);
267
268 /* update budget accounting */
269 budget--;
270 } while (likely(budget));
271
272 i += tx_ring->count;
92915f71 273 tx_ring->next_to_clean = i;
7ad1a093
ET
274 u64_stats_update_begin(&tx_ring->syncp);
275 tx_ring->stats.bytes += total_bytes;
276 tx_ring->stats.packets += total_packets;
277 u64_stats_update_end(&tx_ring->syncp);
278 q_vector->tx.total_bytes += total_bytes;
279 q_vector->tx.total_packets += total_packets;
92915f71
GR
280
281#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
7ad1a093 282 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
f880d07b 283 (ixgbevf_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
92915f71
GR
284 /* Make sure that anybody stopping the queue after this
285 * sees the new next_to_clean.
286 */
287 smp_mb();
7ad1a093 288
fb40195c
AD
289 if (__netif_subqueue_stopped(tx_ring->netdev,
290 tx_ring->queue_index) &&
92915f71 291 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
fb40195c
AD
292 netif_wake_subqueue(tx_ring->netdev,
293 tx_ring->queue_index);
7ad1a093 294 ++tx_ring->tx_stats.restart_queue;
92915f71 295 }
92915f71
GR
296 }
297
7ad1a093 298 return !!budget;
92915f71
GR
299}
300
301/**
302 * ixgbevf_receive_skb - Send a completed packet up the stack
303 * @q_vector: structure containing interrupt and ring information
304 * @skb: packet to send up
305 * @status: hardware indication of status of receive
92915f71
GR
306 * @rx_desc: rx descriptor
307 **/
308static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
309 struct sk_buff *skb, u8 status,
92915f71
GR
310 union ixgbe_adv_rx_desc *rx_desc)
311{
312 struct ixgbevf_adapter *adapter = q_vector->adapter;
313 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
dd1ed3b7 314 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
92915f71 315
5d9a533b 316 if (is_vlan && test_bit(tag & VLAN_VID_MASK, adapter->active_vlans))
86a9bad3 317 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
dadcd65f 318
366c1099
GR
319 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
320 napi_gro_receive(&q_vector->napi, skb);
321 else
322 netif_rx(skb);
92915f71
GR
323}
324
08681618
JK
325/**
326 * ixgbevf_rx_skb - Helper function to determine proper Rx method
327 * @q_vector: structure containing interrupt and ring information
328 * @skb: packet to send up
329 * @status: hardware indication of status of receive
330 * @rx_desc: rx descriptor
331 **/
332static void ixgbevf_rx_skb(struct ixgbevf_q_vector *q_vector,
333 struct sk_buff *skb, u8 status,
334 union ixgbe_adv_rx_desc *rx_desc)
335{
c777cdfa
JK
336#ifdef CONFIG_NET_RX_BUSY_POLL
337 skb_mark_napi_id(skb, &q_vector->napi);
338
339 if (ixgbevf_qv_busy_polling(q_vector)) {
340 netif_receive_skb(skb);
341 /* exit early if we busy polled */
342 return;
343 }
344#endif /* CONFIG_NET_RX_BUSY_POLL */
345
08681618
JK
346 ixgbevf_receive_skb(q_vector, skb, status, rx_desc);
347}
348
92915f71
GR
349/**
350 * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum
55fb277c 351 * @ring: pointer to Rx descriptor ring structure
92915f71
GR
352 * @status_err: hardware indication of status of receive
353 * @skb: skb currently being received and modified
354 **/
55fb277c 355static inline void ixgbevf_rx_checksum(struct ixgbevf_ring *ring,
92915f71
GR
356 u32 status_err, struct sk_buff *skb)
357{
bc8acf2c 358 skb_checksum_none_assert(skb);
92915f71
GR
359
360 /* Rx csum disabled */
fb40195c 361 if (!(ring->netdev->features & NETIF_F_RXCSUM))
92915f71
GR
362 return;
363
364 /* if IP and error */
365 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
366 (status_err & IXGBE_RXDADV_ERR_IPE)) {
095e2617 367 ring->rx_stats.csum_err++;
92915f71
GR
368 return;
369 }
370
371 if (!(status_err & IXGBE_RXD_STAT_L4CS))
372 return;
373
374 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
095e2617 375 ring->rx_stats.csum_err++;
92915f71
GR
376 return;
377 }
378
379 /* It must be a TCP or UDP packet with a valid checksum */
380 skb->ip_summed = CHECKSUM_UNNECESSARY;
92915f71
GR
381}
382
383/**
384 * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split
095e2617 385 * @rx_ring: rx descriptor ring (for a specific queue) to setup buffers on
92915f71 386 **/
095e2617 387static void ixgbevf_alloc_rx_buffers(struct ixgbevf_ring *rx_ring,
92915f71
GR
388 int cleaned_count)
389{
92915f71
GR
390 union ixgbe_adv_rx_desc *rx_desc;
391 struct ixgbevf_rx_buffer *bi;
fb40195c 392 unsigned int i = rx_ring->next_to_use;
92915f71 393
92915f71 394 while (cleaned_count--) {
908421f6 395 rx_desc = IXGBEVF_RX_DESC(rx_ring, i);
05d063aa 396 bi = &rx_ring->rx_buffer_info[i];
b9dd245b
GR
397
398 if (!bi->skb) {
399 struct sk_buff *skb;
400
fb40195c
AD
401 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
402 rx_ring->rx_buf_len);
05d063aa 403 if (!skb)
92915f71 404 goto no_buffers;
05d063aa 405
92915f71 406 bi->skb = skb;
b9dd245b 407
05d063aa 408 bi->dma = dma_map_single(rx_ring->dev, skb->data,
92915f71 409 rx_ring->rx_buf_len,
2a1f8794 410 DMA_FROM_DEVICE);
05d063aa 411 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
6132ee8a
GR
412 dev_kfree_skb(skb);
413 bi->skb = NULL;
05d063aa 414 dev_err(rx_ring->dev, "Rx DMA map failed\n");
6132ee8a
GR
415 break;
416 }
92915f71 417 }
77d5dfca 418 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
92915f71
GR
419
420 i++;
421 if (i == rx_ring->count)
422 i = 0;
92915f71
GR
423 }
424
425no_buffers:
095e2617 426 rx_ring->rx_stats.alloc_rx_buff_failed++;
5cdab2f6
DS
427 if (rx_ring->next_to_use != i)
428 ixgbevf_release_rx_desc(rx_ring, i);
92915f71
GR
429}
430
431static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter,
5f3600eb 432 u32 qmask)
92915f71 433{
92915f71
GR
434 struct ixgbe_hw *hw = &adapter->hw;
435
5f3600eb 436 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, qmask);
92915f71
GR
437}
438
08e50a20
JK
439static int ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector,
440 struct ixgbevf_ring *rx_ring,
441 int budget)
92915f71 442{
92915f71
GR
443 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
444 struct ixgbevf_rx_buffer *rx_buffer_info, *next_buffer;
445 struct sk_buff *skb;
446 unsigned int i;
447 u32 len, staterr;
92915f71
GR
448 int cleaned_count = 0;
449 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
450
451 i = rx_ring->next_to_clean;
908421f6 452 rx_desc = IXGBEVF_RX_DESC(rx_ring, i);
92915f71
GR
453 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
454 rx_buffer_info = &rx_ring->rx_buffer_info[i];
455
456 while (staterr & IXGBE_RXD_STAT_DD) {
fa71ae27 457 if (!budget)
92915f71 458 break;
fa71ae27 459 budget--;
92915f71 460
2d0bb1c1 461 rmb(); /* read descriptor and rx_buffer_info after status DD */
77d5dfca 462 len = le16_to_cpu(rx_desc->wb.upper.length);
92915f71
GR
463 skb = rx_buffer_info->skb;
464 prefetch(skb->data - NET_IP_ALIGN);
465 rx_buffer_info->skb = NULL;
466
467 if (rx_buffer_info->dma) {
05d063aa 468 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
92915f71 469 rx_ring->rx_buf_len,
2a1f8794 470 DMA_FROM_DEVICE);
92915f71
GR
471 rx_buffer_info->dma = 0;
472 skb_put(skb, len);
473 }
474
92915f71
GR
475 i++;
476 if (i == rx_ring->count)
477 i = 0;
478
908421f6 479 next_rxd = IXGBEVF_RX_DESC(rx_ring, i);
92915f71
GR
480 prefetch(next_rxd);
481 cleaned_count++;
482
483 next_buffer = &rx_ring->rx_buffer_info[i];
484
485 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
77d5dfca 486 skb->next = next_buffer->skb;
5c60f81a 487 IXGBE_CB(skb->next)->prev = skb;
095e2617 488 rx_ring->rx_stats.non_eop_descs++;
92915f71
GR
489 goto next_desc;
490 }
491
5c60f81a
AD
492 /* we should not be chaining buffers, if we did drop the skb */
493 if (IXGBE_CB(skb)->prev) {
494 do {
495 struct sk_buff *this = skb;
496 skb = IXGBE_CB(skb)->prev;
497 dev_kfree_skb(this);
498 } while (skb);
499 goto next_desc;
500 }
501
92915f71
GR
502 /* ERR_MASK will only have valid bits if EOP set */
503 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
504 dev_kfree_skb_irq(skb);
505 goto next_desc;
506 }
507
55fb277c 508 ixgbevf_rx_checksum(rx_ring, staterr, skb);
92915f71
GR
509
510 /* probably a little skewed due to removing CRC */
511 total_rx_bytes += skb->len;
512 total_rx_packets++;
513
fb40195c 514 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
92915f71 515
815cccbf
JF
516 /* Workaround hardware that can't do proper VEPA multicast
517 * source pruning.
518 */
bd9d5592
FF
519 if ((skb->pkt_type == PACKET_BROADCAST ||
520 skb->pkt_type == PACKET_MULTICAST) &&
095e2617 521 ether_addr_equal(rx_ring->netdev->dev_addr,
7367d0b5 522 eth_hdr(skb)->h_source)) {
815cccbf
JF
523 dev_kfree_skb_irq(skb);
524 goto next_desc;
525 }
526
08681618 527 ixgbevf_rx_skb(q_vector, skb, staterr, rx_desc);
92915f71
GR
528
529next_desc:
530 rx_desc->wb.upper.status_error = 0;
531
532 /* return some buffers to hardware, one at a time is too slow */
533 if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) {
095e2617 534 ixgbevf_alloc_rx_buffers(rx_ring, cleaned_count);
92915f71
GR
535 cleaned_count = 0;
536 }
537
538 /* use prefetched values */
539 rx_desc = next_rxd;
540 rx_buffer_info = &rx_ring->rx_buffer_info[i];
541
542 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
543 }
544
545 rx_ring->next_to_clean = i;
f880d07b 546 cleaned_count = ixgbevf_desc_unused(rx_ring);
92915f71
GR
547
548 if (cleaned_count)
095e2617 549 ixgbevf_alloc_rx_buffers(rx_ring, cleaned_count);
92915f71 550
4197aa7b 551 u64_stats_update_begin(&rx_ring->syncp);
095e2617
ET
552 rx_ring->stats.packets += total_rx_packets;
553 rx_ring->stats.bytes += total_rx_bytes;
4197aa7b 554 u64_stats_update_end(&rx_ring->syncp);
ac6ed8f0
GR
555 q_vector->rx.total_packets += total_rx_packets;
556 q_vector->rx.total_bytes += total_rx_bytes;
92915f71 557
08e50a20 558 return total_rx_packets;
92915f71
GR
559}
560
561/**
fa71ae27 562 * ixgbevf_poll - NAPI polling calback
92915f71
GR
563 * @napi: napi struct with our devices info in it
564 * @budget: amount of work driver is allowed to do this pass, in packets
565 *
fa71ae27 566 * This function will clean more than one or more rings associated with a
92915f71
GR
567 * q_vector.
568 **/
fa71ae27 569static int ixgbevf_poll(struct napi_struct *napi, int budget)
92915f71
GR
570{
571 struct ixgbevf_q_vector *q_vector =
572 container_of(napi, struct ixgbevf_q_vector, napi);
573 struct ixgbevf_adapter *adapter = q_vector->adapter;
fa71ae27
AD
574 struct ixgbevf_ring *ring;
575 int per_ring_budget;
576 bool clean_complete = true;
577
578 ixgbevf_for_each_ring(ring, q_vector->tx)
579 clean_complete &= ixgbevf_clean_tx_irq(q_vector, ring);
92915f71 580
c777cdfa
JK
581#ifdef CONFIG_NET_RX_BUSY_POLL
582 if (!ixgbevf_qv_lock_napi(q_vector))
583 return budget;
584#endif
585
92915f71
GR
586 /* attempt to distribute budget to each queue fairly, but don't allow
587 * the budget to go below 1 because we'll exit polling */
fa71ae27
AD
588 if (q_vector->rx.count > 1)
589 per_ring_budget = max(budget/q_vector->rx.count, 1);
590 else
591 per_ring_budget = budget;
592
366c1099 593 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
fa71ae27 594 ixgbevf_for_each_ring(ring, q_vector->rx)
08e50a20
JK
595 clean_complete &= (ixgbevf_clean_rx_irq(q_vector, ring,
596 per_ring_budget)
597 < per_ring_budget);
366c1099 598 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
fa71ae27 599
c777cdfa
JK
600#ifdef CONFIG_NET_RX_BUSY_POLL
601 ixgbevf_qv_unlock_napi(q_vector);
602#endif
603
fa71ae27
AD
604 /* If all work not completed, return budget and keep polling */
605 if (!clean_complete)
606 return budget;
607 /* all work done, exit the polling mode */
608 napi_complete(napi);
609 if (adapter->rx_itr_setting & 1)
610 ixgbevf_set_itr(q_vector);
611 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
612 ixgbevf_irq_enable_queues(adapter,
613 1 << q_vector->v_idx);
92915f71 614
fa71ae27 615 return 0;
92915f71
GR
616}
617
ce422606
GR
618/**
619 * ixgbevf_write_eitr - write VTEITR register in hardware specific way
620 * @q_vector: structure containing interrupt and ring information
621 */
3849623e 622void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector)
ce422606
GR
623{
624 struct ixgbevf_adapter *adapter = q_vector->adapter;
625 struct ixgbe_hw *hw = &adapter->hw;
626 int v_idx = q_vector->v_idx;
627 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
628
629 /*
630 * set the WDIS bit to not clear the timer bits and cause an
631 * immediate assertion of the interrupt
632 */
633 itr_reg |= IXGBE_EITR_CNT_WDIS;
634
635 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg);
636}
92915f71 637
c777cdfa
JK
638#ifdef CONFIG_NET_RX_BUSY_POLL
639/* must be called with local_bh_disable()d */
640static int ixgbevf_busy_poll_recv(struct napi_struct *napi)
641{
642 struct ixgbevf_q_vector *q_vector =
643 container_of(napi, struct ixgbevf_q_vector, napi);
644 struct ixgbevf_adapter *adapter = q_vector->adapter;
645 struct ixgbevf_ring *ring;
646 int found = 0;
647
648 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
649 return LL_FLUSH_FAILED;
650
651 if (!ixgbevf_qv_lock_poll(q_vector))
652 return LL_FLUSH_BUSY;
653
654 ixgbevf_for_each_ring(ring, q_vector->rx) {
655 found = ixgbevf_clean_rx_irq(q_vector, ring, 4);
3b5dca26
JK
656#ifdef BP_EXTENDED_STATS
657 if (found)
095e2617 658 ring->stats.cleaned += found;
3b5dca26 659 else
095e2617 660 ring->stats.misses++;
3b5dca26 661#endif
c777cdfa
JK
662 if (found)
663 break;
664 }
665
666 ixgbevf_qv_unlock_poll(q_vector);
667
668 return found;
669}
670#endif /* CONFIG_NET_RX_BUSY_POLL */
671
92915f71
GR
672/**
673 * ixgbevf_configure_msix - Configure MSI-X hardware
674 * @adapter: board private structure
675 *
676 * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X
677 * interrupts.
678 **/
679static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter)
680{
681 struct ixgbevf_q_vector *q_vector;
6b43c446 682 int q_vectors, v_idx;
92915f71
GR
683
684 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5f3600eb 685 adapter->eims_enable_mask = 0;
92915f71
GR
686
687 /*
688 * Populate the IVAR table and set the ITR values to the
689 * corresponding register.
690 */
691 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
6b43c446 692 struct ixgbevf_ring *ring;
92915f71 693 q_vector = adapter->q_vector[v_idx];
6b43c446
AD
694
695 ixgbevf_for_each_ring(ring, q_vector->rx)
696 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx);
697
698 ixgbevf_for_each_ring(ring, q_vector->tx)
699 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx);
92915f71 700
5f3600eb
AD
701 if (q_vector->tx.ring && !q_vector->rx.ring) {
702 /* tx only vector */
703 if (adapter->tx_itr_setting == 1)
704 q_vector->itr = IXGBE_10K_ITR;
705 else
706 q_vector->itr = adapter->tx_itr_setting;
707 } else {
708 /* rx or rx/tx vector */
709 if (adapter->rx_itr_setting == 1)
710 q_vector->itr = IXGBE_20K_ITR;
711 else
712 q_vector->itr = adapter->rx_itr_setting;
713 }
714
715 /* add q_vector eims value to global eims_enable_mask */
716 adapter->eims_enable_mask |= 1 << v_idx;
92915f71 717
5f3600eb 718 ixgbevf_write_eitr(q_vector);
92915f71
GR
719 }
720
721 ixgbevf_set_ivar(adapter, -1, 1, v_idx);
5f3600eb
AD
722 /* setup eims_other and add value to global eims_enable_mask */
723 adapter->eims_other = 1 << v_idx;
724 adapter->eims_enable_mask |= adapter->eims_other;
92915f71
GR
725}
726
727enum latency_range {
728 lowest_latency = 0,
729 low_latency = 1,
730 bulk_latency = 2,
731 latency_invalid = 255
732};
733
734/**
735 * ixgbevf_update_itr - update the dynamic ITR value based on statistics
5f3600eb
AD
736 * @q_vector: structure containing interrupt and ring information
737 * @ring_container: structure containing ring performance data
92915f71
GR
738 *
739 * Stores a new ITR value based on packets and byte
740 * counts during the last interrupt. The advantage of per interrupt
741 * computation is faster updates and more accurate ITR for the current
742 * traffic pattern. Constants in this function were computed
743 * based on theoretical maximum wire speed and thresholds were set based
744 * on testing data as well as attempting to minimize response time
745 * while increasing bulk throughput.
746 **/
5f3600eb
AD
747static void ixgbevf_update_itr(struct ixgbevf_q_vector *q_vector,
748 struct ixgbevf_ring_container *ring_container)
92915f71 749{
5f3600eb
AD
750 int bytes = ring_container->total_bytes;
751 int packets = ring_container->total_packets;
92915f71
GR
752 u32 timepassed_us;
753 u64 bytes_perint;
5f3600eb 754 u8 itr_setting = ring_container->itr;
92915f71
GR
755
756 if (packets == 0)
5f3600eb 757 return;
92915f71
GR
758
759 /* simple throttlerate management
760 * 0-20MB/s lowest (100000 ints/s)
761 * 20-100MB/s low (20000 ints/s)
762 * 100-1249MB/s bulk (8000 ints/s)
763 */
764 /* what was last interrupt timeslice? */
5f3600eb 765 timepassed_us = q_vector->itr >> 2;
92915f71
GR
766 bytes_perint = bytes / timepassed_us; /* bytes/usec */
767
768 switch (itr_setting) {
769 case lowest_latency:
e2c28ce7 770 if (bytes_perint > 10)
5f3600eb 771 itr_setting = low_latency;
92915f71
GR
772 break;
773 case low_latency:
e2c28ce7 774 if (bytes_perint > 20)
5f3600eb 775 itr_setting = bulk_latency;
e2c28ce7 776 else if (bytes_perint <= 10)
5f3600eb 777 itr_setting = lowest_latency;
92915f71
GR
778 break;
779 case bulk_latency:
e2c28ce7 780 if (bytes_perint <= 20)
5f3600eb 781 itr_setting = low_latency;
92915f71
GR
782 break;
783 }
784
5f3600eb
AD
785 /* clear work counters since we have the values we need */
786 ring_container->total_bytes = 0;
787 ring_container->total_packets = 0;
788
789 /* write updated itr to ring container */
790 ring_container->itr = itr_setting;
92915f71
GR
791}
792
fa71ae27 793static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector)
92915f71 794{
5f3600eb
AD
795 u32 new_itr = q_vector->itr;
796 u8 current_itr;
92915f71 797
5f3600eb
AD
798 ixgbevf_update_itr(q_vector, &q_vector->tx);
799 ixgbevf_update_itr(q_vector, &q_vector->rx);
92915f71 800
6b43c446 801 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
92915f71
GR
802
803 switch (current_itr) {
804 /* counts and packets in update_itr are dependent on these numbers */
805 case lowest_latency:
5f3600eb 806 new_itr = IXGBE_100K_ITR;
92915f71
GR
807 break;
808 case low_latency:
5f3600eb 809 new_itr = IXGBE_20K_ITR;
92915f71
GR
810 break;
811 case bulk_latency:
812 default:
5f3600eb 813 new_itr = IXGBE_8K_ITR;
92915f71
GR
814 break;
815 }
816
5f3600eb 817 if (new_itr != q_vector->itr) {
92915f71 818 /* do an exponential smoothing */
5f3600eb
AD
819 new_itr = (10 * new_itr * q_vector->itr) /
820 ((9 * new_itr) + q_vector->itr);
821
822 /* save the algorithm value here */
823 q_vector->itr = new_itr;
824
825 ixgbevf_write_eitr(q_vector);
92915f71 826 }
92915f71
GR
827}
828
4b2cd27f 829static irqreturn_t ixgbevf_msix_other(int irq, void *data)
92915f71 830{
fa71ae27 831 struct ixgbevf_adapter *adapter = data;
92915f71 832 struct ixgbe_hw *hw = &adapter->hw;
08259594 833
4b2cd27f 834 hw->mac.get_link_status = 1;
1e72bfc3 835
c7bb417d
DS
836 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
837 mod_timer(&adapter->watchdog_timer, jiffies);
3a2c4033 838
5f3600eb
AD
839 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_other);
840
92915f71
GR
841 return IRQ_HANDLED;
842}
843
92915f71 844/**
fa71ae27 845 * ixgbevf_msix_clean_rings - single unshared vector rx clean (all queues)
92915f71
GR
846 * @irq: unused
847 * @data: pointer to our q_vector struct for this interrupt vector
848 **/
fa71ae27 849static irqreturn_t ixgbevf_msix_clean_rings(int irq, void *data)
92915f71
GR
850{
851 struct ixgbevf_q_vector *q_vector = data;
92915f71 852
5f3600eb 853 /* EIAM disabled interrupts (on this vector) for us */
fa71ae27
AD
854 if (q_vector->rx.ring || q_vector->tx.ring)
855 napi_schedule(&q_vector->napi);
92915f71
GR
856
857 return IRQ_HANDLED;
858}
859
860static inline void map_vector_to_rxq(struct ixgbevf_adapter *a, int v_idx,
861 int r_idx)
862{
863 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
864
87e70ab9
DS
865 a->rx_ring[r_idx]->next = q_vector->rx.ring;
866 q_vector->rx.ring = a->rx_ring[r_idx];
6b43c446 867 q_vector->rx.count++;
92915f71
GR
868}
869
870static inline void map_vector_to_txq(struct ixgbevf_adapter *a, int v_idx,
871 int t_idx)
872{
873 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
874
87e70ab9
DS
875 a->tx_ring[t_idx]->next = q_vector->tx.ring;
876 q_vector->tx.ring = a->tx_ring[t_idx];
6b43c446 877 q_vector->tx.count++;
92915f71
GR
878}
879
880/**
881 * ixgbevf_map_rings_to_vectors - Maps descriptor rings to vectors
882 * @adapter: board private structure to initialize
883 *
884 * This function maps descriptor rings to the queue-specific vectors
885 * we were allotted through the MSI-X enabling code. Ideally, we'd have
886 * one vector per ring/queue, but on a constrained vector budget, we
887 * group the rings as "efficiently" as possible. You would add new
888 * mapping configurations in here.
889 **/
890static int ixgbevf_map_rings_to_vectors(struct ixgbevf_adapter *adapter)
891{
892 int q_vectors;
893 int v_start = 0;
894 int rxr_idx = 0, txr_idx = 0;
895 int rxr_remaining = adapter->num_rx_queues;
896 int txr_remaining = adapter->num_tx_queues;
897 int i, j;
898 int rqpv, tqpv;
899 int err = 0;
900
901 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
902
903 /*
904 * The ideal configuration...
905 * We have enough vectors to map one per queue.
906 */
907 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
908 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
909 map_vector_to_rxq(adapter, v_start, rxr_idx);
910
911 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
912 map_vector_to_txq(adapter, v_start, txr_idx);
913 goto out;
914 }
915
916 /*
917 * If we don't have enough vectors for a 1-to-1
918 * mapping, we'll have to group them so there are
919 * multiple queues per vector.
920 */
921 /* Re-adjusting *qpv takes care of the remainder. */
922 for (i = v_start; i < q_vectors; i++) {
923 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
924 for (j = 0; j < rqpv; j++) {
925 map_vector_to_rxq(adapter, i, rxr_idx);
926 rxr_idx++;
927 rxr_remaining--;
928 }
929 }
930 for (i = v_start; i < q_vectors; i++) {
931 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
932 for (j = 0; j < tqpv; j++) {
933 map_vector_to_txq(adapter, i, txr_idx);
934 txr_idx++;
935 txr_remaining--;
936 }
937 }
938
939out:
940 return err;
941}
942
943/**
944 * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts
945 * @adapter: board private structure
946 *
947 * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests
948 * interrupts from the kernel.
949 **/
950static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter)
951{
952 struct net_device *netdev = adapter->netdev;
fa71ae27
AD
953 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
954 int vector, err;
92915f71
GR
955 int ri = 0, ti = 0;
956
92915f71 957 for (vector = 0; vector < q_vectors; vector++) {
fa71ae27
AD
958 struct ixgbevf_q_vector *q_vector = adapter->q_vector[vector];
959 struct msix_entry *entry = &adapter->msix_entries[vector];
960
961 if (q_vector->tx.ring && q_vector->rx.ring) {
962 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
963 "%s-%s-%d", netdev->name, "TxRx", ri++);
964 ti++;
965 } else if (q_vector->rx.ring) {
966 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
967 "%s-%s-%d", netdev->name, "rx", ri++);
968 } else if (q_vector->tx.ring) {
969 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
970 "%s-%s-%d", netdev->name, "tx", ti++);
92915f71
GR
971 } else {
972 /* skip this unused q_vector */
973 continue;
974 }
fa71ae27
AD
975 err = request_irq(entry->vector, &ixgbevf_msix_clean_rings, 0,
976 q_vector->name, q_vector);
92915f71
GR
977 if (err) {
978 hw_dbg(&adapter->hw,
979 "request_irq failed for MSIX interrupt "
980 "Error: %d\n", err);
981 goto free_queue_irqs;
982 }
983 }
984
92915f71 985 err = request_irq(adapter->msix_entries[vector].vector,
4b2cd27f 986 &ixgbevf_msix_other, 0, netdev->name, adapter);
92915f71
GR
987 if (err) {
988 hw_dbg(&adapter->hw,
4b2cd27f 989 "request_irq for msix_other failed: %d\n", err);
92915f71
GR
990 goto free_queue_irqs;
991 }
992
993 return 0;
994
995free_queue_irqs:
fa71ae27
AD
996 while (vector) {
997 vector--;
998 free_irq(adapter->msix_entries[vector].vector,
999 adapter->q_vector[vector]);
1000 }
a1f6c6b1 1001 /* This failure is non-recoverable - it indicates the system is
1002 * out of MSIX vector resources and the VF driver cannot run
1003 * without them. Set the number of msix vectors to zero
1004 * indicating that not enough can be allocated. The error
1005 * will be returned to the user indicating device open failed.
1006 * Any further attempts to force the driver to open will also
1007 * fail. The only way to recover is to unload the driver and
1008 * reload it again. If the system has recovered some MSIX
1009 * vectors then it may succeed.
1010 */
1011 adapter->num_msix_vectors = 0;
92915f71
GR
1012 return err;
1013}
1014
1015static inline void ixgbevf_reset_q_vectors(struct ixgbevf_adapter *adapter)
1016{
1017 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1018
1019 for (i = 0; i < q_vectors; i++) {
1020 struct ixgbevf_q_vector *q_vector = adapter->q_vector[i];
6b43c446
AD
1021 q_vector->rx.ring = NULL;
1022 q_vector->tx.ring = NULL;
1023 q_vector->rx.count = 0;
1024 q_vector->tx.count = 0;
92915f71
GR
1025 }
1026}
1027
1028/**
1029 * ixgbevf_request_irq - initialize interrupts
1030 * @adapter: board private structure
1031 *
1032 * Attempts to configure interrupts using the best available
1033 * capabilities of the hardware and kernel.
1034 **/
1035static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter)
1036{
1037 int err = 0;
1038
1039 err = ixgbevf_request_msix_irqs(adapter);
1040
1041 if (err)
1042 hw_dbg(&adapter->hw,
1043 "request_irq failed, Error %d\n", err);
1044
1045 return err;
1046}
1047
1048static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter)
1049{
92915f71
GR
1050 int i, q_vectors;
1051
1052 q_vectors = adapter->num_msix_vectors;
92915f71
GR
1053 i = q_vectors - 1;
1054
fa71ae27 1055 free_irq(adapter->msix_entries[i].vector, adapter);
92915f71
GR
1056 i--;
1057
1058 for (; i >= 0; i--) {
fa71ae27
AD
1059 /* free only the irqs that were actually requested */
1060 if (!adapter->q_vector[i]->rx.ring &&
1061 !adapter->q_vector[i]->tx.ring)
1062 continue;
1063
92915f71
GR
1064 free_irq(adapter->msix_entries[i].vector,
1065 adapter->q_vector[i]);
1066 }
1067
1068 ixgbevf_reset_q_vectors(adapter);
1069}
1070
1071/**
1072 * ixgbevf_irq_disable - Mask off interrupt generation on the NIC
1073 * @adapter: board private structure
1074 **/
1075static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter)
1076{
92915f71 1077 struct ixgbe_hw *hw = &adapter->hw;
5f3600eb 1078 int i;
92915f71 1079
5f3600eb 1080 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, 0);
92915f71 1081 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0);
5f3600eb 1082 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, 0);
92915f71
GR
1083
1084 IXGBE_WRITE_FLUSH(hw);
1085
1086 for (i = 0; i < adapter->num_msix_vectors; i++)
1087 synchronize_irq(adapter->msix_entries[i].vector);
1088}
1089
1090/**
1091 * ixgbevf_irq_enable - Enable default interrupt generation settings
1092 * @adapter: board private structure
1093 **/
5f3600eb 1094static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter)
92915f71
GR
1095{
1096 struct ixgbe_hw *hw = &adapter->hw;
92915f71 1097
5f3600eb
AD
1098 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, adapter->eims_enable_mask);
1099 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, adapter->eims_enable_mask);
1100 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_enable_mask);
92915f71
GR
1101}
1102
de02decb
DS
1103/**
1104 * ixgbevf_configure_tx_ring - Configure 82599 VF Tx ring after Reset
1105 * @adapter: board private structure
1106 * @ring: structure containing ring specific data
1107 *
1108 * Configure the Tx descriptor ring after a reset.
1109 **/
1110static void ixgbevf_configure_tx_ring(struct ixgbevf_adapter *adapter,
1111 struct ixgbevf_ring *ring)
1112{
1113 struct ixgbe_hw *hw = &adapter->hw;
1114 u64 tdba = ring->dma;
1115 int wait_loop = 10;
1116 u32 txdctl = IXGBE_TXDCTL_ENABLE;
1117 u8 reg_idx = ring->reg_idx;
1118
1119 /* disable queue to avoid issues while updating state */
1120 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
1121 IXGBE_WRITE_FLUSH(hw);
1122
1123 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
1124 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32);
1125 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(reg_idx),
1126 ring->count * sizeof(union ixgbe_adv_tx_desc));
1127
1128 /* disable head writeback */
1129 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(reg_idx), 0);
1130 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(reg_idx), 0);
1131
1132 /* enable relaxed ordering */
1133 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(reg_idx),
1134 (IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1135 IXGBE_DCA_TXCTRL_DATA_RRO_EN));
1136
1137 /* reset head and tail pointers */
1138 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(reg_idx), 0);
1139 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(reg_idx), 0);
1140 ring->tail = hw->hw_addr + IXGBE_VFTDT(reg_idx);
1141
1142 /* reset ntu and ntc to place SW in sync with hardwdare */
1143 ring->next_to_clean = 0;
1144 ring->next_to_use = 0;
1145
1146 /* In order to avoid issues WTHRESH + PTHRESH should always be equal
1147 * to or less than the number of on chip descriptors, which is
1148 * currently 40.
1149 */
1150 txdctl |= (8 << 16); /* WTHRESH = 8 */
1151
1152 /* Setting PTHRESH to 32 both improves performance */
1153 txdctl |= (1 << 8) | /* HTHRESH = 1 */
1154 32; /* PTHRESH = 32 */
1155
1156 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), txdctl);
1157
1158 /* poll to verify queue is enabled */
1159 do {
1160 usleep_range(1000, 2000);
1161 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(reg_idx));
1162 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
1163 if (!wait_loop)
1164 pr_err("Could not enable Tx Queue %d\n", reg_idx);
1165}
1166
92915f71
GR
1167/**
1168 * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset
1169 * @adapter: board private structure
1170 *
1171 * Configure the Tx unit of the MAC after a reset.
1172 **/
1173static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter)
1174{
de02decb 1175 u32 i;
92915f71
GR
1176
1177 /* Setup the HW Tx Head and Tail descriptor pointers */
de02decb
DS
1178 for (i = 0; i < adapter->num_tx_queues; i++)
1179 ixgbevf_configure_tx_ring(adapter, adapter->tx_ring[i]);
92915f71
GR
1180}
1181
1182#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1183
1184static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, int index)
1185{
1186 struct ixgbevf_ring *rx_ring;
1187 struct ixgbe_hw *hw = &adapter->hw;
1188 u32 srrctl;
1189
87e70ab9 1190 rx_ring = adapter->rx_ring[index];
92915f71
GR
1191
1192 srrctl = IXGBE_SRRCTL_DROP_EN;
1193
77d5dfca 1194 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
92915f71 1195
dd1fe113
AD
1196 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1197 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1198
92915f71
GR
1199 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl);
1200}
1201
1bb9c639
DS
1202static void ixgbevf_setup_psrtype(struct ixgbevf_adapter *adapter)
1203{
1204 struct ixgbe_hw *hw = &adapter->hw;
1205
1206 /* PSRTYPE must be initialized in 82599 */
1207 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
1208 IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR |
1209 IXGBE_PSRTYPE_L2HDR;
1210
1211 if (adapter->num_rx_queues > 1)
1212 psrtype |= 1 << 29;
1213
1214 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
1215}
1216
dd1fe113
AD
1217static void ixgbevf_set_rx_buffer_len(struct ixgbevf_adapter *adapter)
1218{
1219 struct ixgbe_hw *hw = &adapter->hw;
1220 struct net_device *netdev = adapter->netdev;
1221 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1222 int i;
1223 u16 rx_buf_len;
1224
1225 /* notify the PF of our intent to use this size of frame */
1226 ixgbevf_rlpml_set_vf(hw, max_frame);
1227
1228 /* PF will allow an extra 4 bytes past for vlan tagged frames */
1229 max_frame += VLAN_HLEN;
1230
1231 /*
85624caf
GR
1232 * Allocate buffer sizes that fit well into 32K and
1233 * take into account max frame size of 9.5K
dd1fe113
AD
1234 */
1235 if ((hw->mac.type == ixgbe_mac_X540_vf) &&
1236 (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE))
1237 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85624caf
GR
1238 else if (max_frame <= IXGBEVF_RXBUFFER_2K)
1239 rx_buf_len = IXGBEVF_RXBUFFER_2K;
1240 else if (max_frame <= IXGBEVF_RXBUFFER_4K)
1241 rx_buf_len = IXGBEVF_RXBUFFER_4K;
1242 else if (max_frame <= IXGBEVF_RXBUFFER_8K)
1243 rx_buf_len = IXGBEVF_RXBUFFER_8K;
dd1fe113 1244 else
85624caf 1245 rx_buf_len = IXGBEVF_RXBUFFER_10K;
dd1fe113
AD
1246
1247 for (i = 0; i < adapter->num_rx_queues; i++)
87e70ab9 1248 adapter->rx_ring[i]->rx_buf_len = rx_buf_len;
dd1fe113
AD
1249}
1250
de02decb
DS
1251#define IXGBEVF_MAX_RX_DESC_POLL 10
1252static void ixgbevf_disable_rx_queue(struct ixgbevf_adapter *adapter,
1253 struct ixgbevf_ring *ring)
1254{
1255 struct ixgbe_hw *hw = &adapter->hw;
1256 int wait_loop = IXGBEVF_MAX_RX_DESC_POLL;
1257 u32 rxdctl;
1258 u8 reg_idx = ring->reg_idx;
1259
1260 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));
1261 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
1262
1263 /* write value back with RXDCTL.ENABLE bit cleared */
1264 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl);
1265
1266 /* the hardware may take up to 100us to really disable the rx queue */
1267 do {
1268 udelay(10);
1269 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));
1270 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
1271
1272 if (!wait_loop)
1273 pr_err("RXDCTL.ENABLE queue %d not cleared while polling\n",
1274 reg_idx);
1275}
1276
1277static void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter,
1278 struct ixgbevf_ring *ring)
1279{
1280 struct ixgbe_hw *hw = &adapter->hw;
1281 int wait_loop = IXGBEVF_MAX_RX_DESC_POLL;
1282 u32 rxdctl;
1283 u8 reg_idx = ring->reg_idx;
1284
1285 do {
1286 usleep_range(1000, 2000);
1287 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));
1288 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
1289
1290 if (!wait_loop)
1291 pr_err("RXDCTL.ENABLE queue %d not set while polling\n",
1292 reg_idx);
1293}
1294
1295static void ixgbevf_configure_rx_ring(struct ixgbevf_adapter *adapter,
1296 struct ixgbevf_ring *ring)
1297{
1298 struct ixgbe_hw *hw = &adapter->hw;
1299 u64 rdba = ring->dma;
1300 u32 rxdctl;
1301 u8 reg_idx = ring->reg_idx;
1302
1303 /* disable queue to avoid issues while updating state */
1304 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx));
1305 ixgbevf_disable_rx_queue(adapter, ring);
1306
1307 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(reg_idx), rdba & DMA_BIT_MASK(32));
1308 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(reg_idx), rdba >> 32);
1309 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(reg_idx),
1310 ring->count * sizeof(union ixgbe_adv_rx_desc));
1311
1312 /* enable relaxed ordering */
1313 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx),
1314 IXGBE_DCA_RXCTRL_DESC_RRO_EN);
1315
1316 /* reset head and tail pointers */
1317 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(reg_idx), 0);
1318 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(reg_idx), 0);
1319 ring->tail = hw->hw_addr + IXGBE_VFRDT(reg_idx);
1320
1321 /* reset ntu and ntc to place SW in sync with hardwdare */
1322 ring->next_to_clean = 0;
1323 ring->next_to_use = 0;
1324
1325 ixgbevf_configure_srrctl(adapter, reg_idx);
1326
1327 /* prevent DMA from exceeding buffer space available */
1328 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
1329 rxdctl |= ring->rx_buf_len | IXGBE_RXDCTL_RLPML_EN;
1330 rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME;
1331 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl);
1332
1333 ixgbevf_rx_desc_queue_enable(adapter, ring);
095e2617 1334 ixgbevf_alloc_rx_buffers(ring, ixgbevf_desc_unused(ring));
de02decb
DS
1335}
1336
92915f71
GR
1337/**
1338 * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset
1339 * @adapter: board private structure
1340 *
1341 * Configure the Rx unit of the MAC after a reset.
1342 **/
1343static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter)
1344{
de02decb 1345 int i;
92915f71 1346
1bb9c639 1347 ixgbevf_setup_psrtype(adapter);
dd1fe113
AD
1348
1349 /* set_rx_buffer_len must be called before ring initialization */
1350 ixgbevf_set_rx_buffer_len(adapter);
92915f71 1351
92915f71
GR
1352 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1353 * the Base and Length of the Rx Descriptor Ring */
de02decb
DS
1354 for (i = 0; i < adapter->num_rx_queues; i++)
1355 ixgbevf_configure_rx_ring(adapter, adapter->rx_ring[i]);
92915f71
GR
1356}
1357
80d5c368
PM
1358static int ixgbevf_vlan_rx_add_vid(struct net_device *netdev,
1359 __be16 proto, u16 vid)
92915f71
GR
1360{
1361 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1362 struct ixgbe_hw *hw = &adapter->hw;
2ddc7fe1
AD
1363 int err;
1364
55fdd45b 1365 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1366
92915f71 1367 /* add VID to filter table */
2ddc7fe1 1368 err = hw->mac.ops.set_vfta(hw, vid, 0, true);
1c55ed76 1369
55fdd45b 1370 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 1371
2ddc7fe1
AD
1372 /* translate error return types so error makes sense */
1373 if (err == IXGBE_ERR_MBX)
1374 return -EIO;
1375
1376 if (err == IXGBE_ERR_INVALID_ARGUMENT)
1377 return -EACCES;
1378
dadcd65f 1379 set_bit(vid, adapter->active_vlans);
8e586137 1380
2ddc7fe1 1381 return err;
92915f71
GR
1382}
1383
80d5c368
PM
1384static int ixgbevf_vlan_rx_kill_vid(struct net_device *netdev,
1385 __be16 proto, u16 vid)
92915f71
GR
1386{
1387 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1388 struct ixgbe_hw *hw = &adapter->hw;
2ddc7fe1 1389 int err = -EOPNOTSUPP;
92915f71 1390
55fdd45b 1391 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1392
92915f71 1393 /* remove VID from filter table */
92fe0bf7 1394 err = hw->mac.ops.set_vfta(hw, vid, 0, false);
1c55ed76 1395
55fdd45b 1396 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 1397
dadcd65f 1398 clear_bit(vid, adapter->active_vlans);
8e586137 1399
2ddc7fe1 1400 return err;
92915f71
GR
1401}
1402
1403static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter)
1404{
dadcd65f 1405 u16 vid;
92915f71 1406
dadcd65f 1407 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368
PM
1408 ixgbevf_vlan_rx_add_vid(adapter->netdev,
1409 htons(ETH_P_8021Q), vid);
92915f71
GR
1410}
1411
46ec20ff
GR
1412static int ixgbevf_write_uc_addr_list(struct net_device *netdev)
1413{
1414 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1415 struct ixgbe_hw *hw = &adapter->hw;
1416 int count = 0;
1417
1418 if ((netdev_uc_count(netdev)) > 10) {
dbd9636e 1419 pr_err("Too many unicast filters - No Space\n");
46ec20ff
GR
1420 return -ENOSPC;
1421 }
1422
1423 if (!netdev_uc_empty(netdev)) {
1424 struct netdev_hw_addr *ha;
1425 netdev_for_each_uc_addr(ha, netdev) {
1426 hw->mac.ops.set_uc_addr(hw, ++count, ha->addr);
1427 udelay(200);
1428 }
1429 } else {
1430 /*
1431 * If the list is empty then send message to PF driver to
1432 * clear all macvlans on this VF.
1433 */
1434 hw->mac.ops.set_uc_addr(hw, 0, NULL);
1435 }
1436
1437 return count;
1438}
1439
92915f71 1440/**
dee847f5 1441 * ixgbevf_set_rx_mode - Multicast and unicast set
92915f71
GR
1442 * @netdev: network interface device structure
1443 *
1444 * The set_rx_method entry point is called whenever the multicast address
dee847f5
GR
1445 * list, unicast address list or the network interface flags are updated.
1446 * This routine is responsible for configuring the hardware for proper
1447 * multicast mode and configuring requested unicast filters.
92915f71
GR
1448 **/
1449static void ixgbevf_set_rx_mode(struct net_device *netdev)
1450{
1451 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1452 struct ixgbe_hw *hw = &adapter->hw;
92915f71 1453
55fdd45b 1454 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1455
92915f71 1456 /* reprogram multicast list */
92fe0bf7 1457 hw->mac.ops.update_mc_addr_list(hw, netdev);
46ec20ff
GR
1458
1459 ixgbevf_write_uc_addr_list(netdev);
1c55ed76 1460
55fdd45b 1461 spin_unlock_bh(&adapter->mbx_lock);
92915f71
GR
1462}
1463
1464static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter)
1465{
1466 int q_idx;
1467 struct ixgbevf_q_vector *q_vector;
1468 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1469
1470 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
92915f71 1471 q_vector = adapter->q_vector[q_idx];
c777cdfa
JK
1472#ifdef CONFIG_NET_RX_BUSY_POLL
1473 ixgbevf_qv_init_lock(adapter->q_vector[q_idx]);
1474#endif
fa71ae27 1475 napi_enable(&q_vector->napi);
92915f71
GR
1476 }
1477}
1478
1479static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter)
1480{
1481 int q_idx;
1482 struct ixgbevf_q_vector *q_vector;
1483 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1484
1485 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1486 q_vector = adapter->q_vector[q_idx];
92915f71 1487 napi_disable(&q_vector->napi);
c777cdfa
JK
1488#ifdef CONFIG_NET_RX_BUSY_POLL
1489 while (!ixgbevf_qv_disable(adapter->q_vector[q_idx])) {
1490 pr_info("QV %d locked\n", q_idx);
1491 usleep_range(1000, 20000);
1492 }
1493#endif /* CONFIG_NET_RX_BUSY_POLL */
92915f71
GR
1494 }
1495}
1496
220fe050
DS
1497static int ixgbevf_configure_dcb(struct ixgbevf_adapter *adapter)
1498{
1499 struct ixgbe_hw *hw = &adapter->hw;
1500 unsigned int def_q = 0;
1501 unsigned int num_tcs = 0;
1502 unsigned int num_rx_queues = 1;
1503 int err;
1504
1505 spin_lock_bh(&adapter->mbx_lock);
1506
1507 /* fetch queue configuration from the PF */
1508 err = ixgbevf_get_queues(hw, &num_tcs, &def_q);
1509
1510 spin_unlock_bh(&adapter->mbx_lock);
1511
1512 if (err)
1513 return err;
1514
1515 if (num_tcs > 1) {
1516 /* update default Tx ring register index */
87e70ab9 1517 adapter->tx_ring[0]->reg_idx = def_q;
220fe050
DS
1518
1519 /* we need as many queues as traffic classes */
1520 num_rx_queues = num_tcs;
1521 }
1522
1523 /* if we have a bad config abort request queue reset */
1524 if (adapter->num_rx_queues != num_rx_queues) {
1525 /* force mailbox timeout to prevent further messages */
1526 hw->mbx.timeout = 0;
1527
1528 /* wait for watchdog to come around and bail us out */
1529 adapter->flags |= IXGBEVF_FLAG_QUEUE_RESET_REQUESTED;
1530 }
1531
1532 return 0;
1533}
1534
92915f71
GR
1535static void ixgbevf_configure(struct ixgbevf_adapter *adapter)
1536{
220fe050
DS
1537 ixgbevf_configure_dcb(adapter);
1538
de02decb 1539 ixgbevf_set_rx_mode(adapter->netdev);
92915f71
GR
1540
1541 ixgbevf_restore_vlan(adapter);
1542
1543 ixgbevf_configure_tx(adapter);
1544 ixgbevf_configure_rx(adapter);
92915f71
GR
1545}
1546
33bd9f60
GR
1547static void ixgbevf_save_reset_stats(struct ixgbevf_adapter *adapter)
1548{
1549 /* Only save pre-reset stats if there are some */
1550 if (adapter->stats.vfgprc || adapter->stats.vfgptc) {
1551 adapter->stats.saved_reset_vfgprc += adapter->stats.vfgprc -
1552 adapter->stats.base_vfgprc;
1553 adapter->stats.saved_reset_vfgptc += adapter->stats.vfgptc -
1554 adapter->stats.base_vfgptc;
1555 adapter->stats.saved_reset_vfgorc += adapter->stats.vfgorc -
1556 adapter->stats.base_vfgorc;
1557 adapter->stats.saved_reset_vfgotc += adapter->stats.vfgotc -
1558 adapter->stats.base_vfgotc;
1559 adapter->stats.saved_reset_vfmprc += adapter->stats.vfmprc -
1560 adapter->stats.base_vfmprc;
1561 }
1562}
1563
1564static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter)
1565{
1566 struct ixgbe_hw *hw = &adapter->hw;
1567
1568 adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC);
1569 adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB);
1570 adapter->stats.last_vfgorc |=
1571 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32);
1572 adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC);
1573 adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB);
1574 adapter->stats.last_vfgotc |=
1575 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32);
1576 adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC);
1577
1578 adapter->stats.base_vfgprc = adapter->stats.last_vfgprc;
1579 adapter->stats.base_vfgorc = adapter->stats.last_vfgorc;
1580 adapter->stats.base_vfgptc = adapter->stats.last_vfgptc;
1581 adapter->stats.base_vfgotc = adapter->stats.last_vfgotc;
1582 adapter->stats.base_vfmprc = adapter->stats.last_vfmprc;
1583}
1584
31186785
AD
1585static void ixgbevf_negotiate_api(struct ixgbevf_adapter *adapter)
1586{
1587 struct ixgbe_hw *hw = &adapter->hw;
56e94095
AD
1588 int api[] = { ixgbe_mbox_api_11,
1589 ixgbe_mbox_api_10,
31186785
AD
1590 ixgbe_mbox_api_unknown };
1591 int err = 0, idx = 0;
1592
55fdd45b 1593 spin_lock_bh(&adapter->mbx_lock);
31186785
AD
1594
1595 while (api[idx] != ixgbe_mbox_api_unknown) {
1596 err = ixgbevf_negotiate_api_version(hw, api[idx]);
1597 if (!err)
1598 break;
1599 idx++;
1600 }
1601
55fdd45b 1602 spin_unlock_bh(&adapter->mbx_lock);
31186785
AD
1603}
1604
795180d8 1605static void ixgbevf_up_complete(struct ixgbevf_adapter *adapter)
92915f71
GR
1606{
1607 struct net_device *netdev = adapter->netdev;
1608 struct ixgbe_hw *hw = &adapter->hw;
92915f71
GR
1609
1610 ixgbevf_configure_msix(adapter);
1611
55fdd45b 1612 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 1613
92fe0bf7
GR
1614 if (is_valid_ether_addr(hw->mac.addr))
1615 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
1616 else
1617 hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0);
92915f71 1618
55fdd45b 1619 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 1620
92915f71
GR
1621 clear_bit(__IXGBEVF_DOWN, &adapter->state);
1622 ixgbevf_napi_enable_all(adapter);
1623
1624 /* enable transmits */
1625 netif_tx_start_all_queues(netdev);
1626
33bd9f60
GR
1627 ixgbevf_save_reset_stats(adapter);
1628 ixgbevf_init_last_counter_stats(adapter);
1629
4b2cd27f 1630 hw->mac.get_link_status = 1;
92915f71 1631 mod_timer(&adapter->watchdog_timer, jiffies);
92915f71
GR
1632}
1633
795180d8 1634void ixgbevf_up(struct ixgbevf_adapter *adapter)
92915f71 1635{
92915f71
GR
1636 struct ixgbe_hw *hw = &adapter->hw;
1637
1638 ixgbevf_configure(adapter);
1639
795180d8 1640 ixgbevf_up_complete(adapter);
92915f71
GR
1641
1642 /* clear any pending interrupts, may auto mask */
1643 IXGBE_READ_REG(hw, IXGBE_VTEICR);
1644
5f3600eb 1645 ixgbevf_irq_enable(adapter);
92915f71
GR
1646}
1647
1648/**
1649 * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue
92915f71
GR
1650 * @rx_ring: ring to free buffers from
1651 **/
05d063aa 1652static void ixgbevf_clean_rx_ring(struct ixgbevf_ring *rx_ring)
92915f71 1653{
92915f71
GR
1654 unsigned long size;
1655 unsigned int i;
1656
c0456c23
GR
1657 if (!rx_ring->rx_buffer_info)
1658 return;
92915f71 1659
c0456c23 1660 /* Free all the Rx ring sk_buffs */
92915f71
GR
1661 for (i = 0; i < rx_ring->count; i++) {
1662 struct ixgbevf_rx_buffer *rx_buffer_info;
1663
1664 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1665 if (rx_buffer_info->dma) {
05d063aa 1666 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
92915f71 1667 rx_ring->rx_buf_len,
2a1f8794 1668 DMA_FROM_DEVICE);
92915f71
GR
1669 rx_buffer_info->dma = 0;
1670 }
1671 if (rx_buffer_info->skb) {
1672 struct sk_buff *skb = rx_buffer_info->skb;
1673 rx_buffer_info->skb = NULL;
1674 do {
1675 struct sk_buff *this = skb;
5c60f81a 1676 skb = IXGBE_CB(skb)->prev;
92915f71
GR
1677 dev_kfree_skb(this);
1678 } while (skb);
1679 }
92915f71
GR
1680 }
1681
1682 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
1683 memset(rx_ring->rx_buffer_info, 0, size);
1684
1685 /* Zero out the descriptor ring */
1686 memset(rx_ring->desc, 0, rx_ring->size);
92915f71
GR
1687}
1688
1689/**
1690 * ixgbevf_clean_tx_ring - Free Tx Buffers
92915f71
GR
1691 * @tx_ring: ring to be cleaned
1692 **/
05d063aa 1693static void ixgbevf_clean_tx_ring(struct ixgbevf_ring *tx_ring)
92915f71
GR
1694{
1695 struct ixgbevf_tx_buffer *tx_buffer_info;
1696 unsigned long size;
1697 unsigned int i;
1698
c0456c23
GR
1699 if (!tx_ring->tx_buffer_info)
1700 return;
1701
92915f71 1702 /* Free all the Tx ring sk_buffs */
92915f71
GR
1703 for (i = 0; i < tx_ring->count; i++) {
1704 tx_buffer_info = &tx_ring->tx_buffer_info[i];
70a10e25 1705 ixgbevf_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
92915f71
GR
1706 }
1707
1708 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
1709 memset(tx_ring->tx_buffer_info, 0, size);
1710
1711 memset(tx_ring->desc, 0, tx_ring->size);
92915f71
GR
1712}
1713
1714/**
1715 * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues
1716 * @adapter: board private structure
1717 **/
1718static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter)
1719{
1720 int i;
1721
1722 for (i = 0; i < adapter->num_rx_queues; i++)
05d063aa 1723 ixgbevf_clean_rx_ring(adapter->rx_ring[i]);
92915f71
GR
1724}
1725
1726/**
1727 * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues
1728 * @adapter: board private structure
1729 **/
1730static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter)
1731{
1732 int i;
1733
1734 for (i = 0; i < adapter->num_tx_queues; i++)
05d063aa 1735 ixgbevf_clean_tx_ring(adapter->tx_ring[i]);
92915f71
GR
1736}
1737
1738void ixgbevf_down(struct ixgbevf_adapter *adapter)
1739{
1740 struct net_device *netdev = adapter->netdev;
1741 struct ixgbe_hw *hw = &adapter->hw;
de02decb 1742 int i;
92915f71
GR
1743
1744 /* signal that we are down to the interrupt handler */
1745 set_bit(__IXGBEVF_DOWN, &adapter->state);
858c3dda
DS
1746
1747 /* disable all enabled rx queues */
1748 for (i = 0; i < adapter->num_rx_queues; i++)
87e70ab9 1749 ixgbevf_disable_rx_queue(adapter, adapter->rx_ring[i]);
92915f71
GR
1750
1751 netif_tx_disable(netdev);
1752
1753 msleep(10);
1754
1755 netif_tx_stop_all_queues(netdev);
1756
1757 ixgbevf_irq_disable(adapter);
1758
1759 ixgbevf_napi_disable_all(adapter);
1760
1761 del_timer_sync(&adapter->watchdog_timer);
1762 /* can't call flush scheduled work here because it can deadlock
1763 * if linkwatch_event tries to acquire the rtnl_lock which we are
1764 * holding */
1765 while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK)
1766 msleep(1);
1767
1768 /* disable transmits in the hardware now that interrupts are off */
1769 for (i = 0; i < adapter->num_tx_queues; i++) {
de02decb
DS
1770 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
1771
1772 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx),
1773 IXGBE_TXDCTL_SWFLSH);
92915f71
GR
1774 }
1775
1776 netif_carrier_off(netdev);
1777
1778 if (!pci_channel_offline(adapter->pdev))
1779 ixgbevf_reset(adapter);
1780
1781 ixgbevf_clean_all_tx_rings(adapter);
1782 ixgbevf_clean_all_rx_rings(adapter);
1783}
1784
1785void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter)
1786{
1787 WARN_ON(in_interrupt());
c0456c23 1788
92915f71
GR
1789 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
1790 msleep(1);
1791
4b2cd27f
AD
1792 ixgbevf_down(adapter);
1793 ixgbevf_up(adapter);
92915f71
GR
1794
1795 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
1796}
1797
1798void ixgbevf_reset(struct ixgbevf_adapter *adapter)
1799{
1800 struct ixgbe_hw *hw = &adapter->hw;
1801 struct net_device *netdev = adapter->netdev;
1802
798e381a 1803 if (hw->mac.ops.reset_hw(hw)) {
92915f71 1804 hw_dbg(hw, "PF still resetting\n");
798e381a 1805 } else {
92915f71 1806 hw->mac.ops.init_hw(hw);
798e381a
DS
1807 ixgbevf_negotiate_api(adapter);
1808 }
92915f71
GR
1809
1810 if (is_valid_ether_addr(adapter->hw.mac.addr)) {
1811 memcpy(netdev->dev_addr, adapter->hw.mac.addr,
1812 netdev->addr_len);
1813 memcpy(netdev->perm_addr, adapter->hw.mac.addr,
1814 netdev->addr_len);
1815 }
1816}
1817
e45dd5fe
JK
1818static int ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter,
1819 int vectors)
92915f71 1820{
a5f9337b 1821 int vector_threshold;
92915f71 1822
fa71ae27
AD
1823 /* We'll want at least 2 (vector_threshold):
1824 * 1) TxQ[0] + RxQ[0] handler
1825 * 2) Other (Link Status Change, etc.)
92915f71
GR
1826 */
1827 vector_threshold = MIN_MSIX_COUNT;
1828
1829 /* The more we get, the more we will assign to Tx/Rx Cleanup
1830 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1831 * Right now, we simply care about how many we'll get; we'll
1832 * set them up later while requesting irq's.
1833 */
5c1e3588
AG
1834 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries,
1835 vector_threshold, vectors);
92915f71 1836
5c1e3588 1837 if (vectors < 0) {
e45dd5fe
JK
1838 dev_err(&adapter->pdev->dev,
1839 "Unable to allocate MSI-X interrupts\n");
92915f71
GR
1840 kfree(adapter->msix_entries);
1841 adapter->msix_entries = NULL;
5c1e3588 1842 return vectors;
92915f71 1843 }
dee847f5 1844
5c1e3588
AG
1845 /* Adjust for only the vectors we'll use, which is minimum
1846 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
1847 * vectors we were allocated.
1848 */
1849 adapter->num_msix_vectors = vectors;
1850
1851 return 0;
92915f71
GR
1852}
1853
49ce9c2c
BH
1854/**
1855 * ixgbevf_set_num_queues - Allocate queues for device, feature dependent
92915f71
GR
1856 * @adapter: board private structure to initialize
1857 *
1858 * This is the top level queue allocation routine. The order here is very
1859 * important, starting with the "most" number of features turned on at once,
1860 * and ending with the smallest set of features. This way large combinations
1861 * can be allocated if they're turned on, and smaller combinations are the
1862 * fallthrough conditions.
1863 *
1864 **/
1865static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter)
1866{
220fe050
DS
1867 struct ixgbe_hw *hw = &adapter->hw;
1868 unsigned int def_q = 0;
1869 unsigned int num_tcs = 0;
1870 int err;
1871
92915f71
GR
1872 /* Start with base case */
1873 adapter->num_rx_queues = 1;
1874 adapter->num_tx_queues = 1;
220fe050
DS
1875
1876 spin_lock_bh(&adapter->mbx_lock);
1877
1878 /* fetch queue configuration from the PF */
1879 err = ixgbevf_get_queues(hw, &num_tcs, &def_q);
1880
1881 spin_unlock_bh(&adapter->mbx_lock);
1882
1883 if (err)
1884 return;
1885
1886 /* we need as many queues as traffic classes */
1887 if (num_tcs > 1)
1888 adapter->num_rx_queues = num_tcs;
92915f71
GR
1889}
1890
1891/**
1892 * ixgbevf_alloc_queues - Allocate memory for all rings
1893 * @adapter: board private structure to initialize
1894 *
1895 * We allocate one ring per queue at run-time since we don't know the
1896 * number of queues at compile-time. The polling_netdev array is
1897 * intended for Multiqueue, but should work fine with a single queue.
1898 **/
1899static int ixgbevf_alloc_queues(struct ixgbevf_adapter *adapter)
1900{
87e70ab9
DS
1901 struct ixgbevf_ring *ring;
1902 int rx = 0, tx = 0;
92915f71 1903
87e70ab9
DS
1904 for (; tx < adapter->num_tx_queues; tx++) {
1905 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1906 if (!ring)
1907 goto err_allocation;
92915f71 1908
87e70ab9
DS
1909 ring->dev = &adapter->pdev->dev;
1910 ring->netdev = adapter->netdev;
1911 ring->count = adapter->tx_ring_count;
1912 ring->queue_index = tx;
1913 ring->reg_idx = tx;
92915f71 1914
87e70ab9 1915 adapter->tx_ring[tx] = ring;
92915f71
GR
1916 }
1917
87e70ab9
DS
1918 for (; rx < adapter->num_rx_queues; rx++) {
1919 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1920 if (!ring)
1921 goto err_allocation;
1922
1923 ring->dev = &adapter->pdev->dev;
1924 ring->netdev = adapter->netdev;
1925
1926 ring->count = adapter->rx_ring_count;
1927 ring->queue_index = rx;
1928 ring->reg_idx = rx;
1929
1930 adapter->rx_ring[rx] = ring;
92915f71
GR
1931 }
1932
1933 return 0;
1934
87e70ab9
DS
1935err_allocation:
1936 while (tx) {
1937 kfree(adapter->tx_ring[--tx]);
1938 adapter->tx_ring[tx] = NULL;
1939 }
1940
1941 while (rx) {
1942 kfree(adapter->rx_ring[--rx]);
1943 adapter->rx_ring[rx] = NULL;
1944 }
92915f71
GR
1945 return -ENOMEM;
1946}
1947
1948/**
1949 * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported
1950 * @adapter: board private structure to initialize
1951 *
1952 * Attempt to configure the interrupts using the best available
1953 * capabilities of the hardware and the kernel.
1954 **/
1955static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter)
1956{
91e2b89b 1957 struct net_device *netdev = adapter->netdev;
92915f71
GR
1958 int err = 0;
1959 int vector, v_budget;
1960
1961 /*
1962 * It's easy to be greedy for MSI-X vectors, but it really
1963 * doesn't do us much good if we have a lot more vectors
1964 * than CPU's. So let's be conservative and only ask for
fa71ae27
AD
1965 * (roughly) the same number of vectors as there are CPU's.
1966 * The default is to use pairs of vectors.
92915f71 1967 */
fa71ae27
AD
1968 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
1969 v_budget = min_t(int, v_budget, num_online_cpus());
1970 v_budget += NON_Q_VECTORS;
92915f71
GR
1971
1972 /* A failure in MSI-X entry allocation isn't fatal, but it does
1973 * mean we disable MSI-X capabilities of the adapter. */
1974 adapter->msix_entries = kcalloc(v_budget,
1975 sizeof(struct msix_entry), GFP_KERNEL);
1976 if (!adapter->msix_entries) {
1977 err = -ENOMEM;
1978 goto out;
1979 }
1980
1981 for (vector = 0; vector < v_budget; vector++)
1982 adapter->msix_entries[vector].entry = vector;
1983
e45dd5fe
JK
1984 err = ixgbevf_acquire_msix_vectors(adapter, v_budget);
1985 if (err)
1986 goto out;
92915f71 1987
91e2b89b
GR
1988 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues);
1989 if (err)
1990 goto out;
1991
1992 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues);
1993
92915f71
GR
1994out:
1995 return err;
1996}
1997
1998/**
1999 * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors
2000 * @adapter: board private structure to initialize
2001 *
2002 * We allocate one q_vector per queue interrupt. If allocation fails we
2003 * return -ENOMEM.
2004 **/
2005static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter)
2006{
2007 int q_idx, num_q_vectors;
2008 struct ixgbevf_q_vector *q_vector;
92915f71
GR
2009
2010 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
92915f71
GR
2011
2012 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
2013 q_vector = kzalloc(sizeof(struct ixgbevf_q_vector), GFP_KERNEL);
2014 if (!q_vector)
2015 goto err_out;
2016 q_vector->adapter = adapter;
2017 q_vector->v_idx = q_idx;
fa71ae27
AD
2018 netif_napi_add(adapter->netdev, &q_vector->napi,
2019 ixgbevf_poll, 64);
c777cdfa
JK
2020#ifdef CONFIG_NET_RX_BUSY_POLL
2021 napi_hash_add(&q_vector->napi);
2022#endif
92915f71
GR
2023 adapter->q_vector[q_idx] = q_vector;
2024 }
2025
2026 return 0;
2027
2028err_out:
2029 while (q_idx) {
2030 q_idx--;
2031 q_vector = adapter->q_vector[q_idx];
c777cdfa
JK
2032#ifdef CONFIG_NET_RX_BUSY_POLL
2033 napi_hash_del(&q_vector->napi);
2034#endif
92915f71
GR
2035 netif_napi_del(&q_vector->napi);
2036 kfree(q_vector);
2037 adapter->q_vector[q_idx] = NULL;
2038 }
2039 return -ENOMEM;
2040}
2041
2042/**
2043 * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors
2044 * @adapter: board private structure to initialize
2045 *
2046 * This function frees the memory allocated to the q_vectors. In addition if
2047 * NAPI is enabled it will delete any references to the NAPI struct prior
2048 * to freeing the q_vector.
2049 **/
2050static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter)
2051{
f4477702 2052 int q_idx, num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
92915f71
GR
2053
2054 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
2055 struct ixgbevf_q_vector *q_vector = adapter->q_vector[q_idx];
2056
2057 adapter->q_vector[q_idx] = NULL;
c777cdfa
JK
2058#ifdef CONFIG_NET_RX_BUSY_POLL
2059 napi_hash_del(&q_vector->napi);
2060#endif
f4477702 2061 netif_napi_del(&q_vector->napi);
92915f71
GR
2062 kfree(q_vector);
2063 }
2064}
2065
2066/**
2067 * ixgbevf_reset_interrupt_capability - Reset MSIX setup
2068 * @adapter: board private structure
2069 *
2070 **/
2071static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter)
2072{
2073 pci_disable_msix(adapter->pdev);
2074 kfree(adapter->msix_entries);
2075 adapter->msix_entries = NULL;
92915f71
GR
2076}
2077
2078/**
2079 * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init
2080 * @adapter: board private structure to initialize
2081 *
2082 **/
2083static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter)
2084{
2085 int err;
2086
2087 /* Number of supported queues */
2088 ixgbevf_set_num_queues(adapter);
2089
2090 err = ixgbevf_set_interrupt_capability(adapter);
2091 if (err) {
2092 hw_dbg(&adapter->hw,
2093 "Unable to setup interrupt capabilities\n");
2094 goto err_set_interrupt;
2095 }
2096
2097 err = ixgbevf_alloc_q_vectors(adapter);
2098 if (err) {
2099 hw_dbg(&adapter->hw, "Unable to allocate memory for queue "
2100 "vectors\n");
2101 goto err_alloc_q_vectors;
2102 }
2103
2104 err = ixgbevf_alloc_queues(adapter);
2105 if (err) {
dbd9636e 2106 pr_err("Unable to allocate memory for queues\n");
92915f71
GR
2107 goto err_alloc_queues;
2108 }
2109
2110 hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, "
2111 "Tx Queue count = %u\n",
2112 (adapter->num_rx_queues > 1) ? "Enabled" :
2113 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2114
2115 set_bit(__IXGBEVF_DOWN, &adapter->state);
2116
2117 return 0;
2118err_alloc_queues:
2119 ixgbevf_free_q_vectors(adapter);
2120err_alloc_q_vectors:
2121 ixgbevf_reset_interrupt_capability(adapter);
2122err_set_interrupt:
2123 return err;
2124}
2125
0ac1e8ce
AD
2126/**
2127 * ixgbevf_clear_interrupt_scheme - Clear the current interrupt scheme settings
2128 * @adapter: board private structure to clear interrupt scheme on
2129 *
2130 * We go through and clear interrupt specific resources and reset the structure
2131 * to pre-load conditions
2132 **/
2133static void ixgbevf_clear_interrupt_scheme(struct ixgbevf_adapter *adapter)
2134{
87e70ab9
DS
2135 int i;
2136
2137 for (i = 0; i < adapter->num_tx_queues; i++) {
2138 kfree(adapter->tx_ring[i]);
2139 adapter->tx_ring[i] = NULL;
2140 }
2141 for (i = 0; i < adapter->num_rx_queues; i++) {
2142 kfree(adapter->rx_ring[i]);
2143 adapter->rx_ring[i] = NULL;
2144 }
2145
0ac1e8ce
AD
2146 adapter->num_tx_queues = 0;
2147 adapter->num_rx_queues = 0;
2148
2149 ixgbevf_free_q_vectors(adapter);
2150 ixgbevf_reset_interrupt_capability(adapter);
2151}
2152
92915f71
GR
2153/**
2154 * ixgbevf_sw_init - Initialize general software structures
2155 * (struct ixgbevf_adapter)
2156 * @adapter: board private structure to initialize
2157 *
2158 * ixgbevf_sw_init initializes the Adapter private data structure.
2159 * Fields are initialized based on PCI device information and
2160 * OS network device settings (MTU size).
2161 **/
9f9a12f8 2162static int ixgbevf_sw_init(struct ixgbevf_adapter *adapter)
92915f71
GR
2163{
2164 struct ixgbe_hw *hw = &adapter->hw;
2165 struct pci_dev *pdev = adapter->pdev;
e1941a74 2166 struct net_device *netdev = adapter->netdev;
92915f71
GR
2167 int err;
2168
2169 /* PCI config space info */
2170
2171 hw->vendor_id = pdev->vendor;
2172 hw->device_id = pdev->device;
ff938e43 2173 hw->revision_id = pdev->revision;
92915f71
GR
2174 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2175 hw->subsystem_device_id = pdev->subsystem_device;
2176
2177 hw->mbx.ops.init_params(hw);
56e94095
AD
2178
2179 /* assume legacy case in which PF would only give VF 2 queues */
2180 hw->mac.max_tx_queues = 2;
2181 hw->mac.max_rx_queues = 2;
2182
798e381a
DS
2183 /* lock to protect mailbox accesses */
2184 spin_lock_init(&adapter->mbx_lock);
2185
92915f71
GR
2186 err = hw->mac.ops.reset_hw(hw);
2187 if (err) {
2188 dev_info(&pdev->dev,
e1941a74 2189 "PF still in reset state. Is the PF interface up?\n");
92915f71
GR
2190 } else {
2191 err = hw->mac.ops.init_hw(hw);
2192 if (err) {
dbd9636e 2193 pr_err("init_shared_code failed: %d\n", err);
92915f71
GR
2194 goto out;
2195 }
798e381a 2196 ixgbevf_negotiate_api(adapter);
e1941a74
GR
2197 err = hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2198 if (err)
2199 dev_info(&pdev->dev, "Error reading MAC address\n");
2200 else if (is_zero_ether_addr(adapter->hw.mac.addr))
2201 dev_info(&pdev->dev,
2202 "MAC address not assigned by administrator.\n");
2203 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2204 }
2205
2206 if (!is_valid_ether_addr(netdev->dev_addr)) {
2207 dev_info(&pdev->dev, "Assigning random MAC address\n");
2208 eth_hw_addr_random(netdev);
2209 memcpy(hw->mac.addr, netdev->dev_addr, netdev->addr_len);
92915f71
GR
2210 }
2211
2212 /* Enable dynamic interrupt throttling rates */
5f3600eb
AD
2213 adapter->rx_itr_setting = 1;
2214 adapter->tx_itr_setting = 1;
92915f71 2215
92915f71
GR
2216 /* set default ring sizes */
2217 adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD;
2218 adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD;
2219
92915f71 2220 set_bit(__IXGBEVF_DOWN, &adapter->state);
1a0d6ae5 2221 return 0;
92915f71
GR
2222
2223out:
2224 return err;
2225}
2226
92915f71
GR
2227#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
2228 { \
2229 u32 current_counter = IXGBE_READ_REG(hw, reg); \
2230 if (current_counter < last_counter) \
2231 counter += 0x100000000LL; \
2232 last_counter = current_counter; \
2233 counter &= 0xFFFFFFFF00000000LL; \
2234 counter |= current_counter; \
2235 }
2236
2237#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2238 { \
2239 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
2240 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
2241 u64 current_counter = (current_counter_msb << 32) | \
2242 current_counter_lsb; \
2243 if (current_counter < last_counter) \
2244 counter += 0x1000000000LL; \
2245 last_counter = current_counter; \
2246 counter &= 0xFFFFFFF000000000LL; \
2247 counter |= current_counter; \
2248 }
2249/**
2250 * ixgbevf_update_stats - Update the board statistics counters.
2251 * @adapter: board private structure
2252 **/
2253void ixgbevf_update_stats(struct ixgbevf_adapter *adapter)
2254{
2255 struct ixgbe_hw *hw = &adapter->hw;
55fb277c 2256 int i;
92915f71 2257
088245a3
GR
2258 if (!adapter->link_up)
2259 return;
2260
92915f71
GR
2261 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc,
2262 adapter->stats.vfgprc);
2263 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc,
2264 adapter->stats.vfgptc);
2265 UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2266 adapter->stats.last_vfgorc,
2267 adapter->stats.vfgorc);
2268 UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2269 adapter->stats.last_vfgotc,
2270 adapter->stats.vfgotc);
2271 UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc,
2272 adapter->stats.vfmprc);
55fb277c
GR
2273
2274 for (i = 0; i < adapter->num_rx_queues; i++) {
2275 adapter->hw_csum_rx_error +=
87e70ab9 2276 adapter->rx_ring[i]->hw_csum_rx_error;
87e70ab9 2277 adapter->rx_ring[i]->hw_csum_rx_error = 0;
55fb277c 2278 }
92915f71
GR
2279}
2280
2281/**
2282 * ixgbevf_watchdog - Timer Call-back
2283 * @data: pointer to adapter cast into an unsigned long
2284 **/
2285static void ixgbevf_watchdog(unsigned long data)
2286{
2287 struct ixgbevf_adapter *adapter = (struct ixgbevf_adapter *)data;
2288 struct ixgbe_hw *hw = &adapter->hw;
5f3600eb 2289 u32 eics = 0;
92915f71
GR
2290 int i;
2291
2292 /*
2293 * Do the watchdog outside of interrupt context due to the lovely
2294 * delays that some of the newer hardware requires
2295 */
2296
2297 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
2298 goto watchdog_short_circuit;
2299
2300 /* get one bit for every active tx/rx interrupt vector */
2301 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
2302 struct ixgbevf_q_vector *qv = adapter->q_vector[i];
6b43c446 2303 if (qv->rx.ring || qv->tx.ring)
5f3600eb 2304 eics |= 1 << i;
92915f71
GR
2305 }
2306
5f3600eb 2307 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, eics);
92915f71
GR
2308
2309watchdog_short_circuit:
2310 schedule_work(&adapter->watchdog_task);
2311}
2312
2313/**
2314 * ixgbevf_tx_timeout - Respond to a Tx Hang
2315 * @netdev: network interface device structure
2316 **/
2317static void ixgbevf_tx_timeout(struct net_device *netdev)
2318{
2319 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2320
2321 /* Do the reset outside of interrupt context */
2322 schedule_work(&adapter->reset_task);
2323}
2324
2325static void ixgbevf_reset_task(struct work_struct *work)
2326{
2327 struct ixgbevf_adapter *adapter;
2328 adapter = container_of(work, struct ixgbevf_adapter, reset_task);
2329
2330 /* If we're already down or resetting, just bail */
2331 if (test_bit(__IXGBEVF_DOWN, &adapter->state) ||
2332 test_bit(__IXGBEVF_RESETTING, &adapter->state))
2333 return;
2334
2335 adapter->tx_timeout_count++;
2336
2337 ixgbevf_reinit_locked(adapter);
2338}
2339
2340/**
2341 * ixgbevf_watchdog_task - worker thread to bring link up
2342 * @work: pointer to work_struct containing our data
2343 **/
2344static void ixgbevf_watchdog_task(struct work_struct *work)
2345{
2346 struct ixgbevf_adapter *adapter = container_of(work,
2347 struct ixgbevf_adapter,
2348 watchdog_task);
2349 struct net_device *netdev = adapter->netdev;
2350 struct ixgbe_hw *hw = &adapter->hw;
2351 u32 link_speed = adapter->link_speed;
2352 bool link_up = adapter->link_up;
92fe0bf7 2353 s32 need_reset;
92915f71 2354
220fe050
DS
2355 ixgbevf_queue_reset_subtask(adapter);
2356
92915f71
GR
2357 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
2358
2359 /*
2360 * Always check the link on the watchdog because we have
2361 * no LSC interrupt
2362 */
92fe0bf7 2363 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 2364
92fe0bf7 2365 need_reset = hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1c55ed76 2366
92fe0bf7 2367 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 2368
92fe0bf7
GR
2369 if (need_reset) {
2370 adapter->link_up = link_up;
2371 adapter->link_speed = link_speed;
2372 netif_carrier_off(netdev);
2373 netif_tx_stop_all_queues(netdev);
2374 schedule_work(&adapter->reset_task);
2375 goto pf_has_reset;
92915f71
GR
2376 }
2377 adapter->link_up = link_up;
2378 adapter->link_speed = link_speed;
2379
2380 if (link_up) {
2381 if (!netif_carrier_ok(netdev)) {
b876a744
GR
2382 char *link_speed_string;
2383 switch (link_speed) {
2384 case IXGBE_LINK_SPEED_10GB_FULL:
2385 link_speed_string = "10 Gbps";
2386 break;
2387 case IXGBE_LINK_SPEED_1GB_FULL:
2388 link_speed_string = "1 Gbps";
2389 break;
2390 case IXGBE_LINK_SPEED_100_FULL:
2391 link_speed_string = "100 Mbps";
2392 break;
2393 default:
2394 link_speed_string = "unknown speed";
2395 break;
2396 }
6fe59675 2397 dev_info(&adapter->pdev->dev,
b876a744 2398 "NIC Link is Up, %s\n", link_speed_string);
92915f71
GR
2399 netif_carrier_on(netdev);
2400 netif_tx_wake_all_queues(netdev);
92915f71
GR
2401 }
2402 } else {
2403 adapter->link_up = false;
2404 adapter->link_speed = 0;
2405 if (netif_carrier_ok(netdev)) {
6fe59675 2406 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
92915f71
GR
2407 netif_carrier_off(netdev);
2408 netif_tx_stop_all_queues(netdev);
2409 }
2410 }
2411
92915f71
GR
2412 ixgbevf_update_stats(adapter);
2413
33bd9f60 2414pf_has_reset:
92915f71
GR
2415 /* Reset the timer */
2416 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
2417 mod_timer(&adapter->watchdog_timer,
2418 round_jiffies(jiffies + (2 * HZ)));
2419
2420 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
2421}
2422
2423/**
2424 * ixgbevf_free_tx_resources - Free Tx Resources per Queue
92915f71
GR
2425 * @tx_ring: Tx descriptor ring for a specific queue
2426 *
2427 * Free all transmit software resources
2428 **/
05d063aa 2429void ixgbevf_free_tx_resources(struct ixgbevf_ring *tx_ring)
92915f71 2430{
05d063aa 2431 ixgbevf_clean_tx_ring(tx_ring);
92915f71
GR
2432
2433 vfree(tx_ring->tx_buffer_info);
2434 tx_ring->tx_buffer_info = NULL;
2435
de02decb
DS
2436 /* if not set, then don't free */
2437 if (!tx_ring->desc)
2438 return;
2439
05d063aa 2440 dma_free_coherent(tx_ring->dev, tx_ring->size, tx_ring->desc,
2a1f8794 2441 tx_ring->dma);
92915f71
GR
2442
2443 tx_ring->desc = NULL;
2444}
2445
2446/**
2447 * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues
2448 * @adapter: board private structure
2449 *
2450 * Free all transmit software resources
2451 **/
2452static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter)
2453{
2454 int i;
2455
2456 for (i = 0; i < adapter->num_tx_queues; i++)
87e70ab9 2457 if (adapter->tx_ring[i]->desc)
05d063aa 2458 ixgbevf_free_tx_resources(adapter->tx_ring[i]);
92915f71
GR
2459}
2460
2461/**
2462 * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors)
92915f71
GR
2463 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2464 *
2465 * Return 0 on success, negative on failure
2466 **/
05d063aa 2467int ixgbevf_setup_tx_resources(struct ixgbevf_ring *tx_ring)
92915f71 2468{
92915f71
GR
2469 int size;
2470
2471 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
89bf67f1 2472 tx_ring->tx_buffer_info = vzalloc(size);
92915f71
GR
2473 if (!tx_ring->tx_buffer_info)
2474 goto err;
92915f71
GR
2475
2476 /* round up to nearest 4K */
2477 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2478 tx_ring->size = ALIGN(tx_ring->size, 4096);
2479
05d063aa 2480 tx_ring->desc = dma_alloc_coherent(tx_ring->dev, tx_ring->size,
2a1f8794 2481 &tx_ring->dma, GFP_KERNEL);
92915f71
GR
2482 if (!tx_ring->desc)
2483 goto err;
2484
92915f71
GR
2485 return 0;
2486
2487err:
2488 vfree(tx_ring->tx_buffer_info);
2489 tx_ring->tx_buffer_info = NULL;
2490 hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit "
2491 "descriptor ring\n");
2492 return -ENOMEM;
2493}
2494
2495/**
2496 * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources
2497 * @adapter: board private structure
2498 *
2499 * If this function returns with an error, then it's possible one or
2500 * more of the rings is populated (while the rest are not). It is the
2501 * callers duty to clean those orphaned rings.
2502 *
2503 * Return 0 on success, negative on failure
2504 **/
2505static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter)
2506{
2507 int i, err = 0;
2508
2509 for (i = 0; i < adapter->num_tx_queues; i++) {
05d063aa 2510 err = ixgbevf_setup_tx_resources(adapter->tx_ring[i]);
92915f71
GR
2511 if (!err)
2512 continue;
2513 hw_dbg(&adapter->hw,
2514 "Allocation for Tx Queue %u failed\n", i);
2515 break;
2516 }
2517
2518 return err;
2519}
2520
2521/**
2522 * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors)
92915f71
GR
2523 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2524 *
2525 * Returns 0 on success, negative on failure
2526 **/
05d063aa 2527int ixgbevf_setup_rx_resources(struct ixgbevf_ring *rx_ring)
92915f71 2528{
92915f71
GR
2529 int size;
2530
2531 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
89bf67f1 2532 rx_ring->rx_buffer_info = vzalloc(size);
e404decb 2533 if (!rx_ring->rx_buffer_info)
05d063aa 2534 goto err;
92915f71
GR
2535
2536 /* Round up to nearest 4K */
2537 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2538 rx_ring->size = ALIGN(rx_ring->size, 4096);
2539
05d063aa 2540 rx_ring->desc = dma_alloc_coherent(rx_ring->dev, rx_ring->size,
2a1f8794 2541 &rx_ring->dma, GFP_KERNEL);
92915f71 2542
05d063aa
ET
2543 if (!rx_ring->desc)
2544 goto err;
92915f71 2545
92915f71 2546 return 0;
05d063aa
ET
2547err:
2548 vfree(rx_ring->rx_buffer_info);
2549 rx_ring->rx_buffer_info = NULL;
2550 dev_err(rx_ring->dev, "Unable to allocate memory for the Rx descriptor ring\n");
92915f71
GR
2551 return -ENOMEM;
2552}
2553
2554/**
2555 * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources
2556 * @adapter: board private structure
2557 *
2558 * If this function returns with an error, then it's possible one or
2559 * more of the rings is populated (while the rest are not). It is the
2560 * callers duty to clean those orphaned rings.
2561 *
2562 * Return 0 on success, negative on failure
2563 **/
2564static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter)
2565{
2566 int i, err = 0;
2567
2568 for (i = 0; i < adapter->num_rx_queues; i++) {
05d063aa 2569 err = ixgbevf_setup_rx_resources(adapter->rx_ring[i]);
92915f71
GR
2570 if (!err)
2571 continue;
2572 hw_dbg(&adapter->hw,
2573 "Allocation for Rx Queue %u failed\n", i);
2574 break;
2575 }
2576 return err;
2577}
2578
2579/**
2580 * ixgbevf_free_rx_resources - Free Rx Resources
92915f71
GR
2581 * @rx_ring: ring to clean the resources from
2582 *
2583 * Free all receive software resources
2584 **/
05d063aa 2585void ixgbevf_free_rx_resources(struct ixgbevf_ring *rx_ring)
92915f71 2586{
05d063aa 2587 ixgbevf_clean_rx_ring(rx_ring);
92915f71
GR
2588
2589 vfree(rx_ring->rx_buffer_info);
2590 rx_ring->rx_buffer_info = NULL;
2591
05d063aa 2592 dma_free_coherent(rx_ring->dev, rx_ring->size, rx_ring->desc,
2a1f8794 2593 rx_ring->dma);
92915f71
GR
2594
2595 rx_ring->desc = NULL;
2596}
2597
2598/**
2599 * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues
2600 * @adapter: board private structure
2601 *
2602 * Free all receive software resources
2603 **/
2604static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter)
2605{
2606 int i;
2607
2608 for (i = 0; i < adapter->num_rx_queues; i++)
87e70ab9 2609 if (adapter->rx_ring[i]->desc)
05d063aa 2610 ixgbevf_free_rx_resources(adapter->rx_ring[i]);
92915f71
GR
2611}
2612
2613/**
2614 * ixgbevf_open - Called when a network interface is made active
2615 * @netdev: network interface device structure
2616 *
2617 * Returns 0 on success, negative value on failure
2618 *
2619 * The open entry point is called when a network interface is made
2620 * active by the system (IFF_UP). At this point all resources needed
2621 * for transmit and receive operations are allocated, the interrupt
2622 * handler is registered with the OS, the watchdog timer is started,
2623 * and the stack is notified that the interface is ready.
2624 **/
2625static int ixgbevf_open(struct net_device *netdev)
2626{
2627 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2628 struct ixgbe_hw *hw = &adapter->hw;
2629 int err;
2630
a1f6c6b1 2631 /* A previous failure to open the device because of a lack of
2632 * available MSIX vector resources may have reset the number
2633 * of msix vectors variable to zero. The only way to recover
2634 * is to unload/reload the driver and hope that the system has
2635 * been able to recover some MSIX vector resources.
2636 */
2637 if (!adapter->num_msix_vectors)
2638 return -ENOMEM;
2639
92915f71
GR
2640 /* disallow open during test */
2641 if (test_bit(__IXGBEVF_TESTING, &adapter->state))
2642 return -EBUSY;
2643
2644 if (hw->adapter_stopped) {
2645 ixgbevf_reset(adapter);
2646 /* if adapter is still stopped then PF isn't up and
2647 * the vf can't start. */
2648 if (hw->adapter_stopped) {
2649 err = IXGBE_ERR_MBX;
dbd9636e
JK
2650 pr_err("Unable to start - perhaps the PF Driver isn't "
2651 "up yet\n");
92915f71
GR
2652 goto err_setup_reset;
2653 }
2654 }
2655
2656 /* allocate transmit descriptors */
2657 err = ixgbevf_setup_all_tx_resources(adapter);
2658 if (err)
2659 goto err_setup_tx;
2660
2661 /* allocate receive descriptors */
2662 err = ixgbevf_setup_all_rx_resources(adapter);
2663 if (err)
2664 goto err_setup_rx;
2665
2666 ixgbevf_configure(adapter);
2667
2668 /*
2669 * Map the Tx/Rx rings to the vectors we were allotted.
2670 * if request_irq will be called in this function map_rings
2671 * must be called *before* up_complete
2672 */
2673 ixgbevf_map_rings_to_vectors(adapter);
2674
795180d8 2675 ixgbevf_up_complete(adapter);
92915f71
GR
2676
2677 /* clear any pending interrupts, may auto mask */
2678 IXGBE_READ_REG(hw, IXGBE_VTEICR);
2679 err = ixgbevf_request_irq(adapter);
2680 if (err)
2681 goto err_req_irq;
2682
5f3600eb 2683 ixgbevf_irq_enable(adapter);
92915f71
GR
2684
2685 return 0;
2686
2687err_req_irq:
2688 ixgbevf_down(adapter);
92915f71
GR
2689err_setup_rx:
2690 ixgbevf_free_all_rx_resources(adapter);
2691err_setup_tx:
2692 ixgbevf_free_all_tx_resources(adapter);
2693 ixgbevf_reset(adapter);
2694
2695err_setup_reset:
2696
2697 return err;
2698}
2699
2700/**
2701 * ixgbevf_close - Disables a network interface
2702 * @netdev: network interface device structure
2703 *
2704 * Returns 0, this is not allowed to fail
2705 *
2706 * The close entry point is called when an interface is de-activated
2707 * by the OS. The hardware is still under the drivers control, but
2708 * needs to be disabled. A global MAC reset is issued to stop the
2709 * hardware, and all transmit and receive resources are freed.
2710 **/
2711static int ixgbevf_close(struct net_device *netdev)
2712{
2713 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2714
2715 ixgbevf_down(adapter);
2716 ixgbevf_free_irq(adapter);
2717
2718 ixgbevf_free_all_tx_resources(adapter);
2719 ixgbevf_free_all_rx_resources(adapter);
2720
2721 return 0;
2722}
2723
220fe050
DS
2724static void ixgbevf_queue_reset_subtask(struct ixgbevf_adapter *adapter)
2725{
2726 struct net_device *dev = adapter->netdev;
2727
2728 if (!(adapter->flags & IXGBEVF_FLAG_QUEUE_RESET_REQUESTED))
2729 return;
2730
2731 adapter->flags &= ~IXGBEVF_FLAG_QUEUE_RESET_REQUESTED;
2732
2733 /* if interface is down do nothing */
2734 if (test_bit(__IXGBEVF_DOWN, &adapter->state) ||
2735 test_bit(__IXGBEVF_RESETTING, &adapter->state))
2736 return;
2737
2738 /* Hardware has to reinitialize queues and interrupts to
2739 * match packet buffer alignment. Unfortunately, the
2740 * hardware is not flexible enough to do this dynamically.
2741 */
2742 if (netif_running(dev))
2743 ixgbevf_close(dev);
2744
2745 ixgbevf_clear_interrupt_scheme(adapter);
2746 ixgbevf_init_interrupt_scheme(adapter);
2747
2748 if (netif_running(dev))
2749 ixgbevf_open(dev);
2750}
2751
70a10e25
AD
2752static void ixgbevf_tx_ctxtdesc(struct ixgbevf_ring *tx_ring,
2753 u32 vlan_macip_lens, u32 type_tucmd,
2754 u32 mss_l4len_idx)
92915f71
GR
2755{
2756 struct ixgbe_adv_tx_context_desc *context_desc;
70a10e25 2757 u16 i = tx_ring->next_to_use;
92915f71 2758
70a10e25 2759 context_desc = IXGBEVF_TX_CTXTDESC(tx_ring, i);
92915f71 2760
70a10e25
AD
2761 i++;
2762 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
92915f71 2763
70a10e25
AD
2764 /* set bits to identify this as an advanced context descriptor */
2765 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
92915f71 2766
70a10e25
AD
2767 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2768 context_desc->seqnum_seed = 0;
2769 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
2770 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2771}
2772
2773static int ixgbevf_tso(struct ixgbevf_ring *tx_ring,
7ad1a093
ET
2774 struct ixgbevf_tx_buffer *first,
2775 u8 *hdr_len)
70a10e25 2776{
7ad1a093 2777 struct sk_buff *skb = first->skb;
70a10e25
AD
2778 u32 vlan_macip_lens, type_tucmd;
2779 u32 mss_l4len_idx, l4len;
2780
01a545cf
ET
2781 if (skb->ip_summed != CHECKSUM_PARTIAL)
2782 return 0;
2783
70a10e25
AD
2784 if (!skb_is_gso(skb))
2785 return 0;
92915f71 2786
70a10e25
AD
2787 if (skb_header_cloned(skb)) {
2788 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2789 if (err)
2790 return err;
92915f71
GR
2791 }
2792
70a10e25
AD
2793 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2794 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
2795
2796 if (skb->protocol == htons(ETH_P_IP)) {
2797 struct iphdr *iph = ip_hdr(skb);
2798 iph->tot_len = 0;
2799 iph->check = 0;
2800 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2801 iph->daddr, 0,
2802 IPPROTO_TCP,
2803 0);
2804 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7ad1a093
ET
2805 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
2806 IXGBE_TX_FLAGS_CSUM |
2807 IXGBE_TX_FLAGS_IPV4;
70a10e25
AD
2808 } else if (skb_is_gso_v6(skb)) {
2809 ipv6_hdr(skb)->payload_len = 0;
2810 tcp_hdr(skb)->check =
2811 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2812 &ipv6_hdr(skb)->daddr,
2813 0, IPPROTO_TCP, 0);
7ad1a093
ET
2814 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
2815 IXGBE_TX_FLAGS_CSUM;
70a10e25
AD
2816 }
2817
2818 /* compute header lengths */
2819 l4len = tcp_hdrlen(skb);
2820 *hdr_len += l4len;
2821 *hdr_len = skb_transport_offset(skb) + l4len;
2822
7ad1a093
ET
2823 /* update gso size and bytecount with header size */
2824 first->gso_segs = skb_shinfo(skb)->gso_segs;
2825 first->bytecount += (first->gso_segs - 1) * *hdr_len;
2826
70a10e25
AD
2827 /* mss_l4len_id: use 1 as index for TSO */
2828 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
2829 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
2830 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
2831
2832 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
2833 vlan_macip_lens = skb_network_header_len(skb);
2834 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7ad1a093 2835 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
70a10e25
AD
2836
2837 ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens,
2838 type_tucmd, mss_l4len_idx);
2839
2840 return 1;
92915f71
GR
2841}
2842
7ad1a093
ET
2843static void ixgbevf_tx_csum(struct ixgbevf_ring *tx_ring,
2844 struct ixgbevf_tx_buffer *first)
92915f71 2845{
7ad1a093 2846 struct sk_buff *skb = first->skb;
70a10e25
AD
2847 u32 vlan_macip_lens = 0;
2848 u32 mss_l4len_idx = 0;
2849 u32 type_tucmd = 0;
92915f71 2850
70a10e25
AD
2851 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2852 u8 l4_hdr = 0;
2853 switch (skb->protocol) {
2854 case __constant_htons(ETH_P_IP):
2855 vlan_macip_lens |= skb_network_header_len(skb);
2856 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
2857 l4_hdr = ip_hdr(skb)->protocol;
2858 break;
2859 case __constant_htons(ETH_P_IPV6):
2860 vlan_macip_lens |= skb_network_header_len(skb);
2861 l4_hdr = ipv6_hdr(skb)->nexthdr;
2862 break;
2863 default:
2864 if (unlikely(net_ratelimit())) {
2865 dev_warn(tx_ring->dev,
2866 "partial checksum but proto=%x!\n",
7ad1a093 2867 first->protocol);
70a10e25
AD
2868 }
2869 break;
2870 }
92915f71 2871
70a10e25
AD
2872 switch (l4_hdr) {
2873 case IPPROTO_TCP:
2874 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2875 mss_l4len_idx = tcp_hdrlen(skb) <<
2876 IXGBE_ADVTXD_L4LEN_SHIFT;
2877 break;
2878 case IPPROTO_SCTP:
2879 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
2880 mss_l4len_idx = sizeof(struct sctphdr) <<
2881 IXGBE_ADVTXD_L4LEN_SHIFT;
2882 break;
2883 case IPPROTO_UDP:
2884 mss_l4len_idx = sizeof(struct udphdr) <<
2885 IXGBE_ADVTXD_L4LEN_SHIFT;
2886 break;
2887 default:
2888 if (unlikely(net_ratelimit())) {
2889 dev_warn(tx_ring->dev,
2890 "partial checksum but l4 proto=%x!\n",
2891 l4_hdr);
2892 }
2893 break;
2894 }
7ad1a093
ET
2895
2896 /* update TX checksum flag */
2897 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
92915f71
GR
2898 }
2899
70a10e25
AD
2900 /* vlan_macip_lens: MACLEN, VLAN tag */
2901 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7ad1a093 2902 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
70a10e25
AD
2903
2904 ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens,
2905 type_tucmd, mss_l4len_idx);
92915f71
GR
2906}
2907
29d37fa1 2908static __le32 ixgbevf_tx_cmd_type(u32 tx_flags)
92915f71 2909{
29d37fa1
ET
2910 /* set type for advanced descriptor with frame checksum insertion */
2911 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
2912 IXGBE_ADVTXD_DCMD_IFCS |
2913 IXGBE_ADVTXD_DCMD_DEXT);
92915f71 2914
29d37fa1
ET
2915 /* set HW vlan bit if vlan is present */
2916 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2917 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
92915f71 2918
29d37fa1
ET
2919 /* set segmentation enable bits for TSO/FSO */
2920 if (tx_flags & IXGBE_TX_FLAGS_TSO)
2921 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
92915f71 2922
29d37fa1
ET
2923 return cmd_type;
2924}
92915f71 2925
29d37fa1
ET
2926static void ixgbevf_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
2927 u32 tx_flags, unsigned int paylen)
2928{
2929 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9bdfefd2 2930
29d37fa1
ET
2931 /* enable L4 checksum for TSO and TX checksum offload */
2932 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
2933 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
92915f71 2934
29d37fa1
ET
2935 /* enble IPv4 checksum for TSO */
2936 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
2937 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
92915f71 2938
29d37fa1
ET
2939 /* use index 1 context for TSO/FSO/FCOE */
2940 if (tx_flags & IXGBE_TX_FLAGS_TSO)
2941 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
92915f71 2942
29d37fa1
ET
2943 /* Check Context must be set if Tx switch is enabled, which it
2944 * always is for case where virtual functions are running
2945 */
2946 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
92915f71 2947
29d37fa1
ET
2948 tx_desc->read.olinfo_status = olinfo_status;
2949}
92915f71 2950
29d37fa1
ET
2951static void ixgbevf_tx_map(struct ixgbevf_ring *tx_ring,
2952 struct ixgbevf_tx_buffer *first,
2953 const u8 hdr_len)
2954{
2955 dma_addr_t dma;
2956 struct sk_buff *skb = first->skb;
2957 struct ixgbevf_tx_buffer *tx_buffer;
2958 union ixgbe_adv_tx_desc *tx_desc;
2959 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
2960 unsigned int data_len = skb->data_len;
2961 unsigned int size = skb_headlen(skb);
2962 unsigned int paylen = skb->len - hdr_len;
2963 u32 tx_flags = first->tx_flags;
2964 __le32 cmd_type;
2965 u16 i = tx_ring->next_to_use;
9bdfefd2 2966
29d37fa1 2967 tx_desc = IXGBEVF_TX_DESC(tx_ring, i);
92915f71 2968
29d37fa1
ET
2969 ixgbevf_tx_olinfo_status(tx_desc, tx_flags, paylen);
2970 cmd_type = ixgbevf_tx_cmd_type(tx_flags);
7ad1a093 2971
29d37fa1
ET
2972 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2973 if (dma_mapping_error(tx_ring->dev, dma))
2974 goto dma_error;
92915f71 2975
29d37fa1
ET
2976 /* record length, and DMA address */
2977 dma_unmap_len_set(first, len, size);
2978 dma_unmap_addr_set(first, dma, dma);
92915f71 2979
29d37fa1 2980 tx_desc->read.buffer_addr = cpu_to_le64(dma);
92915f71 2981
29d37fa1
ET
2982 for (;;) {
2983 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
2984 tx_desc->read.cmd_type_len =
2985 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
92915f71 2986
29d37fa1
ET
2987 i++;
2988 tx_desc++;
2989 if (i == tx_ring->count) {
2990 tx_desc = IXGBEVF_TX_DESC(tx_ring, 0);
2991 i = 0;
2992 }
92915f71 2993
29d37fa1
ET
2994 dma += IXGBE_MAX_DATA_PER_TXD;
2995 size -= IXGBE_MAX_DATA_PER_TXD;
92915f71 2996
29d37fa1
ET
2997 tx_desc->read.buffer_addr = cpu_to_le64(dma);
2998 tx_desc->read.olinfo_status = 0;
2999 }
92915f71 3000
29d37fa1
ET
3001 if (likely(!data_len))
3002 break;
92915f71 3003
29d37fa1 3004 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
92915f71 3005
29d37fa1
ET
3006 i++;
3007 tx_desc++;
3008 if (i == tx_ring->count) {
3009 tx_desc = IXGBEVF_TX_DESC(tx_ring, 0);
3010 i = 0;
3011 }
92915f71 3012
29d37fa1
ET
3013 size = skb_frag_size(frag);
3014 data_len -= size;
92915f71 3015
29d37fa1
ET
3016 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3017 DMA_TO_DEVICE);
3018 if (dma_mapping_error(tx_ring->dev, dma))
3019 goto dma_error;
70a10e25 3020
29d37fa1
ET
3021 tx_buffer = &tx_ring->tx_buffer_info[i];
3022 dma_unmap_len_set(tx_buffer, len, size);
3023 dma_unmap_addr_set(tx_buffer, dma, dma);
92915f71 3024
29d37fa1
ET
3025 tx_desc->read.buffer_addr = cpu_to_le64(dma);
3026 tx_desc->read.olinfo_status = 0;
3027
3028 frag++;
70a10e25 3029 }
92915f71 3030
29d37fa1
ET
3031 /* write last descriptor with RS and EOP bits */
3032 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
3033 tx_desc->read.cmd_type_len = cmd_type;
3034
3035 /* set the timestamp */
3036 first->time_stamp = jiffies;
3037
3038 /* Force memory writes to complete before letting h/w know there
3039 * are new descriptors to fetch. (Only applicable for weak-ordered
3040 * memory model archs, such as IA-64).
3041 *
3042 * We also need this memory barrier (wmb) to make certain all of the
3043 * status bits have been updated before next_to_watch is written.
70a10e25 3044 */
29d37fa1 3045 wmb();
92915f71 3046
29d37fa1
ET
3047 /* set next_to_watch value indicating a packet is present */
3048 first->next_to_watch = tx_desc;
92915f71 3049
29d37fa1
ET
3050 i++;
3051 if (i == tx_ring->count)
3052 i = 0;
9bdfefd2 3053
29d37fa1 3054 tx_ring->next_to_use = i;
92915f71 3055
29d37fa1
ET
3056 /* notify HW of packet */
3057 writel(i, tx_ring->tail);
3058
3059 return;
3060dma_error:
3061 dev_err(tx_ring->dev, "TX DMA map failed\n");
3062
3063 /* clear dma mappings for failed tx_buffer_info map */
3064 for (;;) {
3065 tx_buffer = &tx_ring->tx_buffer_info[i];
3066 ixgbevf_unmap_and_free_tx_resource(tx_ring, tx_buffer);
3067 if (tx_buffer == first)
3068 break;
3069 if (i == 0)
3070 i = tx_ring->count;
3071 i--;
3072 }
92915f71 3073
92915f71 3074 tx_ring->next_to_use = i;
92915f71
GR
3075}
3076
fb40195c 3077static int __ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size)
92915f71 3078{
fb40195c 3079 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
92915f71
GR
3080 /* Herbert's original patch had:
3081 * smp_mb__after_netif_stop_queue();
3082 * but since that doesn't exist yet, just open code it. */
3083 smp_mb();
3084
3085 /* We need to check again in a case another CPU has just
3086 * made room available. */
f880d07b 3087 if (likely(ixgbevf_desc_unused(tx_ring) < size))
92915f71
GR
3088 return -EBUSY;
3089
3090 /* A reprieve! - use start_queue because it doesn't call schedule */
fb40195c 3091 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
095e2617
ET
3092 ++tx_ring->tx_stats.restart_queue;
3093
92915f71
GR
3094 return 0;
3095}
3096
fb40195c 3097static int ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size)
92915f71 3098{
f880d07b 3099 if (likely(ixgbevf_desc_unused(tx_ring) >= size))
92915f71 3100 return 0;
fb40195c 3101 return __ixgbevf_maybe_stop_tx(tx_ring, size);
92915f71
GR
3102}
3103
3104static int ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3105{
3106 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
7ad1a093 3107 struct ixgbevf_tx_buffer *first;
92915f71 3108 struct ixgbevf_ring *tx_ring;
7ad1a093
ET
3109 int tso;
3110 u32 tx_flags = 0;
3595990a
AD
3111 u16 count = TXD_USE_COUNT(skb_headlen(skb));
3112#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
3113 unsigned short f;
3114#endif
7ad1a093 3115 u8 hdr_len = 0;
f9d08f16 3116 u8 *dst_mac = skb_header_pointer(skb, 0, 0, NULL);
7ad1a093 3117
46acc460 3118 if (!dst_mac || is_link_local_ether_addr(dst_mac)) {
f9d08f16
GR
3119 dev_kfree_skb(skb);
3120 return NETDEV_TX_OK;
3121 }
92915f71 3122
7ad1a093 3123 tx_ring = adapter->tx_ring[skb->queue_mapping];
92915f71 3124
3595990a
AD
3125 /*
3126 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
3127 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
3128 * + 2 desc gap to keep tail from touching head,
3129 * + 1 desc for context descriptor,
3130 * otherwise try next time
3131 */
3132#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
3133 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3134 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3135#else
3136 count += skb_shinfo(skb)->nr_frags;
3137#endif
fb40195c 3138 if (ixgbevf_maybe_stop_tx(tx_ring, count + 3)) {
095e2617 3139 tx_ring->tx_stats.tx_busy++;
3595990a
AD
3140 return NETDEV_TX_BUSY;
3141 }
3142
7ad1a093
ET
3143 /* record the location of the first descriptor for this packet */
3144 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
3145 first->skb = skb;
3146 first->bytecount = skb->len;
3147 first->gso_segs = 1;
3148
eab6d18d 3149 if (vlan_tx_tag_present(skb)) {
92915f71
GR
3150 tx_flags |= vlan_tx_tag_get(skb);
3151 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3152 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3153 }
3154
7ad1a093
ET
3155 /* record initial flags and protocol */
3156 first->tx_flags = tx_flags;
3157 first->protocol = vlan_get_protocol(skb);
92915f71 3158
7ad1a093
ET
3159 tso = ixgbevf_tso(tx_ring, first, &hdr_len);
3160 if (tso < 0)
3161 goto out_drop;
b5d217f3 3162 else if (!tso)
7ad1a093 3163 ixgbevf_tx_csum(tx_ring, first);
92915f71 3164
29d37fa1 3165 ixgbevf_tx_map(tx_ring, first, hdr_len);
70a10e25 3166
fb40195c 3167 ixgbevf_maybe_stop_tx(tx_ring, DESC_NEEDED);
92915f71 3168
7ad1a093
ET
3169 return NETDEV_TX_OK;
3170
3171out_drop:
3172 dev_kfree_skb_any(first->skb);
3173 first->skb = NULL;
3174
92915f71
GR
3175 return NETDEV_TX_OK;
3176}
3177
92915f71
GR
3178/**
3179 * ixgbevf_set_mac - Change the Ethernet Address of the NIC
3180 * @netdev: network interface device structure
3181 * @p: pointer to an address structure
3182 *
3183 * Returns 0 on success, negative on failure
3184 **/
3185static int ixgbevf_set_mac(struct net_device *netdev, void *p)
3186{
3187 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3188 struct ixgbe_hw *hw = &adapter->hw;
3189 struct sockaddr *addr = p;
3190
3191 if (!is_valid_ether_addr(addr->sa_data))
3192 return -EADDRNOTAVAIL;
3193
3194 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3195 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3196
55fdd45b 3197 spin_lock_bh(&adapter->mbx_lock);
1c55ed76 3198
92fe0bf7 3199 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
92915f71 3200
55fdd45b 3201 spin_unlock_bh(&adapter->mbx_lock);
1c55ed76 3202
92915f71
GR
3203 return 0;
3204}
3205
3206/**
3207 * ixgbevf_change_mtu - Change the Maximum Transfer Unit
3208 * @netdev: network interface device structure
3209 * @new_mtu: new value for maximum frame size
3210 *
3211 * Returns 0 on success, negative on failure
3212 **/
3213static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu)
3214{
3215 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3216 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
69bfbec4 3217 int max_possible_frame = MAXIMUM_ETHERNET_VLAN_SIZE;
69bfbec4 3218
56e94095
AD
3219 switch (adapter->hw.api_version) {
3220 case ixgbe_mbox_api_11:
69bfbec4 3221 max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE;
56e94095
AD
3222 break;
3223 default:
3224 if (adapter->hw.mac.type == ixgbe_mac_X540_vf)
3225 max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE;
3226 break;
3227 }
92915f71
GR
3228
3229 /* MTU < 68 is an error and causes problems on some kernels */
69bfbec4 3230 if ((new_mtu < 68) || (max_frame > max_possible_frame))
92915f71
GR
3231 return -EINVAL;
3232
3233 hw_dbg(&adapter->hw, "changing MTU from %d to %d\n",
3234 netdev->mtu, new_mtu);
3235 /* must set new MTU before calling down or up */
3236 netdev->mtu = new_mtu;
3237
3238 if (netif_running(netdev))
3239 ixgbevf_reinit_locked(adapter);
3240
3241 return 0;
3242}
3243
0ac1e8ce 3244static int ixgbevf_suspend(struct pci_dev *pdev, pm_message_t state)
92915f71
GR
3245{
3246 struct net_device *netdev = pci_get_drvdata(pdev);
3247 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
0ac1e8ce
AD
3248#ifdef CONFIG_PM
3249 int retval = 0;
3250#endif
92915f71
GR
3251
3252 netif_device_detach(netdev);
3253
3254 if (netif_running(netdev)) {
0ac1e8ce 3255 rtnl_lock();
92915f71
GR
3256 ixgbevf_down(adapter);
3257 ixgbevf_free_irq(adapter);
3258 ixgbevf_free_all_tx_resources(adapter);
3259 ixgbevf_free_all_rx_resources(adapter);
0ac1e8ce 3260 rtnl_unlock();
92915f71
GR
3261 }
3262
0ac1e8ce 3263 ixgbevf_clear_interrupt_scheme(adapter);
92915f71 3264
0ac1e8ce
AD
3265#ifdef CONFIG_PM
3266 retval = pci_save_state(pdev);
3267 if (retval)
3268 return retval;
92915f71 3269
0ac1e8ce 3270#endif
92915f71 3271 pci_disable_device(pdev);
0ac1e8ce
AD
3272
3273 return 0;
3274}
3275
3276#ifdef CONFIG_PM
3277static int ixgbevf_resume(struct pci_dev *pdev)
3278{
27ae2967
WY
3279 struct net_device *netdev = pci_get_drvdata(pdev);
3280 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
0ac1e8ce
AD
3281 u32 err;
3282
0ac1e8ce
AD
3283 pci_restore_state(pdev);
3284 /*
3285 * pci_restore_state clears dev->state_saved so call
3286 * pci_save_state to restore it.
3287 */
3288 pci_save_state(pdev);
3289
3290 err = pci_enable_device_mem(pdev);
3291 if (err) {
3292 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
3293 return err;
3294 }
3295 pci_set_master(pdev);
3296
798e381a
DS
3297 ixgbevf_reset(adapter);
3298
0ac1e8ce
AD
3299 rtnl_lock();
3300 err = ixgbevf_init_interrupt_scheme(adapter);
3301 rtnl_unlock();
3302 if (err) {
3303 dev_err(&pdev->dev, "Cannot initialize interrupts\n");
3304 return err;
3305 }
3306
0ac1e8ce
AD
3307 if (netif_running(netdev)) {
3308 err = ixgbevf_open(netdev);
3309 if (err)
3310 return err;
3311 }
3312
3313 netif_device_attach(netdev);
3314
3315 return err;
3316}
3317
3318#endif /* CONFIG_PM */
3319static void ixgbevf_shutdown(struct pci_dev *pdev)
3320{
3321 ixgbevf_suspend(pdev, PMSG_SUSPEND);
92915f71
GR
3322}
3323
4197aa7b
ED
3324static struct rtnl_link_stats64 *ixgbevf_get_stats(struct net_device *netdev,
3325 struct rtnl_link_stats64 *stats)
3326{
3327 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3328 unsigned int start;
3329 u64 bytes, packets;
3330 const struct ixgbevf_ring *ring;
3331 int i;
3332
3333 ixgbevf_update_stats(adapter);
3334
3335 stats->multicast = adapter->stats.vfmprc - adapter->stats.base_vfmprc;
3336
3337 for (i = 0; i < adapter->num_rx_queues; i++) {
87e70ab9 3338 ring = adapter->rx_ring[i];
4197aa7b
ED
3339 do {
3340 start = u64_stats_fetch_begin_bh(&ring->syncp);
095e2617
ET
3341 bytes = ring->stats.bytes;
3342 packets = ring->stats.packets;
4197aa7b
ED
3343 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
3344 stats->rx_bytes += bytes;
3345 stats->rx_packets += packets;
3346 }
3347
3348 for (i = 0; i < adapter->num_tx_queues; i++) {
87e70ab9 3349 ring = adapter->tx_ring[i];
4197aa7b
ED
3350 do {
3351 start = u64_stats_fetch_begin_bh(&ring->syncp);
095e2617
ET
3352 bytes = ring->stats.bytes;
3353 packets = ring->stats.packets;
4197aa7b
ED
3354 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
3355 stats->tx_bytes += bytes;
3356 stats->tx_packets += packets;
3357 }
3358
3359 return stats;
3360}
3361
0ac1e8ce 3362static const struct net_device_ops ixgbevf_netdev_ops = {
c12db769
SH
3363 .ndo_open = ixgbevf_open,
3364 .ndo_stop = ixgbevf_close,
3365 .ndo_start_xmit = ixgbevf_xmit_frame,
3366 .ndo_set_rx_mode = ixgbevf_set_rx_mode,
4197aa7b 3367 .ndo_get_stats64 = ixgbevf_get_stats,
92915f71 3368 .ndo_validate_addr = eth_validate_addr,
c12db769
SH
3369 .ndo_set_mac_address = ixgbevf_set_mac,
3370 .ndo_change_mtu = ixgbevf_change_mtu,
3371 .ndo_tx_timeout = ixgbevf_tx_timeout,
c12db769
SH
3372 .ndo_vlan_rx_add_vid = ixgbevf_vlan_rx_add_vid,
3373 .ndo_vlan_rx_kill_vid = ixgbevf_vlan_rx_kill_vid,
c777cdfa
JK
3374#ifdef CONFIG_NET_RX_BUSY_POLL
3375 .ndo_busy_poll = ixgbevf_busy_poll_recv,
3376#endif
92915f71 3377};
92915f71
GR
3378
3379static void ixgbevf_assign_netdev_ops(struct net_device *dev)
3380{
0ac1e8ce 3381 dev->netdev_ops = &ixgbevf_netdev_ops;
92915f71
GR
3382 ixgbevf_set_ethtool_ops(dev);
3383 dev->watchdog_timeo = 5 * HZ;
3384}
3385
3386/**
3387 * ixgbevf_probe - Device Initialization Routine
3388 * @pdev: PCI device information struct
3389 * @ent: entry in ixgbevf_pci_tbl
3390 *
3391 * Returns 0 on success, negative on failure
3392 *
3393 * ixgbevf_probe initializes an adapter identified by a pci_dev structure.
3394 * The OS initialization, configuring of the adapter private structure,
3395 * and a hardware reset occur.
3396 **/
1dd06ae8 3397static int ixgbevf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
92915f71
GR
3398{
3399 struct net_device *netdev;
3400 struct ixgbevf_adapter *adapter = NULL;
3401 struct ixgbe_hw *hw = NULL;
3402 const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data];
3403 static int cards_found;
3404 int err, pci_using_dac;
3405
3406 err = pci_enable_device(pdev);
3407 if (err)
3408 return err;
3409
53567aa4 3410 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
92915f71
GR
3411 pci_using_dac = 1;
3412 } else {
53567aa4 3413 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
92915f71 3414 if (err) {
53567aa4
RK
3415 dev_err(&pdev->dev, "No usable DMA "
3416 "configuration, aborting\n");
3417 goto err_dma;
92915f71
GR
3418 }
3419 pci_using_dac = 0;
3420 }
3421
3422 err = pci_request_regions(pdev, ixgbevf_driver_name);
3423 if (err) {
3424 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3425 goto err_pci_reg;
3426 }
3427
3428 pci_set_master(pdev);
3429
92915f71
GR
3430 netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter),
3431 MAX_TX_QUEUES);
92915f71
GR
3432 if (!netdev) {
3433 err = -ENOMEM;
3434 goto err_alloc_etherdev;
3435 }
3436
3437 SET_NETDEV_DEV(netdev, &pdev->dev);
3438
3439 pci_set_drvdata(pdev, netdev);
3440 adapter = netdev_priv(netdev);
3441
3442 adapter->netdev = netdev;
3443 adapter->pdev = pdev;
3444 hw = &adapter->hw;
3445 hw->back = adapter;
b3f4d599 3446 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
92915f71
GR
3447
3448 /*
3449 * call save state here in standalone driver because it relies on
3450 * adapter struct to exist, and needs to call netdev_priv
3451 */
3452 pci_save_state(pdev);
3453
3454 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3455 pci_resource_len(pdev, 0));
3456 if (!hw->hw_addr) {
3457 err = -EIO;
3458 goto err_ioremap;
3459 }
3460
3461 ixgbevf_assign_netdev_ops(netdev);
3462
3463 adapter->bd_number = cards_found;
3464
3465 /* Setup hw api */
3466 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3467 hw->mac.type = ii->mac;
3468
3469 memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops,
f416dfc0 3470 sizeof(struct ixgbe_mbx_operations));
92915f71 3471
92915f71
GR
3472 /* setup the private structure */
3473 err = ixgbevf_sw_init(adapter);
1a0d6ae5
DK
3474 if (err)
3475 goto err_sw_init;
3476
3477 /* The HW MAC address was set and/or determined in sw_init */
1a0d6ae5
DK
3478 if (!is_valid_ether_addr(netdev->dev_addr)) {
3479 pr_err("invalid MAC address\n");
3480 err = -EIO;
3481 goto err_sw_init;
3482 }
92915f71 3483
471a76de 3484 netdev->hw_features = NETIF_F_SG |
92915f71 3485 NETIF_F_IP_CSUM |
471a76de
MM
3486 NETIF_F_IPV6_CSUM |
3487 NETIF_F_TSO |
3488 NETIF_F_TSO6 |
3489 NETIF_F_RXCSUM;
3490
3491 netdev->features = netdev->hw_features |
f646968f
PM
3492 NETIF_F_HW_VLAN_CTAG_TX |
3493 NETIF_F_HW_VLAN_CTAG_RX |
3494 NETIF_F_HW_VLAN_CTAG_FILTER;
92915f71 3495
92915f71
GR
3496 netdev->vlan_features |= NETIF_F_TSO;
3497 netdev->vlan_features |= NETIF_F_TSO6;
3498 netdev->vlan_features |= NETIF_F_IP_CSUM;
3bfacf96 3499 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
92915f71
GR
3500 netdev->vlan_features |= NETIF_F_SG;
3501
3502 if (pci_using_dac)
3503 netdev->features |= NETIF_F_HIGHDMA;
3504
01789349
JP
3505 netdev->priv_flags |= IFF_UNICAST_FLT;
3506
92915f71 3507 init_timer(&adapter->watchdog_timer);
c061b18d 3508 adapter->watchdog_timer.function = ixgbevf_watchdog;
92915f71
GR
3509 adapter->watchdog_timer.data = (unsigned long)adapter;
3510
3511 INIT_WORK(&adapter->reset_task, ixgbevf_reset_task);
3512 INIT_WORK(&adapter->watchdog_task, ixgbevf_watchdog_task);
3513
3514 err = ixgbevf_init_interrupt_scheme(adapter);
3515 if (err)
3516 goto err_sw_init;
3517
92915f71
GR
3518 strcpy(netdev->name, "eth%d");
3519
3520 err = register_netdev(netdev);
3521 if (err)
3522 goto err_register;
3523
5d426ad1
GR
3524 netif_carrier_off(netdev);
3525
33bd9f60
GR
3526 ixgbevf_init_last_counter_stats(adapter);
3527
92915f71 3528 /* print the MAC address */
f794e7ef 3529 hw_dbg(hw, "%pM\n", netdev->dev_addr);
92915f71
GR
3530
3531 hw_dbg(hw, "MAC: %d\n", hw->mac.type);
3532
92915f71
GR
3533 hw_dbg(hw, "Intel(R) 82599 Virtual Function\n");
3534 cards_found++;
3535 return 0;
3536
3537err_register:
0ac1e8ce 3538 ixgbevf_clear_interrupt_scheme(adapter);
92915f71
GR
3539err_sw_init:
3540 ixgbevf_reset_interrupt_capability(adapter);
3541 iounmap(hw->hw_addr);
3542err_ioremap:
3543 free_netdev(netdev);
3544err_alloc_etherdev:
3545 pci_release_regions(pdev);
3546err_pci_reg:
3547err_dma:
3548 pci_disable_device(pdev);
3549 return err;
3550}
3551
3552/**
3553 * ixgbevf_remove - Device Removal Routine
3554 * @pdev: PCI device information struct
3555 *
3556 * ixgbevf_remove is called by the PCI subsystem to alert the driver
3557 * that it should release a PCI device. The could be caused by a
3558 * Hot-Plug event, or because the driver is going to be removed from
3559 * memory.
3560 **/
9f9a12f8 3561static void ixgbevf_remove(struct pci_dev *pdev)
92915f71
GR
3562{
3563 struct net_device *netdev = pci_get_drvdata(pdev);
3564 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3565
3566 set_bit(__IXGBEVF_DOWN, &adapter->state);
3567
3568 del_timer_sync(&adapter->watchdog_timer);
3569
23f333a2 3570 cancel_work_sync(&adapter->reset_task);
92915f71
GR
3571 cancel_work_sync(&adapter->watchdog_task);
3572
fd13a9ab 3573 if (netdev->reg_state == NETREG_REGISTERED)
92915f71 3574 unregister_netdev(netdev);
92915f71 3575
0ac1e8ce 3576 ixgbevf_clear_interrupt_scheme(adapter);
92915f71
GR
3577 ixgbevf_reset_interrupt_capability(adapter);
3578
3579 iounmap(adapter->hw.hw_addr);
3580 pci_release_regions(pdev);
3581
3582 hw_dbg(&adapter->hw, "Remove complete\n");
3583
92915f71
GR
3584 free_netdev(netdev);
3585
3586 pci_disable_device(pdev);
3587}
3588
9f19f31d
AD
3589/**
3590 * ixgbevf_io_error_detected - called when PCI error is detected
3591 * @pdev: Pointer to PCI device
3592 * @state: The current pci connection state
3593 *
3594 * This function is called after a PCI bus error affecting
3595 * this device has been detected.
3596 */
3597static pci_ers_result_t ixgbevf_io_error_detected(struct pci_dev *pdev,
3598 pci_channel_state_t state)
3599{
3600 struct net_device *netdev = pci_get_drvdata(pdev);
3601 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3602
3603 netif_device_detach(netdev);
3604
3605 if (state == pci_channel_io_perm_failure)
3606 return PCI_ERS_RESULT_DISCONNECT;
3607
3608 if (netif_running(netdev))
3609 ixgbevf_down(adapter);
3610
3611 pci_disable_device(pdev);
3612
3613 /* Request a slot slot reset. */
3614 return PCI_ERS_RESULT_NEED_RESET;
3615}
3616
3617/**
3618 * ixgbevf_io_slot_reset - called after the pci bus has been reset.
3619 * @pdev: Pointer to PCI device
3620 *
3621 * Restart the card from scratch, as if from a cold-boot. Implementation
3622 * resembles the first-half of the ixgbevf_resume routine.
3623 */
3624static pci_ers_result_t ixgbevf_io_slot_reset(struct pci_dev *pdev)
3625{
3626 struct net_device *netdev = pci_get_drvdata(pdev);
3627 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3628
3629 if (pci_enable_device_mem(pdev)) {
3630 dev_err(&pdev->dev,
3631 "Cannot re-enable PCI device after reset.\n");
3632 return PCI_ERS_RESULT_DISCONNECT;
3633 }
3634
3635 pci_set_master(pdev);
3636
3637 ixgbevf_reset(adapter);
3638
3639 return PCI_ERS_RESULT_RECOVERED;
3640}
3641
3642/**
3643 * ixgbevf_io_resume - called when traffic can start flowing again.
3644 * @pdev: Pointer to PCI device
3645 *
3646 * This callback is called when the error recovery driver tells us that
3647 * its OK to resume normal operation. Implementation resembles the
3648 * second-half of the ixgbevf_resume routine.
3649 */
3650static void ixgbevf_io_resume(struct pci_dev *pdev)
3651{
3652 struct net_device *netdev = pci_get_drvdata(pdev);
3653 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3654
3655 if (netif_running(netdev))
3656 ixgbevf_up(adapter);
3657
3658 netif_device_attach(netdev);
3659}
3660
3661/* PCI Error Recovery (ERS) */
3646f0e5 3662static const struct pci_error_handlers ixgbevf_err_handler = {
9f19f31d
AD
3663 .error_detected = ixgbevf_io_error_detected,
3664 .slot_reset = ixgbevf_io_slot_reset,
3665 .resume = ixgbevf_io_resume,
3666};
3667
92915f71
GR
3668static struct pci_driver ixgbevf_driver = {
3669 .name = ixgbevf_driver_name,
3670 .id_table = ixgbevf_pci_tbl,
3671 .probe = ixgbevf_probe,
9f9a12f8 3672 .remove = ixgbevf_remove,
0ac1e8ce
AD
3673#ifdef CONFIG_PM
3674 /* Power Management Hooks */
3675 .suspend = ixgbevf_suspend,
3676 .resume = ixgbevf_resume,
3677#endif
92915f71 3678 .shutdown = ixgbevf_shutdown,
9f19f31d 3679 .err_handler = &ixgbevf_err_handler
92915f71
GR
3680};
3681
3682/**
65d676c8 3683 * ixgbevf_init_module - Driver Registration Routine
92915f71 3684 *
65d676c8 3685 * ixgbevf_init_module is the first routine called when the driver is
92915f71
GR
3686 * loaded. All it does is register with the PCI subsystem.
3687 **/
3688static int __init ixgbevf_init_module(void)
3689{
3690 int ret;
dbd9636e
JK
3691 pr_info("%s - version %s\n", ixgbevf_driver_string,
3692 ixgbevf_driver_version);
92915f71 3693
dbd9636e 3694 pr_info("%s\n", ixgbevf_copyright);
92915f71
GR
3695
3696 ret = pci_register_driver(&ixgbevf_driver);
3697 return ret;
3698}
3699
3700module_init(ixgbevf_init_module);
3701
3702/**
65d676c8 3703 * ixgbevf_exit_module - Driver Exit Cleanup Routine
92915f71 3704 *
65d676c8 3705 * ixgbevf_exit_module is called just before the driver is removed
92915f71
GR
3706 * from memory.
3707 **/
3708static void __exit ixgbevf_exit_module(void)
3709{
3710 pci_unregister_driver(&ixgbevf_driver);
3711}
3712
3713#ifdef DEBUG
3714/**
65d676c8 3715 * ixgbevf_get_hw_dev_name - return device name string
92915f71
GR
3716 * used by hardware layer to print debugging information
3717 **/
3718char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw)
3719{
3720 struct ixgbevf_adapter *adapter = hw->back;
3721 return adapter->netdev->name;
3722}
3723
3724#endif
3725module_exit(ixgbevf_exit_module);
3726
3727/* ixgbevf_main.c */