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Merge branch 'parisc-5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / jme.c
CommitLineData
8fe76f5a 1// SPDX-License-Identifier: GPL-2.0-only
95252236
GFT		 2/*
3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 *
5 * Copyright 2008 JMicron Technology Corporation
6 * http://www.jmicron.com/
e47dfcd8 7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
95252236
GFT		 8 *
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
95252236
GFT		 10 */
11
49d70c48
JP		 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
95252236
GFT		 14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/ethtool.h>
20#include <linux/mii.h>
21#include <linux/crc32.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/in.h>
25#include <linux/ip.h>
26#include <linux/ipv6.h>
27#include <linux/tcp.h>
28#include <linux/udp.h>
29#include <linux/if_vlan.h>
5a0e3ad6 30#include <linux/slab.h>
b7c6bfb7 31#include <net/ip6_checksum.h>
95252236
GFT		 32#include "jme.h"
33
34static int force_pseudohp = -1;
35static int no_pseudohp = -1;
36static int no_extplug = -1;
37module_param(force_pseudohp, int, 0);
38MODULE_PARM_DESC(force_pseudohp,
39 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
40module_param(no_pseudohp, int, 0);
41MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
42module_param(no_extplug, int, 0);
43MODULE_PARM_DESC(no_extplug,
44 "Do not use external plug signal for pseudo hot-plug.");
45
46static int
47jme_mdio_read(struct net_device *netdev, int phy, int reg)
48{
49 struct jme_adapter *jme = netdev_priv(netdev);
50 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
51
52read_again:
53 jwrite32(jme, JME_SMI, SMI_OP_REQ |
54 smi_phy_addr(phy) |
55 smi_reg_addr(reg));
56
57 wmb();
58 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
59 udelay(20);
60 val = jread32(jme, JME_SMI);
61 if ((val & SMI_OP_REQ) == 0)
62 break;
63 }
64
65 if (i == 0) {
49d70c48 66 pr_err("phy(%d) read timeout : %d\n", phy, reg);
95252236
GFT		 67 return 0;
68 }
69
70 if (again--)
71 goto read_again;
72
73 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
74}
75
76static void
77jme_mdio_write(struct net_device *netdev,
78 int phy, int reg, int val)
79{
80 struct jme_adapter *jme = netdev_priv(netdev);
81 int i;
82
83 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
84 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
85 smi_phy_addr(phy) | smi_reg_addr(reg));
86
87 wmb();
88 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
89 udelay(20);
90 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
91 break;
92 }
93
94 if (i == 0)
49d70c48 95 pr_err("phy(%d) write timeout : %d\n", phy, reg);
95252236
GFT		 96}
97
98static inline void
99jme_reset_phy_processor(struct jme_adapter *jme)
100{
101 u32 val;
102
103 jme_mdio_write(jme->dev,
104 jme->mii_if.phy_id,
105 MII_ADVERTISE, ADVERTISE_ALL |
106 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
107
108 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
109 jme_mdio_write(jme->dev,
110 jme->mii_if.phy_id,
111 MII_CTRL1000,
112 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
113
114 val = jme_mdio_read(jme->dev,
115 jme->mii_if.phy_id,
116 MII_BMCR);
117
118 jme_mdio_write(jme->dev,
119 jme->mii_if.phy_id,
120 MII_BMCR, val | BMCR_RESET);
95252236
GFT		 121}
122
123static void
124jme_setup_wakeup_frame(struct jme_adapter *jme,
b6bc7650 125 const u32 *mask, u32 crc, int fnr)
95252236
GFT		 126{
127 int i;
128
129 /*
130 * Setup CRC pattern
131 */
132 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
133 wmb();
134 jwrite32(jme, JME_WFODP, crc);
135 wmb();
136
137 /*
138 * Setup Mask
139 */
140 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
141 jwrite32(jme, JME_WFOI,
142 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
143 (fnr & WFOI_FRAME_SEL));
144 wmb();
145 jwrite32(jme, JME_WFODP, mask[i]);
146 wmb();
147 }
148}
149
854a2e7c
GFT		 150static inline void
151jme_mac_rxclk_off(struct jme_adapter *jme)
152{
153 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
154 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
155}
156
157static inline void
158jme_mac_rxclk_on(struct jme_adapter *jme)
159{
160 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
161 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
162}
163
164static inline void
165jme_mac_txclk_off(struct jme_adapter *jme)
166{
167 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
168 jwrite32f(jme, JME_GHC, jme->reg_ghc);
169}
170
171static inline void
172jme_mac_txclk_on(struct jme_adapter *jme)
173{
174 u32 speed = jme->reg_ghc & GHC_SPEED;
175 if (speed == GHC_SPEED_1000M)
176 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
177 else
178 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
179 jwrite32f(jme, JME_GHC, jme->reg_ghc);
180}
181
182static inline void
183jme_reset_ghc_speed(struct jme_adapter *jme)
184{
185 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
186 jwrite32f(jme, JME_GHC, jme->reg_ghc);
187}
188
189static inline void
190jme_reset_250A2_workaround(struct jme_adapter *jme)
191{
192 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
193 GPREG1_RSSPATCH);
194 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
195}
196
197static inline void
198jme_assert_ghc_reset(struct jme_adapter *jme)
199{
200 jme->reg_ghc |= GHC_SWRST;
201 jwrite32f(jme, JME_GHC, jme->reg_ghc);
202}
203
204static inline void
205jme_clear_ghc_reset(struct jme_adapter *jme)
206{
207 jme->reg_ghc &= ~GHC_SWRST;
208 jwrite32f(jme, JME_GHC, jme->reg_ghc);
209}
210
ea019649 211static void
95252236
GFT		 212jme_reset_mac_processor(struct jme_adapter *jme)
213{
b6bc7650 214 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
95252236
GFT		 215 u32 crc = 0xCDCDCDCD;
216 u32 gpreg0;
217 int i;
218
854a2e7c
GFT		 219 jme_reset_ghc_speed(jme);
220 jme_reset_250A2_workaround(jme);
221
222 jme_mac_rxclk_on(jme);
223 jme_mac_txclk_on(jme);
224 udelay(1);
225 jme_assert_ghc_reset(jme);
226 udelay(1);
227 jme_mac_rxclk_off(jme);
228 jme_mac_txclk_off(jme);
229 udelay(1);
230 jme_clear_ghc_reset(jme);
231 udelay(1);
232 jme_mac_rxclk_on(jme);
233 jme_mac_txclk_on(jme);
234 udelay(1);
235 jme_mac_rxclk_off(jme);
236 jme_mac_txclk_off(jme);
95252236
GFT		 237
238 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
239 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
240 jwrite32(jme, JME_RXQDC, 0x00000000);
241 jwrite32(jme, JME_RXNDA, 0x00000000);
242 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
243 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
244 jwrite32(jme, JME_TXQDC, 0x00000000);
245 jwrite32(jme, JME_TXNDA, 0x00000000);
246
247 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
248 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
249 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
250 jme_setup_wakeup_frame(jme, mask, crc, i);
251 if (jme->fpgaver)
252 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
253 else
254 gpreg0 = GPREG0_DEFAULT;
255 jwrite32(jme, JME_GPREG0, gpreg0);
95252236
GFT		 256}
257
258static inline void
0772a99b 259jme_clear_pm_enable_wol(struct jme_adapter *jme)
95252236 260{
bc057e03 261 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
95252236
GFT		 262}
263
0772a99b
GFT		 264static inline void
265jme_clear_pm_disable_wol(struct jme_adapter *jme)
266{
267 jwrite32(jme, JME_PMCS, PMCS_STMASK);
268}
269
95252236
GFT		 270static int
271jme_reload_eeprom(struct jme_adapter *jme)
272{
273 u32 val;
274 int i;
275
276 val = jread32(jme, JME_SMBCSR);
277
278 if (val & SMBCSR_EEPROMD) {
279 val |= SMBCSR_CNACK;
280 jwrite32(jme, JME_SMBCSR, val);
281 val |= SMBCSR_RELOAD;
282 jwrite32(jme, JME_SMBCSR, val);
283 mdelay(12);
284
285 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
286 mdelay(1);
287 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
288 break;
289 }
290
291 if (i == 0) {
49d70c48 292 pr_err("eeprom reload timeout\n");
95252236
GFT		 293 return -EIO;
294 }
295 }
296
297 return 0;
298}
299
300static void
301jme_load_macaddr(struct net_device *netdev)
302{
303 struct jme_adapter *jme = netdev_priv(netdev);
d458cdf7 304 unsigned char macaddr[ETH_ALEN];
95252236
GFT		 305 u32 val;
306
307 spin_lock_bh(&jme->macaddr_lock);
308 val = jread32(jme, JME_RXUMA_LO);
309 macaddr[0] = (val >> 0) & 0xFF;
310 macaddr[1] = (val >> 8) & 0xFF;
311 macaddr[2] = (val >> 16) & 0xFF;
312 macaddr[3] = (val >> 24) & 0xFF;
313 val = jread32(jme, JME_RXUMA_HI);
314 macaddr[4] = (val >> 0) & 0xFF;
315 macaddr[5] = (val >> 8) & 0xFF;
d458cdf7 316 memcpy(netdev->dev_addr, macaddr, ETH_ALEN);
95252236
GFT		 317 spin_unlock_bh(&jme->macaddr_lock);
318}
319
320static inline void
321jme_set_rx_pcc(struct jme_adapter *jme, int p)
322{
323 switch (p) {
324 case PCC_OFF:
325 jwrite32(jme, JME_PCCRX0,
326 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
327 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
328 break;
329 case PCC_P1:
330 jwrite32(jme, JME_PCCRX0,
331 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
332 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
333 break;
334 case PCC_P2:
335 jwrite32(jme, JME_PCCRX0,
336 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
337 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
338 break;
339 case PCC_P3:
340 jwrite32(jme, JME_PCCRX0,
341 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
342 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
343 break;
344 default:
345 break;
346 }
347 wmb();
348
349 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
f8502ce4 350 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
95252236
GFT		 351}
352
353static void
354jme_start_irq(struct jme_adapter *jme)
355{
356 register struct dynpcc_info *dpi = &(jme->dpi);
357
358 jme_set_rx_pcc(jme, PCC_P1);
359 dpi->cur = PCC_P1;
360 dpi->attempt = PCC_P1;
361 dpi->cnt = 0;
362
363 jwrite32(jme, JME_PCCTX,
364 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
365 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
366 PCCTXQ0_EN
367 );
368
369 /*
370 * Enable Interrupts
371 */
372 jwrite32(jme, JME_IENS, INTR_ENABLE);
373}
374
375static inline void
376jme_stop_irq(struct jme_adapter *jme)
377{
378 /*
379 * Disable Interrupts
380 */
381 jwrite32f(jme, JME_IENC, INTR_ENABLE);
382}
383
95252236
GFT		 384static u32
385jme_linkstat_from_phy(struct jme_adapter *jme)
386{
387 u32 phylink, bmsr;
388
389 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
390 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
391 if (bmsr & BMSR_ANCOMP)
392 phylink |= PHY_LINK_AUTONEG_COMPLETE;
393
394 return phylink;
395}
396
397static inline void
51754572 398jme_set_phyfifo_5level(struct jme_adapter *jme)
95252236
GFT		 399{
400 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
401}
402
403static inline void
51754572 404jme_set_phyfifo_8level(struct jme_adapter *jme)
95252236
GFT		 405{
406 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
407}
408
409static int
410jme_check_link(struct net_device *netdev, int testonly)
411{
412 struct jme_adapter *jme = netdev_priv(netdev);
854a2e7c 413 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
95252236
GFT		 414 char linkmsg[64];
415 int rc = 0;
416
417 linkmsg[0] = '\0';
418
419 if (jme->fpgaver)
420 phylink = jme_linkstat_from_phy(jme);
421 else
422 phylink = jread32(jme, JME_PHY_LINK);
423
424 if (phylink & PHY_LINK_UP) {
425 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
426 /*
427 * If we did not enable AN
428 * Speed/Duplex Info should be obtained from SMI
429 */
430 phylink = PHY_LINK_UP;
431
432 bmcr = jme_mdio_read(jme->dev,
433 jme->mii_if.phy_id,
434 MII_BMCR);
435
436 phylink |= ((bmcr & BMCR_SPEED1000) &&
437 (bmcr & BMCR_SPEED100) == 0) ?
438 PHY_LINK_SPEED_1000M :
439 (bmcr & BMCR_SPEED100) ?
440 PHY_LINK_SPEED_100M :
441 PHY_LINK_SPEED_10M;
442
443 phylink |= (bmcr & BMCR_FULLDPLX) ?
444 PHY_LINK_DUPLEX : 0;
445
446 strcat(linkmsg, "Forced: ");
447 } else {
448 /*
449 * Keep polling for speed/duplex resolve complete
450 */
451 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
452 --cnt) {
453
454 udelay(1);
455
456 if (jme->fpgaver)
457 phylink = jme_linkstat_from_phy(jme);
458 else
459 phylink = jread32(jme, JME_PHY_LINK);
460 }
461 if (!cnt)
49d70c48 462 pr_err("Waiting speed resolve timeout\n");
95252236
GFT		 463
464 strcat(linkmsg, "ANed: ");
465 }
466
467 if (jme->phylink == phylink) {
468 rc = 1;
469 goto out;
470 }
471 if (testonly)
472 goto out;
473
474 jme->phylink = phylink;
475
854a2e7c
GFT		 476 /*
477 * The speed/duplex setting of jme->reg_ghc already cleared
478 * by jme_reset_mac_processor()
479 */
95252236
GFT		 480 switch (phylink & PHY_LINK_SPEED_MASK) {
481 case PHY_LINK_SPEED_10M:
854a2e7c 482 jme->reg_ghc |= GHC_SPEED_10M;
95252236 483 strcat(linkmsg, "10 Mbps, ");
95252236
GFT		 484 break;
485 case PHY_LINK_SPEED_100M:
854a2e7c 486 jme->reg_ghc |= GHC_SPEED_100M;
95252236 487 strcat(linkmsg, "100 Mbps, ");
95252236
GFT		 488 break;
489 case PHY_LINK_SPEED_1000M:
854a2e7c 490 jme->reg_ghc |= GHC_SPEED_1000M;
95252236 491 strcat(linkmsg, "1000 Mbps, ");
95252236
GFT		 492 break;
493 default:
494 break;
495 }
95252236
GFT		 496
497 if (phylink & PHY_LINK_DUPLEX) {
498 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
3903c023 499 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
854a2e7c 500 jme->reg_ghc |= GHC_DPX;
95252236
GFT		 501 } else {
502 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
503 TXMCS_BACKOFF |
504 TXMCS_CARRIERSENSE |
505 TXMCS_COLLISION);
3903c023 506 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
95252236 507 }
a821ebe5 508
854a2e7c
GFT		 509 jwrite32(jme, JME_GHC, jme->reg_ghc);
510
a821ebe5 511 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
854a2e7c
GFT		 512 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
513 GPREG1_RSSPATCH);
a821ebe5 514 if (!(phylink & PHY_LINK_DUPLEX))
854a2e7c 515 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
a821ebe5
GFT		 516 switch (phylink & PHY_LINK_SPEED_MASK) {
517 case PHY_LINK_SPEED_10M:
51754572 518 jme_set_phyfifo_8level(jme);
854a2e7c 519 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
a821ebe5
GFT		 520 break;
521 case PHY_LINK_SPEED_100M:
51754572 522 jme_set_phyfifo_5level(jme);
854a2e7c 523 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
a821ebe5
GFT		 524 break;
525 case PHY_LINK_SPEED_1000M:
51754572 526 jme_set_phyfifo_8level(jme);
a821ebe5
GFT		 527 break;
528 default:
529 break;
530 }
531 }
854a2e7c 532 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
95252236 533
4f40bf46 534 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
535 "Full-Duplex, " :
536 "Half-Duplex, ");
537 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
538 "MDI-X" :
539 "MDI");
49d70c48 540 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
95252236
GFT		 541 netif_carrier_on(netdev);
542 } else {
543 if (testonly)
544 goto out;
545
49d70c48 546 netif_info(jme, link, jme->dev, "Link is down\n");
95252236
GFT		 547 jme->phylink = 0;
548 netif_carrier_off(netdev);
549 }
550
551out:
552 return rc;
553}
554
555static int
556jme_setup_tx_resources(struct jme_adapter *jme)
557{
558 struct jme_ring *txring = &(jme->txring[0]);
559
560 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
561 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
562 &(txring->dmaalloc),
563 GFP_ATOMIC);
564
47bd10d1
GFT		 565 if (!txring->alloc)
566 goto err_set_null;
95252236
GFT		 567
568 /*
569 * 16 Bytes align
570 */
571 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
572 RING_DESC_ALIGN);
573 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
574 txring->next_to_use = 0;
575 atomic_set(&txring->next_to_clean, 0);
576 atomic_set(&txring->nr_free, jme->tx_ring_size);
577
6396bb22
KC		 578 txring->bufinf = kcalloc(jme->tx_ring_size,
579 sizeof(struct jme_buffer_info),
580 GFP_ATOMIC);
47bd10d1
GFT		 581 if (unlikely(!(txring->bufinf)))
582 goto err_free_txring;
583
95252236 584 return 0;
47bd10d1
GFT		 585
586err_free_txring:
587 dma_free_coherent(&(jme->pdev->dev),
588 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
589 txring->alloc,
590 txring->dmaalloc);
591
592err_set_null:
593 txring->desc = NULL;
594 txring->dmaalloc = 0;
595 txring->dma = 0;
596 txring->bufinf = NULL;
597
598 return -ENOMEM;
95252236
GFT		 599}
600
601static void
602jme_free_tx_resources(struct jme_adapter *jme)
603{
604 int i;
605 struct jme_ring *txring = &(jme->txring[0]);
eacf69a1 606 struct jme_buffer_info *txbi;
95252236
GFT		 607
608 if (txring->alloc) {
47bd10d1
GFT		 609 if (txring->bufinf) {
610 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
611 txbi = txring->bufinf + i;
612 if (txbi->skb) {
613 dev_kfree_skb(txbi->skb);
614 txbi->skb = NULL;
615 }
616 txbi->mapping = 0;
617 txbi->len = 0;
618 txbi->nr_desc = 0;
619 txbi->start_xmit = 0;
95252236 620 }
47bd10d1 621 kfree(txring->bufinf);
95252236
GFT		 622 }
623
624 dma_free_coherent(&(jme->pdev->dev),
625 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
626 txring->alloc,
627 txring->dmaalloc);
628
629 txring->alloc = NULL;
630 txring->desc = NULL;
631 txring->dmaalloc = 0;
632 txring->dma = 0;
47bd10d1 633 txring->bufinf = NULL;
95252236
GFT		 634 }
635 txring->next_to_use = 0;
636 atomic_set(&txring->next_to_clean, 0);
637 atomic_set(&txring->nr_free, 0);
95252236
GFT		 638}
639
640static inline void
641jme_enable_tx_engine(struct jme_adapter *jme)
642{
643 /*
644 * Select Queue 0
645 */
646 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
647 wmb();
648
649 /*
650 * Setup TX Queue 0 DMA Bass Address
651 */
652 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
653 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
654 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
655
656 /*
657 * Setup TX Descptor Count
658 */
659 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
660
661 /*
662 * Enable TX Engine
663 */
664 wmb();
854a2e7c 665 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
95252236
GFT		 666 TXCS_SELECT_QUEUE0 |
667 TXCS_ENABLE);
668
854a2e7c
GFT		 669 /*
670 * Start clock for TX MAC Processor
671 */
672 jme_mac_txclk_on(jme);
95252236
GFT		 673}
674
95252236
GFT		 675static inline void
676jme_disable_tx_engine(struct jme_adapter *jme)
677{
678 int i;
679 u32 val;
680
681 /*
682 * Disable TX Engine
683 */
684 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
685 wmb();
686
687 val = jread32(jme, JME_TXCS);
688 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
689 mdelay(1);
690 val = jread32(jme, JME_TXCS);
691 rmb();
692 }
693
694 if (!i)
49d70c48 695 pr_err("Disable TX engine timeout\n");
854a2e7c
GFT		 696
697 /*
698 * Stop clock for TX MAC Processor
699 */
700 jme_mac_txclk_off(jme);
95252236
GFT		 701}
702
703static void
704jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
705{
eacf69a1 706 struct jme_ring *rxring = &(jme->rxring[0]);
95252236
GFT		 707 register struct rxdesc *rxdesc = rxring->desc;
708 struct jme_buffer_info *rxbi = rxring->bufinf;
709 rxdesc += i;
710 rxbi += i;
711
712 rxdesc->dw[0] = 0;
713 rxdesc->dw[1] = 0;
714 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
715 rxdesc->desc1.bufaddrl = cpu_to_le32(
716 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
717 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
718 if (jme->dev->features & NETIF_F_HIGHDMA)
719 rxdesc->desc1.flags = RXFLAG_64BIT;
720 wmb();
721 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
722}
723
724static int
725jme_make_new_rx_buf(struct jme_adapter *jme, int i)
726{
727 struct jme_ring *rxring = &(jme->rxring[0]);
728 struct jme_buffer_info *rxbi = rxring->bufinf + i;
729 struct sk_buff *skb;
94c5b41b 730 dma_addr_t mapping;
95252236
GFT		 731
732 skb = netdev_alloc_skb(jme->dev,
733 jme->dev->mtu + RX_EXTRA_LEN);
734 if (unlikely(!skb))
735 return -ENOMEM;
736
94c5b41b
GFT		 737 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
738 offset_in_page(skb->data), skb_tailroom(skb),
739 PCI_DMA_FROMDEVICE);
740 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
741 dev_kfree_skb(skb);
742 return -ENOMEM;
743 }
744
745 if (likely(rxbi->mapping))
746 pci_unmap_page(jme->pdev, rxbi->mapping,
747 rxbi->len, PCI_DMA_FROMDEVICE);
748
95252236
GFT		 749 rxbi->skb = skb;
750 rxbi->len = skb_tailroom(skb);
94c5b41b 751 rxbi->mapping = mapping;
95252236
GFT		 752 return 0;
753}
754
755static void
756jme_free_rx_buf(struct jme_adapter *jme, int i)
757{
758 struct jme_ring *rxring = &(jme->rxring[0]);
759 struct jme_buffer_info *rxbi = rxring->bufinf;
760 rxbi += i;
761
762 if (rxbi->skb) {
763 pci_unmap_page(jme->pdev,
764 rxbi->mapping,
765 rxbi->len,
766 PCI_DMA_FROMDEVICE);
767 dev_kfree_skb(rxbi->skb);
768 rxbi->skb = NULL;
769 rxbi->mapping = 0;
770 rxbi->len = 0;
771 }
772}
773
774static void
775jme_free_rx_resources(struct jme_adapter *jme)
776{
777 int i;
778 struct jme_ring *rxring = &(jme->rxring[0]);
779
780 if (rxring->alloc) {
47bd10d1
GFT		 781 if (rxring->bufinf) {
782 for (i = 0 ; i < jme->rx_ring_size ; ++i)
783 jme_free_rx_buf(jme, i);
784 kfree(rxring->bufinf);
785 }
95252236
GFT		 786
787 dma_free_coherent(&(jme->pdev->dev),
788 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
789 rxring->alloc,
790 rxring->dmaalloc);
791 rxring->alloc = NULL;
792 rxring->desc = NULL;
793 rxring->dmaalloc = 0;
794 rxring->dma = 0;
47bd10d1 795 rxring->bufinf = NULL;
95252236
GFT		 796 }
797 rxring->next_to_use = 0;
798 atomic_set(&rxring->next_to_clean, 0);
799}
800
801static int
802jme_setup_rx_resources(struct jme_adapter *jme)
803{
804 int i;
805 struct jme_ring *rxring = &(jme->rxring[0]);
806
807 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
808 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
809 &(rxring->dmaalloc),
810 GFP_ATOMIC);
47bd10d1
GFT		 811 if (!rxring->alloc)
812 goto err_set_null;
95252236
GFT		 813
814 /*
815 * 16 Bytes align
816 */
817 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
818 RING_DESC_ALIGN);
819 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
820 rxring->next_to_use = 0;
821 atomic_set(&rxring->next_to_clean, 0);
822
6396bb22
KC		 823 rxring->bufinf = kcalloc(jme->rx_ring_size,
824 sizeof(struct jme_buffer_info),
825 GFP_ATOMIC);
47bd10d1
GFT		 826 if (unlikely(!(rxring->bufinf)))
827 goto err_free_rxring;
828
95252236
GFT		 829 /*
830 * Initiallize Receive Descriptors
831 */
832 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
833 if (unlikely(jme_make_new_rx_buf(jme, i))) {
834 jme_free_rx_resources(jme);
835 return -ENOMEM;
836 }
837
838 jme_set_clean_rxdesc(jme, i);
839 }
840
841 return 0;
47bd10d1
GFT		 842
843err_free_rxring:
844 dma_free_coherent(&(jme->pdev->dev),
845 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
846 rxring->alloc,
847 rxring->dmaalloc);
848err_set_null:
849 rxring->desc = NULL;
850 rxring->dmaalloc = 0;
851 rxring->dma = 0;
852 rxring->bufinf = NULL;
853
854 return -ENOMEM;
95252236
GFT		 855}
856
857static inline void
858jme_enable_rx_engine(struct jme_adapter *jme)
859{
860 /*
861 * Select Queue 0
862 */
863 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
864 RXCS_QUEUESEL_Q0);
865 wmb();
866
867 /*
868 * Setup RX DMA Bass Address
869 */
eacf69a1 870 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
95252236 871 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
eacf69a1 872 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
95252236
GFT		 873
874 /*
875 * Setup RX Descriptor Count
876 */
877 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
878
879 /*
880 * Setup Unicast Filter
881 */
8b53abae 882 jme_set_unicastaddr(jme->dev);
95252236
GFT		 883 jme_set_multi(jme->dev);
884
885 /*
886 * Enable RX Engine
887 */
888 wmb();
854a2e7c 889 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
95252236
GFT		 890 RXCS_QUEUESEL_Q0 |
891 RXCS_ENABLE |
892 RXCS_QST);
854a2e7c
GFT		 893
894 /*
895 * Start clock for RX MAC Processor
896 */
897 jme_mac_rxclk_on(jme);
95252236
GFT		 898}
899
900static inline void
901jme_restart_rx_engine(struct jme_adapter *jme)
902{
903 /*
904 * Start RX Engine
905 */
906 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
907 RXCS_QUEUESEL_Q0 |
908 RXCS_ENABLE |
909 RXCS_QST);
910}
911
912static inline void
913jme_disable_rx_engine(struct jme_adapter *jme)
914{
915 int i;
916 u32 val;
917
918 /*
919 * Disable RX Engine
920 */
921 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
922 wmb();
923
924 val = jread32(jme, JME_RXCS);
925 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
926 mdelay(1);
927 val = jread32(jme, JME_RXCS);
928 rmb();
929 }
930
931 if (!i)
49d70c48 932 pr_err("Disable RX engine timeout\n");
95252236 933
854a2e7c
GFT		 934 /*
935 * Stop clock for RX MAC Processor
936 */
937 jme_mac_rxclk_off(jme);
95252236
GFT		 938}
939
c00cd826
GFT		 940static u16
941jme_udpsum(struct sk_buff *skb)
942{
943 u16 csum = 0xFFFFu;
944
945 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
946 return csum;
947 if (skb->protocol != htons(ETH_P_IP))
948 return csum;
949 skb_set_network_header(skb, ETH_HLEN);
950 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
951 (skb->len < (ETH_HLEN +
952 (ip_hdr(skb)->ihl << 2) +
953 sizeof(struct udphdr)))) {
954 skb_reset_network_header(skb);
955 return csum;
956 }
957 skb_set_transport_header(skb,
958 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
959 csum = udp_hdr(skb)->check;
960 skb_reset_transport_header(skb);
961 skb_reset_network_header(skb);
962
963 return csum;
964}
965
95252236 966static int
c00cd826 967jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
95252236
GFT		 968{
969 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
970 return false;
971
ce7d70af
GFT		 972 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
973 == RXWBFLAG_TCPON)) {
974 if (flags & RXWBFLAG_IPV4)
f8502ce4 975 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
ce7d70af 976 return false;
95252236
GFT		 977 }
978
ce7d70af 979 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
c00cd826 980 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
ce7d70af 981 if (flags & RXWBFLAG_IPV4)
49d70c48 982 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
ce7d70af 983 return false;
95252236
GFT		 984 }
985
ce7d70af
GFT		 986 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
987 == RXWBFLAG_IPV4)) {
49d70c48 988 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
ce7d70af 989 return false;
95252236
GFT		 990 }
991
992 return true;
95252236
GFT		 993}
994
995static void
996jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
997{
998 struct jme_ring *rxring = &(jme->rxring[0]);
999 struct rxdesc *rxdesc = rxring->desc;
1000 struct jme_buffer_info *rxbi = rxring->bufinf;
1001 struct sk_buff *skb;
1002 int framesize;
1003
1004 rxdesc += idx;
1005 rxbi += idx;
1006
1007 skb = rxbi->skb;
1008 pci_dma_sync_single_for_cpu(jme->pdev,
1009 rxbi->mapping,
1010 rxbi->len,
1011 PCI_DMA_FROMDEVICE);
1012
1013 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1014 pci_dma_sync_single_for_device(jme->pdev,
1015 rxbi->mapping,
1016 rxbi->len,
1017 PCI_DMA_FROMDEVICE);
1018
1019 ++(NET_STAT(jme).rx_dropped);
1020 } else {
1021 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1022 - RX_PREPAD_SIZE;
1023
1024 skb_reserve(skb, RX_PREPAD_SIZE);
1025 skb_put(skb, framesize);
1026 skb->protocol = eth_type_trans(skb, jme->dev);
1027
c00cd826 1028 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
95252236
GFT		 1029 skb->ip_summed = CHECKSUM_UNNECESSARY;
1030 else
bc8acf2c 1031 skb_checksum_none_assert(skb);
95252236 1032
31c221c4 1033 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
5043f505
JP		 1034 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1035
86a9bad3 1036 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
5043f505 1037 NET_STAT(jme).rx_bytes += 4;
95252236 1038 }
5043f505 1039 jme->jme_rx(skb);
95252236 1040
31c221c4
HH		 1041 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1042 cpu_to_le16(RXWBFLAG_DEST_MUL))
95252236
GFT		 1043 ++(NET_STAT(jme).multicast);
1044
95252236
GFT		 1045 NET_STAT(jme).rx_bytes += framesize;
1046 ++(NET_STAT(jme).rx_packets);
1047 }
1048
1049 jme_set_clean_rxdesc(jme, idx);
1050
1051}
1052
1053static int
1054jme_process_receive(struct jme_adapter *jme, int limit)
1055{
1056 struct jme_ring *rxring = &(jme->rxring[0]);
f14d244f 1057 struct rxdesc *rxdesc;
95252236
GFT		 1058 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1059
1060 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1061 goto out_inc;
1062
1063 if (unlikely(atomic_read(&jme->link_changing) != 1))
1064 goto out_inc;
1065
1066 if (unlikely(!netif_carrier_ok(jme->dev)))
1067 goto out_inc;
1068
1069 i = atomic_read(&rxring->next_to_clean);
858b9ced 1070 while (limit > 0) {
95252236
GFT		 1071 rxdesc = rxring->desc;
1072 rxdesc += i;
1073
31c221c4 1074 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
95252236
GFT		 1075 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1076 goto out;
858b9ced 1077 --limit;
95252236 1078
ea192aa8 1079 rmb();
95252236
GFT		 1080 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1081
1082 if (unlikely(desccnt > 1 ||
1083 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1084
1085 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1086 ++(NET_STAT(jme).rx_crc_errors);
1087 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1088 ++(NET_STAT(jme).rx_fifo_errors);
1089 else
1090 ++(NET_STAT(jme).rx_errors);
1091
1092 if (desccnt > 1)
1093 limit -= desccnt - 1;
1094
1095 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1096 jme_set_clean_rxdesc(jme, j);
1097 j = (j + 1) & (mask);
1098 }
1099
1100 } else {
1101 jme_alloc_and_feed_skb(jme, i);
1102 }
1103
1104 i = (i + desccnt) & (mask);
1105 }
1106
1107out:
1108 atomic_set(&rxring->next_to_clean, i);
1109
1110out_inc:
1111 atomic_inc(&jme->rx_cleaning);
1112
1113 return limit > 0 ? limit : 0;
1114
1115}
1116
1117static void
1118jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1119{
1120 if (likely(atmp == dpi->cur)) {
1121 dpi->cnt = 0;
1122 return;
1123 }
1124
1125 if (dpi->attempt == atmp) {
1126 ++(dpi->cnt);
1127 } else {
1128 dpi->attempt = atmp;
1129 dpi->cnt = 0;
1130 }
1131
1132}
1133
1134static void
1135jme_dynamic_pcc(struct jme_adapter *jme)
1136{
1137 register struct dynpcc_info *dpi = &(jme->dpi);
1138
1139 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1140 jme_attempt_pcc(dpi, PCC_P3);
8e95a202
JP		 1141 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1142 dpi->intr_cnt > PCC_INTR_THRESHOLD)
95252236
GFT		 1143 jme_attempt_pcc(dpi, PCC_P2);
1144 else
1145 jme_attempt_pcc(dpi, PCC_P1);
1146
1147 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1148 if (dpi->attempt < dpi->cur)
1149 tasklet_schedule(&jme->rxclean_task);
1150 jme_set_rx_pcc(jme, dpi->attempt);
1151 dpi->cur = dpi->attempt;
1152 dpi->cnt = 0;
1153 }
1154}
1155
1156static void
1157jme_start_pcc_timer(struct jme_adapter *jme)
1158{
1159 struct dynpcc_info *dpi = &(jme->dpi);
1160 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1161 dpi->last_pkts = NET_STAT(jme).rx_packets;
1162 dpi->intr_cnt = 0;
1163 jwrite32(jme, JME_TMCSR,
1164 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1165}
1166
1167static inline void
1168jme_stop_pcc_timer(struct jme_adapter *jme)
1169{
1170 jwrite32(jme, JME_TMCSR, 0);
1171}
1172
1173static void
1174jme_shutdown_nic(struct jme_adapter *jme)
1175{
1176 u32 phylink;
1177
1178 phylink = jme_linkstat_from_phy(jme);
1179
1180 if (!(phylink & PHY_LINK_UP)) {
1181 /*
1182 * Disable all interrupt before issue timer
1183 */
1184 jme_stop_irq(jme);
1185 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1186 }
1187}
1188
1189static void
1190jme_pcc_tasklet(unsigned long arg)
1191{
1192 struct jme_adapter *jme = (struct jme_adapter *)arg;
1193 struct net_device *netdev = jme->dev;
1194
1195 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1196 jme_shutdown_nic(jme);
1197 return;
1198 }
1199
1200 if (unlikely(!netif_carrier_ok(netdev) ||
1201 (atomic_read(&jme->link_changing) != 1)
1202 )) {
1203 jme_stop_pcc_timer(jme);
1204 return;
1205 }
1206
1207 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1208 jme_dynamic_pcc(jme);
1209
1210 jme_start_pcc_timer(jme);
1211}
1212
1213static inline void
1214jme_polling_mode(struct jme_adapter *jme)
1215{
1216 jme_set_rx_pcc(jme, PCC_OFF);
1217}
1218
1219static inline void
1220jme_interrupt_mode(struct jme_adapter *jme)
1221{
1222 jme_set_rx_pcc(jme, PCC_P1);
1223}
1224
1225static inline int
1226jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1227{
1228 u32 apmc;
1229 apmc = jread32(jme, JME_APMC);
1230 return apmc & JME_APMC_PSEUDO_HP_EN;
1231}
1232
1233static void
1234jme_start_shutdown_timer(struct jme_adapter *jme)
1235{
1236 u32 apmc;
1237
1238 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1239 apmc &= ~JME_APMC_EPIEN_CTRL;
1240 if (!no_extplug) {
1241 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1242 wmb();
1243 }
1244 jwrite32f(jme, JME_APMC, apmc);
1245
1246 jwrite32f(jme, JME_TIMER2, 0);
1247 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1248 jwrite32(jme, JME_TMCSR,
1249 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1250}
1251
1252static void
1253jme_stop_shutdown_timer(struct jme_adapter *jme)
1254{
1255 u32 apmc;
1256
1257 jwrite32f(jme, JME_TMCSR, 0);
1258 jwrite32f(jme, JME_TIMER2, 0);
1259 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1260
1261 apmc = jread32(jme, JME_APMC);
1262 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1263 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1264 wmb();
1265 jwrite32f(jme, JME_APMC, apmc);
1266}
1267
1268static void
1269jme_link_change_tasklet(unsigned long arg)
1270{
1271 struct jme_adapter *jme = (struct jme_adapter *)arg;
1272 struct net_device *netdev = jme->dev;
1273 int rc;
1274
1275 while (!atomic_dec_and_test(&jme->link_changing)) {
1276 atomic_inc(&jme->link_changing);
49d70c48 1277 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
95252236 1278 while (atomic_read(&jme->link_changing) != 1)
49d70c48 1279 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
95252236
GFT		 1280 }
1281
1282 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1283 goto out;
1284
1285 jme->old_mtu = netdev->mtu;
1286 netif_stop_queue(netdev);
1287 if (jme_pseudo_hotplug_enabled(jme))
1288 jme_stop_shutdown_timer(jme);
1289
1290 jme_stop_pcc_timer(jme);
1291 tasklet_disable(&jme->txclean_task);
1292 tasklet_disable(&jme->rxclean_task);
1293 tasklet_disable(&jme->rxempty_task);
1294
1295 if (netif_carrier_ok(netdev)) {
95252236
GFT		 1296 jme_disable_rx_engine(jme);
1297 jme_disable_tx_engine(jme);
1298 jme_reset_mac_processor(jme);
1299 jme_free_rx_resources(jme);
1300 jme_free_tx_resources(jme);
1301
1302 if (test_bit(JME_FLAG_POLL, &jme->flags))
1303 jme_polling_mode(jme);
1304
1305 netif_carrier_off(netdev);
1306 }
1307
1308 jme_check_link(netdev, 0);
1309 if (netif_carrier_ok(netdev)) {
1310 rc = jme_setup_rx_resources(jme);
1311 if (rc) {
49d70c48 1312 pr_err("Allocating resources for RX error, Device STOPPED!\n");
95252236
GFT		 1313 goto out_enable_tasklet;
1314 }
1315
1316 rc = jme_setup_tx_resources(jme);
1317 if (rc) {
49d70c48 1318 pr_err("Allocating resources for TX error, Device STOPPED!\n");
95252236
GFT		 1319 goto err_out_free_rx_resources;
1320 }
1321
1322 jme_enable_rx_engine(jme);
1323 jme_enable_tx_engine(jme);
1324
1325 netif_start_queue(netdev);
1326
1327 if (test_bit(JME_FLAG_POLL, &jme->flags))
1328 jme_interrupt_mode(jme);
1329
1330 jme_start_pcc_timer(jme);
1331 } else if (jme_pseudo_hotplug_enabled(jme)) {
1332 jme_start_shutdown_timer(jme);
1333 }
1334
1335 goto out_enable_tasklet;
1336
1337err_out_free_rx_resources:
1338 jme_free_rx_resources(jme);
1339out_enable_tasklet:
1340 tasklet_enable(&jme->txclean_task);
06f66529
QL		 1341 tasklet_enable(&jme->rxclean_task);
1342 tasklet_enable(&jme->rxempty_task);
95252236
GFT		 1343out:
1344 atomic_inc(&jme->link_changing);
1345}
1346
1347static void
1348jme_rx_clean_tasklet(unsigned long arg)
1349{
1350 struct jme_adapter *jme = (struct jme_adapter *)arg;
1351 struct dynpcc_info *dpi = &(jme->dpi);
1352
1353 jme_process_receive(jme, jme->rx_ring_size);
1354 ++(dpi->intr_cnt);
1355
1356}
1357
1358static int
1359jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1360{
1361 struct jme_adapter *jme = jme_napi_priv(holder);
95252236
GFT		 1362 int rest;
1363
1364 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1365
1366 while (atomic_read(&jme->rx_empty) > 0) {
1367 atomic_dec(&jme->rx_empty);
1368 ++(NET_STAT(jme).rx_dropped);
1369 jme_restart_rx_engine(jme);
1370 }
1371 atomic_inc(&jme->rx_empty);
1372
1373 if (rest) {
1374 JME_RX_COMPLETE(netdev, holder);
1375 jme_interrupt_mode(jme);
1376 }
1377
1378 JME_NAPI_WEIGHT_SET(budget, rest);
1379 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1380}
1381
1382static void
1383jme_rx_empty_tasklet(unsigned long arg)
1384{
1385 struct jme_adapter *jme = (struct jme_adapter *)arg;
1386
1387 if (unlikely(atomic_read(&jme->link_changing) != 1))
1388 return;
1389
1390 if (unlikely(!netif_carrier_ok(jme->dev)))
1391 return;
1392
f8502ce4 1393 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
95252236
GFT		 1394
1395 jme_rx_clean_tasklet(arg);
1396
1397 while (atomic_read(&jme->rx_empty) > 0) {
1398 atomic_dec(&jme->rx_empty);
1399 ++(NET_STAT(jme).rx_dropped);
1400 jme_restart_rx_engine(jme);
1401 }
1402 atomic_inc(&jme->rx_empty);
1403}
1404
1405static void
1406jme_wake_queue_if_stopped(struct jme_adapter *jme)
1407{
eacf69a1 1408 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1409
1410 smp_wmb();
1411 if (unlikely(netif_queue_stopped(jme->dev) &&
1412 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
49d70c48 1413 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
95252236
GFT		 1414 netif_wake_queue(jme->dev);
1415 }
1416
1417}
1418
1419static void
1420jme_tx_clean_tasklet(unsigned long arg)
1421{
1422 struct jme_adapter *jme = (struct jme_adapter *)arg;
1423 struct jme_ring *txring = &(jme->txring[0]);
1424 struct txdesc *txdesc = txring->desc;
1425 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1426 int i, j, cnt = 0, max, err, mask;
1427
49d70c48 1428 tx_dbg(jme, "Into txclean\n");
95252236
GFT		 1429
1430 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1431 goto out;
1432
1433 if (unlikely(atomic_read(&jme->link_changing) != 1))
1434 goto out;
1435
1436 if (unlikely(!netif_carrier_ok(jme->dev)))
1437 goto out;
1438
1439 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1440 mask = jme->tx_ring_mask;
1441
1442 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1443
1444 ctxbi = txbi + i;
1445
1446 if (likely(ctxbi->skb &&
1447 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1448
1449 tx_dbg(jme, "txclean: %d+%d@%lu\n",
49d70c48 1450 i, ctxbi->nr_desc, jiffies);
95252236
GFT		 1451
1452 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1453
1454 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1455 ttxbi = txbi + ((i + j) & (mask));
1456 txdesc[(i + j) & (mask)].dw[0] = 0;
1457
1458 pci_unmap_page(jme->pdev,
1459 ttxbi->mapping,
1460 ttxbi->len,
1461 PCI_DMA_TODEVICE);
1462
1463 ttxbi->mapping = 0;
1464 ttxbi->len = 0;
1465 }
1466
1467 dev_kfree_skb(ctxbi->skb);
1468
1469 cnt += ctxbi->nr_desc;
1470
1471 if (unlikely(err)) {
1472 ++(NET_STAT(jme).tx_carrier_errors);
1473 } else {
1474 ++(NET_STAT(jme).tx_packets);
1475 NET_STAT(jme).tx_bytes += ctxbi->len;
1476 }
1477
1478 ctxbi->skb = NULL;
1479 ctxbi->len = 0;
1480 ctxbi->start_xmit = 0;
1481
1482 } else {
1483 break;
1484 }
1485
1486 i = (i + ctxbi->nr_desc) & mask;
1487
1488 ctxbi->nr_desc = 0;
1489 }
1490
49d70c48 1491 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
95252236
GFT		 1492 atomic_set(&txring->next_to_clean, i);
1493 atomic_add(cnt, &txring->nr_free);
1494
1495 jme_wake_queue_if_stopped(jme);
1496
1497out:
1498 atomic_inc(&jme->tx_cleaning);
1499}
1500
1501static void
1502jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1503{
1504 /*
1505 * Disable interrupt
1506 */
1507 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1508
1509 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1510 /*
1511 * Link change event is critical
1512 * all other events are ignored
1513 */
1514 jwrite32(jme, JME_IEVE, intrstat);
1515 tasklet_schedule(&jme->linkch_task);
1516 goto out_reenable;
1517 }
1518
1519 if (intrstat & INTR_TMINTR) {
1520 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1521 tasklet_schedule(&jme->pcc_task);
1522 }
1523
1524 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1525 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1526 tasklet_schedule(&jme->txclean_task);
1527 }
1528
1529 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1530 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1531 INTR_PCCRX0 |
1532 INTR_RX0EMP)) |
1533 INTR_RX0);
1534 }
1535
1536 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1537 if (intrstat & INTR_RX0EMP)
1538 atomic_inc(&jme->rx_empty);
1539
1540 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1541 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1542 jme_polling_mode(jme);
1543 JME_RX_SCHEDULE(jme);
1544 }
1545 }
1546 } else {
1547 if (intrstat & INTR_RX0EMP) {
1548 atomic_inc(&jme->rx_empty);
1549 tasklet_hi_schedule(&jme->rxempty_task);
1550 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1551 tasklet_hi_schedule(&jme->rxclean_task);
1552 }
1553 }
1554
1555out_reenable:
1556 /*
1557 * Re-enable interrupt
1558 */
1559 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1560}
1561
1562static irqreturn_t
1563jme_intr(int irq, void *dev_id)
1564{
1565 struct net_device *netdev = dev_id;
1566 struct jme_adapter *jme = netdev_priv(netdev);
1567 u32 intrstat;
1568
1569 intrstat = jread32(jme, JME_IEVE);
1570
1571 /*
1572 * Check if it's really an interrupt for us
1573 */
576b5223 1574 if (unlikely((intrstat & INTR_ENABLE) == 0))
95252236
GFT		 1575 return IRQ_NONE;
1576
1577 /*
1578 * Check if the device still exist
1579 */
1580 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1581 return IRQ_NONE;
1582
1583 jme_intr_msi(jme, intrstat);
1584
1585 return IRQ_HANDLED;
1586}
1587
1588static irqreturn_t
1589jme_msi(int irq, void *dev_id)
1590{
1591 struct net_device *netdev = dev_id;
1592 struct jme_adapter *jme = netdev_priv(netdev);
1593 u32 intrstat;
1594
d1dfa1d1 1595 intrstat = jread32(jme, JME_IEVE);
95252236
GFT		 1596
1597 jme_intr_msi(jme, intrstat);
1598
1599 return IRQ_HANDLED;
1600}
1601
1602static void
1603jme_reset_link(struct jme_adapter *jme)
1604{
1605 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1606}
1607
1608static void
1609jme_restart_an(struct jme_adapter *jme)
1610{
1611 u32 bmcr;
1612
1613 spin_lock_bh(&jme->phy_lock);
1614 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1615 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1616 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1617 spin_unlock_bh(&jme->phy_lock);
1618}
1619
1620static int
1621jme_request_irq(struct jme_adapter *jme)
1622{
1623 int rc;
1624 struct net_device *netdev = jme->dev;
1625 irq_handler_t handler = jme_intr;
1626 int irq_flags = IRQF_SHARED;
1627
1628 if (!pci_enable_msi(jme->pdev)) {
1629 set_bit(JME_FLAG_MSI, &jme->flags);
1630 handler = jme_msi;
1631 irq_flags = 0;
1632 }
1633
1634 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1635 netdev);
1636 if (rc) {
49d70c48
JP		 1637 netdev_err(netdev,
1638 "Unable to request %s interrupt (return: %d)\n",
1639 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1640 rc);
95252236
GFT		 1641
1642 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1643 pci_disable_msi(jme->pdev);
1644 clear_bit(JME_FLAG_MSI, &jme->flags);
1645 }
1646 } else {
1647 netdev->irq = jme->pdev->irq;
1648 }
1649
1650 return rc;
1651}
1652
1653static void
1654jme_free_irq(struct jme_adapter *jme)
1655{
1656 free_irq(jme->pdev->irq, jme->dev);
1657 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1658 pci_disable_msi(jme->pdev);
1659 clear_bit(JME_FLAG_MSI, &jme->flags);
1660 jme->dev->irq = jme->pdev->irq;
1661 }
1662}
1663
4872b11f
GFT		 1664static inline void
1665jme_new_phy_on(struct jme_adapter *jme)
1666{
1667 u32 reg;
1668
1669 reg = jread32(jme, JME_PHY_PWR);
1670 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1671 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1672 jwrite32(jme, JME_PHY_PWR, reg);
1673
1674 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1675 reg &= ~PE1_GPREG0_PBG;
1676 reg |= PE1_GPREG0_ENBG;
1677 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1678}
1679
1680static inline void
1681jme_new_phy_off(struct jme_adapter *jme)
1682{
1683 u32 reg;
1684
1685 reg = jread32(jme, JME_PHY_PWR);
1686 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1687 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1688 jwrite32(jme, JME_PHY_PWR, reg);
1689
1690 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1691 reg &= ~PE1_GPREG0_PBG;
1692 reg |= PE1_GPREG0_PDD3COLD;
1693 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1694}
1695
c8a8684d
GFT		 1696static inline void
1697jme_phy_on(struct jme_adapter *jme)
1698{
1699 u32 bmcr;
1700
1701 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1702 bmcr &= ~BMCR_PDOWN;
1703 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
4872b11f
GFT		 1704
1705 if (new_phy_power_ctrl(jme->chip_main_rev))
1706 jme_new_phy_on(jme);
1707}
1708
1709static inline void
1710jme_phy_off(struct jme_adapter *jme)
1711{
1712 u32 bmcr;
1713
1714 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1715 bmcr |= BMCR_PDOWN;
1716 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1717
1718 if (new_phy_power_ctrl(jme->chip_main_rev))
1719 jme_new_phy_off(jme);
c8a8684d
GFT		 1720}
1721
c4860ba2
AL		 1722static int
1723jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1724{
1725 u32 phy_addr;
1726
1727 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1728 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1729 phy_addr);
1730 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1731 JM_PHY_SPEC_DATA_REG);
1732}
1733
1734static void
1735jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1736{
1737 u32 phy_addr;
1738
1739 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1740 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1741 phy_data);
1742 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1743 phy_addr);
1744}
1745
1746static int
1747jme_phy_calibration(struct jme_adapter *jme)
1748{
1749 u32 ctrl1000, phy_data;
1750
1751 jme_phy_off(jme);
1752 jme_phy_on(jme);
1753 /* Enabel PHY test mode 1 */
1754 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1755 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1756 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1757 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1758
1759 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1760 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1761 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1762 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1763 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1764 msleep(20);
1765 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1766 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1767 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1768 JM_PHY_EXT_COMM_2_CALI_LATCH);
1769 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1770
1771 /* Disable PHY test mode */
1772 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1773 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1774 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1775 return 0;
1776}
1777
1778static int
1779jme_phy_setEA(struct jme_adapter *jme)
1780{
1781 u32 phy_comm0 = 0, phy_comm1 = 0;
1782 u8 nic_ctrl;
1783
1784 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1785 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1786 return 0;
1787
1788 switch (jme->pdev->device) {
1789 case PCI_DEVICE_ID_JMICRON_JMC250:
1790 if (((jme->chip_main_rev == 5) &&
1791 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1792 (jme->chip_sub_rev == 3))) ||
1793 (jme->chip_main_rev >= 6)) {
1794 phy_comm0 = 0x008A;
1795 phy_comm1 = 0x4109;
1796 }
1797 if ((jme->chip_main_rev == 3) &&
1798 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1799 phy_comm0 = 0xE088;
1800 break;
1801 case PCI_DEVICE_ID_JMICRON_JMC260:
1802 if (((jme->chip_main_rev == 5) &&
1803 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1804 (jme->chip_sub_rev == 3))) ||
1805 (jme->chip_main_rev >= 6)) {
1806 phy_comm0 = 0x008A;
1807 phy_comm1 = 0x4109;
1808 }
1809 if ((jme->chip_main_rev == 3) &&
1810 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1811 phy_comm0 = 0xE088;
1812 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1813 phy_comm0 = 0x608A;
1814 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1815 phy_comm0 = 0x408A;
1816 break;
1817 default:
1818 return -ENODEV;
1819 }
1820 if (phy_comm0)
1821 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1822 if (phy_comm1)
1823 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1824
1825 return 0;
1826}
1827
95252236
GFT		 1828static int
1829jme_open(struct net_device *netdev)
1830{
1831 struct jme_adapter *jme = netdev_priv(netdev);
1832 int rc;
1833
0772a99b 1834 jme_clear_pm_disable_wol(jme);
95252236
GFT		 1835 JME_NAPI_ENABLE(jme);
1836
71c6c837
XF		 1837 tasklet_init(&jme->linkch_task, jme_link_change_tasklet,
1838 (unsigned long) jme);
1839 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet,
1840 (unsigned long) jme);
1841 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet,
1842 (unsigned long) jme);
1843 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet,
1844 (unsigned long) jme);
95252236
GFT		 1845
1846 rc = jme_request_irq(jme);
1847 if (rc)
1848 goto err_out;
1849
95252236
GFT		 1850 jme_start_irq(jme);
1851
4872b11f
GFT		 1852 jme_phy_on(jme);
1853 if (test_bit(JME_FLAG_SSET, &jme->flags))
c523838c 1854 jme_set_link_ksettings(netdev, &jme->old_cmd);
4872b11f 1855 else
95252236 1856 jme_reset_phy_processor(jme);
c4860ba2
AL		 1857 jme_phy_calibration(jme);
1858 jme_phy_setEA(jme);
95252236
GFT		 1859 jme_reset_link(jme);
1860
1861 return 0;
1862
1863err_out:
1864 netif_stop_queue(netdev);
1865 netif_carrier_off(netdev);
1866 return rc;
1867}
1868
1869static void
1870jme_set_100m_half(struct jme_adapter *jme)
1871{
1872 u32 bmcr, tmp;
1873
1c557819 1874 jme_phy_on(jme);
95252236
GFT		 1875 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1876 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1877 BMCR_SPEED1000 | BMCR_FULLDPLX);
1878 tmp |= BMCR_SPEED100;
1879
1880 if (bmcr != tmp)
1881 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1882
1883 if (jme->fpgaver)
1884 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1885 else
1886 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1887}
1888
1889#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1890static void
1891jme_wait_link(struct jme_adapter *jme)
1892{
1893 u32 phylink, to = JME_WAIT_LINK_TIME;
1894
d818c59a 1895 msleep(1000);
95252236
GFT		 1896 phylink = jme_linkstat_from_phy(jme);
1897 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
d818c59a 1898 usleep_range(10000, 11000);
95252236
GFT		 1899 phylink = jme_linkstat_from_phy(jme);
1900 }
1901}
1902
1c557819
GFT		 1903static void
1904jme_powersave_phy(struct jme_adapter *jme)
1905{
81422e67 1906 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1c557819 1907 jme_set_100m_half(jme);
1c557819
GFT		 1908 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1909 jme_wait_link(jme);
0772a99b 1910 jme_clear_pm_enable_wol(jme);
1c557819
GFT		 1911 } else {
1912 jme_phy_off(jme);
1913 }
1914}
1915
95252236
GFT		 1916static int
1917jme_close(struct net_device *netdev)
1918{
1919 struct jme_adapter *jme = netdev_priv(netdev);
1920
1921 netif_stop_queue(netdev);
1922 netif_carrier_off(netdev);
1923
1924 jme_stop_irq(jme);
95252236
GFT		 1925 jme_free_irq(jme);
1926
1927 JME_NAPI_DISABLE(jme);
1928
175c0dff
XF		 1929 tasklet_kill(&jme->linkch_task);
1930 tasklet_kill(&jme->txclean_task);
1931 tasklet_kill(&jme->rxclean_task);
1932 tasklet_kill(&jme->rxempty_task);
95252236 1933
95252236
GFT		 1934 jme_disable_rx_engine(jme);
1935 jme_disable_tx_engine(jme);
1936 jme_reset_mac_processor(jme);
1937 jme_free_rx_resources(jme);
1938 jme_free_tx_resources(jme);
1939 jme->phylink = 0;
1940 jme_phy_off(jme);
1941
1942 return 0;
1943}
1944
1945static int
1946jme_alloc_txdesc(struct jme_adapter *jme,
1947 struct sk_buff *skb)
1948{
eacf69a1 1949 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 1950 int idx, nr_alloc, mask = jme->tx_ring_mask;
1951
1952 idx = txring->next_to_use;
1953 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1954
1955 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1956 return -1;
1957
1958 atomic_sub(nr_alloc, &txring->nr_free);
1959
1960 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1961
1962 return idx;
1963}
1964
76a691d0 1965static int
95252236
GFT		 1966jme_fill_tx_map(struct pci_dev *pdev,
1967 struct txdesc *txdesc,
1968 struct jme_buffer_info *txbi,
1969 struct page *page,
1970 u32 page_offset,
1971 u32 len,
3ad9b358 1972 bool hidma)
95252236
GFT		 1973{
1974 dma_addr_t dmaaddr;
1975
1976 dmaaddr = pci_map_page(pdev,
1977 page,
1978 page_offset,
1979 len,
1980 PCI_DMA_TODEVICE);
1981
76a691d0
NH		 1982 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr)))
1983 return -EINVAL;
1984
95252236
GFT		 1985 pci_dma_sync_single_for_device(pdev,
1986 dmaaddr,
1987 len,
1988 PCI_DMA_TODEVICE);
1989
1990 txdesc->dw[0] = 0;
1991 txdesc->dw[1] = 0;
1992 txdesc->desc2.flags = TXFLAG_OWN;
1993 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1994 txdesc->desc2.datalen = cpu_to_le16(len);
1995 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1996 txdesc->desc2.bufaddrl = cpu_to_le32(
1997 (__u64)dmaaddr & 0xFFFFFFFFUL);
1998
1999 txbi->mapping = dmaaddr;
2000 txbi->len = len;
76a691d0 2001 return 0;
95252236
GFT		 2002}
2003
c4b16068 2004static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
76a691d0
NH		 2005{
2006 struct jme_ring *txring = &(jme->txring[0]);
2007 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2008 int mask = jme->tx_ring_mask;
2009 int j;
2010
c4b16068 2011 for (j = 0 ; j < count ; j++) {
76a691d0
NH		 2012 ctxbi = txbi + ((startidx + j + 2) & (mask));
2013 pci_unmap_page(jme->pdev,
2014 ctxbi->mapping,
2015 ctxbi->len,
2016 PCI_DMA_TODEVICE);
2017
fb70950e
CIK		 2018 ctxbi->mapping = 0;
2019 ctxbi->len = 0;
76a691d0 2020 }
76a691d0
NH		 2021}
2022
2023static int
95252236
GFT		 2024jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2025{
eacf69a1 2026 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 2027 struct txdesc *txdesc = txring->desc, *ctxdesc;
2028 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
3ad9b358 2029 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
95252236
GFT		 2030 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2031 int mask = jme->tx_ring_mask;
95252236 2032 u32 len;
76a691d0 2033 int ret = 0;
95252236
GFT		 2034
2035 for (i = 0 ; i < nr_frags ; ++i) {
d7840976
MWO		 2036 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2037
95252236
GFT		 2038 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2039 ctxbi = txbi + ((idx + i + 2) & (mask));
2040
76a691d0 2041 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
b54c9d5b
JL		 2042 skb_frag_page(frag), skb_frag_off(frag),
2043 skb_frag_size(frag), hidma);
76a691d0 2044 if (ret) {
c4b16068 2045 jme_drop_tx_map(jme, idx, i);
76a691d0
NH		 2046 goto out;
2047 }
95252236
GFT		 2048 }
2049
2050 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2051 ctxdesc = txdesc + ((idx + 1) & (mask));
2052 ctxbi = txbi + ((idx + 1) & (mask));
76a691d0 2053 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
95252236 2054 offset_in_page(skb->data), len, hidma);
76a691d0 2055 if (ret)
c4b16068 2056 jme_drop_tx_map(jme, idx, i);
76a691d0
NH		 2057
2058out:
2059 return ret;
95252236
GFT		 2060
2061}
2062
76a691d0 2063
95252236 2064static int
31c221c4 2065jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
95252236 2066{
31c221c4 2067 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
95252236
GFT		 2068 if (*mss) {
2069 *flags |= TXFLAG_LSEN;
2070
2071 if (skb->protocol == htons(ETH_P_IP)) {
2072 struct iphdr *iph = ip_hdr(skb);
2073
2074 iph->check = 0;
2075 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2076 iph->daddr, 0,
2077 IPPROTO_TCP,
2078 0);
2079 } else {
2080 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2081
2082 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2083 &ip6h->daddr, 0,
2084 IPPROTO_TCP,
2085 0);
2086 }
2087
2088 return 0;
2089 }
2090
2091 return 1;
2092}
2093
2094static void
2095jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2096{
2097 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2098 u8 ip_proto;
2099
2100 switch (skb->protocol) {
2101 case htons(ETH_P_IP):
2102 ip_proto = ip_hdr(skb)->protocol;
2103 break;
2104 case htons(ETH_P_IPV6):
2105 ip_proto = ipv6_hdr(skb)->nexthdr;
2106 break;
2107 default:
2108 ip_proto = 0;
2109 break;
2110 }
2111
2112 switch (ip_proto) {
2113 case IPPROTO_TCP:
2114 *flags |= TXFLAG_TCPCS;
2115 break;
2116 case IPPROTO_UDP:
2117 *flags |= TXFLAG_UDPCS;
2118 break;
2119 default:
49d70c48 2120 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
95252236
GFT		 2121 break;
2122 }
2123 }
2124}
2125
2126static inline void
31c221c4 2127jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
95252236 2128{
df8a39de 2129 if (skb_vlan_tag_present(skb)) {
95252236 2130 *flags |= TXFLAG_TAGON;
df8a39de 2131 *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
95252236
GFT		 2132 }
2133}
2134
2135static int
7f7fd2da 2136jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
95252236 2137{
eacf69a1 2138 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 2139 struct txdesc *txdesc;
2140 struct jme_buffer_info *txbi;
2141 u8 flags;
76a691d0 2142 int ret = 0;
95252236
GFT		 2143
2144 txdesc = (struct txdesc *)txring->desc + idx;
2145 txbi = txring->bufinf + idx;
2146
2147 txdesc->dw[0] = 0;
2148 txdesc->dw[1] = 0;
2149 txdesc->dw[2] = 0;
2150 txdesc->dw[3] = 0;
2151 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2152 /*
2153 * Set OWN bit at final.
2154 * When kernel transmit faster than NIC.
2155 * And NIC trying to send this descriptor before we tell
2156 * it to start sending this TX queue.
2157 * Other fields are already filled correctly.
2158 */
2159 wmb();
2160 flags = TXFLAG_OWN | TXFLAG_INT;
2161 /*
2162 * Set checksum flags while not tso
2163 */
2164 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2165 jme_tx_csum(jme, skb, &flags);
2166 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
76a691d0
NH		 2167 ret = jme_map_tx_skb(jme, skb, idx);
2168 if (ret)
2169 return ret;
2170
95252236
GFT		 2171 txdesc->desc1.flags = flags;
2172 /*
2173 * Set tx buffer info after telling NIC to send
2174 * For better tx_clean timing
2175 */
2176 wmb();
2177 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2178 txbi->skb = skb;
2179 txbi->len = skb->len;
2180 txbi->start_xmit = jiffies;
2181 if (!txbi->start_xmit)
2182 txbi->start_xmit = (0UL-1);
2183
2184 return 0;
2185}
2186
2187static void
2188jme_stop_queue_if_full(struct jme_adapter *jme)
2189{
eacf69a1 2190 struct jme_ring *txring = &(jme->txring[0]);
95252236
GFT		 2191 struct jme_buffer_info *txbi = txring->bufinf;
2192 int idx = atomic_read(&txring->next_to_clean);
2193
2194 txbi += idx;
2195
2196 smp_wmb();
2197 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2198 netif_stop_queue(jme->dev);
49d70c48 2199 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
95252236
GFT		 2200 smp_wmb();
2201 if (atomic_read(&txring->nr_free)
2202 >= (jme->tx_wake_threshold)) {
2203 netif_wake_queue(jme->dev);
49d70c48 2204 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
95252236
GFT		 2205 }
2206 }
2207
2208 if (unlikely(txbi->start_xmit &&
2209 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2210 txbi->skb)) {
2211 netif_stop_queue(jme->dev);
49d70c48
JP		 2212 netif_info(jme, tx_queued, jme->dev,
2213 "TX Queue Stopped %d@%lu\n", idx, jiffies);
95252236
GFT		 2214 }
2215}
2216
2217/*
2218 * This function is already protected by netif_tx_lock()
2219 */
2220
61357325 2221static netdev_tx_t
95252236
GFT		 2222jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2223{
2224 struct jme_adapter *jme = netdev_priv(netdev);
2225 int idx;
2226
ba4e6d19 2227 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
2228 dev_kfree_skb_any(skb);
95252236
GFT		 2229 ++(NET_STAT(jme).tx_dropped);
2230 return NETDEV_TX_OK;
2231 }
2232
2233 idx = jme_alloc_txdesc(jme, skb);
2234
2235 if (unlikely(idx < 0)) {
2236 netif_stop_queue(netdev);
49d70c48
JP		 2237 netif_err(jme, tx_err, jme->dev,
2238 "BUG! Tx ring full when queue awake!\n");
95252236
GFT		 2239
2240 return NETDEV_TX_BUSY;
2241 }
2242
76a691d0 2243 if (jme_fill_tx_desc(jme, skb, idx))
c4b16068 2244 return NETDEV_TX_OK;
95252236
GFT		 2245
2246 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2247 TXCS_SELECT_QUEUE0 |
2248 TXCS_QUEUE0S |
2249 TXCS_ENABLE);
95252236 2250
49d70c48
JP		 2251 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2252 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
95252236
GFT		 2253 jme_stop_queue_if_full(jme);
2254
2255 return NETDEV_TX_OK;
2256}
2257
8b53abae
GFT		 2258static void
2259jme_set_unicastaddr(struct net_device *netdev)
2260{
2261 struct jme_adapter *jme = netdev_priv(netdev);
2262 u32 val;
2263
2264 val = (netdev->dev_addr[3] & 0xff) << 24 |
2265 (netdev->dev_addr[2] & 0xff) << 16 |
2266 (netdev->dev_addr[1] & 0xff) << 8 |
2267 (netdev->dev_addr[0] & 0xff);
2268 jwrite32(jme, JME_RXUMA_LO, val);
2269 val = (netdev->dev_addr[5] & 0xff) << 8 |
2270 (netdev->dev_addr[4] & 0xff);
2271 jwrite32(jme, JME_RXUMA_HI, val);
2272}
2273
95252236
GFT		 2274static int
2275jme_set_macaddr(struct net_device *netdev, void *p)
2276{
2277 struct jme_adapter *jme = netdev_priv(netdev);
2278 struct sockaddr *addr = p;
95252236
GFT		 2279
2280 if (netif_running(netdev))
2281 return -EBUSY;
2282
2283 spin_lock_bh(&jme->macaddr_lock);
2284 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8b53abae 2285 jme_set_unicastaddr(netdev);
95252236
GFT		 2286 spin_unlock_bh(&jme->macaddr_lock);
2287
2288 return 0;
2289}
2290
2291static void
2292jme_set_multi(struct net_device *netdev)
2293{
2294 struct jme_adapter *jme = netdev_priv(netdev);
2295 u32 mc_hash[2] = {};
95252236
GFT		 2296
2297 spin_lock_bh(&jme->rxmcs_lock);
2298
2299 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2300
2301 if (netdev->flags & IFF_PROMISC) {
2302 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2303 } else if (netdev->flags & IFF_ALLMULTI) {
2304 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2305 } else if (netdev->flags & IFF_MULTICAST) {
22bedad3 2306 struct netdev_hw_addr *ha;
95252236
GFT		 2307 int bit_nr;
2308
2309 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
22bedad3
JP		 2310 netdev_for_each_mc_addr(ha, netdev) {
2311 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
95252236
GFT		 2312 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2313 }
2314
2315 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2316 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2317 }
2318
2319 wmb();
2320 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2321
2322 spin_unlock_bh(&jme->rxmcs_lock);
2323}
2324
2325static int
2326jme_change_mtu(struct net_device *netdev, int new_mtu)
2327{
2328 struct jme_adapter *jme = netdev_priv(netdev);
2329
95252236 2330 netdev->mtu = new_mtu;
d7b57654
MM		 2331 netdev_update_features(netdev);
2332
ba9adbe6 2333 jme_restart_rx_engine(jme);
95252236
GFT		 2334 jme_reset_link(jme);
2335
2336 return 0;
2337}
2338
2339static void
0290bd29 2340jme_tx_timeout(struct net_device *netdev, unsigned int txqueue)
95252236
GFT		 2341{
2342 struct jme_adapter *jme = netdev_priv(netdev);
2343
2344 jme->phylink = 0;
2345 jme_reset_phy_processor(jme);
2346 if (test_bit(JME_FLAG_SSET, &jme->flags))
c523838c 2347 jme_set_link_ksettings(netdev, &jme->old_cmd);
95252236
GFT		 2348
2349 /*
2350 * Force to Reset the link again
2351 */
2352 jme_reset_link(jme);
2353}
2354
95252236
GFT		 2355static void
2356jme_get_drvinfo(struct net_device *netdev,
2357 struct ethtool_drvinfo *info)
2358{
2359 struct jme_adapter *jme = netdev_priv(netdev);
2360
23020ab3
RJ		 2361 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2362 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2363 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
95252236
GFT		 2364}
2365
2366static int
2367jme_get_regs_len(struct net_device *netdev)
2368{
2369 return JME_REG_LEN;
2370}
2371
2372static void
2373mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2374{
2375 int i;
2376
2377 for (i = 0 ; i < len ; i += 4)
2378 p[i >> 2] = jread32(jme, reg + i);
2379}
2380
2381static void
2382mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2383{
2384 int i;
2385 u16 *p16 = (u16 *)p;
2386
2387 for (i = 0 ; i < reg_nr ; ++i)
2388 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2389}
2390
2391static void
2392jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2393{
2394 struct jme_adapter *jme = netdev_priv(netdev);
2395 u32 *p32 = (u32 *)p;
2396
2397 memset(p, 0xFF, JME_REG_LEN);
2398
2399 regs->version = 1;
2400 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2401
2402 p32 += 0x100 >> 2;
2403 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2404
2405 p32 += 0x100 >> 2;
2406 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2407
2408 p32 += 0x100 >> 2;
2409 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2410
2411 p32 += 0x100 >> 2;
2412 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2413}
2414
2415static int
2416jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2417{
2418 struct jme_adapter *jme = netdev_priv(netdev);
2419
2420 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2421 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2422
2423 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2424 ecmd->use_adaptive_rx_coalesce = false;
2425 ecmd->rx_coalesce_usecs = 0;
2426 ecmd->rx_max_coalesced_frames = 0;
2427 return 0;
2428 }
2429
2430 ecmd->use_adaptive_rx_coalesce = true;
2431
2432 switch (jme->dpi.cur) {
2433 case PCC_P1:
2434 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2435 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2436 break;
2437 case PCC_P2:
2438 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2439 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2440 break;
2441 case PCC_P3:
2442 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2443 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2444 break;
2445 default:
2446 break;
2447 }
2448
2449 return 0;
2450}
2451
2452static int
2453jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2454{
2455 struct jme_adapter *jme = netdev_priv(netdev);
2456 struct dynpcc_info *dpi = &(jme->dpi);
2457
2458 if (netif_running(netdev))
2459 return -EBUSY;
2460
8e95a202
JP		 2461 if (ecmd->use_adaptive_rx_coalesce &&
2462 test_bit(JME_FLAG_POLL, &jme->flags)) {
95252236
GFT		 2463 clear_bit(JME_FLAG_POLL, &jme->flags);
2464 jme->jme_rx = netif_rx;
95252236
GFT		 2465 dpi->cur = PCC_P1;
2466 dpi->attempt = PCC_P1;
2467 dpi->cnt = 0;
2468 jme_set_rx_pcc(jme, PCC_P1);
2469 jme_interrupt_mode(jme);
8e95a202
JP		 2470 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2471 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
95252236
GFT		 2472 set_bit(JME_FLAG_POLL, &jme->flags);
2473 jme->jme_rx = netif_receive_skb;
95252236
GFT		 2474 jme_interrupt_mode(jme);
2475 }
2476
2477 return 0;
2478}
2479
2480static void
2481jme_get_pauseparam(struct net_device *netdev,
2482 struct ethtool_pauseparam *ecmd)
2483{
2484 struct jme_adapter *jme = netdev_priv(netdev);
2485 u32 val;
2486
2487 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2488 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2489
2490 spin_lock_bh(&jme->phy_lock);
2491 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2492 spin_unlock_bh(&jme->phy_lock);
2493
2494 ecmd->autoneg =
2495 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2496}
2497
2498static int
2499jme_set_pauseparam(struct net_device *netdev,
2500 struct ethtool_pauseparam *ecmd)
2501{
2502 struct jme_adapter *jme = netdev_priv(netdev);
2503 u32 val;
2504
2505 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2506 (ecmd->tx_pause != 0)) {
2507
2508 if (ecmd->tx_pause)
2509 jme->reg_txpfc |= TXPFC_PF_EN;
2510 else
2511 jme->reg_txpfc &= ~TXPFC_PF_EN;
2512
2513 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2514 }
2515
2516 spin_lock_bh(&jme->rxmcs_lock);
2517 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2518 (ecmd->rx_pause != 0)) {
2519
2520 if (ecmd->rx_pause)
2521 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2522 else
2523 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2524
2525 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2526 }
2527 spin_unlock_bh(&jme->rxmcs_lock);
2528
2529 spin_lock_bh(&jme->phy_lock);
2530 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2531 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2532 (ecmd->autoneg != 0)) {
2533
2534 if (ecmd->autoneg)
2535 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2536 else
2537 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2538
2539 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2540 MII_ADVERTISE, val);
2541 }
2542 spin_unlock_bh(&jme->phy_lock);
2543
2544 return 0;
2545}
2546
2547static void
2548jme_get_wol(struct net_device *netdev,
2549 struct ethtool_wolinfo *wol)
2550{
2551 struct jme_adapter *jme = netdev_priv(netdev);
2552
2553 wol->supported = WAKE_MAGIC | WAKE_PHY;
2554
2555 wol->wolopts = 0;
2556
2557 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2558 wol->wolopts |= WAKE_PHY;
2559
2560 if (jme->reg_pmcs & PMCS_MFEN)
2561 wol->wolopts |= WAKE_MAGIC;
2562
2563}
2564
2565static int
2566jme_set_wol(struct net_device *netdev,
2567 struct ethtool_wolinfo *wol)
2568{
2569 struct jme_adapter *jme = netdev_priv(netdev);
2570
2571 if (wol->wolopts & (WAKE_MAGICSECURE |
2572 WAKE_UCAST |
2573 WAKE_MCAST |
2574 WAKE_BCAST |
2575 WAKE_ARP))
2576 return -EOPNOTSUPP;
2577
2578 jme->reg_pmcs = 0;
2579
2580 if (wol->wolopts & WAKE_PHY)
2581 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2582
2583 if (wol->wolopts & WAKE_MAGIC)
2584 jme->reg_pmcs |= PMCS_MFEN;
2585
95252236
GFT		 2586 return 0;
2587}
2588
2589static int
c523838c
PR		 2590jme_get_link_ksettings(struct net_device *netdev,
2591 struct ethtool_link_ksettings *cmd)
95252236
GFT		 2592{
2593 struct jme_adapter *jme = netdev_priv(netdev);
95252236
GFT		 2594
2595 spin_lock_bh(&jme->phy_lock);
82c01a84 2596 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
95252236 2597 spin_unlock_bh(&jme->phy_lock);
82c01a84 2598 return 0;
95252236
GFT		 2599}
2600
2601static int
c523838c
PR		 2602jme_set_link_ksettings(struct net_device *netdev,
2603 const struct ethtool_link_ksettings *cmd)
95252236
GFT		 2604{
2605 struct jme_adapter *jme = netdev_priv(netdev);
2606 int rc, fdc = 0;
2607
c523838c
PR		 2608 if (cmd->base.speed == SPEED_1000 &&
2609 cmd->base.autoneg != AUTONEG_ENABLE)
95252236
GFT		 2610 return -EINVAL;
2611
3ee94018
GFT		 2612 /*
2613 * Check If user changed duplex only while force_media.
2614 * Hardware would not generate link change interrupt.
2615 */
95252236 2616 if (jme->mii_if.force_media &&
c523838c
PR		 2617 cmd->base.autoneg != AUTONEG_ENABLE &&
2618 (jme->mii_if.full_duplex != cmd->base.duplex))
95252236
GFT		 2619 fdc = 1;
2620
2621 spin_lock_bh(&jme->phy_lock);
c523838c 2622 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
95252236
GFT		 2623 spin_unlock_bh(&jme->phy_lock);
2624
95252236 2625 if (!rc) {
3ee94018
GFT		 2626 if (fdc)
2627 jme_reset_link(jme);
c523838c 2628 jme->old_cmd = *cmd;
334fbbb7
GFT		 2629 set_bit(JME_FLAG_SSET, &jme->flags);
2630 }
2631
2632 return rc;
2633}
2634
2635static int
2636jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2637{
2638 int rc;
2639 struct jme_adapter *jme = netdev_priv(netdev);
2640 struct mii_ioctl_data *mii_data = if_mii(rq);
2641 unsigned int duplex_chg;
2642
2643 if (cmd == SIOCSMIIREG) {
2644 u16 val = mii_data->val_in;
2645 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2646 (val & BMCR_SPEED1000))
2647 return -EINVAL;
2648 }
2649
2650 spin_lock_bh(&jme->phy_lock);
2651 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2652 spin_unlock_bh(&jme->phy_lock);
2653
2654 if (!rc && (cmd == SIOCSMIIREG)) {
2655 if (duplex_chg)
2656 jme_reset_link(jme);
c523838c 2657 jme_get_link_ksettings(netdev, &jme->old_cmd);
334fbbb7 2658 set_bit(JME_FLAG_SSET, &jme->flags);
95252236
GFT		 2659 }
2660
2661 return rc;
2662}
2663
2664static u32
2665jme_get_link(struct net_device *netdev)
2666{
2667 struct jme_adapter *jme = netdev_priv(netdev);
2668 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2669}
2670
2671static u32
2672jme_get_msglevel(struct net_device *netdev)
2673{
2674 struct jme_adapter *jme = netdev_priv(netdev);
2675 return jme->msg_enable;
2676}
2677
2678static void
2679jme_set_msglevel(struct net_device *netdev, u32 value)
2680{
2681 struct jme_adapter *jme = netdev_priv(netdev);
2682 jme->msg_enable = value;
2683}
2684
c8f44aff
MM		 2685static netdev_features_t
2686jme_fix_features(struct net_device *netdev, netdev_features_t features)
95252236 2687{
d7b57654 2688 if (netdev->mtu > 1900)
a188222b 2689 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
d7b57654 2690 return features;
95252236
GFT		 2691}
2692
2693static int
c8f44aff 2694jme_set_features(struct net_device *netdev, netdev_features_t features)
95252236
GFT		 2695{
2696 struct jme_adapter *jme = netdev_priv(netdev);
2697
2698 spin_lock_bh(&jme->rxmcs_lock);
d7b57654 2699 if (features & NETIF_F_RXCSUM)
95252236
GFT		 2700 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2701 else
2702 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2703 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2704 spin_unlock_bh(&jme->rxmcs_lock);
2705
2706 return 0;
2707}
2708
ed36d7b2
PW		 2709#ifdef CONFIG_NET_POLL_CONTROLLER
2710static void jme_netpoll(struct net_device *dev)
2711{
2712 unsigned long flags;
2713
2714 local_irq_save(flags);
2715 jme_intr(dev->irq, dev);
2716 local_irq_restore(flags);
2717}
2718#endif
2719
95252236
GFT		 2720static int
2721jme_nway_reset(struct net_device *netdev)
2722{
2723 struct jme_adapter *jme = netdev_priv(netdev);
2724 jme_restart_an(jme);
2725 return 0;
2726}
2727
2728static u8
2729jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2730{
2731 u32 val;
2732 int to;
2733
2734 val = jread32(jme, JME_SMBCSR);
2735 to = JME_SMB_BUSY_TIMEOUT;
2736 while ((val & SMBCSR_BUSY) && --to) {
2737 msleep(1);
2738 val = jread32(jme, JME_SMBCSR);
2739 }
2740 if (!to) {
49d70c48 2741 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2742 return 0xFF;
2743 }
2744
2745 jwrite32(jme, JME_SMBINTF,
2746 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2747 SMBINTF_HWRWN_READ |
2748 SMBINTF_HWCMD);
2749
2750 val = jread32(jme, JME_SMBINTF);
2751 to = JME_SMB_BUSY_TIMEOUT;
2752 while ((val & SMBINTF_HWCMD) && --to) {
2753 msleep(1);
2754 val = jread32(jme, JME_SMBINTF);
2755 }
2756 if (!to) {
49d70c48 2757 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2758 return 0xFF;
2759 }
2760
2761 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2762}
2763
2764static void
2765jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2766{
2767 u32 val;
2768 int to;
2769
2770 val = jread32(jme, JME_SMBCSR);
2771 to = JME_SMB_BUSY_TIMEOUT;
2772 while ((val & SMBCSR_BUSY) && --to) {
2773 msleep(1);
2774 val = jread32(jme, JME_SMBCSR);
2775 }
2776 if (!to) {
49d70c48 2777 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2778 return;
2779 }
2780
2781 jwrite32(jme, JME_SMBINTF,
2782 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2783 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2784 SMBINTF_HWRWN_WRITE |
2785 SMBINTF_HWCMD);
2786
2787 val = jread32(jme, JME_SMBINTF);
2788 to = JME_SMB_BUSY_TIMEOUT;
2789 while ((val & SMBINTF_HWCMD) && --to) {
2790 msleep(1);
2791 val = jread32(jme, JME_SMBINTF);
2792 }
2793 if (!to) {
49d70c48 2794 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
95252236
GFT		 2795 return;
2796 }
2797
2798 mdelay(2);
2799}
2800
2801static int
2802jme_get_eeprom_len(struct net_device *netdev)
2803{
2804 struct jme_adapter *jme = netdev_priv(netdev);
2805 u32 val;
2806 val = jread32(jme, JME_SMBCSR);
2807 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2808}
2809
2810static int
2811jme_get_eeprom(struct net_device *netdev,
2812 struct ethtool_eeprom *eeprom, u8 *data)
2813{
2814 struct jme_adapter *jme = netdev_priv(netdev);
2815 int i, offset = eeprom->offset, len = eeprom->len;
2816
2817 /*
2818 * ethtool will check the boundary for us
2819 */
2820 eeprom->magic = JME_EEPROM_MAGIC;
2821 for (i = 0 ; i < len ; ++i)
2822 data[i] = jme_smb_read(jme, i + offset);
2823
2824 return 0;
2825}
2826
2827static int
2828jme_set_eeprom(struct net_device *netdev,
2829 struct ethtool_eeprom *eeprom, u8 *data)
2830{
2831 struct jme_adapter *jme = netdev_priv(netdev);
2832 int i, offset = eeprom->offset, len = eeprom->len;
2833
2834 if (eeprom->magic != JME_EEPROM_MAGIC)
2835 return -EINVAL;
2836
2837 /*
2838 * ethtool will check the boundary for us
2839 */
2840 for (i = 0 ; i < len ; ++i)
2841 jme_smb_write(jme, i + offset, data[i]);
2842
2843 return 0;
2844}
2845
2846static const struct ethtool_ops jme_ethtool_ops = {
2847 .get_drvinfo = jme_get_drvinfo,
2848 .get_regs_len = jme_get_regs_len,
2849 .get_regs = jme_get_regs,
2850 .get_coalesce = jme_get_coalesce,
2851 .set_coalesce = jme_set_coalesce,
2852 .get_pauseparam = jme_get_pauseparam,
2853 .set_pauseparam = jme_set_pauseparam,
2854 .get_wol = jme_get_wol,
2855 .set_wol = jme_set_wol,
95252236
GFT		 2856 .get_link = jme_get_link,
2857 .get_msglevel = jme_get_msglevel,
2858 .set_msglevel = jme_set_msglevel,
95252236
GFT		 2859 .nway_reset = jme_nway_reset,
2860 .get_eeprom_len = jme_get_eeprom_len,
2861 .get_eeprom = jme_get_eeprom,
2862 .set_eeprom = jme_set_eeprom,
c523838c
PR		 2863 .get_link_ksettings = jme_get_link_ksettings,
2864 .set_link_ksettings = jme_set_link_ksettings,
95252236
GFT		 2865};
2866
2867static int
2868jme_pci_dma64(struct pci_dev *pdev)
2869{
814c01dc 2870 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
e930438c
YH		 2871 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2872 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
814c01dc
GFT		 2873 return 1;
2874
2875 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
e930438c
YH		 2876 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2877 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
814c01dc
GFT		 2878 return 1;
2879
284901a9
YH		 2880 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2881 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
95252236
GFT		 2882 return 0;
2883
2884 return -1;
2885}
2886
2887static inline void
2888jme_phy_init(struct jme_adapter *jme)
2889{
2890 u16 reg26;
2891
2892 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2893 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2894}
2895
2896static inline void
2897jme_check_hw_ver(struct jme_adapter *jme)
2898{
2899 u32 chipmode;
2900
2901 chipmode = jread32(jme, JME_CHIPMODE);
2902
2903 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2904 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
19d96017
GFT		 2905 jme->chip_main_rev = jme->chiprev & 0xF;
2906 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
95252236
GFT		 2907}
2908
e48714ba
SH		 2909static const struct net_device_ops jme_netdev_ops = {
2910 .ndo_open = jme_open,
2911 .ndo_stop = jme_close,
2912 .ndo_validate_addr = eth_validate_addr,
334fbbb7 2913 .ndo_do_ioctl = jme_ioctl,
e48714ba
SH		 2914 .ndo_start_xmit = jme_start_xmit,
2915 .ndo_set_mac_address = jme_set_macaddr,
afc4b13d 2916 .ndo_set_rx_mode = jme_set_multi,
e48714ba
SH		 2917 .ndo_change_mtu = jme_change_mtu,
2918 .ndo_tx_timeout = jme_tx_timeout,
d7b57654
MM		 2919 .ndo_fix_features = jme_fix_features,
2920 .ndo_set_features = jme_set_features,
ed36d7b2
PW		 2921#ifdef CONFIG_NET_POLL_CONTROLLER
2922 .ndo_poll_controller = jme_netpoll,
2923#endif
e48714ba
SH		 2924};
2925
af37557b 2926static int
95252236
GFT		 2927jme_init_one(struct pci_dev *pdev,
2928 const struct pci_device_id *ent)
2929{
2930 int rc = 0, using_dac, i;
2931 struct net_device *netdev;
2932 struct jme_adapter *jme;
2933 u16 bmcr, bmsr;
2934 u32 apmc;
2935
2936 /*
2937 * set up PCI device basics
2938 */
aac9453b
KB		 2939 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2940 PCIE_LINK_STATE_CLKPM);
2941
95252236
GFT		 2942 rc = pci_enable_device(pdev);
2943 if (rc) {
49d70c48 2944 pr_err("Cannot enable PCI device\n");
95252236
GFT		 2945 goto err_out;
2946 }
2947
2948 using_dac = jme_pci_dma64(pdev);
2949 if (using_dac < 0) {
49d70c48 2950 pr_err("Cannot set PCI DMA Mask\n");
95252236
GFT		 2951 rc = -EIO;
2952 goto err_out_disable_pdev;
2953 }
2954
2955 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
49d70c48 2956 pr_err("No PCI resource region found\n");
95252236
GFT		 2957 rc = -ENOMEM;
2958 goto err_out_disable_pdev;
2959 }
2960
2961 rc = pci_request_regions(pdev, DRV_NAME);
2962 if (rc) {
49d70c48 2963 pr_err("Cannot obtain PCI resource region\n");
95252236
GFT		 2964 goto err_out_disable_pdev;
2965 }
2966
2967 pci_set_master(pdev);
2968
2969 /*
2970 * alloc and init net device
2971 */
2972 netdev = alloc_etherdev(sizeof(*jme));
2973 if (!netdev) {
95252236
GFT		 2974 rc = -ENOMEM;
2975 goto err_out_release_regions;
2976 }
e48714ba 2977 netdev->netdev_ops = &jme_netdev_ops;
95252236 2978 netdev->ethtool_ops = &jme_ethtool_ops;
95252236 2979 netdev->watchdog_timeo = TX_TIMEOUT;
d7b57654
MM		 2980 netdev->hw_features = NETIF_F_IP_CSUM |
2981 NETIF_F_IPV6_CSUM |
2982 NETIF_F_SG |
2983 NETIF_F_TSO |
2984 NETIF_F_TSO6 |
2985 NETIF_F_RXCSUM;
79032644
MM		 2986 netdev->features = NETIF_F_IP_CSUM |
2987 NETIF_F_IPV6_CSUM |
95252236
GFT		 2988 NETIF_F_SG |
2989 NETIF_F_TSO |
2990 NETIF_F_TSO6 |
f646968f
PM		 2991 NETIF_F_HW_VLAN_CTAG_TX |
2992 NETIF_F_HW_VLAN_CTAG_RX;
95252236
GFT		 2993 if (using_dac)
2994 netdev->features |= NETIF_F_HIGHDMA;
2995
d894be57
JW		 2996 /* MTU range: 1280 - 9202*/
2997 netdev->min_mtu = IPV6_MIN_MTU;
2998 netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
2999
95252236
GFT		 3000 SET_NETDEV_DEV(netdev, &pdev->dev);
3001 pci_set_drvdata(pdev, netdev);
3002
3003 /*
3004 * init adapter info
3005 */
3006 jme = netdev_priv(netdev);
3007 jme->pdev = pdev;
3008 jme->dev = netdev;
3009 jme->jme_rx = netif_rx;
95252236
GFT		 3010 jme->old_mtu = netdev->mtu = 1500;
3011 jme->phylink = 0;
3012 jme->tx_ring_size = 1 << 10;
3013 jme->tx_ring_mask = jme->tx_ring_size - 1;
3014 jme->tx_wake_threshold = 1 << 9;
3015 jme->rx_ring_size = 1 << 9;
3016 jme->rx_ring_mask = jme->rx_ring_size - 1;
3017 jme->msg_enable = JME_DEF_MSG_ENABLE;
3018 jme->regs = ioremap(pci_resource_start(pdev, 0),
3019 pci_resource_len(pdev, 0));
3020 if (!(jme->regs)) {
49d70c48 3021 pr_err("Mapping PCI resource region error\n");
95252236
GFT		 3022 rc = -ENOMEM;
3023 goto err_out_free_netdev;
3024 }
95252236
GFT		 3025
3026 if (no_pseudohp) {
3027 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3028 jwrite32(jme, JME_APMC, apmc);
3029 } else if (force_pseudohp) {
3030 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3031 jwrite32(jme, JME_APMC, apmc);
3032 }
3033
449cfcc1 3034 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT)
95252236
GFT		 3035
3036 spin_lock_init(&jme->phy_lock);
3037 spin_lock_init(&jme->macaddr_lock);
3038 spin_lock_init(&jme->rxmcs_lock);
3039
3040 atomic_set(&jme->link_changing, 1);
3041 atomic_set(&jme->rx_cleaning, 1);
3042 atomic_set(&jme->tx_cleaning, 1);
3043 atomic_set(&jme->rx_empty, 1);
3044
3045 tasklet_init(&jme->pcc_task,
164165da 3046 jme_pcc_tasklet,
95252236 3047 (unsigned long) jme);
95252236
GFT		 3048 jme->dpi.cur = PCC_P1;
3049
3050 jme->reg_ghc = 0;
3051 jme->reg_rxcs = RXCS_DEFAULT;
3052 jme->reg_rxmcs = RXMCS_DEFAULT;
3053 jme->reg_txpfc = 0;
3054 jme->reg_pmcs = PMCS_MFEN;
854a2e7c 3055 jme->reg_gpreg1 = GPREG1_DEFAULT;
d7b57654
MM		 3056
3057 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3058 netdev->features |= NETIF_F_RXCSUM;
95252236
GFT		 3059
3060 /*
3061 * Get Max Read Req Size from PCI Config Space
3062 */
3063 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3064 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3065 switch (jme->mrrs) {
3066 case MRRS_128B:
3067 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3068 break;
3069 case MRRS_256B:
3070 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3071 break;
3072 default:
3073 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3074 break;
ee289b64 3075 }
95252236
GFT		 3076
3077 /*
3078 * Must check before reset_mac_processor
3079 */
3080 jme_check_hw_ver(jme);
3081 jme->mii_if.dev = netdev;
3082 if (jme->fpgaver) {
3083 jme->mii_if.phy_id = 0;
3084 for (i = 1 ; i < 32 ; ++i) {
3085 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3086 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3087 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3088 jme->mii_if.phy_id = i;
3089 break;
3090 }
3091 }
3092
3093 if (!jme->mii_if.phy_id) {
3094 rc = -EIO;
49d70c48
JP		 3095 pr_err("Can not find phy_id\n");
3096 goto err_out_unmap;
95252236
GFT		 3097 }
3098
3099 jme->reg_ghc |= GHC_LINK_POLL;
3100 } else {
3101 jme->mii_if.phy_id = 1;
3102 }
3103 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3104 jme->mii_if.supports_gmii = true;
3105 else
3106 jme->mii_if.supports_gmii = false;
334fbbb7
GFT		 3107 jme->mii_if.phy_id_mask = 0x1F;
3108 jme->mii_if.reg_num_mask = 0x1F;
95252236
GFT		 3109 jme->mii_if.mdio_read = jme_mdio_read;
3110 jme->mii_if.mdio_write = jme_mdio_write;
3111
0772a99b 3112 jme_clear_pm_disable_wol(jme);
81422e67 3113 device_init_wakeup(&pdev->dev, true);
bc057e03 3114
51754572 3115 jme_set_phyfifo_5level(jme);
ff938e43 3116 jme->pcirev = pdev->revision;
95252236
GFT		 3117 if (!jme->fpgaver)
3118 jme_phy_init(jme);
3119 jme_phy_off(jme);
3120
3121 /*
3122 * Reset MAC processor and reload EEPROM for MAC Address
3123 */
3124 jme_reset_mac_processor(jme);
3125 rc = jme_reload_eeprom(jme);
3126 if (rc) {
49d70c48 3127 pr_err("Reload eeprom for reading MAC Address error\n");
d1dfa1d1 3128 goto err_out_unmap;
95252236
GFT		 3129 }
3130 jme_load_macaddr(netdev);
3131
3132 /*
3133 * Tell stack that we are not ready to work until open()
3134 */
3135 netif_carrier_off(netdev);
95252236 3136
95252236
GFT		 3137 rc = register_netdev(netdev);
3138 if (rc) {
49d70c48 3139 pr_err("Cannot register net device\n");
d1dfa1d1 3140 goto err_out_unmap;
95252236
GFT		 3141 }
3142
19d96017 3143 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
f8502ce4
JP		 3144 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3145 "JMC250 Gigabit Ethernet" :
3146 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3147 "JMC260 Fast Ethernet" : "Unknown",
3148 (jme->fpgaver != 0) ? " (FPGA)" : "",
3149 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
19d96017 3150 jme->pcirev, netdev->dev_addr);
95252236
GFT		 3151
3152 return 0;
3153
95252236
GFT		 3154err_out_unmap:
3155 iounmap(jme->regs);
3156err_out_free_netdev:
95252236
GFT		 3157 free_netdev(netdev);
3158err_out_release_regions:
3159 pci_release_regions(pdev);
3160err_out_disable_pdev:
3161 pci_disable_device(pdev);
3162err_out:
3163 return rc;
3164}
3165
af37557b 3166static void
95252236
GFT		 3167jme_remove_one(struct pci_dev *pdev)
3168{
3169 struct net_device *netdev = pci_get_drvdata(pdev);
3170 struct jme_adapter *jme = netdev_priv(netdev);
3171
3172 unregister_netdev(netdev);
95252236 3173 iounmap(jme->regs);
95252236
GFT		 3174 free_netdev(netdev);
3175 pci_release_regions(pdev);
3176 pci_disable_device(pdev);
3177
3178}
3179
1c557819
GFT		 3180static void
3181jme_shutdown(struct pci_dev *pdev)
3182{
3183 struct net_device *netdev = pci_get_drvdata(pdev);
3184 struct jme_adapter *jme = netdev_priv(netdev);
3185
3186 jme_powersave_phy(jme);
3187 pci_pme_active(pdev, true);
3188}
3189
aab6fb82 3190#ifdef CONFIG_PM_SLEEP
bc057e03
GFT		 3191static int
3192jme_suspend(struct device *dev)
95252236 3193{
c9b6c56d 3194 struct net_device *netdev = dev_get_drvdata(dev);
95252236
GFT		 3195 struct jme_adapter *jme = netdev_priv(netdev);
3196
a7d5b76d
CB		 3197 if (!netif_running(netdev))
3198 return 0;
3199
95252236
GFT		 3200 atomic_dec(&jme->link_changing);
3201
3202 netif_device_detach(netdev);
3203 netif_stop_queue(netdev);
3204 jme_stop_irq(jme);
3205
3206 tasklet_disable(&jme->txclean_task);
3207 tasklet_disable(&jme->rxclean_task);
3208 tasklet_disable(&jme->rxempty_task);
3209
95252236
GFT		 3210 if (netif_carrier_ok(netdev)) {
3211 if (test_bit(JME_FLAG_POLL, &jme->flags))
3212 jme_polling_mode(jme);
3213
3214 jme_stop_pcc_timer(jme);
95252236
GFT		 3215 jme_disable_rx_engine(jme);
3216 jme_disable_tx_engine(jme);
3217 jme_reset_mac_processor(jme);
3218 jme_free_rx_resources(jme);
3219 jme_free_tx_resources(jme);
3220 netif_carrier_off(netdev);
3221 jme->phylink = 0;
3222 }
3223
3224 tasklet_enable(&jme->txclean_task);
06f66529
QL		 3225 tasklet_enable(&jme->rxclean_task);
3226 tasklet_enable(&jme->rxempty_task);
95252236 3227
1c557819 3228 jme_powersave_phy(jme);
95252236
GFT		 3229
3230 return 0;
3231}
3232
bc057e03
GFT		 3233static int
3234jme_resume(struct device *dev)
95252236 3235{
c9b6c56d 3236 struct net_device *netdev = dev_get_drvdata(dev);
95252236
GFT		 3237 struct jme_adapter *jme = netdev_priv(netdev);
3238
a7d5b76d
CB		 3239 if (!netif_running(netdev))
3240 return 0;
3241
0772a99b 3242 jme_clear_pm_disable_wol(jme);
4872b11f
GFT		 3243 jme_phy_on(jme);
3244 if (test_bit(JME_FLAG_SSET, &jme->flags))
c523838c 3245 jme_set_link_ksettings(netdev, &jme->old_cmd);
4872b11f 3246 else
95252236 3247 jme_reset_phy_processor(jme);
c4860ba2
AL		 3248 jme_phy_calibration(jme);
3249 jme_phy_setEA(jme);
95252236
GFT		 3250 netif_device_attach(netdev);
3251
3252 atomic_inc(&jme->link_changing);
3253
3254 jme_reset_link(jme);
3255
ee50c130
DV		 3256 jme_start_irq(jme);
3257
95252236
GFT		 3258 return 0;
3259}
f4e5bd4f
RW		 3260
3261static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3262#define JME_PM_OPS (&jme_pm_ops)
3263
3264#else
3265
3266#define JME_PM_OPS NULL
724f8805 3267#endif
95252236 3268
9baa3c34 3269static const struct pci_device_id jme_pci_tbl[] = {
95252236
GFT		 3270 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3271 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3272 { }
3273};
3274
3275static struct pci_driver jme_driver = {
3276 .name = DRV_NAME,
3277 .id_table = jme_pci_tbl,
3278 .probe = jme_init_one,
af37557b 3279 .remove = jme_remove_one,
1c557819 3280 .shutdown = jme_shutdown,
f4e5bd4f 3281 .driver.pm = JME_PM_OPS,
95252236
GFT		 3282};
3283
3284static int __init
3285jme_init_module(void)
3286{
49d70c48 3287 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
95252236
GFT		 3288 return pci_register_driver(&jme_driver);
3289}
3290
3291static void __exit
3292jme_cleanup_module(void)
3293{
3294 pci_unregister_driver(&jme_driver);
3295}
3296
3297module_init(jme_init_module);
3298module_exit(jme_cleanup_module);
3299
3300MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3301MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3302MODULE_LICENSE("GPL");
3303MODULE_VERSION(DRV_VERSION);
3304MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
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