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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
7542db8b
JP		 38#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/dma-mapping.h>
b6298c22 42#include <linux/in.h>
c3efab8e 43#include <linux/ip.h>
1da177e4
LT		 44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/etherdevice.h>
1da177e4
LT		 47#include <linux/delay.h>
48#include <linux/ethtool.h>
d052d1be 49#include <linux/platform_device.h>
fbd6a754
LB		 50#include <linux/module.h>
51#include <linux/kernel.h>
52#include <linux/spinlock.h>
53#include <linux/workqueue.h>
ed94493f 54#include <linux/phy.h>
fbd6a754 55#include <linux/mv643xx_eth.h>
10a9948d
LB		 56#include <linux/io.h>
57#include <linux/types.h>
eaf5d590 58#include <linux/inet_lro.h>
5a0e3ad6 59#include <linux/slab.h>
1da177e4 60#include <asm/system.h>
fbd6a754 61
e5371493 62static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 63static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 64
fbd6a754 65
fbd6a754
LB		 66/*
67 * Registers shared between all ports.
68 */
3cb4667c
LB		 69#define PHY_ADDR 0x0000
70#define SMI_REG 0x0004
45c5d3bc
LB		 71#define SMI_BUSY 0x10000000
72#define SMI_READ_VALID 0x08000000
73#define SMI_OPCODE_READ 0x04000000
74#define SMI_OPCODE_WRITE 0x00000000
75#define ERR_INT_CAUSE 0x0080
76#define ERR_INT_SMI_DONE 0x00000010
77#define ERR_INT_MASK 0x0084
3cb4667c
LB		 78#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81#define WINDOW_BAR_ENABLE 0x0290
82#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 83
84/*
37a6084f
LB		 85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 87 */
37a6084f 88#define PORT_CONFIG 0x0000
d9a073ea 89#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 90#define PORT_CONFIG_EXT 0x0004
91#define MAC_ADDR_LOW 0x0014
92#define MAC_ADDR_HIGH 0x0018
93#define SDMA_CONFIG 0x001c
becfad97
LB		 94#define TX_BURST_SIZE_16_64BIT 0x01000000
95#define TX_BURST_SIZE_4_64BIT 0x00800000
96#define BLM_TX_NO_SWAP 0x00000020
97#define BLM_RX_NO_SWAP 0x00000010
98#define RX_BURST_SIZE_16_64BIT 0x00000008
99#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 100#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 101#define SET_MII_SPEED_TO_100 0x01000000
102#define SET_GMII_SPEED_TO_1000 0x00800000
103#define SET_FULL_DUPLEX_MODE 0x00200000
104#define MAX_RX_PACKET_9700BYTE 0x000a0000
105#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106#define DO_NOT_FORCE_LINK_FAIL 0x00000400
107#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110#define FORCE_LINK_PASS 0x00000002
111#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 112#define PORT_STATUS 0x0044
a2a41689 113#define TX_FIFO_EMPTY 0x00000400
ae9ae064 114#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 115#define PORT_SPEED_MASK 0x00000030
116#define PORT_SPEED_1000 0x00000010
117#define PORT_SPEED_100 0x00000020
118#define PORT_SPEED_10 0x00000000
119#define FLOW_CONTROL_ENABLED 0x00000008
120#define FULL_DUPLEX 0x00000004
81600eea 121#define LINK_UP 0x00000002
37a6084f
LB		 122#define TXQ_COMMAND 0x0048
123#define TXQ_FIX_PRIO_CONF 0x004c
124#define TX_BW_RATE 0x0050
125#define TX_BW_MTU 0x0058
126#define TX_BW_BURST 0x005c
127#define INT_CAUSE 0x0060
226bb6b7 128#define INT_TX_END 0x07f80000
e0ca8410 129#define INT_TX_END_0 0x00080000
befefe21 130#define INT_RX 0x000003fc
e0ca8410 131#define INT_RX_0 0x00000004
073a345c 132#define INT_EXT 0x00000002
37a6084f 133#define INT_CAUSE_EXT 0x0064
befefe21
LB		 134#define INT_EXT_LINK_PHY 0x00110000
135#define INT_EXT_TX 0x000000ff
37a6084f
LB		 136#define INT_MASK 0x0068
137#define INT_MASK_EXT 0x006c
138#define TX_FIFO_URGENT_THRESHOLD 0x0074
139#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
140#define TX_BW_RATE_MOVED 0x00e0
141#define TX_BW_MTU_MOVED 0x00e8
142#define TX_BW_BURST_MOVED 0x00ec
143#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
144#define RXQ_COMMAND 0x0280
145#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
146#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
147#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
148#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
149
150/*
151 * Misc per-port registers.
152 */
3cb4667c
LB		 153#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
154#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
155#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
156#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 157
2679a550
LB		 158
159/*
becfad97 160 * SDMA configuration register default value.
2679a550 161 */
fbd6a754
LB		 162#if defined(__BIG_ENDIAN)
163#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 164 (RX_BURST_SIZE_4_64BIT | \
165 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 166#elif defined(__LITTLE_ENDIAN)
167#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 168 (RX_BURST_SIZE_4_64BIT | \
169 BLM_RX_NO_SWAP | \
170 BLM_TX_NO_SWAP | \
171 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 172#else
173#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
174#endif
175
2beff77b
LB		 176
177/*
becfad97 178 * Misc definitions.
2beff77b 179 */
becfad97
LB		 180#define DEFAULT_RX_QUEUE_SIZE 128
181#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 182#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 183
fbd6a754 184
7ca72a3b
LB		 185/*
186 * RX/TX descriptors.
fbd6a754
LB		 187 */
188#if defined(__BIG_ENDIAN)
cc9754b3 189struct rx_desc {
fbd6a754
LB		 190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
195};
196
cc9754b3 197struct tx_desc {
fbd6a754
LB		 198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
203};
204#elif defined(__LITTLE_ENDIAN)
cc9754b3 205struct rx_desc {
fbd6a754
LB		 206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
211};
212
cc9754b3 213struct tx_desc {
fbd6a754
LB		 214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
219};
220#else
221#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
222#endif
223
7ca72a3b 224/* RX & TX descriptor command */
cc9754b3 225#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 226
227/* RX & TX descriptor status */
cc9754b3 228#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 229
230/* RX descriptor status */
cc9754b3
LB		 231#define LAYER_4_CHECKSUM_OK 0x40000000
232#define RX_ENABLE_INTERRUPT 0x20000000
233#define RX_FIRST_DESC 0x08000000
234#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 235#define RX_IP_HDR_OK 0x02000000
236#define RX_PKT_IS_IPV4 0x01000000
237#define RX_PKT_IS_ETHERNETV2 0x00800000
238#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
239#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
240#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 241
242/* TX descriptor command */
cc9754b3
LB		 243#define TX_ENABLE_INTERRUPT 0x00800000
244#define GEN_CRC 0x00400000
245#define TX_FIRST_DESC 0x00200000
246#define TX_LAST_DESC 0x00100000
247#define ZERO_PADDING 0x00080000
248#define GEN_IP_V4_CHECKSUM 0x00040000
249#define GEN_TCP_UDP_CHECKSUM 0x00020000
250#define UDP_FRAME 0x00010000
e32b6617
LB		 251#define MAC_HDR_EXTRA_4_BYTES 0x00008000
252#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 253
cc9754b3 254#define TX_IHL_SHIFT 11
7ca72a3b
LB		 255
256
c9df406f 257/* global *******************************************************************/
e5371493 258struct mv643xx_eth_shared_private {
fc32b0e2
LB		 259 /*
260 * Ethernet controller base address.
261 */
cc9754b3 262 void __iomem *base;
c9df406f 263
fc0eb9f2
LB		 264 /*
265 * Points at the right SMI instance to use.
266 */
267 struct mv643xx_eth_shared_private *smi;
268
fc32b0e2 269 /*
ed94493f 270 * Provides access to local SMI interface.
fc32b0e2 271 */
298cf9be 272 struct mii_bus *smi_bus;
c9df406f 273
45c5d3bc
LB		 274 /*
275 * If we have access to the error interrupt pin (which is
276 * somewhat misnamed as it not only reflects internal errors
277 * but also reflects SMI completion), use that to wait for
278 * SMI access completion instead of polling the SMI busy bit.
279 */
280 int err_interrupt;
281 wait_queue_head_t smi_busy_wait;
282
fc32b0e2
LB		 283 /*
284 * Per-port MBUS window access register value.
285 */
c9df406f
LB		 286 u32 win_protect;
287
fc32b0e2
LB		 288 /*
289 * Hardware-specific parameters.
290 */
c9df406f 291 unsigned int t_clk;
773fc3ee 292 int extended_rx_coal_limit;
457b1d5a 293 int tx_bw_control;
9b2c2ff7 294 int tx_csum_limit;
c9df406f
LB		 295};
296
457b1d5a
LB		 297#define TX_BW_CONTROL_ABSENT 0
298#define TX_BW_CONTROL_OLD_LAYOUT 1
299#define TX_BW_CONTROL_NEW_LAYOUT 2
300
e7d2f4db
LB		 301static int mv643xx_eth_open(struct net_device *dev);
302static int mv643xx_eth_stop(struct net_device *dev);
303
c9df406f
LB		 304
305/* per-port *****************************************************************/
e5371493 306struct mib_counters {
fbd6a754
LB		 307 u64 good_octets_received;
308 u32 bad_octets_received;
309 u32 internal_mac_transmit_err;
310 u32 good_frames_received;
311 u32 bad_frames_received;
312 u32 broadcast_frames_received;
313 u32 multicast_frames_received;
314 u32 frames_64_octets;
315 u32 frames_65_to_127_octets;
316 u32 frames_128_to_255_octets;
317 u32 frames_256_to_511_octets;
318 u32 frames_512_to_1023_octets;
319 u32 frames_1024_to_max_octets;
320 u64 good_octets_sent;
321 u32 good_frames_sent;
322 u32 excessive_collision;
323 u32 multicast_frames_sent;
324 u32 broadcast_frames_sent;
325 u32 unrec_mac_control_received;
326 u32 fc_sent;
327 u32 good_fc_received;
328 u32 bad_fc_received;
329 u32 undersize_received;
330 u32 fragments_received;
331 u32 oversize_received;
332 u32 jabber_received;
333 u32 mac_receive_error;
334 u32 bad_crc_event;
335 u32 collision;
336 u32 late_collision;
337};
338
eaf5d590
LB		 339struct lro_counters {
340 u32 lro_aggregated;
341 u32 lro_flushed;
342 u32 lro_no_desc;
343};
344
8a578111 345struct rx_queue {
64da80a2
LB		 346 int index;
347
8a578111
LB		 348 int rx_ring_size;
349
350 int rx_desc_count;
351 int rx_curr_desc;
352 int rx_used_desc;
353
354 struct rx_desc *rx_desc_area;
355 dma_addr_t rx_desc_dma;
356 int rx_desc_area_size;
357 struct sk_buff **rx_skb;
eaf5d590 358
eaf5d590
LB		 359 struct net_lro_mgr lro_mgr;
360 struct net_lro_desc lro_arr[8];
8a578111
LB		 361};
362
13d64285 363struct tx_queue {
3d6b35bc
LB		 364 int index;
365
13d64285 366 int tx_ring_size;
fbd6a754 367
13d64285
LB		 368 int tx_desc_count;
369 int tx_curr_desc;
370 int tx_used_desc;
fbd6a754 371
5daffe94 372 struct tx_desc *tx_desc_area;
fbd6a754
LB		 373 dma_addr_t tx_desc_dma;
374 int tx_desc_area_size;
99ab08e0
LB		 375
376 struct sk_buff_head tx_skb;
8fd89211
LB		 377
378 unsigned long tx_packets;
379 unsigned long tx_bytes;
380 unsigned long tx_dropped;
13d64285
LB		 381};
382
383struct mv643xx_eth_private {
384 struct mv643xx_eth_shared_private *shared;
37a6084f 385 void __iomem *base;
fc32b0e2 386 int port_num;
13d64285 387
fc32b0e2 388 struct net_device *dev;
fbd6a754 389
ed94493f 390 struct phy_device *phy;
fbd6a754 391
4ff3495a
LB		 392 struct timer_list mib_counters_timer;
393 spinlock_t mib_counters_lock;
fc32b0e2 394 struct mib_counters mib_counters;
4ff3495a 395
eaf5d590
LB		 396 struct lro_counters lro_counters;
397
fc32b0e2 398 struct work_struct tx_timeout_task;
8a578111 399
1fa38c58 400 struct napi_struct napi;
e0ca8410 401 u32 int_mask;
1319ebad 402 u8 oom;
1fa38c58
LB		 403 u8 work_link;
404 u8 work_tx;
405 u8 work_tx_end;
406 u8 work_rx;
407 u8 work_rx_refill;
1fa38c58 408
2bcb4b0f
LB		 409 int skb_size;
410 struct sk_buff_head rx_recycle;
411
8a578111
LB		 412 /*
413 * RX state.
414 */
e7d2f4db 415 int rx_ring_size;
8a578111
LB		 416 unsigned long rx_desc_sram_addr;
417 int rx_desc_sram_size;
f7981c1c 418 int rxq_count;
2257e05c 419 struct timer_list rx_oom;
64da80a2 420 struct rx_queue rxq[8];
13d64285
LB		 421
422 /*
423 * TX state.
424 */
e7d2f4db 425 int tx_ring_size;
13d64285
LB		 426 unsigned long tx_desc_sram_addr;
427 int tx_desc_sram_size;
f7981c1c 428 int txq_count;
3d6b35bc 429 struct tx_queue txq[8];
fbd6a754 430};
1da177e4 431
fbd6a754 432
c9df406f 433/* port register accessors **************************************************/
e5371493 434static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 435{
cc9754b3 436 return readl(mp->shared->base + offset);
c9df406f 437}
fbd6a754 438
37a6084f
LB		 439static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
440{
441 return readl(mp->base + offset);
442}
443
e5371493 444static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 445{
cc9754b3 446 writel(data, mp->shared->base + offset);
c9df406f 447}
fbd6a754 448
37a6084f
LB		 449static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
450{
451 writel(data, mp->base + offset);
452}
453
fbd6a754 454
c9df406f 455/* rxq/txq helper functions *************************************************/
8a578111 456static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 457{
64da80a2 458 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 459}
fbd6a754 460
13d64285
LB		 461static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
462{
3d6b35bc 463 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 464}
465
8a578111 466static void rxq_enable(struct rx_queue *rxq)
c9df406f 467{
8a578111 468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 469 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 470}
1da177e4 471
8a578111
LB		 472static void rxq_disable(struct rx_queue *rxq)
473{
474 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 475 u8 mask = 1 << rxq->index;
1da177e4 476
37a6084f
LB		 477 wrlp(mp, RXQ_COMMAND, mask << 8);
478 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 479 udelay(10);
c9df406f
LB		 480}
481
6b368f68
LB		 482static void txq_reset_hw_ptr(struct tx_queue *txq)
483{
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 485 u32 addr;
486
487 addr = (u32)txq->tx_desc_dma;
488 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 489 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 490}
491
13d64285 492static void txq_enable(struct tx_queue *txq)
1da177e4 493{
13d64285 494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 495 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 496}
497
13d64285 498static void txq_disable(struct tx_queue *txq)
1da177e4 499{
13d64285 500 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 501 u8 mask = 1 << txq->index;
c9df406f 502
37a6084f
LB		 503 wrlp(mp, TXQ_COMMAND, mask << 8);
504 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 505 udelay(10);
506}
507
1fa38c58 508static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 509{
510 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 511 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 512
8fd89211
LB		 513 if (netif_tx_queue_stopped(nq)) {
514 __netif_tx_lock(nq, smp_processor_id());
515 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
516 netif_tx_wake_queue(nq);
517 __netif_tx_unlock(nq);
518 }
1da177e4
LT		 519}
520
c9df406f 521
1fa38c58 522/* rx napi ******************************************************************/
eaf5d590
LB		 523static int
524mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
525 u64 *hdr_flags, void *priv)
526{
527 unsigned long cmd_sts = (unsigned long)priv;
528
529 /*
530 * Make sure that this packet is Ethernet II, is not VLAN
531 * tagged, is IPv4, has a valid IP header, and is TCP.
532 */
533 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
535 RX_PKT_IS_VLAN_TAGGED)) !=
536 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
537 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
538 return -1;
539
540 skb_reset_network_header(skb);
541 skb_set_transport_header(skb, ip_hdrlen(skb));
542 *iphdr = ip_hdr(skb);
543 *tcph = tcp_hdr(skb);
544 *hdr_flags = LRO_IPV4 | LRO_TCP;
545
546 return 0;
547}
eaf5d590 548
8a578111 549static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 550{
8a578111
LB		 551 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
552 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 553 int lro_flush_needed;
8a578111 554 int rx;
1da177e4 555
eaf5d590 556 lro_flush_needed = 0;
8a578111 557 rx = 0;
9e1f3772 558 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 559 struct rx_desc *rx_desc;
96587661 560 unsigned int cmd_sts;
fc32b0e2 561 struct sk_buff *skb;
6b8f90c2 562 u16 byte_cnt;
ff561eef 563
8a578111 564 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 565
96587661 566 cmd_sts = rx_desc->cmd_sts;
2257e05c 567 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 568 break;
96587661 569 rmb();
1da177e4 570
8a578111
LB		 571 skb = rxq->rx_skb[rxq->rx_curr_desc];
572 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 573
9da78745
LB		 574 rxq->rx_curr_desc++;
575 if (rxq->rx_curr_desc == rxq->rx_ring_size)
576 rxq->rx_curr_desc = 0;
ff561eef 577
eb0519b5 578 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 579 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 580 rxq->rx_desc_count--;
581 rx++;
b1dd9ca1 582
1fa38c58
LB		 583 mp->work_rx_refill |= 1 << rxq->index;
584
6b8f90c2
LB		 585 byte_cnt = rx_desc->byte_cnt;
586
468d09f8
DF		 587 /*
588 * Update statistics.
fc32b0e2
LB		 589 *
590 * Note that the descriptor byte count includes 2 dummy
591 * bytes automatically inserted by the hardware at the
592 * start of the packet (which we don't count), and a 4
593 * byte CRC at the end of the packet (which we do count).
468d09f8 594 */
1da177e4 595 stats->rx_packets++;
6b8f90c2 596 stats->rx_bytes += byte_cnt - 2;
96587661 597
1da177e4 598 /*
fc32b0e2
LB		 599 * In case we received a packet without first / last bits
600 * on, or the error summary bit is set, the packet needs
601 * to be dropped.
1da177e4 602 */
f61e5547
LB		 603 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
604 != (RX_FIRST_DESC | RX_LAST_DESC))
605 goto err;
606
607 /*
608 * The -4 is for the CRC in the trailer of the
609 * received packet
610 */
611 skb_put(skb, byte_cnt - 2 - 4);
612
613 if (cmd_sts & LAYER_4_CHECKSUM_OK)
614 skb->ip_summed = CHECKSUM_UNNECESSARY;
615 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 616
eaf5d590
LB		 617 if (skb->dev->features & NETIF_F_LRO &&
618 skb->ip_summed == CHECKSUM_UNNECESSARY) {
619 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
620 lro_flush_needed = 1;
621 } else
eaf5d590 622 netif_receive_skb(skb);
f61e5547
LB		 623
624 continue;
625
626err:
627 stats->rx_dropped++;
628
629 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
630 (RX_FIRST_DESC | RX_LAST_DESC)) {
631 if (net_ratelimit())
7542db8b
JP		 632 netdev_err(mp->dev,
633 "received packet spanning multiple descriptors\n");
1da177e4 634 }
f61e5547
LB		 635
636 if (cmd_sts & ERROR_SUMMARY)
637 stats->rx_errors++;
638
639 dev_kfree_skb(skb);
1da177e4 640 }
fc32b0e2 641
eaf5d590
LB		 642 if (lro_flush_needed)
643 lro_flush_all(&rxq->lro_mgr);
eaf5d590 644
1fa38c58
LB		 645 if (rx < budget)
646 mp->work_rx &= ~(1 << rxq->index);
647
8a578111 648 return rx;
1da177e4
LT		 649}
650
1fa38c58 651static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 652{
1fa38c58 653 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 654 int refilled;
8a578111 655
1fa38c58
LB		 656 refilled = 0;
657 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
658 struct sk_buff *skb;
1fa38c58 659 int rx;
53771522 660 struct rx_desc *rx_desc;
530e557a 661 int size;
d0412d96 662
2bcb4b0f
LB		 663 skb = __skb_dequeue(&mp->rx_recycle);
664 if (skb == NULL)
7fd96ce4 665 skb = dev_alloc_skb(mp->skb_size);
2bcb4b0f 666
1fa38c58 667 if (skb == NULL) {
1319ebad 668 mp->oom = 1;
1fa38c58
LB		 669 goto oom;
670 }
d0412d96 671
7fd96ce4
LB		 672 if (SKB_DMA_REALIGN)
673 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 674
1fa38c58
LB		 675 refilled++;
676 rxq->rx_desc_count++;
c9df406f 677
1fa38c58
LB		 678 rx = rxq->rx_used_desc++;
679 if (rxq->rx_used_desc == rxq->rx_ring_size)
680 rxq->rx_used_desc = 0;
2257e05c 681
53771522
LB		 682 rx_desc = rxq->rx_desc_area + rx;
683
530e557a 684 size = skb->end - skb->data;
eb0519b5 685 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 686 skb->data, size,
eb0519b5 687 DMA_FROM_DEVICE);
530e557a 688 rx_desc->buf_size = size;
1fa38c58
LB		 689 rxq->rx_skb[rx] = skb;
690 wmb();
53771522 691 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 692 wmb();
2257e05c 693
1fa38c58
LB		 694 /*
695 * The hardware automatically prepends 2 bytes of
696 * dummy data to each received packet, so that the
697 * IP header ends up 16-byte aligned.
698 */
699 skb_reserve(skb, 2);
700 }
701
702 if (refilled < budget)
703 mp->work_rx_refill &= ~(1 << rxq->index);
704
705oom:
706 return refilled;
d0412d96
JC		 707}
708
c9df406f
LB		 709
710/* tx ***********************************************************************/
c9df406f 711static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 712{
13d64285 713 int frag;
1da177e4 714
c9df406f 715 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
9e903e08
ED		 716 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
717
718 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
c9df406f 719 return 1;
1da177e4 720 }
13d64285 721
c9df406f
LB		 722 return 0;
723}
7303fde8 724
13d64285 725static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 726{
eb0519b5 727 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 728 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 729 int frag;
1da177e4 730
13d64285
LB		 731 for (frag = 0; frag < nr_frags; frag++) {
732 skb_frag_t *this_frag;
733 int tx_index;
734 struct tx_desc *desc;
735
736 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 737 tx_index = txq->tx_curr_desc++;
738 if (txq->tx_curr_desc == txq->tx_ring_size)
739 txq->tx_curr_desc = 0;
13d64285
LB		 740 desc = &txq->tx_desc_area[tx_index];
741
742 /*
743 * The last fragment will generate an interrupt
744 * which will free the skb on TX completion.
745 */
746 if (frag == nr_frags - 1) {
747 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
748 ZERO_PADDING | TX_LAST_DESC |
749 TX_ENABLE_INTERRUPT;
13d64285
LB		 750 } else {
751 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 752 }
753
c9df406f 754 desc->l4i_chk = 0;
9e903e08 755 desc->byte_cnt = skb_frag_size(this_frag);
f106358b
IC		 756 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
757 this_frag, 0,
9e903e08 758 skb_frag_size(this_frag),
f106358b 759 DMA_TO_DEVICE);
c9df406f 760 }
1da177e4
LT		 761}
762
c9df406f
LB		 763static inline __be16 sum16_as_be(__sum16 sum)
764{
765 return (__force __be16)sum;
766}
1da177e4 767
4df89bd5 768static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 769{
8fa89bf5 770 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 771 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 772 int tx_index;
cc9754b3 773 struct tx_desc *desc;
c9df406f 774 u32 cmd_sts;
4df89bd5 775 u16 l4i_chk;
c9df406f 776 int length;
1da177e4 777
cc9754b3 778 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 779 l4i_chk = 0;
c9df406f
LB		 780
781 if (skb->ip_summed == CHECKSUM_PARTIAL) {
9b2c2ff7 782 int hdr_len;
4df89bd5 783 int tag_bytes;
e32b6617
LB		 784
785 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
786 skb->protocol != htons(ETH_P_8021Q));
c9df406f 787
9b2c2ff7
SB		 788 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
789 tag_bytes = hdr_len - ETH_HLEN;
790 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
791 unlikely(tag_bytes & ~12)) {
4df89bd5
LB		 792 if (skb_checksum_help(skb) == 0)
793 goto no_csum;
794 kfree_skb(skb);
795 return 1;
796 }
c9df406f 797
4df89bd5 798 if (tag_bytes & 4)
e32b6617 799 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 800 if (tag_bytes & 8)
e32b6617 801 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 802
803 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
804 GEN_IP_V4_CHECKSUM |
805 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 806
c9df406f
LB		 807 switch (ip_hdr(skb)->protocol) {
808 case IPPROTO_UDP:
cc9754b3 809 cmd_sts |= UDP_FRAME;
4df89bd5 810 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 811 break;
812 case IPPROTO_TCP:
4df89bd5 813 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 814 break;
815 default:
816 BUG();
817 }
818 } else {
4df89bd5 819no_csum:
c9df406f 820 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 821 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 822 }
823
66823b92
LB		 824 tx_index = txq->tx_curr_desc++;
825 if (txq->tx_curr_desc == txq->tx_ring_size)
826 txq->tx_curr_desc = 0;
4df89bd5
LB		 827 desc = &txq->tx_desc_area[tx_index];
828
829 if (nr_frags) {
830 txq_submit_frag_skb(txq, skb);
831 length = skb_headlen(skb);
832 } else {
833 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
834 length = skb->len;
835 }
836
837 desc->l4i_chk = l4i_chk;
838 desc->byte_cnt = length;
eb0519b5
GP		 839 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
840 length, DMA_TO_DEVICE);
4df89bd5 841
99ab08e0
LB		 842 __skb_queue_tail(&txq->tx_skb, skb);
843
3b182d7d
RC		 844 skb_tx_timestamp(skb);
845
c9df406f
LB		 846 /* ensure all other descriptors are written before first cmd_sts */
847 wmb();
848 desc->cmd_sts = cmd_sts;
849
1fa38c58
LB		 850 /* clear TX_END status */
851 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 852
c9df406f
LB		 853 /* ensure all descriptors are written before poking hardware */
854 wmb();
13d64285 855 txq_enable(txq);
c9df406f 856
13d64285 857 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 858
859 return 0;
1da177e4 860}
1da177e4 861
0ccfe64d 862static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 863{
e5371493 864 struct mv643xx_eth_private *mp = netdev_priv(dev);
73151ce3 865 int length, queue;
13d64285 866 struct tx_queue *txq;
e5ef1de1 867 struct netdev_queue *nq;
afdb57a2 868
8fd89211
LB		 869 queue = skb_get_queue_mapping(skb);
870 txq = mp->txq + queue;
871 nq = netdev_get_tx_queue(dev, queue);
872
c9df406f 873 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 874 txq->tx_dropped++;
7542db8b
JP		 875 netdev_printk(KERN_DEBUG, dev,
876 "failed to linearize skb with tiny unaligned fragment\n");
c9df406f
LB		 877 return NETDEV_TX_BUSY;
878 }
879
17cd0a59 880 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1 881 if (net_ratelimit())
7542db8b 882 netdev_err(dev, "tx queue full?!\n");
3d6b35bc
LB		 883 kfree_skb(skb);
884 return NETDEV_TX_OK;
c9df406f
LB		 885 }
886
73151ce3
RC		 887 length = skb->len;
888
4df89bd5
LB		 889 if (!txq_submit_skb(txq, skb)) {
890 int entries_left;
891
73151ce3 892 txq->tx_bytes += length;
4df89bd5 893 txq->tx_packets++;
c9df406f 894
4df89bd5
LB		 895 entries_left = txq->tx_ring_size - txq->tx_desc_count;
896 if (entries_left < MAX_SKB_FRAGS + 1)
897 netif_tx_stop_queue(nq);
898 }
c9df406f 899
c9df406f 900 return NETDEV_TX_OK;
1da177e4
LT		 901}
902
c9df406f 903
1fa38c58
LB		 904/* tx napi ******************************************************************/
905static void txq_kick(struct tx_queue *txq)
906{
907 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 908 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 909 u32 hw_desc_ptr;
910 u32 expected_ptr;
911
8fd89211 912 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 913
37a6084f 914 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 915 goto out;
916
37a6084f 917 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 918 expected_ptr = (u32)txq->tx_desc_dma +
919 txq->tx_curr_desc * sizeof(struct tx_desc);
920
921 if (hw_desc_ptr != expected_ptr)
922 txq_enable(txq);
923
924out:
8fd89211 925 __netif_tx_unlock(nq);
1fa38c58
LB		 926
927 mp->work_tx_end &= ~(1 << txq->index);
928}
929
930static int txq_reclaim(struct tx_queue *txq, int budget, int force)
931{
932 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 933 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 934 int reclaimed;
935
8fd89211 936 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 937
938 reclaimed = 0;
939 while (reclaimed < budget && txq->tx_desc_count > 0) {
940 int tx_index;
941 struct tx_desc *desc;
942 u32 cmd_sts;
943 struct sk_buff *skb;
1fa38c58
LB		 944
945 tx_index = txq->tx_used_desc;
946 desc = &txq->tx_desc_area[tx_index];
947 cmd_sts = desc->cmd_sts;
948
949 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
950 if (!force)
951 break;
952 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
953 }
954
955 txq->tx_used_desc = tx_index + 1;
956 if (txq->tx_used_desc == txq->tx_ring_size)
957 txq->tx_used_desc = 0;
958
959 reclaimed++;
960 txq->tx_desc_count--;
961
99ab08e0
LB		 962 skb = NULL;
963 if (cmd_sts & TX_LAST_DESC)
964 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 965
966 if (cmd_sts & ERROR_SUMMARY) {
7542db8b 967 netdev_info(mp->dev, "tx error\n");
1fa38c58
LB		 968 mp->dev->stats.tx_errors++;
969 }
970
a418950c 971 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 972 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 973 desc->byte_cnt, DMA_TO_DEVICE);
974 } else {
eb0519b5 975 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 976 desc->byte_cnt, DMA_TO_DEVICE);
977 }
1fa38c58 978
2bcb4b0f
LB		 979 if (skb != NULL) {
980 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 981 mp->rx_ring_size &&
7fd96ce4 982 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 983 __skb_queue_head(&mp->rx_recycle, skb);
984 else
985 dev_kfree_skb(skb);
986 }
1fa38c58
LB		 987 }
988
8fd89211
LB		 989 __netif_tx_unlock(nq);
990
1fa38c58
LB		 991 if (reclaimed < budget)
992 mp->work_tx &= ~(1 << txq->index);
993
1fa38c58
LB		 994 return reclaimed;
995}
996
997
89df5fdc
LB		 998/* tx rate control **********************************************************/
999/*
1000 * Set total maximum TX rate (shared by all TX queues for this port)
1001 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1002 */
1003static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1004{
1005 int token_rate;
1006 int mtu;
1007 int bucket_size;
1008
1009 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1010 if (token_rate > 1023)
1011 token_rate = 1023;
1012
1013 mtu = (mp->dev->mtu + 255) >> 8;
1014 if (mtu > 63)
1015 mtu = 63;
1016
1017 bucket_size = (burst + 255) >> 8;
1018 if (bucket_size > 65535)
1019 bucket_size = 65535;
1020
457b1d5a
LB		 1021 switch (mp->shared->tx_bw_control) {
1022 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1023 wrlp(mp, TX_BW_RATE, token_rate);
1024 wrlp(mp, TX_BW_MTU, mtu);
1025 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1026 break;
1027 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1028 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1029 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1030 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1031 break;
1e881592 1032 }
89df5fdc
LB		 1033}
1034
1035static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1036{
1037 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1038 int token_rate;
1039 int bucket_size;
1040
1041 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1042 if (token_rate > 1023)
1043 token_rate = 1023;
1044
1045 bucket_size = (burst + 255) >> 8;
1046 if (bucket_size > 65535)
1047 bucket_size = 65535;
1048
37a6084f
LB		 1049 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1050 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1051}
1052
1053static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1054{
1055 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1056 int off;
1057 u32 val;
1058
1059 /*
1060 * Turn on fixed priority mode.
1061 */
457b1d5a
LB		 1062 off = 0;
1063 switch (mp->shared->tx_bw_control) {
1064 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1065 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1066 break;
1067 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1068 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1069 break;
1070 }
89df5fdc 1071
457b1d5a 1072 if (off) {
37a6084f 1073 val = rdlp(mp, off);
457b1d5a 1074 val |= 1 << txq->index;
37a6084f 1075 wrlp(mp, off, val);
457b1d5a 1076 }
89df5fdc
LB		 1077}
1078
89df5fdc 1079
c9df406f 1080/* mii management interface *************************************************/
45c5d3bc
LB		 1081static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1082{
1083 struct mv643xx_eth_shared_private *msp = dev_id;
1084
1085 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1086 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1087 wake_up(&msp->smi_busy_wait);
1088 return IRQ_HANDLED;
1089 }
1090
1091 return IRQ_NONE;
1092}
c9df406f 1093
45c5d3bc 1094static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1095{
45c5d3bc
LB		 1096 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1097}
1da177e4 1098
45c5d3bc
LB		 1099static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1100{
1101 if (msp->err_interrupt == NO_IRQ) {
1102 int i;
c9df406f 1103
45c5d3bc
LB		 1104 for (i = 0; !smi_is_done(msp); i++) {
1105 if (i == 10)
1106 return -ETIMEDOUT;
1107 msleep(10);
c9df406f 1108 }
45c5d3bc
LB		 1109
1110 return 0;
1111 }
1112
ee04448d
LB		 1113 if (!smi_is_done(msp)) {
1114 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1115 msecs_to_jiffies(100));
1116 if (!smi_is_done(msp))
1117 return -ETIMEDOUT;
1118 }
45c5d3bc
LB		 1119
1120 return 0;
1121}
1122
ed94493f 1123static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1124{
ed94493f 1125 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1126 void __iomem *smi_reg = msp->base + SMI_REG;
1127 int ret;
1128
45c5d3bc 1129 if (smi_wait_ready(msp)) {
7542db8b 1130 pr_warn("SMI bus busy timeout\n");
ed94493f 1131 return -ETIMEDOUT;
1da177e4
LT		 1132 }
1133
fc32b0e2 1134 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1135
45c5d3bc 1136 if (smi_wait_ready(msp)) {
7542db8b 1137 pr_warn("SMI bus busy timeout\n");
ed94493f 1138 return -ETIMEDOUT;
45c5d3bc
LB		 1139 }
1140
1141 ret = readl(smi_reg);
1142 if (!(ret & SMI_READ_VALID)) {
7542db8b 1143 pr_warn("SMI bus read not valid\n");
ed94493f 1144 return -ENODEV;
c9df406f
LB		 1145 }
1146
ed94493f 1147 return ret & 0xffff;
1da177e4
LT		 1148}
1149
ed94493f 1150static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1151{
ed94493f 1152 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1153 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1154
45c5d3bc 1155 if (smi_wait_ready(msp)) {
7542db8b 1156 pr_warn("SMI bus busy timeout\n");
45c5d3bc 1157 return -ETIMEDOUT;
1da177e4
LT		 1158 }
1159
fc32b0e2 1160 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1161 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1162
ed94493f 1163 if (smi_wait_ready(msp)) {
7542db8b 1164 pr_warn("SMI bus busy timeout\n");
ed94493f
LB		 1165 return -ETIMEDOUT;
1166 }
45c5d3bc
LB		 1167
1168 return 0;
c9df406f 1169}
1da177e4 1170
c9df406f 1171
8fd89211
LB		 1172/* statistics ***************************************************************/
1173static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1174{
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1176 struct net_device_stats *stats = &dev->stats;
1177 unsigned long tx_packets = 0;
1178 unsigned long tx_bytes = 0;
1179 unsigned long tx_dropped = 0;
1180 int i;
1181
1182 for (i = 0; i < mp->txq_count; i++) {
1183 struct tx_queue *txq = mp->txq + i;
1184
1185 tx_packets += txq->tx_packets;
1186 tx_bytes += txq->tx_bytes;
1187 tx_dropped += txq->tx_dropped;
1188 }
1189
1190 stats->tx_packets = tx_packets;
1191 stats->tx_bytes = tx_bytes;
1192 stats->tx_dropped = tx_dropped;
1193
1194 return stats;
1195}
1196
eaf5d590
LB		 1197static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1198{
1199 u32 lro_aggregated = 0;
1200 u32 lro_flushed = 0;
1201 u32 lro_no_desc = 0;
1202 int i;
1203
eaf5d590
LB		 1204 for (i = 0; i < mp->rxq_count; i++) {
1205 struct rx_queue *rxq = mp->rxq + i;
1206
1207 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1208 lro_flushed += rxq->lro_mgr.stats.flushed;
1209 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1210 }
eaf5d590
LB		 1211
1212 mp->lro_counters.lro_aggregated = lro_aggregated;
1213 mp->lro_counters.lro_flushed = lro_flushed;
1214 mp->lro_counters.lro_no_desc = lro_no_desc;
1215}
1216
fc32b0e2 1217static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1218{
fc32b0e2 1219 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1220}
1221
fc32b0e2 1222static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1223{
fc32b0e2
LB		 1224 int i;
1225
1226 for (i = 0; i < 0x80; i += 4)
1227 mib_read(mp, i);
c9df406f 1228}
d0412d96 1229
fc32b0e2 1230static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1231{
e5371493 1232 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1233
57e8f26a 1234 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1235 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1236 p->bad_octets_received += mib_read(mp, 0x08);
1237 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1238 p->good_frames_received += mib_read(mp, 0x10);
1239 p->bad_frames_received += mib_read(mp, 0x14);
1240 p->broadcast_frames_received += mib_read(mp, 0x18);
1241 p->multicast_frames_received += mib_read(mp, 0x1c);
1242 p->frames_64_octets += mib_read(mp, 0x20);
1243 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1244 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1245 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1246 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1247 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1248 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1249 p->good_frames_sent += mib_read(mp, 0x40);
1250 p->excessive_collision += mib_read(mp, 0x44);
1251 p->multicast_frames_sent += mib_read(mp, 0x48);
1252 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1253 p->unrec_mac_control_received += mib_read(mp, 0x50);
1254 p->fc_sent += mib_read(mp, 0x54);
1255 p->good_fc_received += mib_read(mp, 0x58);
1256 p->bad_fc_received += mib_read(mp, 0x5c);
1257 p->undersize_received += mib_read(mp, 0x60);
1258 p->fragments_received += mib_read(mp, 0x64);
1259 p->oversize_received += mib_read(mp, 0x68);
1260 p->jabber_received += mib_read(mp, 0x6c);
1261 p->mac_receive_error += mib_read(mp, 0x70);
1262 p->bad_crc_event += mib_read(mp, 0x74);
1263 p->collision += mib_read(mp, 0x78);
1264 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1265 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1266
1267 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1268}
1269
1270static void mib_counters_timer_wrapper(unsigned long _mp)
1271{
1272 struct mv643xx_eth_private *mp = (void *)_mp;
1273
1274 mib_counters_update(mp);
d0412d96
JC		 1275}
1276
c9df406f 1277
3e508034
LB		 1278/* interrupt coalescing *****************************************************/
1279/*
1280 * Hardware coalescing parameters are set in units of 64 t_clk
1281 * cycles. I.e.:
1282 *
1283 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1284 *
1285 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1286 *
1287 * In the ->set*() methods, we round the computed register value
1288 * to the nearest integer.
1289 */
1290static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1291{
1292 u32 val = rdlp(mp, SDMA_CONFIG);
1293 u64 temp;
1294
1295 if (mp->shared->extended_rx_coal_limit)
1296 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1297 else
1298 temp = (val & 0x003fff00) >> 8;
1299
1300 temp *= 64000000;
1301 do_div(temp, mp->shared->t_clk);
1302
1303 return (unsigned int)temp;
1304}
1305
1306static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1307{
1308 u64 temp;
1309 u32 val;
1310
1311 temp = (u64)usec * mp->shared->t_clk;
1312 temp += 31999999;
1313 do_div(temp, 64000000);
1314
1315 val = rdlp(mp, SDMA_CONFIG);
1316 if (mp->shared->extended_rx_coal_limit) {
1317 if (temp > 0xffff)
1318 temp = 0xffff;
1319 val &= ~0x023fff80;
1320 val |= (temp & 0x8000) << 10;
1321 val |= (temp & 0x7fff) << 7;
1322 } else {
1323 if (temp > 0x3fff)
1324 temp = 0x3fff;
1325 val &= ~0x003fff00;
1326 val |= (temp & 0x3fff) << 8;
1327 }
1328 wrlp(mp, SDMA_CONFIG, val);
1329}
1330
1331static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1332{
1333 u64 temp;
1334
1335 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1336 temp *= 64000000;
1337 do_div(temp, mp->shared->t_clk);
1338
1339 return (unsigned int)temp;
1340}
1341
1342static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1343{
1344 u64 temp;
1345
1346 temp = (u64)usec * mp->shared->t_clk;
1347 temp += 31999999;
1348 do_div(temp, 64000000);
1349
1350 if (temp > 0x3fff)
1351 temp = 0x3fff;
1352
1353 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1354}
1355
1356
c9df406f 1357/* ethtool ******************************************************************/
e5371493 1358struct mv643xx_eth_stats {
c9df406f
LB		 1359 char stat_string[ETH_GSTRING_LEN];
1360 int sizeof_stat;
16820054
LB		 1361 int netdev_off;
1362 int mp_off;
c9df406f
LB		 1363};
1364
16820054
LB		 1365#define SSTAT(m) \
1366 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1367 offsetof(struct net_device, stats.m), -1 }
1368
1369#define MIBSTAT(m) \
1370 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1371 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1372
eaf5d590
LB		 1373#define LROSTAT(m) \
1374 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1375 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1376
16820054
LB		 1377static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1378 SSTAT(rx_packets),
1379 SSTAT(tx_packets),
1380 SSTAT(rx_bytes),
1381 SSTAT(tx_bytes),
1382 SSTAT(rx_errors),
1383 SSTAT(tx_errors),
1384 SSTAT(rx_dropped),
1385 SSTAT(tx_dropped),
1386 MIBSTAT(good_octets_received),
1387 MIBSTAT(bad_octets_received),
1388 MIBSTAT(internal_mac_transmit_err),
1389 MIBSTAT(good_frames_received),
1390 MIBSTAT(bad_frames_received),
1391 MIBSTAT(broadcast_frames_received),
1392 MIBSTAT(multicast_frames_received),
1393 MIBSTAT(frames_64_octets),
1394 MIBSTAT(frames_65_to_127_octets),
1395 MIBSTAT(frames_128_to_255_octets),
1396 MIBSTAT(frames_256_to_511_octets),
1397 MIBSTAT(frames_512_to_1023_octets),
1398 MIBSTAT(frames_1024_to_max_octets),
1399 MIBSTAT(good_octets_sent),
1400 MIBSTAT(good_frames_sent),
1401 MIBSTAT(excessive_collision),
1402 MIBSTAT(multicast_frames_sent),
1403 MIBSTAT(broadcast_frames_sent),
1404 MIBSTAT(unrec_mac_control_received),
1405 MIBSTAT(fc_sent),
1406 MIBSTAT(good_fc_received),
1407 MIBSTAT(bad_fc_received),
1408 MIBSTAT(undersize_received),
1409 MIBSTAT(fragments_received),
1410 MIBSTAT(oversize_received),
1411 MIBSTAT(jabber_received),
1412 MIBSTAT(mac_receive_error),
1413 MIBSTAT(bad_crc_event),
1414 MIBSTAT(collision),
1415 MIBSTAT(late_collision),
eaf5d590
LB		 1416 LROSTAT(lro_aggregated),
1417 LROSTAT(lro_flushed),
1418 LROSTAT(lro_no_desc),
c9df406f
LB		 1419};
1420
10a9948d 1421static int
6bdf576e
LB		 1422mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1423 struct ethtool_cmd *cmd)
d0412d96 1424{
d0412d96
JC		 1425 int err;
1426
ed94493f
LB		 1427 err = phy_read_status(mp->phy);
1428 if (err == 0)
1429 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1430
fc32b0e2
LB		 1431 /*
1432 * The MAC does not support 1000baseT_Half.
1433 */
d0412d96
JC		 1434 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1435 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1436
1437 return err;
1438}
1439
10a9948d 1440static int
6bdf576e 1441mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1442 struct ethtool_cmd *cmd)
bedfe324 1443{
81600eea
LB		 1444 u32 port_status;
1445
37a6084f 1446 port_status = rdlp(mp, PORT_STATUS);
81600eea 1447
bedfe324
LB		 1448 cmd->supported = SUPPORTED_MII;
1449 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1450 switch (port_status & PORT_SPEED_MASK) {
1451 case PORT_SPEED_10:
70739497 1452 ethtool_cmd_speed_set(cmd, SPEED_10);
81600eea
LB		 1453 break;
1454 case PORT_SPEED_100:
70739497 1455 ethtool_cmd_speed_set(cmd, SPEED_100);
81600eea
LB		 1456 break;
1457 case PORT_SPEED_1000:
70739497 1458 ethtool_cmd_speed_set(cmd, SPEED_1000);
81600eea
LB		 1459 break;
1460 default:
1461 cmd->speed = -1;
1462 break;
1463 }
1464 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1465 cmd->port = PORT_MII;
1466 cmd->phy_address = 0;
1467 cmd->transceiver = XCVR_INTERNAL;
1468 cmd->autoneg = AUTONEG_DISABLE;
1469 cmd->maxtxpkt = 1;
1470 cmd->maxrxpkt = 1;
1471
1472 return 0;
1473}
1474
6bdf576e
LB		 1475static int
1476mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1477{
1478 struct mv643xx_eth_private *mp = netdev_priv(dev);
1479
1480 if (mp->phy != NULL)
1481 return mv643xx_eth_get_settings_phy(mp, cmd);
1482 else
1483 return mv643xx_eth_get_settings_phyless(mp, cmd);
1484}
1485
10a9948d
LB		 1486static int
1487mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1488{
e5371493 1489 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1490
6bdf576e
LB		 1491 if (mp->phy == NULL)
1492 return -EINVAL;
1493
fc32b0e2
LB		 1494 /*
1495 * The MAC does not support 1000baseT_Half.
1496 */
1497 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1498
ed94493f 1499 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1500}
1da177e4 1501
fc32b0e2
LB		 1502static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1503 struct ethtool_drvinfo *drvinfo)
c9df406f 1504{
e5371493
LB		 1505 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1506 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1507 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1508 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1509 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1510}
1da177e4 1511
fc32b0e2 1512static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1513{
e5371493 1514 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1515
6bdf576e
LB		 1516 if (mp->phy == NULL)
1517 return -EINVAL;
1da177e4 1518
6bdf576e 1519 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1520}
1521
3e508034
LB		 1522static int
1523mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1524{
1525 struct mv643xx_eth_private *mp = netdev_priv(dev);
1526
1527 ec->rx_coalesce_usecs = get_rx_coal(mp);
1528 ec->tx_coalesce_usecs = get_tx_coal(mp);
1529
1530 return 0;
1531}
1532
1533static int
1534mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1535{
1536 struct mv643xx_eth_private *mp = netdev_priv(dev);
1537
1538 set_rx_coal(mp, ec->rx_coalesce_usecs);
1539 set_tx_coal(mp, ec->tx_coalesce_usecs);
1540
1541 return 0;
1542}
1543
e7d2f4db
LB		 1544static void
1545mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1546{
1547 struct mv643xx_eth_private *mp = netdev_priv(dev);
1548
1549 er->rx_max_pending = 4096;
1550 er->tx_max_pending = 4096;
e7d2f4db
LB		 1551
1552 er->rx_pending = mp->rx_ring_size;
1553 er->tx_pending = mp->tx_ring_size;
e7d2f4db
LB		 1554}
1555
1556static int
1557mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1558{
1559 struct mv643xx_eth_private *mp = netdev_priv(dev);
1560
1561 if (er->rx_mini_pending || er->rx_jumbo_pending)
1562 return -EINVAL;
1563
1564 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1565 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1566
1567 if (netif_running(dev)) {
1568 mv643xx_eth_stop(dev);
1569 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 1570 netdev_err(dev,
1571 "fatal error on re-opening device after ring param change\n");
e7d2f4db
LB		 1572 return -ENOMEM;
1573 }
1574 }
1575
1576 return 0;
1577}
1578
d888b373
LB		 1579
1580static int
aad59c43 1581mv643xx_eth_set_features(struct net_device *dev, u32 features)
d888b373
LB		 1582{
1583 struct mv643xx_eth_private *mp = netdev_priv(dev);
aad59c43 1584 u32 rx_csum = features & NETIF_F_RXCSUM;
d888b373
LB		 1585
1586 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1587
1588 return 0;
1589}
1590
fc32b0e2
LB		 1591static void mv643xx_eth_get_strings(struct net_device *dev,
1592 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1593{
1594 int i;
1da177e4 1595
fc32b0e2
LB		 1596 if (stringset == ETH_SS_STATS) {
1597 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1598 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1599 mv643xx_eth_stats[i].stat_string,
e5371493 1600 ETH_GSTRING_LEN);
c9df406f 1601 }
c9df406f
LB		 1602 }
1603}
1da177e4 1604
fc32b0e2
LB		 1605static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1606 struct ethtool_stats *stats,
1607 uint64_t *data)
c9df406f 1608{
b9873841 1609 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1610 int i;
1da177e4 1611
8fd89211 1612 mv643xx_eth_get_stats(dev);
fc32b0e2 1613 mib_counters_update(mp);
eaf5d590 1614 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1615
16820054
LB		 1616 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1617 const struct mv643xx_eth_stats *stat;
1618 void *p;
1619
1620 stat = mv643xx_eth_stats + i;
1621
1622 if (stat->netdev_off >= 0)
1623 p = ((void *)mp->dev) + stat->netdev_off;
1624 else
1625 p = ((void *)mp) + stat->mp_off;
1626
1627 data[i] = (stat->sizeof_stat == 8) ?
1628 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1629 }
c9df406f 1630}
1da177e4 1631
fc32b0e2 1632static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1633{
fc32b0e2 1634 if (sset == ETH_SS_STATS)
16820054 1635 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1636
1637 return -EOPNOTSUPP;
c9df406f 1638}
1da177e4 1639
e5371493 1640static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1641 .get_settings = mv643xx_eth_get_settings,
1642 .set_settings = mv643xx_eth_set_settings,
1643 .get_drvinfo = mv643xx_eth_get_drvinfo,
1644 .nway_reset = mv643xx_eth_nway_reset,
ed4ba4b5 1645 .get_link = ethtool_op_get_link,
3e508034
LB		 1646 .get_coalesce = mv643xx_eth_get_coalesce,
1647 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1648 .get_ringparam = mv643xx_eth_get_ringparam,
1649 .set_ringparam = mv643xx_eth_set_ringparam,
fc32b0e2
LB		 1650 .get_strings = mv643xx_eth_get_strings,
1651 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1652 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1653};
1da177e4 1654
bea3348e 1655
c9df406f 1656/* address handling *********************************************************/
5daffe94 1657static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1658{
66e63ffb
LB		 1659 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1660 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1661
5daffe94
LB		 1662 addr[0] = (mac_h >> 24) & 0xff;
1663 addr[1] = (mac_h >> 16) & 0xff;
1664 addr[2] = (mac_h >> 8) & 0xff;
1665 addr[3] = mac_h & 0xff;
1666 addr[4] = (mac_l >> 8) & 0xff;
1667 addr[5] = mac_l & 0xff;
c9df406f 1668}
1da177e4 1669
66e63ffb 1670static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1671{
66e63ffb
LB		 1672 wrlp(mp, MAC_ADDR_HIGH,
1673 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1674 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1675}
d0412d96 1676
66e63ffb 1677static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1678{
ccffad25 1679 struct netdev_hw_addr *ha;
66e63ffb 1680 u32 nibbles;
1da177e4 1681
66e63ffb
LB		 1682 if (dev->flags & IFF_PROMISC)
1683 return 0;
1da177e4 1684
66e63ffb 1685 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1686 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1687 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1688 return 0;
ccffad25 1689 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1690 return 0;
ff561eef 1691
ccffad25 1692 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1693 }
1da177e4 1694
66e63ffb 1695 return nibbles;
1da177e4
LT		 1696}
1697
66e63ffb 1698static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1699{
e5371493 1700 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1701 u32 port_config;
1702 u32 nibbles;
1703 int i;
1da177e4 1704
cc9754b3 1705 uc_addr_set(mp, dev->dev_addr);
1da177e4 1706
6877f54e
PS		 1707 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1708
66e63ffb
LB		 1709 nibbles = uc_addr_filter_mask(dev);
1710 if (!nibbles) {
1711 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1712 nibbles = 0xffff;
66e63ffb
LB		 1713 }
1714
1715 for (i = 0; i < 16; i += 4) {
1716 int off = UNICAST_TABLE(mp->port_num) + i;
1717 u32 v;
1718
1719 v = 0;
1720 if (nibbles & 1)
1721 v |= 0x00000001;
1722 if (nibbles & 2)
1723 v |= 0x00000100;
1724 if (nibbles & 4)
1725 v |= 0x00010000;
1726 if (nibbles & 8)
1727 v |= 0x01000000;
1728 nibbles >>= 4;
1729
1730 wrl(mp, off, v);
1731 }
1732
66e63ffb 1733 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1734}
1735
69876569
LB		 1736static int addr_crc(unsigned char *addr)
1737{
1738 int crc = 0;
1739 int i;
1740
1741 for (i = 0; i < 6; i++) {
1742 int j;
1743
1744 crc = (crc ^ addr[i]) << 8;
1745 for (j = 7; j >= 0; j--) {
1746 if (crc & (0x100 << j))
1747 crc ^= 0x107 << j;
1748 }
1749 }
1750
1751 return crc;
1752}
1753
66e63ffb 1754static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1755{
fc32b0e2 1756 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1757 u32 *mc_spec;
1758 u32 *mc_other;
22bedad3 1759 struct netdev_hw_addr *ha;
fc32b0e2 1760 int i;
c8aaea25 1761
fc32b0e2 1762 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1763 int port_num;
1764 u32 accept;
c8aaea25 1765
66e63ffb
LB		 1766oom:
1767 port_num = mp->port_num;
1768 accept = 0x01010101;
fc32b0e2
LB		 1769 for (i = 0; i < 0x100; i += 4) {
1770 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1771 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1772 }
1773 return;
1774 }
c8aaea25 1775
82a5bd6a 1776 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1777 if (mc_spec == NULL)
1778 goto oom;
1779 mc_other = mc_spec + (0x100 >> 2);
1780
1781 memset(mc_spec, 0, 0x100);
1782 memset(mc_other, 0, 0x100);
1da177e4 1783
22bedad3
JP		 1784 netdev_for_each_mc_addr(ha, dev) {
1785 u8 *a = ha->addr;
66e63ffb
LB		 1786 u32 *table;
1787 int entry;
1da177e4 1788
fc32b0e2 1789 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1790 table = mc_spec;
1791 entry = a[5];
fc32b0e2 1792 } else {
66e63ffb
LB		 1793 table = mc_other;
1794 entry = addr_crc(a);
fc32b0e2 1795 }
66e63ffb 1796
2b448334 1797 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1798 }
66e63ffb
LB		 1799
1800 for (i = 0; i < 0x100; i += 4) {
1801 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1802 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1803 }
1804
1805 kfree(mc_spec);
1806}
1807
1808static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1809{
1810 mv643xx_eth_program_unicast_filter(dev);
1811 mv643xx_eth_program_multicast_filter(dev);
1812}
1813
1814static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1815{
1816 struct sockaddr *sa = addr;
1817
a29ec08a
DK		 1818 if (!is_valid_ether_addr(sa->sa_data))
1819 return -EINVAL;
1820
66e63ffb
LB		 1821 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1822
1823 netif_addr_lock_bh(dev);
1824 mv643xx_eth_program_unicast_filter(dev);
1825 netif_addr_unlock_bh(dev);
1826
1827 return 0;
c9df406f 1828}
c8aaea25 1829
c8aaea25 1830
c9df406f 1831/* rx/tx queue initialisation ***********************************************/
64da80a2 1832static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1833{
64da80a2 1834 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1835 struct rx_desc *rx_desc;
1836 int size;
c9df406f
LB		 1837 int i;
1838
64da80a2
LB		 1839 rxq->index = index;
1840
e7d2f4db 1841 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1842
1843 rxq->rx_desc_count = 0;
1844 rxq->rx_curr_desc = 0;
1845 rxq->rx_used_desc = 0;
1846
1847 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1848
f7981c1c 1849 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1850 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1851 mp->rx_desc_sram_size);
1852 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1853 } else {
eb0519b5
GP		 1854 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1855 size, &rxq->rx_desc_dma,
1856 GFP_KERNEL);
f7ea3337
PJ		 1857 }
1858
8a578111 1859 if (rxq->rx_desc_area == NULL) {
7542db8b 1860 netdev_err(mp->dev,
8a578111
LB		 1861 "can't allocate rx ring (%d bytes)\n", size);
1862 goto out;
1863 }
1864 memset(rxq->rx_desc_area, 0, size);
1da177e4 1865
8a578111
LB		 1866 rxq->rx_desc_area_size = size;
1867 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1868 GFP_KERNEL);
1869 if (rxq->rx_skb == NULL) {
7542db8b 1870 netdev_err(mp->dev, "can't allocate rx skb ring\n");
8a578111
LB		 1871 goto out_free;
1872 }
1873
1874 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1875 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1876 int nexti;
1877
1878 nexti = i + 1;
1879 if (nexti == rxq->rx_ring_size)
1880 nexti = 0;
1881
8a578111
LB		 1882 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1883 nexti * sizeof(struct rx_desc);
1884 }
1885
eaf5d590
LB		 1886 rxq->lro_mgr.dev = mp->dev;
1887 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1888 rxq->lro_mgr.features = LRO_F_NAPI;
1889 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1890 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1891 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1892 rxq->lro_mgr.max_aggr = 32;
1893 rxq->lro_mgr.frag_align_pad = 0;
1894 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1895 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1896
1897 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1898
8a578111
LB		 1899 return 0;
1900
1901
1902out_free:
f7981c1c 1903 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1904 iounmap(rxq->rx_desc_area);
1905 else
eb0519b5 1906 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1907 rxq->rx_desc_area,
1908 rxq->rx_desc_dma);
1909
1910out:
1911 return -ENOMEM;
c9df406f 1912}
c8aaea25 1913
8a578111 1914static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1915{
8a578111
LB		 1916 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1917 int i;
1918
1919 rxq_disable(rxq);
c8aaea25 1920
8a578111
LB		 1921 for (i = 0; i < rxq->rx_ring_size; i++) {
1922 if (rxq->rx_skb[i]) {
1923 dev_kfree_skb(rxq->rx_skb[i]);
1924 rxq->rx_desc_count--;
1da177e4 1925 }
c8aaea25 1926 }
1da177e4 1927
8a578111 1928 if (rxq->rx_desc_count) {
7542db8b 1929 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
8a578111
LB		 1930 rxq->rx_desc_count);
1931 }
1932
f7981c1c 1933 if (rxq->index == 0 &&
64da80a2 1934 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1935 iounmap(rxq->rx_desc_area);
c9df406f 1936 else
eb0519b5 1937 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1938 rxq->rx_desc_area, rxq->rx_desc_dma);
1939
1940 kfree(rxq->rx_skb);
c9df406f 1941}
1da177e4 1942
3d6b35bc 1943static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1944{
3d6b35bc 1945 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1946 struct tx_desc *tx_desc;
1947 int size;
c9df406f 1948 int i;
1da177e4 1949
3d6b35bc
LB		 1950 txq->index = index;
1951
e7d2f4db 1952 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1953
1954 txq->tx_desc_count = 0;
1955 txq->tx_curr_desc = 0;
1956 txq->tx_used_desc = 0;
1957
1958 size = txq->tx_ring_size * sizeof(struct tx_desc);
1959
f7981c1c 1960 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1961 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1962 mp->tx_desc_sram_size);
1963 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1964 } else {
eb0519b5
GP		 1965 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1966 size, &txq->tx_desc_dma,
1967 GFP_KERNEL);
13d64285
LB		 1968 }
1969
1970 if (txq->tx_desc_area == NULL) {
7542db8b 1971 netdev_err(mp->dev,
13d64285 1972 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1973 return -ENOMEM;
c9df406f 1974 }
13d64285
LB		 1975 memset(txq->tx_desc_area, 0, size);
1976
1977 txq->tx_desc_area_size = size;
13d64285
LB		 1978
1979 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1980 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1981 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1982 int nexti;
1983
1984 nexti = i + 1;
1985 if (nexti == txq->tx_ring_size)
1986 nexti = 0;
6b368f68
LB		 1987
1988 txd->cmd_sts = 0;
1989 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1990 nexti * sizeof(struct tx_desc);
1991 }
1992
99ab08e0 1993 skb_queue_head_init(&txq->tx_skb);
c9df406f 1994
99ab08e0 1995 return 0;
c8aaea25 1996}
1da177e4 1997
13d64285 1998static void txq_deinit(struct tx_queue *txq)
c9df406f 1999{
13d64285 2000 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2001
13d64285 2002 txq_disable(txq);
1fa38c58 2003 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2004
13d64285 2005 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2006
f7981c1c 2007 if (txq->index == 0 &&
3d6b35bc 2008 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2009 iounmap(txq->tx_desc_area);
c9df406f 2010 else
eb0519b5 2011 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2012 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2013}
1da177e4 2014
1da177e4 2015
c9df406f 2016/* netdev ops and related ***************************************************/
1fa38c58
LB		 2017static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2018{
2019 u32 int_cause;
2020 u32 int_cause_ext;
2021
e0ca8410 2022 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2023 if (int_cause == 0)
2024 return 0;
2025
2026 int_cause_ext = 0;
e0ca8410
SB		 2027 if (int_cause & INT_EXT) {
2028 int_cause &= ~INT_EXT;
37a6084f 2029 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2030 }
1fa38c58 2031
1fa38c58 2032 if (int_cause) {
37a6084f 2033 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2034 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2035 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2036 mp->work_rx |= (int_cause & INT_RX) >> 2;
2037 }
2038
2039 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2040 if (int_cause_ext) {
37a6084f 2041 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2042 if (int_cause_ext & INT_EXT_LINK_PHY)
2043 mp->work_link = 1;
2044 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2045 }
2046
2047 return 1;
2048}
2049
2050static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2051{
2052 struct net_device *dev = (struct net_device *)dev_id;
2053 struct mv643xx_eth_private *mp = netdev_priv(dev);
2054
2055 if (unlikely(!mv643xx_eth_collect_events(mp)))
2056 return IRQ_NONE;
2057
37a6084f 2058 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2059 napi_schedule(&mp->napi);
2060
2061 return IRQ_HANDLED;
2062}
2063
2f7eb47a
LB		 2064static void handle_link_event(struct mv643xx_eth_private *mp)
2065{
2066 struct net_device *dev = mp->dev;
2067 u32 port_status;
2068 int speed;
2069 int duplex;
2070 int fc;
2071
37a6084f 2072 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2073 if (!(port_status & LINK_UP)) {
2074 if (netif_carrier_ok(dev)) {
2075 int i;
2076
7542db8b 2077 netdev_info(dev, "link down\n");
2f7eb47a
LB		 2078
2079 netif_carrier_off(dev);
2f7eb47a 2080
f7981c1c 2081 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2082 struct tx_queue *txq = mp->txq + i;
2083
1fa38c58 2084 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2085 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2086 }
2087 }
2088 return;
2089 }
2090
2091 switch (port_status & PORT_SPEED_MASK) {
2092 case PORT_SPEED_10:
2093 speed = 10;
2094 break;
2095 case PORT_SPEED_100:
2096 speed = 100;
2097 break;
2098 case PORT_SPEED_1000:
2099 speed = 1000;
2100 break;
2101 default:
2102 speed = -1;
2103 break;
2104 }
2105 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2106 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2107
7542db8b
JP		 2108 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2109 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2f7eb47a 2110
4fdeca3f 2111 if (!netif_carrier_ok(dev))
2f7eb47a 2112 netif_carrier_on(dev);
2f7eb47a
LB		 2113}
2114
1fa38c58 2115static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2116{
1fa38c58
LB		 2117 struct mv643xx_eth_private *mp;
2118 int work_done;
ce4e2e45 2119
1fa38c58 2120 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2121
1319ebad
LB		 2122 if (unlikely(mp->oom)) {
2123 mp->oom = 0;
2124 del_timer(&mp->rx_oom);
2125 }
1da177e4 2126
1fa38c58
LB		 2127 work_done = 0;
2128 while (work_done < budget) {
2129 u8 queue_mask;
2130 int queue;
2131 int work_tbd;
2132
2133 if (mp->work_link) {
2134 mp->work_link = 0;
2135 handle_link_event(mp);
26ef1f17 2136 work_done++;
1fa38c58
LB		 2137 continue;
2138 }
1da177e4 2139
1319ebad
LB		 2140 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2141 if (likely(!mp->oom))
2142 queue_mask |= mp->work_rx_refill;
2143
1fa38c58
LB		 2144 if (!queue_mask) {
2145 if (mv643xx_eth_collect_events(mp))
2146 continue;
2147 break;
2148 }
1da177e4 2149
1fa38c58
LB		 2150 queue = fls(queue_mask) - 1;
2151 queue_mask = 1 << queue;
2152
2153 work_tbd = budget - work_done;
2154 if (work_tbd > 16)
2155 work_tbd = 16;
2156
2157 if (mp->work_tx_end & queue_mask) {
2158 txq_kick(mp->txq + queue);
2159 } else if (mp->work_tx & queue_mask) {
2160 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2161 txq_maybe_wake(mp->txq + queue);
2162 } else if (mp->work_rx & queue_mask) {
2163 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2164 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2165 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2166 } else {
2167 BUG();
2168 }
84dd619e 2169 }
fc32b0e2 2170
1fa38c58 2171 if (work_done < budget) {
1319ebad 2172 if (mp->oom)
1fa38c58
LB		 2173 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2174 napi_complete(napi);
e0ca8410 2175 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2176 }
3d6b35bc 2177
1fa38c58
LB		 2178 return work_done;
2179}
8fa89bf5 2180
1fa38c58
LB		 2181static inline void oom_timer_wrapper(unsigned long data)
2182{
2183 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2184
1fa38c58 2185 napi_schedule(&mp->napi);
1da177e4
LT		 2186}
2187
e5371493 2188static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2189{
45c5d3bc
LB		 2190 int data;
2191
ed94493f 2192 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2193 if (data < 0)
2194 return;
1da177e4 2195
7f106c1d 2196 data |= BMCR_RESET;
ed94493f 2197 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2198 return;
1da177e4 2199
c9df406f 2200 do {
ed94493f 2201 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2202 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2203}
2204
fc32b0e2 2205static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2206{
d0412d96 2207 u32 pscr;
8a578111 2208 int i;
1da177e4 2209
bedfe324
LB		 2210 /*
2211 * Perform PHY reset, if there is a PHY.
2212 */
ed94493f 2213 if (mp->phy != NULL) {
bedfe324
LB		 2214 struct ethtool_cmd cmd;
2215
2216 mv643xx_eth_get_settings(mp->dev, &cmd);
2217 phy_reset(mp);
2218 mv643xx_eth_set_settings(mp->dev, &cmd);
2219 }
1da177e4 2220
81600eea
LB		 2221 /*
2222 * Configure basic link parameters.
2223 */
37a6084f 2224 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2225
2226 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2227 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2228
2229 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2230 if (mp->phy == NULL)
81600eea 2231 pscr |= FORCE_LINK_PASS;
37a6084f 2232 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2233
13d64285
LB		 2234 /*
2235 * Configure TX path and queues.
2236 */
89df5fdc 2237 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2238 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2239 struct tx_queue *txq = mp->txq + i;
13d64285 2240
6b368f68 2241 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2242 txq_set_rate(txq, 1000000000, 16777216);
2243 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2244 }
2245
d9a073ea
LB		 2246 /*
2247 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2248 * frames to RX queue #0, and include the pseudo-header when
2249 * calculating receive checksums.
d9a073ea 2250 */
e138f96b 2251 mv643xx_eth_set_features(mp->dev, mp->dev->features);
01999873 2252
376489a2
LB		 2253 /*
2254 * Treat BPDUs as normal multicasts, and disable partition mode.
2255 */
37a6084f 2256 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2257
5a893922
LB		 2258 /*
2259 * Add configured unicast addresses to address filter table.
2260 */
2261 mv643xx_eth_program_unicast_filter(mp->dev);
2262
8a578111 2263 /*
64da80a2 2264 * Enable the receive queues.
8a578111 2265 */
f7981c1c 2266 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2267 struct rx_queue *rxq = mp->rxq + i;
8a578111 2268 u32 addr;
1da177e4 2269
8a578111
LB		 2270 addr = (u32)rxq->rx_desc_dma;
2271 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2272 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2273
8a578111
LB		 2274 rxq_enable(rxq);
2275 }
1da177e4
LT		 2276}
2277
2bcb4b0f
LB		 2278static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2279{
2280 int skb_size;
2281
2282 /*
2283 * Reserve 2+14 bytes for an ethernet header (the hardware
2284 * automatically prepends 2 bytes of dummy data to each
2285 * received packet), 16 bytes for up to four VLAN tags, and
2286 * 4 bytes for the trailing FCS -- 36 bytes total.
2287 */
2288 skb_size = mp->dev->mtu + 36;
2289
2290 /*
2291 * Make sure that the skb size is a multiple of 8 bytes, as
2292 * the lower three bits of the receive descriptor's buffer
2293 * size field are ignored by the hardware.
2294 */
2295 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2296
2297 /*
2298 * If NET_SKB_PAD is smaller than a cache line,
2299 * netdev_alloc_skb() will cause skb->data to be misaligned
2300 * to a cache line boundary. If this is the case, include
2301 * some extra space to allow re-aligning the data area.
2302 */
2303 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2304}
2305
c9df406f 2306static int mv643xx_eth_open(struct net_device *dev)
16e03018 2307{
e5371493 2308 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2309 int err;
64da80a2 2310 int i;
16e03018 2311
37a6084f
LB		 2312 wrlp(mp, INT_CAUSE, 0);
2313 wrlp(mp, INT_CAUSE_EXT, 0);
2314 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2315
fc32b0e2 2316 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2317 IRQF_SHARED, dev->name, dev);
c9df406f 2318 if (err) {
7542db8b 2319 netdev_err(dev, "can't assign irq\n");
c9df406f 2320 return -EAGAIN;
16e03018
DF		 2321 }
2322
2bcb4b0f
LB		 2323 mv643xx_eth_recalc_skb_size(mp);
2324
2257e05c
LB		 2325 napi_enable(&mp->napi);
2326
2bcb4b0f
LB		 2327 skb_queue_head_init(&mp->rx_recycle);
2328
e0ca8410
SB		 2329 mp->int_mask = INT_EXT;
2330
f7981c1c 2331 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2332 err = rxq_init(mp, i);
2333 if (err) {
2334 while (--i >= 0)
f7981c1c 2335 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2336 goto out;
2337 }
2338
1fa38c58 2339 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2340 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2341 }
2342
1319ebad 2343 if (mp->oom) {
2257e05c
LB		 2344 mp->rx_oom.expires = jiffies + (HZ / 10);
2345 add_timer(&mp->rx_oom);
64da80a2 2346 }
8a578111 2347
f7981c1c 2348 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2349 err = txq_init(mp, i);
2350 if (err) {
2351 while (--i >= 0)
f7981c1c 2352 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2353 goto out_free;
2354 }
e0ca8410 2355 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2356 }
16e03018 2357
fc32b0e2 2358 port_start(mp);
16e03018 2359
37a6084f 2360 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2361 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2362
c9df406f
LB		 2363 return 0;
2364
13d64285 2365
fc32b0e2 2366out_free:
f7981c1c
LB		 2367 for (i = 0; i < mp->rxq_count; i++)
2368 rxq_deinit(mp->rxq + i);
fc32b0e2 2369out:
c9df406f
LB		 2370 free_irq(dev->irq, dev);
2371
2372 return err;
16e03018
DF		 2373}
2374
e5371493 2375static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2376{
fc32b0e2 2377 unsigned int data;
64da80a2 2378 int i;
1da177e4 2379
f7981c1c
LB		 2380 for (i = 0; i < mp->rxq_count; i++)
2381 rxq_disable(mp->rxq + i);
2382 for (i = 0; i < mp->txq_count; i++)
2383 txq_disable(mp->txq + i);
ae9ae064
LB		 2384
2385 while (1) {
37a6084f 2386 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2387
2388 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2389 break;
13d64285 2390 udelay(10);
ae9ae064 2391 }
1da177e4 2392
c9df406f 2393 /* Reset the Enable bit in the Configuration Register */
37a6084f 2394 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2395 data &= ~(SERIAL_PORT_ENABLE |
2396 DO_NOT_FORCE_LINK_FAIL |
2397 FORCE_LINK_PASS);
37a6084f 2398 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2399}
2400
c9df406f 2401static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2402{
e5371493 2403 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2404 int i;
1da177e4 2405
fe65e704 2406 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2407 wrlp(mp, INT_MASK, 0x00000000);
2408 rdlp(mp, INT_MASK);
1da177e4 2409
c9df406f 2410 napi_disable(&mp->napi);
78fff83b 2411
2257e05c
LB		 2412 del_timer_sync(&mp->rx_oom);
2413
c9df406f 2414 netif_carrier_off(dev);
1da177e4 2415
fc32b0e2
LB		 2416 free_irq(dev->irq, dev);
2417
cc9754b3 2418 port_reset(mp);
8fd89211 2419 mv643xx_eth_get_stats(dev);
fc32b0e2 2420 mib_counters_update(mp);
57e8f26a 2421 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2422
2bcb4b0f
LB		 2423 skb_queue_purge(&mp->rx_recycle);
2424
f7981c1c
LB		 2425 for (i = 0; i < mp->rxq_count; i++)
2426 rxq_deinit(mp->rxq + i);
2427 for (i = 0; i < mp->txq_count; i++)
2428 txq_deinit(mp->txq + i);
1da177e4 2429
c9df406f 2430 return 0;
1da177e4
LT		 2431}
2432
fc32b0e2 2433static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2434{
e5371493 2435 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2436
ed94493f 2437 if (mp->phy != NULL)
28b04113 2438 return phy_mii_ioctl(mp->phy, ifr, cmd);
bedfe324
LB		 2439
2440 return -EOPNOTSUPP;
1da177e4
LT		 2441}
2442
c9df406f 2443static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2444{
89df5fdc
LB		 2445 struct mv643xx_eth_private *mp = netdev_priv(dev);
2446
fc32b0e2 2447 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2448 return -EINVAL;
1da177e4 2449
c9df406f 2450 dev->mtu = new_mtu;
2bcb4b0f 2451 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2452 tx_set_rate(mp, 1000000000, 16777216);
2453
c9df406f
LB		 2454 if (!netif_running(dev))
2455 return 0;
1da177e4 2456
c9df406f
LB		 2457 /*
2458 * Stop and then re-open the interface. This will allocate RX
2459 * skbs of the new MTU.
2460 * There is a possible danger that the open will not succeed,
fc32b0e2 2461 * due to memory being full.
c9df406f
LB		 2462 */
2463 mv643xx_eth_stop(dev);
2464 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 2465 netdev_err(dev,
2466 "fatal error on re-opening device after MTU change\n");
c9df406f
LB		 2467 }
2468
2469 return 0;
1da177e4
LT		 2470}
2471
fc32b0e2 2472static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2473{
fc32b0e2 2474 struct mv643xx_eth_private *mp;
1da177e4 2475
fc32b0e2
LB		 2476 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2477 if (netif_running(mp->dev)) {
e5ef1de1 2478 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2479 port_reset(mp);
2480 port_start(mp);
e5ef1de1 2481 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2482 }
c9df406f
LB		 2483}
2484
c9df406f 2485static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2486{
e5371493 2487 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2488
7542db8b 2489 netdev_info(dev, "tx timeout\n");
d0412d96 2490
c9df406f 2491 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2492}
2493
c9df406f 2494#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2495static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2496{
fc32b0e2 2497 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2498
37a6084f
LB		 2499 wrlp(mp, INT_MASK, 0x00000000);
2500 rdlp(mp, INT_MASK);
c9df406f 2501
fc32b0e2 2502 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2503
e0ca8410 2504 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2505}
c9df406f 2506#endif
9f8dd319 2507
9f8dd319 2508
c9df406f 2509/* platform glue ************************************************************/
e5371493
LB		 2510static void
2511mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2512 struct mbus_dram_target_info *dram)
c9df406f 2513{
cc9754b3 2514 void __iomem *base = msp->base;
c9df406f
LB		 2515 u32 win_enable;
2516 u32 win_protect;
2517 int i;
9f8dd319 2518
c9df406f
LB		 2519 for (i = 0; i < 6; i++) {
2520 writel(0, base + WINDOW_BASE(i));
2521 writel(0, base + WINDOW_SIZE(i));
2522 if (i < 4)
2523 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2524 }
2525
c9df406f
LB		 2526 win_enable = 0x3f;
2527 win_protect = 0;
2528
2529 for (i = 0; i < dram->num_cs; i++) {
2530 struct mbus_dram_window *cs = dram->cs + i;
2531
2532 writel((cs->base & 0xffff0000) |
2533 (cs->mbus_attr << 8) |
2534 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2535 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2536
2537 win_enable &= ~(1 << i);
2538 win_protect |= 3 << (2 * i);
2539 }
2540
2541 writel(win_enable, base + WINDOW_BAR_ENABLE);
2542 msp->win_protect = win_protect;
9f8dd319
DF		 2543}
2544
773fc3ee
LB		 2545static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2546{
2547 /*
2548 * Check whether we have a 14-bit coal limit field in bits
2549 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2550 * SDMA config register.
2551 */
37a6084f
LB		 2552 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2553 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2554 msp->extended_rx_coal_limit = 1;
2555 else
2556 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2557
2558 /*
457b1d5a
LB		 2559 * Check whether the MAC supports TX rate control, and if
2560 * yes, whether its associated registers are in the old or
2561 * the new place.
1e881592 2562 */
37a6084f
LB		 2563 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2564 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2565 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2566 } else {
37a6084f
LB		 2567 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2568 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2569 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2570 else
2571 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2572 }
773fc3ee
LB		 2573}
2574
c9df406f 2575static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2576{
10a9948d 2577 static int mv643xx_eth_version_printed;
c9df406f 2578 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2579 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2580 struct resource *res;
2581 int ret;
9f8dd319 2582
e5371493 2583 if (!mv643xx_eth_version_printed++)
7542db8b
JP		 2584 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2585 mv643xx_eth_driver_version);
9f8dd319 2586
c9df406f
LB		 2587 ret = -EINVAL;
2588 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2589 if (res == NULL)
2590 goto out;
9f8dd319 2591
c9df406f 2592 ret = -ENOMEM;
beae22e6 2593 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
c9df406f
LB		 2594 if (msp == NULL)
2595 goto out;
c9df406f 2596
28f65c11 2597 msp->base = ioremap(res->start, resource_size(res));
cc9754b3 2598 if (msp->base == NULL)
c9df406f
LB		 2599 goto out_free;
2600
ed94493f
LB		 2601 /*
2602 * Set up and register SMI bus.
2603 */
2604 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2605 msp->smi_bus = mdiobus_alloc();
2606 if (msp->smi_bus == NULL)
ed94493f 2607 goto out_unmap;
298cf9be
LB		 2608
2609 msp->smi_bus->priv = msp;
2610 msp->smi_bus->name = "mv643xx_eth smi";
2611 msp->smi_bus->read = smi_bus_read;
2612 msp->smi_bus->write = smi_bus_write,
2613 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2614 msp->smi_bus->parent = &pdev->dev;
2615 msp->smi_bus->phy_mask = 0xffffffff;
2616 if (mdiobus_register(msp->smi_bus) < 0)
2617 goto out_free_mii_bus;
ed94493f
LB		 2618 msp->smi = msp;
2619 } else {
fc0eb9f2 2620 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2621 }
c9df406f 2622
45c5d3bc
LB		 2623 msp->err_interrupt = NO_IRQ;
2624 init_waitqueue_head(&msp->smi_busy_wait);
2625
2626 /*
2627 * Check whether the error interrupt is hooked up.
2628 */
2629 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2630 if (res != NULL) {
2631 int err;
2632
2633 err = request_irq(res->start, mv643xx_eth_err_irq,
2634 IRQF_SHARED, "mv643xx_eth", msp);
2635 if (!err) {
2636 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2637 msp->err_interrupt = res->start;
2638 }
2639 }
2640
c9df406f
LB		 2641 /*
2642 * (Re-)program MBUS remapping windows if we are asked to.
2643 */
2644 if (pd != NULL && pd->dram != NULL)
2645 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2646
fc32b0e2
LB		 2647 /*
2648 * Detect hardware parameters.
2649 */
2650 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
50a749c1
DC		 2651 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2652 pd->tx_csum_limit : 9 * 1024;
773fc3ee 2653 infer_hw_params(msp);
fc32b0e2
LB		 2654
2655 platform_set_drvdata(pdev, msp);
2656
c9df406f
LB		 2657 return 0;
2658
298cf9be
LB		 2659out_free_mii_bus:
2660 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2661out_unmap:
2662 iounmap(msp->base);
c9df406f
LB		 2663out_free:
2664 kfree(msp);
2665out:
2666 return ret;
2667}
2668
2669static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2670{
e5371493 2671 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2672 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2673
298cf9be 2674 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2675 mdiobus_unregister(msp->smi_bus);
bcb3336c 2676 mdiobus_free(msp->smi_bus);
298cf9be 2677 }
45c5d3bc
LB		 2678 if (msp->err_interrupt != NO_IRQ)
2679 free_irq(msp->err_interrupt, msp);
cc9754b3 2680 iounmap(msp->base);
c9df406f
LB		 2681 kfree(msp);
2682
2683 return 0;
9f8dd319
DF		 2684}
2685
c9df406f 2686static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2687 .probe = mv643xx_eth_shared_probe,
2688 .remove = mv643xx_eth_shared_remove,
c9df406f 2689 .driver = {
fc32b0e2 2690 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2691 .owner = THIS_MODULE,
2692 },
2693};
2694
e5371493 2695static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2696{
c9df406f 2697 int addr_shift = 5 * mp->port_num;
fc32b0e2 2698 u32 data;
1da177e4 2699
fc32b0e2
LB		 2700 data = rdl(mp, PHY_ADDR);
2701 data &= ~(0x1f << addr_shift);
2702 data |= (phy_addr & 0x1f) << addr_shift;
2703 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2704}
2705
e5371493 2706static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2707{
fc32b0e2
LB		 2708 unsigned int data;
2709
2710 data = rdl(mp, PHY_ADDR);
2711
2712 return (data >> (5 * mp->port_num)) & 0x1f;
2713}
2714
2715static void set_params(struct mv643xx_eth_private *mp,
2716 struct mv643xx_eth_platform_data *pd)
2717{
2718 struct net_device *dev = mp->dev;
2719
2720 if (is_valid_ether_addr(pd->mac_addr))
2721 memcpy(dev->dev_addr, pd->mac_addr, 6);
2722 else
2723 uc_addr_get(mp, dev->dev_addr);
2724
e7d2f4db 2725 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2726 if (pd->rx_queue_size)
e7d2f4db 2727 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2728 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2729 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2730
f7981c1c 2731 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2732
e7d2f4db 2733 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2734 if (pd->tx_queue_size)
e7d2f4db 2735 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2736 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2737 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2738
f7981c1c 2739 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2740}
2741
ed94493f
LB		 2742static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2743 int phy_addr)
1da177e4 2744{
298cf9be 2745 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2746 struct phy_device *phydev;
2747 int start;
2748 int num;
2749 int i;
45c5d3bc 2750
ed94493f
LB		 2751 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2752 start = phy_addr_get(mp) & 0x1f;
2753 num = 32;
2754 } else {
2755 start = phy_addr & 0x1f;
2756 num = 1;
2757 }
45c5d3bc 2758
ed94493f
LB		 2759 phydev = NULL;
2760 for (i = 0; i < num; i++) {
2761 int addr = (start + i) & 0x1f;
fc32b0e2 2762
ed94493f
LB		 2763 if (bus->phy_map[addr] == NULL)
2764 mdiobus_scan(bus, addr);
1da177e4 2765
ed94493f
LB		 2766 if (phydev == NULL) {
2767 phydev = bus->phy_map[addr];
2768 if (phydev != NULL)
2769 phy_addr_set(mp, addr);
2770 }
2771 }
1da177e4 2772
ed94493f 2773 return phydev;
1da177e4
LT		 2774}
2775
ed94493f 2776static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2777{
ed94493f 2778 struct phy_device *phy = mp->phy;
c28a4f89 2779
fc32b0e2
LB		 2780 phy_reset(mp);
2781
db1d7bf7 2782 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2783
2784 if (speed == 0) {
2785 phy->autoneg = AUTONEG_ENABLE;
2786 phy->speed = 0;
2787 phy->duplex = 0;
2788 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2789 } else {
ed94493f
LB		 2790 phy->autoneg = AUTONEG_DISABLE;
2791 phy->advertising = 0;
2792 phy->speed = speed;
2793 phy->duplex = duplex;
c9df406f 2794 }
ed94493f 2795 phy_start_aneg(phy);
c28a4f89
JC		 2796}
2797
81600eea
LB		 2798static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2799{
2800 u32 pscr;
2801
37a6084f 2802 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2803 if (pscr & SERIAL_PORT_ENABLE) {
2804 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2805 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2806 }
2807
2808 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2809 if (mp->phy == NULL) {
81600eea
LB		 2810 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2811 if (speed == SPEED_1000)
2812 pscr |= SET_GMII_SPEED_TO_1000;
2813 else if (speed == SPEED_100)
2814 pscr |= SET_MII_SPEED_TO_100;
2815
2816 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2817
2818 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2819 if (duplex == DUPLEX_FULL)
2820 pscr |= SET_FULL_DUPLEX_MODE;
2821 }
2822
37a6084f 2823 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2824}
2825
ea8a8642
LB		 2826static const struct net_device_ops mv643xx_eth_netdev_ops = {
2827 .ndo_open = mv643xx_eth_open,
2828 .ndo_stop = mv643xx_eth_stop,
2829 .ndo_start_xmit = mv643xx_eth_xmit,
2830 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2831 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 2832 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 2833 .ndo_do_ioctl = mv643xx_eth_ioctl,
2834 .ndo_change_mtu = mv643xx_eth_change_mtu,
aad59c43 2835 .ndo_set_features = mv643xx_eth_set_features,
ea8a8642
LB		 2836 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2837 .ndo_get_stats = mv643xx_eth_get_stats,
2838#ifdef CONFIG_NET_POLL_CONTROLLER
2839 .ndo_poll_controller = mv643xx_eth_netpoll,
2840#endif
2841};
2842
c9df406f 2843static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2844{
c9df406f 2845 struct mv643xx_eth_platform_data *pd;
e5371493 2846 struct mv643xx_eth_private *mp;
c9df406f 2847 struct net_device *dev;
c9df406f 2848 struct resource *res;
fc32b0e2 2849 int err;
1da177e4 2850
c9df406f
LB		 2851 pd = pdev->dev.platform_data;
2852 if (pd == NULL) {
7542db8b 2853 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2854 return -ENODEV;
2855 }
1da177e4 2856
c9df406f 2857 if (pd->shared == NULL) {
7542db8b 2858 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2859 return -ENODEV;
2860 }
8f518703 2861
e5ef1de1 2862 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2863 if (!dev)
2864 return -ENOMEM;
1da177e4 2865
c9df406f 2866 mp = netdev_priv(dev);
fc32b0e2
LB		 2867 platform_set_drvdata(pdev, mp);
2868
2869 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2870 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2871 mp->port_num = pd->port_number;
2872
c9df406f 2873 mp->dev = dev;
78fff83b 2874
fc32b0e2 2875 set_params(mp, pd);
206d6b32
BH		 2876 netif_set_real_num_tx_queues(dev, mp->txq_count);
2877 netif_set_real_num_rx_queues(dev, mp->rxq_count);
fc32b0e2 2878
ed94493f
LB		 2879 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2880 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2881
6bdf576e 2882 if (mp->phy != NULL)
ed94493f 2883 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2884
2885 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2886
81600eea 2887 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2888
4ff3495a
LB		 2889
2890 mib_counters_clear(mp);
2891
2892 init_timer(&mp->mib_counters_timer);
2893 mp->mib_counters_timer.data = (unsigned long)mp;
2894 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2895 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2896 add_timer(&mp->mib_counters_timer);
2897
2898 spin_lock_init(&mp->mib_counters_lock);
2899
2900 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2901
2257e05c
LB		 2902 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2903
2904 init_timer(&mp->rx_oom);
2905 mp->rx_oom.data = (unsigned long)mp;
2906 mp->rx_oom.function = oom_timer_wrapper;
2907
fc32b0e2 2908
c9df406f
LB		 2909 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2910 BUG_ON(!res);
2911 dev->irq = res->start;
1da177e4 2912
ea8a8642
LB		 2913 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2914
c9df406f
LB		 2915 dev->watchdog_timeo = 2 * HZ;
2916 dev->base_addr = 0;
1da177e4 2917
aad59c43
MM		 2918 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2919 NETIF_F_RXCSUM | NETIF_F_LRO;
2920 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
e32b6617 2921 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2922
01789349
JP		 2923 dev->priv_flags |= IFF_UNICAST_FLT;
2924
fc32b0e2 2925 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2926
c9df406f 2927 if (mp->shared->win_protect)
fc32b0e2 2928 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2929
a5fe3616
LB		 2930 netif_carrier_off(dev);
2931
b5e86db4
LB		 2932 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2933
4fb0a54a 2934 set_rx_coal(mp, 250);
a5fe3616
LB		 2935 set_tx_coal(mp, 0);
2936
c9df406f
LB		 2937 err = register_netdev(dev);
2938 if (err)
2939 goto out;
1da177e4 2940
7542db8b
JP		 2941 netdev_notice(dev, "port %d with MAC address %pM\n",
2942 mp->port_num, dev->dev_addr);
1da177e4 2943
13d64285 2944 if (mp->tx_desc_sram_size > 0)
7542db8b 2945 netdev_notice(dev, "configured with sram\n");
1da177e4 2946
c9df406f 2947 return 0;
1da177e4 2948
c9df406f
LB		 2949out:
2950 free_netdev(dev);
1da177e4 2951
c9df406f 2952 return err;
1da177e4
LT		 2953}
2954
c9df406f 2955static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2956{
fc32b0e2 2957 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2958
fc32b0e2 2959 unregister_netdev(mp->dev);
ed94493f
LB		 2960 if (mp->phy != NULL)
2961 phy_detach(mp->phy);
23f333a2 2962 cancel_work_sync(&mp->tx_timeout_task);
fc32b0e2 2963 free_netdev(mp->dev);
c9df406f 2964
c9df406f 2965 platform_set_drvdata(pdev, NULL);
fc32b0e2 2966
c9df406f 2967 return 0;
1da177e4
LT		 2968}
2969
c9df406f 2970static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2971{
fc32b0e2 2972 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2973
c9df406f 2974 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2975 wrlp(mp, INT_MASK, 0);
2976 rdlp(mp, INT_MASK);
c9df406f 2977
fc32b0e2
LB		 2978 if (netif_running(mp->dev))
2979 port_reset(mp);
d0412d96
JC		 2980}
2981
c9df406f 2982static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2983 .probe = mv643xx_eth_probe,
2984 .remove = mv643xx_eth_remove,
2985 .shutdown = mv643xx_eth_shutdown,
c9df406f 2986 .driver = {
fc32b0e2 2987 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2988 .owner = THIS_MODULE,
2989 },
2990};
2991
e5371493 2992static int __init mv643xx_eth_init_module(void)
d0412d96 2993{
c9df406f 2994 int rc;
d0412d96 2995
c9df406f
LB		 2996 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2997 if (!rc) {
2998 rc = platform_driver_register(&mv643xx_eth_driver);
2999 if (rc)
3000 platform_driver_unregister(&mv643xx_eth_shared_driver);
3001 }
fc32b0e2 3002
c9df406f 3003 return rc;
d0412d96 3004}
fc32b0e2 3005module_init(mv643xx_eth_init_module);
d0412d96 3006
e5371493 3007static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3008{
c9df406f
LB		 3009 platform_driver_unregister(&mv643xx_eth_driver);
3010 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3011}
e5371493 3012module_exit(mv643xx_eth_cleanup_module);
1da177e4 3013
45675bc6
LB		 3014MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3015 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3016MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3017MODULE_LICENSE("GPL");
c9df406f 3018MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3019MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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