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Merge tag 'linux-kselftest-4.13-rc6-fixes' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
3871c387
MS		 23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
24 *
1da177e4
LT		 25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
0ab75ae8 36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
1da177e4 37 */
a779d38c 38
7542db8b
JP		 39#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40
1da177e4
LT		 41#include <linux/init.h>
42#include <linux/dma-mapping.h>
b6298c22 43#include <linux/in.h>
c3efab8e 44#include <linux/ip.h>
3ae8f4e0 45#include <net/tso.h>
1da177e4
LT		 46#include <linux/tcp.h>
47#include <linux/udp.h>
48#include <linux/etherdevice.h>
1da177e4
LT		 49#include <linux/delay.h>
50#include <linux/ethtool.h>
d052d1be 51#include <linux/platform_device.h>
fbd6a754
LB		 52#include <linux/module.h>
53#include <linux/kernel.h>
54#include <linux/spinlock.h>
55#include <linux/workqueue.h>
ed94493f 56#include <linux/phy.h>
fbd6a754 57#include <linux/mv643xx_eth.h>
10a9948d 58#include <linux/io.h>
3619eb85 59#include <linux/interrupt.h>
10a9948d 60#include <linux/types.h>
5a0e3ad6 61#include <linux/slab.h>
452503eb 62#include <linux/clk.h>
76723bca
SH		 63#include <linux/of.h>
64#include <linux/of_irq.h>
65#include <linux/of_net.h>
cc9d4598 66#include <linux/of_mdio.h>
fbd6a754 67
e5371493 68static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 69static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 70
fbd6a754 71
fbd6a754
LB		 72/*
73 * Registers shared between all ports.
74 */
3cb4667c 75#define PHY_ADDR 0x0000
3cb4667c
LB		 76#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79#define WINDOW_BAR_ENABLE 0x0290
80#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 81
82/*
37a6084f
LB		 83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 85 */
37a6084f 86#define PORT_CONFIG 0x0000
d9a073ea 87#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 88#define PORT_CONFIG_EXT 0x0004
89#define MAC_ADDR_LOW 0x0014
90#define MAC_ADDR_HIGH 0x0018
91#define SDMA_CONFIG 0x001c
becfad97
LB		 92#define TX_BURST_SIZE_16_64BIT 0x01000000
93#define TX_BURST_SIZE_4_64BIT 0x00800000
94#define BLM_TX_NO_SWAP 0x00000020
95#define BLM_RX_NO_SWAP 0x00000010
96#define RX_BURST_SIZE_16_64BIT 0x00000008
97#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 98#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 99#define SET_MII_SPEED_TO_100 0x01000000
100#define SET_GMII_SPEED_TO_1000 0x00800000
101#define SET_FULL_DUPLEX_MODE 0x00200000
102#define MAX_RX_PACKET_9700BYTE 0x000a0000
103#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104#define DO_NOT_FORCE_LINK_FAIL 0x00000400
105#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108#define FORCE_LINK_PASS 0x00000002
109#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 110#define PORT_STATUS 0x0044
a2a41689 111#define TX_FIFO_EMPTY 0x00000400
ae9ae064 112#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 113#define PORT_SPEED_MASK 0x00000030
114#define PORT_SPEED_1000 0x00000010
115#define PORT_SPEED_100 0x00000020
116#define PORT_SPEED_10 0x00000000
117#define FLOW_CONTROL_ENABLED 0x00000008
118#define FULL_DUPLEX 0x00000004
81600eea 119#define LINK_UP 0x00000002
37a6084f
LB		 120#define TXQ_COMMAND 0x0048
121#define TXQ_FIX_PRIO_CONF 0x004c
cb85215f
SH		 122#define PORT_SERIAL_CONTROL1 0x004c
123#define CLK125_BYPASS_EN 0x00000010
37a6084f
LB		 124#define TX_BW_RATE 0x0050
125#define TX_BW_MTU 0x0058
126#define TX_BW_BURST 0x005c
127#define INT_CAUSE 0x0060
226bb6b7 128#define INT_TX_END 0x07f80000
e0ca8410 129#define INT_TX_END_0 0x00080000
befefe21 130#define INT_RX 0x000003fc
e0ca8410 131#define INT_RX_0 0x00000004
073a345c 132#define INT_EXT 0x00000002
37a6084f 133#define INT_CAUSE_EXT 0x0064
befefe21
LB		 134#define INT_EXT_LINK_PHY 0x00110000
135#define INT_EXT_TX 0x000000ff
37a6084f
LB		 136#define INT_MASK 0x0068
137#define INT_MASK_EXT 0x006c
138#define TX_FIFO_URGENT_THRESHOLD 0x0074
302476c9
PZ		 139#define RX_DISCARD_FRAME_CNT 0x0084
140#define RX_OVERRUN_FRAME_CNT 0x0088
37a6084f
LB		 141#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142#define TX_BW_RATE_MOVED 0x00e0
143#define TX_BW_MTU_MOVED 0x00e8
144#define TX_BW_BURST_MOVED 0x00ec
145#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146#define RXQ_COMMAND 0x0280
147#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
151
152/*
153 * Misc per-port registers.
154 */
3cb4667c
LB		 155#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 159
2679a550
LB		 160
161/*
becfad97 162 * SDMA configuration register default value.
2679a550 163 */
fbd6a754
LB		 164#if defined(__BIG_ENDIAN)
165#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 168#elif defined(__LITTLE_ENDIAN)
169#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 170 (RX_BURST_SIZE_4_64BIT | \
171 BLM_RX_NO_SWAP | \
172 BLM_TX_NO_SWAP | \
173 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 174#else
175#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176#endif
177
2beff77b
LB		 178
179/*
becfad97 180 * Misc definitions.
2beff77b 181 */
becfad97 182#define DEFAULT_RX_QUEUE_SIZE 128
3ae8f4e0 183#define DEFAULT_TX_QUEUE_SIZE 512
7fd96ce4 184#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 185
3ae8f4e0 186#define TSO_HEADER_SIZE 128
fbd6a754 187
ee9e4956
EG		 188/* Max number of allowed TCP segments for software TSO */
189#define MV643XX_MAX_TSO_SEGS 100
190#define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
191
b926260c
EG		 192#define IS_TSO_HEADER(txq, addr) \
193 ((addr >= txq->tso_hdrs_dma) && \
194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
9e911414
EG		 195
196#define DESC_DMA_MAP_SINGLE 0
197#define DESC_DMA_MAP_PAGE 1
198
7ca72a3b
LB		 199/*
200 * RX/TX descriptors.
fbd6a754
LB		 201 */
202#if defined(__BIG_ENDIAN)
cc9754b3 203struct rx_desc {
fbd6a754
LB		 204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u16 buf_size; /* Buffer size */
206 u32 cmd_sts; /* Descriptor command status */
207 u32 next_desc_ptr; /* Next descriptor pointer */
208 u32 buf_ptr; /* Descriptor buffer pointer */
209};
210
cc9754b3 211struct tx_desc {
fbd6a754
LB		 212 u16 byte_cnt; /* buffer byte count */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u32 cmd_sts; /* Command/status field */
215 u32 next_desc_ptr; /* Pointer to next descriptor */
216 u32 buf_ptr; /* pointer to buffer for this descriptor*/
217};
218#elif defined(__LITTLE_ENDIAN)
cc9754b3 219struct rx_desc {
fbd6a754
LB		 220 u32 cmd_sts; /* Descriptor command status */
221 u16 buf_size; /* Buffer size */
222 u16 byte_cnt; /* Descriptor buffer byte count */
223 u32 buf_ptr; /* Descriptor buffer pointer */
224 u32 next_desc_ptr; /* Next descriptor pointer */
225};
226
cc9754b3 227struct tx_desc {
fbd6a754
LB		 228 u32 cmd_sts; /* Command/status field */
229 u16 l4i_chk; /* CPU provided TCP checksum */
230 u16 byte_cnt; /* buffer byte count */
231 u32 buf_ptr; /* pointer to buffer for this descriptor*/
232 u32 next_desc_ptr; /* Pointer to next descriptor */
233};
234#else
235#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
236#endif
237
7ca72a3b 238/* RX & TX descriptor command */
cc9754b3 239#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 240
241/* RX & TX descriptor status */
cc9754b3 242#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 243
244/* RX descriptor status */
cc9754b3
LB		 245#define LAYER_4_CHECKSUM_OK 0x40000000
246#define RX_ENABLE_INTERRUPT 0x20000000
247#define RX_FIRST_DESC 0x08000000
248#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 249#define RX_IP_HDR_OK 0x02000000
250#define RX_PKT_IS_IPV4 0x01000000
251#define RX_PKT_IS_ETHERNETV2 0x00800000
252#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
253#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
254#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 255
256/* TX descriptor command */
cc9754b3
LB		 257#define TX_ENABLE_INTERRUPT 0x00800000
258#define GEN_CRC 0x00400000
259#define TX_FIRST_DESC 0x00200000
260#define TX_LAST_DESC 0x00100000
261#define ZERO_PADDING 0x00080000
262#define GEN_IP_V4_CHECKSUM 0x00040000
263#define GEN_TCP_UDP_CHECKSUM 0x00020000
264#define UDP_FRAME 0x00010000
e32b6617 265#define MAC_HDR_EXTRA_4_BYTES 0x00008000
84411f73 266#define GEN_TCP_UDP_CHK_FULL 0x00000400
e32b6617 267#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 268
cc9754b3 269#define TX_IHL_SHIFT 11
7ca72a3b
LB		 270
271
c9df406f 272/* global *******************************************************************/
e5371493 273struct mv643xx_eth_shared_private {
fc32b0e2
LB		 274 /*
275 * Ethernet controller base address.
276 */
cc9754b3 277 void __iomem *base;
c9df406f 278
fc32b0e2
LB		 279 /*
280 * Per-port MBUS window access register value.
281 */
c9df406f
LB		 282 u32 win_protect;
283
fc32b0e2
LB		 284 /*
285 * Hardware-specific parameters.
286 */
773fc3ee 287 int extended_rx_coal_limit;
457b1d5a 288 int tx_bw_control;
9b2c2ff7 289 int tx_csum_limit;
20922486 290 struct clk *clk;
c9df406f
LB		 291};
292
457b1d5a
LB		 293#define TX_BW_CONTROL_ABSENT 0
294#define TX_BW_CONTROL_OLD_LAYOUT 1
295#define TX_BW_CONTROL_NEW_LAYOUT 2
296
e7d2f4db
LB		 297static int mv643xx_eth_open(struct net_device *dev);
298static int mv643xx_eth_stop(struct net_device *dev);
299
c9df406f
LB		 300
301/* per-port *****************************************************************/
e5371493 302struct mib_counters {
fbd6a754
LB		 303 u64 good_octets_received;
304 u32 bad_octets_received;
305 u32 internal_mac_transmit_err;
306 u32 good_frames_received;
307 u32 bad_frames_received;
308 u32 broadcast_frames_received;
309 u32 multicast_frames_received;
310 u32 frames_64_octets;
311 u32 frames_65_to_127_octets;
312 u32 frames_128_to_255_octets;
313 u32 frames_256_to_511_octets;
314 u32 frames_512_to_1023_octets;
315 u32 frames_1024_to_max_octets;
316 u64 good_octets_sent;
317 u32 good_frames_sent;
318 u32 excessive_collision;
319 u32 multicast_frames_sent;
320 u32 broadcast_frames_sent;
321 u32 unrec_mac_control_received;
322 u32 fc_sent;
323 u32 good_fc_received;
324 u32 bad_fc_received;
325 u32 undersize_received;
326 u32 fragments_received;
327 u32 oversize_received;
328 u32 jabber_received;
329 u32 mac_receive_error;
330 u32 bad_crc_event;
331 u32 collision;
332 u32 late_collision;
302476c9
PZ		 333 /* Non MIB hardware counters */
334 u32 rx_discard;
335 u32 rx_overrun;
fbd6a754
LB		 336};
337
8a578111 338struct rx_queue {
64da80a2
LB		 339 int index;
340
8a578111
LB		 341 int rx_ring_size;
342
343 int rx_desc_count;
344 int rx_curr_desc;
345 int rx_used_desc;
346
347 struct rx_desc *rx_desc_area;
348 dma_addr_t rx_desc_dma;
349 int rx_desc_area_size;
350 struct sk_buff **rx_skb;
8a578111
LB		 351};
352
13d64285 353struct tx_queue {
3d6b35bc
LB		 354 int index;
355
13d64285 356 int tx_ring_size;
fbd6a754 357
13d64285
LB		 358 int tx_desc_count;
359 int tx_curr_desc;
360 int tx_used_desc;
fbd6a754 361
ee9e4956
EG		 362 int tx_stop_threshold;
363 int tx_wake_threshold;
364
3ae8f4e0
EG		 365 char *tso_hdrs;
366 dma_addr_t tso_hdrs_dma;
367
5daffe94 368 struct tx_desc *tx_desc_area;
9e911414 369 char *tx_desc_mapping; /* array to track the type of the dma mapping */
fbd6a754
LB		 370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
99ab08e0
LB		 372
373 struct sk_buff_head tx_skb;
8fd89211
LB		 374
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
13d64285
LB		 378};
379
380struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
37a6084f 382 void __iomem *base;
fc32b0e2 383 int port_num;
13d64285 384
fc32b0e2 385 struct net_device *dev;
fbd6a754 386
4ff3495a
LB		 387 struct timer_list mib_counters_timer;
388 spinlock_t mib_counters_lock;
fc32b0e2 389 struct mib_counters mib_counters;
4ff3495a 390
fc32b0e2 391 struct work_struct tx_timeout_task;
8a578111 392
1fa38c58 393 struct napi_struct napi;
e0ca8410 394 u32 int_mask;
1319ebad 395 u8 oom;
1fa38c58
LB		 396 u8 work_link;
397 u8 work_tx;
398 u8 work_tx_end;
399 u8 work_rx;
400 u8 work_rx_refill;
1fa38c58 401
2bcb4b0f 402 int skb_size;
2bcb4b0f 403
8a578111
LB		 404 /*
405 * RX state.
406 */
e7d2f4db 407 int rx_ring_size;
8a578111
LB		 408 unsigned long rx_desc_sram_addr;
409 int rx_desc_sram_size;
f7981c1c 410 int rxq_count;
2257e05c 411 struct timer_list rx_oom;
64da80a2 412 struct rx_queue rxq[8];
13d64285
LB		 413
414 /*
415 * TX state.
416 */
e7d2f4db 417 int tx_ring_size;
13d64285
LB		 418 unsigned long tx_desc_sram_addr;
419 int tx_desc_sram_size;
f7981c1c 420 int txq_count;
3d6b35bc 421 struct tx_queue txq[8];
452503eb
AL		 422
423 /*
424 * Hardware-specific parameters.
425 */
426 struct clk *clk;
427 unsigned int t_clk;
fbd6a754 428};
1da177e4 429
fbd6a754 430
c9df406f 431/* port register accessors **************************************************/
e5371493 432static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 433{
cc9754b3 434 return readl(mp->shared->base + offset);
c9df406f 435}
fbd6a754 436
37a6084f
LB		 437static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
438{
439 return readl(mp->base + offset);
440}
441
e5371493 442static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 443{
cc9754b3 444 writel(data, mp->shared->base + offset);
c9df406f 445}
fbd6a754 446
37a6084f
LB		 447static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
448{
449 writel(data, mp->base + offset);
450}
451
fbd6a754 452
c9df406f 453/* rxq/txq helper functions *************************************************/
8a578111 454static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 455{
64da80a2 456 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 457}
fbd6a754 458
13d64285
LB		 459static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
460{
3d6b35bc 461 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 462}
463
8a578111 464static void rxq_enable(struct rx_queue *rxq)
c9df406f 465{
8a578111 466 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 467 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 468}
1da177e4 469
8a578111
LB		 470static void rxq_disable(struct rx_queue *rxq)
471{
472 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 473 u8 mask = 1 << rxq->index;
1da177e4 474
37a6084f
LB		 475 wrlp(mp, RXQ_COMMAND, mask << 8);
476 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 477 udelay(10);
c9df406f
LB		 478}
479
6b368f68
LB		 480static void txq_reset_hw_ptr(struct tx_queue *txq)
481{
482 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 483 u32 addr;
484
485 addr = (u32)txq->tx_desc_dma;
486 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 487 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 488}
489
13d64285 490static void txq_enable(struct tx_queue *txq)
1da177e4 491{
13d64285 492 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 493 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 494}
495
13d64285 496static void txq_disable(struct tx_queue *txq)
1da177e4 497{
13d64285 498 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 499 u8 mask = 1 << txq->index;
c9df406f 500
37a6084f
LB		 501 wrlp(mp, TXQ_COMMAND, mask << 8);
502 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 503 udelay(10);
504}
505
1fa38c58 506static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 507{
508 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 509 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 510
8fd89211
LB		 511 if (netif_tx_queue_stopped(nq)) {
512 __netif_tx_lock(nq, smp_processor_id());
ee9e4956 513 if (txq->tx_desc_count <= txq->tx_wake_threshold)
8fd89211
LB		 514 netif_tx_wake_queue(nq);
515 __netif_tx_unlock(nq);
516 }
1da177e4
LT		 517}
518
8a578111 519static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 520{
8a578111
LB		 521 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
522 struct net_device_stats *stats = &mp->dev->stats;
523 int rx;
1da177e4 524
8a578111 525 rx = 0;
9e1f3772 526 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 527 struct rx_desc *rx_desc;
96587661 528 unsigned int cmd_sts;
fc32b0e2 529 struct sk_buff *skb;
6b8f90c2 530 u16 byte_cnt;
ff561eef 531
8a578111 532 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 533
96587661 534 cmd_sts = rx_desc->cmd_sts;
2257e05c 535 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 536 break;
96587661 537 rmb();
1da177e4 538
8a578111
LB		 539 skb = rxq->rx_skb[rxq->rx_curr_desc];
540 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 541
9da78745
LB		 542 rxq->rx_curr_desc++;
543 if (rxq->rx_curr_desc == rxq->rx_ring_size)
544 rxq->rx_curr_desc = 0;
ff561eef 545
eb0519b5 546 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 547 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 548 rxq->rx_desc_count--;
549 rx++;
b1dd9ca1 550
1fa38c58
LB		 551 mp->work_rx_refill |= 1 << rxq->index;
552
6b8f90c2
LB		 553 byte_cnt = rx_desc->byte_cnt;
554
468d09f8
DF		 555 /*
556 * Update statistics.
fc32b0e2
LB		 557 *
558 * Note that the descriptor byte count includes 2 dummy
559 * bytes automatically inserted by the hardware at the
560 * start of the packet (which we don't count), and a 4
561 * byte CRC at the end of the packet (which we do count).
468d09f8 562 */
1da177e4 563 stats->rx_packets++;
6b8f90c2 564 stats->rx_bytes += byte_cnt - 2;
96587661 565
1da177e4 566 /*
fc32b0e2
LB		 567 * In case we received a packet without first / last bits
568 * on, or the error summary bit is set, the packet needs
569 * to be dropped.
1da177e4 570 */
f61e5547
LB		 571 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
572 != (RX_FIRST_DESC | RX_LAST_DESC))
573 goto err;
574
575 /*
576 * The -4 is for the CRC in the trailer of the
577 * received packet
578 */
579 skb_put(skb, byte_cnt - 2 - 4);
580
581 if (cmd_sts & LAYER_4_CHECKSUM_OK)
582 skb->ip_summed = CHECKSUM_UNNECESSARY;
583 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 584
3619eb85 585 napi_gro_receive(&mp->napi, skb);
f61e5547
LB		 586
587 continue;
588
589err:
590 stats->rx_dropped++;
591
592 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
593 (RX_FIRST_DESC | RX_LAST_DESC)) {
594 if (net_ratelimit())
7542db8b
JP		 595 netdev_err(mp->dev,
596 "received packet spanning multiple descriptors\n");
1da177e4 597 }
f61e5547
LB		 598
599 if (cmd_sts & ERROR_SUMMARY)
600 stats->rx_errors++;
601
602 dev_kfree_skb(skb);
1da177e4 603 }
fc32b0e2 604
1fa38c58
LB		 605 if (rx < budget)
606 mp->work_rx &= ~(1 << rxq->index);
607
8a578111 608 return rx;
1da177e4
LT		 609}
610
1fa38c58 611static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 612{
1fa38c58 613 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 614 int refilled;
8a578111 615
1fa38c58
LB		 616 refilled = 0;
617 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
618 struct sk_buff *skb;
1fa38c58 619 int rx;
53771522 620 struct rx_desc *rx_desc;
530e557a 621 int size;
d0412d96 622
acb600de 623 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
2bcb4b0f 624
1fa38c58 625 if (skb == NULL) {
1319ebad 626 mp->oom = 1;
1fa38c58
LB		 627 goto oom;
628 }
d0412d96 629
7fd96ce4
LB		 630 if (SKB_DMA_REALIGN)
631 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 632
1fa38c58
LB		 633 refilled++;
634 rxq->rx_desc_count++;
c9df406f 635
1fa38c58
LB		 636 rx = rxq->rx_used_desc++;
637 if (rxq->rx_used_desc == rxq->rx_ring_size)
638 rxq->rx_used_desc = 0;
2257e05c 639
53771522
LB		 640 rx_desc = rxq->rx_desc_area + rx;
641
18f1d054 642 size = skb_end_pointer(skb) - skb->data;
eb0519b5 643 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 644 skb->data, size,
eb0519b5 645 DMA_FROM_DEVICE);
530e557a 646 rx_desc->buf_size = size;
1fa38c58
LB		 647 rxq->rx_skb[rx] = skb;
648 wmb();
53771522 649 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 650 wmb();
2257e05c 651
1fa38c58
LB		 652 /*
653 * The hardware automatically prepends 2 bytes of
654 * dummy data to each received packet, so that the
655 * IP header ends up 16-byte aligned.
656 */
657 skb_reserve(skb, 2);
658 }
659
660 if (refilled < budget)
661 mp->work_rx_refill &= ~(1 << rxq->index);
662
663oom:
664 return refilled;
d0412d96
JC		 665}
666
c9df406f
LB		 667
668/* tx ***********************************************************************/
c9df406f 669static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 670{
13d64285 671 int frag;
1da177e4 672
c9df406f 673 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
9e903e08
ED		 674 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
675
676 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
c9df406f 677 return 1;
1da177e4 678 }
13d64285 679
c9df406f
LB		 680 return 0;
681}
7303fde8 682
0a8fa933
EG		 683static inline __be16 sum16_as_be(__sum16 sum)
684{
685 return (__force __be16)sum;
686}
687
688static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
689 u16 *l4i_chk, u32 *command, int length)
690{
691 int ret;
692 u32 cmd = 0;
693
694 if (skb->ip_summed == CHECKSUM_PARTIAL) {
695 int hdr_len;
696 int tag_bytes;
697
698 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
699 skb->protocol != htons(ETH_P_8021Q));
700
701 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
702 tag_bytes = hdr_len - ETH_HLEN;
703
704 if (length - hdr_len > mp->shared->tx_csum_limit ||
705 unlikely(tag_bytes & ~12)) {
706 ret = skb_checksum_help(skb);
707 if (!ret)
708 goto no_csum;
709 return ret;
710 }
711
712 if (tag_bytes & 4)
713 cmd |= MAC_HDR_EXTRA_4_BYTES;
714 if (tag_bytes & 8)
715 cmd |= MAC_HDR_EXTRA_8_BYTES;
716
84411f73 717 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
0a8fa933
EG		 718 GEN_IP_V4_CHECKSUM |
719 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
720
84411f73
EG		 721 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
722 * it seems we don't need to pass the initial checksum. */
0a8fa933
EG		 723 switch (ip_hdr(skb)->protocol) {
724 case IPPROTO_UDP:
725 cmd |= UDP_FRAME;
84411f73 726 *l4i_chk = 0;
0a8fa933
EG		 727 break;
728 case IPPROTO_TCP:
84411f73 729 *l4i_chk = 0;
0a8fa933
EG		 730 break;
731 default:
732 WARN(1, "protocol not supported");
733 }
734 } else {
735no_csum:
736 /* Errata BTS #50, IHL must be 5 if no HW checksum */
737 cmd |= 5 << TX_IHL_SHIFT;
738 }
739 *command = cmd;
740 return 0;
741}
742
3ae8f4e0
EG		 743static inline int
744txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
745 struct sk_buff *skb, char *data, int length,
746 bool last_tcp, bool is_last)
747{
748 int tx_index;
749 u32 cmd_sts;
750 struct tx_desc *desc;
751
752 tx_index = txq->tx_curr_desc++;
753 if (txq->tx_curr_desc == txq->tx_ring_size)
754 txq->tx_curr_desc = 0;
755 desc = &txq->tx_desc_area[tx_index];
9e911414 756 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
3ae8f4e0
EG		 757
758 desc->l4i_chk = 0;
759 desc->byte_cnt = length;
91986fd3
PK		 760
761 if (length <= 8 && (uintptr_t)data & 0x7) {
762 /* Copy unaligned small data fragment to TSO header data area */
3b89624a 763 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
91986fd3
PK		 764 data, length);
765 desc->buf_ptr = txq->tso_hdrs_dma
3b89624a 766 + tx_index * TSO_HEADER_SIZE;
91986fd3
PK		 767 } else {
768 /* Alignment is okay, map buffer and hand off to hardware */
769 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
770 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
771 length, DMA_TO_DEVICE);
772 if (unlikely(dma_mapping_error(dev->dev.parent,
773 desc->buf_ptr))) {
774 WARN(1, "dma_map_single failed!\n");
775 return -ENOMEM;
776 }
3ae8f4e0
EG		 777 }
778
779 cmd_sts = BUFFER_OWNED_BY_DMA;
780 if (last_tcp) {
781 /* last descriptor in the TCP packet */
782 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
783 /* last descriptor in SKB */
784 if (is_last)
785 cmd_sts |= TX_ENABLE_INTERRUPT;
786 }
787 desc->cmd_sts = cmd_sts;
788 return 0;
789}
790
791static inline void
968200f3
PK		 792txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
793 u32 *first_cmd_sts, bool first_desc)
3ae8f4e0
EG		 794{
795 struct mv643xx_eth_private *mp = txq_to_mp(txq);
796 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
797 int tx_index;
798 struct tx_desc *desc;
799 int ret;
800 u32 cmd_csum = 0;
801 u16 l4i_chk = 0;
968200f3 802 u32 cmd_sts;
3ae8f4e0
EG		 803
804 tx_index = txq->tx_curr_desc;
805 desc = &txq->tx_desc_area[tx_index];
806
807 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
808 if (ret)
809 WARN(1, "failed to prepare checksum!");
810
811 /* Should we set this? Can't use the value from skb_tx_csum()
812 * as it's not the correct initial L4 checksum to use. */
813 desc->l4i_chk = 0;
814
815 desc->byte_cnt = hdr_len;
816 desc->buf_ptr = txq->tso_hdrs_dma +
817 txq->tx_curr_desc * TSO_HEADER_SIZE;
968200f3 818 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
3ae8f4e0
EG		 819 GEN_CRC;
820
968200f3
PK		 821 /* Defer updating the first command descriptor until all
822 * following descriptors have been written.
823 */
824 if (first_desc)
825 *first_cmd_sts = cmd_sts;
826 else
827 desc->cmd_sts = cmd_sts;
828
3ae8f4e0
EG		 829 txq->tx_curr_desc++;
830 if (txq->tx_curr_desc == txq->tx_ring_size)
831 txq->tx_curr_desc = 0;
832}
833
834static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
835 struct net_device *dev)
836{
837 struct mv643xx_eth_private *mp = txq_to_mp(txq);
838 int total_len, data_left, ret;
839 int desc_count = 0;
840 struct tso_t tso;
841 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
968200f3
PK		 842 struct tx_desc *first_tx_desc;
843 u32 first_cmd_sts = 0;
3ae8f4e0
EG		 844
845 /* Count needed descriptors */
846 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
847 netdev_dbg(dev, "not enough descriptors for TSO!\n");
848 return -EBUSY;
849 }
850
968200f3
PK		 851 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
852
3ae8f4e0
EG		 853 /* Initialize the TSO handler, and prepare the first payload */
854 tso_start(skb, &tso);
855
856 total_len = skb->len - hdr_len;
857 while (total_len > 0) {
968200f3 858 bool first_desc = (desc_count == 0);
3ae8f4e0
EG		 859 char *hdr;
860
861 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
862 total_len -= data_left;
863 desc_count++;
864
865 /* prepare packet headers: MAC + IP + TCP */
866 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
867 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
968200f3
PK		 868 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
869 first_desc);
3ae8f4e0
EG		 870
871 while (data_left > 0) {
872 int size;
873 desc_count++;
874
875 size = min_t(int, tso.size, data_left);
876 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
877 size == data_left,
878 total_len == 0);
879 if (ret)
880 goto err_release;
881 data_left -= size;
882 tso_build_data(skb, &tso, size);
883 }
884 }
885
886 __skb_queue_tail(&txq->tx_skb, skb);
887 skb_tx_timestamp(skb);
888
968200f3
PK		 889 /* ensure all other descriptors are written before first cmd_sts */
890 wmb();
891 first_tx_desc->cmd_sts = first_cmd_sts;
892
3ae8f4e0
EG		 893 /* clear TX_END status */
894 mp->work_tx_end &= ~(1 << txq->index);
895
896 /* ensure all descriptors are written before poking hardware */
897 wmb();
898 txq_enable(txq);
899 txq->tx_desc_count += desc_count;
900 return 0;
901err_release:
902 /* TODO: Release all used data descriptors; header descriptors must not
903 * be DMA-unmapped.
904 */
905 return ret;
906}
907
13d64285 908static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 909{
eb0519b5 910 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 911 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 912 int frag;
1da177e4 913
13d64285
LB		 914 for (frag = 0; frag < nr_frags; frag++) {
915 skb_frag_t *this_frag;
916 int tx_index;
917 struct tx_desc *desc;
918
919 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 920 tx_index = txq->tx_curr_desc++;
921 if (txq->tx_curr_desc == txq->tx_ring_size)
922 txq->tx_curr_desc = 0;
13d64285 923 desc = &txq->tx_desc_area[tx_index];
9e911414 924 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
13d64285
LB		 925
926 /*
927 * The last fragment will generate an interrupt
928 * which will free the skb on TX completion.
929 */
930 if (frag == nr_frags - 1) {
931 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
932 ZERO_PADDING | TX_LAST_DESC |
933 TX_ENABLE_INTERRUPT;
13d64285
LB		 934 } else {
935 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 936 }
937
c9df406f 938 desc->l4i_chk = 0;
9e903e08 939 desc->byte_cnt = skb_frag_size(this_frag);
9e911414
EG		 940 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
941 this_frag, 0, desc->byte_cnt,
942 DMA_TO_DEVICE);
c9df406f 943 }
1da177e4
LT		 944}
945
ee9e4956
EG		 946static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
947 struct net_device *dev)
1da177e4 948{
8fa89bf5 949 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 950 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 951 int tx_index;
cc9754b3 952 struct tx_desc *desc;
c9df406f 953 u32 cmd_sts;
4df89bd5 954 u16 l4i_chk;
0a8fa933 955 int length, ret;
1da177e4 956
0a8fa933 957 cmd_sts = 0;
4df89bd5 958 l4i_chk = 0;
c9df406f 959
ee9e4956
EG		 960 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
961 if (net_ratelimit())
962 netdev_err(dev, "tx queue full?!\n");
963 return -EBUSY;
964 }
965
0a8fa933 966 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
ee9e4956 967 if (ret)
0a8fa933 968 return ret;
0a8fa933 969 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
c9df406f 970
66823b92
LB		 971 tx_index = txq->tx_curr_desc++;
972 if (txq->tx_curr_desc == txq->tx_ring_size)
973 txq->tx_curr_desc = 0;
4df89bd5 974 desc = &txq->tx_desc_area[tx_index];
9e911414 975 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
4df89bd5
LB		 976
977 if (nr_frags) {
978 txq_submit_frag_skb(txq, skb);
979 length = skb_headlen(skb);
980 } else {
981 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
982 length = skb->len;
983 }
984
985 desc->l4i_chk = l4i_chk;
986 desc->byte_cnt = length;
eb0519b5
GP		 987 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
988 length, DMA_TO_DEVICE);
4df89bd5 989
99ab08e0
LB		 990 __skb_queue_tail(&txq->tx_skb, skb);
991
3b182d7d
RC		 992 skb_tx_timestamp(skb);
993
c9df406f
LB		 994 /* ensure all other descriptors are written before first cmd_sts */
995 wmb();
996 desc->cmd_sts = cmd_sts;
997
1fa38c58
LB		 998 /* clear TX_END status */
999 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 1000
c9df406f
LB		 1001 /* ensure all descriptors are written before poking hardware */
1002 wmb();
13d64285 1003 txq_enable(txq);
c9df406f 1004
13d64285 1005 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 1006
1007 return 0;
1da177e4 1008}
1da177e4 1009
0ccfe64d 1010static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 1011{
e5371493 1012 struct mv643xx_eth_private *mp = netdev_priv(dev);
3ae8f4e0 1013 int length, queue, ret;
13d64285 1014 struct tx_queue *txq;
e5ef1de1 1015 struct netdev_queue *nq;
afdb57a2 1016
8fd89211
LB		 1017 queue = skb_get_queue_mapping(skb);
1018 txq = mp->txq + queue;
1019 nq = netdev_get_tx_queue(dev, queue);
1020
c9df406f 1021 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
7542db8b
JP		 1022 netdev_printk(KERN_DEBUG, dev,
1023 "failed to linearize skb with tiny unaligned fragment\n");
c9df406f
LB		 1024 return NETDEV_TX_BUSY;
1025 }
1026
73151ce3
RC		 1027 length = skb->len;
1028
3ae8f4e0
EG		 1029 if (skb_is_gso(skb))
1030 ret = txq_submit_tso(txq, skb, dev);
1031 else
ee9e4956 1032 ret = txq_submit_skb(txq, skb, dev);
3ae8f4e0 1033 if (!ret) {
73151ce3 1034 txq->tx_bytes += length;
4df89bd5 1035 txq->tx_packets++;
c9df406f 1036
ee9e4956 1037 if (txq->tx_desc_count >= txq->tx_stop_threshold)
4df89bd5 1038 netif_tx_stop_queue(nq);
dd11680d
EG		 1039 } else {
1040 txq->tx_dropped++;
1041 dev_kfree_skb_any(skb);
4df89bd5 1042 }
c9df406f 1043
c9df406f 1044 return NETDEV_TX_OK;
1da177e4
LT		 1045}
1046
c9df406f 1047
1fa38c58
LB		 1048/* tx napi ******************************************************************/
1049static void txq_kick(struct tx_queue *txq)
1050{
1051 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 1052 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 1053 u32 hw_desc_ptr;
1054 u32 expected_ptr;
1055
8fd89211 1056 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 1057
37a6084f 1058 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 1059 goto out;
1060
37a6084f 1061 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 1062 expected_ptr = (u32)txq->tx_desc_dma +
1063 txq->tx_curr_desc * sizeof(struct tx_desc);
1064
1065 if (hw_desc_ptr != expected_ptr)
1066 txq_enable(txq);
1067
1068out:
8fd89211 1069 __netif_tx_unlock(nq);
1fa38c58
LB		 1070
1071 mp->work_tx_end &= ~(1 << txq->index);
1072}
1073
1074static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1075{
1076 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 1077 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 1078 int reclaimed;
1079
3aefe2b4 1080 __netif_tx_lock_bh(nq);
1fa38c58
LB		 1081
1082 reclaimed = 0;
1083 while (reclaimed < budget && txq->tx_desc_count > 0) {
1084 int tx_index;
1085 struct tx_desc *desc;
1086 u32 cmd_sts;
9e911414 1087 char desc_dma_map;
1fa38c58
LB		 1088
1089 tx_index = txq->tx_used_desc;
1090 desc = &txq->tx_desc_area[tx_index];
9e911414
EG		 1091 desc_dma_map = txq->tx_desc_mapping[tx_index];
1092
1fa38c58
LB		 1093 cmd_sts = desc->cmd_sts;
1094
1095 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1096 if (!force)
1097 break;
1098 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1099 }
1100
1101 txq->tx_used_desc = tx_index + 1;
1102 if (txq->tx_used_desc == txq->tx_ring_size)
1103 txq->tx_used_desc = 0;
1104
1105 reclaimed++;
1106 txq->tx_desc_count--;
1107
9e911414
EG		 1108 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1109
1110 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1111 dma_unmap_page(mp->dev->dev.parent,
1112 desc->buf_ptr,
1113 desc->byte_cnt,
1114 DMA_TO_DEVICE);
1115 else
1116 dma_unmap_single(mp->dev->dev.parent,
1117 desc->buf_ptr,
1118 desc->byte_cnt,
1119 DMA_TO_DEVICE);
1120 }
2c2a9cbd
KB		 1121
1122 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1123 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1124
1125 if (!WARN_ON(!skb))
1126 dev_kfree_skb(skb);
1127 }
1fa38c58
LB		 1128
1129 if (cmd_sts & ERROR_SUMMARY) {
7542db8b 1130 netdev_info(mp->dev, "tx error\n");
1fa38c58
LB		 1131 mp->dev->stats.tx_errors++;
1132 }
1133
1fa38c58
LB		 1134 }
1135
3aefe2b4 1136 __netif_tx_unlock_bh(nq);
8fd89211 1137
1fa38c58
LB		 1138 if (reclaimed < budget)
1139 mp->work_tx &= ~(1 << txq->index);
1140
1fa38c58
LB		 1141 return reclaimed;
1142}
1143
1144
89df5fdc
LB		 1145/* tx rate control **********************************************************/
1146/*
1147 * Set total maximum TX rate (shared by all TX queues for this port)
1148 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1149 */
1150static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1151{
1152 int token_rate;
1153 int mtu;
1154 int bucket_size;
1155
452503eb 1156 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 1157 if (token_rate > 1023)
1158 token_rate = 1023;
1159
1160 mtu = (mp->dev->mtu + 255) >> 8;
1161 if (mtu > 63)
1162 mtu = 63;
1163
1164 bucket_size = (burst + 255) >> 8;
1165 if (bucket_size > 65535)
1166 bucket_size = 65535;
1167
457b1d5a
LB		 1168 switch (mp->shared->tx_bw_control) {
1169 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1170 wrlp(mp, TX_BW_RATE, token_rate);
1171 wrlp(mp, TX_BW_MTU, mtu);
1172 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1173 break;
1174 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1175 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1176 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1177 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1178 break;
1e881592 1179 }
89df5fdc
LB		 1180}
1181
1182static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1183{
1184 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1185 int token_rate;
1186 int bucket_size;
1187
452503eb 1188 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 1189 if (token_rate > 1023)
1190 token_rate = 1023;
1191
1192 bucket_size = (burst + 255) >> 8;
1193 if (bucket_size > 65535)
1194 bucket_size = 65535;
1195
37a6084f
LB		 1196 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1197 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1198}
1199
1200static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1201{
1202 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1203 int off;
1204 u32 val;
1205
1206 /*
1207 * Turn on fixed priority mode.
1208 */
457b1d5a
LB		 1209 off = 0;
1210 switch (mp->shared->tx_bw_control) {
1211 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1212 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1213 break;
1214 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1215 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1216 break;
1217 }
89df5fdc 1218
457b1d5a 1219 if (off) {
37a6084f 1220 val = rdlp(mp, off);
457b1d5a 1221 val |= 1 << txq->index;
37a6084f 1222 wrlp(mp, off, val);
457b1d5a 1223 }
89df5fdc
LB		 1224}
1225
89df5fdc 1226
c9df406f 1227/* mii management interface *************************************************/
0a9e413b 1228static void mv643xx_eth_adjust_link(struct net_device *dev)
260055bb 1229{
0a9e413b 1230 struct mv643xx_eth_private *mp = netdev_priv(dev);
260055bb
PS		 1231 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1232 u32 autoneg_disable = FORCE_LINK_PASS |
1233 DISABLE_AUTO_NEG_SPEED_GMII |
1234 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1235 DISABLE_AUTO_NEG_FOR_DUPLEX;
1236
1e8a655d 1237 if (dev->phydev->autoneg == AUTONEG_ENABLE) {
260055bb
PS		 1238 /* enable auto negotiation */
1239 pscr &= ~autoneg_disable;
1240 goto out_write;
1241 }
1242
1243 pscr |= autoneg_disable;
1244
1e8a655d 1245 if (dev->phydev->speed == SPEED_1000) {
260055bb
PS		 1246 /* force gigabit, half duplex not supported */
1247 pscr |= SET_GMII_SPEED_TO_1000;
1248 pscr |= SET_FULL_DUPLEX_MODE;
1249 goto out_write;
1250 }
1251
1252 pscr &= ~SET_GMII_SPEED_TO_1000;
1253
1e8a655d 1254 if (dev->phydev->speed == SPEED_100)
260055bb
PS		 1255 pscr |= SET_MII_SPEED_TO_100;
1256 else
1257 pscr &= ~SET_MII_SPEED_TO_100;
1258
1e8a655d 1259 if (dev->phydev->duplex == DUPLEX_FULL)
260055bb
PS		 1260 pscr |= SET_FULL_DUPLEX_MODE;
1261 else
1262 pscr &= ~SET_FULL_DUPLEX_MODE;
1263
1264out_write:
1265 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1266}
1267
8fd89211
LB		 1268/* statistics ***************************************************************/
1269static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1270{
1271 struct mv643xx_eth_private *mp = netdev_priv(dev);
1272 struct net_device_stats *stats = &dev->stats;
1273 unsigned long tx_packets = 0;
1274 unsigned long tx_bytes = 0;
1275 unsigned long tx_dropped = 0;
1276 int i;
1277
1278 for (i = 0; i < mp->txq_count; i++) {
1279 struct tx_queue *txq = mp->txq + i;
1280
1281 tx_packets += txq->tx_packets;
1282 tx_bytes += txq->tx_bytes;
1283 tx_dropped += txq->tx_dropped;
1284 }
1285
1286 stats->tx_packets = tx_packets;
1287 stats->tx_bytes = tx_bytes;
1288 stats->tx_dropped = tx_dropped;
1289
1290 return stats;
1291}
1292
fc32b0e2 1293static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1294{
fc32b0e2 1295 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1296}
1297
fc32b0e2 1298static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1299{
fc32b0e2
LB		 1300 int i;
1301
1302 for (i = 0; i < 0x80; i += 4)
1303 mib_read(mp, i);
302476c9
PZ		 1304
1305 /* Clear non MIB hw counters also */
1306 rdlp(mp, RX_DISCARD_FRAME_CNT);
1307 rdlp(mp, RX_OVERRUN_FRAME_CNT);
c9df406f 1308}
d0412d96 1309
fc32b0e2 1310static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1311{
e5371493 1312 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1313
57e8f26a 1314 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1315 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1316 p->bad_octets_received += mib_read(mp, 0x08);
1317 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1318 p->good_frames_received += mib_read(mp, 0x10);
1319 p->bad_frames_received += mib_read(mp, 0x14);
1320 p->broadcast_frames_received += mib_read(mp, 0x18);
1321 p->multicast_frames_received += mib_read(mp, 0x1c);
1322 p->frames_64_octets += mib_read(mp, 0x20);
1323 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1324 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1325 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1326 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1327 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1328 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1329 p->good_frames_sent += mib_read(mp, 0x40);
1330 p->excessive_collision += mib_read(mp, 0x44);
1331 p->multicast_frames_sent += mib_read(mp, 0x48);
1332 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1333 p->unrec_mac_control_received += mib_read(mp, 0x50);
1334 p->fc_sent += mib_read(mp, 0x54);
1335 p->good_fc_received += mib_read(mp, 0x58);
1336 p->bad_fc_received += mib_read(mp, 0x5c);
1337 p->undersize_received += mib_read(mp, 0x60);
1338 p->fragments_received += mib_read(mp, 0x64);
1339 p->oversize_received += mib_read(mp, 0x68);
1340 p->jabber_received += mib_read(mp, 0x6c);
1341 p->mac_receive_error += mib_read(mp, 0x70);
1342 p->bad_crc_event += mib_read(mp, 0x74);
1343 p->collision += mib_read(mp, 0x78);
1344 p->late_collision += mib_read(mp, 0x7c);
302476c9
PZ		 1345 /* Non MIB hardware counters */
1346 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1347 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
57e8f26a 1348 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1349}
1350
1351static void mib_counters_timer_wrapper(unsigned long _mp)
1352{
1353 struct mv643xx_eth_private *mp = (void *)_mp;
4ff3495a 1354 mib_counters_update(mp);
041b4ddb 1355 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
d0412d96
JC		 1356}
1357
c9df406f 1358
3e508034
LB		 1359/* interrupt coalescing *****************************************************/
1360/*
1361 * Hardware coalescing parameters are set in units of 64 t_clk
1362 * cycles. I.e.:
1363 *
1364 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1365 *
1366 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1367 *
1368 * In the ->set*() methods, we round the computed register value
1369 * to the nearest integer.
1370 */
1371static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1372{
1373 u32 val = rdlp(mp, SDMA_CONFIG);
1374 u64 temp;
1375
1376 if (mp->shared->extended_rx_coal_limit)
1377 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1378 else
1379 temp = (val & 0x003fff00) >> 8;
1380
1381 temp *= 64000000;
b9b84fc0 1382 temp += mp->t_clk / 2;
452503eb 1383 do_div(temp, mp->t_clk);
3e508034
LB		 1384
1385 return (unsigned int)temp;
1386}
1387
1388static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1389{
1390 u64 temp;
1391 u32 val;
1392
452503eb 1393 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1394 temp += 31999999;
1395 do_div(temp, 64000000);
1396
1397 val = rdlp(mp, SDMA_CONFIG);
1398 if (mp->shared->extended_rx_coal_limit) {
1399 if (temp > 0xffff)
1400 temp = 0xffff;
1401 val &= ~0x023fff80;
1402 val |= (temp & 0x8000) << 10;
1403 val |= (temp & 0x7fff) << 7;
1404 } else {
1405 if (temp > 0x3fff)
1406 temp = 0x3fff;
1407 val &= ~0x003fff00;
1408 val |= (temp & 0x3fff) << 8;
1409 }
1410 wrlp(mp, SDMA_CONFIG, val);
1411}
1412
1413static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1414{
1415 u64 temp;
1416
1417 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1418 temp *= 64000000;
b9b84fc0 1419 temp += mp->t_clk / 2;
452503eb 1420 do_div(temp, mp->t_clk);
3e508034
LB		 1421
1422 return (unsigned int)temp;
1423}
1424
1425static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1426{
1427 u64 temp;
1428
452503eb 1429 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1430 temp += 31999999;
1431 do_div(temp, 64000000);
1432
1433 if (temp > 0x3fff)
1434 temp = 0x3fff;
1435
1436 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1437}
1438
1439
c9df406f 1440/* ethtool ******************************************************************/
e5371493 1441struct mv643xx_eth_stats {
c9df406f
LB		 1442 char stat_string[ETH_GSTRING_LEN];
1443 int sizeof_stat;
16820054
LB		 1444 int netdev_off;
1445 int mp_off;
c9df406f
LB		 1446};
1447
16820054
LB		 1448#define SSTAT(m) \
1449 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1450 offsetof(struct net_device, stats.m), -1 }
1451
1452#define MIBSTAT(m) \
1453 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1454 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1455
1456static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1457 SSTAT(rx_packets),
1458 SSTAT(tx_packets),
1459 SSTAT(rx_bytes),
1460 SSTAT(tx_bytes),
1461 SSTAT(rx_errors),
1462 SSTAT(tx_errors),
1463 SSTAT(rx_dropped),
1464 SSTAT(tx_dropped),
1465 MIBSTAT(good_octets_received),
1466 MIBSTAT(bad_octets_received),
1467 MIBSTAT(internal_mac_transmit_err),
1468 MIBSTAT(good_frames_received),
1469 MIBSTAT(bad_frames_received),
1470 MIBSTAT(broadcast_frames_received),
1471 MIBSTAT(multicast_frames_received),
1472 MIBSTAT(frames_64_octets),
1473 MIBSTAT(frames_65_to_127_octets),
1474 MIBSTAT(frames_128_to_255_octets),
1475 MIBSTAT(frames_256_to_511_octets),
1476 MIBSTAT(frames_512_to_1023_octets),
1477 MIBSTAT(frames_1024_to_max_octets),
1478 MIBSTAT(good_octets_sent),
1479 MIBSTAT(good_frames_sent),
1480 MIBSTAT(excessive_collision),
1481 MIBSTAT(multicast_frames_sent),
1482 MIBSTAT(broadcast_frames_sent),
1483 MIBSTAT(unrec_mac_control_received),
1484 MIBSTAT(fc_sent),
1485 MIBSTAT(good_fc_received),
1486 MIBSTAT(bad_fc_received),
1487 MIBSTAT(undersize_received),
1488 MIBSTAT(fragments_received),
1489 MIBSTAT(oversize_received),
1490 MIBSTAT(jabber_received),
1491 MIBSTAT(mac_receive_error),
1492 MIBSTAT(bad_crc_event),
1493 MIBSTAT(collision),
1494 MIBSTAT(late_collision),
302476c9
PZ		 1495 MIBSTAT(rx_discard),
1496 MIBSTAT(rx_overrun),
c9df406f
LB		 1497};
1498
10a9948d 1499static int
a54e1612
PR		 1500mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1501 struct ethtool_link_ksettings *cmd)
d0412d96 1502{
1e8a655d 1503 struct net_device *dev = mp->dev;
a54e1612 1504 u32 supported, advertising;
d0412d96 1505
5514174f 1506 phy_ethtool_ksettings_get(dev->phydev, cmd);
d0412d96 1507
fc32b0e2
LB		 1508 /*
1509 * The MAC does not support 1000baseT_Half.
1510 */
a54e1612
PR		 1511 ethtool_convert_link_mode_to_legacy_u32(&supported,
1512 cmd->link_modes.supported);
1513 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1514 cmd->link_modes.advertising);
1515 supported &= ~SUPPORTED_1000baseT_Half;
1516 advertising &= ~ADVERTISED_1000baseT_Half;
1517 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1518 supported);
1519 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1520 advertising);
d0412d96 1521
5514174f 1522 return 0;
d0412d96
JC		 1523}
1524
10a9948d 1525static int
a54e1612
PR		 1526mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1527 struct ethtool_link_ksettings *cmd)
bedfe324 1528{
81600eea 1529 u32 port_status;
a54e1612 1530 u32 supported, advertising;
81600eea 1531
37a6084f 1532 port_status = rdlp(mp, PORT_STATUS);
81600eea 1533
a54e1612
PR		 1534 supported = SUPPORTED_MII;
1535 advertising = ADVERTISED_MII;
81600eea
LB		 1536 switch (port_status & PORT_SPEED_MASK) {
1537 case PORT_SPEED_10:
a54e1612 1538 cmd->base.speed = SPEED_10;
81600eea
LB		 1539 break;
1540 case PORT_SPEED_100:
a54e1612 1541 cmd->base.speed = SPEED_100;
81600eea
LB		 1542 break;
1543 case PORT_SPEED_1000:
a54e1612 1544 cmd->base.speed = SPEED_1000;
81600eea
LB		 1545 break;
1546 default:
a54e1612 1547 cmd->base.speed = -1;
81600eea
LB		 1548 break;
1549 }
a54e1612
PR		 1550 cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1551 DUPLEX_FULL : DUPLEX_HALF;
1552 cmd->base.port = PORT_MII;
1553 cmd->base.phy_address = 0;
1554 cmd->base.autoneg = AUTONEG_DISABLE;
1555
1556 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1557 supported);
1558 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1559 advertising);
bedfe324
LB		 1560
1561 return 0;
1562}
1563
3871c387
MS		 1564static void
1565mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1566{
3871c387
MS		 1567 wol->supported = 0;
1568 wol->wolopts = 0;
1e8a655d
PR		 1569 if (dev->phydev)
1570 phy_ethtool_get_wol(dev->phydev, wol);
3871c387
MS		 1571}
1572
1573static int
1574mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1575{
3871c387
MS		 1576 int err;
1577
1e8a655d 1578 if (!dev->phydev)
3871c387
MS		 1579 return -EOPNOTSUPP;
1580
1e8a655d 1581 err = phy_ethtool_set_wol(dev->phydev, wol);
3871c387
MS		 1582 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1583 * this debugging hint is useful to have.
1584 */
1585 if (err == -EOPNOTSUPP)
1586 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1587 return err;
1588}
1589
6bdf576e 1590static int
a54e1612
PR		 1591mv643xx_eth_get_link_ksettings(struct net_device *dev,
1592 struct ethtool_link_ksettings *cmd)
6bdf576e
LB		 1593{
1594 struct mv643xx_eth_private *mp = netdev_priv(dev);
1595
1e8a655d 1596 if (dev->phydev)
a54e1612 1597 return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
6bdf576e 1598 else
a54e1612 1599 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
6bdf576e
LB		 1600}
1601
10a9948d 1602static int
a54e1612
PR		 1603mv643xx_eth_set_link_ksettings(struct net_device *dev,
1604 const struct ethtool_link_ksettings *cmd)
1da177e4 1605{
a54e1612
PR		 1606 struct ethtool_link_ksettings c = *cmd;
1607 u32 advertising;
260055bb 1608 int ret;
ab4384a6 1609
1e8a655d 1610 if (!dev->phydev)
6bdf576e
LB		 1611 return -EINVAL;
1612
fc32b0e2
LB		 1613 /*
1614 * The MAC does not support 1000baseT_Half.
1615 */
a54e1612
PR		 1616 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1617 c.link_modes.advertising);
1618 advertising &= ~ADVERTISED_1000baseT_Half;
1619 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1620 advertising);
fc32b0e2 1621
a54e1612 1622 ret = phy_ethtool_ksettings_set(dev->phydev, &c);
260055bb 1623 if (!ret)
0a9e413b 1624 mv643xx_eth_adjust_link(dev);
260055bb 1625 return ret;
c9df406f 1626}
1da177e4 1627
fc32b0e2
LB		 1628static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1629 struct ethtool_drvinfo *drvinfo)
c9df406f 1630{
6f39da2c
AL		 1631 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1632 sizeof(drvinfo->driver));
68aad78c 1633 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
6f39da2c
AL		 1634 sizeof(drvinfo->version));
1635 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1636 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
c9df406f 1637}
1da177e4 1638
3e508034
LB		 1639static int
1640mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1641{
1642 struct mv643xx_eth_private *mp = netdev_priv(dev);
1643
1644 ec->rx_coalesce_usecs = get_rx_coal(mp);
1645 ec->tx_coalesce_usecs = get_tx_coal(mp);
1646
1647 return 0;
1648}
1649
1650static int
1651mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1652{
1653 struct mv643xx_eth_private *mp = netdev_priv(dev);
1654
1655 set_rx_coal(mp, ec->rx_coalesce_usecs);
1656 set_tx_coal(mp, ec->tx_coalesce_usecs);
1657
1658 return 0;
1659}
1660
e7d2f4db
LB		 1661static void
1662mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1663{
1664 struct mv643xx_eth_private *mp = netdev_priv(dev);
1665
1666 er->rx_max_pending = 4096;
1667 er->tx_max_pending = 4096;
e7d2f4db
LB		 1668
1669 er->rx_pending = mp->rx_ring_size;
1670 er->tx_pending = mp->tx_ring_size;
e7d2f4db
LB		 1671}
1672
1673static int
1674mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1675{
1676 struct mv643xx_eth_private *mp = netdev_priv(dev);
1677
1678 if (er->rx_mini_pending || er->rx_jumbo_pending)
1679 return -EINVAL;
1680
1681 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
ee9e4956
EG		 1682 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1683 MV643XX_MAX_SKB_DESCS * 2, 4096);
1684 if (mp->tx_ring_size != er->tx_pending)
1685 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1686 mp->tx_ring_size, er->tx_pending);
e7d2f4db
LB		 1687
1688 if (netif_running(dev)) {
1689 mv643xx_eth_stop(dev);
1690 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 1691 netdev_err(dev,
1692 "fatal error on re-opening device after ring param change\n");
e7d2f4db
LB		 1693 return -ENOMEM;
1694 }
1695 }
1696
1697 return 0;
1698}
1699
d888b373
LB		 1700
1701static int
c8f44aff 1702mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
d888b373
LB		 1703{
1704 struct mv643xx_eth_private *mp = netdev_priv(dev);
3ad9b358 1705 bool rx_csum = features & NETIF_F_RXCSUM;
d888b373
LB		 1706
1707 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1708
1709 return 0;
1710}
1711
fc32b0e2
LB		 1712static void mv643xx_eth_get_strings(struct net_device *dev,
1713 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1714{
1715 int i;
1da177e4 1716
fc32b0e2
LB		 1717 if (stringset == ETH_SS_STATS) {
1718 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1719 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1720 mv643xx_eth_stats[i].stat_string,
e5371493 1721 ETH_GSTRING_LEN);
c9df406f 1722 }
c9df406f
LB		 1723 }
1724}
1da177e4 1725
fc32b0e2
LB		 1726static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1727 struct ethtool_stats *stats,
1728 uint64_t *data)
c9df406f 1729{
b9873841 1730 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1731 int i;
1da177e4 1732
8fd89211 1733 mv643xx_eth_get_stats(dev);
fc32b0e2 1734 mib_counters_update(mp);
1da177e4 1735
16820054
LB		 1736 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1737 const struct mv643xx_eth_stats *stat;
1738 void *p;
1739
1740 stat = mv643xx_eth_stats + i;
1741
1742 if (stat->netdev_off >= 0)
1743 p = ((void *)mp->dev) + stat->netdev_off;
1744 else
1745 p = ((void *)mp) + stat->mp_off;
1746
1747 data[i] = (stat->sizeof_stat == 8) ?
1748 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1749 }
c9df406f 1750}
1da177e4 1751
fc32b0e2 1752static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1753{
fc32b0e2 1754 if (sset == ETH_SS_STATS)
16820054 1755 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1756
1757 return -EOPNOTSUPP;
c9df406f 1758}
1da177e4 1759
e5371493 1760static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2 1761 .get_drvinfo = mv643xx_eth_get_drvinfo,
fc5e353c 1762 .nway_reset = phy_ethtool_nway_reset,
ed4ba4b5 1763 .get_link = ethtool_op_get_link,
3e508034
LB		 1764 .get_coalesce = mv643xx_eth_get_coalesce,
1765 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1766 .get_ringparam = mv643xx_eth_get_ringparam,
1767 .set_ringparam = mv643xx_eth_set_ringparam,
fc32b0e2
LB		 1768 .get_strings = mv643xx_eth_get_strings,
1769 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1770 .get_sset_count = mv643xx_eth_get_sset_count,
ebad0a8d 1771 .get_ts_info = ethtool_op_get_ts_info,
3871c387
MS		 1772 .get_wol = mv643xx_eth_get_wol,
1773 .set_wol = mv643xx_eth_set_wol,
a54e1612
PR		 1774 .get_link_ksettings = mv643xx_eth_get_link_ksettings,
1775 .set_link_ksettings = mv643xx_eth_set_link_ksettings,
c9df406f 1776};
1da177e4 1777
bea3348e 1778
c9df406f 1779/* address handling *********************************************************/
5daffe94 1780static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1781{
66e63ffb
LB		 1782 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1783 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1784
5daffe94
LB		 1785 addr[0] = (mac_h >> 24) & 0xff;
1786 addr[1] = (mac_h >> 16) & 0xff;
1787 addr[2] = (mac_h >> 8) & 0xff;
1788 addr[3] = mac_h & 0xff;
1789 addr[4] = (mac_l >> 8) & 0xff;
1790 addr[5] = mac_l & 0xff;
c9df406f 1791}
1da177e4 1792
66e63ffb 1793static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1794{
66e63ffb
LB		 1795 wrlp(mp, MAC_ADDR_HIGH,
1796 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1797 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1798}
d0412d96 1799
66e63ffb 1800static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1801{
ccffad25 1802 struct netdev_hw_addr *ha;
66e63ffb 1803 u32 nibbles;
1da177e4 1804
66e63ffb
LB		 1805 if (dev->flags & IFF_PROMISC)
1806 return 0;
1da177e4 1807
66e63ffb 1808 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1809 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1810 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1811 return 0;
ccffad25 1812 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1813 return 0;
ff561eef 1814
ccffad25 1815 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1816 }
1da177e4 1817
66e63ffb 1818 return nibbles;
1da177e4
LT		 1819}
1820
66e63ffb 1821static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1822{
e5371493 1823 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1824 u32 port_config;
1825 u32 nibbles;
1826 int i;
1da177e4 1827
cc9754b3 1828 uc_addr_set(mp, dev->dev_addr);
1da177e4 1829
6877f54e
PS		 1830 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1831
66e63ffb
LB		 1832 nibbles = uc_addr_filter_mask(dev);
1833 if (!nibbles) {
1834 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1835 nibbles = 0xffff;
66e63ffb
LB		 1836 }
1837
1838 for (i = 0; i < 16; i += 4) {
1839 int off = UNICAST_TABLE(mp->port_num) + i;
1840 u32 v;
1841
1842 v = 0;
1843 if (nibbles & 1)
1844 v |= 0x00000001;
1845 if (nibbles & 2)
1846 v |= 0x00000100;
1847 if (nibbles & 4)
1848 v |= 0x00010000;
1849 if (nibbles & 8)
1850 v |= 0x01000000;
1851 nibbles >>= 4;
1852
1853 wrl(mp, off, v);
1854 }
1855
66e63ffb 1856 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1857}
1858
69876569
LB		 1859static int addr_crc(unsigned char *addr)
1860{
1861 int crc = 0;
1862 int i;
1863
1864 for (i = 0; i < 6; i++) {
1865 int j;
1866
1867 crc = (crc ^ addr[i]) << 8;
1868 for (j = 7; j >= 0; j--) {
1869 if (crc & (0x100 << j))
1870 crc ^= 0x107 << j;
1871 }
1872 }
1873
1874 return crc;
1875}
1876
66e63ffb 1877static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1878{
fc32b0e2 1879 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1880 u32 *mc_spec;
1881 u32 *mc_other;
22bedad3 1882 struct netdev_hw_addr *ha;
fc32b0e2 1883 int i;
c8aaea25 1884
8b711d6d
JP		 1885 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1886 goto promiscuous;
c8aaea25 1887
8b711d6d
JP		 1888 /* Allocate both mc_spec and mc_other tables */
1889 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1890 if (!mc_spec)
1891 goto promiscuous;
1892 mc_other = &mc_spec[64];
66e63ffb 1893
22bedad3
JP		 1894 netdev_for_each_mc_addr(ha, dev) {
1895 u8 *a = ha->addr;
66e63ffb 1896 u32 *table;
8b711d6d 1897 u8 entry;
1da177e4 1898
fc32b0e2 1899 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1900 table = mc_spec;
1901 entry = a[5];
fc32b0e2 1902 } else {
66e63ffb
LB		 1903 table = mc_other;
1904 entry = addr_crc(a);
fc32b0e2 1905 }
66e63ffb 1906
2b448334 1907 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1908 }
66e63ffb 1909
8b711d6d
JP		 1910 for (i = 0; i < 64; i++) {
1911 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1912 mc_spec[i]);
1913 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1914 mc_other[i]);
66e63ffb
LB		 1915 }
1916
1917 kfree(mc_spec);
8b711d6d
JP		 1918 return;
1919
1920promiscuous:
1921 for (i = 0; i < 64; i++) {
1922 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1923 0x01010101u);
1924 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1925 0x01010101u);
1926 }
66e63ffb
LB		 1927}
1928
1929static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1930{
1931 mv643xx_eth_program_unicast_filter(dev);
1932 mv643xx_eth_program_multicast_filter(dev);
1933}
1934
1935static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1936{
1937 struct sockaddr *sa = addr;
1938
a29ec08a 1939 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 1940 return -EADDRNOTAVAIL;
a29ec08a 1941
66e63ffb
LB		 1942 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1943
1944 netif_addr_lock_bh(dev);
1945 mv643xx_eth_program_unicast_filter(dev);
1946 netif_addr_unlock_bh(dev);
1947
1948 return 0;
c9df406f 1949}
c8aaea25 1950
c8aaea25 1951
c9df406f 1952/* rx/tx queue initialisation ***********************************************/
64da80a2 1953static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1954{
64da80a2 1955 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1956 struct rx_desc *rx_desc;
1957 int size;
c9df406f
LB		 1958 int i;
1959
64da80a2
LB		 1960 rxq->index = index;
1961
e7d2f4db 1962 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1963
1964 rxq->rx_desc_count = 0;
1965 rxq->rx_curr_desc = 0;
1966 rxq->rx_used_desc = 0;
1967
1968 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1969
f7981c1c 1970 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1971 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1972 mp->rx_desc_sram_size);
1973 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1974 } else {
eb0519b5
GP		 1975 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1976 size, &rxq->rx_desc_dma,
1977 GFP_KERNEL);
f7ea3337
PJ		 1978 }
1979
8a578111 1980 if (rxq->rx_desc_area == NULL) {
7542db8b 1981 netdev_err(mp->dev,
8a578111
LB		 1982 "can't allocate rx ring (%d bytes)\n", size);
1983 goto out;
1984 }
1985 memset(rxq->rx_desc_area, 0, size);
1da177e4 1986
8a578111 1987 rxq->rx_desc_area_size = size;
9fa8e980 1988 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
b2adaca9
JP		 1989 GFP_KERNEL);
1990 if (rxq->rx_skb == NULL)
8a578111 1991 goto out_free;
8a578111 1992
64699336 1993 rx_desc = rxq->rx_desc_area;
8a578111 1994 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1995 int nexti;
1996
1997 nexti = i + 1;
1998 if (nexti == rxq->rx_ring_size)
1999 nexti = 0;
2000
8a578111
LB		 2001 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
2002 nexti * sizeof(struct rx_desc);
2003 }
2004
8a578111
LB		 2005 return 0;
2006
2007
2008out_free:
f7981c1c 2009 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 2010 iounmap(rxq->rx_desc_area);
2011 else
eb0519b5 2012 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 2013 rxq->rx_desc_area,
2014 rxq->rx_desc_dma);
2015
2016out:
2017 return -ENOMEM;
c9df406f 2018}
c8aaea25 2019
8a578111 2020static void rxq_deinit(struct rx_queue *rxq)
c9df406f 2021{
8a578111
LB		 2022 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2023 int i;
2024
2025 rxq_disable(rxq);
c8aaea25 2026
8a578111
LB		 2027 for (i = 0; i < rxq->rx_ring_size; i++) {
2028 if (rxq->rx_skb[i]) {
2029 dev_kfree_skb(rxq->rx_skb[i]);
2030 rxq->rx_desc_count--;
1da177e4 2031 }
c8aaea25 2032 }
1da177e4 2033
8a578111 2034 if (rxq->rx_desc_count) {
7542db8b 2035 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
8a578111
LB		 2036 rxq->rx_desc_count);
2037 }
2038
f7981c1c 2039 if (rxq->index == 0 &&
64da80a2 2040 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 2041 iounmap(rxq->rx_desc_area);
c9df406f 2042 else
eb0519b5 2043 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 2044 rxq->rx_desc_area, rxq->rx_desc_dma);
2045
2046 kfree(rxq->rx_skb);
c9df406f 2047}
1da177e4 2048
3d6b35bc 2049static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 2050{
3d6b35bc 2051 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 2052 struct tx_desc *tx_desc;
2053 int size;
9e911414 2054 int ret;
c9df406f 2055 int i;
1da177e4 2056
3d6b35bc
LB		 2057 txq->index = index;
2058
e7d2f4db 2059 txq->tx_ring_size = mp->tx_ring_size;
13d64285 2060
ee9e4956
EG		 2061 /* A queue must always have room for at least one skb.
2062 * Therefore, stop the queue when the free entries reaches
2063 * the maximum number of descriptors per skb.
2064 */
2065 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2066 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2067
13d64285
LB		 2068 txq->tx_desc_count = 0;
2069 txq->tx_curr_desc = 0;
2070 txq->tx_used_desc = 0;
2071
2072 size = txq->tx_ring_size * sizeof(struct tx_desc);
2073
f7981c1c 2074 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 2075 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2076 mp->tx_desc_sram_size);
2077 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2078 } else {
eb0519b5
GP		 2079 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2080 size, &txq->tx_desc_dma,
2081 GFP_KERNEL);
13d64285
LB		 2082 }
2083
2084 if (txq->tx_desc_area == NULL) {
7542db8b 2085 netdev_err(mp->dev,
13d64285 2086 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 2087 return -ENOMEM;
c9df406f 2088 }
13d64285
LB		 2089 memset(txq->tx_desc_area, 0, size);
2090
2091 txq->tx_desc_area_size = size;
13d64285 2092
64699336 2093 tx_desc = txq->tx_desc_area;
13d64285 2094 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 2095 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 2096 int nexti;
2097
2098 nexti = i + 1;
2099 if (nexti == txq->tx_ring_size)
2100 nexti = 0;
6b368f68
LB		 2101
2102 txd->cmd_sts = 0;
2103 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2104 nexti * sizeof(struct tx_desc);
2105 }
2106
9e911414
EG		 2107 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2108 GFP_KERNEL);
2109 if (!txq->tx_desc_mapping) {
2110 ret = -ENOMEM;
2111 goto err_free_desc_area;
2112 }
2113
3ae8f4e0
EG		 2114 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2115 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2116 txq->tx_ring_size * TSO_HEADER_SIZE,
2117 &txq->tso_hdrs_dma, GFP_KERNEL);
2118 if (txq->tso_hdrs == NULL) {
9e911414
EG		 2119 ret = -ENOMEM;
2120 goto err_free_desc_mapping;
3ae8f4e0 2121 }
99ab08e0 2122 skb_queue_head_init(&txq->tx_skb);
c9df406f 2123
99ab08e0 2124 return 0;
9e911414
EG		 2125
2126err_free_desc_mapping:
2127 kfree(txq->tx_desc_mapping);
2128err_free_desc_area:
2129 if (index == 0 && size <= mp->tx_desc_sram_size)
2130 iounmap(txq->tx_desc_area);
2131 else
2132 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2133 txq->tx_desc_area, txq->tx_desc_dma);
2134 return ret;
c8aaea25 2135}
1da177e4 2136
13d64285 2137static void txq_deinit(struct tx_queue *txq)
c9df406f 2138{
13d64285 2139 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2140
13d64285 2141 txq_disable(txq);
1fa38c58 2142 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2143
13d64285 2144 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2145
f7981c1c 2146 if (txq->index == 0 &&
3d6b35bc 2147 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2148 iounmap(txq->tx_desc_area);
c9df406f 2149 else
eb0519b5 2150 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2151 txq->tx_desc_area, txq->tx_desc_dma);
9e911414
EG		 2152 kfree(txq->tx_desc_mapping);
2153
3ae8f4e0
EG		 2154 if (txq->tso_hdrs)
2155 dma_free_coherent(mp->dev->dev.parent,
2156 txq->tx_ring_size * TSO_HEADER_SIZE,
2157 txq->tso_hdrs, txq->tso_hdrs_dma);
c9df406f 2158}
1da177e4 2159
1da177e4 2160
c9df406f 2161/* netdev ops and related ***************************************************/
1fa38c58
LB		 2162static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2163{
2164 u32 int_cause;
2165 u32 int_cause_ext;
2166
e0ca8410 2167 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2168 if (int_cause == 0)
2169 return 0;
2170
2171 int_cause_ext = 0;
e0ca8410
SB		 2172 if (int_cause & INT_EXT) {
2173 int_cause &= ~INT_EXT;
37a6084f 2174 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2175 }
1fa38c58 2176
1fa38c58 2177 if (int_cause) {
37a6084f 2178 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2179 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2180 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2181 mp->work_rx |= (int_cause & INT_RX) >> 2;
2182 }
2183
2184 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2185 if (int_cause_ext) {
37a6084f 2186 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2187 if (int_cause_ext & INT_EXT_LINK_PHY)
2188 mp->work_link = 1;
2189 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2190 }
2191
2192 return 1;
2193}
2194
2195static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2196{
2197 struct net_device *dev = (struct net_device *)dev_id;
2198 struct mv643xx_eth_private *mp = netdev_priv(dev);
2199
2200 if (unlikely(!mv643xx_eth_collect_events(mp)))
2201 return IRQ_NONE;
2202
37a6084f 2203 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2204 napi_schedule(&mp->napi);
2205
2206 return IRQ_HANDLED;
2207}
2208
2f7eb47a
LB		 2209static void handle_link_event(struct mv643xx_eth_private *mp)
2210{
2211 struct net_device *dev = mp->dev;
2212 u32 port_status;
2213 int speed;
2214 int duplex;
2215 int fc;
2216
37a6084f 2217 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2218 if (!(port_status & LINK_UP)) {
2219 if (netif_carrier_ok(dev)) {
2220 int i;
2221
7542db8b 2222 netdev_info(dev, "link down\n");
2f7eb47a
LB		 2223
2224 netif_carrier_off(dev);
2f7eb47a 2225
f7981c1c 2226 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2227 struct tx_queue *txq = mp->txq + i;
2228
1fa38c58 2229 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2230 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2231 }
2232 }
2233 return;
2234 }
2235
2236 switch (port_status & PORT_SPEED_MASK) {
2237 case PORT_SPEED_10:
2238 speed = 10;
2239 break;
2240 case PORT_SPEED_100:
2241 speed = 100;
2242 break;
2243 case PORT_SPEED_1000:
2244 speed = 1000;
2245 break;
2246 default:
2247 speed = -1;
2248 break;
2249 }
2250 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2251 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2252
7542db8b
JP		 2253 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2254 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2f7eb47a 2255
4fdeca3f 2256 if (!netif_carrier_ok(dev))
2f7eb47a 2257 netif_carrier_on(dev);
2f7eb47a
LB		 2258}
2259
1fa38c58 2260static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2261{
1fa38c58
LB		 2262 struct mv643xx_eth_private *mp;
2263 int work_done;
ce4e2e45 2264
1fa38c58 2265 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2266
1319ebad
LB		 2267 if (unlikely(mp->oom)) {
2268 mp->oom = 0;
2269 del_timer(&mp->rx_oom);
2270 }
1da177e4 2271
1fa38c58
LB		 2272 work_done = 0;
2273 while (work_done < budget) {
2274 u8 queue_mask;
2275 int queue;
2276 int work_tbd;
2277
2278 if (mp->work_link) {
2279 mp->work_link = 0;
2280 handle_link_event(mp);
26ef1f17 2281 work_done++;
1fa38c58
LB		 2282 continue;
2283 }
1da177e4 2284
1319ebad
LB		 2285 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2286 if (likely(!mp->oom))
2287 queue_mask |= mp->work_rx_refill;
2288
1fa38c58
LB		 2289 if (!queue_mask) {
2290 if (mv643xx_eth_collect_events(mp))
2291 continue;
2292 break;
2293 }
1da177e4 2294
1fa38c58
LB		 2295 queue = fls(queue_mask) - 1;
2296 queue_mask = 1 << queue;
2297
2298 work_tbd = budget - work_done;
2299 if (work_tbd > 16)
2300 work_tbd = 16;
2301
2302 if (mp->work_tx_end & queue_mask) {
2303 txq_kick(mp->txq + queue);
2304 } else if (mp->work_tx & queue_mask) {
2305 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2306 txq_maybe_wake(mp->txq + queue);
2307 } else if (mp->work_rx & queue_mask) {
2308 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2309 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2310 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2311 } else {
2312 BUG();
2313 }
84dd619e 2314 }
fc32b0e2 2315
1fa38c58 2316 if (work_done < budget) {
1319ebad 2317 if (mp->oom)
1fa38c58 2318 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
6ad20165 2319 napi_complete_done(napi, work_done);
e0ca8410 2320 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2321 }
3d6b35bc 2322
1fa38c58
LB		 2323 return work_done;
2324}
8fa89bf5 2325
1fa38c58
LB		 2326static inline void oom_timer_wrapper(unsigned long data)
2327{
2328 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2329
1fa38c58 2330 napi_schedule(&mp->napi);
1da177e4
LT		 2331}
2332
fc32b0e2 2333static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2334{
1e8a655d 2335 struct net_device *dev = mp->dev;
d0412d96 2336 u32 pscr;
8a578111 2337 int i;
1da177e4 2338
bedfe324
LB		 2339 /*
2340 * Perform PHY reset, if there is a PHY.
2341 */
1e8a655d 2342 if (dev->phydev) {
a54e1612 2343 struct ethtool_link_ksettings cmd;
bedfe324 2344
a54e1612 2345 mv643xx_eth_get_link_ksettings(dev, &cmd);
1e8a655d 2346 phy_init_hw(dev->phydev);
a54e1612
PR		 2347 mv643xx_eth_set_link_ksettings(
2348 dev, (const struct ethtool_link_ksettings *)&cmd);
1e8a655d 2349 phy_start(dev->phydev);
bedfe324 2350 }
1da177e4 2351
81600eea
LB		 2352 /*
2353 * Configure basic link parameters.
2354 */
37a6084f 2355 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2356
2357 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2358 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2359
2360 pscr |= DO_NOT_FORCE_LINK_FAIL;
1e8a655d 2361 if (!dev->phydev)
81600eea 2362 pscr |= FORCE_LINK_PASS;
37a6084f 2363 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2364
13d64285
LB		 2365 /*
2366 * Configure TX path and queues.
2367 */
89df5fdc 2368 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2369 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2370 struct tx_queue *txq = mp->txq + i;
13d64285 2371
6b368f68 2372 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2373 txq_set_rate(txq, 1000000000, 16777216);
2374 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2375 }
2376
d9a073ea
LB		 2377 /*
2378 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2379 * frames to RX queue #0, and include the pseudo-header when
2380 * calculating receive checksums.
d9a073ea 2381 */
e138f96b 2382 mv643xx_eth_set_features(mp->dev, mp->dev->features);
01999873 2383
376489a2
LB		 2384 /*
2385 * Treat BPDUs as normal multicasts, and disable partition mode.
2386 */
37a6084f 2387 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2388
5a893922
LB		 2389 /*
2390 * Add configured unicast addresses to address filter table.
2391 */
2392 mv643xx_eth_program_unicast_filter(mp->dev);
2393
8a578111 2394 /*
64da80a2 2395 * Enable the receive queues.
8a578111 2396 */
f7981c1c 2397 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2398 struct rx_queue *rxq = mp->rxq + i;
8a578111 2399 u32 addr;
1da177e4 2400
8a578111
LB		 2401 addr = (u32)rxq->rx_desc_dma;
2402 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2403 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2404
8a578111
LB		 2405 rxq_enable(rxq);
2406 }
1da177e4
LT		 2407}
2408
2bcb4b0f
LB		 2409static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2410{
2411 int skb_size;
2412
2413 /*
2414 * Reserve 2+14 bytes for an ethernet header (the hardware
2415 * automatically prepends 2 bytes of dummy data to each
2416 * received packet), 16 bytes for up to four VLAN tags, and
2417 * 4 bytes for the trailing FCS -- 36 bytes total.
2418 */
2419 skb_size = mp->dev->mtu + 36;
2420
2421 /*
2422 * Make sure that the skb size is a multiple of 8 bytes, as
2423 * the lower three bits of the receive descriptor's buffer
2424 * size field are ignored by the hardware.
2425 */
2426 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2427
2428 /*
2429 * If NET_SKB_PAD is smaller than a cache line,
2430 * netdev_alloc_skb() will cause skb->data to be misaligned
2431 * to a cache line boundary. If this is the case, include
2432 * some extra space to allow re-aligning the data area.
2433 */
2434 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2435}
2436
c9df406f 2437static int mv643xx_eth_open(struct net_device *dev)
16e03018 2438{
e5371493 2439 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2440 int err;
64da80a2 2441 int i;
16e03018 2442
37a6084f
LB		 2443 wrlp(mp, INT_CAUSE, 0);
2444 wrlp(mp, INT_CAUSE_EXT, 0);
2445 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2446
fc32b0e2 2447 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2448 IRQF_SHARED, dev->name, dev);
c9df406f 2449 if (err) {
7542db8b 2450 netdev_err(dev, "can't assign irq\n");
c9df406f 2451 return -EAGAIN;
16e03018
DF		 2452 }
2453
2bcb4b0f
LB		 2454 mv643xx_eth_recalc_skb_size(mp);
2455
2257e05c
LB		 2456 napi_enable(&mp->napi);
2457
e0ca8410
SB		 2458 mp->int_mask = INT_EXT;
2459
f7981c1c 2460 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2461 err = rxq_init(mp, i);
2462 if (err) {
2463 while (--i >= 0)
f7981c1c 2464 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2465 goto out;
2466 }
2467
1fa38c58 2468 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2469 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2470 }
2471
1319ebad 2472 if (mp->oom) {
2257e05c
LB		 2473 mp->rx_oom.expires = jiffies + (HZ / 10);
2474 add_timer(&mp->rx_oom);
64da80a2 2475 }
8a578111 2476
f7981c1c 2477 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2478 err = txq_init(mp, i);
2479 if (err) {
2480 while (--i >= 0)
f7981c1c 2481 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2482 goto out_free;
2483 }
e0ca8410 2484 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2485 }
16e03018 2486
f564412c 2487 add_timer(&mp->mib_counters_timer);
fc32b0e2 2488 port_start(mp);
16e03018 2489
37a6084f 2490 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2491 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2492
c9df406f
LB		 2493 return 0;
2494
13d64285 2495
fc32b0e2 2496out_free:
f7981c1c
LB		 2497 for (i = 0; i < mp->rxq_count; i++)
2498 rxq_deinit(mp->rxq + i);
fc32b0e2 2499out:
c9df406f
LB		 2500 free_irq(dev->irq, dev);
2501
2502 return err;
16e03018
DF		 2503}
2504
e5371493 2505static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2506{
fc32b0e2 2507 unsigned int data;
64da80a2 2508 int i;
1da177e4 2509
f7981c1c
LB		 2510 for (i = 0; i < mp->rxq_count; i++)
2511 rxq_disable(mp->rxq + i);
2512 for (i = 0; i < mp->txq_count; i++)
2513 txq_disable(mp->txq + i);
ae9ae064
LB		 2514
2515 while (1) {
37a6084f 2516 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2517
2518 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2519 break;
13d64285 2520 udelay(10);
ae9ae064 2521 }
1da177e4 2522
c9df406f 2523 /* Reset the Enable bit in the Configuration Register */
37a6084f 2524 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2525 data &= ~(SERIAL_PORT_ENABLE |
2526 DO_NOT_FORCE_LINK_FAIL |
2527 FORCE_LINK_PASS);
37a6084f 2528 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2529}
2530
c9df406f 2531static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2532{
e5371493 2533 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2534 int i;
1da177e4 2535
fe65e704 2536 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2537 wrlp(mp, INT_MASK, 0x00000000);
2538 rdlp(mp, INT_MASK);
1da177e4 2539
c9df406f 2540 napi_disable(&mp->napi);
78fff83b 2541
2257e05c
LB		 2542 del_timer_sync(&mp->rx_oom);
2543
c9df406f 2544 netif_carrier_off(dev);
1e8a655d
PR		 2545 if (dev->phydev)
2546 phy_stop(dev->phydev);
fc32b0e2
LB		 2547 free_irq(dev->irq, dev);
2548
cc9754b3 2549 port_reset(mp);
8fd89211 2550 mv643xx_eth_get_stats(dev);
fc32b0e2 2551 mib_counters_update(mp);
57e8f26a 2552 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2553
f7981c1c
LB		 2554 for (i = 0; i < mp->rxq_count; i++)
2555 rxq_deinit(mp->rxq + i);
2556 for (i = 0; i < mp->txq_count; i++)
2557 txq_deinit(mp->txq + i);
1da177e4 2558
c9df406f 2559 return 0;
1da177e4
LT		 2560}
2561
fc32b0e2 2562static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2563{
260055bb 2564 int ret;
1da177e4 2565
1e8a655d 2566 if (!dev->phydev)
260055bb 2567 return -ENOTSUPP;
bedfe324 2568
1e8a655d 2569 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
260055bb 2570 if (!ret)
0a9e413b 2571 mv643xx_eth_adjust_link(dev);
260055bb 2572 return ret;
1da177e4
LT		 2573}
2574
c9df406f 2575static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2576{
89df5fdc
LB		 2577 struct mv643xx_eth_private *mp = netdev_priv(dev);
2578
c9df406f 2579 dev->mtu = new_mtu;
2bcb4b0f 2580 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2581 tx_set_rate(mp, 1000000000, 16777216);
2582
c9df406f
LB		 2583 if (!netif_running(dev))
2584 return 0;
1da177e4 2585
c9df406f
LB		 2586 /*
2587 * Stop and then re-open the interface. This will allocate RX
2588 * skbs of the new MTU.
2589 * There is a possible danger that the open will not succeed,
fc32b0e2 2590 * due to memory being full.
c9df406f
LB		 2591 */
2592 mv643xx_eth_stop(dev);
2593 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 2594 netdev_err(dev,
2595 "fatal error on re-opening device after MTU change\n");
c9df406f
LB		 2596 }
2597
2598 return 0;
1da177e4
LT		 2599}
2600
fc32b0e2 2601static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2602{
fc32b0e2 2603 struct mv643xx_eth_private *mp;
1da177e4 2604
fc32b0e2
LB		 2605 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2606 if (netif_running(mp->dev)) {
e5ef1de1 2607 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2608 port_reset(mp);
2609 port_start(mp);
e5ef1de1 2610 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2611 }
c9df406f
LB		 2612}
2613
c9df406f 2614static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2615{
e5371493 2616 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2617
7542db8b 2618 netdev_info(dev, "tx timeout\n");
d0412d96 2619
c9df406f 2620 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2621}
2622
c9df406f 2623#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2624static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2625{
fc32b0e2 2626 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2627
37a6084f
LB		 2628 wrlp(mp, INT_MASK, 0x00000000);
2629 rdlp(mp, INT_MASK);
c9df406f 2630
fc32b0e2 2631 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2632
e0ca8410 2633 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2634}
c9df406f 2635#endif
9f8dd319 2636
9f8dd319 2637
c9df406f 2638/* platform glue ************************************************************/
e5371493
LB		 2639static void
2640mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
63a9332b 2641 const struct mbus_dram_target_info *dram)
c9df406f 2642{
cc9754b3 2643 void __iomem *base = msp->base;
c9df406f
LB		 2644 u32 win_enable;
2645 u32 win_protect;
2646 int i;
9f8dd319 2647
c9df406f
LB		 2648 for (i = 0; i < 6; i++) {
2649 writel(0, base + WINDOW_BASE(i));
2650 writel(0, base + WINDOW_SIZE(i));
2651 if (i < 4)
2652 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2653 }
2654
c9df406f
LB		 2655 win_enable = 0x3f;
2656 win_protect = 0;
2657
2658 for (i = 0; i < dram->num_cs; i++) {
63a9332b 2659 const struct mbus_dram_window *cs = dram->cs + i;
c9df406f
LB		 2660
2661 writel((cs->base & 0xffff0000) |
2662 (cs->mbus_attr << 8) |
2663 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2664 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2665
2666 win_enable &= ~(1 << i);
2667 win_protect |= 3 << (2 * i);
2668 }
2669
2670 writel(win_enable, base + WINDOW_BAR_ENABLE);
2671 msp->win_protect = win_protect;
9f8dd319
DF		 2672}
2673
773fc3ee
LB		 2674static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2675{
2676 /*
2677 * Check whether we have a 14-bit coal limit field in bits
2678 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2679 * SDMA config register.
2680 */
37a6084f
LB		 2681 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2682 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2683 msp->extended_rx_coal_limit = 1;
2684 else
2685 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2686
2687 /*
457b1d5a
LB		 2688 * Check whether the MAC supports TX rate control, and if
2689 * yes, whether its associated registers are in the old or
2690 * the new place.
1e881592 2691 */
37a6084f
LB		 2692 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2693 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2694 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2695 } else {
37a6084f
LB		 2696 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2697 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2698 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2699 else
2700 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2701 }
773fc3ee
LB		 2702}
2703
76723bca
SH		 2704#if defined(CONFIG_OF)
2705static const struct of_device_id mv643xx_eth_shared_ids[] = {
2706 { .compatible = "marvell,orion-eth", },
2707 { .compatible = "marvell,kirkwood-eth", },
2708 { }
2709};
2710MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2711#endif
2712
3e3397e7 2713#if defined(CONFIG_OF_IRQ) && !defined(CONFIG_MV64X60)
76723bca
SH		 2714#define mv643xx_eth_property(_np, _name, _v) \
2715 do { \
2716 u32 tmp; \
2717 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2718 _v = tmp; \
2719 } while (0)
2720
2721static struct platform_device *port_platdev[3];
2722
2723static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2724 struct device_node *pnp)
2725{
2726 struct platform_device *ppdev;
2727 struct mv643xx_eth_platform_data ppd;
2728 struct resource res;
2729 const char *mac_addr;
2730 int ret;
785bf6f7 2731 int dev_num = 0;
76723bca
SH		 2732
2733 memset(&ppd, 0, sizeof(ppd));
2734 ppd.shared = pdev;
2735
2736 memset(&res, 0, sizeof(res));
cfbcb61f 2737 if (of_irq_to_resource(pnp, 0, &res) <= 0) {
76723bca
SH		 2738 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2739 return -EINVAL;
2740 }
2741
2742 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2743 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2744 return -EINVAL;
2745 }
2746
2747 if (ppd.port_number >= 3) {
2748 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2749 return -EINVAL;
2750 }
2751
785bf6f7
JG		 2752 while (dev_num < 3 && port_platdev[dev_num])
2753 dev_num++;
2754
2755 if (dev_num == 3) {
2756 dev_err(&pdev->dev, "too many ports registered\n");
2757 return -EINVAL;
2758 }
2759
76723bca
SH		 2760 mac_addr = of_get_mac_address(pnp);
2761 if (mac_addr)
d458cdf7 2762 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
76723bca
SH		 2763
2764 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2765 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2766 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2767 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2768 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2769 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2770
2771 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2772 if (!ppd.phy_node) {
2773 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2774 of_property_read_u32(pnp, "speed", &ppd.speed);
2775 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2776 }
2777
785bf6f7 2778 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
76723bca
SH		 2779 if (!ppdev)
2780 return -ENOMEM;
2781 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
b5d82db8 2782 ppdev->dev.of_node = pnp;
76723bca
SH		 2783
2784 ret = platform_device_add_resources(ppdev, &res, 1);
2785 if (ret)
2786 goto port_err;
2787
2788 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2789 if (ret)
2790 goto port_err;
2791
2792 ret = platform_device_add(ppdev);
2793 if (ret)
2794 goto port_err;
2795
785bf6f7 2796 port_platdev[dev_num] = ppdev;
76723bca
SH		 2797
2798 return 0;
2799
2800port_err:
2801 platform_device_put(ppdev);
2802 return ret;
2803}
2804
2805static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2806{
2807 struct mv643xx_eth_shared_platform_data *pd;
2808 struct device_node *pnp, *np = pdev->dev.of_node;
2809 int ret;
2810
2811 /* bail out if not registered from DT */
2812 if (!np)
2813 return 0;
2814
2815 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2816 if (!pd)
2817 return -ENOMEM;
2818 pdev->dev.platform_data = pd;
2819
2820 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2821
2822 for_each_available_child_of_node(np, pnp) {
2823 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
26b7974d
JL		 2824 if (ret) {
2825 of_node_put(pnp);
76723bca 2826 return ret;
26b7974d 2827 }
76723bca
SH		 2828 }
2829 return 0;
2830}
2831
2832static void mv643xx_eth_shared_of_remove(void)
2833{
2834 int n;
2835
2836 for (n = 0; n < 3; n++) {
2837 platform_device_del(port_platdev[n]);
2838 port_platdev[n] = NULL;
2839 }
2840}
2841#else
ff20877a 2842static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
76723bca 2843{
ff20877a 2844 return 0;
76723bca
SH		 2845}
2846
ff20877a
AB		 2847static inline void mv643xx_eth_shared_of_remove(void)
2848{
2849}
76723bca
SH		 2850#endif
2851
c9df406f 2852static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2853{
10a9948d 2854 static int mv643xx_eth_version_printed;
76723bca 2855 struct mv643xx_eth_shared_platform_data *pd;
e5371493 2856 struct mv643xx_eth_shared_private *msp;
63a9332b 2857 const struct mbus_dram_target_info *dram;
c9df406f 2858 struct resource *res;
76723bca 2859 int ret;
9f8dd319 2860
e5371493 2861 if (!mv643xx_eth_version_printed++)
7542db8b
JP		 2862 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2863 mv643xx_eth_driver_version);
9f8dd319 2864
c9df406f
LB		 2865 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2866 if (res == NULL)
727f957a 2867 return -EINVAL;
9f8dd319 2868
727f957a 2869 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
c9df406f 2870 if (msp == NULL)
727f957a 2871 return -ENOMEM;
76723bca 2872 platform_set_drvdata(pdev, msp);
c9df406f 2873
65a6f969 2874 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
cc9754b3 2875 if (msp->base == NULL)
727f957a 2876 return -ENOMEM;
c9df406f 2877
20922486
SH		 2878 msp->clk = devm_clk_get(&pdev->dev, NULL);
2879 if (!IS_ERR(msp->clk))
2880 clk_prepare_enable(msp->clk);
2881
c9df406f
LB		 2882 /*
2883 * (Re-)program MBUS remapping windows if we are asked to.
2884 */
63a9332b
AL		 2885 dram = mv_mbus_dram_info();
2886 if (dram)
2887 mv643xx_eth_conf_mbus_windows(msp, dram);
c9df406f 2888
76723bca
SH		 2889 ret = mv643xx_eth_shared_of_probe(pdev);
2890 if (ret)
2891 return ret;
bbfa6d0a 2892 pd = dev_get_platdata(&pdev->dev);
76723bca 2893
50a749c1
DC		 2894 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2895 pd->tx_csum_limit : 9 * 1024;
773fc3ee 2896 infer_hw_params(msp);
fc32b0e2 2897
c9df406f 2898 return 0;
c9df406f
LB		 2899}
2900
2901static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2902{
e5371493 2903 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2904
76723bca 2905 mv643xx_eth_shared_of_remove();
20922486
SH		 2906 if (!IS_ERR(msp->clk))
2907 clk_disable_unprepare(msp->clk);
c9df406f 2908 return 0;
9f8dd319
DF		 2909}
2910
c9df406f 2911static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2912 .probe = mv643xx_eth_shared_probe,
2913 .remove = mv643xx_eth_shared_remove,
c9df406f 2914 .driver = {
fc32b0e2 2915 .name = MV643XX_ETH_SHARED_NAME,
76723bca 2916 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
c9df406f
LB		 2917 },
2918};
2919
e5371493 2920static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2921{
c9df406f 2922 int addr_shift = 5 * mp->port_num;
fc32b0e2 2923 u32 data;
1da177e4 2924
fc32b0e2
LB		 2925 data = rdl(mp, PHY_ADDR);
2926 data &= ~(0x1f << addr_shift);
2927 data |= (phy_addr & 0x1f) << addr_shift;
2928 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2929}
2930
e5371493 2931static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2932{
fc32b0e2
LB		 2933 unsigned int data;
2934
2935 data = rdl(mp, PHY_ADDR);
2936
2937 return (data >> (5 * mp->port_num)) & 0x1f;
2938}
2939
2940static void set_params(struct mv643xx_eth_private *mp,
2941 struct mv643xx_eth_platform_data *pd)
2942{
2943 struct net_device *dev = mp->dev;
ee9e4956 2944 unsigned int tx_ring_size;
fc32b0e2
LB		 2945
2946 if (is_valid_ether_addr(pd->mac_addr))
d458cdf7 2947 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
fc32b0e2
LB		 2948 else
2949 uc_addr_get(mp, dev->dev_addr);
2950
e7d2f4db 2951 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2952 if (pd->rx_queue_size)
e7d2f4db 2953 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2954 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2955 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2956
f7981c1c 2957 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2958
ee9e4956 2959 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2960 if (pd->tx_queue_size)
ee9e4956
EG		 2961 tx_ring_size = pd->tx_queue_size;
2962
2963 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2964 MV643XX_MAX_SKB_DESCS * 2, 4096);
2965 if (mp->tx_ring_size != tx_ring_size)
2966 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2967 mp->tx_ring_size, tx_ring_size);
2968
fc32b0e2
LB		 2969 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2970 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2971
f7981c1c 2972 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2973}
2974
fd33b244
JG		 2975static int get_phy_mode(struct mv643xx_eth_private *mp)
2976{
2977 struct device *dev = mp->dev->dev.parent;
2978 int iface = -1;
2979
2980 if (dev->of_node)
2981 iface = of_get_phy_mode(dev->of_node);
2982
2983 /* Historical default if unspecified. We could also read/write
2984 * the interface state in the PSC1
2985 */
2986 if (iface < 0)
2987 iface = PHY_INTERFACE_MODE_GMII;
2988 return iface;
2989}
2990
ed94493f
LB		 2991static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2992 int phy_addr)
1da177e4 2993{
ed94493f
LB		 2994 struct phy_device *phydev;
2995 int start;
2996 int num;
2997 int i;
c3a07134 2998 char phy_id[MII_BUS_ID_SIZE + 3];
45c5d3bc 2999
ed94493f
LB		 3000 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
3001 start = phy_addr_get(mp) & 0x1f;
3002 num = 32;
3003 } else {
3004 start = phy_addr & 0x1f;
3005 num = 1;
3006 }
45c5d3bc 3007
c3a07134 3008 /* Attempt to connect to the PHY using orion-mdio */
976c90b9 3009 phydev = ERR_PTR(-ENODEV);
ed94493f
LB		 3010 for (i = 0; i < num; i++) {
3011 int addr = (start + i) & 0x1f;
fc32b0e2 3012
c3a07134
FF		 3013 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
3014 "orion-mdio-mii", addr);
1da177e4 3015
c3a07134 3016 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
fd33b244 3017 get_phy_mode(mp));
c3a07134
FF		 3018 if (!IS_ERR(phydev)) {
3019 phy_addr_set(mp, addr);
3020 break;
ed94493f
LB		 3021 }
3022 }
1da177e4 3023
ed94493f 3024 return phydev;
1da177e4
LT		 3025}
3026
ed94493f 3027static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 3028{
1e8a655d
PR		 3029 struct net_device *dev = mp->dev;
3030 struct phy_device *phy = dev->phydev;
c28a4f89 3031
ed94493f
LB		 3032 if (speed == 0) {
3033 phy->autoneg = AUTONEG_ENABLE;
3034 phy->speed = 0;
3035 phy->duplex = 0;
3036 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 3037 } else {
ed94493f
LB		 3038 phy->autoneg = AUTONEG_DISABLE;
3039 phy->advertising = 0;
3040 phy->speed = speed;
3041 phy->duplex = duplex;
c9df406f 3042 }
ed94493f 3043 phy_start_aneg(phy);
c28a4f89
JC		 3044}
3045
81600eea
LB		 3046static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3047{
1e8a655d 3048 struct net_device *dev = mp->dev;
81600eea
LB		 3049 u32 pscr;
3050
37a6084f 3051 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 3052 if (pscr & SERIAL_PORT_ENABLE) {
3053 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 3054 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 3055 }
3056
3057 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
1e8a655d 3058 if (!dev->phydev) {
81600eea
LB		 3059 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3060 if (speed == SPEED_1000)
3061 pscr |= SET_GMII_SPEED_TO_1000;
3062 else if (speed == SPEED_100)
3063 pscr |= SET_MII_SPEED_TO_100;
3064
3065 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3066
3067 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3068 if (duplex == DUPLEX_FULL)
3069 pscr |= SET_FULL_DUPLEX_MODE;
3070 }
3071
37a6084f 3072 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 3073}
3074
ea8a8642
LB		 3075static const struct net_device_ops mv643xx_eth_netdev_ops = {
3076 .ndo_open = mv643xx_eth_open,
3077 .ndo_stop = mv643xx_eth_stop,
3078 .ndo_start_xmit = mv643xx_eth_xmit,
3079 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3080 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 3081 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 3082 .ndo_do_ioctl = mv643xx_eth_ioctl,
3083 .ndo_change_mtu = mv643xx_eth_change_mtu,
aad59c43 3084 .ndo_set_features = mv643xx_eth_set_features,
ea8a8642
LB		 3085 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3086 .ndo_get_stats = mv643xx_eth_get_stats,
3087#ifdef CONFIG_NET_POLL_CONTROLLER
3088 .ndo_poll_controller = mv643xx_eth_netpoll,
3089#endif
3090};
3091
c9df406f 3092static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 3093{
c9df406f 3094 struct mv643xx_eth_platform_data *pd;
e5371493 3095 struct mv643xx_eth_private *mp;
c9df406f 3096 struct net_device *dev;
1e8a655d 3097 struct phy_device *phydev = NULL;
c9df406f 3098 struct resource *res;
fc32b0e2 3099 int err;
1da177e4 3100
bbfa6d0a 3101 pd = dev_get_platdata(&pdev->dev);
c9df406f 3102 if (pd == NULL) {
7542db8b 3103 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
c9df406f
LB		 3104 return -ENODEV;
3105 }
1da177e4 3106
c9df406f 3107 if (pd->shared == NULL) {
7542db8b 3108 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 3109 return -ENODEV;
3110 }
8f518703 3111
e5ef1de1 3112 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 3113 if (!dev)
3114 return -ENOMEM;
1da177e4 3115
fd33b244 3116 SET_NETDEV_DEV(dev, &pdev->dev);
c9df406f 3117 mp = netdev_priv(dev);
fc32b0e2
LB		 3118 platform_set_drvdata(pdev, mp);
3119
3120 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 3121 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 3122 mp->port_num = pd->port_number;
3123
c9df406f 3124 mp->dev = dev;
78fff83b 3125
cb85215f
SH		 3126 /* Kirkwood resets some registers on gated clocks. Especially
3127 * CLK125_BYPASS_EN must be cleared but is not available on
3128 * all other SoCs/System Controllers using this driver.
3129 */
3130 if (of_device_is_compatible(pdev->dev.of_node,
3131 "marvell,kirkwood-eth-port"))
3132 wrlp(mp, PORT_SERIAL_CONTROL1,
3133 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3134
452503eb 3135 /*
9a43a026
AL		 3136 * Start with a default rate, and if there is a clock, allow
3137 * it to override the default.
452503eb 3138 */
9a43a026 3139 mp->t_clk = 133000000;
20922486 3140 mp->clk = devm_clk_get(&pdev->dev, NULL);
452503eb
AL		 3141 if (!IS_ERR(mp->clk)) {
3142 clk_prepare_enable(mp->clk);
3143 mp->t_clk = clk_get_rate(mp->clk);
76723bca
SH		 3144 } else if (!IS_ERR(mp->shared->clk)) {
3145 mp->t_clk = clk_get_rate(mp->shared->clk);
452503eb 3146 }
20922486 3147
fc32b0e2 3148 set_params(mp, pd);
206d6b32
BH		 3149 netif_set_real_num_tx_queues(dev, mp->txq_count);
3150 netif_set_real_num_rx_queues(dev, mp->rxq_count);
fc32b0e2 3151
cc9d4598
SH		 3152 err = 0;
3153 if (pd->phy_node) {
1e8a655d
PR		 3154 phydev = of_phy_connect(mp->dev, pd->phy_node,
3155 mv643xx_eth_adjust_link, 0,
27058af4 3156 get_phy_mode(mp));
1e8a655d 3157 if (!phydev)
cc9d4598 3158 err = -ENODEV;
6115c11f 3159 else
1e8a655d 3160 phy_addr_set(mp, phydev->mdio.addr);
cc9d4598 3161 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
1e8a655d 3162 phydev = phy_scan(mp, pd->phy_addr);
bedfe324 3163
1e8a655d
PR		 3164 if (IS_ERR(phydev))
3165 err = PTR_ERR(phydev);
cc9d4598
SH		 3166 else
3167 phy_init(mp, pd->speed, pd->duplex);
976c90b9 3168 }
cc9d4598
SH		 3169 if (err == -ENODEV) {
3170 err = -EPROBE_DEFER;
3171 goto out;
3172 }
3173 if (err)
3174 goto out;
6bdf576e 3175
7ad24ea4 3176 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
ed94493f 3177
81600eea 3178 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 3179
4ff3495a
LB		 3180
3181 mib_counters_clear(mp);
3182
12d5e6fd
VT		 3183 setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper,
3184 (unsigned long)mp);
4ff3495a 3185 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
4ff3495a
LB		 3186
3187 spin_lock_init(&mp->mib_counters_lock);
3188
3189 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3190
a3659aa0 3191 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2257e05c 3192
12d5e6fd 3193 setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp);
2257e05c 3194
fc32b0e2 3195
c9df406f
LB		 3196 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3197 BUG_ON(!res);
3198 dev->irq = res->start;
1da177e4 3199
ea8a8642
LB		 3200 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3201
c9df406f
LB		 3202 dev->watchdog_timeo = 2 * HZ;
3203 dev->base_addr = 0;
1da177e4 3204
3ae8f4e0 3205 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
4d48d589
EG		 3206 dev->vlan_features = dev->features;
3207
3208 dev->features |= NETIF_F_RXCSUM;
3209 dev->hw_features = dev->features;
1da177e4 3210
01789349 3211 dev->priv_flags |= IFF_UNICAST_FLT;
ee9e4956 3212 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
01789349 3213
d894be57
JW		 3214 /* MTU range: 64 - 9500 */
3215 dev->min_mtu = 64;
3216 dev->max_mtu = 9500;
3217
c9df406f 3218 if (mp->shared->win_protect)
fc32b0e2 3219 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 3220
a5fe3616
LB		 3221 netif_carrier_off(dev);
3222
b5e86db4
LB		 3223 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3224
4fb0a54a 3225 set_rx_coal(mp, 250);
a5fe3616
LB		 3226 set_tx_coal(mp, 0);
3227
c9df406f
LB		 3228 err = register_netdev(dev);
3229 if (err)
3230 goto out;
1da177e4 3231
7542db8b
JP		 3232 netdev_notice(dev, "port %d with MAC address %pM\n",
3233 mp->port_num, dev->dev_addr);
1da177e4 3234
13d64285 3235 if (mp->tx_desc_sram_size > 0)
7542db8b 3236 netdev_notice(dev, "configured with sram\n");
1da177e4 3237
c9df406f 3238 return 0;
1da177e4 3239
c9df406f 3240out:
20922486 3241 if (!IS_ERR(mp->clk))
baffab28 3242 clk_disable_unprepare(mp->clk);
c9df406f 3243 free_netdev(dev);
1da177e4 3244
c9df406f 3245 return err;
1da177e4
LT		 3246}
3247
c9df406f 3248static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 3249{
fc32b0e2 3250 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1e8a655d 3251 struct net_device *dev = mp->dev;
1da177e4 3252
fc32b0e2 3253 unregister_netdev(mp->dev);
1e8a655d
PR		 3254 if (dev->phydev)
3255 phy_disconnect(dev->phydev);
23f333a2 3256 cancel_work_sync(&mp->tx_timeout_task);
452503eb 3257
20922486 3258 if (!IS_ERR(mp->clk))
452503eb 3259 clk_disable_unprepare(mp->clk);
9a43a026 3260
fc32b0e2 3261 free_netdev(mp->dev);
c9df406f 3262
c9df406f 3263 return 0;
1da177e4
LT		 3264}
3265
c9df406f 3266static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 3267{
fc32b0e2 3268 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 3269
c9df406f 3270 /* Mask all interrupts on ethernet port */
37a6084f
LB		 3271 wrlp(mp, INT_MASK, 0);
3272 rdlp(mp, INT_MASK);
c9df406f 3273
fc32b0e2
LB		 3274 if (netif_running(mp->dev))
3275 port_reset(mp);
d0412d96
JC		 3276}
3277
c9df406f 3278static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 3279 .probe = mv643xx_eth_probe,
3280 .remove = mv643xx_eth_remove,
3281 .shutdown = mv643xx_eth_shutdown,
c9df406f 3282 .driver = {
fc32b0e2 3283 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3284 },
3285};
3286
3b5dde70
TR		 3287static struct platform_driver * const drivers[] = {
3288 &mv643xx_eth_shared_driver,
3289 &mv643xx_eth_driver,
3290};
3291
e5371493 3292static int __init mv643xx_eth_init_module(void)
d0412d96 3293{
3b5dde70 3294 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
d0412d96 3295}
fc32b0e2 3296module_init(mv643xx_eth_init_module);
d0412d96 3297
e5371493 3298static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3299{
3b5dde70 3300 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
d0412d96 3301}
e5371493 3302module_exit(mv643xx_eth_cleanup_module);
1da177e4 3303
45675bc6
LB		 3304MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3305 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3306MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3307MODULE_LICENSE("GPL");
c9df406f 3308MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3309MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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