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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
c5aff182 TP |
15 | #include <linux/netdevice.h> |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/skbuff.h> | |
19 | #include <linux/inetdevice.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
2d39d120 | 23 | #include <linux/if_vlan.h> |
c5aff182 TP |
24 | #include <net/ip.h> |
25 | #include <net/ipv6.h> | |
c3f0dd38 | 26 | #include <linux/io.h> |
2adb719d | 27 | #include <net/tso.h> |
c5aff182 TP |
28 | #include <linux/of.h> |
29 | #include <linux/of_irq.h> | |
30 | #include <linux/of_mdio.h> | |
31 | #include <linux/of_net.h> | |
32 | #include <linux/of_address.h> | |
33 | #include <linux/phy.h> | |
189dd626 | 34 | #include <linux/clk.h> |
c5aff182 TP |
35 | |
36 | /* Registers */ | |
37 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
38 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) | |
39 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) | |
40 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
41 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
42 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
43 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
44 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
45 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
46 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
47 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
48 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
49 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
50 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
51 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
52 | #define MVNETA_PORT_RX_RESET 0x1cc0 | |
53 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
54 | #define MVNETA_PHY_ADDR 0x2000 | |
55 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
56 | #define MVNETA_MBUS_RETRY 0x2010 | |
57 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
58 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
59 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
60 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
61 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
62 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
63 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
64 | #define MVNETA_PORT_CONFIG 0x2400 | |
65 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
66 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
67 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
68 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
69 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
70 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
71 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
72 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
73 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
74 | MVNETA_DEF_RXQ_ARP(q) | \ | |
75 | MVNETA_DEF_RXQ_TCP(q) | \ | |
76 | MVNETA_DEF_RXQ_UDP(q) | \ | |
77 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
78 | MVNETA_TX_UNSET_ERR_SUM | \ | |
79 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
80 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
81 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
82 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
83 | #define MVNETA_SDMA_CONFIG 0x241c | |
84 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
85 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
86 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
87 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 88 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
89 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
90 | #define MVNETA_PORT_STATUS 0x2444 | |
91 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
92 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
93 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 94 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 95 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 96 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
97 | #define MVNETA_TYPE_PRIO 0x24bc |
98 | #define MVNETA_FORCE_UNI BIT(21) | |
99 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
100 | #define MVNETA_TXQ_CMD 0x2448 | |
101 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
102 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
898b2970 SS |
103 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
104 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 TP |
105 | #define MVNETA_ACC_MODE 0x2500 |
106 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) | |
107 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
108 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
109 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) | |
40ba35e7 | 110 | |
111 | /* Exception Interrupt Port/Queue Cause register */ | |
112 | ||
c5aff182 | 113 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 114 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 115 | |
116 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
117 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
118 | * bits 16..23 = RXQ FREE, one bit per queue. | |
119 | * bit 29 = OLD_REG_SUM, see old reg ? | |
120 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
121 | * bit 31 = MISC_SUM, one bit for 4 ports | |
122 | */ | |
123 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
124 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
125 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
126 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 127 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 128 | |
c5aff182 TP |
129 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
130 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 131 | |
132 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
133 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
134 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 135 | |
136 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
137 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
138 | #define MVNETA_CAUSE_PTP BIT(4) | |
139 | ||
140 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
141 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
142 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
143 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
144 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
145 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
146 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
147 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
148 | ||
149 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
150 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
151 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
152 | ||
153 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
154 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
155 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
156 | ||
c5aff182 TP |
157 | #define MVNETA_INTR_ENABLE 0x25b8 |
158 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
40ba35e7 | 159 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF |
160 | ||
c5aff182 TP |
161 | #define MVNETA_RXQ_CMD 0x2680 |
162 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
163 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
164 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
165 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
166 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
167 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
168 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
169 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
170 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 171 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 172 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
173 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
174 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
175 | #define MVNETA_GMAC_STATUS 0x2c10 | |
176 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
177 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
178 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
179 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
180 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
181 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
182 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
183 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
184 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
185 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
186 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 187 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
c5aff182 TP |
188 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
189 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 190 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
898b2970 | 191 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 192 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 193 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
c5aff182 TP |
194 | #define MVNETA_MIB_COUNTERS_BASE 0x3080 |
195 | #define MVNETA_MIB_LATE_COLLISION 0x7c | |
196 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
197 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
198 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
199 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
200 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
201 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
202 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
203 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
204 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
205 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) | |
206 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
207 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
208 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
209 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
210 | #define MVNETA_TX_MTU 0x3e0c | |
211 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
212 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
213 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
214 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
215 | ||
216 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff | |
217 | ||
218 | /* Descriptor ring Macros */ | |
219 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
220 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
221 | ||
222 | /* Various constants */ | |
223 | ||
224 | /* Coalescing */ | |
aebea2ba | 225 | #define MVNETA_TXDONE_COAL_PKTS 1 |
c5aff182 TP |
226 | #define MVNETA_RX_COAL_PKTS 32 |
227 | #define MVNETA_RX_COAL_USEC 100 | |
228 | ||
6a20c175 | 229 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
230 | * by Marvell switches when a specific hardware mode is enabled (not |
231 | * supported by this driver) or is filled automatically by zeroes on | |
232 | * the RX side. Those two bytes being at the front of the Ethernet | |
233 | * header, they allow to have the IP header aligned on a 4 bytes | |
234 | * boundary automatically: the hardware skips those two bytes on its | |
235 | * own. | |
236 | */ | |
237 | #define MVNETA_MH_SIZE 2 | |
238 | ||
239 | #define MVNETA_VLAN_TAG_LEN 4 | |
240 | ||
241 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 | |
242 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 | |
243 | #define MVNETA_ACC_MODE_EXT 1 | |
244 | ||
245 | /* Timeout constants */ | |
246 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
247 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
248 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
249 | ||
250 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
251 | ||
2adb719d EG |
252 | /* TSO header size */ |
253 | #define TSO_HEADER_SIZE 128 | |
254 | ||
c5aff182 TP |
255 | /* Max number of Rx descriptors */ |
256 | #define MVNETA_MAX_RXD 128 | |
257 | ||
258 | /* Max number of Tx descriptors */ | |
259 | #define MVNETA_MAX_TXD 532 | |
260 | ||
8eef5f97 EG |
261 | /* Max number of allowed TCP segments for software TSO */ |
262 | #define MVNETA_MAX_TSO_SEGS 100 | |
263 | ||
264 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
265 | ||
c5aff182 TP |
266 | /* descriptor aligned size */ |
267 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
268 | ||
269 | #define MVNETA_RX_PKT_SIZE(mtu) \ | |
270 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
271 | ETH_HLEN + ETH_FCS_LEN, \ | |
272 | MVNETA_CPU_D_CACHE_LINE_SIZE) | |
273 | ||
2e3173a3 EG |
274 | #define IS_TSO_HEADER(txq, addr) \ |
275 | ((addr >= txq->tso_hdrs_phys) && \ | |
276 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
277 | ||
c5aff182 TP |
278 | #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) |
279 | ||
74c41b04 | 280 | struct mvneta_pcpu_stats { |
c5aff182 | 281 | struct u64_stats_sync syncp; |
74c41b04 | 282 | u64 rx_packets; |
283 | u64 rx_bytes; | |
284 | u64 tx_packets; | |
285 | u64 tx_bytes; | |
c5aff182 TP |
286 | }; |
287 | ||
12bb03b4 MR |
288 | struct mvneta_pcpu_port { |
289 | /* Pointer to the shared port */ | |
290 | struct mvneta_port *pp; | |
291 | ||
292 | /* Pointer to the CPU-local NAPI struct */ | |
293 | struct napi_struct napi; | |
294 | ||
295 | /* Cause of the previous interrupt */ | |
296 | u32 cause_rx_tx; | |
297 | }; | |
298 | ||
c5aff182 | 299 | struct mvneta_port { |
12bb03b4 MR |
300 | struct mvneta_pcpu_port __percpu *ports; |
301 | struct mvneta_pcpu_stats __percpu *stats; | |
302 | ||
c5aff182 | 303 | int pkt_size; |
8ec2cd48 | 304 | unsigned int frag_size; |
c5aff182 TP |
305 | void __iomem *base; |
306 | struct mvneta_rx_queue *rxqs; | |
307 | struct mvneta_tx_queue *txqs; | |
c5aff182 TP |
308 | struct net_device *dev; |
309 | ||
c5aff182 | 310 | /* Core clock */ |
189dd626 | 311 | struct clk *clk; |
c5aff182 TP |
312 | u8 mcast_count[256]; |
313 | u16 tx_ring_size; | |
314 | u16 rx_ring_size; | |
c5aff182 TP |
315 | |
316 | struct mii_bus *mii_bus; | |
317 | struct phy_device *phy_dev; | |
318 | phy_interface_t phy_interface; | |
319 | struct device_node *phy_node; | |
320 | unsigned int link; | |
321 | unsigned int duplex; | |
322 | unsigned int speed; | |
b65657fc | 323 | unsigned int tx_csum_limit; |
898b2970 | 324 | int use_inband_status:1; |
c5aff182 TP |
325 | }; |
326 | ||
6a20c175 | 327 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
328 | * layout of the transmit and reception DMA descriptors, and their |
329 | * layout is therefore defined by the hardware design | |
330 | */ | |
6083ed44 | 331 | |
c5aff182 TP |
332 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
333 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
334 | #define MVNETA_TX_L4_UDP BIT(16) | |
335 | #define MVNETA_TX_L3_IP6 BIT(17) | |
336 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
337 | #define MVNETA_TXD_Z_PAD BIT(19) | |
338 | #define MVNETA_TXD_L_DESC BIT(20) | |
339 | #define MVNETA_TXD_F_DESC BIT(21) | |
340 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
341 | MVNETA_TXD_L_DESC | \ | |
342 | MVNETA_TXD_F_DESC) | |
343 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
344 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
345 | ||
c5aff182 TP |
346 | #define MVNETA_RXD_ERR_CRC 0x0 |
347 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) | |
348 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
349 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
350 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
351 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
352 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
353 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
354 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
355 | ||
9ad8fef6 | 356 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
357 | struct mvneta_tx_desc { |
358 | u32 command; /* Options used by HW for packet transmitting.*/ | |
359 | u16 reserverd1; /* csum_l4 (for future use) */ | |
360 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
361 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
362 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
363 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
364 | }; | |
365 | ||
366 | struct mvneta_rx_desc { | |
367 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
368 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
369 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 370 | |
c5aff182 TP |
371 | u32 buf_phys_addr; /* Physical address of the buffer */ |
372 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 373 | |
c5aff182 TP |
374 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
375 | u16 reserved3; /* prefetch_cmd, for future use */ | |
376 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 377 | |
c5aff182 TP |
378 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
379 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
380 | }; | |
9ad8fef6 TP |
381 | #else |
382 | struct mvneta_tx_desc { | |
383 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
384 | u16 reserverd1; /* csum_l4 (for future use) */ | |
385 | u32 command; /* Options used by HW for packet transmitting.*/ | |
386 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
387 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
388 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
389 | }; | |
390 | ||
391 | struct mvneta_rx_desc { | |
392 | u16 data_size; /* Size of received packet in bytes */ | |
393 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
394 | u32 status; /* Info about received packet */ | |
395 | ||
396 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
397 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
398 | ||
399 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
400 | u16 reserved3; /* prefetch_cmd, for future use */ | |
401 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
402 | ||
403 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
404 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
405 | }; | |
406 | #endif | |
c5aff182 TP |
407 | |
408 | struct mvneta_tx_queue { | |
409 | /* Number of this TX queue, in the range 0-7 */ | |
410 | u8 id; | |
411 | ||
412 | /* Number of TX DMA descriptors in the descriptor ring */ | |
413 | int size; | |
414 | ||
415 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
416 | * descriptor ring |
417 | */ | |
c5aff182 | 418 | int count; |
8eef5f97 EG |
419 | int tx_stop_threshold; |
420 | int tx_wake_threshold; | |
c5aff182 TP |
421 | |
422 | /* Array of transmitted skb */ | |
423 | struct sk_buff **tx_skb; | |
424 | ||
425 | /* Index of last TX DMA descriptor that was inserted */ | |
426 | int txq_put_index; | |
427 | ||
428 | /* Index of the TX DMA descriptor to be cleaned up */ | |
429 | int txq_get_index; | |
430 | ||
431 | u32 done_pkts_coal; | |
432 | ||
433 | /* Virtual address of the TX DMA descriptors array */ | |
434 | struct mvneta_tx_desc *descs; | |
435 | ||
436 | /* DMA address of the TX DMA descriptors array */ | |
437 | dma_addr_t descs_phys; | |
438 | ||
439 | /* Index of the last TX DMA descriptor */ | |
440 | int last_desc; | |
441 | ||
442 | /* Index of the next TX DMA descriptor to process */ | |
443 | int next_desc_to_proc; | |
2adb719d EG |
444 | |
445 | /* DMA buffers for TSO headers */ | |
446 | char *tso_hdrs; | |
447 | ||
448 | /* DMA address of TSO headers */ | |
449 | dma_addr_t tso_hdrs_phys; | |
c5aff182 TP |
450 | }; |
451 | ||
452 | struct mvneta_rx_queue { | |
453 | /* rx queue number, in the range 0-7 */ | |
454 | u8 id; | |
455 | ||
456 | /* num of rx descriptors in the rx descriptor ring */ | |
457 | int size; | |
458 | ||
459 | /* counter of times when mvneta_refill() failed */ | |
460 | int missed; | |
461 | ||
462 | u32 pkts_coal; | |
463 | u32 time_coal; | |
464 | ||
465 | /* Virtual address of the RX DMA descriptors array */ | |
466 | struct mvneta_rx_desc *descs; | |
467 | ||
468 | /* DMA address of the RX DMA descriptors array */ | |
469 | dma_addr_t descs_phys; | |
470 | ||
471 | /* Index of the last RX DMA descriptor */ | |
472 | int last_desc; | |
473 | ||
474 | /* Index of the next RX DMA descriptor to process */ | |
475 | int next_desc_to_proc; | |
476 | }; | |
477 | ||
edadb7fa EG |
478 | /* The hardware supports eight (8) rx queues, but we are only allowing |
479 | * the first one to be used. Therefore, let's just allocate one queue. | |
480 | */ | |
481 | static int rxq_number = 1; | |
c5aff182 TP |
482 | static int txq_number = 8; |
483 | ||
484 | static int rxq_def; | |
c5aff182 | 485 | |
f19fadfc | 486 | static int rx_copybreak __read_mostly = 256; |
487 | ||
c5aff182 TP |
488 | #define MVNETA_DRIVER_NAME "mvneta" |
489 | #define MVNETA_DRIVER_VERSION "1.0" | |
490 | ||
491 | /* Utility/helper methods */ | |
492 | ||
493 | /* Write helper method */ | |
494 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
495 | { | |
496 | writel(data, pp->base + offset); | |
497 | } | |
498 | ||
499 | /* Read helper method */ | |
500 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
501 | { | |
502 | return readl(pp->base + offset); | |
503 | } | |
504 | ||
505 | /* Increment txq get counter */ | |
506 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
507 | { | |
508 | txq->txq_get_index++; | |
509 | if (txq->txq_get_index == txq->size) | |
510 | txq->txq_get_index = 0; | |
511 | } | |
512 | ||
513 | /* Increment txq put counter */ | |
514 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
515 | { | |
516 | txq->txq_put_index++; | |
517 | if (txq->txq_put_index == txq->size) | |
518 | txq->txq_put_index = 0; | |
519 | } | |
520 | ||
521 | ||
522 | /* Clear all MIB counters */ | |
523 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
524 | { | |
525 | int i; | |
526 | u32 dummy; | |
527 | ||
528 | /* Perform dummy reads from MIB counters */ | |
529 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
530 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
531 | } | |
532 | ||
533 | /* Get System Network Statistics */ | |
534 | struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, | |
535 | struct rtnl_link_stats64 *stats) | |
536 | { | |
537 | struct mvneta_port *pp = netdev_priv(dev); | |
538 | unsigned int start; | |
74c41b04 | 539 | int cpu; |
c5aff182 | 540 | |
74c41b04 | 541 | for_each_possible_cpu(cpu) { |
542 | struct mvneta_pcpu_stats *cpu_stats; | |
543 | u64 rx_packets; | |
544 | u64 rx_bytes; | |
545 | u64 tx_packets; | |
546 | u64 tx_bytes; | |
c5aff182 | 547 | |
74c41b04 | 548 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
549 | do { | |
57a7744e | 550 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 551 | rx_packets = cpu_stats->rx_packets; |
552 | rx_bytes = cpu_stats->rx_bytes; | |
553 | tx_packets = cpu_stats->tx_packets; | |
554 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 555 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 556 | |
74c41b04 | 557 | stats->rx_packets += rx_packets; |
558 | stats->rx_bytes += rx_bytes; | |
559 | stats->tx_packets += tx_packets; | |
560 | stats->tx_bytes += tx_bytes; | |
561 | } | |
c5aff182 TP |
562 | |
563 | stats->rx_errors = dev->stats.rx_errors; | |
564 | stats->rx_dropped = dev->stats.rx_dropped; | |
565 | ||
566 | stats->tx_dropped = dev->stats.tx_dropped; | |
567 | ||
568 | return stats; | |
569 | } | |
570 | ||
571 | /* Rx descriptors helper methods */ | |
572 | ||
5428213c | 573 | /* Checks whether the RX descriptor having this status is both the first |
574 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
575 | * received through a single RX descriptor, so not having each RX |
576 | * descriptor with its first and last bits set is an error | |
577 | */ | |
5428213c | 578 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 579 | { |
5428213c | 580 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
581 | MVNETA_RXD_FIRST_LAST_DESC; |
582 | } | |
583 | ||
584 | /* Add number of descriptors ready to receive new packets */ | |
585 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
586 | struct mvneta_rx_queue *rxq, | |
587 | int ndescs) | |
588 | { | |
589 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
590 | * be added at once |
591 | */ | |
c5aff182 TP |
592 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
593 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
594 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
595 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
596 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
597 | } | |
598 | ||
599 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
600 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
601 | } | |
602 | ||
603 | /* Get number of RX descriptors occupied by received packets */ | |
604 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
605 | struct mvneta_rx_queue *rxq) | |
606 | { | |
607 | u32 val; | |
608 | ||
609 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
610 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
611 | } | |
612 | ||
6a20c175 | 613 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
614 | * from mvneta_rxq_drop_pkts(). |
615 | */ | |
616 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
617 | struct mvneta_rx_queue *rxq, | |
618 | int rx_done, int rx_filled) | |
619 | { | |
620 | u32 val; | |
621 | ||
622 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
623 | val = rx_done | | |
624 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
625 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
626 | return; | |
627 | } | |
628 | ||
629 | /* Only 255 descriptors can be added at once */ | |
630 | while ((rx_done > 0) || (rx_filled > 0)) { | |
631 | if (rx_done <= 0xff) { | |
632 | val = rx_done; | |
633 | rx_done = 0; | |
634 | } else { | |
635 | val = 0xff; | |
636 | rx_done -= 0xff; | |
637 | } | |
638 | if (rx_filled <= 0xff) { | |
639 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
640 | rx_filled = 0; | |
641 | } else { | |
642 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
643 | rx_filled -= 0xff; | |
644 | } | |
645 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
646 | } | |
647 | } | |
648 | ||
649 | /* Get pointer to next RX descriptor to be processed by SW */ | |
650 | static struct mvneta_rx_desc * | |
651 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
652 | { | |
653 | int rx_desc = rxq->next_desc_to_proc; | |
654 | ||
655 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 656 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
657 | return rxq->descs + rx_desc; |
658 | } | |
659 | ||
660 | /* Change maximum receive size of the port. */ | |
661 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
662 | { | |
663 | u32 val; | |
664 | ||
665 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
666 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
667 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
668 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
669 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
670 | } | |
671 | ||
672 | ||
673 | /* Set rx queue offset */ | |
674 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
675 | struct mvneta_rx_queue *rxq, | |
676 | int offset) | |
677 | { | |
678 | u32 val; | |
679 | ||
680 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
681 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
682 | ||
683 | /* Offset is in */ | |
684 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
685 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
686 | } | |
687 | ||
688 | ||
689 | /* Tx descriptors helper methods */ | |
690 | ||
691 | /* Update HW with number of TX descriptors to be sent */ | |
692 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
693 | struct mvneta_tx_queue *txq, | |
694 | int pend_desc) | |
695 | { | |
696 | u32 val; | |
697 | ||
698 | /* Only 255 descriptors can be added at once ; Assume caller | |
6a20c175 TP |
699 | * process TX desriptors in quanta less than 256 |
700 | */ | |
c5aff182 TP |
701 | val = pend_desc; |
702 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
703 | } | |
704 | ||
705 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
706 | static struct mvneta_tx_desc * | |
707 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
708 | { | |
709 | int tx_desc = txq->next_desc_to_proc; | |
710 | ||
711 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
712 | return txq->descs + tx_desc; | |
713 | } | |
714 | ||
715 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
716 | * mapping failures in the TX path. |
717 | */ | |
c5aff182 TP |
718 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
719 | { | |
720 | if (txq->next_desc_to_proc == 0) | |
721 | txq->next_desc_to_proc = txq->last_desc - 1; | |
722 | else | |
723 | txq->next_desc_to_proc--; | |
724 | } | |
725 | ||
726 | /* Set rxq buf size */ | |
727 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
728 | struct mvneta_rx_queue *rxq, | |
729 | int buf_size) | |
730 | { | |
731 | u32 val; | |
732 | ||
733 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
734 | ||
735 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
736 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
737 | ||
738 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
739 | } | |
740 | ||
741 | /* Disable buffer management (BM) */ | |
742 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
743 | struct mvneta_rx_queue *rxq) | |
744 | { | |
745 | u32 val; | |
746 | ||
747 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
748 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
749 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
750 | } | |
751 | ||
c5aff182 TP |
752 | /* Start the Ethernet port RX and TX activity */ |
753 | static void mvneta_port_up(struct mvneta_port *pp) | |
754 | { | |
755 | int queue; | |
756 | u32 q_map; | |
757 | ||
758 | /* Enable all initialized TXs. */ | |
759 | mvneta_mib_counters_clear(pp); | |
760 | q_map = 0; | |
761 | for (queue = 0; queue < txq_number; queue++) { | |
762 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
763 | if (txq->descs != NULL) | |
764 | q_map |= (1 << queue); | |
765 | } | |
766 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
767 | ||
768 | /* Enable all initialized RXQs. */ | |
769 | q_map = 0; | |
770 | for (queue = 0; queue < rxq_number; queue++) { | |
771 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
772 | if (rxq->descs != NULL) | |
773 | q_map |= (1 << queue); | |
774 | } | |
775 | ||
776 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
777 | } | |
778 | ||
779 | /* Stop the Ethernet port activity */ | |
780 | static void mvneta_port_down(struct mvneta_port *pp) | |
781 | { | |
782 | u32 val; | |
783 | int count; | |
784 | ||
785 | /* Stop Rx port activity. Check port Rx activity. */ | |
786 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
787 | ||
788 | /* Issue stop command for active channels only */ | |
789 | if (val != 0) | |
790 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
791 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
792 | ||
793 | /* Wait for all Rx activity to terminate. */ | |
794 | count = 0; | |
795 | do { | |
796 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
797 | netdev_warn(pp->dev, | |
798 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", | |
799 | val); | |
800 | break; | |
801 | } | |
802 | mdelay(1); | |
803 | ||
804 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
805 | } while (val & 0xff); | |
806 | ||
807 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
808 | * command for active channels only |
809 | */ | |
c5aff182 TP |
810 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
811 | ||
812 | if (val != 0) | |
813 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
814 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
815 | ||
816 | /* Wait for all Tx activity to terminate. */ | |
817 | count = 0; | |
818 | do { | |
819 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
820 | netdev_warn(pp->dev, | |
821 | "TIMEOUT for TX stopped status=0x%08x\n", | |
822 | val); | |
823 | break; | |
824 | } | |
825 | mdelay(1); | |
826 | ||
827 | /* Check TX Command reg that all Txqs are stopped */ | |
828 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
829 | ||
830 | } while (val & 0xff); | |
831 | ||
832 | /* Double check to verify that TX FIFO is empty */ | |
833 | count = 0; | |
834 | do { | |
835 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
836 | netdev_warn(pp->dev, | |
837 | "TX FIFO empty timeout status=0x08%x\n", | |
838 | val); | |
839 | break; | |
840 | } | |
841 | mdelay(1); | |
842 | ||
843 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
844 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
845 | (val & MVNETA_TX_IN_PRGRS)); | |
846 | ||
847 | udelay(200); | |
848 | } | |
849 | ||
850 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
851 | static void mvneta_port_enable(struct mvneta_port *pp) | |
852 | { | |
853 | u32 val; | |
854 | ||
855 | /* Enable port */ | |
856 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
857 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
858 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
859 | } | |
860 | ||
861 | /* Disable the port and wait for about 200 usec before retuning */ | |
862 | static void mvneta_port_disable(struct mvneta_port *pp) | |
863 | { | |
864 | u32 val; | |
865 | ||
866 | /* Reset the Enable bit in the Serial Control Register */ | |
867 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
868 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
869 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
870 | ||
871 | udelay(200); | |
872 | } | |
873 | ||
874 | /* Multicast tables methods */ | |
875 | ||
876 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
877 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
878 | { | |
879 | int offset; | |
880 | u32 val; | |
881 | ||
882 | if (queue == -1) { | |
883 | val = 0; | |
884 | } else { | |
885 | val = 0x1 | (queue << 1); | |
886 | val |= (val << 24) | (val << 16) | (val << 8); | |
887 | } | |
888 | ||
889 | for (offset = 0; offset <= 0xc; offset += 4) | |
890 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
891 | } | |
892 | ||
893 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
894 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
895 | { | |
896 | int offset; | |
897 | u32 val; | |
898 | ||
899 | if (queue == -1) { | |
900 | val = 0; | |
901 | } else { | |
902 | val = 0x1 | (queue << 1); | |
903 | val |= (val << 24) | (val << 16) | (val << 8); | |
904 | } | |
905 | ||
906 | for (offset = 0; offset <= 0xfc; offset += 4) | |
907 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
908 | ||
909 | } | |
910 | ||
911 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
912 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
913 | { | |
914 | int offset; | |
915 | u32 val; | |
916 | ||
917 | if (queue == -1) { | |
918 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
919 | val = 0; | |
920 | } else { | |
921 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
922 | val = 0x1 | (queue << 1); | |
923 | val |= (val << 24) | (val << 16) | (val << 8); | |
924 | } | |
925 | ||
926 | for (offset = 0; offset <= 0xfc; offset += 4) | |
927 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
928 | } | |
929 | ||
930 | /* This method sets defaults to the NETA port: | |
931 | * Clears interrupt Cause and Mask registers. | |
932 | * Clears all MAC tables. | |
933 | * Sets defaults to all registers. | |
934 | * Resets RX and TX descriptor rings. | |
935 | * Resets PHY. | |
936 | * This method can be called after mvneta_port_down() to return the port | |
937 | * settings to defaults. | |
938 | */ | |
939 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
940 | { | |
941 | int cpu; | |
942 | int queue; | |
943 | u32 val; | |
944 | ||
945 | /* Clear all Cause registers */ | |
946 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
947 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
948 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
949 | ||
950 | /* Mask all interrupts */ | |
951 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
952 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
953 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
954 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); | |
955 | ||
956 | /* Enable MBUS Retry bit16 */ | |
957 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
958 | ||
959 | /* Set CPU queue access map - all CPUs have access to all RX | |
6a20c175 TP |
960 | * queues and to all TX queues |
961 | */ | |
2502d0ef | 962 | for_each_present_cpu(cpu) |
c5aff182 TP |
963 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), |
964 | (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | | |
965 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); | |
966 | ||
967 | /* Reset RX and TX DMAs */ | |
968 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
969 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
970 | ||
971 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
972 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
973 | for (queue = 0; queue < txq_number; queue++) { | |
974 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
975 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
976 | } | |
977 | ||
978 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
979 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
980 | ||
981 | /* Set Port Acceleration Mode */ | |
982 | val = MVNETA_ACC_MODE_EXT; | |
983 | mvreg_write(pp, MVNETA_ACC_MODE, val); | |
984 | ||
985 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
986 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); | |
987 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
988 | ||
989 | val = 0; | |
990 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
991 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
992 | ||
993 | /* Build PORT_SDMA_CONFIG_REG */ | |
994 | val = 0; | |
995 | ||
996 | /* Default burst size */ | |
997 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
998 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 999 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1000 | |
9ad8fef6 TP |
1001 | #if defined(__BIG_ENDIAN) |
1002 | val |= MVNETA_DESC_SWAP; | |
1003 | #endif | |
c5aff182 TP |
1004 | |
1005 | /* Assign port SDMA configuration */ | |
1006 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1007 | ||
71408602 TP |
1008 | /* Disable PHY polling in hardware, since we're using the |
1009 | * kernel phylib to do this. | |
1010 | */ | |
1011 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1012 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1013 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1014 | ||
898b2970 SS |
1015 | if (pp->use_inband_status) { |
1016 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1017 | val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | | |
1018 | MVNETA_GMAC_FORCE_LINK_DOWN | | |
1019 | MVNETA_GMAC_AN_FLOW_CTRL_EN); | |
1020 | val |= MVNETA_GMAC_INBAND_AN_ENABLE | | |
1021 | MVNETA_GMAC_AN_SPEED_EN | | |
1022 | MVNETA_GMAC_AN_DUPLEX_EN; | |
1023 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1024 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1025 | val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1026 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
538761b7 SS |
1027 | } else { |
1028 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1029 | val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
1030 | MVNETA_GMAC_AN_SPEED_EN | | |
1031 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1032 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
898b2970 SS |
1033 | } |
1034 | ||
c5aff182 TP |
1035 | mvneta_set_ucast_table(pp, -1); |
1036 | mvneta_set_special_mcast_table(pp, -1); | |
1037 | mvneta_set_other_mcast_table(pp, -1); | |
1038 | ||
1039 | /* Set port interrupt enable register - default enable all */ | |
1040 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1041 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1042 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
1043 | } | |
1044 | ||
1045 | /* Set max sizes for tx queues */ | |
1046 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1047 | ||
1048 | { | |
1049 | u32 val, size, mtu; | |
1050 | int queue; | |
1051 | ||
1052 | mtu = max_tx_size * 8; | |
1053 | if (mtu > MVNETA_TX_MTU_MAX) | |
1054 | mtu = MVNETA_TX_MTU_MAX; | |
1055 | ||
1056 | /* Set MTU */ | |
1057 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1058 | val &= ~MVNETA_TX_MTU_MAX; | |
1059 | val |= mtu; | |
1060 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1061 | ||
1062 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1063 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1064 | ||
1065 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1066 | if (size < mtu) { | |
1067 | size = mtu; | |
1068 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1069 | val |= size; | |
1070 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1071 | } | |
1072 | for (queue = 0; queue < txq_number; queue++) { | |
1073 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1074 | ||
1075 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1076 | if (size < mtu) { | |
1077 | size = mtu; | |
1078 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1079 | val |= size; | |
1080 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1081 | } | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | /* Set unicast address */ | |
1086 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1087 | int queue) | |
1088 | { | |
1089 | unsigned int unicast_reg; | |
1090 | unsigned int tbl_offset; | |
1091 | unsigned int reg_offset; | |
1092 | ||
1093 | /* Locate the Unicast table entry */ | |
1094 | last_nibble = (0xf & last_nibble); | |
1095 | ||
1096 | /* offset from unicast tbl base */ | |
1097 | tbl_offset = (last_nibble / 4) * 4; | |
1098 | ||
1099 | /* offset within the above reg */ | |
1100 | reg_offset = last_nibble % 4; | |
1101 | ||
1102 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1103 | ||
1104 | if (queue == -1) { | |
1105 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1106 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1107 | } else { | |
1108 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1109 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1110 | } | |
1111 | ||
1112 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1113 | } | |
1114 | ||
1115 | /* Set mac address */ | |
1116 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1117 | int queue) | |
1118 | { | |
1119 | unsigned int mac_h; | |
1120 | unsigned int mac_l; | |
1121 | ||
1122 | if (queue != -1) { | |
1123 | mac_l = (addr[4] << 8) | (addr[5]); | |
1124 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1125 | (addr[2] << 8) | (addr[3] << 0); | |
1126 | ||
1127 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1128 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1129 | } | |
1130 | ||
1131 | /* Accept frames of this address */ | |
1132 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1133 | } | |
1134 | ||
6a20c175 TP |
1135 | /* Set the number of packets that will be received before RX interrupt |
1136 | * will be generated by HW. | |
c5aff182 TP |
1137 | */ |
1138 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1139 | struct mvneta_rx_queue *rxq, u32 value) | |
1140 | { | |
1141 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1142 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
1143 | rxq->pkts_coal = value; | |
1144 | } | |
1145 | ||
6a20c175 TP |
1146 | /* Set the time delay in usec before RX interrupt will be generated by |
1147 | * HW. | |
c5aff182 TP |
1148 | */ |
1149 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1150 | struct mvneta_rx_queue *rxq, u32 value) | |
1151 | { | |
189dd626 TP |
1152 | u32 val; |
1153 | unsigned long clk_rate; | |
1154 | ||
1155 | clk_rate = clk_get_rate(pp->clk); | |
1156 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1157 | |
1158 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
1159 | rxq->time_coal = value; | |
1160 | } | |
1161 | ||
1162 | /* Set threshold for TX_DONE pkts coalescing */ | |
1163 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1164 | struct mvneta_tx_queue *txq, u32 value) | |
1165 | { | |
1166 | u32 val; | |
1167 | ||
1168 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1169 | ||
1170 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1171 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1172 | ||
1173 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
1174 | ||
1175 | txq->done_pkts_coal = value; | |
1176 | } | |
1177 | ||
c5aff182 TP |
1178 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1179 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
1180 | u32 phys_addr, u32 cookie) | |
1181 | { | |
1182 | rx_desc->buf_cookie = cookie; | |
1183 | rx_desc->buf_phys_addr = phys_addr; | |
1184 | } | |
1185 | ||
1186 | /* Decrement sent descriptors counter */ | |
1187 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1188 | struct mvneta_tx_queue *txq, | |
1189 | int sent_desc) | |
1190 | { | |
1191 | u32 val; | |
1192 | ||
1193 | /* Only 255 TX descriptors can be updated at once */ | |
1194 | while (sent_desc > 0xff) { | |
1195 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1196 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1197 | sent_desc = sent_desc - 0xff; | |
1198 | } | |
1199 | ||
1200 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1201 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1202 | } | |
1203 | ||
1204 | /* Get number of TX descriptors already sent by HW */ | |
1205 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1206 | struct mvneta_tx_queue *txq) | |
1207 | { | |
1208 | u32 val; | |
1209 | int sent_desc; | |
1210 | ||
1211 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1212 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1213 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1214 | ||
1215 | return sent_desc; | |
1216 | } | |
1217 | ||
6a20c175 | 1218 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1219 | * The number of sent descriptors is returned. |
1220 | */ | |
1221 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1222 | struct mvneta_tx_queue *txq) | |
1223 | { | |
1224 | int sent_desc; | |
1225 | ||
1226 | /* Get number of sent descriptors */ | |
1227 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1228 | ||
1229 | /* Decrement sent descriptors counter */ | |
1230 | if (sent_desc) | |
1231 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1232 | ||
1233 | return sent_desc; | |
1234 | } | |
1235 | ||
1236 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1237 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1238 | int ip_hdr_len, int l4_proto) | |
1239 | { | |
1240 | u32 command; | |
1241 | ||
1242 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1243 | * G_L4_chk, L4_type; required only for checksum |
1244 | * calculation | |
1245 | */ | |
c5aff182 TP |
1246 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1247 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1248 | ||
0a198587 | 1249 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1250 | command |= MVNETA_TXD_IP_CSUM; |
1251 | else | |
1252 | command |= MVNETA_TX_L3_IP6; | |
1253 | ||
1254 | if (l4_proto == IPPROTO_TCP) | |
1255 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1256 | else if (l4_proto == IPPROTO_UDP) | |
1257 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1258 | else | |
1259 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1260 | ||
1261 | return command; | |
1262 | } | |
1263 | ||
1264 | ||
1265 | /* Display more error info */ | |
1266 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1267 | struct mvneta_rx_desc *rx_desc) | |
1268 | { | |
1269 | u32 status = rx_desc->status; | |
1270 | ||
5428213c | 1271 | if (!mvneta_rxq_desc_is_first_last(status)) { |
c5aff182 TP |
1272 | netdev_err(pp->dev, |
1273 | "bad rx status %08x (buffer oversize), size=%d\n", | |
5428213c | 1274 | status, rx_desc->data_size); |
c5aff182 TP |
1275 | return; |
1276 | } | |
1277 | ||
1278 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
1279 | case MVNETA_RXD_ERR_CRC: | |
1280 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1281 | status, rx_desc->data_size); | |
1282 | break; | |
1283 | case MVNETA_RXD_ERR_OVERRUN: | |
1284 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1285 | status, rx_desc->data_size); | |
1286 | break; | |
1287 | case MVNETA_RXD_ERR_LEN: | |
1288 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1289 | status, rx_desc->data_size); | |
1290 | break; | |
1291 | case MVNETA_RXD_ERR_RESOURCE: | |
1292 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1293 | status, rx_desc->data_size); | |
1294 | break; | |
1295 | } | |
1296 | } | |
1297 | ||
5428213c | 1298 | /* Handle RX checksum offload based on the descriptor's status */ |
1299 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1300 | struct sk_buff *skb) |
1301 | { | |
5428213c | 1302 | if ((status & MVNETA_RXD_L3_IP4) && |
1303 | (status & MVNETA_RXD_L4_CSUM_OK)) { | |
c5aff182 TP |
1304 | skb->csum = 0; |
1305 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1306 | return; | |
1307 | } | |
1308 | ||
1309 | skb->ip_summed = CHECKSUM_NONE; | |
1310 | } | |
1311 | ||
6c498974 | 1312 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1313 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1314 | * valid queue for matching the first one found in <cause>. | |
1315 | */ | |
c5aff182 TP |
1316 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1317 | u32 cause) | |
1318 | { | |
1319 | int queue = fls(cause) - 1; | |
1320 | ||
6c498974 | 1321 | return &pp->txqs[queue]; |
c5aff182 TP |
1322 | } |
1323 | ||
1324 | /* Free tx queue skbuffs */ | |
1325 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
1326 | struct mvneta_tx_queue *txq, int num) | |
1327 | { | |
1328 | int i; | |
1329 | ||
1330 | for (i = 0; i < num; i++) { | |
1331 | struct mvneta_tx_desc *tx_desc = txq->descs + | |
1332 | txq->txq_get_index; | |
1333 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; | |
1334 | ||
1335 | mvneta_txq_inc_get(txq); | |
1336 | ||
2e3173a3 EG |
1337 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
1338 | dma_unmap_single(pp->dev->dev.parent, | |
1339 | tx_desc->buf_phys_addr, | |
1340 | tx_desc->data_size, DMA_TO_DEVICE); | |
ba7e46ef EG |
1341 | if (!skb) |
1342 | continue; | |
c5aff182 TP |
1343 | dev_kfree_skb_any(skb); |
1344 | } | |
1345 | } | |
1346 | ||
1347 | /* Handle end of transmission */ | |
cd713199 | 1348 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1349 | struct mvneta_tx_queue *txq) |
1350 | { | |
1351 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1352 | int tx_done; | |
1353 | ||
1354 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1355 | if (!tx_done) |
1356 | return; | |
1357 | ||
c5aff182 TP |
1358 | mvneta_txq_bufs_free(pp, txq, tx_done); |
1359 | ||
1360 | txq->count -= tx_done; | |
1361 | ||
1362 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1363 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1364 | netif_tx_wake_queue(nq); |
1365 | } | |
c5aff182 TP |
1366 | } |
1367 | ||
8ec2cd48 | 1368 | static void *mvneta_frag_alloc(const struct mvneta_port *pp) |
1369 | { | |
1370 | if (likely(pp->frag_size <= PAGE_SIZE)) | |
1371 | return netdev_alloc_frag(pp->frag_size); | |
1372 | else | |
1373 | return kmalloc(pp->frag_size, GFP_ATOMIC); | |
1374 | } | |
1375 | ||
1376 | static void mvneta_frag_free(const struct mvneta_port *pp, void *data) | |
1377 | { | |
1378 | if (likely(pp->frag_size <= PAGE_SIZE)) | |
13dc0d2b | 1379 | skb_free_frag(data); |
8ec2cd48 | 1380 | else |
1381 | kfree(data); | |
1382 | } | |
1383 | ||
c5aff182 TP |
1384 | /* Refill processing */ |
1385 | static int mvneta_rx_refill(struct mvneta_port *pp, | |
1386 | struct mvneta_rx_desc *rx_desc) | |
1387 | ||
1388 | { | |
1389 | dma_addr_t phys_addr; | |
8ec2cd48 | 1390 | void *data; |
c5aff182 | 1391 | |
8ec2cd48 | 1392 | data = mvneta_frag_alloc(pp); |
1393 | if (!data) | |
c5aff182 TP |
1394 | return -ENOMEM; |
1395 | ||
8ec2cd48 | 1396 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
c5aff182 TP |
1397 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
1398 | DMA_FROM_DEVICE); | |
1399 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { | |
8ec2cd48 | 1400 | mvneta_frag_free(pp, data); |
c5aff182 TP |
1401 | return -ENOMEM; |
1402 | } | |
1403 | ||
8ec2cd48 | 1404 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); |
c5aff182 TP |
1405 | return 0; |
1406 | } | |
1407 | ||
1408 | /* Handle tx checksum */ | |
1409 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1410 | { | |
1411 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1412 | int ip_hdr_len = 0; | |
817dbfa5 | 1413 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1414 | u8 l4_proto; |
1415 | ||
817dbfa5 | 1416 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1417 | struct iphdr *ip4h = ip_hdr(skb); |
1418 | ||
1419 | /* Calculate IPv4 checksum and L4 checksum */ | |
1420 | ip_hdr_len = ip4h->ihl; | |
1421 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1422 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1423 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1424 | ||
1425 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1426 | if (skb_network_header_len(skb) > 0) | |
1427 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1428 | l4_proto = ip6h->nexthdr; | |
1429 | } else | |
1430 | return MVNETA_TX_L4_CSUM_NOT; | |
1431 | ||
1432 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1433 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1434 | } |
1435 | ||
1436 | return MVNETA_TX_L4_CSUM_NOT; | |
1437 | } | |
1438 | ||
6a20c175 | 1439 | /* Returns rx queue pointer (find last set bit) according to causeRxTx |
c5aff182 TP |
1440 | * value |
1441 | */ | |
1442 | static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp, | |
1443 | u32 cause) | |
1444 | { | |
1445 | int queue = fls(cause >> 8) - 1; | |
1446 | ||
1447 | return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue]; | |
1448 | } | |
1449 | ||
1450 | /* Drop packets received by the RXQ and free buffers */ | |
1451 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1452 | struct mvneta_rx_queue *rxq) | |
1453 | { | |
1454 | int rx_done, i; | |
1455 | ||
1456 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1457 | for (i = 0; i < rxq->size; i++) { | |
1458 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
8ec2cd48 | 1459 | void *data = (void *)rx_desc->buf_cookie; |
c5aff182 | 1460 | |
8ec2cd48 | 1461 | mvneta_frag_free(pp, data); |
c5aff182 | 1462 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
a328f3a0 | 1463 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
c5aff182 TP |
1464 | } |
1465 | ||
1466 | if (rx_done) | |
1467 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1468 | } | |
1469 | ||
1470 | /* Main rx processing */ | |
1471 | static int mvneta_rx(struct mvneta_port *pp, int rx_todo, | |
1472 | struct mvneta_rx_queue *rxq) | |
1473 | { | |
12bb03b4 | 1474 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 | 1475 | struct net_device *dev = pp->dev; |
a84e3289 | 1476 | int rx_done; |
dc4277dd | 1477 | u32 rcvd_pkts = 0; |
1478 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
1479 | |
1480 | /* Get number of received packets */ | |
1481 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1482 | ||
1483 | if (rx_todo > rx_done) | |
1484 | rx_todo = rx_done; | |
1485 | ||
1486 | rx_done = 0; | |
c5aff182 TP |
1487 | |
1488 | /* Fairness NAPI loop */ | |
1489 | while (rx_done < rx_todo) { | |
1490 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1491 | struct sk_buff *skb; | |
8ec2cd48 | 1492 | unsigned char *data; |
daf158d0 | 1493 | dma_addr_t phys_addr; |
c5aff182 TP |
1494 | u32 rx_status; |
1495 | int rx_bytes, err; | |
1496 | ||
c5aff182 | 1497 | rx_done++; |
c5aff182 | 1498 | rx_status = rx_desc->status; |
f19fadfc | 1499 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
8ec2cd48 | 1500 | data = (unsigned char *)rx_desc->buf_cookie; |
daf158d0 | 1501 | phys_addr = rx_desc->buf_phys_addr; |
c5aff182 | 1502 | |
5428213c | 1503 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 1504 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
1505 | err_drop_frame: | |
c5aff182 TP |
1506 | dev->stats.rx_errors++; |
1507 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 1508 | /* leave the descriptor untouched */ |
c5aff182 TP |
1509 | continue; |
1510 | } | |
1511 | ||
f19fadfc | 1512 | if (rx_bytes <= rx_copybreak) { |
1513 | /* better copy a small frame and not unmap the DMA region */ | |
1514 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
1515 | if (unlikely(!skb)) | |
1516 | goto err_drop_frame; | |
1517 | ||
1518 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
1519 | rx_desc->buf_phys_addr, | |
1520 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
1521 | rx_bytes, | |
1522 | DMA_FROM_DEVICE); | |
1523 | memcpy(skb_put(skb, rx_bytes), | |
1524 | data + MVNETA_MH_SIZE + NET_SKB_PAD, | |
1525 | rx_bytes); | |
1526 | ||
1527 | skb->protocol = eth_type_trans(skb, dev); | |
1528 | mvneta_rx_csum(pp, rx_status, skb); | |
12bb03b4 | 1529 | napi_gro_receive(&port->napi, skb); |
f19fadfc | 1530 | |
1531 | rcvd_pkts++; | |
1532 | rcvd_bytes += rx_bytes; | |
1533 | ||
1534 | /* leave the descriptor and buffer untouched */ | |
1535 | continue; | |
1536 | } | |
1537 | ||
a84e3289 SG |
1538 | /* Refill processing */ |
1539 | err = mvneta_rx_refill(pp, rx_desc); | |
1540 | if (err) { | |
1541 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
1542 | rxq->missed++; | |
1543 | goto err_drop_frame; | |
1544 | } | |
1545 | ||
f19fadfc | 1546 | skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); |
1547 | if (!skb) | |
1548 | goto err_drop_frame; | |
1549 | ||
daf158d0 | 1550 | dma_unmap_single(dev->dev.parent, phys_addr, |
a328f3a0 | 1551 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
c5aff182 | 1552 | |
dc4277dd | 1553 | rcvd_pkts++; |
1554 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
1555 | |
1556 | /* Linux processing */ | |
8ec2cd48 | 1557 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
1558 | skb_put(skb, rx_bytes); |
1559 | ||
1560 | skb->protocol = eth_type_trans(skb, dev); | |
1561 | ||
5428213c | 1562 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 1563 | |
12bb03b4 | 1564 | napi_gro_receive(&port->napi, skb); |
c5aff182 TP |
1565 | } |
1566 | ||
dc4277dd | 1567 | if (rcvd_pkts) { |
74c41b04 | 1568 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
1569 | ||
1570 | u64_stats_update_begin(&stats->syncp); | |
1571 | stats->rx_packets += rcvd_pkts; | |
1572 | stats->rx_bytes += rcvd_bytes; | |
1573 | u64_stats_update_end(&stats->syncp); | |
dc4277dd | 1574 | } |
1575 | ||
c5aff182 | 1576 | /* Update rxq management counters */ |
a84e3289 | 1577 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
1578 | |
1579 | return rx_done; | |
1580 | } | |
1581 | ||
2adb719d EG |
1582 | static inline void |
1583 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
1584 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
1585 | { | |
1586 | struct mvneta_tx_desc *tx_desc; | |
1587 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1588 | ||
1589 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1590 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1591 | tx_desc->data_size = hdr_len; | |
1592 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
1593 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
1594 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
1595 | txq->txq_put_index * TSO_HEADER_SIZE; | |
1596 | mvneta_txq_inc_put(txq); | |
1597 | } | |
1598 | ||
1599 | static inline int | |
1600 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
1601 | struct sk_buff *skb, char *data, int size, | |
1602 | bool last_tcp, bool is_last) | |
1603 | { | |
1604 | struct mvneta_tx_desc *tx_desc; | |
1605 | ||
1606 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1607 | tx_desc->data_size = size; | |
1608 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
1609 | size, DMA_TO_DEVICE); | |
1610 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
1611 | tx_desc->buf_phys_addr))) { | |
1612 | mvneta_txq_desc_put(txq); | |
1613 | return -ENOMEM; | |
1614 | } | |
1615 | ||
1616 | tx_desc->command = 0; | |
1617 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1618 | ||
1619 | if (last_tcp) { | |
1620 | /* last descriptor in the TCP packet */ | |
1621 | tx_desc->command = MVNETA_TXD_L_DESC; | |
1622 | ||
1623 | /* last descriptor in SKB */ | |
1624 | if (is_last) | |
1625 | txq->tx_skb[txq->txq_put_index] = skb; | |
1626 | } | |
1627 | mvneta_txq_inc_put(txq); | |
1628 | return 0; | |
1629 | } | |
1630 | ||
1631 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
1632 | struct mvneta_tx_queue *txq) | |
1633 | { | |
1634 | int total_len, data_left; | |
1635 | int desc_count = 0; | |
1636 | struct mvneta_port *pp = netdev_priv(dev); | |
1637 | struct tso_t tso; | |
1638 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1639 | int i; | |
1640 | ||
1641 | /* Count needed descriptors */ | |
1642 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
1643 | return 0; | |
1644 | ||
1645 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
1646 | pr_info("*** Is this even possible???!?!?\n"); | |
1647 | return 0; | |
1648 | } | |
1649 | ||
1650 | /* Initialize the TSO handler, and prepare the first payload */ | |
1651 | tso_start(skb, &tso); | |
1652 | ||
1653 | total_len = skb->len - hdr_len; | |
1654 | while (total_len > 0) { | |
1655 | char *hdr; | |
1656 | ||
1657 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
1658 | total_len -= data_left; | |
1659 | desc_count++; | |
1660 | ||
1661 | /* prepare packet headers: MAC + IP + TCP */ | |
1662 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
1663 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
1664 | ||
1665 | mvneta_tso_put_hdr(skb, pp, txq); | |
1666 | ||
1667 | while (data_left > 0) { | |
1668 | int size; | |
1669 | desc_count++; | |
1670 | ||
1671 | size = min_t(int, tso.size, data_left); | |
1672 | ||
1673 | if (mvneta_tso_put_data(dev, txq, skb, | |
1674 | tso.data, size, | |
1675 | size == data_left, | |
1676 | total_len == 0)) | |
1677 | goto err_release; | |
1678 | data_left -= size; | |
1679 | ||
1680 | tso_build_data(skb, &tso, size); | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | return desc_count; | |
1685 | ||
1686 | err_release: | |
1687 | /* Release all used data descriptors; header descriptors must not | |
1688 | * be DMA-unmapped. | |
1689 | */ | |
1690 | for (i = desc_count - 1; i >= 0; i--) { | |
1691 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 1692 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
1693 | dma_unmap_single(pp->dev->dev.parent, |
1694 | tx_desc->buf_phys_addr, | |
1695 | tx_desc->data_size, | |
1696 | DMA_TO_DEVICE); | |
1697 | mvneta_txq_desc_put(txq); | |
1698 | } | |
1699 | return 0; | |
1700 | } | |
1701 | ||
c5aff182 TP |
1702 | /* Handle tx fragmentation processing */ |
1703 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
1704 | struct mvneta_tx_queue *txq) | |
1705 | { | |
1706 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 1707 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 1708 | |
3d4ea02f | 1709 | for (i = 0; i < nr_frags; i++) { |
c5aff182 TP |
1710 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1711 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
1712 | ||
1713 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1714 | tx_desc->data_size = frag->size; | |
1715 | ||
1716 | tx_desc->buf_phys_addr = | |
1717 | dma_map_single(pp->dev->dev.parent, addr, | |
1718 | tx_desc->data_size, DMA_TO_DEVICE); | |
1719 | ||
1720 | if (dma_mapping_error(pp->dev->dev.parent, | |
1721 | tx_desc->buf_phys_addr)) { | |
1722 | mvneta_txq_desc_put(txq); | |
1723 | goto error; | |
1724 | } | |
1725 | ||
3d4ea02f | 1726 | if (i == nr_frags - 1) { |
c5aff182 TP |
1727 | /* Last descriptor */ |
1728 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
c5aff182 | 1729 | txq->tx_skb[txq->txq_put_index] = skb; |
c5aff182 TP |
1730 | } else { |
1731 | /* Descriptor in the middle: Not First, Not Last */ | |
1732 | tx_desc->command = 0; | |
c5aff182 | 1733 | txq->tx_skb[txq->txq_put_index] = NULL; |
c5aff182 | 1734 | } |
3d4ea02f | 1735 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
1736 | } |
1737 | ||
1738 | return 0; | |
1739 | ||
1740 | error: | |
1741 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
1742 | * this packet, as well as the corresponding DMA mappings |
1743 | */ | |
c5aff182 TP |
1744 | for (i = i - 1; i >= 0; i--) { |
1745 | tx_desc = txq->descs + i; | |
1746 | dma_unmap_single(pp->dev->dev.parent, | |
1747 | tx_desc->buf_phys_addr, | |
1748 | tx_desc->data_size, | |
1749 | DMA_TO_DEVICE); | |
1750 | mvneta_txq_desc_put(txq); | |
1751 | } | |
1752 | ||
1753 | return -ENOMEM; | |
1754 | } | |
1755 | ||
1756 | /* Main tx processing */ | |
1757 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) | |
1758 | { | |
1759 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
1760 | u16 txq_id = skb_get_queue_mapping(skb); |
1761 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
c5aff182 | 1762 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 1763 | int len = skb->len; |
c5aff182 TP |
1764 | int frags = 0; |
1765 | u32 tx_cmd; | |
1766 | ||
1767 | if (!netif_running(dev)) | |
1768 | goto out; | |
1769 | ||
2adb719d EG |
1770 | if (skb_is_gso(skb)) { |
1771 | frags = mvneta_tx_tso(skb, dev, txq); | |
1772 | goto out; | |
1773 | } | |
1774 | ||
c5aff182 | 1775 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
1776 | |
1777 | /* Get a descriptor for the first part of the packet */ | |
1778 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1779 | ||
1780 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
1781 | ||
1782 | tx_desc->data_size = skb_headlen(skb); | |
1783 | ||
1784 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
1785 | tx_desc->data_size, | |
1786 | DMA_TO_DEVICE); | |
1787 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
1788 | tx_desc->buf_phys_addr))) { | |
1789 | mvneta_txq_desc_put(txq); | |
1790 | frags = 0; | |
1791 | goto out; | |
1792 | } | |
1793 | ||
1794 | if (frags == 1) { | |
1795 | /* First and Last descriptor */ | |
1796 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
1797 | tx_desc->command = tx_cmd; | |
1798 | txq->tx_skb[txq->txq_put_index] = skb; | |
1799 | mvneta_txq_inc_put(txq); | |
1800 | } else { | |
1801 | /* First but not Last */ | |
1802 | tx_cmd |= MVNETA_TXD_F_DESC; | |
1803 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1804 | mvneta_txq_inc_put(txq); | |
1805 | tx_desc->command = tx_cmd; | |
1806 | /* Continue with other skb fragments */ | |
1807 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
1808 | dma_unmap_single(dev->dev.parent, | |
1809 | tx_desc->buf_phys_addr, | |
1810 | tx_desc->data_size, | |
1811 | DMA_TO_DEVICE); | |
1812 | mvneta_txq_desc_put(txq); | |
1813 | frags = 0; | |
1814 | goto out; | |
1815 | } | |
1816 | } | |
1817 | ||
c5aff182 TP |
1818 | out: |
1819 | if (frags > 0) { | |
74c41b04 | 1820 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
e19d2dda EG |
1821 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
1822 | ||
1823 | txq->count += frags; | |
1824 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
1825 | ||
8eef5f97 | 1826 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 1827 | netif_tx_stop_queue(nq); |
c5aff182 | 1828 | |
74c41b04 | 1829 | u64_stats_update_begin(&stats->syncp); |
1830 | stats->tx_packets++; | |
5f478b41 | 1831 | stats->tx_bytes += len; |
74c41b04 | 1832 | u64_stats_update_end(&stats->syncp); |
c5aff182 TP |
1833 | } else { |
1834 | dev->stats.tx_dropped++; | |
1835 | dev_kfree_skb_any(skb); | |
1836 | } | |
1837 | ||
c5aff182 TP |
1838 | return NETDEV_TX_OK; |
1839 | } | |
1840 | ||
1841 | ||
1842 | /* Free tx resources, when resetting a port */ | |
1843 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
1844 | struct mvneta_tx_queue *txq) | |
1845 | ||
1846 | { | |
1847 | int tx_done = txq->count; | |
1848 | ||
1849 | mvneta_txq_bufs_free(pp, txq, tx_done); | |
1850 | ||
1851 | /* reset txq */ | |
1852 | txq->count = 0; | |
1853 | txq->txq_put_index = 0; | |
1854 | txq->txq_get_index = 0; | |
1855 | } | |
1856 | ||
6c498974 | 1857 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
1858 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
1859 | */ | |
0713a86a | 1860 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
1861 | { |
1862 | struct mvneta_tx_queue *txq; | |
c5aff182 TP |
1863 | struct netdev_queue *nq; |
1864 | ||
6c498974 | 1865 | while (cause_tx_done) { |
c5aff182 | 1866 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
1867 | |
1868 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1869 | __netif_tx_lock(nq, smp_processor_id()); | |
1870 | ||
0713a86a AE |
1871 | if (txq->count) |
1872 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
1873 | |
1874 | __netif_tx_unlock(nq); | |
1875 | cause_tx_done &= ~((1 << txq->id)); | |
1876 | } | |
c5aff182 TP |
1877 | } |
1878 | ||
6a20c175 | 1879 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
1880 | * according to hw spec, different than generic crc8 algorithm |
1881 | */ | |
1882 | static int mvneta_addr_crc(unsigned char *addr) | |
1883 | { | |
1884 | int crc = 0; | |
1885 | int i; | |
1886 | ||
1887 | for (i = 0; i < ETH_ALEN; i++) { | |
1888 | int j; | |
1889 | ||
1890 | crc = (crc ^ addr[i]) << 8; | |
1891 | for (j = 7; j >= 0; j--) { | |
1892 | if (crc & (0x100 << j)) | |
1893 | crc ^= 0x107 << j; | |
1894 | } | |
1895 | } | |
1896 | ||
1897 | return crc; | |
1898 | } | |
1899 | ||
1900 | /* This method controls the net device special MAC multicast support. | |
1901 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
1902 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
1903 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1904 | * Table entries in the DA-Filter table. This method set the Special | |
1905 | * Multicast Table appropriate entry. | |
1906 | */ | |
1907 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
1908 | unsigned char last_byte, | |
1909 | int queue) | |
1910 | { | |
1911 | unsigned int smc_table_reg; | |
1912 | unsigned int tbl_offset; | |
1913 | unsigned int reg_offset; | |
1914 | ||
1915 | /* Register offset from SMC table base */ | |
1916 | tbl_offset = (last_byte / 4); | |
1917 | /* Entry offset within the above reg */ | |
1918 | reg_offset = last_byte % 4; | |
1919 | ||
1920 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
1921 | + tbl_offset * 4)); | |
1922 | ||
1923 | if (queue == -1) | |
1924 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1925 | else { | |
1926 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1927 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1928 | } | |
1929 | ||
1930 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
1931 | smc_table_reg); | |
1932 | } | |
1933 | ||
1934 | /* This method controls the network device Other MAC multicast support. | |
1935 | * The Other Multicast Table is used for multicast of another type. | |
1936 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
1937 | * in the DA-Filter table. | |
1938 | * The method gets the CRC-8 value from the calling routine and | |
1939 | * sets the Other Multicast Table appropriate entry according to the | |
1940 | * specified CRC-8 . | |
1941 | */ | |
1942 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
1943 | unsigned char crc8, | |
1944 | int queue) | |
1945 | { | |
1946 | unsigned int omc_table_reg; | |
1947 | unsigned int tbl_offset; | |
1948 | unsigned int reg_offset; | |
1949 | ||
1950 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
1951 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
1952 | ||
1953 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
1954 | ||
1955 | if (queue == -1) { | |
1956 | /* Clear accepts frame bit at specified Other DA table entry */ | |
1957 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1958 | } else { | |
1959 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1960 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1961 | } | |
1962 | ||
1963 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
1964 | } | |
1965 | ||
1966 | /* The network device supports multicast using two tables: | |
1967 | * 1) Special Multicast Table for MAC addresses of the form | |
1968 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
1969 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1970 | * Table entries in the DA-Filter table. | |
1971 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
1972 | * is used as an index to the Other Multicast Table entries in the | |
1973 | * DA-Filter table. | |
1974 | */ | |
1975 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
1976 | int queue) | |
1977 | { | |
1978 | unsigned char crc_result = 0; | |
1979 | ||
1980 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
1981 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
1982 | return 0; | |
1983 | } | |
1984 | ||
1985 | crc_result = mvneta_addr_crc(p_addr); | |
1986 | if (queue == -1) { | |
1987 | if (pp->mcast_count[crc_result] == 0) { | |
1988 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
1989 | crc_result); | |
1990 | return -EINVAL; | |
1991 | } | |
1992 | ||
1993 | pp->mcast_count[crc_result]--; | |
1994 | if (pp->mcast_count[crc_result] != 0) { | |
1995 | netdev_info(pp->dev, | |
1996 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
1997 | pp->mcast_count[crc_result], crc_result); | |
1998 | return -EINVAL; | |
1999 | } | |
2000 | } else | |
2001 | pp->mcast_count[crc_result]++; | |
2002 | ||
2003 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2004 | ||
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | /* Configure Fitering mode of Ethernet port */ | |
2009 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2010 | int is_promisc) | |
2011 | { | |
2012 | u32 port_cfg_reg, val; | |
2013 | ||
2014 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2015 | ||
2016 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2017 | ||
2018 | /* Set / Clear UPM bit in port configuration register */ | |
2019 | if (is_promisc) { | |
2020 | /* Accept all Unicast addresses */ | |
2021 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2022 | val |= MVNETA_FORCE_UNI; | |
2023 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2024 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2025 | } else { | |
2026 | /* Reject all Unicast addresses */ | |
2027 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2028 | val &= ~MVNETA_FORCE_UNI; | |
2029 | } | |
2030 | ||
2031 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2032 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2033 | } | |
2034 | ||
2035 | /* register unicast and multicast addresses */ | |
2036 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2037 | { | |
2038 | struct mvneta_port *pp = netdev_priv(dev); | |
2039 | struct netdev_hw_addr *ha; | |
2040 | ||
2041 | if (dev->flags & IFF_PROMISC) { | |
2042 | /* Accept all: Multicast + Unicast */ | |
2043 | mvneta_rx_unicast_promisc_set(pp, 1); | |
2044 | mvneta_set_ucast_table(pp, rxq_def); | |
2045 | mvneta_set_special_mcast_table(pp, rxq_def); | |
2046 | mvneta_set_other_mcast_table(pp, rxq_def); | |
2047 | } else { | |
2048 | /* Accept single Unicast */ | |
2049 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2050 | mvneta_set_ucast_table(pp, -1); | |
2051 | mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); | |
2052 | ||
2053 | if (dev->flags & IFF_ALLMULTI) { | |
2054 | /* Accept all multicast */ | |
2055 | mvneta_set_special_mcast_table(pp, rxq_def); | |
2056 | mvneta_set_other_mcast_table(pp, rxq_def); | |
2057 | } else { | |
2058 | /* Accept only initialized multicast */ | |
2059 | mvneta_set_special_mcast_table(pp, -1); | |
2060 | mvneta_set_other_mcast_table(pp, -1); | |
2061 | ||
2062 | if (!netdev_mc_empty(dev)) { | |
2063 | netdev_for_each_mc_addr(ha, dev) { | |
2064 | mvneta_mcast_addr_set(pp, ha->addr, | |
2065 | rxq_def); | |
2066 | } | |
2067 | } | |
2068 | } | |
2069 | } | |
2070 | } | |
2071 | ||
2072 | /* Interrupt handling - the callback for request_irq() */ | |
2073 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2074 | { | |
12bb03b4 | 2075 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2076 | |
12bb03b4 | 2077 | disable_percpu_irq(port->pp->dev->irq); |
c5aff182 | 2078 | |
12bb03b4 | 2079 | napi_schedule(&port->napi); |
c5aff182 TP |
2080 | |
2081 | return IRQ_HANDLED; | |
2082 | } | |
2083 | ||
898b2970 SS |
2084 | static int mvneta_fixed_link_update(struct mvneta_port *pp, |
2085 | struct phy_device *phy) | |
2086 | { | |
2087 | struct fixed_phy_status status; | |
2088 | struct fixed_phy_status changed = {}; | |
2089 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); | |
2090 | ||
2091 | status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
2092 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) | |
2093 | status.speed = SPEED_1000; | |
2094 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) | |
2095 | status.speed = SPEED_100; | |
2096 | else | |
2097 | status.speed = SPEED_10; | |
2098 | status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
2099 | changed.link = 1; | |
2100 | changed.speed = 1; | |
2101 | changed.duplex = 1; | |
2102 | fixed_phy_update_state(phy, &status, &changed); | |
2103 | return 0; | |
2104 | } | |
2105 | ||
c5aff182 TP |
2106 | /* NAPI handler |
2107 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
2108 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
2109 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
2110 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
2111 | * Each CPU has its own causeRxTx register | |
2112 | */ | |
2113 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
2114 | { | |
2115 | int rx_done = 0; | |
2116 | u32 cause_rx_tx; | |
c5aff182 | 2117 | struct mvneta_port *pp = netdev_priv(napi->dev); |
12bb03b4 | 2118 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
2119 | |
2120 | if (!netif_running(pp->dev)) { | |
12bb03b4 | 2121 | napi_complete(&port->napi); |
c5aff182 TP |
2122 | return rx_done; |
2123 | } | |
2124 | ||
2125 | /* Read cause register */ | |
898b2970 SS |
2126 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
2127 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
2128 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
2129 | ||
2130 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2131 | if (pp->use_inband_status && (cause_misc & | |
2132 | (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2133 | MVNETA_CAUSE_LINK_CHANGE | | |
2134 | MVNETA_CAUSE_PSC_SYNC_CHANGE))) { | |
2135 | mvneta_fixed_link_update(pp, pp->phy_dev); | |
2136 | } | |
2137 | } | |
71f6d1b3 | 2138 | |
2139 | /* Release Tx descriptors */ | |
2140 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 2141 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 2142 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
2143 | } | |
c5aff182 | 2144 | |
6a20c175 | 2145 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
2146 | * RX packets |
2147 | */ | |
12bb03b4 | 2148 | cause_rx_tx |= port->cause_rx_tx; |
c5aff182 | 2149 | if (rxq_number > 1) { |
71f6d1b3 | 2150 | while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) { |
c5aff182 TP |
2151 | int count; |
2152 | struct mvneta_rx_queue *rxq; | |
2153 | /* get rx queue number from cause_rx_tx */ | |
2154 | rxq = mvneta_rx_policy(pp, cause_rx_tx); | |
2155 | if (!rxq) | |
2156 | break; | |
2157 | ||
2158 | /* process the packet in that rx queue */ | |
2159 | count = mvneta_rx(pp, budget, rxq); | |
2160 | rx_done += count; | |
2161 | budget -= count; | |
2162 | if (budget > 0) { | |
6a20c175 TP |
2163 | /* set off the rx bit of the |
2164 | * corresponding bit in the cause rx | |
2165 | * tx register, so that next iteration | |
2166 | * will find the next rx queue where | |
2167 | * packets are received on | |
2168 | */ | |
c5aff182 TP |
2169 | cause_rx_tx &= ~((1 << rxq->id) << 8); |
2170 | } | |
2171 | } | |
2172 | } else { | |
2173 | rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); | |
2174 | budget -= rx_done; | |
2175 | } | |
2176 | ||
2177 | if (budget > 0) { | |
2178 | cause_rx_tx = 0; | |
12bb03b4 MR |
2179 | napi_complete(&port->napi); |
2180 | enable_percpu_irq(pp->dev->irq, 0); | |
c5aff182 TP |
2181 | } |
2182 | ||
12bb03b4 | 2183 | port->cause_rx_tx = cause_rx_tx; |
c5aff182 TP |
2184 | return rx_done; |
2185 | } | |
2186 | ||
c5aff182 TP |
2187 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
2188 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2189 | int num) | |
2190 | { | |
c5aff182 TP |
2191 | int i; |
2192 | ||
2193 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 2194 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
2195 | if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { | |
2196 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", | |
c5aff182 TP |
2197 | __func__, rxq->id, i, num); |
2198 | break; | |
2199 | } | |
c5aff182 TP |
2200 | } |
2201 | ||
2202 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
2203 | * get packets) |
2204 | */ | |
c5aff182 TP |
2205 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
2206 | ||
2207 | return i; | |
2208 | } | |
2209 | ||
2210 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
2211 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
2212 | { | |
2213 | int queue; | |
2214 | ||
9672850b | 2215 | /* free the skb's in the tx ring */ |
c5aff182 TP |
2216 | for (queue = 0; queue < txq_number; queue++) |
2217 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
2218 | ||
2219 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
2220 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
2221 | } | |
2222 | ||
2223 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
2224 | { | |
2225 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
2226 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
2227 | } | |
2228 | ||
2229 | /* Rx/Tx queue initialization/cleanup methods */ | |
2230 | ||
2231 | /* Create a specified RX queue */ | |
2232 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
2233 | struct mvneta_rx_queue *rxq) | |
2234 | ||
2235 | { | |
2236 | rxq->size = pp->rx_ring_size; | |
2237 | ||
2238 | /* Allocate memory for RX descriptors */ | |
2239 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2240 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2241 | &rxq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2242 | if (rxq->descs == NULL) |
c5aff182 | 2243 | return -ENOMEM; |
c5aff182 TP |
2244 | |
2245 | BUG_ON(rxq->descs != | |
2246 | PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | |
2247 | ||
2248 | rxq->last_desc = rxq->size - 1; | |
2249 | ||
2250 | /* Set Rx descriptors queue starting address */ | |
2251 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
2252 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
2253 | ||
2254 | /* Set Offset */ | |
2255 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); | |
2256 | ||
2257 | /* Set coalescing pkts and time */ | |
2258 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2259 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2260 | ||
2261 | /* Fill RXQ with buffers from RX pool */ | |
2262 | mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); | |
2263 | mvneta_rxq_bm_disable(pp, rxq); | |
2264 | mvneta_rxq_fill(pp, rxq, rxq->size); | |
2265 | ||
2266 | return 0; | |
2267 | } | |
2268 | ||
2269 | /* Cleanup Rx queue */ | |
2270 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
2271 | struct mvneta_rx_queue *rxq) | |
2272 | { | |
2273 | mvneta_rxq_drop_pkts(pp, rxq); | |
2274 | ||
2275 | if (rxq->descs) | |
2276 | dma_free_coherent(pp->dev->dev.parent, | |
2277 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2278 | rxq->descs, | |
2279 | rxq->descs_phys); | |
2280 | ||
2281 | rxq->descs = NULL; | |
2282 | rxq->last_desc = 0; | |
2283 | rxq->next_desc_to_proc = 0; | |
2284 | rxq->descs_phys = 0; | |
2285 | } | |
2286 | ||
2287 | /* Create and initialize a tx queue */ | |
2288 | static int mvneta_txq_init(struct mvneta_port *pp, | |
2289 | struct mvneta_tx_queue *txq) | |
2290 | { | |
2291 | txq->size = pp->tx_ring_size; | |
2292 | ||
8eef5f97 EG |
2293 | /* A queue must always have room for at least one skb. |
2294 | * Therefore, stop the queue when the free entries reaches | |
2295 | * the maximum number of descriptors per skb. | |
2296 | */ | |
2297 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
2298 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
2299 | ||
2300 | ||
c5aff182 TP |
2301 | /* Allocate memory for TX descriptors */ |
2302 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2303 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2304 | &txq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2305 | if (txq->descs == NULL) |
c5aff182 | 2306 | return -ENOMEM; |
c5aff182 TP |
2307 | |
2308 | /* Make sure descriptor address is cache line size aligned */ | |
2309 | BUG_ON(txq->descs != | |
2310 | PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | |
2311 | ||
2312 | txq->last_desc = txq->size - 1; | |
2313 | ||
2314 | /* Set maximum bandwidth for enabled TXQs */ | |
2315 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
2316 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
2317 | ||
2318 | /* Set Tx descriptors queue starting address */ | |
2319 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
2320 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
2321 | ||
2322 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); | |
2323 | if (txq->tx_skb == NULL) { | |
2324 | dma_free_coherent(pp->dev->dev.parent, | |
2325 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2326 | txq->descs, txq->descs_phys); | |
2327 | return -ENOMEM; | |
2328 | } | |
2adb719d EG |
2329 | |
2330 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
2331 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
2332 | txq->size * TSO_HEADER_SIZE, | |
2333 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
2334 | if (txq->tso_hdrs == NULL) { | |
2335 | kfree(txq->tx_skb); | |
2336 | dma_free_coherent(pp->dev->dev.parent, | |
2337 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2338 | txq->descs, txq->descs_phys); | |
2339 | return -ENOMEM; | |
2340 | } | |
c5aff182 TP |
2341 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
2342 | ||
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
2347 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
2348 | struct mvneta_tx_queue *txq) | |
2349 | { | |
2350 | kfree(txq->tx_skb); | |
2351 | ||
2adb719d EG |
2352 | if (txq->tso_hdrs) |
2353 | dma_free_coherent(pp->dev->dev.parent, | |
2354 | txq->size * TSO_HEADER_SIZE, | |
2355 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
2356 | if (txq->descs) |
2357 | dma_free_coherent(pp->dev->dev.parent, | |
2358 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2359 | txq->descs, txq->descs_phys); | |
2360 | ||
2361 | txq->descs = NULL; | |
2362 | txq->last_desc = 0; | |
2363 | txq->next_desc_to_proc = 0; | |
2364 | txq->descs_phys = 0; | |
2365 | ||
2366 | /* Set minimum bandwidth for disabled TXQs */ | |
2367 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
2368 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
2369 | ||
2370 | /* Set Tx descriptors queue starting address and size */ | |
2371 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
2372 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
2373 | } | |
2374 | ||
2375 | /* Cleanup all Tx queues */ | |
2376 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
2377 | { | |
2378 | int queue; | |
2379 | ||
2380 | for (queue = 0; queue < txq_number; queue++) | |
2381 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
2382 | } | |
2383 | ||
2384 | /* Cleanup all Rx queues */ | |
2385 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
2386 | { | |
2387 | int queue; | |
2388 | ||
2389 | for (queue = 0; queue < rxq_number; queue++) | |
2390 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
2391 | } | |
2392 | ||
2393 | ||
2394 | /* Init all Rx queues */ | |
2395 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
2396 | { | |
2397 | int queue; | |
2398 | ||
2399 | for (queue = 0; queue < rxq_number; queue++) { | |
2400 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
2401 | if (err) { | |
2402 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
2403 | __func__, queue); | |
2404 | mvneta_cleanup_rxqs(pp); | |
2405 | return err; | |
2406 | } | |
2407 | } | |
2408 | ||
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | /* Init all tx queues */ | |
2413 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
2414 | { | |
2415 | int queue; | |
2416 | ||
2417 | for (queue = 0; queue < txq_number; queue++) { | |
2418 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
2419 | if (err) { | |
2420 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
2421 | __func__, queue); | |
2422 | mvneta_cleanup_txqs(pp); | |
2423 | return err; | |
2424 | } | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | static void mvneta_start_dev(struct mvneta_port *pp) | |
2431 | { | |
12bb03b4 MR |
2432 | unsigned int cpu; |
2433 | ||
c5aff182 TP |
2434 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
2435 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
2436 | ||
2437 | /* start the Rx/Tx activity */ | |
2438 | mvneta_port_enable(pp); | |
2439 | ||
2440 | /* Enable polling on the port */ | |
12bb03b4 MR |
2441 | for_each_present_cpu(cpu) { |
2442 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
2443 | ||
2444 | napi_enable(&port->napi); | |
2445 | } | |
c5aff182 TP |
2446 | |
2447 | /* Unmask interrupts */ | |
2448 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
898b2970 SS |
2449 | MVNETA_RX_INTR_MASK(rxq_number) | |
2450 | MVNETA_TX_INTR_MASK(txq_number) | | |
2451 | MVNETA_MISCINTR_INTR_MASK); | |
2452 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
2453 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2454 | MVNETA_CAUSE_LINK_CHANGE | | |
2455 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
c5aff182 TP |
2456 | |
2457 | phy_start(pp->phy_dev); | |
2458 | netif_tx_start_all_queues(pp->dev); | |
2459 | } | |
2460 | ||
2461 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
2462 | { | |
12bb03b4 MR |
2463 | unsigned int cpu; |
2464 | ||
c5aff182 TP |
2465 | phy_stop(pp->phy_dev); |
2466 | ||
12bb03b4 MR |
2467 | for_each_present_cpu(cpu) { |
2468 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
2469 | ||
2470 | napi_disable(&port->napi); | |
2471 | } | |
c5aff182 TP |
2472 | |
2473 | netif_carrier_off(pp->dev); | |
2474 | ||
2475 | mvneta_port_down(pp); | |
2476 | netif_tx_stop_all_queues(pp->dev); | |
2477 | ||
2478 | /* Stop the port activity */ | |
2479 | mvneta_port_disable(pp); | |
2480 | ||
2481 | /* Clear all ethernet port interrupts */ | |
2482 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2483 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
2484 | ||
2485 | /* Mask all ethernet port interrupts */ | |
2486 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2487 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
2488 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
2489 | ||
2490 | mvneta_tx_reset(pp); | |
2491 | mvneta_rx_reset(pp); | |
2492 | } | |
2493 | ||
c5aff182 TP |
2494 | /* Return positive if MTU is valid */ |
2495 | static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) | |
2496 | { | |
2497 | if (mtu < 68) { | |
2498 | netdev_err(dev, "cannot change mtu to less than 68\n"); | |
2499 | return -EINVAL; | |
2500 | } | |
2501 | ||
6a20c175 | 2502 | /* 9676 == 9700 - 20 and rounding to 8 */ |
c5aff182 TP |
2503 | if (mtu > 9676) { |
2504 | netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); | |
2505 | mtu = 9676; | |
2506 | } | |
2507 | ||
2508 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { | |
2509 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
2510 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
2511 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
2512 | } | |
2513 | ||
2514 | return mtu; | |
2515 | } | |
2516 | ||
2517 | /* Change the device mtu */ | |
2518 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
2519 | { | |
2520 | struct mvneta_port *pp = netdev_priv(dev); | |
2521 | int ret; | |
2522 | ||
2523 | mtu = mvneta_check_mtu_valid(dev, mtu); | |
2524 | if (mtu < 0) | |
2525 | return -EINVAL; | |
2526 | ||
2527 | dev->mtu = mtu; | |
2528 | ||
b65657fc SG |
2529 | if (!netif_running(dev)) { |
2530 | netdev_update_features(dev); | |
c5aff182 | 2531 | return 0; |
b65657fc | 2532 | } |
c5aff182 | 2533 | |
6a20c175 | 2534 | /* The interface is running, so we have to force a |
a92dbd96 | 2535 | * reallocation of the queues |
c5aff182 TP |
2536 | */ |
2537 | mvneta_stop_dev(pp); | |
2538 | ||
2539 | mvneta_cleanup_txqs(pp); | |
2540 | mvneta_cleanup_rxqs(pp); | |
2541 | ||
a92dbd96 | 2542 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
8ec2cd48 | 2543 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
2544 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
2545 | |
2546 | ret = mvneta_setup_rxqs(pp); | |
2547 | if (ret) { | |
a92dbd96 | 2548 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
2549 | return ret; |
2550 | } | |
2551 | ||
a92dbd96 EG |
2552 | ret = mvneta_setup_txqs(pp); |
2553 | if (ret) { | |
2554 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
2555 | return ret; | |
2556 | } | |
c5aff182 TP |
2557 | |
2558 | mvneta_start_dev(pp); | |
2559 | mvneta_port_up(pp); | |
2560 | ||
b65657fc SG |
2561 | netdev_update_features(dev); |
2562 | ||
c5aff182 TP |
2563 | return 0; |
2564 | } | |
2565 | ||
b65657fc SG |
2566 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
2567 | netdev_features_t features) | |
2568 | { | |
2569 | struct mvneta_port *pp = netdev_priv(dev); | |
2570 | ||
2571 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
2572 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
2573 | netdev_info(dev, | |
2574 | "Disable IP checksum for MTU greater than %dB\n", | |
2575 | pp->tx_csum_limit); | |
2576 | } | |
2577 | ||
2578 | return features; | |
2579 | } | |
2580 | ||
8cc3e439 TP |
2581 | /* Get mac address */ |
2582 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
2583 | { | |
2584 | u32 mac_addr_l, mac_addr_h; | |
2585 | ||
2586 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
2587 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
2588 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
2589 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
2590 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
2591 | addr[3] = mac_addr_h & 0xFF; | |
2592 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
2593 | addr[5] = mac_addr_l & 0xFF; | |
2594 | } | |
2595 | ||
c5aff182 TP |
2596 | /* Handle setting mac address */ |
2597 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
2598 | { | |
2599 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
2600 | struct sockaddr *sockaddr = addr; |
2601 | int ret; | |
c5aff182 | 2602 | |
e68de360 EG |
2603 | ret = eth_prepare_mac_addr_change(dev, addr); |
2604 | if (ret < 0) | |
2605 | return ret; | |
c5aff182 TP |
2606 | /* Remove previous address table entry */ |
2607 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
2608 | ||
2609 | /* Set new addr in hw */ | |
e68de360 | 2610 | mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def); |
c5aff182 | 2611 | |
e68de360 | 2612 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
2613 | return 0; |
2614 | } | |
2615 | ||
2616 | static void mvneta_adjust_link(struct net_device *ndev) | |
2617 | { | |
2618 | struct mvneta_port *pp = netdev_priv(ndev); | |
2619 | struct phy_device *phydev = pp->phy_dev; | |
2620 | int status_change = 0; | |
2621 | ||
2622 | if (phydev->link) { | |
2623 | if ((pp->speed != phydev->speed) || | |
2624 | (pp->duplex != phydev->duplex)) { | |
2625 | u32 val; | |
2626 | ||
2627 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
2628 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
2629 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
898b2970 | 2630 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); |
c5aff182 TP |
2631 | |
2632 | if (phydev->duplex) | |
2633 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
2634 | ||
2635 | if (phydev->speed == SPEED_1000) | |
2636 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
4d12bc63 | 2637 | else if (phydev->speed == SPEED_100) |
c5aff182 TP |
2638 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
2639 | ||
2640 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
2641 | ||
2642 | pp->duplex = phydev->duplex; | |
2643 | pp->speed = phydev->speed; | |
2644 | } | |
2645 | } | |
2646 | ||
2647 | if (phydev->link != pp->link) { | |
2648 | if (!phydev->link) { | |
2649 | pp->duplex = -1; | |
2650 | pp->speed = 0; | |
2651 | } | |
2652 | ||
2653 | pp->link = phydev->link; | |
2654 | status_change = 1; | |
2655 | } | |
2656 | ||
2657 | if (status_change) { | |
2658 | if (phydev->link) { | |
898b2970 SS |
2659 | if (!pp->use_inband_status) { |
2660 | u32 val = mvreg_read(pp, | |
2661 | MVNETA_GMAC_AUTONEG_CONFIG); | |
2662 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
2663 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
2664 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
2665 | val); | |
2666 | } | |
c5aff182 | 2667 | mvneta_port_up(pp); |
c5aff182 | 2668 | } else { |
898b2970 SS |
2669 | if (!pp->use_inband_status) { |
2670 | u32 val = mvreg_read(pp, | |
2671 | MVNETA_GMAC_AUTONEG_CONFIG); | |
2672 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
2673 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
2674 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
2675 | val); | |
2676 | } | |
c5aff182 | 2677 | mvneta_port_down(pp); |
c5aff182 | 2678 | } |
0089b745 | 2679 | phy_print_status(phydev); |
c5aff182 TP |
2680 | } |
2681 | } | |
2682 | ||
2683 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
2684 | { | |
2685 | struct phy_device *phy_dev; | |
2686 | ||
2687 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, | |
2688 | pp->phy_interface); | |
2689 | if (!phy_dev) { | |
2690 | netdev_err(pp->dev, "could not find the PHY\n"); | |
2691 | return -ENODEV; | |
2692 | } | |
2693 | ||
2694 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
2695 | phy_dev->advertising = phy_dev->supported; | |
2696 | ||
2697 | pp->phy_dev = phy_dev; | |
2698 | pp->link = 0; | |
2699 | pp->duplex = 0; | |
2700 | pp->speed = 0; | |
2701 | ||
2702 | return 0; | |
2703 | } | |
2704 | ||
2705 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
2706 | { | |
2707 | phy_disconnect(pp->phy_dev); | |
2708 | pp->phy_dev = NULL; | |
2709 | } | |
2710 | ||
2711 | static int mvneta_open(struct net_device *dev) | |
2712 | { | |
2713 | struct mvneta_port *pp = netdev_priv(dev); | |
2714 | int ret; | |
2715 | ||
c5aff182 | 2716 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
8ec2cd48 | 2717 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
2718 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
2719 | |
2720 | ret = mvneta_setup_rxqs(pp); | |
2721 | if (ret) | |
2722 | return ret; | |
2723 | ||
2724 | ret = mvneta_setup_txqs(pp); | |
2725 | if (ret) | |
2726 | goto err_cleanup_rxqs; | |
2727 | ||
2728 | /* Connect to port interrupt line */ | |
12bb03b4 MR |
2729 | ret = request_percpu_irq(pp->dev->irq, mvneta_isr, |
2730 | MVNETA_DRIVER_NAME, pp->ports); | |
c5aff182 TP |
2731 | if (ret) { |
2732 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
2733 | goto err_cleanup_txqs; | |
2734 | } | |
2735 | ||
2736 | /* In default link is down */ | |
2737 | netif_carrier_off(pp->dev); | |
2738 | ||
2739 | ret = mvneta_mdio_probe(pp); | |
2740 | if (ret < 0) { | |
2741 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
2742 | goto err_free_irq; | |
2743 | } | |
2744 | ||
2745 | mvneta_start_dev(pp); | |
2746 | ||
2747 | return 0; | |
2748 | ||
2749 | err_free_irq: | |
12bb03b4 | 2750 | free_percpu_irq(pp->dev->irq, pp->ports); |
c5aff182 TP |
2751 | err_cleanup_txqs: |
2752 | mvneta_cleanup_txqs(pp); | |
2753 | err_cleanup_rxqs: | |
2754 | mvneta_cleanup_rxqs(pp); | |
2755 | return ret; | |
2756 | } | |
2757 | ||
2758 | /* Stop the port, free port interrupt line */ | |
2759 | static int mvneta_stop(struct net_device *dev) | |
2760 | { | |
2761 | struct mvneta_port *pp = netdev_priv(dev); | |
2762 | ||
2763 | mvneta_stop_dev(pp); | |
2764 | mvneta_mdio_remove(pp); | |
12bb03b4 | 2765 | free_percpu_irq(dev->irq, pp->ports); |
c5aff182 TP |
2766 | mvneta_cleanup_rxqs(pp); |
2767 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
2768 | |
2769 | return 0; | |
2770 | } | |
2771 | ||
15f59456 TP |
2772 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2773 | { | |
2774 | struct mvneta_port *pp = netdev_priv(dev); | |
15f59456 TP |
2775 | |
2776 | if (!pp->phy_dev) | |
2777 | return -ENOTSUPP; | |
2778 | ||
ecf7b361 | 2779 | return phy_mii_ioctl(pp->phy_dev, ifr, cmd); |
15f59456 TP |
2780 | } |
2781 | ||
c5aff182 TP |
2782 | /* Ethtool methods */ |
2783 | ||
2784 | /* Get settings (phy address, speed) for ethtools */ | |
2785 | int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2786 | { | |
2787 | struct mvneta_port *pp = netdev_priv(dev); | |
2788 | ||
2789 | if (!pp->phy_dev) | |
2790 | return -ENODEV; | |
2791 | ||
2792 | return phy_ethtool_gset(pp->phy_dev, cmd); | |
2793 | } | |
2794 | ||
2795 | /* Set settings (phy address, speed) for ethtools */ | |
2796 | int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2797 | { | |
2798 | struct mvneta_port *pp = netdev_priv(dev); | |
2799 | ||
2800 | if (!pp->phy_dev) | |
2801 | return -ENODEV; | |
2802 | ||
2803 | return phy_ethtool_sset(pp->phy_dev, cmd); | |
2804 | } | |
2805 | ||
2806 | /* Set interrupt coalescing for ethtools */ | |
2807 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
2808 | struct ethtool_coalesce *c) | |
2809 | { | |
2810 | struct mvneta_port *pp = netdev_priv(dev); | |
2811 | int queue; | |
2812 | ||
2813 | for (queue = 0; queue < rxq_number; queue++) { | |
2814 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
2815 | rxq->time_coal = c->rx_coalesce_usecs; | |
2816 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
2817 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2818 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2819 | } | |
2820 | ||
2821 | for (queue = 0; queue < txq_number; queue++) { | |
2822 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
2823 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
2824 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
2825 | } | |
2826 | ||
2827 | return 0; | |
2828 | } | |
2829 | ||
2830 | /* get coalescing for ethtools */ | |
2831 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
2832 | struct ethtool_coalesce *c) | |
2833 | { | |
2834 | struct mvneta_port *pp = netdev_priv(dev); | |
2835 | ||
2836 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
2837 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
2838 | ||
2839 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
2840 | return 0; | |
2841 | } | |
2842 | ||
2843 | ||
2844 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
2845 | struct ethtool_drvinfo *drvinfo) | |
2846 | { | |
2847 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
2848 | sizeof(drvinfo->driver)); | |
2849 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
2850 | sizeof(drvinfo->version)); | |
2851 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
2852 | sizeof(drvinfo->bus_info)); | |
2853 | } | |
2854 | ||
2855 | ||
2856 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
2857 | struct ethtool_ringparam *ring) | |
2858 | { | |
2859 | struct mvneta_port *pp = netdev_priv(netdev); | |
2860 | ||
2861 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
2862 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
2863 | ring->rx_pending = pp->rx_ring_size; | |
2864 | ring->tx_pending = pp->tx_ring_size; | |
2865 | } | |
2866 | ||
2867 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
2868 | struct ethtool_ringparam *ring) | |
2869 | { | |
2870 | struct mvneta_port *pp = netdev_priv(dev); | |
2871 | ||
2872 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
2873 | return -EINVAL; | |
2874 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
2875 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
2876 | |
2877 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
2878 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
2879 | if (pp->tx_ring_size != ring->tx_pending) | |
2880 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
2881 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
2882 | |
2883 | if (netif_running(dev)) { | |
2884 | mvneta_stop(dev); | |
2885 | if (mvneta_open(dev)) { | |
2886 | netdev_err(dev, | |
2887 | "error on opening device after ring param change\n"); | |
2888 | return -ENOMEM; | |
2889 | } | |
2890 | } | |
2891 | ||
2892 | return 0; | |
2893 | } | |
2894 | ||
2895 | static const struct net_device_ops mvneta_netdev_ops = { | |
2896 | .ndo_open = mvneta_open, | |
2897 | .ndo_stop = mvneta_stop, | |
2898 | .ndo_start_xmit = mvneta_tx, | |
2899 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
2900 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
2901 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 2902 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 2903 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 2904 | .ndo_do_ioctl = mvneta_ioctl, |
c5aff182 TP |
2905 | }; |
2906 | ||
2907 | const struct ethtool_ops mvneta_eth_tool_ops = { | |
2908 | .get_link = ethtool_op_get_link, | |
2909 | .get_settings = mvneta_ethtool_get_settings, | |
2910 | .set_settings = mvneta_ethtool_set_settings, | |
2911 | .set_coalesce = mvneta_ethtool_set_coalesce, | |
2912 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
2913 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
2914 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
2915 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
2916 | }; | |
2917 | ||
2918 | /* Initialize hw */ | |
9672850b | 2919 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
2920 | { |
2921 | int queue; | |
2922 | ||
2923 | /* Disable port */ | |
2924 | mvneta_port_disable(pp); | |
2925 | ||
2926 | /* Set port default values */ | |
2927 | mvneta_defaults_set(pp); | |
2928 | ||
9672850b EG |
2929 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), |
2930 | GFP_KERNEL); | |
c5aff182 TP |
2931 | if (!pp->txqs) |
2932 | return -ENOMEM; | |
2933 | ||
2934 | /* Initialize TX descriptor rings */ | |
2935 | for (queue = 0; queue < txq_number; queue++) { | |
2936 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
2937 | txq->id = queue; | |
2938 | txq->size = pp->tx_ring_size; | |
2939 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
2940 | } | |
2941 | ||
9672850b EG |
2942 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), |
2943 | GFP_KERNEL); | |
2944 | if (!pp->rxqs) | |
c5aff182 | 2945 | return -ENOMEM; |
c5aff182 TP |
2946 | |
2947 | /* Create Rx descriptor rings */ | |
2948 | for (queue = 0; queue < rxq_number; queue++) { | |
2949 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
2950 | rxq->id = queue; | |
2951 | rxq->size = pp->rx_ring_size; | |
2952 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
2953 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
2954 | } | |
2955 | ||
2956 | return 0; | |
2957 | } | |
2958 | ||
c5aff182 | 2959 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
2960 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
2961 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
2962 | { |
2963 | u32 win_enable; | |
2964 | u32 win_protect; | |
2965 | int i; | |
2966 | ||
2967 | for (i = 0; i < 6; i++) { | |
2968 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
2969 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
2970 | ||
2971 | if (i < 4) | |
2972 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
2973 | } | |
2974 | ||
2975 | win_enable = 0x3f; | |
2976 | win_protect = 0; | |
2977 | ||
2978 | for (i = 0; i < dram->num_cs; i++) { | |
2979 | const struct mbus_dram_window *cs = dram->cs + i; | |
2980 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | | |
2981 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); | |
2982 | ||
2983 | mvreg_write(pp, MVNETA_WIN_SIZE(i), | |
2984 | (cs->size - 1) & 0xffff0000); | |
2985 | ||
2986 | win_enable &= ~(1 << i); | |
2987 | win_protect |= 3 << (2 * i); | |
2988 | } | |
2989 | ||
2990 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
2991 | } | |
2992 | ||
2993 | /* Power up the port */ | |
3f1dd4bc | 2994 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 2995 | { |
3f1dd4bc | 2996 | u32 ctrl; |
c5aff182 TP |
2997 | |
2998 | /* MAC Cause register should be cleared */ | |
2999 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
3000 | ||
3f1dd4bc | 3001 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
c5aff182 | 3002 | |
3f1dd4bc TP |
3003 | /* Even though it might look weird, when we're configured in |
3004 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
3005 | */ | |
3006 | switch(phy_mode) { | |
3007 | case PHY_INTERFACE_MODE_QSGMII: | |
3008 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
3009 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
3010 | break; | |
3011 | case PHY_INTERFACE_MODE_SGMII: | |
3012 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
3013 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
3014 | break; | |
3015 | case PHY_INTERFACE_MODE_RGMII: | |
3016 | case PHY_INTERFACE_MODE_RGMII_ID: | |
3017 | ctrl |= MVNETA_GMAC2_PORT_RGMII; | |
3018 | break; | |
3019 | default: | |
3020 | return -EINVAL; | |
3021 | } | |
c5aff182 | 3022 | |
898b2970 SS |
3023 | if (pp->use_inband_status) |
3024 | ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
3025 | ||
c5aff182 | 3026 | /* Cancel Port Reset */ |
3f1dd4bc TP |
3027 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; |
3028 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
c5aff182 TP |
3029 | |
3030 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
3031 | MVNETA_GMAC2_PORT_RESET) != 0) | |
3032 | continue; | |
3f1dd4bc TP |
3033 | |
3034 | return 0; | |
c5aff182 TP |
3035 | } |
3036 | ||
3037 | /* Device initialization routine */ | |
03ce758e | 3038 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 TP |
3039 | { |
3040 | const struct mbus_dram_target_info *dram_target_info; | |
c3f0dd38 | 3041 | struct resource *res; |
c5aff182 TP |
3042 | struct device_node *dn = pdev->dev.of_node; |
3043 | struct device_node *phy_node; | |
c5aff182 TP |
3044 | struct mvneta_port *pp; |
3045 | struct net_device *dev; | |
8cc3e439 TP |
3046 | const char *dt_mac_addr; |
3047 | char hw_mac_addr[ETH_ALEN]; | |
3048 | const char *mac_from; | |
f8af8e6e | 3049 | const char *managed; |
c5aff182 TP |
3050 | int phy_mode; |
3051 | int err; | |
12bb03b4 | 3052 | int cpu; |
c5aff182 | 3053 | |
6a20c175 | 3054 | /* Our multiqueue support is not complete, so for now, only |
c5aff182 TP |
3055 | * allow the usage of the first RX queue |
3056 | */ | |
3057 | if (rxq_def != 0) { | |
3058 | dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def); | |
3059 | return -EINVAL; | |
3060 | } | |
3061 | ||
ee40a116 | 3062 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
c5aff182 TP |
3063 | if (!dev) |
3064 | return -ENOMEM; | |
3065 | ||
3066 | dev->irq = irq_of_parse_and_map(dn, 0); | |
3067 | if (dev->irq == 0) { | |
3068 | err = -EINVAL; | |
3069 | goto err_free_netdev; | |
3070 | } | |
3071 | ||
3072 | phy_node = of_parse_phandle(dn, "phy", 0); | |
3073 | if (!phy_node) { | |
83895bed TP |
3074 | if (!of_phy_is_fixed_link(dn)) { |
3075 | dev_err(&pdev->dev, "no PHY specified\n"); | |
3076 | err = -ENODEV; | |
3077 | goto err_free_irq; | |
3078 | } | |
3079 | ||
3080 | err = of_phy_register_fixed_link(dn); | |
3081 | if (err < 0) { | |
3082 | dev_err(&pdev->dev, "cannot register fixed PHY\n"); | |
3083 | goto err_free_irq; | |
3084 | } | |
3085 | ||
3086 | /* In the case of a fixed PHY, the DT node associated | |
3087 | * to the PHY is the Ethernet MAC DT node. | |
3088 | */ | |
c891c24c | 3089 | phy_node = of_node_get(dn); |
c5aff182 TP |
3090 | } |
3091 | ||
3092 | phy_mode = of_get_phy_mode(dn); | |
3093 | if (phy_mode < 0) { | |
3094 | dev_err(&pdev->dev, "incorrect phy-mode\n"); | |
3095 | err = -EINVAL; | |
c891c24c | 3096 | goto err_put_phy_node; |
c5aff182 TP |
3097 | } |
3098 | ||
c5aff182 TP |
3099 | dev->tx_queue_len = MVNETA_MAX_TXD; |
3100 | dev->watchdog_timeo = 5 * HZ; | |
3101 | dev->netdev_ops = &mvneta_netdev_ops; | |
3102 | ||
7ad24ea4 | 3103 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 TP |
3104 | |
3105 | pp = netdev_priv(dev); | |
c5aff182 TP |
3106 | pp->phy_node = phy_node; |
3107 | pp->phy_interface = phy_mode; | |
f8af8e6e SS |
3108 | |
3109 | err = of_property_read_string(dn, "managed", &managed); | |
3110 | pp->use_inband_status = (err == 0 && | |
3111 | strcmp(managed, "in-band-status") == 0); | |
c5aff182 | 3112 | |
189dd626 TP |
3113 | pp->clk = devm_clk_get(&pdev->dev, NULL); |
3114 | if (IS_ERR(pp->clk)) { | |
3115 | err = PTR_ERR(pp->clk); | |
c891c24c | 3116 | goto err_put_phy_node; |
189dd626 TP |
3117 | } |
3118 | ||
3119 | clk_prepare_enable(pp->clk); | |
3120 | ||
c3f0dd38 TP |
3121 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
3122 | pp->base = devm_ioremap_resource(&pdev->dev, res); | |
3123 | if (IS_ERR(pp->base)) { | |
3124 | err = PTR_ERR(pp->base); | |
5445eaf3 AP |
3125 | goto err_clk; |
3126 | } | |
3127 | ||
12bb03b4 MR |
3128 | /* Alloc per-cpu port structure */ |
3129 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
3130 | if (!pp->ports) { | |
3131 | err = -ENOMEM; | |
3132 | goto err_clk; | |
3133 | } | |
3134 | ||
74c41b04 | 3135 | /* Alloc per-cpu stats */ |
1c213bd2 | 3136 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 3137 | if (!pp->stats) { |
3138 | err = -ENOMEM; | |
12bb03b4 | 3139 | goto err_free_ports; |
74c41b04 | 3140 | } |
3141 | ||
8cc3e439 | 3142 | dt_mac_addr = of_get_mac_address(dn); |
6c7a9a3c | 3143 | if (dt_mac_addr) { |
8cc3e439 TP |
3144 | mac_from = "device tree"; |
3145 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); | |
3146 | } else { | |
3147 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
3148 | if (is_valid_ether_addr(hw_mac_addr)) { | |
3149 | mac_from = "hardware"; | |
3150 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
3151 | } else { | |
3152 | mac_from = "random"; | |
3153 | eth_hw_addr_random(dev); | |
3154 | } | |
3155 | } | |
3156 | ||
b65657fc SG |
3157 | if (of_device_is_compatible(dn, "marvell,armada-370-neta")) |
3158 | pp->tx_csum_limit = 1600; | |
3159 | ||
c5aff182 TP |
3160 | pp->tx_ring_size = MVNETA_MAX_TXD; |
3161 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
3162 | ||
3163 | pp->dev = dev; | |
3164 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3165 | ||
9672850b EG |
3166 | err = mvneta_init(&pdev->dev, pp); |
3167 | if (err < 0) | |
74c41b04 | 3168 | goto err_free_stats; |
3f1dd4bc TP |
3169 | |
3170 | err = mvneta_port_power_up(pp, phy_mode); | |
3171 | if (err < 0) { | |
3172 | dev_err(&pdev->dev, "can't power up port\n"); | |
9672850b | 3173 | goto err_free_stats; |
3f1dd4bc | 3174 | } |
c5aff182 TP |
3175 | |
3176 | dram_target_info = mv_mbus_dram_info(); | |
3177 | if (dram_target_info) | |
3178 | mvneta_conf_mbus_windows(pp, dram_target_info); | |
3179 | ||
12bb03b4 MR |
3180 | for_each_present_cpu(cpu) { |
3181 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
3182 | ||
3183 | netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
3184 | port->pp = pp; | |
3185 | } | |
c5aff182 | 3186 | |
2adb719d | 3187 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
01ef26ca EG |
3188 | dev->hw_features |= dev->features; |
3189 | dev->vlan_features |= dev->features; | |
b50b72de | 3190 | dev->priv_flags |= IFF_UNICAST_FLT; |
8eef5f97 | 3191 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 3192 | |
c5aff182 TP |
3193 | err = register_netdev(dev); |
3194 | if (err < 0) { | |
3195 | dev_err(&pdev->dev, "failed to register\n"); | |
9672850b | 3196 | goto err_free_stats; |
c5aff182 TP |
3197 | } |
3198 | ||
8cc3e439 TP |
3199 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
3200 | dev->dev_addr); | |
c5aff182 TP |
3201 | |
3202 | platform_set_drvdata(pdev, pp->dev); | |
3203 | ||
898b2970 SS |
3204 | if (pp->use_inband_status) { |
3205 | struct phy_device *phy = of_phy_find_device(dn); | |
3206 | ||
3207 | mvneta_fixed_link_update(pp, phy); | |
04d53b20 RK |
3208 | |
3209 | put_device(&phy->dev); | |
898b2970 SS |
3210 | } |
3211 | ||
c5aff182 TP |
3212 | return 0; |
3213 | ||
74c41b04 | 3214 | err_free_stats: |
3215 | free_percpu(pp->stats); | |
12bb03b4 MR |
3216 | err_free_ports: |
3217 | free_percpu(pp->ports); | |
5445eaf3 AP |
3218 | err_clk: |
3219 | clk_disable_unprepare(pp->clk); | |
c891c24c UKK |
3220 | err_put_phy_node: |
3221 | of_node_put(phy_node); | |
c5aff182 TP |
3222 | err_free_irq: |
3223 | irq_dispose_mapping(dev->irq); | |
3224 | err_free_netdev: | |
3225 | free_netdev(dev); | |
3226 | return err; | |
3227 | } | |
3228 | ||
3229 | /* Device removal routine */ | |
03ce758e | 3230 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
3231 | { |
3232 | struct net_device *dev = platform_get_drvdata(pdev); | |
3233 | struct mvneta_port *pp = netdev_priv(dev); | |
3234 | ||
3235 | unregister_netdev(dev); | |
189dd626 | 3236 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 3237 | free_percpu(pp->ports); |
74c41b04 | 3238 | free_percpu(pp->stats); |
c5aff182 | 3239 | irq_dispose_mapping(dev->irq); |
c891c24c | 3240 | of_node_put(pp->phy_node); |
c5aff182 TP |
3241 | free_netdev(dev); |
3242 | ||
c5aff182 TP |
3243 | return 0; |
3244 | } | |
3245 | ||
3246 | static const struct of_device_id mvneta_match[] = { | |
3247 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 3248 | { .compatible = "marvell,armada-xp-neta" }, |
c5aff182 TP |
3249 | { } |
3250 | }; | |
3251 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
3252 | ||
3253 | static struct platform_driver mvneta_driver = { | |
3254 | .probe = mvneta_probe, | |
03ce758e | 3255 | .remove = mvneta_remove, |
c5aff182 TP |
3256 | .driver = { |
3257 | .name = MVNETA_DRIVER_NAME, | |
3258 | .of_match_table = mvneta_match, | |
3259 | }, | |
3260 | }; | |
3261 | ||
3262 | module_platform_driver(mvneta_driver); | |
3263 | ||
3264 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
3265 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
3266 | MODULE_LICENSE("GPL"); | |
3267 | ||
3268 | module_param(rxq_number, int, S_IRUGO); | |
3269 | module_param(txq_number, int, S_IRUGO); | |
3270 | ||
3271 | module_param(rxq_def, int, S_IRUGO); | |
f19fadfc | 3272 | module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); |