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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0e03f563 JZ |
14 | #include <linux/clk.h> |
15 | #include <linux/cpu.h> | |
c5aff182 | 16 | #include <linux/etherdevice.h> |
0e03f563 | 17 | #include <linux/if_vlan.h> |
c5aff182 | 18 | #include <linux/inetdevice.h> |
c5aff182 | 19 | #include <linux/interrupt.h> |
c3f0dd38 | 20 | #include <linux/io.h> |
0e03f563 JZ |
21 | #include <linux/kernel.h> |
22 | #include <linux/mbus.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
c5aff182 | 25 | #include <linux/of.h> |
0e03f563 | 26 | #include <linux/of_address.h> |
c5aff182 TP |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> | |
29 | #include <linux/of_net.h> | |
c5aff182 | 30 | #include <linux/phy.h> |
9303ab2b | 31 | #include <linux/phy_fixed.h> |
0e03f563 JZ |
32 | #include <linux/platform_device.h> |
33 | #include <linux/skbuff.h> | |
baa11ebc | 34 | #include <net/hwbm.h> |
dc35a10f | 35 | #include "mvneta_bm.h" |
0e03f563 JZ |
36 | #include <net/ip.h> |
37 | #include <net/ipv6.h> | |
38 | #include <net/tso.h> | |
c5aff182 TP |
39 | |
40 | /* Registers */ | |
41 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 42 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
dc35a10f MW |
43 | #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 |
44 | #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 | |
45 | #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 | |
46 | #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 | |
c5aff182 TP |
47 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
48 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
49 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
50 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
51 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
52 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
53 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
54 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
55 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
56 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
57 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
58 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
59 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
dc35a10f MW |
60 | #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) |
61 | #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 | |
62 | #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 | |
c5aff182 TP |
63 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
64 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
65 | #define MVNETA_PHY_ADDR 0x2000 | |
66 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
67 | #define MVNETA_MBUS_RETRY 0x2010 | |
68 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
69 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
70 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
71 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
72 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
73 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
74 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 75 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
76 | #define MVNETA_PORT_CONFIG 0x2400 |
77 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
78 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
79 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
80 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
81 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
82 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
83 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
84 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
85 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
86 | MVNETA_DEF_RXQ_ARP(q) | \ | |
87 | MVNETA_DEF_RXQ_TCP(q) | \ | |
88 | MVNETA_DEF_RXQ_UDP(q) | \ | |
89 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
90 | MVNETA_TX_UNSET_ERR_SUM | \ | |
91 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
92 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
93 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
94 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
95 | #define MVNETA_SDMA_CONFIG 0x241c | |
96 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
97 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
98 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
99 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 100 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
101 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
102 | #define MVNETA_PORT_STATUS 0x2444 | |
103 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
104 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
105 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 106 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 107 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 108 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
109 | #define MVNETA_TYPE_PRIO 0x24bc |
110 | #define MVNETA_FORCE_UNI BIT(21) | |
111 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
112 | #define MVNETA_TXQ_CMD 0x2448 | |
113 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
114 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
115 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
116 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
117 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
118 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 | 119 | #define MVNETA_ACC_MODE 0x2500 |
dc35a10f | 120 | #define MVNETA_BM_ADDRESS 0x2504 |
c5aff182 TP |
121 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
122 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
123 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 124 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 125 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 126 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 127 | |
2dcf75e2 GC |
128 | /* Exception Interrupt Port/Queue Cause register |
129 | * | |
130 | * Their behavior depend of the mapping done using the PCPX2Q | |
131 | * registers. For a given CPU if the bit associated to a queue is not | |
132 | * set, then for the register a read from this CPU will always return | |
133 | * 0 and a write won't do anything | |
134 | */ | |
40ba35e7 | 135 | |
c5aff182 | 136 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 137 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 138 | |
139 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
140 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
141 | * bits 16..23 = RXQ FREE, one bit per queue. | |
142 | * bit 29 = OLD_REG_SUM, see old reg ? | |
143 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
144 | * bit 31 = MISC_SUM, one bit for 4 ports | |
145 | */ | |
146 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
147 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
148 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
149 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 150 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 151 | |
c5aff182 TP |
152 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
153 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 154 | |
155 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
156 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
157 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 158 | |
159 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
160 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
161 | #define MVNETA_CAUSE_PTP BIT(4) | |
162 | ||
163 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
164 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
165 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
166 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
167 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
168 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
169 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
170 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
171 | ||
172 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
173 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
174 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
175 | ||
176 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
177 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
178 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
179 | ||
c5aff182 TP |
180 | #define MVNETA_INTR_ENABLE 0x25b8 |
181 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 182 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 183 | |
c5aff182 TP |
184 | #define MVNETA_RXQ_CMD 0x2680 |
185 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
186 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
187 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
188 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
189 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
190 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
191 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
192 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
193 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 194 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 195 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
196 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
197 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
198 | #define MVNETA_GMAC_STATUS 0x2c10 | |
199 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
200 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
201 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
202 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
203 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
204 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
205 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
206 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
207 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
208 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
209 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 210 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
c5aff182 TP |
211 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
212 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 213 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
898b2970 | 214 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 215 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 216 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
e483911f | 217 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
218 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
219 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
220 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
221 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
222 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
223 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
224 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
225 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
226 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
227 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
2a90f7e1 | 228 | #define MVNETA_TXQ_DEC_SENT_MASK 0xff |
c5aff182 TP |
229 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) |
230 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
231 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
232 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
233 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
234 | #define MVNETA_TX_MTU 0x3e0c | |
235 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
236 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
237 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
238 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
239 | ||
240 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff | |
241 | ||
242 | /* Descriptor ring Macros */ | |
243 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
244 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
245 | ||
246 | /* Various constants */ | |
247 | ||
248 | /* Coalescing */ | |
06708f81 | 249 | #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ |
c5aff182 TP |
250 | #define MVNETA_RX_COAL_PKTS 32 |
251 | #define MVNETA_RX_COAL_USEC 100 | |
252 | ||
6a20c175 | 253 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
254 | * by Marvell switches when a specific hardware mode is enabled (not |
255 | * supported by this driver) or is filled automatically by zeroes on | |
256 | * the RX side. Those two bytes being at the front of the Ethernet | |
257 | * header, they allow to have the IP header aligned on a 4 bytes | |
258 | * boundary automatically: the hardware skips those two bytes on its | |
259 | * own. | |
260 | */ | |
261 | #define MVNETA_MH_SIZE 2 | |
262 | ||
263 | #define MVNETA_VLAN_TAG_LEN 4 | |
264 | ||
9110ee07 | 265 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 | 266 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
dc35a10f MW |
267 | #define MVNETA_ACC_MODE_EXT1 1 |
268 | #define MVNETA_ACC_MODE_EXT2 2 | |
269 | ||
270 | #define MVNETA_MAX_DECODE_WIN 6 | |
c5aff182 TP |
271 | |
272 | /* Timeout constants */ | |
273 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
274 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
275 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
276 | ||
277 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
278 | ||
9a401dea GC |
279 | /* The RSS lookup table actually has 256 entries but we do not use |
280 | * them yet | |
281 | */ | |
282 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
283 | ||
c5aff182 TP |
284 | /* Max number of Rx descriptors */ |
285 | #define MVNETA_MAX_RXD 128 | |
286 | ||
287 | /* Max number of Tx descriptors */ | |
288 | #define MVNETA_MAX_TXD 532 | |
289 | ||
8eef5f97 EG |
290 | /* Max number of allowed TCP segments for software TSO */ |
291 | #define MVNETA_MAX_TSO_SEGS 100 | |
292 | ||
293 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
294 | ||
c5aff182 TP |
295 | /* descriptor aligned size */ |
296 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
297 | ||
8d5047cf MW |
298 | /* Number of bytes to be taken into account by HW when putting incoming data |
299 | * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet | |
300 | * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. | |
301 | */ | |
302 | #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 | |
303 | ||
c5aff182 TP |
304 | #define MVNETA_RX_PKT_SIZE(mtu) \ |
305 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
306 | ETH_HLEN + ETH_FCS_LEN, \ | |
c66e98c9 | 307 | cache_line_size()) |
c5aff182 | 308 | |
2e3173a3 EG |
309 | #define IS_TSO_HEADER(txq, addr) \ |
310 | ((addr >= txq->tso_hdrs_phys) && \ | |
311 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
312 | ||
dc35a10f MW |
313 | #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ |
314 | (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) | |
c5aff182 | 315 | |
9b0cdefa RK |
316 | struct mvneta_statistic { |
317 | unsigned short offset; | |
318 | unsigned short type; | |
319 | const char name[ETH_GSTRING_LEN]; | |
320 | }; | |
321 | ||
322 | #define T_REG_32 32 | |
323 | #define T_REG_64 64 | |
324 | ||
325 | static const struct mvneta_statistic mvneta_statistics[] = { | |
326 | { 0x3000, T_REG_64, "good_octets_received", }, | |
327 | { 0x3010, T_REG_32, "good_frames_received", }, | |
328 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
329 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
330 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
331 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
332 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
333 | { 0x3058, T_REG_32, "good_fc_received", }, | |
334 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
335 | { 0x3060, T_REG_32, "undersize_received", }, | |
336 | { 0x3064, T_REG_32, "fragments_received", }, | |
337 | { 0x3068, T_REG_32, "oversize_received", }, | |
338 | { 0x306c, T_REG_32, "jabber_received", }, | |
339 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
340 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
341 | { 0x3078, T_REG_32, "collision", }, | |
342 | { 0x307c, T_REG_32, "late_collision", }, | |
343 | { 0x2484, T_REG_32, "rx_discard", }, | |
344 | { 0x2488, T_REG_32, "rx_overrun", }, | |
345 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
346 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
347 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
348 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
349 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
350 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
351 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
352 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
353 | { 0x3044, T_REG_32, "excessive_collision", }, | |
354 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
355 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
356 | { 0x3054, T_REG_32, "fc_sent", }, | |
357 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
358 | }; | |
359 | ||
74c41b04 | 360 | struct mvneta_pcpu_stats { |
c5aff182 | 361 | struct u64_stats_sync syncp; |
74c41b04 | 362 | u64 rx_packets; |
363 | u64 rx_bytes; | |
364 | u64 tx_packets; | |
365 | u64 tx_bytes; | |
c5aff182 TP |
366 | }; |
367 | ||
12bb03b4 MR |
368 | struct mvneta_pcpu_port { |
369 | /* Pointer to the shared port */ | |
370 | struct mvneta_port *pp; | |
371 | ||
372 | /* Pointer to the CPU-local NAPI struct */ | |
373 | struct napi_struct napi; | |
374 | ||
375 | /* Cause of the previous interrupt */ | |
376 | u32 cause_rx_tx; | |
377 | }; | |
378 | ||
c5aff182 | 379 | struct mvneta_port { |
dc35a10f | 380 | u8 id; |
12bb03b4 MR |
381 | struct mvneta_pcpu_port __percpu *ports; |
382 | struct mvneta_pcpu_stats __percpu *stats; | |
383 | ||
c5aff182 | 384 | int pkt_size; |
8ec2cd48 | 385 | unsigned int frag_size; |
c5aff182 TP |
386 | void __iomem *base; |
387 | struct mvneta_rx_queue *rxqs; | |
388 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 389 | struct net_device *dev; |
84a3f4db SAS |
390 | struct hlist_node node_online; |
391 | struct hlist_node node_dead; | |
90b74c01 | 392 | int rxq_def; |
5888511e GC |
393 | /* Protect the access to the percpu interrupt registers, |
394 | * ensuring that the configuration remains coherent. | |
395 | */ | |
396 | spinlock_t lock; | |
120cfa50 | 397 | bool is_stopped; |
c5aff182 | 398 | |
2636ac3c MW |
399 | u32 cause_rx_tx; |
400 | struct napi_struct napi; | |
401 | ||
c5aff182 | 402 | /* Core clock */ |
189dd626 | 403 | struct clk *clk; |
15cc4a4a JZ |
404 | /* AXI clock */ |
405 | struct clk *clk_bus; | |
c5aff182 TP |
406 | u8 mcast_count[256]; |
407 | u16 tx_ring_size; | |
408 | u16 rx_ring_size; | |
c5aff182 TP |
409 | |
410 | struct mii_bus *mii_bus; | |
c5aff182 TP |
411 | phy_interface_t phy_interface; |
412 | struct device_node *phy_node; | |
413 | unsigned int link; | |
414 | unsigned int duplex; | |
415 | unsigned int speed; | |
b65657fc | 416 | unsigned int tx_csum_limit; |
0c0744fc | 417 | unsigned int use_inband_status:1; |
9b0cdefa | 418 | |
dc35a10f MW |
419 | struct mvneta_bm *bm_priv; |
420 | struct mvneta_bm_pool *pool_long; | |
421 | struct mvneta_bm_pool *pool_short; | |
422 | int bm_win_id; | |
423 | ||
9b0cdefa | 424 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
9a401dea GC |
425 | |
426 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
2636ac3c MW |
427 | |
428 | /* Flags for special SoC configurations */ | |
429 | bool neta_armada3700; | |
8d5047cf | 430 | u16 rx_offset_correction; |
9768b45c | 431 | const struct mbus_dram_target_info *dram_target_info; |
c5aff182 TP |
432 | }; |
433 | ||
6a20c175 | 434 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
435 | * layout of the transmit and reception DMA descriptors, and their |
436 | * layout is therefore defined by the hardware design | |
437 | */ | |
6083ed44 | 438 | |
c5aff182 TP |
439 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
440 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
441 | #define MVNETA_TX_L4_UDP BIT(16) | |
442 | #define MVNETA_TX_L3_IP6 BIT(17) | |
443 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
444 | #define MVNETA_TXD_Z_PAD BIT(19) | |
445 | #define MVNETA_TXD_L_DESC BIT(20) | |
446 | #define MVNETA_TXD_F_DESC BIT(21) | |
447 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
448 | MVNETA_TXD_L_DESC | \ | |
449 | MVNETA_TXD_F_DESC) | |
450 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
451 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
452 | ||
c5aff182 | 453 | #define MVNETA_RXD_ERR_CRC 0x0 |
dc35a10f MW |
454 | #define MVNETA_RXD_BM_POOL_SHIFT 13 |
455 | #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) | |
c5aff182 TP |
456 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
457 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
458 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
459 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
460 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
461 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
462 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
463 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
464 | ||
9ad8fef6 | 465 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
466 | struct mvneta_tx_desc { |
467 | u32 command; /* Options used by HW for packet transmitting.*/ | |
468 | u16 reserverd1; /* csum_l4 (for future use) */ | |
469 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
470 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
471 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
472 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
473 | }; | |
474 | ||
475 | struct mvneta_rx_desc { | |
476 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
477 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
478 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 479 | |
c5aff182 TP |
480 | u32 buf_phys_addr; /* Physical address of the buffer */ |
481 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 482 | |
c5aff182 TP |
483 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
484 | u16 reserved3; /* prefetch_cmd, for future use */ | |
485 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 486 | |
c5aff182 TP |
487 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
488 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
489 | }; | |
9ad8fef6 TP |
490 | #else |
491 | struct mvneta_tx_desc { | |
492 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
493 | u16 reserverd1; /* csum_l4 (for future use) */ | |
494 | u32 command; /* Options used by HW for packet transmitting.*/ | |
495 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
496 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
497 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
498 | }; | |
499 | ||
500 | struct mvneta_rx_desc { | |
501 | u16 data_size; /* Size of received packet in bytes */ | |
502 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
503 | u32 status; /* Info about received packet */ | |
504 | ||
505 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
506 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
507 | ||
508 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
509 | u16 reserved3; /* prefetch_cmd, for future use */ | |
510 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
511 | ||
512 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
513 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
514 | }; | |
515 | #endif | |
c5aff182 TP |
516 | |
517 | struct mvneta_tx_queue { | |
518 | /* Number of this TX queue, in the range 0-7 */ | |
519 | u8 id; | |
520 | ||
521 | /* Number of TX DMA descriptors in the descriptor ring */ | |
522 | int size; | |
523 | ||
524 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
525 | * descriptor ring |
526 | */ | |
c5aff182 | 527 | int count; |
2a90f7e1 | 528 | int pending; |
8eef5f97 EG |
529 | int tx_stop_threshold; |
530 | int tx_wake_threshold; | |
c5aff182 TP |
531 | |
532 | /* Array of transmitted skb */ | |
533 | struct sk_buff **tx_skb; | |
534 | ||
535 | /* Index of last TX DMA descriptor that was inserted */ | |
536 | int txq_put_index; | |
537 | ||
538 | /* Index of the TX DMA descriptor to be cleaned up */ | |
539 | int txq_get_index; | |
540 | ||
541 | u32 done_pkts_coal; | |
542 | ||
543 | /* Virtual address of the TX DMA descriptors array */ | |
544 | struct mvneta_tx_desc *descs; | |
545 | ||
546 | /* DMA address of the TX DMA descriptors array */ | |
547 | dma_addr_t descs_phys; | |
548 | ||
549 | /* Index of the last TX DMA descriptor */ | |
550 | int last_desc; | |
551 | ||
552 | /* Index of the next TX DMA descriptor to process */ | |
553 | int next_desc_to_proc; | |
2adb719d EG |
554 | |
555 | /* DMA buffers for TSO headers */ | |
556 | char *tso_hdrs; | |
557 | ||
558 | /* DMA address of TSO headers */ | |
559 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
560 | |
561 | /* Affinity mask for CPUs*/ | |
562 | cpumask_t affinity_mask; | |
c5aff182 TP |
563 | }; |
564 | ||
565 | struct mvneta_rx_queue { | |
566 | /* rx queue number, in the range 0-7 */ | |
567 | u8 id; | |
568 | ||
569 | /* num of rx descriptors in the rx descriptor ring */ | |
570 | int size; | |
571 | ||
572 | /* counter of times when mvneta_refill() failed */ | |
573 | int missed; | |
574 | ||
575 | u32 pkts_coal; | |
576 | u32 time_coal; | |
577 | ||
f88bee1c GC |
578 | /* Virtual address of the RX buffer */ |
579 | void **buf_virt_addr; | |
580 | ||
c5aff182 TP |
581 | /* Virtual address of the RX DMA descriptors array */ |
582 | struct mvneta_rx_desc *descs; | |
583 | ||
584 | /* DMA address of the RX DMA descriptors array */ | |
585 | dma_addr_t descs_phys; | |
586 | ||
587 | /* Index of the last RX DMA descriptor */ | |
588 | int last_desc; | |
589 | ||
590 | /* Index of the next RX DMA descriptor to process */ | |
591 | int next_desc_to_proc; | |
592 | }; | |
593 | ||
84a3f4db | 594 | static enum cpuhp_state online_hpstate; |
edadb7fa EG |
595 | /* The hardware supports eight (8) rx queues, but we are only allowing |
596 | * the first one to be used. Therefore, let's just allocate one queue. | |
597 | */ | |
d8936657 | 598 | static int rxq_number = 8; |
c5aff182 TP |
599 | static int txq_number = 8; |
600 | ||
601 | static int rxq_def; | |
c5aff182 | 602 | |
f19fadfc | 603 | static int rx_copybreak __read_mostly = 256; |
604 | ||
dc35a10f MW |
605 | /* HW BM need that each port be identify by a unique ID */ |
606 | static int global_port_id; | |
607 | ||
c5aff182 TP |
608 | #define MVNETA_DRIVER_NAME "mvneta" |
609 | #define MVNETA_DRIVER_VERSION "1.0" | |
610 | ||
611 | /* Utility/helper methods */ | |
612 | ||
613 | /* Write helper method */ | |
614 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
615 | { | |
616 | writel(data, pp->base + offset); | |
617 | } | |
618 | ||
619 | /* Read helper method */ | |
620 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
621 | { | |
622 | return readl(pp->base + offset); | |
623 | } | |
624 | ||
625 | /* Increment txq get counter */ | |
626 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
627 | { | |
628 | txq->txq_get_index++; | |
629 | if (txq->txq_get_index == txq->size) | |
630 | txq->txq_get_index = 0; | |
631 | } | |
632 | ||
633 | /* Increment txq put counter */ | |
634 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
635 | { | |
636 | txq->txq_put_index++; | |
637 | if (txq->txq_put_index == txq->size) | |
638 | txq->txq_put_index = 0; | |
639 | } | |
640 | ||
641 | ||
642 | /* Clear all MIB counters */ | |
643 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
644 | { | |
645 | int i; | |
646 | u32 dummy; | |
647 | ||
648 | /* Perform dummy reads from MIB counters */ | |
649 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
650 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
e483911f AL |
651 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
652 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
653 | } |
654 | ||
655 | /* Get System Network Statistics */ | |
bc1f4470 | 656 | static void |
2dc0d2b4 BX |
657 | mvneta_get_stats64(struct net_device *dev, |
658 | struct rtnl_link_stats64 *stats) | |
c5aff182 TP |
659 | { |
660 | struct mvneta_port *pp = netdev_priv(dev); | |
661 | unsigned int start; | |
74c41b04 | 662 | int cpu; |
c5aff182 | 663 | |
74c41b04 | 664 | for_each_possible_cpu(cpu) { |
665 | struct mvneta_pcpu_stats *cpu_stats; | |
666 | u64 rx_packets; | |
667 | u64 rx_bytes; | |
668 | u64 tx_packets; | |
669 | u64 tx_bytes; | |
c5aff182 | 670 | |
74c41b04 | 671 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
672 | do { | |
57a7744e | 673 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 674 | rx_packets = cpu_stats->rx_packets; |
675 | rx_bytes = cpu_stats->rx_bytes; | |
676 | tx_packets = cpu_stats->tx_packets; | |
677 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 678 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 679 | |
74c41b04 | 680 | stats->rx_packets += rx_packets; |
681 | stats->rx_bytes += rx_bytes; | |
682 | stats->tx_packets += tx_packets; | |
683 | stats->tx_bytes += tx_bytes; | |
684 | } | |
c5aff182 TP |
685 | |
686 | stats->rx_errors = dev->stats.rx_errors; | |
687 | stats->rx_dropped = dev->stats.rx_dropped; | |
688 | ||
689 | stats->tx_dropped = dev->stats.tx_dropped; | |
c5aff182 TP |
690 | } |
691 | ||
692 | /* Rx descriptors helper methods */ | |
693 | ||
5428213c | 694 | /* Checks whether the RX descriptor having this status is both the first |
695 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
696 | * received through a single RX descriptor, so not having each RX |
697 | * descriptor with its first and last bits set is an error | |
698 | */ | |
5428213c | 699 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 700 | { |
5428213c | 701 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
702 | MVNETA_RXD_FIRST_LAST_DESC; |
703 | } | |
704 | ||
705 | /* Add number of descriptors ready to receive new packets */ | |
706 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
707 | struct mvneta_rx_queue *rxq, | |
708 | int ndescs) | |
709 | { | |
710 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
711 | * be added at once |
712 | */ | |
c5aff182 TP |
713 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
714 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
715 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
716 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
717 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
718 | } | |
719 | ||
720 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
721 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
722 | } | |
723 | ||
724 | /* Get number of RX descriptors occupied by received packets */ | |
725 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
726 | struct mvneta_rx_queue *rxq) | |
727 | { | |
728 | u32 val; | |
729 | ||
730 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
731 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
732 | } | |
733 | ||
6a20c175 | 734 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
735 | * from mvneta_rxq_drop_pkts(). |
736 | */ | |
737 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
738 | struct mvneta_rx_queue *rxq, | |
739 | int rx_done, int rx_filled) | |
740 | { | |
741 | u32 val; | |
742 | ||
743 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
744 | val = rx_done | | |
745 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
746 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
747 | return; | |
748 | } | |
749 | ||
750 | /* Only 255 descriptors can be added at once */ | |
751 | while ((rx_done > 0) || (rx_filled > 0)) { | |
752 | if (rx_done <= 0xff) { | |
753 | val = rx_done; | |
754 | rx_done = 0; | |
755 | } else { | |
756 | val = 0xff; | |
757 | rx_done -= 0xff; | |
758 | } | |
759 | if (rx_filled <= 0xff) { | |
760 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
761 | rx_filled = 0; | |
762 | } else { | |
763 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
764 | rx_filled -= 0xff; | |
765 | } | |
766 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
767 | } | |
768 | } | |
769 | ||
770 | /* Get pointer to next RX descriptor to be processed by SW */ | |
771 | static struct mvneta_rx_desc * | |
772 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
773 | { | |
774 | int rx_desc = rxq->next_desc_to_proc; | |
775 | ||
776 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 777 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
778 | return rxq->descs + rx_desc; |
779 | } | |
780 | ||
781 | /* Change maximum receive size of the port. */ | |
782 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
783 | { | |
784 | u32 val; | |
785 | ||
786 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
787 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
788 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
789 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
790 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
791 | } | |
792 | ||
793 | ||
794 | /* Set rx queue offset */ | |
795 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
796 | struct mvneta_rx_queue *rxq, | |
797 | int offset) | |
798 | { | |
799 | u32 val; | |
800 | ||
801 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
802 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
803 | ||
804 | /* Offset is in */ | |
805 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
806 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
807 | } | |
808 | ||
809 | ||
810 | /* Tx descriptors helper methods */ | |
811 | ||
812 | /* Update HW with number of TX descriptors to be sent */ | |
813 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
814 | struct mvneta_tx_queue *txq, | |
815 | int pend_desc) | |
816 | { | |
817 | u32 val; | |
818 | ||
0d63785c SG |
819 | pend_desc += txq->pending; |
820 | ||
821 | /* Only 255 Tx descriptors can be added at once */ | |
822 | do { | |
823 | val = min(pend_desc, 255); | |
824 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
825 | pend_desc -= val; | |
826 | } while (pend_desc > 0); | |
2a90f7e1 | 827 | txq->pending = 0; |
c5aff182 TP |
828 | } |
829 | ||
830 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
831 | static struct mvneta_tx_desc * | |
832 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
833 | { | |
834 | int tx_desc = txq->next_desc_to_proc; | |
835 | ||
836 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
837 | return txq->descs + tx_desc; | |
838 | } | |
839 | ||
840 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
841 | * mapping failures in the TX path. |
842 | */ | |
c5aff182 TP |
843 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
844 | { | |
845 | if (txq->next_desc_to_proc == 0) | |
846 | txq->next_desc_to_proc = txq->last_desc - 1; | |
847 | else | |
848 | txq->next_desc_to_proc--; | |
849 | } | |
850 | ||
851 | /* Set rxq buf size */ | |
852 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
853 | struct mvneta_rx_queue *rxq, | |
854 | int buf_size) | |
855 | { | |
856 | u32 val; | |
857 | ||
858 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
859 | ||
860 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
861 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
862 | ||
863 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
864 | } | |
865 | ||
866 | /* Disable buffer management (BM) */ | |
867 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
868 | struct mvneta_rx_queue *rxq) | |
869 | { | |
870 | u32 val; | |
871 | ||
872 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
873 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
874 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
875 | } | |
876 | ||
dc35a10f MW |
877 | /* Enable buffer management (BM) */ |
878 | static void mvneta_rxq_bm_enable(struct mvneta_port *pp, | |
879 | struct mvneta_rx_queue *rxq) | |
880 | { | |
881 | u32 val; | |
882 | ||
883 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
884 | val |= MVNETA_RXQ_HW_BUF_ALLOC; | |
885 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
886 | } | |
887 | ||
888 | /* Notify HW about port's assignment of pool for bigger packets */ | |
889 | static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, | |
890 | struct mvneta_rx_queue *rxq) | |
891 | { | |
892 | u32 val; | |
893 | ||
894 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
895 | val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; | |
896 | val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); | |
897 | ||
898 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
899 | } | |
900 | ||
901 | /* Notify HW about port's assignment of pool for smaller packets */ | |
902 | static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, | |
903 | struct mvneta_rx_queue *rxq) | |
904 | { | |
905 | u32 val; | |
906 | ||
907 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
908 | val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; | |
909 | val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); | |
910 | ||
911 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
912 | } | |
913 | ||
914 | /* Set port's receive buffer size for assigned BM pool */ | |
915 | static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, | |
916 | int buf_size, | |
917 | u8 pool_id) | |
918 | { | |
919 | u32 val; | |
920 | ||
921 | if (!IS_ALIGNED(buf_size, 8)) { | |
922 | dev_warn(pp->dev->dev.parent, | |
923 | "illegal buf_size value %d, round to %d\n", | |
924 | buf_size, ALIGN(buf_size, 8)); | |
925 | buf_size = ALIGN(buf_size, 8); | |
926 | } | |
927 | ||
928 | val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); | |
929 | val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; | |
930 | mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); | |
931 | } | |
932 | ||
933 | /* Configure MBUS window in order to enable access BM internal SRAM */ | |
934 | static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, | |
935 | u8 target, u8 attr) | |
936 | { | |
937 | u32 win_enable, win_protect; | |
938 | int i; | |
939 | ||
940 | win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); | |
941 | ||
942 | if (pp->bm_win_id < 0) { | |
943 | /* Find first not occupied window */ | |
944 | for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { | |
945 | if (win_enable & (1 << i)) { | |
946 | pp->bm_win_id = i; | |
947 | break; | |
948 | } | |
949 | } | |
950 | if (i == MVNETA_MAX_DECODE_WIN) | |
951 | return -ENOMEM; | |
952 | } else { | |
953 | i = pp->bm_win_id; | |
954 | } | |
955 | ||
956 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
957 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
958 | ||
959 | if (i < 4) | |
960 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
961 | ||
962 | mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | | |
963 | (attr << 8) | target); | |
964 | ||
965 | mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); | |
966 | ||
967 | win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); | |
968 | win_protect |= 3 << (2 * i); | |
969 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); | |
970 | ||
971 | win_enable &= ~(1 << i); | |
972 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
2636ac3c | 977 | static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) |
dc35a10f | 978 | { |
2636ac3c | 979 | u32 wsize; |
dc35a10f MW |
980 | u8 target, attr; |
981 | int err; | |
982 | ||
983 | /* Get BM window information */ | |
984 | err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, | |
985 | &target, &attr); | |
986 | if (err < 0) | |
987 | return err; | |
988 | ||
989 | pp->bm_win_id = -1; | |
990 | ||
991 | /* Open NETA -> BM window */ | |
992 | err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, | |
993 | target, attr); | |
994 | if (err < 0) { | |
995 | netdev_info(pp->dev, "fail to configure mbus window to BM\n"); | |
996 | return err; | |
997 | } | |
2636ac3c MW |
998 | return 0; |
999 | } | |
1000 | ||
1001 | /* Assign and initialize pools for port. In case of fail | |
1002 | * buffer manager will remain disabled for current port. | |
1003 | */ | |
1004 | static int mvneta_bm_port_init(struct platform_device *pdev, | |
1005 | struct mvneta_port *pp) | |
1006 | { | |
1007 | struct device_node *dn = pdev->dev.of_node; | |
1008 | u32 long_pool_id, short_pool_id; | |
1009 | ||
1010 | if (!pp->neta_armada3700) { | |
1011 | int ret; | |
1012 | ||
1013 | ret = mvneta_bm_port_mbus_init(pp); | |
1014 | if (ret) | |
1015 | return ret; | |
1016 | } | |
dc35a10f MW |
1017 | |
1018 | if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { | |
1019 | netdev_info(pp->dev, "missing long pool id\n"); | |
1020 | return -EINVAL; | |
1021 | } | |
1022 | ||
1023 | /* Create port's long pool depending on mtu */ | |
1024 | pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, | |
1025 | MVNETA_BM_LONG, pp->id, | |
1026 | MVNETA_RX_PKT_SIZE(pp->dev->mtu)); | |
1027 | if (!pp->pool_long) { | |
1028 | netdev_info(pp->dev, "fail to obtain long pool for port\n"); | |
1029 | return -ENOMEM; | |
1030 | } | |
1031 | ||
1032 | pp->pool_long->port_map |= 1 << pp->id; | |
1033 | ||
1034 | mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, | |
1035 | pp->pool_long->id); | |
1036 | ||
1037 | /* If short pool id is not defined, assume using single pool */ | |
1038 | if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) | |
1039 | short_pool_id = long_pool_id; | |
1040 | ||
1041 | /* Create port's short pool */ | |
1042 | pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, | |
1043 | MVNETA_BM_SHORT, pp->id, | |
1044 | MVNETA_BM_SHORT_PKT_SIZE); | |
1045 | if (!pp->pool_short) { | |
1046 | netdev_info(pp->dev, "fail to obtain short pool for port\n"); | |
1047 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1048 | return -ENOMEM; | |
1049 | } | |
1050 | ||
1051 | if (short_pool_id != long_pool_id) { | |
1052 | pp->pool_short->port_map |= 1 << pp->id; | |
1053 | mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, | |
1054 | pp->pool_short->id); | |
1055 | } | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | /* Update settings of a pool for bigger packets */ | |
1061 | static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) | |
1062 | { | |
1063 | struct mvneta_bm_pool *bm_pool = pp->pool_long; | |
baa11ebc | 1064 | struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; |
dc35a10f MW |
1065 | int num; |
1066 | ||
1067 | /* Release all buffers from long pool */ | |
1068 | mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); | |
baa11ebc | 1069 | if (hwbm_pool->buf_num) { |
dc35a10f MW |
1070 | WARN(1, "cannot free all buffers in pool %d\n", |
1071 | bm_pool->id); | |
1072 | goto bm_mtu_err; | |
1073 | } | |
1074 | ||
1075 | bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); | |
1076 | bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); | |
baa11ebc GC |
1077 | hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1078 | SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); | |
dc35a10f MW |
1079 | |
1080 | /* Fill entire long pool */ | |
baa11ebc GC |
1081 | num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC); |
1082 | if (num != hwbm_pool->size) { | |
dc35a10f | 1083 | WARN(1, "pool %d: %d of %d allocated\n", |
baa11ebc | 1084 | bm_pool->id, num, hwbm_pool->size); |
dc35a10f MW |
1085 | goto bm_mtu_err; |
1086 | } | |
1087 | mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); | |
1088 | ||
1089 | return; | |
1090 | ||
1091 | bm_mtu_err: | |
1092 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1093 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); | |
1094 | ||
1095 | pp->bm_priv = NULL; | |
1096 | mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); | |
1097 | netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); | |
1098 | } | |
1099 | ||
c5aff182 TP |
1100 | /* Start the Ethernet port RX and TX activity */ |
1101 | static void mvneta_port_up(struct mvneta_port *pp) | |
1102 | { | |
1103 | int queue; | |
1104 | u32 q_map; | |
1105 | ||
1106 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
1107 | q_map = 0; |
1108 | for (queue = 0; queue < txq_number; queue++) { | |
1109 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
f95936cc | 1110 | if (txq->descs) |
c5aff182 TP |
1111 | q_map |= (1 << queue); |
1112 | } | |
1113 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
1114 | ||
1115 | /* Enable all initialized RXQs. */ | |
2dcf75e2 GC |
1116 | for (queue = 0; queue < rxq_number; queue++) { |
1117 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1118 | ||
f95936cc | 1119 | if (rxq->descs) |
2dcf75e2 GC |
1120 | q_map |= (1 << queue); |
1121 | } | |
1122 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
1123 | } |
1124 | ||
1125 | /* Stop the Ethernet port activity */ | |
1126 | static void mvneta_port_down(struct mvneta_port *pp) | |
1127 | { | |
1128 | u32 val; | |
1129 | int count; | |
1130 | ||
1131 | /* Stop Rx port activity. Check port Rx activity. */ | |
1132 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
1133 | ||
1134 | /* Issue stop command for active channels only */ | |
1135 | if (val != 0) | |
1136 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
1137 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
1138 | ||
1139 | /* Wait for all Rx activity to terminate. */ | |
1140 | count = 0; | |
1141 | do { | |
1142 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
1143 | netdev_warn(pp->dev, | |
0838abb3 | 1144 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", |
c5aff182 TP |
1145 | val); |
1146 | break; | |
1147 | } | |
1148 | mdelay(1); | |
1149 | ||
1150 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
a3703fb3 | 1151 | } while (val & MVNETA_RXQ_ENABLE_MASK); |
c5aff182 TP |
1152 | |
1153 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
1154 | * command for active channels only |
1155 | */ | |
c5aff182 TP |
1156 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
1157 | ||
1158 | if (val != 0) | |
1159 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
1160 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
1161 | ||
1162 | /* Wait for all Tx activity to terminate. */ | |
1163 | count = 0; | |
1164 | do { | |
1165 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
1166 | netdev_warn(pp->dev, | |
1167 | "TIMEOUT for TX stopped status=0x%08x\n", | |
1168 | val); | |
1169 | break; | |
1170 | } | |
1171 | mdelay(1); | |
1172 | ||
1173 | /* Check TX Command reg that all Txqs are stopped */ | |
1174 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
1175 | ||
a3703fb3 | 1176 | } while (val & MVNETA_TXQ_ENABLE_MASK); |
c5aff182 TP |
1177 | |
1178 | /* Double check to verify that TX FIFO is empty */ | |
1179 | count = 0; | |
1180 | do { | |
1181 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
1182 | netdev_warn(pp->dev, | |
0838abb3 | 1183 | "TX FIFO empty timeout status=0x%08x\n", |
c5aff182 TP |
1184 | val); |
1185 | break; | |
1186 | } | |
1187 | mdelay(1); | |
1188 | ||
1189 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
1190 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
1191 | (val & MVNETA_TX_IN_PRGRS)); | |
1192 | ||
1193 | udelay(200); | |
1194 | } | |
1195 | ||
1196 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
1197 | static void mvneta_port_enable(struct mvneta_port *pp) | |
1198 | { | |
1199 | u32 val; | |
1200 | ||
1201 | /* Enable port */ | |
1202 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1203 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
1204 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1205 | } | |
1206 | ||
1207 | /* Disable the port and wait for about 200 usec before retuning */ | |
1208 | static void mvneta_port_disable(struct mvneta_port *pp) | |
1209 | { | |
1210 | u32 val; | |
1211 | ||
1212 | /* Reset the Enable bit in the Serial Control Register */ | |
1213 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1214 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
1215 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1216 | ||
4423c18e YK |
1217 | pp->link = 0; |
1218 | pp->duplex = -1; | |
1219 | pp->speed = 0; | |
1220 | ||
c5aff182 TP |
1221 | udelay(200); |
1222 | } | |
1223 | ||
1224 | /* Multicast tables methods */ | |
1225 | ||
1226 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
1227 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
1228 | { | |
1229 | int offset; | |
1230 | u32 val; | |
1231 | ||
1232 | if (queue == -1) { | |
1233 | val = 0; | |
1234 | } else { | |
1235 | val = 0x1 | (queue << 1); | |
1236 | val |= (val << 24) | (val << 16) | (val << 8); | |
1237 | } | |
1238 | ||
1239 | for (offset = 0; offset <= 0xc; offset += 4) | |
1240 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
1241 | } | |
1242 | ||
1243 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
1244 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
1245 | { | |
1246 | int offset; | |
1247 | u32 val; | |
1248 | ||
1249 | if (queue == -1) { | |
1250 | val = 0; | |
1251 | } else { | |
1252 | val = 0x1 | (queue << 1); | |
1253 | val |= (val << 24) | (val << 16) | (val << 8); | |
1254 | } | |
1255 | ||
1256 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1257 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
1258 | ||
1259 | } | |
1260 | ||
1261 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
1262 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
1263 | { | |
1264 | int offset; | |
1265 | u32 val; | |
1266 | ||
1267 | if (queue == -1) { | |
1268 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
1269 | val = 0; | |
1270 | } else { | |
1271 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
1272 | val = 0x1 | (queue << 1); | |
1273 | val |= (val << 24) | (val << 16) | (val << 8); | |
1274 | } | |
1275 | ||
1276 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1277 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
1278 | } | |
1279 | ||
0c0744fc SS |
1280 | static void mvneta_set_autoneg(struct mvneta_port *pp, int enable) |
1281 | { | |
1282 | u32 val; | |
1283 | ||
1284 | if (enable) { | |
1285 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1286 | val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | | |
1287 | MVNETA_GMAC_FORCE_LINK_DOWN | | |
1288 | MVNETA_GMAC_AN_FLOW_CTRL_EN); | |
1289 | val |= MVNETA_GMAC_INBAND_AN_ENABLE | | |
1290 | MVNETA_GMAC_AN_SPEED_EN | | |
1291 | MVNETA_GMAC_AN_DUPLEX_EN; | |
1292 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1293 | ||
1294 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1295 | val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1296 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1297 | ||
1298 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1299 | val |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1300 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1301 | } else { | |
1302 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1303 | val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
1304 | MVNETA_GMAC_AN_SPEED_EN | | |
1305 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1306 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1307 | ||
1308 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1309 | val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1310 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1311 | ||
1312 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1313 | val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1314 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1315 | } | |
1316 | } | |
1317 | ||
db488c10 GC |
1318 | static void mvneta_percpu_unmask_interrupt(void *arg) |
1319 | { | |
1320 | struct mvneta_port *pp = arg; | |
1321 | ||
1322 | /* All the queue are unmasked, but actually only the ones | |
1323 | * mapped to this CPU will be unmasked | |
1324 | */ | |
1325 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
1326 | MVNETA_RX_INTR_MASK_ALL | | |
1327 | MVNETA_TX_INTR_MASK_ALL | | |
1328 | MVNETA_MISCINTR_INTR_MASK); | |
1329 | } | |
1330 | ||
1331 | static void mvneta_percpu_mask_interrupt(void *arg) | |
1332 | { | |
1333 | struct mvneta_port *pp = arg; | |
1334 | ||
1335 | /* All the queue are masked, but actually only the ones | |
1336 | * mapped to this CPU will be masked | |
1337 | */ | |
1338 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1339 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1340 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1341 | } | |
1342 | ||
1343 | static void mvneta_percpu_clear_intr_cause(void *arg) | |
1344 | { | |
1345 | struct mvneta_port *pp = arg; | |
1346 | ||
1347 | /* All the queue are cleared, but actually only the ones | |
1348 | * mapped to this CPU will be cleared | |
1349 | */ | |
1350 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1351 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1352 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1353 | } | |
1354 | ||
c5aff182 TP |
1355 | /* This method sets defaults to the NETA port: |
1356 | * Clears interrupt Cause and Mask registers. | |
1357 | * Clears all MAC tables. | |
1358 | * Sets defaults to all registers. | |
1359 | * Resets RX and TX descriptor rings. | |
1360 | * Resets PHY. | |
1361 | * This method can be called after mvneta_port_down() to return the port | |
1362 | * settings to defaults. | |
1363 | */ | |
1364 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1365 | { | |
1366 | int cpu; | |
1367 | int queue; | |
1368 | u32 val; | |
2dcf75e2 | 1369 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1370 | |
1371 | /* Clear all Cause registers */ | |
db488c10 | 1372 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
1373 | |
1374 | /* Mask all interrupts */ | |
db488c10 | 1375 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
1376 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
1377 | ||
1378 | /* Enable MBUS Retry bit16 */ | |
1379 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1380 | ||
50bf8cb6 GC |
1381 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1382 | * TX queues modulo their number. If there is only one TX | |
1383 | * queue then it is assigned to the CPU associated to the | |
1384 | * default RX queue. | |
6a20c175 | 1385 | */ |
2dcf75e2 GC |
1386 | for_each_present_cpu(cpu) { |
1387 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1388 | int rxq, txq; |
2636ac3c MW |
1389 | if (!pp->neta_armada3700) { |
1390 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1391 | if ((rxq % max_cpu) == cpu) | |
1392 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1393 | ||
1394 | for (txq = 0; txq < txq_number; txq++) | |
1395 | if ((txq % max_cpu) == cpu) | |
1396 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1397 | ||
1398 | /* With only one TX queue we configure a special case | |
1399 | * which will allow to get all the irq on a single | |
1400 | * CPU | |
1401 | */ | |
1402 | if (txq_number == 1) | |
1403 | txq_map = (cpu == pp->rxq_def) ? | |
1404 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 | 1405 | |
2636ac3c MW |
1406 | } else { |
1407 | txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
1408 | rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; | |
1409 | } | |
2dcf75e2 GC |
1410 | |
1411 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1412 | } | |
c5aff182 TP |
1413 | |
1414 | /* Reset RX and TX DMAs */ | |
1415 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1416 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1417 | ||
1418 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1419 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1420 | for (queue = 0; queue < txq_number; queue++) { | |
1421 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1422 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1423 | } | |
1424 | ||
1425 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1426 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1427 | ||
1428 | /* Set Port Acceleration Mode */ | |
dc35a10f MW |
1429 | if (pp->bm_priv) |
1430 | /* HW buffer management + legacy parser */ | |
1431 | val = MVNETA_ACC_MODE_EXT2; | |
1432 | else | |
1433 | /* SW buffer management + legacy parser */ | |
1434 | val = MVNETA_ACC_MODE_EXT1; | |
c5aff182 TP |
1435 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
1436 | ||
dc35a10f MW |
1437 | if (pp->bm_priv) |
1438 | mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); | |
1439 | ||
c5aff182 | 1440 | /* Update val of portCfg register accordingly with all RxQueue types */ |
90b74c01 | 1441 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1442 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1443 | ||
1444 | val = 0; | |
1445 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1446 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1447 | ||
1448 | /* Build PORT_SDMA_CONFIG_REG */ | |
1449 | val = 0; | |
1450 | ||
1451 | /* Default burst size */ | |
1452 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1453 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1454 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1455 | |
9ad8fef6 TP |
1456 | #if defined(__BIG_ENDIAN) |
1457 | val |= MVNETA_DESC_SWAP; | |
1458 | #endif | |
c5aff182 TP |
1459 | |
1460 | /* Assign port SDMA configuration */ | |
1461 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1462 | ||
71408602 TP |
1463 | /* Disable PHY polling in hardware, since we're using the |
1464 | * kernel phylib to do this. | |
1465 | */ | |
1466 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1467 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1468 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1469 | ||
0c0744fc | 1470 | mvneta_set_autoneg(pp, pp->use_inband_status); |
c5aff182 TP |
1471 | mvneta_set_ucast_table(pp, -1); |
1472 | mvneta_set_special_mcast_table(pp, -1); | |
1473 | mvneta_set_other_mcast_table(pp, -1); | |
1474 | ||
1475 | /* Set port interrupt enable register - default enable all */ | |
1476 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1477 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1478 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1479 | |
1480 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1481 | } |
1482 | ||
1483 | /* Set max sizes for tx queues */ | |
1484 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1485 | ||
1486 | { | |
1487 | u32 val, size, mtu; | |
1488 | int queue; | |
1489 | ||
1490 | mtu = max_tx_size * 8; | |
1491 | if (mtu > MVNETA_TX_MTU_MAX) | |
1492 | mtu = MVNETA_TX_MTU_MAX; | |
1493 | ||
1494 | /* Set MTU */ | |
1495 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1496 | val &= ~MVNETA_TX_MTU_MAX; | |
1497 | val |= mtu; | |
1498 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1499 | ||
1500 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1501 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1502 | ||
1503 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1504 | if (size < mtu) { | |
1505 | size = mtu; | |
1506 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1507 | val |= size; | |
1508 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1509 | } | |
1510 | for (queue = 0; queue < txq_number; queue++) { | |
1511 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1512 | ||
1513 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1514 | if (size < mtu) { | |
1515 | size = mtu; | |
1516 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1517 | val |= size; | |
1518 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1519 | } | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | /* Set unicast address */ | |
1524 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1525 | int queue) | |
1526 | { | |
1527 | unsigned int unicast_reg; | |
1528 | unsigned int tbl_offset; | |
1529 | unsigned int reg_offset; | |
1530 | ||
1531 | /* Locate the Unicast table entry */ | |
1532 | last_nibble = (0xf & last_nibble); | |
1533 | ||
1534 | /* offset from unicast tbl base */ | |
1535 | tbl_offset = (last_nibble / 4) * 4; | |
1536 | ||
1537 | /* offset within the above reg */ | |
1538 | reg_offset = last_nibble % 4; | |
1539 | ||
1540 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1541 | ||
1542 | if (queue == -1) { | |
1543 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1544 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1545 | } else { | |
1546 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1547 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1548 | } | |
1549 | ||
1550 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1551 | } | |
1552 | ||
1553 | /* Set mac address */ | |
1554 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1555 | int queue) | |
1556 | { | |
1557 | unsigned int mac_h; | |
1558 | unsigned int mac_l; | |
1559 | ||
1560 | if (queue != -1) { | |
1561 | mac_l = (addr[4] << 8) | (addr[5]); | |
1562 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1563 | (addr[2] << 8) | (addr[3] << 0); | |
1564 | ||
1565 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1566 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1567 | } | |
1568 | ||
1569 | /* Accept frames of this address */ | |
1570 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1571 | } | |
1572 | ||
6a20c175 TP |
1573 | /* Set the number of packets that will be received before RX interrupt |
1574 | * will be generated by HW. | |
c5aff182 TP |
1575 | */ |
1576 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1577 | struct mvneta_rx_queue *rxq, u32 value) | |
1578 | { | |
1579 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1580 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
1581 | rxq->pkts_coal = value; | |
1582 | } | |
1583 | ||
6a20c175 TP |
1584 | /* Set the time delay in usec before RX interrupt will be generated by |
1585 | * HW. | |
c5aff182 TP |
1586 | */ |
1587 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1588 | struct mvneta_rx_queue *rxq, u32 value) | |
1589 | { | |
189dd626 TP |
1590 | u32 val; |
1591 | unsigned long clk_rate; | |
1592 | ||
1593 | clk_rate = clk_get_rate(pp->clk); | |
1594 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1595 | |
1596 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
1597 | rxq->time_coal = value; | |
1598 | } | |
1599 | ||
1600 | /* Set threshold for TX_DONE pkts coalescing */ | |
1601 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1602 | struct mvneta_tx_queue *txq, u32 value) | |
1603 | { | |
1604 | u32 val; | |
1605 | ||
1606 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1607 | ||
1608 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1609 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1610 | ||
1611 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
1612 | ||
1613 | txq->done_pkts_coal = value; | |
1614 | } | |
1615 | ||
c5aff182 TP |
1616 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1617 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
f88bee1c GC |
1618 | u32 phys_addr, void *virt_addr, |
1619 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 1620 | { |
f88bee1c GC |
1621 | int i; |
1622 | ||
c5aff182 | 1623 | rx_desc->buf_phys_addr = phys_addr; |
f88bee1c GC |
1624 | i = rx_desc - rxq->descs; |
1625 | rxq->buf_virt_addr[i] = virt_addr; | |
c5aff182 TP |
1626 | } |
1627 | ||
1628 | /* Decrement sent descriptors counter */ | |
1629 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1630 | struct mvneta_tx_queue *txq, | |
1631 | int sent_desc) | |
1632 | { | |
1633 | u32 val; | |
1634 | ||
1635 | /* Only 255 TX descriptors can be updated at once */ | |
1636 | while (sent_desc > 0xff) { | |
1637 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1638 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1639 | sent_desc = sent_desc - 0xff; | |
1640 | } | |
1641 | ||
1642 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1643 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1644 | } | |
1645 | ||
1646 | /* Get number of TX descriptors already sent by HW */ | |
1647 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1648 | struct mvneta_tx_queue *txq) | |
1649 | { | |
1650 | u32 val; | |
1651 | int sent_desc; | |
1652 | ||
1653 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1654 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1655 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1656 | ||
1657 | return sent_desc; | |
1658 | } | |
1659 | ||
6a20c175 | 1660 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1661 | * The number of sent descriptors is returned. |
1662 | */ | |
1663 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1664 | struct mvneta_tx_queue *txq) | |
1665 | { | |
1666 | int sent_desc; | |
1667 | ||
1668 | /* Get number of sent descriptors */ | |
1669 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1670 | ||
1671 | /* Decrement sent descriptors counter */ | |
1672 | if (sent_desc) | |
1673 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1674 | ||
1675 | return sent_desc; | |
1676 | } | |
1677 | ||
1678 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1679 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1680 | int ip_hdr_len, int l4_proto) | |
1681 | { | |
1682 | u32 command; | |
1683 | ||
1684 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1685 | * G_L4_chk, L4_type; required only for checksum |
1686 | * calculation | |
1687 | */ | |
c5aff182 TP |
1688 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1689 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1690 | ||
0a198587 | 1691 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1692 | command |= MVNETA_TXD_IP_CSUM; |
1693 | else | |
1694 | command |= MVNETA_TX_L3_IP6; | |
1695 | ||
1696 | if (l4_proto == IPPROTO_TCP) | |
1697 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1698 | else if (l4_proto == IPPROTO_UDP) | |
1699 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1700 | else | |
1701 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1702 | ||
1703 | return command; | |
1704 | } | |
1705 | ||
1706 | ||
1707 | /* Display more error info */ | |
1708 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1709 | struct mvneta_rx_desc *rx_desc) | |
1710 | { | |
1711 | u32 status = rx_desc->status; | |
1712 | ||
5428213c | 1713 | if (!mvneta_rxq_desc_is_first_last(status)) { |
c5aff182 TP |
1714 | netdev_err(pp->dev, |
1715 | "bad rx status %08x (buffer oversize), size=%d\n", | |
5428213c | 1716 | status, rx_desc->data_size); |
c5aff182 TP |
1717 | return; |
1718 | } | |
1719 | ||
1720 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
1721 | case MVNETA_RXD_ERR_CRC: | |
1722 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1723 | status, rx_desc->data_size); | |
1724 | break; | |
1725 | case MVNETA_RXD_ERR_OVERRUN: | |
1726 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1727 | status, rx_desc->data_size); | |
1728 | break; | |
1729 | case MVNETA_RXD_ERR_LEN: | |
1730 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1731 | status, rx_desc->data_size); | |
1732 | break; | |
1733 | case MVNETA_RXD_ERR_RESOURCE: | |
1734 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1735 | status, rx_desc->data_size); | |
1736 | break; | |
1737 | } | |
1738 | } | |
1739 | ||
5428213c | 1740 | /* Handle RX checksum offload based on the descriptor's status */ |
1741 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1742 | struct sk_buff *skb) |
1743 | { | |
5428213c | 1744 | if ((status & MVNETA_RXD_L3_IP4) && |
1745 | (status & MVNETA_RXD_L4_CSUM_OK)) { | |
c5aff182 TP |
1746 | skb->csum = 0; |
1747 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1748 | return; | |
1749 | } | |
1750 | ||
1751 | skb->ip_summed = CHECKSUM_NONE; | |
1752 | } | |
1753 | ||
6c498974 | 1754 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1755 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1756 | * valid queue for matching the first one found in <cause>. | |
1757 | */ | |
c5aff182 TP |
1758 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1759 | u32 cause) | |
1760 | { | |
1761 | int queue = fls(cause) - 1; | |
1762 | ||
6c498974 | 1763 | return &pp->txqs[queue]; |
c5aff182 TP |
1764 | } |
1765 | ||
1766 | /* Free tx queue skbuffs */ | |
1767 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
a29b6235 MW |
1768 | struct mvneta_tx_queue *txq, int num, |
1769 | struct netdev_queue *nq) | |
c5aff182 | 1770 | { |
a29b6235 | 1771 | unsigned int bytes_compl = 0, pkts_compl = 0; |
c5aff182 TP |
1772 | int i; |
1773 | ||
1774 | for (i = 0; i < num; i++) { | |
1775 | struct mvneta_tx_desc *tx_desc = txq->descs + | |
1776 | txq->txq_get_index; | |
1777 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; | |
1778 | ||
a29b6235 MW |
1779 | if (skb) { |
1780 | bytes_compl += skb->len; | |
1781 | pkts_compl++; | |
1782 | } | |
1783 | ||
c5aff182 TP |
1784 | mvneta_txq_inc_get(txq); |
1785 | ||
2e3173a3 EG |
1786 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
1787 | dma_unmap_single(pp->dev->dev.parent, | |
1788 | tx_desc->buf_phys_addr, | |
1789 | tx_desc->data_size, DMA_TO_DEVICE); | |
ba7e46ef EG |
1790 | if (!skb) |
1791 | continue; | |
c5aff182 TP |
1792 | dev_kfree_skb_any(skb); |
1793 | } | |
a29b6235 MW |
1794 | |
1795 | netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); | |
c5aff182 TP |
1796 | } |
1797 | ||
1798 | /* Handle end of transmission */ | |
cd713199 | 1799 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1800 | struct mvneta_tx_queue *txq) |
1801 | { | |
1802 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1803 | int tx_done; | |
1804 | ||
1805 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1806 | if (!tx_done) |
1807 | return; | |
1808 | ||
a29b6235 | 1809 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
1810 | |
1811 | txq->count -= tx_done; | |
1812 | ||
1813 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1814 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1815 | netif_tx_wake_queue(nq); |
1816 | } | |
c5aff182 TP |
1817 | } |
1818 | ||
dc35a10f | 1819 | void *mvneta_frag_alloc(unsigned int frag_size) |
8ec2cd48 | 1820 | { |
dc35a10f MW |
1821 | if (likely(frag_size <= PAGE_SIZE)) |
1822 | return netdev_alloc_frag(frag_size); | |
8ec2cd48 | 1823 | else |
dc35a10f | 1824 | return kmalloc(frag_size, GFP_ATOMIC); |
8ec2cd48 | 1825 | } |
dc35a10f | 1826 | EXPORT_SYMBOL_GPL(mvneta_frag_alloc); |
8ec2cd48 | 1827 | |
dc35a10f | 1828 | void mvneta_frag_free(unsigned int frag_size, void *data) |
8ec2cd48 | 1829 | { |
dc35a10f | 1830 | if (likely(frag_size <= PAGE_SIZE)) |
13dc0d2b | 1831 | skb_free_frag(data); |
8ec2cd48 | 1832 | else |
1833 | kfree(data); | |
1834 | } | |
dc35a10f | 1835 | EXPORT_SYMBOL_GPL(mvneta_frag_free); |
8ec2cd48 | 1836 | |
dc35a10f | 1837 | /* Refill processing for SW buffer management */ |
c5aff182 | 1838 | static int mvneta_rx_refill(struct mvneta_port *pp, |
f88bee1c GC |
1839 | struct mvneta_rx_desc *rx_desc, |
1840 | struct mvneta_rx_queue *rxq) | |
c5aff182 TP |
1841 | |
1842 | { | |
1843 | dma_addr_t phys_addr; | |
8ec2cd48 | 1844 | void *data; |
c5aff182 | 1845 | |
dc35a10f | 1846 | data = mvneta_frag_alloc(pp->frag_size); |
8ec2cd48 | 1847 | if (!data) |
c5aff182 TP |
1848 | return -ENOMEM; |
1849 | ||
8ec2cd48 | 1850 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
c5aff182 TP |
1851 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
1852 | DMA_FROM_DEVICE); | |
1853 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { | |
dc35a10f | 1854 | mvneta_frag_free(pp->frag_size, data); |
c5aff182 TP |
1855 | return -ENOMEM; |
1856 | } | |
1857 | ||
8d5047cf | 1858 | phys_addr += pp->rx_offset_correction; |
f88bee1c | 1859 | mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq); |
c5aff182 TP |
1860 | return 0; |
1861 | } | |
1862 | ||
1863 | /* Handle tx checksum */ | |
1864 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1865 | { | |
1866 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1867 | int ip_hdr_len = 0; | |
817dbfa5 | 1868 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1869 | u8 l4_proto; |
1870 | ||
817dbfa5 | 1871 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1872 | struct iphdr *ip4h = ip_hdr(skb); |
1873 | ||
1874 | /* Calculate IPv4 checksum and L4 checksum */ | |
1875 | ip_hdr_len = ip4h->ihl; | |
1876 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1877 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1878 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1879 | ||
1880 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1881 | if (skb_network_header_len(skb) > 0) | |
1882 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1883 | l4_proto = ip6h->nexthdr; | |
1884 | } else | |
1885 | return MVNETA_TX_L4_CSUM_NOT; | |
1886 | ||
1887 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1888 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1889 | } |
1890 | ||
1891 | return MVNETA_TX_L4_CSUM_NOT; | |
1892 | } | |
1893 | ||
c5aff182 TP |
1894 | /* Drop packets received by the RXQ and free buffers */ |
1895 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1896 | struct mvneta_rx_queue *rxq) | |
1897 | { | |
1898 | int rx_done, i; | |
1899 | ||
1900 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
dc35a10f MW |
1901 | if (rx_done) |
1902 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1903 | ||
1904 | if (pp->bm_priv) { | |
1905 | for (i = 0; i < rx_done; i++) { | |
1906 | struct mvneta_rx_desc *rx_desc = | |
1907 | mvneta_rxq_next_desc_get(rxq); | |
1908 | u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); | |
1909 | struct mvneta_bm_pool *bm_pool; | |
1910 | ||
1911 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
1912 | /* Return dropped buffer to the pool */ | |
1913 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
1914 | rx_desc->buf_phys_addr); | |
1915 | } | |
1916 | return; | |
1917 | } | |
1918 | ||
c5aff182 TP |
1919 | for (i = 0; i < rxq->size; i++) { |
1920 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
f88bee1c | 1921 | void *data = rxq->buf_virt_addr[i]; |
c5aff182 | 1922 | |
c5aff182 | 1923 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
a328f3a0 | 1924 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
dc35a10f | 1925 | mvneta_frag_free(pp->frag_size, data); |
c5aff182 | 1926 | } |
dc35a10f | 1927 | } |
c5aff182 | 1928 | |
dc35a10f MW |
1929 | /* Main rx processing when using software buffer management */ |
1930 | static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, | |
1931 | struct mvneta_rx_queue *rxq) | |
1932 | { | |
1933 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); | |
1934 | struct net_device *dev = pp->dev; | |
1935 | int rx_done; | |
1936 | u32 rcvd_pkts = 0; | |
1937 | u32 rcvd_bytes = 0; | |
1938 | ||
1939 | /* Get number of received packets */ | |
1940 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1941 | ||
1942 | if (rx_todo > rx_done) | |
1943 | rx_todo = rx_done; | |
1944 | ||
1945 | rx_done = 0; | |
1946 | ||
1947 | /* Fairness NAPI loop */ | |
1948 | while (rx_done < rx_todo) { | |
1949 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1950 | struct sk_buff *skb; | |
1951 | unsigned char *data; | |
1952 | dma_addr_t phys_addr; | |
1953 | u32 rx_status, frag_size; | |
f88bee1c | 1954 | int rx_bytes, err, index; |
dc35a10f MW |
1955 | |
1956 | rx_done++; | |
1957 | rx_status = rx_desc->status; | |
1958 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); | |
f88bee1c GC |
1959 | index = rx_desc - rxq->descs; |
1960 | data = rxq->buf_virt_addr[index]; | |
dc35a10f MW |
1961 | phys_addr = rx_desc->buf_phys_addr; |
1962 | ||
1963 | if (!mvneta_rxq_desc_is_first_last(rx_status) || | |
1964 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { | |
2eecb2e0 | 1965 | mvneta_rx_error(pp, rx_desc); |
dc35a10f MW |
1966 | err_drop_frame: |
1967 | dev->stats.rx_errors++; | |
dc35a10f MW |
1968 | /* leave the descriptor untouched */ |
1969 | continue; | |
1970 | } | |
1971 | ||
1972 | if (rx_bytes <= rx_copybreak) { | |
1973 | /* better copy a small frame and not unmap the DMA region */ | |
1974 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
1975 | if (unlikely(!skb)) | |
1976 | goto err_drop_frame; | |
1977 | ||
1978 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
ac83b7dd | 1979 | phys_addr, |
dc35a10f MW |
1980 | MVNETA_MH_SIZE + NET_SKB_PAD, |
1981 | rx_bytes, | |
1982 | DMA_FROM_DEVICE); | |
59ae1d12 JB |
1983 | skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, |
1984 | rx_bytes); | |
dc35a10f MW |
1985 | |
1986 | skb->protocol = eth_type_trans(skb, dev); | |
1987 | mvneta_rx_csum(pp, rx_status, skb); | |
1988 | napi_gro_receive(&port->napi, skb); | |
1989 | ||
1990 | rcvd_pkts++; | |
1991 | rcvd_bytes += rx_bytes; | |
1992 | ||
1993 | /* leave the descriptor and buffer untouched */ | |
1994 | continue; | |
1995 | } | |
1996 | ||
1997 | /* Refill processing */ | |
f88bee1c | 1998 | err = mvneta_rx_refill(pp, rx_desc, rxq); |
dc35a10f MW |
1999 | if (err) { |
2000 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
2001 | rxq->missed++; | |
2002 | goto err_drop_frame; | |
2003 | } | |
2004 | ||
2005 | frag_size = pp->frag_size; | |
2006 | ||
2007 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
2008 | ||
2009 | /* After refill old buffer has to be unmapped regardless | |
2010 | * the skb is successfully built or not. | |
2011 | */ | |
2012 | dma_unmap_single(dev->dev.parent, phys_addr, | |
2013 | MVNETA_RX_BUF_SIZE(pp->pkt_size), | |
2014 | DMA_FROM_DEVICE); | |
2015 | ||
2016 | if (!skb) | |
2017 | goto err_drop_frame; | |
2018 | ||
2019 | rcvd_pkts++; | |
2020 | rcvd_bytes += rx_bytes; | |
2021 | ||
2022 | /* Linux processing */ | |
2023 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); | |
2024 | skb_put(skb, rx_bytes); | |
2025 | ||
2026 | skb->protocol = eth_type_trans(skb, dev); | |
2027 | ||
2028 | mvneta_rx_csum(pp, rx_status, skb); | |
2029 | ||
2030 | napi_gro_receive(&port->napi, skb); | |
2031 | } | |
2032 | ||
2033 | if (rcvd_pkts) { | |
2034 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
2035 | ||
2036 | u64_stats_update_begin(&stats->syncp); | |
2037 | stats->rx_packets += rcvd_pkts; | |
2038 | stats->rx_bytes += rcvd_bytes; | |
2039 | u64_stats_update_end(&stats->syncp); | |
2040 | } | |
2041 | ||
2042 | /* Update rxq management counters */ | |
2043 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
2044 | ||
2045 | return rx_done; | |
c5aff182 TP |
2046 | } |
2047 | ||
dc35a10f MW |
2048 | /* Main rx processing when using hardware buffer management */ |
2049 | static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo, | |
2050 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 2051 | { |
12bb03b4 | 2052 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 | 2053 | struct net_device *dev = pp->dev; |
a84e3289 | 2054 | int rx_done; |
dc4277dd | 2055 | u32 rcvd_pkts = 0; |
2056 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
2057 | |
2058 | /* Get number of received packets */ | |
2059 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
2060 | ||
2061 | if (rx_todo > rx_done) | |
2062 | rx_todo = rx_done; | |
2063 | ||
2064 | rx_done = 0; | |
c5aff182 TP |
2065 | |
2066 | /* Fairness NAPI loop */ | |
2067 | while (rx_done < rx_todo) { | |
2068 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
dc35a10f | 2069 | struct mvneta_bm_pool *bm_pool = NULL; |
c5aff182 | 2070 | struct sk_buff *skb; |
8ec2cd48 | 2071 | unsigned char *data; |
daf158d0 | 2072 | dma_addr_t phys_addr; |
dc35a10f | 2073 | u32 rx_status, frag_size; |
c5aff182 | 2074 | int rx_bytes, err; |
dc35a10f | 2075 | u8 pool_id; |
c5aff182 | 2076 | |
c5aff182 | 2077 | rx_done++; |
c5aff182 | 2078 | rx_status = rx_desc->status; |
f19fadfc | 2079 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
f88bee1c | 2080 | data = (u8 *)(uintptr_t)rx_desc->buf_cookie; |
daf158d0 | 2081 | phys_addr = rx_desc->buf_phys_addr; |
dc35a10f MW |
2082 | pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); |
2083 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
c5aff182 | 2084 | |
5428213c | 2085 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 2086 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
dc35a10f MW |
2087 | err_drop_frame_ret_pool: |
2088 | /* Return the buffer to the pool */ | |
2089 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2090 | rx_desc->buf_phys_addr); | |
2091 | err_drop_frame: | |
c5aff182 TP |
2092 | dev->stats.rx_errors++; |
2093 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 2094 | /* leave the descriptor untouched */ |
c5aff182 TP |
2095 | continue; |
2096 | } | |
2097 | ||
f19fadfc | 2098 | if (rx_bytes <= rx_copybreak) { |
2099 | /* better copy a small frame and not unmap the DMA region */ | |
2100 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
2101 | if (unlikely(!skb)) | |
dc35a10f | 2102 | goto err_drop_frame_ret_pool; |
f19fadfc | 2103 | |
2104 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
2105 | rx_desc->buf_phys_addr, | |
2106 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
2107 | rx_bytes, | |
2108 | DMA_FROM_DEVICE); | |
59ae1d12 JB |
2109 | skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, |
2110 | rx_bytes); | |
f19fadfc | 2111 | |
2112 | skb->protocol = eth_type_trans(skb, dev); | |
2113 | mvneta_rx_csum(pp, rx_status, skb); | |
12bb03b4 | 2114 | napi_gro_receive(&port->napi, skb); |
f19fadfc | 2115 | |
2116 | rcvd_pkts++; | |
2117 | rcvd_bytes += rx_bytes; | |
2118 | ||
dc35a10f MW |
2119 | /* Return the buffer to the pool */ |
2120 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2121 | rx_desc->buf_phys_addr); | |
2122 | ||
f19fadfc | 2123 | /* leave the descriptor and buffer untouched */ |
2124 | continue; | |
2125 | } | |
2126 | ||
a84e3289 | 2127 | /* Refill processing */ |
baa11ebc | 2128 | err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); |
a84e3289 SG |
2129 | if (err) { |
2130 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
2131 | rxq->missed++; | |
dc35a10f | 2132 | goto err_drop_frame_ret_pool; |
a84e3289 SG |
2133 | } |
2134 | ||
baa11ebc | 2135 | frag_size = bm_pool->hwbm_pool.frag_size; |
dc35a10f MW |
2136 | |
2137 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
f19fadfc | 2138 | |
26c17a17 MW |
2139 | /* After refill old buffer has to be unmapped regardless |
2140 | * the skb is successfully built or not. | |
2141 | */ | |
dc35a10f MW |
2142 | dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, |
2143 | bm_pool->buf_size, DMA_FROM_DEVICE); | |
26c17a17 MW |
2144 | if (!skb) |
2145 | goto err_drop_frame; | |
2146 | ||
dc4277dd | 2147 | rcvd_pkts++; |
2148 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
2149 | |
2150 | /* Linux processing */ | |
8ec2cd48 | 2151 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
2152 | skb_put(skb, rx_bytes); |
2153 | ||
2154 | skb->protocol = eth_type_trans(skb, dev); | |
2155 | ||
5428213c | 2156 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 2157 | |
12bb03b4 | 2158 | napi_gro_receive(&port->napi, skb); |
c5aff182 TP |
2159 | } |
2160 | ||
dc4277dd | 2161 | if (rcvd_pkts) { |
74c41b04 | 2162 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
2163 | ||
2164 | u64_stats_update_begin(&stats->syncp); | |
2165 | stats->rx_packets += rcvd_pkts; | |
2166 | stats->rx_bytes += rcvd_bytes; | |
2167 | u64_stats_update_end(&stats->syncp); | |
dc4277dd | 2168 | } |
2169 | ||
c5aff182 | 2170 | /* Update rxq management counters */ |
a84e3289 | 2171 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
2172 | |
2173 | return rx_done; | |
2174 | } | |
2175 | ||
2adb719d EG |
2176 | static inline void |
2177 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
2178 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
2179 | { | |
2180 | struct mvneta_tx_desc *tx_desc; | |
2181 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2182 | ||
2183 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2184 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2185 | tx_desc->data_size = hdr_len; | |
2186 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
2187 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
2188 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
2189 | txq->txq_put_index * TSO_HEADER_SIZE; | |
2190 | mvneta_txq_inc_put(txq); | |
2191 | } | |
2192 | ||
2193 | static inline int | |
2194 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
2195 | struct sk_buff *skb, char *data, int size, | |
2196 | bool last_tcp, bool is_last) | |
2197 | { | |
2198 | struct mvneta_tx_desc *tx_desc; | |
2199 | ||
2200 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2201 | tx_desc->data_size = size; | |
2202 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
2203 | size, DMA_TO_DEVICE); | |
2204 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2205 | tx_desc->buf_phys_addr))) { | |
2206 | mvneta_txq_desc_put(txq); | |
2207 | return -ENOMEM; | |
2208 | } | |
2209 | ||
2210 | tx_desc->command = 0; | |
2211 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2212 | ||
2213 | if (last_tcp) { | |
2214 | /* last descriptor in the TCP packet */ | |
2215 | tx_desc->command = MVNETA_TXD_L_DESC; | |
2216 | ||
2217 | /* last descriptor in SKB */ | |
2218 | if (is_last) | |
2219 | txq->tx_skb[txq->txq_put_index] = skb; | |
2220 | } | |
2221 | mvneta_txq_inc_put(txq); | |
2222 | return 0; | |
2223 | } | |
2224 | ||
2225 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
2226 | struct mvneta_tx_queue *txq) | |
2227 | { | |
2228 | int total_len, data_left; | |
2229 | int desc_count = 0; | |
2230 | struct mvneta_port *pp = netdev_priv(dev); | |
2231 | struct tso_t tso; | |
2232 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2233 | int i; | |
2234 | ||
2235 | /* Count needed descriptors */ | |
2236 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
2237 | return 0; | |
2238 | ||
2239 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
2240 | pr_info("*** Is this even possible???!?!?\n"); | |
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | /* Initialize the TSO handler, and prepare the first payload */ | |
2245 | tso_start(skb, &tso); | |
2246 | ||
2247 | total_len = skb->len - hdr_len; | |
2248 | while (total_len > 0) { | |
2249 | char *hdr; | |
2250 | ||
2251 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
2252 | total_len -= data_left; | |
2253 | desc_count++; | |
2254 | ||
2255 | /* prepare packet headers: MAC + IP + TCP */ | |
2256 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
2257 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
2258 | ||
2259 | mvneta_tso_put_hdr(skb, pp, txq); | |
2260 | ||
2261 | while (data_left > 0) { | |
2262 | int size; | |
2263 | desc_count++; | |
2264 | ||
2265 | size = min_t(int, tso.size, data_left); | |
2266 | ||
2267 | if (mvneta_tso_put_data(dev, txq, skb, | |
2268 | tso.data, size, | |
2269 | size == data_left, | |
2270 | total_len == 0)) | |
2271 | goto err_release; | |
2272 | data_left -= size; | |
2273 | ||
2274 | tso_build_data(skb, &tso, size); | |
2275 | } | |
2276 | } | |
2277 | ||
2278 | return desc_count; | |
2279 | ||
2280 | err_release: | |
2281 | /* Release all used data descriptors; header descriptors must not | |
2282 | * be DMA-unmapped. | |
2283 | */ | |
2284 | for (i = desc_count - 1; i >= 0; i--) { | |
2285 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 2286 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
2287 | dma_unmap_single(pp->dev->dev.parent, |
2288 | tx_desc->buf_phys_addr, | |
2289 | tx_desc->data_size, | |
2290 | DMA_TO_DEVICE); | |
2291 | mvneta_txq_desc_put(txq); | |
2292 | } | |
2293 | return 0; | |
2294 | } | |
2295 | ||
c5aff182 TP |
2296 | /* Handle tx fragmentation processing */ |
2297 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
2298 | struct mvneta_tx_queue *txq) | |
2299 | { | |
2300 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 2301 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 2302 | |
3d4ea02f | 2303 | for (i = 0; i < nr_frags; i++) { |
c5aff182 TP |
2304 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2305 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
2306 | ||
2307 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2308 | tx_desc->data_size = frag->size; | |
2309 | ||
2310 | tx_desc->buf_phys_addr = | |
2311 | dma_map_single(pp->dev->dev.parent, addr, | |
2312 | tx_desc->data_size, DMA_TO_DEVICE); | |
2313 | ||
2314 | if (dma_mapping_error(pp->dev->dev.parent, | |
2315 | tx_desc->buf_phys_addr)) { | |
2316 | mvneta_txq_desc_put(txq); | |
2317 | goto error; | |
2318 | } | |
2319 | ||
3d4ea02f | 2320 | if (i == nr_frags - 1) { |
c5aff182 TP |
2321 | /* Last descriptor */ |
2322 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
c5aff182 | 2323 | txq->tx_skb[txq->txq_put_index] = skb; |
c5aff182 TP |
2324 | } else { |
2325 | /* Descriptor in the middle: Not First, Not Last */ | |
2326 | tx_desc->command = 0; | |
c5aff182 | 2327 | txq->tx_skb[txq->txq_put_index] = NULL; |
c5aff182 | 2328 | } |
3d4ea02f | 2329 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
2330 | } |
2331 | ||
2332 | return 0; | |
2333 | ||
2334 | error: | |
2335 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
2336 | * this packet, as well as the corresponding DMA mappings |
2337 | */ | |
c5aff182 TP |
2338 | for (i = i - 1; i >= 0; i--) { |
2339 | tx_desc = txq->descs + i; | |
2340 | dma_unmap_single(pp->dev->dev.parent, | |
2341 | tx_desc->buf_phys_addr, | |
2342 | tx_desc->data_size, | |
2343 | DMA_TO_DEVICE); | |
2344 | mvneta_txq_desc_put(txq); | |
2345 | } | |
2346 | ||
2347 | return -ENOMEM; | |
2348 | } | |
2349 | ||
2350 | /* Main tx processing */ | |
2351 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) | |
2352 | { | |
2353 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
2354 | u16 txq_id = skb_get_queue_mapping(skb); |
2355 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
c5aff182 | 2356 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 2357 | int len = skb->len; |
c5aff182 TP |
2358 | int frags = 0; |
2359 | u32 tx_cmd; | |
2360 | ||
2361 | if (!netif_running(dev)) | |
2362 | goto out; | |
2363 | ||
2adb719d EG |
2364 | if (skb_is_gso(skb)) { |
2365 | frags = mvneta_tx_tso(skb, dev, txq); | |
2366 | goto out; | |
2367 | } | |
2368 | ||
c5aff182 | 2369 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
2370 | |
2371 | /* Get a descriptor for the first part of the packet */ | |
2372 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2373 | ||
2374 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
2375 | ||
2376 | tx_desc->data_size = skb_headlen(skb); | |
2377 | ||
2378 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
2379 | tx_desc->data_size, | |
2380 | DMA_TO_DEVICE); | |
2381 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2382 | tx_desc->buf_phys_addr))) { | |
2383 | mvneta_txq_desc_put(txq); | |
2384 | frags = 0; | |
2385 | goto out; | |
2386 | } | |
2387 | ||
2388 | if (frags == 1) { | |
2389 | /* First and Last descriptor */ | |
2390 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
2391 | tx_desc->command = tx_cmd; | |
2392 | txq->tx_skb[txq->txq_put_index] = skb; | |
2393 | mvneta_txq_inc_put(txq); | |
2394 | } else { | |
2395 | /* First but not Last */ | |
2396 | tx_cmd |= MVNETA_TXD_F_DESC; | |
2397 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2398 | mvneta_txq_inc_put(txq); | |
2399 | tx_desc->command = tx_cmd; | |
2400 | /* Continue with other skb fragments */ | |
2401 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
2402 | dma_unmap_single(dev->dev.parent, | |
2403 | tx_desc->buf_phys_addr, | |
2404 | tx_desc->data_size, | |
2405 | DMA_TO_DEVICE); | |
2406 | mvneta_txq_desc_put(txq); | |
2407 | frags = 0; | |
2408 | goto out; | |
2409 | } | |
2410 | } | |
2411 | ||
c5aff182 TP |
2412 | out: |
2413 | if (frags > 0) { | |
74c41b04 | 2414 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
e19d2dda EG |
2415 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
2416 | ||
a29b6235 MW |
2417 | netdev_tx_sent_queue(nq, len); |
2418 | ||
e19d2dda | 2419 | txq->count += frags; |
8eef5f97 | 2420 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 2421 | netif_tx_stop_queue(nq); |
c5aff182 | 2422 | |
2a90f7e1 SG |
2423 | if (!skb->xmit_more || netif_xmit_stopped(nq) || |
2424 | txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) | |
2425 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
2426 | else | |
2427 | txq->pending += frags; | |
2428 | ||
74c41b04 | 2429 | u64_stats_update_begin(&stats->syncp); |
2430 | stats->tx_packets++; | |
5f478b41 | 2431 | stats->tx_bytes += len; |
74c41b04 | 2432 | u64_stats_update_end(&stats->syncp); |
c5aff182 TP |
2433 | } else { |
2434 | dev->stats.tx_dropped++; | |
2435 | dev_kfree_skb_any(skb); | |
2436 | } | |
2437 | ||
c5aff182 TP |
2438 | return NETDEV_TX_OK; |
2439 | } | |
2440 | ||
2441 | ||
2442 | /* Free tx resources, when resetting a port */ | |
2443 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
2444 | struct mvneta_tx_queue *txq) | |
2445 | ||
2446 | { | |
a29b6235 | 2447 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
c5aff182 TP |
2448 | int tx_done = txq->count; |
2449 | ||
a29b6235 | 2450 | mvneta_txq_bufs_free(pp, txq, tx_done, nq); |
c5aff182 TP |
2451 | |
2452 | /* reset txq */ | |
2453 | txq->count = 0; | |
2454 | txq->txq_put_index = 0; | |
2455 | txq->txq_get_index = 0; | |
2456 | } | |
2457 | ||
6c498974 | 2458 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
2459 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
2460 | */ | |
0713a86a | 2461 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
2462 | { |
2463 | struct mvneta_tx_queue *txq; | |
c5aff182 TP |
2464 | struct netdev_queue *nq; |
2465 | ||
6c498974 | 2466 | while (cause_tx_done) { |
c5aff182 | 2467 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
2468 | |
2469 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2470 | __netif_tx_lock(nq, smp_processor_id()); | |
2471 | ||
0713a86a AE |
2472 | if (txq->count) |
2473 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
2474 | |
2475 | __netif_tx_unlock(nq); | |
2476 | cause_tx_done &= ~((1 << txq->id)); | |
2477 | } | |
c5aff182 TP |
2478 | } |
2479 | ||
6a20c175 | 2480 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
2481 | * according to hw spec, different than generic crc8 algorithm |
2482 | */ | |
2483 | static int mvneta_addr_crc(unsigned char *addr) | |
2484 | { | |
2485 | int crc = 0; | |
2486 | int i; | |
2487 | ||
2488 | for (i = 0; i < ETH_ALEN; i++) { | |
2489 | int j; | |
2490 | ||
2491 | crc = (crc ^ addr[i]) << 8; | |
2492 | for (j = 7; j >= 0; j--) { | |
2493 | if (crc & (0x100 << j)) | |
2494 | crc ^= 0x107 << j; | |
2495 | } | |
2496 | } | |
2497 | ||
2498 | return crc; | |
2499 | } | |
2500 | ||
2501 | /* This method controls the net device special MAC multicast support. | |
2502 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2503 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2504 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2505 | * Table entries in the DA-Filter table. This method set the Special | |
2506 | * Multicast Table appropriate entry. | |
2507 | */ | |
2508 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2509 | unsigned char last_byte, | |
2510 | int queue) | |
2511 | { | |
2512 | unsigned int smc_table_reg; | |
2513 | unsigned int tbl_offset; | |
2514 | unsigned int reg_offset; | |
2515 | ||
2516 | /* Register offset from SMC table base */ | |
2517 | tbl_offset = (last_byte / 4); | |
2518 | /* Entry offset within the above reg */ | |
2519 | reg_offset = last_byte % 4; | |
2520 | ||
2521 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2522 | + tbl_offset * 4)); | |
2523 | ||
2524 | if (queue == -1) | |
2525 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2526 | else { | |
2527 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2528 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2529 | } | |
2530 | ||
2531 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2532 | smc_table_reg); | |
2533 | } | |
2534 | ||
2535 | /* This method controls the network device Other MAC multicast support. | |
2536 | * The Other Multicast Table is used for multicast of another type. | |
2537 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2538 | * in the DA-Filter table. | |
2539 | * The method gets the CRC-8 value from the calling routine and | |
2540 | * sets the Other Multicast Table appropriate entry according to the | |
2541 | * specified CRC-8 . | |
2542 | */ | |
2543 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2544 | unsigned char crc8, | |
2545 | int queue) | |
2546 | { | |
2547 | unsigned int omc_table_reg; | |
2548 | unsigned int tbl_offset; | |
2549 | unsigned int reg_offset; | |
2550 | ||
2551 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2552 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2553 | ||
2554 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2555 | ||
2556 | if (queue == -1) { | |
2557 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2558 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2559 | } else { | |
2560 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2561 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2562 | } | |
2563 | ||
2564 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2565 | } | |
2566 | ||
2567 | /* The network device supports multicast using two tables: | |
2568 | * 1) Special Multicast Table for MAC addresses of the form | |
2569 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2570 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2571 | * Table entries in the DA-Filter table. | |
2572 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
2573 | * is used as an index to the Other Multicast Table entries in the | |
2574 | * DA-Filter table. | |
2575 | */ | |
2576 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
2577 | int queue) | |
2578 | { | |
2579 | unsigned char crc_result = 0; | |
2580 | ||
2581 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
2582 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
2583 | return 0; | |
2584 | } | |
2585 | ||
2586 | crc_result = mvneta_addr_crc(p_addr); | |
2587 | if (queue == -1) { | |
2588 | if (pp->mcast_count[crc_result] == 0) { | |
2589 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
2590 | crc_result); | |
2591 | return -EINVAL; | |
2592 | } | |
2593 | ||
2594 | pp->mcast_count[crc_result]--; | |
2595 | if (pp->mcast_count[crc_result] != 0) { | |
2596 | netdev_info(pp->dev, | |
2597 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
2598 | pp->mcast_count[crc_result], crc_result); | |
2599 | return -EINVAL; | |
2600 | } | |
2601 | } else | |
2602 | pp->mcast_count[crc_result]++; | |
2603 | ||
2604 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2605 | ||
2606 | return 0; | |
2607 | } | |
2608 | ||
2609 | /* Configure Fitering mode of Ethernet port */ | |
2610 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2611 | int is_promisc) | |
2612 | { | |
2613 | u32 port_cfg_reg, val; | |
2614 | ||
2615 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2616 | ||
2617 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2618 | ||
2619 | /* Set / Clear UPM bit in port configuration register */ | |
2620 | if (is_promisc) { | |
2621 | /* Accept all Unicast addresses */ | |
2622 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2623 | val |= MVNETA_FORCE_UNI; | |
2624 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2625 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2626 | } else { | |
2627 | /* Reject all Unicast addresses */ | |
2628 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2629 | val &= ~MVNETA_FORCE_UNI; | |
2630 | } | |
2631 | ||
2632 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2633 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2634 | } | |
2635 | ||
2636 | /* register unicast and multicast addresses */ | |
2637 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2638 | { | |
2639 | struct mvneta_port *pp = netdev_priv(dev); | |
2640 | struct netdev_hw_addr *ha; | |
2641 | ||
2642 | if (dev->flags & IFF_PROMISC) { | |
2643 | /* Accept all: Multicast + Unicast */ | |
2644 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
2645 | mvneta_set_ucast_table(pp, pp->rxq_def); |
2646 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
2647 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2648 | } else { |
2649 | /* Accept single Unicast */ | |
2650 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2651 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 2652 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
2653 | |
2654 | if (dev->flags & IFF_ALLMULTI) { | |
2655 | /* Accept all multicast */ | |
90b74c01 GC |
2656 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
2657 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2658 | } else { |
2659 | /* Accept only initialized multicast */ | |
2660 | mvneta_set_special_mcast_table(pp, -1); | |
2661 | mvneta_set_other_mcast_table(pp, -1); | |
2662 | ||
2663 | if (!netdev_mc_empty(dev)) { | |
2664 | netdev_for_each_mc_addr(ha, dev) { | |
2665 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 2666 | pp->rxq_def); |
c5aff182 TP |
2667 | } |
2668 | } | |
2669 | } | |
2670 | } | |
2671 | } | |
2672 | ||
2673 | /* Interrupt handling - the callback for request_irq() */ | |
2674 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2636ac3c MW |
2675 | { |
2676 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; | |
2677 | ||
2678 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2679 | napi_schedule(&pp->napi); | |
2680 | ||
2681 | return IRQ_HANDLED; | |
2682 | } | |
2683 | ||
2684 | /* Interrupt handling - the callback for request_percpu_irq() */ | |
2685 | static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) | |
c5aff182 | 2686 | { |
12bb03b4 | 2687 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2688 | |
12bb03b4 | 2689 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 2690 | napi_schedule(&port->napi); |
c5aff182 TP |
2691 | |
2692 | return IRQ_HANDLED; | |
2693 | } | |
2694 | ||
898b2970 SS |
2695 | static int mvneta_fixed_link_update(struct mvneta_port *pp, |
2696 | struct phy_device *phy) | |
2697 | { | |
2698 | struct fixed_phy_status status; | |
2699 | struct fixed_phy_status changed = {}; | |
2700 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); | |
2701 | ||
2702 | status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
2703 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) | |
2704 | status.speed = SPEED_1000; | |
2705 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) | |
2706 | status.speed = SPEED_100; | |
2707 | else | |
2708 | status.speed = SPEED_10; | |
2709 | status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
2710 | changed.link = 1; | |
2711 | changed.speed = 1; | |
2712 | changed.duplex = 1; | |
2713 | fixed_phy_update_state(phy, &status, &changed); | |
2714 | return 0; | |
2715 | } | |
2716 | ||
c5aff182 TP |
2717 | /* NAPI handler |
2718 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
2719 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
2720 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
2721 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
2722 | * Each CPU has its own causeRxTx register | |
2723 | */ | |
2724 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
2725 | { | |
2726 | int rx_done = 0; | |
2727 | u32 cause_rx_tx; | |
2dcf75e2 | 2728 | int rx_queue; |
c5aff182 | 2729 | struct mvneta_port *pp = netdev_priv(napi->dev); |
c6c022e3 | 2730 | struct net_device *ndev = pp->dev; |
12bb03b4 | 2731 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
2732 | |
2733 | if (!netif_running(pp->dev)) { | |
2636ac3c | 2734 | napi_complete(napi); |
c5aff182 TP |
2735 | return rx_done; |
2736 | } | |
2737 | ||
2738 | /* Read cause register */ | |
898b2970 SS |
2739 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
2740 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
2741 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
2742 | ||
2743 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2744 | if (pp->use_inband_status && (cause_misc & | |
2745 | (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2746 | MVNETA_CAUSE_LINK_CHANGE | | |
2747 | MVNETA_CAUSE_PSC_SYNC_CHANGE))) { | |
c6c022e3 | 2748 | mvneta_fixed_link_update(pp, ndev->phydev); |
898b2970 SS |
2749 | } |
2750 | } | |
71f6d1b3 | 2751 | |
2752 | /* Release Tx descriptors */ | |
2753 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 2754 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 2755 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
2756 | } | |
c5aff182 | 2757 | |
6a20c175 | 2758 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
2759 | * RX packets |
2760 | */ | |
2dcf75e2 GC |
2761 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
2762 | ||
2636ac3c MW |
2763 | cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : |
2764 | port->cause_rx_tx; | |
2dcf75e2 GC |
2765 | |
2766 | if (rx_queue) { | |
2767 | rx_queue = rx_queue - 1; | |
dc35a10f MW |
2768 | if (pp->bm_priv) |
2769 | rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]); | |
2770 | else | |
2771 | rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]); | |
2dcf75e2 GC |
2772 | } |
2773 | ||
6ad20165 | 2774 | if (rx_done < budget) { |
c5aff182 | 2775 | cause_rx_tx = 0; |
6ad20165 | 2776 | napi_complete_done(napi, rx_done); |
2636ac3c MW |
2777 | |
2778 | if (pp->neta_armada3700) { | |
2779 | unsigned long flags; | |
2780 | ||
2781 | local_irq_save(flags); | |
2782 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
2783 | MVNETA_RX_INTR_MASK(rxq_number) | | |
2784 | MVNETA_TX_INTR_MASK(txq_number) | | |
2785 | MVNETA_MISCINTR_INTR_MASK); | |
2786 | local_irq_restore(flags); | |
2787 | } else { | |
2788 | enable_percpu_irq(pp->dev->irq, 0); | |
2789 | } | |
c5aff182 TP |
2790 | } |
2791 | ||
2636ac3c MW |
2792 | if (pp->neta_armada3700) |
2793 | pp->cause_rx_tx = cause_rx_tx; | |
2794 | else | |
2795 | port->cause_rx_tx = cause_rx_tx; | |
2796 | ||
c5aff182 TP |
2797 | return rx_done; |
2798 | } | |
2799 | ||
c5aff182 TP |
2800 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
2801 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2802 | int num) | |
2803 | { | |
c5aff182 TP |
2804 | int i; |
2805 | ||
2806 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 2807 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
f88bee1c | 2808 | if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) { |
a1a65ab1 | 2809 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", |
c5aff182 TP |
2810 | __func__, rxq->id, i, num); |
2811 | break; | |
2812 | } | |
c5aff182 TP |
2813 | } |
2814 | ||
2815 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
2816 | * get packets) |
2817 | */ | |
c5aff182 TP |
2818 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
2819 | ||
2820 | return i; | |
2821 | } | |
2822 | ||
2823 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
2824 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
2825 | { | |
2826 | int queue; | |
2827 | ||
9672850b | 2828 | /* free the skb's in the tx ring */ |
c5aff182 TP |
2829 | for (queue = 0; queue < txq_number; queue++) |
2830 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
2831 | ||
2832 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
2833 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
2834 | } | |
2835 | ||
2836 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
2837 | { | |
2838 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
2839 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
2840 | } | |
2841 | ||
2842 | /* Rx/Tx queue initialization/cleanup methods */ | |
2843 | ||
2844 | /* Create a specified RX queue */ | |
2845 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
2846 | struct mvneta_rx_queue *rxq) | |
2847 | ||
2848 | { | |
2849 | rxq->size = pp->rx_ring_size; | |
2850 | ||
2851 | /* Allocate memory for RX descriptors */ | |
2852 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2853 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2854 | &rxq->descs_phys, GFP_KERNEL); | |
f95936cc | 2855 | if (!rxq->descs) |
c5aff182 | 2856 | return -ENOMEM; |
c5aff182 | 2857 | |
c5aff182 TP |
2858 | rxq->last_desc = rxq->size - 1; |
2859 | ||
2860 | /* Set Rx descriptors queue starting address */ | |
2861 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
2862 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
2863 | ||
2864 | /* Set Offset */ | |
8d5047cf | 2865 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction); |
c5aff182 TP |
2866 | |
2867 | /* Set coalescing pkts and time */ | |
2868 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2869 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2870 | ||
dc35a10f MW |
2871 | if (!pp->bm_priv) { |
2872 | /* Fill RXQ with buffers from RX pool */ | |
2873 | mvneta_rxq_buf_size_set(pp, rxq, | |
2874 | MVNETA_RX_BUF_SIZE(pp->pkt_size)); | |
2875 | mvneta_rxq_bm_disable(pp, rxq); | |
e9f64999 | 2876 | mvneta_rxq_fill(pp, rxq, rxq->size); |
dc35a10f MW |
2877 | } else { |
2878 | mvneta_rxq_bm_enable(pp, rxq); | |
2879 | mvneta_rxq_long_pool_set(pp, rxq); | |
2880 | mvneta_rxq_short_pool_set(pp, rxq); | |
e9f64999 | 2881 | mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); |
dc35a10f MW |
2882 | } |
2883 | ||
c5aff182 TP |
2884 | return 0; |
2885 | } | |
2886 | ||
2887 | /* Cleanup Rx queue */ | |
2888 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
2889 | struct mvneta_rx_queue *rxq) | |
2890 | { | |
2891 | mvneta_rxq_drop_pkts(pp, rxq); | |
2892 | ||
2893 | if (rxq->descs) | |
2894 | dma_free_coherent(pp->dev->dev.parent, | |
2895 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2896 | rxq->descs, | |
2897 | rxq->descs_phys); | |
2898 | ||
2899 | rxq->descs = NULL; | |
2900 | rxq->last_desc = 0; | |
2901 | rxq->next_desc_to_proc = 0; | |
2902 | rxq->descs_phys = 0; | |
2903 | } | |
2904 | ||
2905 | /* Create and initialize a tx queue */ | |
2906 | static int mvneta_txq_init(struct mvneta_port *pp, | |
2907 | struct mvneta_tx_queue *txq) | |
2908 | { | |
50bf8cb6 GC |
2909 | int cpu; |
2910 | ||
c5aff182 TP |
2911 | txq->size = pp->tx_ring_size; |
2912 | ||
8eef5f97 EG |
2913 | /* A queue must always have room for at least one skb. |
2914 | * Therefore, stop the queue when the free entries reaches | |
2915 | * the maximum number of descriptors per skb. | |
2916 | */ | |
2917 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
2918 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
2919 | ||
2920 | ||
c5aff182 TP |
2921 | /* Allocate memory for TX descriptors */ |
2922 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2923 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2924 | &txq->descs_phys, GFP_KERNEL); | |
f95936cc | 2925 | if (!txq->descs) |
c5aff182 | 2926 | return -ENOMEM; |
c5aff182 | 2927 | |
c5aff182 TP |
2928 | txq->last_desc = txq->size - 1; |
2929 | ||
2930 | /* Set maximum bandwidth for enabled TXQs */ | |
2931 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
2932 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
2933 | ||
2934 | /* Set Tx descriptors queue starting address */ | |
2935 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
2936 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
2937 | ||
d441b688 ME |
2938 | txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), |
2939 | GFP_KERNEL); | |
f95936cc | 2940 | if (!txq->tx_skb) { |
c5aff182 TP |
2941 | dma_free_coherent(pp->dev->dev.parent, |
2942 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2943 | txq->descs, txq->descs_phys); | |
2944 | return -ENOMEM; | |
2945 | } | |
2adb719d EG |
2946 | |
2947 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
2948 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
2949 | txq->size * TSO_HEADER_SIZE, | |
2950 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
f95936cc | 2951 | if (!txq->tso_hdrs) { |
2adb719d EG |
2952 | kfree(txq->tx_skb); |
2953 | dma_free_coherent(pp->dev->dev.parent, | |
2954 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2955 | txq->descs, txq->descs_phys); | |
2956 | return -ENOMEM; | |
2957 | } | |
c5aff182 TP |
2958 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
2959 | ||
50bf8cb6 GC |
2960 | /* Setup XPS mapping */ |
2961 | if (txq_number > 1) | |
2962 | cpu = txq->id % num_present_cpus(); | |
2963 | else | |
2964 | cpu = pp->rxq_def % num_present_cpus(); | |
2965 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
2966 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
2967 | ||
c5aff182 TP |
2968 | return 0; |
2969 | } | |
2970 | ||
2971 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
2972 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
2973 | struct mvneta_tx_queue *txq) | |
2974 | { | |
a29b6235 MW |
2975 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); |
2976 | ||
c5aff182 TP |
2977 | kfree(txq->tx_skb); |
2978 | ||
2adb719d EG |
2979 | if (txq->tso_hdrs) |
2980 | dma_free_coherent(pp->dev->dev.parent, | |
2981 | txq->size * TSO_HEADER_SIZE, | |
2982 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
2983 | if (txq->descs) |
2984 | dma_free_coherent(pp->dev->dev.parent, | |
2985 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2986 | txq->descs, txq->descs_phys); | |
2987 | ||
a29b6235 MW |
2988 | netdev_tx_reset_queue(nq); |
2989 | ||
c5aff182 TP |
2990 | txq->descs = NULL; |
2991 | txq->last_desc = 0; | |
2992 | txq->next_desc_to_proc = 0; | |
2993 | txq->descs_phys = 0; | |
2994 | ||
2995 | /* Set minimum bandwidth for disabled TXQs */ | |
2996 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
2997 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
2998 | ||
2999 | /* Set Tx descriptors queue starting address and size */ | |
3000 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
3001 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
3002 | } | |
3003 | ||
3004 | /* Cleanup all Tx queues */ | |
3005 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
3006 | { | |
3007 | int queue; | |
3008 | ||
3009 | for (queue = 0; queue < txq_number; queue++) | |
3010 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
3011 | } | |
3012 | ||
3013 | /* Cleanup all Rx queues */ | |
3014 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
3015 | { | |
2dcf75e2 GC |
3016 | int queue; |
3017 | ||
ca5902a6 | 3018 | for (queue = 0; queue < rxq_number; queue++) |
2dcf75e2 | 3019 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); |
c5aff182 TP |
3020 | } |
3021 | ||
3022 | ||
3023 | /* Init all Rx queues */ | |
3024 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
3025 | { | |
2dcf75e2 GC |
3026 | int queue; |
3027 | ||
3028 | for (queue = 0; queue < rxq_number; queue++) { | |
3029 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
3030 | ||
3031 | if (err) { | |
3032 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
3033 | __func__, queue); | |
3034 | mvneta_cleanup_rxqs(pp); | |
3035 | return err; | |
3036 | } | |
c5aff182 TP |
3037 | } |
3038 | ||
3039 | return 0; | |
3040 | } | |
3041 | ||
3042 | /* Init all tx queues */ | |
3043 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
3044 | { | |
3045 | int queue; | |
3046 | ||
3047 | for (queue = 0; queue < txq_number; queue++) { | |
3048 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
3049 | if (err) { | |
3050 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
3051 | __func__, queue); | |
3052 | mvneta_cleanup_txqs(pp); | |
3053 | return err; | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | return 0; | |
3058 | } | |
3059 | ||
3060 | static void mvneta_start_dev(struct mvneta_port *pp) | |
3061 | { | |
6b125d63 | 3062 | int cpu; |
c6c022e3 | 3063 | struct net_device *ndev = pp->dev; |
12bb03b4 | 3064 | |
c5aff182 TP |
3065 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
3066 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
3067 | ||
3068 | /* start the Rx/Tx activity */ | |
3069 | mvneta_port_enable(pp); | |
3070 | ||
2636ac3c MW |
3071 | if (!pp->neta_armada3700) { |
3072 | /* Enable polling on the port */ | |
3073 | for_each_online_cpu(cpu) { | |
3074 | struct mvneta_pcpu_port *port = | |
3075 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3076 | |
2636ac3c MW |
3077 | napi_enable(&port->napi); |
3078 | } | |
3079 | } else { | |
3080 | napi_enable(&pp->napi); | |
12bb03b4 | 3081 | } |
c5aff182 | 3082 | |
2dcf75e2 | 3083 | /* Unmask interrupts. It has to be done from each CPU */ |
6b125d63 GC |
3084 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
3085 | ||
898b2970 SS |
3086 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3087 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3088 | MVNETA_CAUSE_LINK_CHANGE | | |
3089 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
c5aff182 | 3090 | |
c6c022e3 | 3091 | phy_start(ndev->phydev); |
c5aff182 TP |
3092 | netif_tx_start_all_queues(pp->dev); |
3093 | } | |
3094 | ||
3095 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
3096 | { | |
12bb03b4 | 3097 | unsigned int cpu; |
c6c022e3 | 3098 | struct net_device *ndev = pp->dev; |
12bb03b4 | 3099 | |
c6c022e3 | 3100 | phy_stop(ndev->phydev); |
c5aff182 | 3101 | |
2636ac3c MW |
3102 | if (!pp->neta_armada3700) { |
3103 | for_each_online_cpu(cpu) { | |
3104 | struct mvneta_pcpu_port *port = | |
3105 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 3106 | |
2636ac3c MW |
3107 | napi_disable(&port->napi); |
3108 | } | |
3109 | } else { | |
3110 | napi_disable(&pp->napi); | |
12bb03b4 | 3111 | } |
c5aff182 TP |
3112 | |
3113 | netif_carrier_off(pp->dev); | |
3114 | ||
3115 | mvneta_port_down(pp); | |
3116 | netif_tx_stop_all_queues(pp->dev); | |
3117 | ||
3118 | /* Stop the port activity */ | |
3119 | mvneta_port_disable(pp); | |
3120 | ||
3121 | /* Clear all ethernet port interrupts */ | |
db488c10 | 3122 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
3123 | |
3124 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3125 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
3126 | |
3127 | mvneta_tx_reset(pp); | |
3128 | mvneta_rx_reset(pp); | |
3129 | } | |
3130 | ||
db5dd0db MW |
3131 | static void mvneta_percpu_enable(void *arg) |
3132 | { | |
3133 | struct mvneta_port *pp = arg; | |
3134 | ||
3135 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
3136 | } | |
3137 | ||
3138 | static void mvneta_percpu_disable(void *arg) | |
3139 | { | |
3140 | struct mvneta_port *pp = arg; | |
3141 | ||
3142 | disable_percpu_irq(pp->dev->irq); | |
3143 | } | |
3144 | ||
c5aff182 TP |
3145 | /* Change the device mtu */ |
3146 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
3147 | { | |
3148 | struct mvneta_port *pp = netdev_priv(dev); | |
3149 | int ret; | |
3150 | ||
5777987e JW |
3151 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { |
3152 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
3153 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
3154 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
3155 | } | |
c5aff182 TP |
3156 | |
3157 | dev->mtu = mtu; | |
3158 | ||
b65657fc | 3159 | if (!netif_running(dev)) { |
dc35a10f MW |
3160 | if (pp->bm_priv) |
3161 | mvneta_bm_update_mtu(pp, mtu); | |
3162 | ||
b65657fc | 3163 | netdev_update_features(dev); |
c5aff182 | 3164 | return 0; |
b65657fc | 3165 | } |
c5aff182 | 3166 | |
6a20c175 | 3167 | /* The interface is running, so we have to force a |
a92dbd96 | 3168 | * reallocation of the queues |
c5aff182 TP |
3169 | */ |
3170 | mvneta_stop_dev(pp); | |
db5dd0db | 3171 | on_each_cpu(mvneta_percpu_disable, pp, true); |
c5aff182 TP |
3172 | |
3173 | mvneta_cleanup_txqs(pp); | |
3174 | mvneta_cleanup_rxqs(pp); | |
3175 | ||
dc35a10f MW |
3176 | if (pp->bm_priv) |
3177 | mvneta_bm_update_mtu(pp, mtu); | |
3178 | ||
a92dbd96 | 3179 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
8ec2cd48 | 3180 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
3181 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
3182 | |
3183 | ret = mvneta_setup_rxqs(pp); | |
3184 | if (ret) { | |
a92dbd96 | 3185 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
3186 | return ret; |
3187 | } | |
3188 | ||
a92dbd96 EG |
3189 | ret = mvneta_setup_txqs(pp); |
3190 | if (ret) { | |
3191 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
3192 | return ret; | |
3193 | } | |
c5aff182 | 3194 | |
db5dd0db | 3195 | on_each_cpu(mvneta_percpu_enable, pp, true); |
c5aff182 TP |
3196 | mvneta_start_dev(pp); |
3197 | mvneta_port_up(pp); | |
3198 | ||
b65657fc SG |
3199 | netdev_update_features(dev); |
3200 | ||
c5aff182 TP |
3201 | return 0; |
3202 | } | |
3203 | ||
b65657fc SG |
3204 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
3205 | netdev_features_t features) | |
3206 | { | |
3207 | struct mvneta_port *pp = netdev_priv(dev); | |
3208 | ||
3209 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
3210 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
3211 | netdev_info(dev, | |
3212 | "Disable IP checksum for MTU greater than %dB\n", | |
3213 | pp->tx_csum_limit); | |
3214 | } | |
3215 | ||
3216 | return features; | |
3217 | } | |
3218 | ||
8cc3e439 TP |
3219 | /* Get mac address */ |
3220 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
3221 | { | |
3222 | u32 mac_addr_l, mac_addr_h; | |
3223 | ||
3224 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
3225 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
3226 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
3227 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
3228 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
3229 | addr[3] = mac_addr_h & 0xFF; | |
3230 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
3231 | addr[5] = mac_addr_l & 0xFF; | |
3232 | } | |
3233 | ||
c5aff182 TP |
3234 | /* Handle setting mac address */ |
3235 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
3236 | { | |
3237 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
3238 | struct sockaddr *sockaddr = addr; |
3239 | int ret; | |
c5aff182 | 3240 | |
e68de360 EG |
3241 | ret = eth_prepare_mac_addr_change(dev, addr); |
3242 | if (ret < 0) | |
3243 | return ret; | |
c5aff182 TP |
3244 | /* Remove previous address table entry */ |
3245 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
3246 | ||
3247 | /* Set new addr in hw */ | |
90b74c01 | 3248 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 3249 | |
e68de360 | 3250 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
3251 | return 0; |
3252 | } | |
3253 | ||
3254 | static void mvneta_adjust_link(struct net_device *ndev) | |
3255 | { | |
3256 | struct mvneta_port *pp = netdev_priv(ndev); | |
c6c022e3 | 3257 | struct phy_device *phydev = ndev->phydev; |
c5aff182 TP |
3258 | int status_change = 0; |
3259 | ||
3260 | if (phydev->link) { | |
3261 | if ((pp->speed != phydev->speed) || | |
3262 | (pp->duplex != phydev->duplex)) { | |
3263 | u32 val; | |
3264 | ||
3265 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3266 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3267 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
898b2970 | 3268 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); |
c5aff182 TP |
3269 | |
3270 | if (phydev->duplex) | |
3271 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3272 | ||
3273 | if (phydev->speed == SPEED_1000) | |
3274 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
4d12bc63 | 3275 | else if (phydev->speed == SPEED_100) |
c5aff182 TP |
3276 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
3277 | ||
3278 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3279 | ||
3280 | pp->duplex = phydev->duplex; | |
3281 | pp->speed = phydev->speed; | |
3282 | } | |
3283 | } | |
3284 | ||
3285 | if (phydev->link != pp->link) { | |
3286 | if (!phydev->link) { | |
3287 | pp->duplex = -1; | |
3288 | pp->speed = 0; | |
3289 | } | |
3290 | ||
3291 | pp->link = phydev->link; | |
3292 | status_change = 1; | |
3293 | } | |
3294 | ||
3295 | if (status_change) { | |
3296 | if (phydev->link) { | |
898b2970 SS |
3297 | if (!pp->use_inband_status) { |
3298 | u32 val = mvreg_read(pp, | |
3299 | MVNETA_GMAC_AUTONEG_CONFIG); | |
3300 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
3301 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
3302 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3303 | val); | |
3304 | } | |
c5aff182 | 3305 | mvneta_port_up(pp); |
c5aff182 | 3306 | } else { |
898b2970 SS |
3307 | if (!pp->use_inband_status) { |
3308 | u32 val = mvreg_read(pp, | |
3309 | MVNETA_GMAC_AUTONEG_CONFIG); | |
3310 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
3311 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
3312 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3313 | val); | |
3314 | } | |
c5aff182 | 3315 | mvneta_port_down(pp); |
c5aff182 | 3316 | } |
0089b745 | 3317 | phy_print_status(phydev); |
c5aff182 TP |
3318 | } |
3319 | } | |
3320 | ||
3321 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
3322 | { | |
3323 | struct phy_device *phy_dev; | |
82960fff | 3324 | struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; |
c5aff182 TP |
3325 | |
3326 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, | |
3327 | pp->phy_interface); | |
3328 | if (!phy_dev) { | |
3329 | netdev_err(pp->dev, "could not find the PHY\n"); | |
3330 | return -ENODEV; | |
3331 | } | |
3332 | ||
82960fff JZ |
3333 | phy_ethtool_get_wol(phy_dev, &wol); |
3334 | device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); | |
3335 | ||
c5aff182 TP |
3336 | phy_dev->supported &= PHY_GBIT_FEATURES; |
3337 | phy_dev->advertising = phy_dev->supported; | |
3338 | ||
c5aff182 TP |
3339 | pp->link = 0; |
3340 | pp->duplex = 0; | |
3341 | pp->speed = 0; | |
3342 | ||
3343 | return 0; | |
3344 | } | |
3345 | ||
3346 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
3347 | { | |
c6c022e3 PR |
3348 | struct net_device *ndev = pp->dev; |
3349 | ||
3350 | phy_disconnect(ndev->phydev); | |
c5aff182 TP |
3351 | } |
3352 | ||
120cfa50 GC |
3353 | /* Electing a CPU must be done in an atomic way: it should be done |
3354 | * after or before the removal/insertion of a CPU and this function is | |
3355 | * not reentrant. | |
3356 | */ | |
f8642885 MR |
3357 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
3358 | { | |
cad5d847 GC |
3359 | int elected_cpu = 0, max_cpu, cpu, i = 0; |
3360 | ||
3361 | /* Use the cpu associated to the rxq when it is online, in all | |
3362 | * the other cases, use the cpu 0 which can't be offline. | |
3363 | */ | |
3364 | if (cpu_online(pp->rxq_def)) | |
3365 | elected_cpu = pp->rxq_def; | |
f8642885 | 3366 | |
2dcf75e2 | 3367 | max_cpu = num_present_cpus(); |
f8642885 MR |
3368 | |
3369 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
3370 | int rxq_map = 0, txq_map = 0; |
3371 | int rxq; | |
3372 | ||
3373 | for (rxq = 0; rxq < rxq_number; rxq++) | |
3374 | if ((rxq % max_cpu) == cpu) | |
3375 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
3376 | ||
cad5d847 | 3377 | if (cpu == elected_cpu) |
50bf8cb6 GC |
3378 | /* Map the default receive queue queue to the |
3379 | * elected CPU | |
f8642885 | 3380 | */ |
2dcf75e2 | 3381 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
3382 | |
3383 | /* We update the TX queue map only if we have one | |
3384 | * queue. In this case we associate the TX queue to | |
3385 | * the CPU bound to the default RX queue | |
3386 | */ | |
3387 | if (txq_number == 1) | |
cad5d847 | 3388 | txq_map = (cpu == elected_cpu) ? |
50bf8cb6 GC |
3389 | MVNETA_CPU_TXQ_ACCESS(1) : 0; |
3390 | else | |
3391 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
3392 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
3393 | ||
2dcf75e2 GC |
3394 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
3395 | ||
3396 | /* Update the interrupt mask on each CPU according the | |
3397 | * new mapping | |
3398 | */ | |
3399 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
3400 | pp, true); | |
f8642885 | 3401 | i++; |
2dcf75e2 | 3402 | |
f8642885 MR |
3403 | } |
3404 | }; | |
3405 | ||
84a3f4db | 3406 | static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) |
f8642885 | 3407 | { |
84a3f4db SAS |
3408 | int other_cpu; |
3409 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3410 | node_online); | |
f8642885 MR |
3411 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
3412 | ||
f8642885 | 3413 | |
84a3f4db SAS |
3414 | spin_lock(&pp->lock); |
3415 | /* | |
3416 | * Configuring the driver for a new CPU while the driver is | |
3417 | * stopping is racy, so just avoid it. | |
3418 | */ | |
3419 | if (pp->is_stopped) { | |
3420 | spin_unlock(&pp->lock); | |
3421 | return 0; | |
3422 | } | |
3423 | netif_tx_stop_all_queues(pp->dev); | |
f8642885 | 3424 | |
84a3f4db SAS |
3425 | /* |
3426 | * We have to synchronise on tha napi of each CPU except the one | |
3427 | * just being woken up | |
3428 | */ | |
3429 | for_each_online_cpu(other_cpu) { | |
3430 | if (other_cpu != cpu) { | |
3431 | struct mvneta_pcpu_port *other_port = | |
3432 | per_cpu_ptr(pp->ports, other_cpu); | |
3433 | ||
3434 | napi_synchronize(&other_port->napi); | |
f8642885 | 3435 | } |
84a3f4db | 3436 | } |
f8642885 | 3437 | |
84a3f4db SAS |
3438 | /* Mask all ethernet port interrupts */ |
3439 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
3440 | napi_enable(&port->napi); | |
f8642885 | 3441 | |
84a3f4db SAS |
3442 | /* |
3443 | * Enable per-CPU interrupts on the CPU that is | |
3444 | * brought up. | |
3445 | */ | |
3446 | mvneta_percpu_enable(pp); | |
2dcf75e2 | 3447 | |
84a3f4db SAS |
3448 | /* |
3449 | * Enable per-CPU interrupt on the one CPU we care | |
3450 | * about. | |
3451 | */ | |
3452 | mvneta_percpu_elect(pp); | |
2dcf75e2 | 3453 | |
84a3f4db SAS |
3454 | /* Unmask all ethernet port interrupts */ |
3455 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
3456 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
3457 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3458 | MVNETA_CAUSE_LINK_CHANGE | | |
3459 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
3460 | netif_tx_start_all_queues(pp->dev); | |
3461 | spin_unlock(&pp->lock); | |
3462 | return 0; | |
3463 | } | |
f8642885 | 3464 | |
84a3f4db SAS |
3465 | static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) |
3466 | { | |
3467 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3468 | node_online); | |
3469 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
f8642885 | 3470 | |
84a3f4db SAS |
3471 | /* |
3472 | * Thanks to this lock we are sure that any pending cpu election is | |
3473 | * done. | |
3474 | */ | |
3475 | spin_lock(&pp->lock); | |
3476 | /* Mask all ethernet port interrupts */ | |
3477 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); | |
3478 | spin_unlock(&pp->lock); | |
f8642885 | 3479 | |
84a3f4db SAS |
3480 | napi_synchronize(&port->napi); |
3481 | napi_disable(&port->napi); | |
3482 | /* Disable per-CPU interrupts on the CPU that is brought down. */ | |
3483 | mvneta_percpu_disable(pp); | |
3484 | return 0; | |
3485 | } | |
3486 | ||
3487 | static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) | |
3488 | { | |
3489 | struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, | |
3490 | node_dead); | |
3491 | ||
3492 | /* Check if a new CPU must be elected now this on is down */ | |
3493 | spin_lock(&pp->lock); | |
3494 | mvneta_percpu_elect(pp); | |
3495 | spin_unlock(&pp->lock); | |
3496 | /* Unmask all ethernet port interrupts */ | |
3497 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
3498 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
3499 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3500 | MVNETA_CAUSE_LINK_CHANGE | | |
3501 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
3502 | netif_tx_start_all_queues(pp->dev); | |
3503 | return 0; | |
f8642885 MR |
3504 | } |
3505 | ||
c5aff182 TP |
3506 | static int mvneta_open(struct net_device *dev) |
3507 | { | |
3508 | struct mvneta_port *pp = netdev_priv(dev); | |
6b125d63 | 3509 | int ret; |
c5aff182 | 3510 | |
c5aff182 | 3511 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
8ec2cd48 | 3512 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
3513 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
3514 | |
3515 | ret = mvneta_setup_rxqs(pp); | |
3516 | if (ret) | |
3517 | return ret; | |
3518 | ||
3519 | ret = mvneta_setup_txqs(pp); | |
3520 | if (ret) | |
3521 | goto err_cleanup_rxqs; | |
3522 | ||
3523 | /* Connect to port interrupt line */ | |
2636ac3c MW |
3524 | if (pp->neta_armada3700) |
3525 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, | |
3526 | dev->name, pp); | |
3527 | else | |
3528 | ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, | |
3529 | dev->name, pp->ports); | |
c5aff182 TP |
3530 | if (ret) { |
3531 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
3532 | goto err_cleanup_txqs; | |
3533 | } | |
3534 | ||
2636ac3c MW |
3535 | if (!pp->neta_armada3700) { |
3536 | /* Enable per-CPU interrupt on all the CPU to handle our RX | |
3537 | * queue interrupts | |
3538 | */ | |
3539 | on_each_cpu(mvneta_percpu_enable, pp, true); | |
2dcf75e2 | 3540 | |
2636ac3c MW |
3541 | pp->is_stopped = false; |
3542 | /* Register a CPU notifier to handle the case where our CPU | |
3543 | * might be taken offline. | |
3544 | */ | |
3545 | ret = cpuhp_state_add_instance_nocalls(online_hpstate, | |
3546 | &pp->node_online); | |
3547 | if (ret) | |
3548 | goto err_free_irq; | |
84a3f4db | 3549 | |
2636ac3c MW |
3550 | ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, |
3551 | &pp->node_dead); | |
3552 | if (ret) | |
3553 | goto err_free_online_hp; | |
3554 | } | |
f8642885 | 3555 | |
c5aff182 TP |
3556 | /* In default link is down */ |
3557 | netif_carrier_off(pp->dev); | |
3558 | ||
3559 | ret = mvneta_mdio_probe(pp); | |
3560 | if (ret < 0) { | |
3561 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
84a3f4db | 3562 | goto err_free_dead_hp; |
c5aff182 TP |
3563 | } |
3564 | ||
3565 | mvneta_start_dev(pp); | |
3566 | ||
3567 | return 0; | |
3568 | ||
84a3f4db | 3569 | err_free_dead_hp: |
2636ac3c MW |
3570 | if (!pp->neta_armada3700) |
3571 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
3572 | &pp->node_dead); | |
84a3f4db | 3573 | err_free_online_hp: |
2636ac3c MW |
3574 | if (!pp->neta_armada3700) |
3575 | cpuhp_state_remove_instance_nocalls(online_hpstate, | |
3576 | &pp->node_online); | |
c5aff182 | 3577 | err_free_irq: |
2636ac3c MW |
3578 | if (pp->neta_armada3700) { |
3579 | free_irq(pp->dev->irq, pp); | |
3580 | } else { | |
3581 | on_each_cpu(mvneta_percpu_disable, pp, true); | |
3582 | free_percpu_irq(pp->dev->irq, pp->ports); | |
3583 | } | |
c5aff182 TP |
3584 | err_cleanup_txqs: |
3585 | mvneta_cleanup_txqs(pp); | |
3586 | err_cleanup_rxqs: | |
3587 | mvneta_cleanup_rxqs(pp); | |
3588 | return ret; | |
3589 | } | |
3590 | ||
3591 | /* Stop the port, free port interrupt line */ | |
3592 | static int mvneta_stop(struct net_device *dev) | |
3593 | { | |
3594 | struct mvneta_port *pp = netdev_priv(dev); | |
3595 | ||
2636ac3c MW |
3596 | if (!pp->neta_armada3700) { |
3597 | /* Inform that we are stopping so we don't want to setup the | |
3598 | * driver for new CPUs in the notifiers. The code of the | |
3599 | * notifier for CPU online is protected by the same spinlock, | |
3600 | * so when we get the lock, the notifer work is done. | |
3601 | */ | |
3602 | spin_lock(&pp->lock); | |
3603 | pp->is_stopped = true; | |
3604 | spin_unlock(&pp->lock); | |
1c2722a9 | 3605 | |
2636ac3c MW |
3606 | mvneta_stop_dev(pp); |
3607 | mvneta_mdio_remove(pp); | |
84a3f4db | 3608 | |
d26aac2d DC |
3609 | cpuhp_state_remove_instance_nocalls(online_hpstate, |
3610 | &pp->node_online); | |
3611 | cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, | |
3612 | &pp->node_dead); | |
2636ac3c MW |
3613 | on_each_cpu(mvneta_percpu_disable, pp, true); |
3614 | free_percpu_irq(dev->irq, pp->ports); | |
3615 | } else { | |
3616 | mvneta_stop_dev(pp); | |
3617 | mvneta_mdio_remove(pp); | |
3618 | free_irq(dev->irq, pp); | |
3619 | } | |
3620 | ||
c5aff182 TP |
3621 | mvneta_cleanup_rxqs(pp); |
3622 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
3623 | |
3624 | return 0; | |
3625 | } | |
3626 | ||
15f59456 TP |
3627 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3628 | { | |
c6c022e3 | 3629 | if (!dev->phydev) |
15f59456 TP |
3630 | return -ENOTSUPP; |
3631 | ||
c6c022e3 | 3632 | return phy_mii_ioctl(dev->phydev, ifr, cmd); |
15f59456 TP |
3633 | } |
3634 | ||
c5aff182 TP |
3635 | /* Ethtool methods */ |
3636 | ||
013ad40d | 3637 | /* Set link ksettings (phy address, speed) for ethtools */ |
2dc0d2b4 BX |
3638 | static int |
3639 | mvneta_ethtool_set_link_ksettings(struct net_device *ndev, | |
3640 | const struct ethtool_link_ksettings *cmd) | |
c5aff182 | 3641 | { |
013ad40d PR |
3642 | struct mvneta_port *pp = netdev_priv(ndev); |
3643 | struct phy_device *phydev = ndev->phydev; | |
c5aff182 | 3644 | |
0c0744fc | 3645 | if (!phydev) |
c5aff182 TP |
3646 | return -ENODEV; |
3647 | ||
013ad40d | 3648 | if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) { |
0c0744fc SS |
3649 | u32 val; |
3650 | ||
013ad40d | 3651 | mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE); |
0c0744fc | 3652 | |
013ad40d | 3653 | if (cmd->base.autoneg == AUTONEG_DISABLE) { |
0c0744fc SS |
3654 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3655 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3656 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3657 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); | |
3658 | ||
3659 | if (phydev->duplex) | |
3660 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3661 | ||
3662 | if (phydev->speed == SPEED_1000) | |
3663 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
3664 | else if (phydev->speed == SPEED_100) | |
3665 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
3666 | ||
3667 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3668 | } | |
3669 | ||
013ad40d | 3670 | pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE); |
0c0744fc SS |
3671 | netdev_info(pp->dev, "autoneg status set to %i\n", |
3672 | pp->use_inband_status); | |
3673 | ||
013ad40d | 3674 | if (netif_running(ndev)) { |
0c0744fc SS |
3675 | mvneta_port_down(pp); |
3676 | mvneta_port_up(pp); | |
3677 | } | |
3678 | } | |
3679 | ||
013ad40d | 3680 | return phy_ethtool_ksettings_set(ndev->phydev, cmd); |
c5aff182 TP |
3681 | } |
3682 | ||
3683 | /* Set interrupt coalescing for ethtools */ | |
3684 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
3685 | struct ethtool_coalesce *c) | |
3686 | { | |
3687 | struct mvneta_port *pp = netdev_priv(dev); | |
3688 | int queue; | |
3689 | ||
3690 | for (queue = 0; queue < rxq_number; queue++) { | |
3691 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3692 | rxq->time_coal = c->rx_coalesce_usecs; | |
3693 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
3694 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3695 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3696 | } | |
3697 | ||
3698 | for (queue = 0; queue < txq_number; queue++) { | |
3699 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3700 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
3701 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3702 | } | |
3703 | ||
3704 | return 0; | |
3705 | } | |
3706 | ||
3707 | /* get coalescing for ethtools */ | |
3708 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
3709 | struct ethtool_coalesce *c) | |
3710 | { | |
3711 | struct mvneta_port *pp = netdev_priv(dev); | |
3712 | ||
3713 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
3714 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
3715 | ||
3716 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
3717 | return 0; | |
3718 | } | |
3719 | ||
3720 | ||
3721 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
3722 | struct ethtool_drvinfo *drvinfo) | |
3723 | { | |
3724 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
3725 | sizeof(drvinfo->driver)); | |
3726 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
3727 | sizeof(drvinfo->version)); | |
3728 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
3729 | sizeof(drvinfo->bus_info)); | |
3730 | } | |
3731 | ||
3732 | ||
3733 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
3734 | struct ethtool_ringparam *ring) | |
3735 | { | |
3736 | struct mvneta_port *pp = netdev_priv(netdev); | |
3737 | ||
3738 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
3739 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
3740 | ring->rx_pending = pp->rx_ring_size; | |
3741 | ring->tx_pending = pp->tx_ring_size; | |
3742 | } | |
3743 | ||
3744 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
3745 | struct ethtool_ringparam *ring) | |
3746 | { | |
3747 | struct mvneta_port *pp = netdev_priv(dev); | |
3748 | ||
3749 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
3750 | return -EINVAL; | |
3751 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
3752 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
3753 | |
3754 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
3755 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
3756 | if (pp->tx_ring_size != ring->tx_pending) | |
3757 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
3758 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
3759 | |
3760 | if (netif_running(dev)) { | |
3761 | mvneta_stop(dev); | |
3762 | if (mvneta_open(dev)) { | |
3763 | netdev_err(dev, | |
3764 | "error on opening device after ring param change\n"); | |
3765 | return -ENOMEM; | |
3766 | } | |
3767 | } | |
3768 | ||
3769 | return 0; | |
3770 | } | |
3771 | ||
9b0cdefa RK |
3772 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
3773 | u8 *data) | |
3774 | { | |
3775 | if (sset == ETH_SS_STATS) { | |
3776 | int i; | |
3777 | ||
3778 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3779 | memcpy(data + i * ETH_GSTRING_LEN, | |
3780 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
3781 | } | |
3782 | } | |
3783 | ||
3784 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) | |
3785 | { | |
3786 | const struct mvneta_statistic *s; | |
3787 | void __iomem *base = pp->base; | |
3788 | u32 high, low, val; | |
2c832293 | 3789 | u64 val64; |
9b0cdefa RK |
3790 | int i; |
3791 | ||
3792 | for (i = 0, s = mvneta_statistics; | |
3793 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
3794 | s++, i++) { | |
9b0cdefa RK |
3795 | switch (s->type) { |
3796 | case T_REG_32: | |
3797 | val = readl_relaxed(base + s->offset); | |
2c832293 | 3798 | pp->ethtool_stats[i] += val; |
9b0cdefa RK |
3799 | break; |
3800 | case T_REG_64: | |
3801 | /* Docs say to read low 32-bit then high */ | |
3802 | low = readl_relaxed(base + s->offset); | |
3803 | high = readl_relaxed(base + s->offset + 4); | |
2c832293 JZ |
3804 | val64 = (u64)high << 32 | low; |
3805 | pp->ethtool_stats[i] += val64; | |
9b0cdefa RK |
3806 | break; |
3807 | } | |
9b0cdefa RK |
3808 | } |
3809 | } | |
3810 | ||
3811 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
3812 | struct ethtool_stats *stats, u64 *data) | |
3813 | { | |
3814 | struct mvneta_port *pp = netdev_priv(dev); | |
3815 | int i; | |
3816 | ||
3817 | mvneta_ethtool_update_stats(pp); | |
3818 | ||
3819 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3820 | *data++ = pp->ethtool_stats[i]; | |
3821 | } | |
3822 | ||
3823 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
3824 | { | |
3825 | if (sset == ETH_SS_STATS) | |
3826 | return ARRAY_SIZE(mvneta_statistics); | |
3827 | return -EOPNOTSUPP; | |
3828 | } | |
3829 | ||
9a401dea GC |
3830 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
3831 | { | |
3832 | return MVNETA_RSS_LU_TABLE_SIZE; | |
3833 | } | |
3834 | ||
3835 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
3836 | struct ethtool_rxnfc *info, | |
3837 | u32 *rules __always_unused) | |
3838 | { | |
3839 | switch (info->cmd) { | |
3840 | case ETHTOOL_GRXRINGS: | |
3841 | info->data = rxq_number; | |
3842 | return 0; | |
3843 | case ETHTOOL_GRXFH: | |
3844 | return -EOPNOTSUPP; | |
3845 | default: | |
3846 | return -EOPNOTSUPP; | |
3847 | } | |
3848 | } | |
3849 | ||
3850 | static int mvneta_config_rss(struct mvneta_port *pp) | |
3851 | { | |
3852 | int cpu; | |
3853 | u32 val; | |
3854 | ||
3855 | netif_tx_stop_all_queues(pp->dev); | |
3856 | ||
6b125d63 | 3857 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
9a401dea GC |
3858 | |
3859 | /* We have to synchronise on the napi of each CPU */ | |
3860 | for_each_online_cpu(cpu) { | |
3861 | struct mvneta_pcpu_port *pcpu_port = | |
3862 | per_cpu_ptr(pp->ports, cpu); | |
3863 | ||
3864 | napi_synchronize(&pcpu_port->napi); | |
3865 | napi_disable(&pcpu_port->napi); | |
3866 | } | |
3867 | ||
3868 | pp->rxq_def = pp->indir[0]; | |
3869 | ||
3870 | /* Update unicast mapping */ | |
3871 | mvneta_set_rx_mode(pp->dev); | |
3872 | ||
3873 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
3874 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
3875 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
3876 | ||
3877 | /* Update the elected CPU matching the new rxq_def */ | |
120cfa50 | 3878 | spin_lock(&pp->lock); |
9a401dea | 3879 | mvneta_percpu_elect(pp); |
120cfa50 | 3880 | spin_unlock(&pp->lock); |
9a401dea GC |
3881 | |
3882 | /* We have to synchronise on the napi of each CPU */ | |
3883 | for_each_online_cpu(cpu) { | |
3884 | struct mvneta_pcpu_port *pcpu_port = | |
3885 | per_cpu_ptr(pp->ports, cpu); | |
3886 | ||
3887 | napi_enable(&pcpu_port->napi); | |
3888 | } | |
3889 | ||
3890 | netif_tx_start_all_queues(pp->dev); | |
3891 | ||
3892 | return 0; | |
3893 | } | |
3894 | ||
3895 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
3896 | const u8 *key, const u8 hfunc) | |
3897 | { | |
3898 | struct mvneta_port *pp = netdev_priv(dev); | |
2636ac3c MW |
3899 | |
3900 | /* Current code for Armada 3700 doesn't support RSS features yet */ | |
3901 | if (pp->neta_armada3700) | |
3902 | return -EOPNOTSUPP; | |
3903 | ||
9a401dea GC |
3904 | /* We require at least one supported parameter to be changed |
3905 | * and no change in any of the unsupported parameters | |
3906 | */ | |
3907 | if (key || | |
3908 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
3909 | return -EOPNOTSUPP; | |
3910 | ||
3911 | if (!indir) | |
3912 | return 0; | |
3913 | ||
3914 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3915 | ||
3916 | return mvneta_config_rss(pp); | |
3917 | } | |
3918 | ||
3919 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
3920 | u8 *hfunc) | |
3921 | { | |
3922 | struct mvneta_port *pp = netdev_priv(dev); | |
3923 | ||
2636ac3c MW |
3924 | /* Current code for Armada 3700 doesn't support RSS features yet */ |
3925 | if (pp->neta_armada3700) | |
3926 | return -EOPNOTSUPP; | |
3927 | ||
9a401dea GC |
3928 | if (hfunc) |
3929 | *hfunc = ETH_RSS_HASH_TOP; | |
3930 | ||
3931 | if (!indir) | |
3932 | return 0; | |
3933 | ||
3934 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3935 | ||
3936 | return 0; | |
3937 | } | |
3938 | ||
b60a00f9 JH |
3939 | static void mvneta_ethtool_get_wol(struct net_device *dev, |
3940 | struct ethtool_wolinfo *wol) | |
3941 | { | |
3942 | wol->supported = 0; | |
3943 | wol->wolopts = 0; | |
3944 | ||
3945 | if (dev->phydev) | |
3946 | phy_ethtool_get_wol(dev->phydev, wol); | |
3947 | } | |
3948 | ||
3949 | static int mvneta_ethtool_set_wol(struct net_device *dev, | |
3950 | struct ethtool_wolinfo *wol) | |
3951 | { | |
82960fff JZ |
3952 | int ret; |
3953 | ||
b60a00f9 JH |
3954 | if (!dev->phydev) |
3955 | return -EOPNOTSUPP; | |
3956 | ||
82960fff JZ |
3957 | ret = phy_ethtool_set_wol(dev->phydev, wol); |
3958 | if (!ret) | |
3959 | device_set_wakeup_enable(&dev->dev, !!wol->wolopts); | |
3960 | ||
3961 | return ret; | |
b60a00f9 JH |
3962 | } |
3963 | ||
c5aff182 TP |
3964 | static const struct net_device_ops mvneta_netdev_ops = { |
3965 | .ndo_open = mvneta_open, | |
3966 | .ndo_stop = mvneta_stop, | |
3967 | .ndo_start_xmit = mvneta_tx, | |
3968 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
3969 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
3970 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 3971 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 3972 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 3973 | .ndo_do_ioctl = mvneta_ioctl, |
c5aff182 TP |
3974 | }; |
3975 | ||
4581be42 | 3976 | static const struct ethtool_ops mvneta_eth_tool_ops = { |
5489ee89 | 3977 | .nway_reset = phy_ethtool_nway_reset, |
c5aff182 | 3978 | .get_link = ethtool_op_get_link, |
c5aff182 TP |
3979 | .set_coalesce = mvneta_ethtool_set_coalesce, |
3980 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
3981 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
3982 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
3983 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
9b0cdefa RK |
3984 | .get_strings = mvneta_ethtool_get_strings, |
3985 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
3986 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
3987 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
3988 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
3989 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
3990 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
013ad40d PR |
3991 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
3992 | .set_link_ksettings = mvneta_ethtool_set_link_ksettings, | |
b60a00f9 JH |
3993 | .get_wol = mvneta_ethtool_get_wol, |
3994 | .set_wol = mvneta_ethtool_set_wol, | |
c5aff182 TP |
3995 | }; |
3996 | ||
3997 | /* Initialize hw */ | |
9672850b | 3998 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
3999 | { |
4000 | int queue; | |
4001 | ||
4002 | /* Disable port */ | |
4003 | mvneta_port_disable(pp); | |
4004 | ||
4005 | /* Set port default values */ | |
4006 | mvneta_defaults_set(pp); | |
4007 | ||
5d6312ed | 4008 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); |
c5aff182 TP |
4009 | if (!pp->txqs) |
4010 | return -ENOMEM; | |
4011 | ||
4012 | /* Initialize TX descriptor rings */ | |
4013 | for (queue = 0; queue < txq_number; queue++) { | |
4014 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
4015 | txq->id = queue; | |
4016 | txq->size = pp->tx_ring_size; | |
4017 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
4018 | } | |
4019 | ||
5d6312ed | 4020 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); |
9672850b | 4021 | if (!pp->rxqs) |
c5aff182 | 4022 | return -ENOMEM; |
c5aff182 TP |
4023 | |
4024 | /* Create Rx descriptor rings */ | |
4025 | for (queue = 0; queue < rxq_number; queue++) { | |
4026 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
4027 | rxq->id = queue; | |
4028 | rxq->size = pp->rx_ring_size; | |
4029 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
4030 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
29110630 ME |
4031 | rxq->buf_virt_addr |
4032 | = devm_kmalloc_array(pp->dev->dev.parent, | |
4033 | rxq->size, | |
4034 | sizeof(*rxq->buf_virt_addr), | |
4035 | GFP_KERNEL); | |
f88bee1c GC |
4036 | if (!rxq->buf_virt_addr) |
4037 | return -ENOMEM; | |
c5aff182 TP |
4038 | } |
4039 | ||
4040 | return 0; | |
4041 | } | |
4042 | ||
c5aff182 | 4043 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
4044 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
4045 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
4046 | { |
4047 | u32 win_enable; | |
4048 | u32 win_protect; | |
4049 | int i; | |
4050 | ||
4051 | for (i = 0; i < 6; i++) { | |
4052 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
4053 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
4054 | ||
4055 | if (i < 4) | |
4056 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
4057 | } | |
4058 | ||
4059 | win_enable = 0x3f; | |
4060 | win_protect = 0; | |
4061 | ||
2636ac3c MW |
4062 | if (dram) { |
4063 | for (i = 0; i < dram->num_cs; i++) { | |
4064 | const struct mbus_dram_window *cs = dram->cs + i; | |
4065 | ||
4066 | mvreg_write(pp, MVNETA_WIN_BASE(i), | |
4067 | (cs->base & 0xffff0000) | | |
4068 | (cs->mbus_attr << 8) | | |
4069 | dram->mbus_dram_target_id); | |
c5aff182 | 4070 | |
2636ac3c MW |
4071 | mvreg_write(pp, MVNETA_WIN_SIZE(i), |
4072 | (cs->size - 1) & 0xffff0000); | |
c5aff182 | 4073 | |
2636ac3c MW |
4074 | win_enable &= ~(1 << i); |
4075 | win_protect |= 3 << (2 * i); | |
4076 | } | |
4077 | } else { | |
4078 | /* For Armada3700 open default 4GB Mbus window, leaving | |
4079 | * arbitration of target/attribute to a different layer | |
4080 | * of configuration. | |
4081 | */ | |
4082 | mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); | |
4083 | win_enable &= ~BIT(0); | |
4084 | win_protect = 3; | |
c5aff182 TP |
4085 | } |
4086 | ||
4087 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 4088 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
4089 | } |
4090 | ||
4091 | /* Power up the port */ | |
3f1dd4bc | 4092 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 4093 | { |
3f1dd4bc | 4094 | u32 ctrl; |
c5aff182 TP |
4095 | |
4096 | /* MAC Cause register should be cleared */ | |
4097 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
4098 | ||
3f1dd4bc | 4099 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
c5aff182 | 4100 | |
3f1dd4bc TP |
4101 | /* Even though it might look weird, when we're configured in |
4102 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
4103 | */ | |
4104 | switch(phy_mode) { | |
4105 | case PHY_INTERFACE_MODE_QSGMII: | |
4106 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
4107 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
4108 | break; | |
4109 | case PHY_INTERFACE_MODE_SGMII: | |
4110 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
4111 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
4112 | break; | |
4113 | case PHY_INTERFACE_MODE_RGMII: | |
4114 | case PHY_INTERFACE_MODE_RGMII_ID: | |
a38d20d7 JZ |
4115 | case PHY_INTERFACE_MODE_RGMII_RXID: |
4116 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
3f1dd4bc TP |
4117 | ctrl |= MVNETA_GMAC2_PORT_RGMII; |
4118 | break; | |
4119 | default: | |
4120 | return -EINVAL; | |
4121 | } | |
c5aff182 TP |
4122 | |
4123 | /* Cancel Port Reset */ | |
3f1dd4bc TP |
4124 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; |
4125 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
c5aff182 TP |
4126 | |
4127 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
4128 | MVNETA_GMAC2_PORT_RESET) != 0) | |
4129 | continue; | |
3f1dd4bc TP |
4130 | |
4131 | return 0; | |
c5aff182 TP |
4132 | } |
4133 | ||
4134 | /* Device initialization routine */ | |
03ce758e | 4135 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 | 4136 | { |
c3f0dd38 | 4137 | struct resource *res; |
c5aff182 TP |
4138 | struct device_node *dn = pdev->dev.of_node; |
4139 | struct device_node *phy_node; | |
dc35a10f | 4140 | struct device_node *bm_node; |
c5aff182 TP |
4141 | struct mvneta_port *pp; |
4142 | struct net_device *dev; | |
8cc3e439 TP |
4143 | const char *dt_mac_addr; |
4144 | char hw_mac_addr[ETH_ALEN]; | |
4145 | const char *mac_from; | |
f8af8e6e | 4146 | const char *managed; |
9110ee07 | 4147 | int tx_csum_limit; |
c5aff182 TP |
4148 | int phy_mode; |
4149 | int err; | |
12bb03b4 | 4150 | int cpu; |
c5aff182 | 4151 | |
ee40a116 | 4152 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
c5aff182 TP |
4153 | if (!dev) |
4154 | return -ENOMEM; | |
4155 | ||
4156 | dev->irq = irq_of_parse_and_map(dn, 0); | |
4157 | if (dev->irq == 0) { | |
4158 | err = -EINVAL; | |
4159 | goto err_free_netdev; | |
4160 | } | |
4161 | ||
4162 | phy_node = of_parse_phandle(dn, "phy", 0); | |
4163 | if (!phy_node) { | |
83895bed TP |
4164 | if (!of_phy_is_fixed_link(dn)) { |
4165 | dev_err(&pdev->dev, "no PHY specified\n"); | |
4166 | err = -ENODEV; | |
4167 | goto err_free_irq; | |
4168 | } | |
4169 | ||
4170 | err = of_phy_register_fixed_link(dn); | |
4171 | if (err < 0) { | |
4172 | dev_err(&pdev->dev, "cannot register fixed PHY\n"); | |
4173 | goto err_free_irq; | |
4174 | } | |
4175 | ||
4176 | /* In the case of a fixed PHY, the DT node associated | |
4177 | * to the PHY is the Ethernet MAC DT node. | |
4178 | */ | |
c891c24c | 4179 | phy_node = of_node_get(dn); |
c5aff182 TP |
4180 | } |
4181 | ||
4182 | phy_mode = of_get_phy_mode(dn); | |
4183 | if (phy_mode < 0) { | |
4184 | dev_err(&pdev->dev, "incorrect phy-mode\n"); | |
4185 | err = -EINVAL; | |
c891c24c | 4186 | goto err_put_phy_node; |
c5aff182 TP |
4187 | } |
4188 | ||
c5aff182 TP |
4189 | dev->tx_queue_len = MVNETA_MAX_TXD; |
4190 | dev->watchdog_timeo = 5 * HZ; | |
4191 | dev->netdev_ops = &mvneta_netdev_ops; | |
4192 | ||
7ad24ea4 | 4193 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 TP |
4194 | |
4195 | pp = netdev_priv(dev); | |
1c2722a9 | 4196 | spin_lock_init(&pp->lock); |
c5aff182 TP |
4197 | pp->phy_node = phy_node; |
4198 | pp->phy_interface = phy_mode; | |
f8af8e6e SS |
4199 | |
4200 | err = of_property_read_string(dn, "managed", &managed); | |
4201 | pp->use_inband_status = (err == 0 && | |
4202 | strcmp(managed, "in-band-status") == 0); | |
c5aff182 | 4203 | |
90b74c01 GC |
4204 | pp->rxq_def = rxq_def; |
4205 | ||
8d5047cf MW |
4206 | /* Set RX packet offset correction for platforms, whose |
4207 | * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit | |
4208 | * platforms and 0B for 32-bit ones. | |
4209 | */ | |
4210 | pp->rx_offset_correction = | |
4211 | max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION); | |
4212 | ||
9a401dea GC |
4213 | pp->indir[0] = rxq_def; |
4214 | ||
2636ac3c MW |
4215 | /* Get special SoC configurations */ |
4216 | if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) | |
4217 | pp->neta_armada3700 = true; | |
4218 | ||
2804ba4e JZ |
4219 | pp->clk = devm_clk_get(&pdev->dev, "core"); |
4220 | if (IS_ERR(pp->clk)) | |
4221 | pp->clk = devm_clk_get(&pdev->dev, NULL); | |
189dd626 TP |
4222 | if (IS_ERR(pp->clk)) { |
4223 | err = PTR_ERR(pp->clk); | |
c891c24c | 4224 | goto err_put_phy_node; |
189dd626 TP |
4225 | } |
4226 | ||
4227 | clk_prepare_enable(pp->clk); | |
4228 | ||
15cc4a4a JZ |
4229 | pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); |
4230 | if (!IS_ERR(pp->clk_bus)) | |
4231 | clk_prepare_enable(pp->clk_bus); | |
4232 | ||
c3f0dd38 TP |
4233 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4234 | pp->base = devm_ioremap_resource(&pdev->dev, res); | |
4235 | if (IS_ERR(pp->base)) { | |
4236 | err = PTR_ERR(pp->base); | |
5445eaf3 AP |
4237 | goto err_clk; |
4238 | } | |
4239 | ||
12bb03b4 MR |
4240 | /* Alloc per-cpu port structure */ |
4241 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
4242 | if (!pp->ports) { | |
4243 | err = -ENOMEM; | |
4244 | goto err_clk; | |
4245 | } | |
4246 | ||
74c41b04 | 4247 | /* Alloc per-cpu stats */ |
1c213bd2 | 4248 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 4249 | if (!pp->stats) { |
4250 | err = -ENOMEM; | |
12bb03b4 | 4251 | goto err_free_ports; |
74c41b04 | 4252 | } |
4253 | ||
8cc3e439 | 4254 | dt_mac_addr = of_get_mac_address(dn); |
6c7a9a3c | 4255 | if (dt_mac_addr) { |
8cc3e439 TP |
4256 | mac_from = "device tree"; |
4257 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); | |
4258 | } else { | |
4259 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
4260 | if (is_valid_ether_addr(hw_mac_addr)) { | |
4261 | mac_from = "hardware"; | |
4262 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
4263 | } else { | |
4264 | mac_from = "random"; | |
4265 | eth_hw_addr_random(dev); | |
4266 | } | |
4267 | } | |
4268 | ||
9110ee07 MW |
4269 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
4270 | if (tx_csum_limit < 0 || | |
4271 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
4272 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4273 | dev_info(&pdev->dev, | |
4274 | "Wrong TX csum limit in DT, set to %dB\n", | |
4275 | MVNETA_TX_CSUM_DEF_SIZE); | |
4276 | } | |
4277 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
4278 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4279 | } else { | |
4280 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
4281 | } | |
4282 | ||
4283 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 4284 | |
9768b45c | 4285 | pp->dram_target_info = mv_mbus_dram_info(); |
2636ac3c MW |
4286 | /* Armada3700 requires setting default configuration of Mbus |
4287 | * windows, however without using filled mbus_dram_target_info | |
4288 | * structure. | |
4289 | */ | |
9768b45c JL |
4290 | if (pp->dram_target_info || pp->neta_armada3700) |
4291 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
dc35a10f | 4292 | |
c5aff182 TP |
4293 | pp->tx_ring_size = MVNETA_MAX_TXD; |
4294 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
4295 | ||
4296 | pp->dev = dev; | |
4297 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4298 | ||
dc35a10f MW |
4299 | pp->id = global_port_id++; |
4300 | ||
4301 | /* Obtain access to BM resources if enabled and already initialized */ | |
4302 | bm_node = of_parse_phandle(dn, "buffer-manager", 0); | |
4303 | if (bm_node && bm_node->data) { | |
4304 | pp->bm_priv = bm_node->data; | |
4305 | err = mvneta_bm_port_init(pdev, pp); | |
4306 | if (err < 0) { | |
4307 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
4308 | pp->bm_priv = NULL; | |
4309 | } | |
4310 | } | |
d4e4da00 | 4311 | of_node_put(bm_node); |
dc35a10f | 4312 | |
9672850b EG |
4313 | err = mvneta_init(&pdev->dev, pp); |
4314 | if (err < 0) | |
dc35a10f | 4315 | goto err_netdev; |
3f1dd4bc TP |
4316 | |
4317 | err = mvneta_port_power_up(pp, phy_mode); | |
4318 | if (err < 0) { | |
4319 | dev_err(&pdev->dev, "can't power up port\n"); | |
dc35a10f | 4320 | goto err_netdev; |
3f1dd4bc | 4321 | } |
c5aff182 | 4322 | |
2636ac3c MW |
4323 | /* Armada3700 network controller does not support per-cpu |
4324 | * operation, so only single NAPI should be initialized. | |
4325 | */ | |
4326 | if (pp->neta_armada3700) { | |
4327 | netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
4328 | } else { | |
4329 | for_each_present_cpu(cpu) { | |
4330 | struct mvneta_pcpu_port *port = | |
4331 | per_cpu_ptr(pp->ports, cpu); | |
12bb03b4 | 4332 | |
2636ac3c MW |
4333 | netif_napi_add(dev, &port->napi, mvneta_poll, |
4334 | NAPI_POLL_WEIGHT); | |
4335 | port->pp = pp; | |
4336 | } | |
12bb03b4 | 4337 | } |
c5aff182 | 4338 | |
c54a5048 | 4339 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO; |
01ef26ca EG |
4340 | dev->hw_features |= dev->features; |
4341 | dev->vlan_features |= dev->features; | |
97db8afa | 4342 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
8eef5f97 | 4343 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 4344 | |
5777987e JW |
4345 | /* MTU range: 68 - 9676 */ |
4346 | dev->min_mtu = ETH_MIN_MTU; | |
4347 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
4348 | dev->max_mtu = 9676; | |
4349 | ||
c5aff182 TP |
4350 | err = register_netdev(dev); |
4351 | if (err < 0) { | |
4352 | dev_err(&pdev->dev, "failed to register\n"); | |
9672850b | 4353 | goto err_free_stats; |
c5aff182 TP |
4354 | } |
4355 | ||
8cc3e439 TP |
4356 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
4357 | dev->dev_addr); | |
c5aff182 TP |
4358 | |
4359 | platform_set_drvdata(pdev, pp->dev); | |
4360 | ||
898b2970 SS |
4361 | if (pp->use_inband_status) { |
4362 | struct phy_device *phy = of_phy_find_device(dn); | |
4363 | ||
4364 | mvneta_fixed_link_update(pp, phy); | |
04d53b20 | 4365 | |
e5a03bfd | 4366 | put_device(&phy->mdio.dev); |
898b2970 SS |
4367 | } |
4368 | ||
c5aff182 TP |
4369 | return 0; |
4370 | ||
dc35a10f MW |
4371 | err_netdev: |
4372 | unregister_netdev(dev); | |
4373 | if (pp->bm_priv) { | |
4374 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
4375 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
4376 | 1 << pp->id); | |
4377 | } | |
74c41b04 | 4378 | err_free_stats: |
4379 | free_percpu(pp->stats); | |
12bb03b4 MR |
4380 | err_free_ports: |
4381 | free_percpu(pp->ports); | |
5445eaf3 | 4382 | err_clk: |
15cc4a4a | 4383 | clk_disable_unprepare(pp->clk_bus); |
5445eaf3 | 4384 | clk_disable_unprepare(pp->clk); |
c891c24c UKK |
4385 | err_put_phy_node: |
4386 | of_node_put(phy_node); | |
5a57a304 JH |
4387 | if (of_phy_is_fixed_link(dn)) |
4388 | of_phy_deregister_fixed_link(dn); | |
c5aff182 TP |
4389 | err_free_irq: |
4390 | irq_dispose_mapping(dev->irq); | |
4391 | err_free_netdev: | |
4392 | free_netdev(dev); | |
4393 | return err; | |
4394 | } | |
4395 | ||
4396 | /* Device removal routine */ | |
03ce758e | 4397 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
4398 | { |
4399 | struct net_device *dev = platform_get_drvdata(pdev); | |
5a57a304 | 4400 | struct device_node *dn = pdev->dev.of_node; |
c5aff182 TP |
4401 | struct mvneta_port *pp = netdev_priv(dev); |
4402 | ||
4403 | unregister_netdev(dev); | |
15cc4a4a | 4404 | clk_disable_unprepare(pp->clk_bus); |
189dd626 | 4405 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 4406 | free_percpu(pp->ports); |
74c41b04 | 4407 | free_percpu(pp->stats); |
5a57a304 JH |
4408 | if (of_phy_is_fixed_link(dn)) |
4409 | of_phy_deregister_fixed_link(dn); | |
c5aff182 | 4410 | irq_dispose_mapping(dev->irq); |
c891c24c | 4411 | of_node_put(pp->phy_node); |
c5aff182 TP |
4412 | free_netdev(dev); |
4413 | ||
dc35a10f MW |
4414 | if (pp->bm_priv) { |
4415 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
4416 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
4417 | 1 << pp->id); | |
4418 | } | |
4419 | ||
c5aff182 TP |
4420 | return 0; |
4421 | } | |
4422 | ||
9768b45c JL |
4423 | #ifdef CONFIG_PM_SLEEP |
4424 | static int mvneta_suspend(struct device *device) | |
4425 | { | |
4426 | struct net_device *dev = dev_get_drvdata(device); | |
4427 | struct mvneta_port *pp = netdev_priv(dev); | |
4428 | ||
4429 | if (netif_running(dev)) | |
4430 | mvneta_stop(dev); | |
4431 | netif_device_detach(dev); | |
4432 | clk_disable_unprepare(pp->clk_bus); | |
4433 | clk_disable_unprepare(pp->clk); | |
4434 | return 0; | |
4435 | } | |
4436 | ||
4437 | static int mvneta_resume(struct device *device) | |
4438 | { | |
4439 | struct platform_device *pdev = to_platform_device(device); | |
4440 | struct net_device *dev = dev_get_drvdata(device); | |
4441 | struct mvneta_port *pp = netdev_priv(dev); | |
4442 | int err; | |
4443 | ||
4444 | clk_prepare_enable(pp->clk); | |
4445 | if (!IS_ERR(pp->clk_bus)) | |
4446 | clk_prepare_enable(pp->clk_bus); | |
4447 | if (pp->dram_target_info || pp->neta_armada3700) | |
4448 | mvneta_conf_mbus_windows(pp, pp->dram_target_info); | |
4449 | if (pp->bm_priv) { | |
4450 | err = mvneta_bm_port_init(pdev, pp); | |
4451 | if (err < 0) { | |
4452 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
4453 | pp->bm_priv = NULL; | |
4454 | } | |
4455 | } | |
4456 | mvneta_defaults_set(pp); | |
4457 | err = mvneta_port_power_up(pp, pp->phy_interface); | |
4458 | if (err < 0) { | |
4459 | dev_err(device, "can't power up port\n"); | |
4460 | return err; | |
4461 | } | |
4462 | ||
4463 | if (pp->use_inband_status) | |
4464 | mvneta_fixed_link_update(pp, dev->phydev); | |
4465 | ||
4466 | netif_device_attach(dev); | |
d6956ac8 | 4467 | if (netif_running(dev)) { |
9768b45c | 4468 | mvneta_open(dev); |
d6956ac8 JZ |
4469 | mvneta_set_rx_mode(dev); |
4470 | } | |
4471 | ||
9768b45c JL |
4472 | return 0; |
4473 | } | |
4474 | #endif | |
4475 | ||
4476 | static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); | |
4477 | ||
c5aff182 TP |
4478 | static const struct of_device_id mvneta_match[] = { |
4479 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 4480 | { .compatible = "marvell,armada-xp-neta" }, |
2636ac3c | 4481 | { .compatible = "marvell,armada-3700-neta" }, |
c5aff182 TP |
4482 | { } |
4483 | }; | |
4484 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
4485 | ||
4486 | static struct platform_driver mvneta_driver = { | |
4487 | .probe = mvneta_probe, | |
03ce758e | 4488 | .remove = mvneta_remove, |
c5aff182 TP |
4489 | .driver = { |
4490 | .name = MVNETA_DRIVER_NAME, | |
4491 | .of_match_table = mvneta_match, | |
9768b45c | 4492 | .pm = &mvneta_pm_ops, |
c5aff182 TP |
4493 | }, |
4494 | }; | |
4495 | ||
84a3f4db SAS |
4496 | static int __init mvneta_driver_init(void) |
4497 | { | |
4498 | int ret; | |
4499 | ||
4500 | ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", | |
4501 | mvneta_cpu_online, | |
4502 | mvneta_cpu_down_prepare); | |
4503 | if (ret < 0) | |
4504 | goto out; | |
4505 | online_hpstate = ret; | |
4506 | ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", | |
4507 | NULL, mvneta_cpu_dead); | |
4508 | if (ret) | |
4509 | goto err_dead; | |
4510 | ||
4511 | ret = platform_driver_register(&mvneta_driver); | |
4512 | if (ret) | |
4513 | goto err; | |
4514 | return 0; | |
4515 | ||
4516 | err: | |
4517 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
4518 | err_dead: | |
4519 | cpuhp_remove_multi_state(online_hpstate); | |
4520 | out: | |
4521 | return ret; | |
4522 | } | |
4523 | module_init(mvneta_driver_init); | |
4524 | ||
4525 | static void __exit mvneta_driver_exit(void) | |
4526 | { | |
4527 | platform_driver_unregister(&mvneta_driver); | |
4528 | cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); | |
4529 | cpuhp_remove_multi_state(online_hpstate); | |
4530 | } | |
4531 | module_exit(mvneta_driver_exit); | |
c5aff182 TP |
4532 | |
4533 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
4534 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
4535 | MODULE_LICENSE("GPL"); | |
4536 | ||
4537 | module_param(rxq_number, int, S_IRUGO); | |
4538 | module_param(txq_number, int, S_IRUGO); | |
4539 | ||
4540 | module_param(rxq_def, int, S_IRUGO); | |
f19fadfc | 4541 | module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); |