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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
c5aff182 TP |
15 | #include <linux/netdevice.h> |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/skbuff.h> | |
19 | #include <linux/inetdevice.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <net/ip.h> | |
24 | #include <net/ipv6.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_mdio.h> | |
28 | #include <linux/of_net.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/phy.h> | |
189dd626 | 31 | #include <linux/clk.h> |
c5aff182 TP |
32 | |
33 | /* Registers */ | |
34 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
35 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) | |
36 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) | |
37 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
38 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
39 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
40 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
41 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
42 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
43 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
44 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
45 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
46 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
47 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
48 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
49 | #define MVNETA_PORT_RX_RESET 0x1cc0 | |
50 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
51 | #define MVNETA_PHY_ADDR 0x2000 | |
52 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
53 | #define MVNETA_MBUS_RETRY 0x2010 | |
54 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
55 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
56 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
57 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
58 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
59 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
60 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
61 | #define MVNETA_PORT_CONFIG 0x2400 | |
62 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
63 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
64 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
65 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
66 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
67 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
68 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
69 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
70 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
71 | MVNETA_DEF_RXQ_ARP(q) | \ | |
72 | MVNETA_DEF_RXQ_TCP(q) | \ | |
73 | MVNETA_DEF_RXQ_UDP(q) | \ | |
74 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
75 | MVNETA_TX_UNSET_ERR_SUM | \ | |
76 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
77 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
78 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
79 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
80 | #define MVNETA_SDMA_CONFIG 0x241c | |
81 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
82 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
83 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
84 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 85 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
86 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
87 | #define MVNETA_PORT_STATUS 0x2444 | |
88 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
89 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
90 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
5445eaf3 AP |
91 | #define MVNETA_SGMII_SERDES_CFG 0x24A0 |
92 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 | |
c5aff182 TP |
93 | #define MVNETA_TYPE_PRIO 0x24bc |
94 | #define MVNETA_FORCE_UNI BIT(21) | |
95 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
96 | #define MVNETA_TXQ_CMD 0x2448 | |
97 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
98 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
99 | #define MVNETA_ACC_MODE 0x2500 | |
100 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) | |
101 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
102 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
103 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) | |
40ba35e7 | 104 | |
105 | /* Exception Interrupt Port/Queue Cause register */ | |
106 | ||
c5aff182 | 107 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 108 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 109 | |
110 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
111 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
112 | * bits 16..23 = RXQ FREE, one bit per queue. | |
113 | * bit 29 = OLD_REG_SUM, see old reg ? | |
114 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
115 | * bit 31 = MISC_SUM, one bit for 4 ports | |
116 | */ | |
117 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
118 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
119 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
120 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
121 | ||
c5aff182 TP |
122 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
123 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 124 | |
125 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
126 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
127 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 128 | |
129 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
130 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
131 | #define MVNETA_CAUSE_PTP BIT(4) | |
132 | ||
133 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
134 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
135 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
136 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
137 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
138 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
139 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
140 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
141 | ||
142 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
143 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
144 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
145 | ||
146 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
147 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
148 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
149 | ||
c5aff182 TP |
150 | #define MVNETA_INTR_ENABLE 0x25b8 |
151 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
40ba35e7 | 152 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF |
153 | ||
c5aff182 TP |
154 | #define MVNETA_RXQ_CMD 0x2680 |
155 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
156 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
157 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
158 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
159 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
160 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
161 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
162 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
163 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
164 | #define MVNETA_GMAC2_PSC_ENABLE BIT(3) | |
165 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) | |
166 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
167 | #define MVNETA_GMAC_STATUS 0x2c10 | |
168 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
169 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
170 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
171 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
172 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
173 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
174 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
175 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
176 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
177 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
178 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
179 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) | |
180 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 181 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
c5aff182 | 182 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 183 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
c5aff182 TP |
184 | #define MVNETA_MIB_COUNTERS_BASE 0x3080 |
185 | #define MVNETA_MIB_LATE_COLLISION 0x7c | |
186 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
187 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
188 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
189 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
190 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
191 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
192 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
193 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
194 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
195 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) | |
196 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
197 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
198 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
199 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
200 | #define MVNETA_TX_MTU 0x3e0c | |
201 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
202 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
203 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
204 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
205 | ||
206 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff | |
207 | ||
208 | /* Descriptor ring Macros */ | |
209 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
210 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
211 | ||
212 | /* Various constants */ | |
213 | ||
214 | /* Coalescing */ | |
215 | #define MVNETA_TXDONE_COAL_PKTS 16 | |
216 | #define MVNETA_RX_COAL_PKTS 32 | |
217 | #define MVNETA_RX_COAL_USEC 100 | |
218 | ||
c5aff182 TP |
219 | /* Napi polling weight */ |
220 | #define MVNETA_RX_POLL_WEIGHT 64 | |
221 | ||
6a20c175 | 222 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
223 | * by Marvell switches when a specific hardware mode is enabled (not |
224 | * supported by this driver) or is filled automatically by zeroes on | |
225 | * the RX side. Those two bytes being at the front of the Ethernet | |
226 | * header, they allow to have the IP header aligned on a 4 bytes | |
227 | * boundary automatically: the hardware skips those two bytes on its | |
228 | * own. | |
229 | */ | |
230 | #define MVNETA_MH_SIZE 2 | |
231 | ||
232 | #define MVNETA_VLAN_TAG_LEN 4 | |
233 | ||
234 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 | |
235 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 | |
236 | #define MVNETA_ACC_MODE_EXT 1 | |
237 | ||
238 | /* Timeout constants */ | |
239 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
240 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
241 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
242 | ||
243 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
244 | ||
245 | /* Max number of Rx descriptors */ | |
246 | #define MVNETA_MAX_RXD 128 | |
247 | ||
248 | /* Max number of Tx descriptors */ | |
249 | #define MVNETA_MAX_TXD 532 | |
250 | ||
251 | /* descriptor aligned size */ | |
252 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
253 | ||
254 | #define MVNETA_RX_PKT_SIZE(mtu) \ | |
255 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
256 | ETH_HLEN + ETH_FCS_LEN, \ | |
257 | MVNETA_CPU_D_CACHE_LINE_SIZE) | |
258 | ||
259 | #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) | |
260 | ||
74c41b04 | 261 | struct mvneta_pcpu_stats { |
c5aff182 | 262 | struct u64_stats_sync syncp; |
74c41b04 | 263 | u64 rx_packets; |
264 | u64 rx_bytes; | |
265 | u64 tx_packets; | |
266 | u64 tx_bytes; | |
c5aff182 TP |
267 | }; |
268 | ||
269 | struct mvneta_port { | |
270 | int pkt_size; | |
8ec2cd48 | 271 | unsigned int frag_size; |
c5aff182 TP |
272 | void __iomem *base; |
273 | struct mvneta_rx_queue *rxqs; | |
274 | struct mvneta_tx_queue *txqs; | |
c5aff182 TP |
275 | struct net_device *dev; |
276 | ||
277 | u32 cause_rx_tx; | |
278 | struct napi_struct napi; | |
279 | ||
c5aff182 TP |
280 | /* Napi weight */ |
281 | int weight; | |
282 | ||
283 | /* Core clock */ | |
189dd626 | 284 | struct clk *clk; |
c5aff182 TP |
285 | u8 mcast_count[256]; |
286 | u16 tx_ring_size; | |
287 | u16 rx_ring_size; | |
74c41b04 | 288 | struct mvneta_pcpu_stats *stats; |
c5aff182 TP |
289 | |
290 | struct mii_bus *mii_bus; | |
291 | struct phy_device *phy_dev; | |
292 | phy_interface_t phy_interface; | |
293 | struct device_node *phy_node; | |
294 | unsigned int link; | |
295 | unsigned int duplex; | |
296 | unsigned int speed; | |
297 | }; | |
298 | ||
6a20c175 | 299 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
300 | * layout of the transmit and reception DMA descriptors, and their |
301 | * layout is therefore defined by the hardware design | |
302 | */ | |
6083ed44 | 303 | |
c5aff182 TP |
304 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
305 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
306 | #define MVNETA_TX_L4_UDP BIT(16) | |
307 | #define MVNETA_TX_L3_IP6 BIT(17) | |
308 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
309 | #define MVNETA_TXD_Z_PAD BIT(19) | |
310 | #define MVNETA_TXD_L_DESC BIT(20) | |
311 | #define MVNETA_TXD_F_DESC BIT(21) | |
312 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
313 | MVNETA_TXD_L_DESC | \ | |
314 | MVNETA_TXD_F_DESC) | |
315 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
316 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
317 | ||
c5aff182 TP |
318 | #define MVNETA_RXD_ERR_CRC 0x0 |
319 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) | |
320 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
321 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
322 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
323 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
324 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
325 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
326 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
327 | ||
9ad8fef6 | 328 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
329 | struct mvneta_tx_desc { |
330 | u32 command; /* Options used by HW for packet transmitting.*/ | |
331 | u16 reserverd1; /* csum_l4 (for future use) */ | |
332 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
333 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
334 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
335 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
336 | }; | |
337 | ||
338 | struct mvneta_rx_desc { | |
339 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
340 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
341 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 342 | |
c5aff182 TP |
343 | u32 buf_phys_addr; /* Physical address of the buffer */ |
344 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 345 | |
c5aff182 TP |
346 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
347 | u16 reserved3; /* prefetch_cmd, for future use */ | |
348 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 349 | |
c5aff182 TP |
350 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
351 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
352 | }; | |
9ad8fef6 TP |
353 | #else |
354 | struct mvneta_tx_desc { | |
355 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
356 | u16 reserverd1; /* csum_l4 (for future use) */ | |
357 | u32 command; /* Options used by HW for packet transmitting.*/ | |
358 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
359 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
360 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
361 | }; | |
362 | ||
363 | struct mvneta_rx_desc { | |
364 | u16 data_size; /* Size of received packet in bytes */ | |
365 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
366 | u32 status; /* Info about received packet */ | |
367 | ||
368 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
369 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
370 | ||
371 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
372 | u16 reserved3; /* prefetch_cmd, for future use */ | |
373 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
374 | ||
375 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
376 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
377 | }; | |
378 | #endif | |
c5aff182 TP |
379 | |
380 | struct mvneta_tx_queue { | |
381 | /* Number of this TX queue, in the range 0-7 */ | |
382 | u8 id; | |
383 | ||
384 | /* Number of TX DMA descriptors in the descriptor ring */ | |
385 | int size; | |
386 | ||
387 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
388 | * descriptor ring |
389 | */ | |
c5aff182 TP |
390 | int count; |
391 | ||
392 | /* Array of transmitted skb */ | |
393 | struct sk_buff **tx_skb; | |
394 | ||
395 | /* Index of last TX DMA descriptor that was inserted */ | |
396 | int txq_put_index; | |
397 | ||
398 | /* Index of the TX DMA descriptor to be cleaned up */ | |
399 | int txq_get_index; | |
400 | ||
401 | u32 done_pkts_coal; | |
402 | ||
403 | /* Virtual address of the TX DMA descriptors array */ | |
404 | struct mvneta_tx_desc *descs; | |
405 | ||
406 | /* DMA address of the TX DMA descriptors array */ | |
407 | dma_addr_t descs_phys; | |
408 | ||
409 | /* Index of the last TX DMA descriptor */ | |
410 | int last_desc; | |
411 | ||
412 | /* Index of the next TX DMA descriptor to process */ | |
413 | int next_desc_to_proc; | |
414 | }; | |
415 | ||
416 | struct mvneta_rx_queue { | |
417 | /* rx queue number, in the range 0-7 */ | |
418 | u8 id; | |
419 | ||
420 | /* num of rx descriptors in the rx descriptor ring */ | |
421 | int size; | |
422 | ||
423 | /* counter of times when mvneta_refill() failed */ | |
424 | int missed; | |
425 | ||
426 | u32 pkts_coal; | |
427 | u32 time_coal; | |
428 | ||
429 | /* Virtual address of the RX DMA descriptors array */ | |
430 | struct mvneta_rx_desc *descs; | |
431 | ||
432 | /* DMA address of the RX DMA descriptors array */ | |
433 | dma_addr_t descs_phys; | |
434 | ||
435 | /* Index of the last RX DMA descriptor */ | |
436 | int last_desc; | |
437 | ||
438 | /* Index of the next RX DMA descriptor to process */ | |
439 | int next_desc_to_proc; | |
440 | }; | |
441 | ||
442 | static int rxq_number = 8; | |
443 | static int txq_number = 8; | |
444 | ||
445 | static int rxq_def; | |
c5aff182 TP |
446 | |
447 | #define MVNETA_DRIVER_NAME "mvneta" | |
448 | #define MVNETA_DRIVER_VERSION "1.0" | |
449 | ||
450 | /* Utility/helper methods */ | |
451 | ||
452 | /* Write helper method */ | |
453 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
454 | { | |
455 | writel(data, pp->base + offset); | |
456 | } | |
457 | ||
458 | /* Read helper method */ | |
459 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
460 | { | |
461 | return readl(pp->base + offset); | |
462 | } | |
463 | ||
464 | /* Increment txq get counter */ | |
465 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
466 | { | |
467 | txq->txq_get_index++; | |
468 | if (txq->txq_get_index == txq->size) | |
469 | txq->txq_get_index = 0; | |
470 | } | |
471 | ||
472 | /* Increment txq put counter */ | |
473 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
474 | { | |
475 | txq->txq_put_index++; | |
476 | if (txq->txq_put_index == txq->size) | |
477 | txq->txq_put_index = 0; | |
478 | } | |
479 | ||
480 | ||
481 | /* Clear all MIB counters */ | |
482 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
483 | { | |
484 | int i; | |
485 | u32 dummy; | |
486 | ||
487 | /* Perform dummy reads from MIB counters */ | |
488 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
489 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
490 | } | |
491 | ||
492 | /* Get System Network Statistics */ | |
493 | struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, | |
494 | struct rtnl_link_stats64 *stats) | |
495 | { | |
496 | struct mvneta_port *pp = netdev_priv(dev); | |
497 | unsigned int start; | |
74c41b04 | 498 | int cpu; |
c5aff182 | 499 | |
74c41b04 | 500 | for_each_possible_cpu(cpu) { |
501 | struct mvneta_pcpu_stats *cpu_stats; | |
502 | u64 rx_packets; | |
503 | u64 rx_bytes; | |
504 | u64 tx_packets; | |
505 | u64 tx_bytes; | |
c5aff182 | 506 | |
74c41b04 | 507 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
508 | do { | |
509 | start = u64_stats_fetch_begin_bh(&cpu_stats->syncp); | |
510 | rx_packets = cpu_stats->rx_packets; | |
511 | rx_bytes = cpu_stats->rx_bytes; | |
512 | tx_packets = cpu_stats->tx_packets; | |
513 | tx_bytes = cpu_stats->tx_bytes; | |
514 | } while (u64_stats_fetch_retry_bh(&cpu_stats->syncp, start)); | |
c5aff182 | 515 | |
74c41b04 | 516 | stats->rx_packets += rx_packets; |
517 | stats->rx_bytes += rx_bytes; | |
518 | stats->tx_packets += tx_packets; | |
519 | stats->tx_bytes += tx_bytes; | |
520 | } | |
c5aff182 TP |
521 | |
522 | stats->rx_errors = dev->stats.rx_errors; | |
523 | stats->rx_dropped = dev->stats.rx_dropped; | |
524 | ||
525 | stats->tx_dropped = dev->stats.tx_dropped; | |
526 | ||
527 | return stats; | |
528 | } | |
529 | ||
530 | /* Rx descriptors helper methods */ | |
531 | ||
5428213c | 532 | /* Checks whether the RX descriptor having this status is both the first |
533 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
534 | * received through a single RX descriptor, so not having each RX |
535 | * descriptor with its first and last bits set is an error | |
536 | */ | |
5428213c | 537 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 538 | { |
5428213c | 539 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
540 | MVNETA_RXD_FIRST_LAST_DESC; |
541 | } | |
542 | ||
543 | /* Add number of descriptors ready to receive new packets */ | |
544 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
545 | struct mvneta_rx_queue *rxq, | |
546 | int ndescs) | |
547 | { | |
548 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
549 | * be added at once |
550 | */ | |
c5aff182 TP |
551 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
552 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
553 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
554 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
555 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
556 | } | |
557 | ||
558 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
559 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
560 | } | |
561 | ||
562 | /* Get number of RX descriptors occupied by received packets */ | |
563 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
564 | struct mvneta_rx_queue *rxq) | |
565 | { | |
566 | u32 val; | |
567 | ||
568 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
569 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
570 | } | |
571 | ||
6a20c175 | 572 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
573 | * from mvneta_rxq_drop_pkts(). |
574 | */ | |
575 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
576 | struct mvneta_rx_queue *rxq, | |
577 | int rx_done, int rx_filled) | |
578 | { | |
579 | u32 val; | |
580 | ||
581 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
582 | val = rx_done | | |
583 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
584 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
585 | return; | |
586 | } | |
587 | ||
588 | /* Only 255 descriptors can be added at once */ | |
589 | while ((rx_done > 0) || (rx_filled > 0)) { | |
590 | if (rx_done <= 0xff) { | |
591 | val = rx_done; | |
592 | rx_done = 0; | |
593 | } else { | |
594 | val = 0xff; | |
595 | rx_done -= 0xff; | |
596 | } | |
597 | if (rx_filled <= 0xff) { | |
598 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
599 | rx_filled = 0; | |
600 | } else { | |
601 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
602 | rx_filled -= 0xff; | |
603 | } | |
604 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
605 | } | |
606 | } | |
607 | ||
608 | /* Get pointer to next RX descriptor to be processed by SW */ | |
609 | static struct mvneta_rx_desc * | |
610 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
611 | { | |
612 | int rx_desc = rxq->next_desc_to_proc; | |
613 | ||
614 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 615 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
616 | return rxq->descs + rx_desc; |
617 | } | |
618 | ||
619 | /* Change maximum receive size of the port. */ | |
620 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
621 | { | |
622 | u32 val; | |
623 | ||
624 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
625 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
626 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
627 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
628 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
629 | } | |
630 | ||
631 | ||
632 | /* Set rx queue offset */ | |
633 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
634 | struct mvneta_rx_queue *rxq, | |
635 | int offset) | |
636 | { | |
637 | u32 val; | |
638 | ||
639 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
640 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
641 | ||
642 | /* Offset is in */ | |
643 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
644 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
645 | } | |
646 | ||
647 | ||
648 | /* Tx descriptors helper methods */ | |
649 | ||
650 | /* Update HW with number of TX descriptors to be sent */ | |
651 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
652 | struct mvneta_tx_queue *txq, | |
653 | int pend_desc) | |
654 | { | |
655 | u32 val; | |
656 | ||
657 | /* Only 255 descriptors can be added at once ; Assume caller | |
6a20c175 TP |
658 | * process TX desriptors in quanta less than 256 |
659 | */ | |
c5aff182 TP |
660 | val = pend_desc; |
661 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
662 | } | |
663 | ||
664 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
665 | static struct mvneta_tx_desc * | |
666 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
667 | { | |
668 | int tx_desc = txq->next_desc_to_proc; | |
669 | ||
670 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
671 | return txq->descs + tx_desc; | |
672 | } | |
673 | ||
674 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
675 | * mapping failures in the TX path. |
676 | */ | |
c5aff182 TP |
677 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
678 | { | |
679 | if (txq->next_desc_to_proc == 0) | |
680 | txq->next_desc_to_proc = txq->last_desc - 1; | |
681 | else | |
682 | txq->next_desc_to_proc--; | |
683 | } | |
684 | ||
685 | /* Set rxq buf size */ | |
686 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
687 | struct mvneta_rx_queue *rxq, | |
688 | int buf_size) | |
689 | { | |
690 | u32 val; | |
691 | ||
692 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
693 | ||
694 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
695 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
696 | ||
697 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
698 | } | |
699 | ||
700 | /* Disable buffer management (BM) */ | |
701 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
702 | struct mvneta_rx_queue *rxq) | |
703 | { | |
704 | u32 val; | |
705 | ||
706 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
707 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
708 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
709 | } | |
710 | ||
711 | ||
712 | ||
713 | /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */ | |
03ce758e | 714 | static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable) |
c5aff182 TP |
715 | { |
716 | u32 val; | |
717 | ||
718 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
719 | ||
720 | if (enable) | |
721 | val |= MVNETA_GMAC2_PORT_RGMII; | |
722 | else | |
723 | val &= ~MVNETA_GMAC2_PORT_RGMII; | |
724 | ||
725 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
726 | } | |
727 | ||
728 | /* Config SGMII port */ | |
03ce758e | 729 | static void mvneta_port_sgmii_config(struct mvneta_port *pp) |
c5aff182 TP |
730 | { |
731 | u32 val; | |
732 | ||
733 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
734 | val |= MVNETA_GMAC2_PSC_ENABLE; | |
735 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
5445eaf3 AP |
736 | |
737 | mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
c5aff182 TP |
738 | } |
739 | ||
740 | /* Start the Ethernet port RX and TX activity */ | |
741 | static void mvneta_port_up(struct mvneta_port *pp) | |
742 | { | |
743 | int queue; | |
744 | u32 q_map; | |
745 | ||
746 | /* Enable all initialized TXs. */ | |
747 | mvneta_mib_counters_clear(pp); | |
748 | q_map = 0; | |
749 | for (queue = 0; queue < txq_number; queue++) { | |
750 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
751 | if (txq->descs != NULL) | |
752 | q_map |= (1 << queue); | |
753 | } | |
754 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
755 | ||
756 | /* Enable all initialized RXQs. */ | |
757 | q_map = 0; | |
758 | for (queue = 0; queue < rxq_number; queue++) { | |
759 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
760 | if (rxq->descs != NULL) | |
761 | q_map |= (1 << queue); | |
762 | } | |
763 | ||
764 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
765 | } | |
766 | ||
767 | /* Stop the Ethernet port activity */ | |
768 | static void mvneta_port_down(struct mvneta_port *pp) | |
769 | { | |
770 | u32 val; | |
771 | int count; | |
772 | ||
773 | /* Stop Rx port activity. Check port Rx activity. */ | |
774 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
775 | ||
776 | /* Issue stop command for active channels only */ | |
777 | if (val != 0) | |
778 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
779 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
780 | ||
781 | /* Wait for all Rx activity to terminate. */ | |
782 | count = 0; | |
783 | do { | |
784 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
785 | netdev_warn(pp->dev, | |
786 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", | |
787 | val); | |
788 | break; | |
789 | } | |
790 | mdelay(1); | |
791 | ||
792 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
793 | } while (val & 0xff); | |
794 | ||
795 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
796 | * command for active channels only |
797 | */ | |
c5aff182 TP |
798 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
799 | ||
800 | if (val != 0) | |
801 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
802 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
803 | ||
804 | /* Wait for all Tx activity to terminate. */ | |
805 | count = 0; | |
806 | do { | |
807 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
808 | netdev_warn(pp->dev, | |
809 | "TIMEOUT for TX stopped status=0x%08x\n", | |
810 | val); | |
811 | break; | |
812 | } | |
813 | mdelay(1); | |
814 | ||
815 | /* Check TX Command reg that all Txqs are stopped */ | |
816 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
817 | ||
818 | } while (val & 0xff); | |
819 | ||
820 | /* Double check to verify that TX FIFO is empty */ | |
821 | count = 0; | |
822 | do { | |
823 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
824 | netdev_warn(pp->dev, | |
825 | "TX FIFO empty timeout status=0x08%x\n", | |
826 | val); | |
827 | break; | |
828 | } | |
829 | mdelay(1); | |
830 | ||
831 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
832 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
833 | (val & MVNETA_TX_IN_PRGRS)); | |
834 | ||
835 | udelay(200); | |
836 | } | |
837 | ||
838 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
839 | static void mvneta_port_enable(struct mvneta_port *pp) | |
840 | { | |
841 | u32 val; | |
842 | ||
843 | /* Enable port */ | |
844 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
845 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
846 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
847 | } | |
848 | ||
849 | /* Disable the port and wait for about 200 usec before retuning */ | |
850 | static void mvneta_port_disable(struct mvneta_port *pp) | |
851 | { | |
852 | u32 val; | |
853 | ||
854 | /* Reset the Enable bit in the Serial Control Register */ | |
855 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
856 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
857 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
858 | ||
859 | udelay(200); | |
860 | } | |
861 | ||
862 | /* Multicast tables methods */ | |
863 | ||
864 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
865 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
866 | { | |
867 | int offset; | |
868 | u32 val; | |
869 | ||
870 | if (queue == -1) { | |
871 | val = 0; | |
872 | } else { | |
873 | val = 0x1 | (queue << 1); | |
874 | val |= (val << 24) | (val << 16) | (val << 8); | |
875 | } | |
876 | ||
877 | for (offset = 0; offset <= 0xc; offset += 4) | |
878 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
879 | } | |
880 | ||
881 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
882 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
883 | { | |
884 | int offset; | |
885 | u32 val; | |
886 | ||
887 | if (queue == -1) { | |
888 | val = 0; | |
889 | } else { | |
890 | val = 0x1 | (queue << 1); | |
891 | val |= (val << 24) | (val << 16) | (val << 8); | |
892 | } | |
893 | ||
894 | for (offset = 0; offset <= 0xfc; offset += 4) | |
895 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
896 | ||
897 | } | |
898 | ||
899 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
900 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
901 | { | |
902 | int offset; | |
903 | u32 val; | |
904 | ||
905 | if (queue == -1) { | |
906 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
907 | val = 0; | |
908 | } else { | |
909 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
910 | val = 0x1 | (queue << 1); | |
911 | val |= (val << 24) | (val << 16) | (val << 8); | |
912 | } | |
913 | ||
914 | for (offset = 0; offset <= 0xfc; offset += 4) | |
915 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
916 | } | |
917 | ||
918 | /* This method sets defaults to the NETA port: | |
919 | * Clears interrupt Cause and Mask registers. | |
920 | * Clears all MAC tables. | |
921 | * Sets defaults to all registers. | |
922 | * Resets RX and TX descriptor rings. | |
923 | * Resets PHY. | |
924 | * This method can be called after mvneta_port_down() to return the port | |
925 | * settings to defaults. | |
926 | */ | |
927 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
928 | { | |
929 | int cpu; | |
930 | int queue; | |
931 | u32 val; | |
932 | ||
933 | /* Clear all Cause registers */ | |
934 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
935 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
936 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
937 | ||
938 | /* Mask all interrupts */ | |
939 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
940 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
941 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
942 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); | |
943 | ||
944 | /* Enable MBUS Retry bit16 */ | |
945 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
946 | ||
947 | /* Set CPU queue access map - all CPUs have access to all RX | |
6a20c175 TP |
948 | * queues and to all TX queues |
949 | */ | |
c5aff182 TP |
950 | for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) |
951 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), | |
952 | (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | | |
953 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); | |
954 | ||
955 | /* Reset RX and TX DMAs */ | |
956 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
957 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
958 | ||
959 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
960 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
961 | for (queue = 0; queue < txq_number; queue++) { | |
962 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
963 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
964 | } | |
965 | ||
966 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
967 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
968 | ||
969 | /* Set Port Acceleration Mode */ | |
970 | val = MVNETA_ACC_MODE_EXT; | |
971 | mvreg_write(pp, MVNETA_ACC_MODE, val); | |
972 | ||
973 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
974 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); | |
975 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
976 | ||
977 | val = 0; | |
978 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
979 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
980 | ||
981 | /* Build PORT_SDMA_CONFIG_REG */ | |
982 | val = 0; | |
983 | ||
984 | /* Default burst size */ | |
985 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
986 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 987 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 988 | |
9ad8fef6 TP |
989 | #if defined(__BIG_ENDIAN) |
990 | val |= MVNETA_DESC_SWAP; | |
991 | #endif | |
c5aff182 TP |
992 | |
993 | /* Assign port SDMA configuration */ | |
994 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
995 | ||
71408602 TP |
996 | /* Disable PHY polling in hardware, since we're using the |
997 | * kernel phylib to do this. | |
998 | */ | |
999 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1000 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1001 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1002 | ||
c5aff182 TP |
1003 | mvneta_set_ucast_table(pp, -1); |
1004 | mvneta_set_special_mcast_table(pp, -1); | |
1005 | mvneta_set_other_mcast_table(pp, -1); | |
1006 | ||
1007 | /* Set port interrupt enable register - default enable all */ | |
1008 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1009 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1010 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
1011 | } | |
1012 | ||
1013 | /* Set max sizes for tx queues */ | |
1014 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1015 | ||
1016 | { | |
1017 | u32 val, size, mtu; | |
1018 | int queue; | |
1019 | ||
1020 | mtu = max_tx_size * 8; | |
1021 | if (mtu > MVNETA_TX_MTU_MAX) | |
1022 | mtu = MVNETA_TX_MTU_MAX; | |
1023 | ||
1024 | /* Set MTU */ | |
1025 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1026 | val &= ~MVNETA_TX_MTU_MAX; | |
1027 | val |= mtu; | |
1028 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1029 | ||
1030 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1031 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1032 | ||
1033 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1034 | if (size < mtu) { | |
1035 | size = mtu; | |
1036 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1037 | val |= size; | |
1038 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1039 | } | |
1040 | for (queue = 0; queue < txq_number; queue++) { | |
1041 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1042 | ||
1043 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1044 | if (size < mtu) { | |
1045 | size = mtu; | |
1046 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1047 | val |= size; | |
1048 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1049 | } | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | /* Set unicast address */ | |
1054 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1055 | int queue) | |
1056 | { | |
1057 | unsigned int unicast_reg; | |
1058 | unsigned int tbl_offset; | |
1059 | unsigned int reg_offset; | |
1060 | ||
1061 | /* Locate the Unicast table entry */ | |
1062 | last_nibble = (0xf & last_nibble); | |
1063 | ||
1064 | /* offset from unicast tbl base */ | |
1065 | tbl_offset = (last_nibble / 4) * 4; | |
1066 | ||
1067 | /* offset within the above reg */ | |
1068 | reg_offset = last_nibble % 4; | |
1069 | ||
1070 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1071 | ||
1072 | if (queue == -1) { | |
1073 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1074 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1075 | } else { | |
1076 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1077 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1078 | } | |
1079 | ||
1080 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1081 | } | |
1082 | ||
1083 | /* Set mac address */ | |
1084 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1085 | int queue) | |
1086 | { | |
1087 | unsigned int mac_h; | |
1088 | unsigned int mac_l; | |
1089 | ||
1090 | if (queue != -1) { | |
1091 | mac_l = (addr[4] << 8) | (addr[5]); | |
1092 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1093 | (addr[2] << 8) | (addr[3] << 0); | |
1094 | ||
1095 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1096 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1097 | } | |
1098 | ||
1099 | /* Accept frames of this address */ | |
1100 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1101 | } | |
1102 | ||
6a20c175 TP |
1103 | /* Set the number of packets that will be received before RX interrupt |
1104 | * will be generated by HW. | |
c5aff182 TP |
1105 | */ |
1106 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1107 | struct mvneta_rx_queue *rxq, u32 value) | |
1108 | { | |
1109 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1110 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
1111 | rxq->pkts_coal = value; | |
1112 | } | |
1113 | ||
6a20c175 TP |
1114 | /* Set the time delay in usec before RX interrupt will be generated by |
1115 | * HW. | |
c5aff182 TP |
1116 | */ |
1117 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1118 | struct mvneta_rx_queue *rxq, u32 value) | |
1119 | { | |
189dd626 TP |
1120 | u32 val; |
1121 | unsigned long clk_rate; | |
1122 | ||
1123 | clk_rate = clk_get_rate(pp->clk); | |
1124 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1125 | |
1126 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
1127 | rxq->time_coal = value; | |
1128 | } | |
1129 | ||
1130 | /* Set threshold for TX_DONE pkts coalescing */ | |
1131 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1132 | struct mvneta_tx_queue *txq, u32 value) | |
1133 | { | |
1134 | u32 val; | |
1135 | ||
1136 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1137 | ||
1138 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1139 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1140 | ||
1141 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
1142 | ||
1143 | txq->done_pkts_coal = value; | |
1144 | } | |
1145 | ||
c5aff182 TP |
1146 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1147 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
1148 | u32 phys_addr, u32 cookie) | |
1149 | { | |
1150 | rx_desc->buf_cookie = cookie; | |
1151 | rx_desc->buf_phys_addr = phys_addr; | |
1152 | } | |
1153 | ||
1154 | /* Decrement sent descriptors counter */ | |
1155 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1156 | struct mvneta_tx_queue *txq, | |
1157 | int sent_desc) | |
1158 | { | |
1159 | u32 val; | |
1160 | ||
1161 | /* Only 255 TX descriptors can be updated at once */ | |
1162 | while (sent_desc > 0xff) { | |
1163 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1164 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1165 | sent_desc = sent_desc - 0xff; | |
1166 | } | |
1167 | ||
1168 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1169 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1170 | } | |
1171 | ||
1172 | /* Get number of TX descriptors already sent by HW */ | |
1173 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1174 | struct mvneta_tx_queue *txq) | |
1175 | { | |
1176 | u32 val; | |
1177 | int sent_desc; | |
1178 | ||
1179 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1180 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1181 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1182 | ||
1183 | return sent_desc; | |
1184 | } | |
1185 | ||
6a20c175 | 1186 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1187 | * The number of sent descriptors is returned. |
1188 | */ | |
1189 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1190 | struct mvneta_tx_queue *txq) | |
1191 | { | |
1192 | int sent_desc; | |
1193 | ||
1194 | /* Get number of sent descriptors */ | |
1195 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1196 | ||
1197 | /* Decrement sent descriptors counter */ | |
1198 | if (sent_desc) | |
1199 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1200 | ||
1201 | return sent_desc; | |
1202 | } | |
1203 | ||
1204 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1205 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1206 | int ip_hdr_len, int l4_proto) | |
1207 | { | |
1208 | u32 command; | |
1209 | ||
1210 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1211 | * G_L4_chk, L4_type; required only for checksum |
1212 | * calculation | |
1213 | */ | |
c5aff182 TP |
1214 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1215 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1216 | ||
1217 | if (l3_proto == swab16(ETH_P_IP)) | |
1218 | command |= MVNETA_TXD_IP_CSUM; | |
1219 | else | |
1220 | command |= MVNETA_TX_L3_IP6; | |
1221 | ||
1222 | if (l4_proto == IPPROTO_TCP) | |
1223 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1224 | else if (l4_proto == IPPROTO_UDP) | |
1225 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1226 | else | |
1227 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1228 | ||
1229 | return command; | |
1230 | } | |
1231 | ||
1232 | ||
1233 | /* Display more error info */ | |
1234 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1235 | struct mvneta_rx_desc *rx_desc) | |
1236 | { | |
1237 | u32 status = rx_desc->status; | |
1238 | ||
5428213c | 1239 | if (!mvneta_rxq_desc_is_first_last(status)) { |
c5aff182 TP |
1240 | netdev_err(pp->dev, |
1241 | "bad rx status %08x (buffer oversize), size=%d\n", | |
5428213c | 1242 | status, rx_desc->data_size); |
c5aff182 TP |
1243 | return; |
1244 | } | |
1245 | ||
1246 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
1247 | case MVNETA_RXD_ERR_CRC: | |
1248 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1249 | status, rx_desc->data_size); | |
1250 | break; | |
1251 | case MVNETA_RXD_ERR_OVERRUN: | |
1252 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1253 | status, rx_desc->data_size); | |
1254 | break; | |
1255 | case MVNETA_RXD_ERR_LEN: | |
1256 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1257 | status, rx_desc->data_size); | |
1258 | break; | |
1259 | case MVNETA_RXD_ERR_RESOURCE: | |
1260 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1261 | status, rx_desc->data_size); | |
1262 | break; | |
1263 | } | |
1264 | } | |
1265 | ||
5428213c | 1266 | /* Handle RX checksum offload based on the descriptor's status */ |
1267 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1268 | struct sk_buff *skb) |
1269 | { | |
5428213c | 1270 | if ((status & MVNETA_RXD_L3_IP4) && |
1271 | (status & MVNETA_RXD_L4_CSUM_OK)) { | |
c5aff182 TP |
1272 | skb->csum = 0; |
1273 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1274 | return; | |
1275 | } | |
1276 | ||
1277 | skb->ip_summed = CHECKSUM_NONE; | |
1278 | } | |
1279 | ||
6c498974 | 1280 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1281 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1282 | * valid queue for matching the first one found in <cause>. | |
1283 | */ | |
c5aff182 TP |
1284 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1285 | u32 cause) | |
1286 | { | |
1287 | int queue = fls(cause) - 1; | |
1288 | ||
6c498974 | 1289 | return &pp->txqs[queue]; |
c5aff182 TP |
1290 | } |
1291 | ||
1292 | /* Free tx queue skbuffs */ | |
1293 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
1294 | struct mvneta_tx_queue *txq, int num) | |
1295 | { | |
1296 | int i; | |
1297 | ||
1298 | for (i = 0; i < num; i++) { | |
1299 | struct mvneta_tx_desc *tx_desc = txq->descs + | |
1300 | txq->txq_get_index; | |
1301 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; | |
1302 | ||
1303 | mvneta_txq_inc_get(txq); | |
1304 | ||
1305 | if (!skb) | |
1306 | continue; | |
1307 | ||
1308 | dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr, | |
1309 | tx_desc->data_size, DMA_TO_DEVICE); | |
1310 | dev_kfree_skb_any(skb); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | /* Handle end of transmission */ | |
1315 | static int mvneta_txq_done(struct mvneta_port *pp, | |
1316 | struct mvneta_tx_queue *txq) | |
1317 | { | |
1318 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1319 | int tx_done; | |
1320 | ||
1321 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
1322 | if (tx_done == 0) | |
1323 | return tx_done; | |
1324 | mvneta_txq_bufs_free(pp, txq, tx_done); | |
1325 | ||
1326 | txq->count -= tx_done; | |
1327 | ||
1328 | if (netif_tx_queue_stopped(nq)) { | |
1329 | if (txq->size - txq->count >= MAX_SKB_FRAGS + 1) | |
1330 | netif_tx_wake_queue(nq); | |
1331 | } | |
1332 | ||
1333 | return tx_done; | |
1334 | } | |
1335 | ||
8ec2cd48 | 1336 | static void *mvneta_frag_alloc(const struct mvneta_port *pp) |
1337 | { | |
1338 | if (likely(pp->frag_size <= PAGE_SIZE)) | |
1339 | return netdev_alloc_frag(pp->frag_size); | |
1340 | else | |
1341 | return kmalloc(pp->frag_size, GFP_ATOMIC); | |
1342 | } | |
1343 | ||
1344 | static void mvneta_frag_free(const struct mvneta_port *pp, void *data) | |
1345 | { | |
1346 | if (likely(pp->frag_size <= PAGE_SIZE)) | |
1347 | put_page(virt_to_head_page(data)); | |
1348 | else | |
1349 | kfree(data); | |
1350 | } | |
1351 | ||
c5aff182 TP |
1352 | /* Refill processing */ |
1353 | static int mvneta_rx_refill(struct mvneta_port *pp, | |
1354 | struct mvneta_rx_desc *rx_desc) | |
1355 | ||
1356 | { | |
1357 | dma_addr_t phys_addr; | |
8ec2cd48 | 1358 | void *data; |
c5aff182 | 1359 | |
8ec2cd48 | 1360 | data = mvneta_frag_alloc(pp); |
1361 | if (!data) | |
c5aff182 TP |
1362 | return -ENOMEM; |
1363 | ||
8ec2cd48 | 1364 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
c5aff182 TP |
1365 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
1366 | DMA_FROM_DEVICE); | |
1367 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { | |
8ec2cd48 | 1368 | mvneta_frag_free(pp, data); |
c5aff182 TP |
1369 | return -ENOMEM; |
1370 | } | |
1371 | ||
8ec2cd48 | 1372 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); |
c5aff182 TP |
1373 | return 0; |
1374 | } | |
1375 | ||
1376 | /* Handle tx checksum */ | |
1377 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1378 | { | |
1379 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1380 | int ip_hdr_len = 0; | |
1381 | u8 l4_proto; | |
1382 | ||
1383 | if (skb->protocol == htons(ETH_P_IP)) { | |
1384 | struct iphdr *ip4h = ip_hdr(skb); | |
1385 | ||
1386 | /* Calculate IPv4 checksum and L4 checksum */ | |
1387 | ip_hdr_len = ip4h->ihl; | |
1388 | l4_proto = ip4h->protocol; | |
1389 | } else if (skb->protocol == htons(ETH_P_IPV6)) { | |
1390 | struct ipv6hdr *ip6h = ipv6_hdr(skb); | |
1391 | ||
1392 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1393 | if (skb_network_header_len(skb) > 0) | |
1394 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1395 | l4_proto = ip6h->nexthdr; | |
1396 | } else | |
1397 | return MVNETA_TX_L4_CSUM_NOT; | |
1398 | ||
1399 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
1400 | skb->protocol, ip_hdr_len, l4_proto); | |
1401 | } | |
1402 | ||
1403 | return MVNETA_TX_L4_CSUM_NOT; | |
1404 | } | |
1405 | ||
6a20c175 | 1406 | /* Returns rx queue pointer (find last set bit) according to causeRxTx |
c5aff182 TP |
1407 | * value |
1408 | */ | |
1409 | static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp, | |
1410 | u32 cause) | |
1411 | { | |
1412 | int queue = fls(cause >> 8) - 1; | |
1413 | ||
1414 | return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue]; | |
1415 | } | |
1416 | ||
1417 | /* Drop packets received by the RXQ and free buffers */ | |
1418 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1419 | struct mvneta_rx_queue *rxq) | |
1420 | { | |
1421 | int rx_done, i; | |
1422 | ||
1423 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1424 | for (i = 0; i < rxq->size; i++) { | |
1425 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
8ec2cd48 | 1426 | void *data = (void *)rx_desc->buf_cookie; |
c5aff182 | 1427 | |
8ec2cd48 | 1428 | mvneta_frag_free(pp, data); |
c5aff182 | 1429 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
a328f3a0 | 1430 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
c5aff182 TP |
1431 | } |
1432 | ||
1433 | if (rx_done) | |
1434 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1435 | } | |
1436 | ||
1437 | /* Main rx processing */ | |
1438 | static int mvneta_rx(struct mvneta_port *pp, int rx_todo, | |
1439 | struct mvneta_rx_queue *rxq) | |
1440 | { | |
1441 | struct net_device *dev = pp->dev; | |
1442 | int rx_done, rx_filled; | |
dc4277dd | 1443 | u32 rcvd_pkts = 0; |
1444 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
1445 | |
1446 | /* Get number of received packets */ | |
1447 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1448 | ||
1449 | if (rx_todo > rx_done) | |
1450 | rx_todo = rx_done; | |
1451 | ||
1452 | rx_done = 0; | |
1453 | rx_filled = 0; | |
1454 | ||
1455 | /* Fairness NAPI loop */ | |
1456 | while (rx_done < rx_todo) { | |
1457 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1458 | struct sk_buff *skb; | |
8ec2cd48 | 1459 | unsigned char *data; |
c5aff182 TP |
1460 | u32 rx_status; |
1461 | int rx_bytes, err; | |
1462 | ||
c5aff182 TP |
1463 | rx_done++; |
1464 | rx_filled++; | |
1465 | rx_status = rx_desc->status; | |
8ec2cd48 | 1466 | data = (unsigned char *)rx_desc->buf_cookie; |
c5aff182 | 1467 | |
5428213c | 1468 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
8ec2cd48 | 1469 | (rx_status & MVNETA_RXD_ERR_SUMMARY) || |
1470 | !(skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size))) { | |
c5aff182 TP |
1471 | dev->stats.rx_errors++; |
1472 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 1473 | /* leave the descriptor untouched */ |
c5aff182 TP |
1474 | continue; |
1475 | } | |
1476 | ||
1477 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, | |
a328f3a0 | 1478 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
c5aff182 TP |
1479 | |
1480 | rx_bytes = rx_desc->data_size - | |
1481 | (ETH_FCS_LEN + MVNETA_MH_SIZE); | |
dc4277dd | 1482 | rcvd_pkts++; |
1483 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
1484 | |
1485 | /* Linux processing */ | |
8ec2cd48 | 1486 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
1487 | skb_put(skb, rx_bytes); |
1488 | ||
1489 | skb->protocol = eth_type_trans(skb, dev); | |
1490 | ||
5428213c | 1491 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 TP |
1492 | |
1493 | napi_gro_receive(&pp->napi, skb); | |
1494 | ||
1495 | /* Refill processing */ | |
1496 | err = mvneta_rx_refill(pp, rx_desc); | |
1497 | if (err) { | |
1498 | netdev_err(pp->dev, "Linux processing - Can't refill\n"); | |
1499 | rxq->missed++; | |
1500 | rx_filled--; | |
1501 | } | |
1502 | } | |
1503 | ||
dc4277dd | 1504 | if (rcvd_pkts) { |
74c41b04 | 1505 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
1506 | ||
1507 | u64_stats_update_begin(&stats->syncp); | |
1508 | stats->rx_packets += rcvd_pkts; | |
1509 | stats->rx_bytes += rcvd_bytes; | |
1510 | u64_stats_update_end(&stats->syncp); | |
dc4277dd | 1511 | } |
1512 | ||
c5aff182 TP |
1513 | /* Update rxq management counters */ |
1514 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled); | |
1515 | ||
1516 | return rx_done; | |
1517 | } | |
1518 | ||
1519 | /* Handle tx fragmentation processing */ | |
1520 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
1521 | struct mvneta_tx_queue *txq) | |
1522 | { | |
1523 | struct mvneta_tx_desc *tx_desc; | |
1524 | int i; | |
1525 | ||
1526 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1527 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1528 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
1529 | ||
1530 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1531 | tx_desc->data_size = frag->size; | |
1532 | ||
1533 | tx_desc->buf_phys_addr = | |
1534 | dma_map_single(pp->dev->dev.parent, addr, | |
1535 | tx_desc->data_size, DMA_TO_DEVICE); | |
1536 | ||
1537 | if (dma_mapping_error(pp->dev->dev.parent, | |
1538 | tx_desc->buf_phys_addr)) { | |
1539 | mvneta_txq_desc_put(txq); | |
1540 | goto error; | |
1541 | } | |
1542 | ||
1543 | if (i == (skb_shinfo(skb)->nr_frags - 1)) { | |
1544 | /* Last descriptor */ | |
1545 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
1546 | ||
1547 | txq->tx_skb[txq->txq_put_index] = skb; | |
1548 | ||
1549 | mvneta_txq_inc_put(txq); | |
1550 | } else { | |
1551 | /* Descriptor in the middle: Not First, Not Last */ | |
1552 | tx_desc->command = 0; | |
1553 | ||
1554 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1555 | mvneta_txq_inc_put(txq); | |
1556 | } | |
1557 | } | |
1558 | ||
1559 | return 0; | |
1560 | ||
1561 | error: | |
1562 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
1563 | * this packet, as well as the corresponding DMA mappings |
1564 | */ | |
c5aff182 TP |
1565 | for (i = i - 1; i >= 0; i--) { |
1566 | tx_desc = txq->descs + i; | |
1567 | dma_unmap_single(pp->dev->dev.parent, | |
1568 | tx_desc->buf_phys_addr, | |
1569 | tx_desc->data_size, | |
1570 | DMA_TO_DEVICE); | |
1571 | mvneta_txq_desc_put(txq); | |
1572 | } | |
1573 | ||
1574 | return -ENOMEM; | |
1575 | } | |
1576 | ||
1577 | /* Main tx processing */ | |
1578 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) | |
1579 | { | |
1580 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
1581 | u16 txq_id = skb_get_queue_mapping(skb); |
1582 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
c5aff182 TP |
1583 | struct mvneta_tx_desc *tx_desc; |
1584 | struct netdev_queue *nq; | |
1585 | int frags = 0; | |
1586 | u32 tx_cmd; | |
1587 | ||
1588 | if (!netif_running(dev)) | |
1589 | goto out; | |
1590 | ||
1591 | frags = skb_shinfo(skb)->nr_frags + 1; | |
ee40a116 | 1592 | nq = netdev_get_tx_queue(dev, txq_id); |
c5aff182 TP |
1593 | |
1594 | /* Get a descriptor for the first part of the packet */ | |
1595 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1596 | ||
1597 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
1598 | ||
1599 | tx_desc->data_size = skb_headlen(skb); | |
1600 | ||
1601 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
1602 | tx_desc->data_size, | |
1603 | DMA_TO_DEVICE); | |
1604 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
1605 | tx_desc->buf_phys_addr))) { | |
1606 | mvneta_txq_desc_put(txq); | |
1607 | frags = 0; | |
1608 | goto out; | |
1609 | } | |
1610 | ||
1611 | if (frags == 1) { | |
1612 | /* First and Last descriptor */ | |
1613 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
1614 | tx_desc->command = tx_cmd; | |
1615 | txq->tx_skb[txq->txq_put_index] = skb; | |
1616 | mvneta_txq_inc_put(txq); | |
1617 | } else { | |
1618 | /* First but not Last */ | |
1619 | tx_cmd |= MVNETA_TXD_F_DESC; | |
1620 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1621 | mvneta_txq_inc_put(txq); | |
1622 | tx_desc->command = tx_cmd; | |
1623 | /* Continue with other skb fragments */ | |
1624 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
1625 | dma_unmap_single(dev->dev.parent, | |
1626 | tx_desc->buf_phys_addr, | |
1627 | tx_desc->data_size, | |
1628 | DMA_TO_DEVICE); | |
1629 | mvneta_txq_desc_put(txq); | |
1630 | frags = 0; | |
1631 | goto out; | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | txq->count += frags; | |
1636 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
1637 | ||
1638 | if (txq->size - txq->count < MAX_SKB_FRAGS + 1) | |
1639 | netif_tx_stop_queue(nq); | |
1640 | ||
1641 | out: | |
1642 | if (frags > 0) { | |
74c41b04 | 1643 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
c5aff182 | 1644 | |
74c41b04 | 1645 | u64_stats_update_begin(&stats->syncp); |
1646 | stats->tx_packets++; | |
1647 | stats->tx_bytes += skb->len; | |
1648 | u64_stats_update_end(&stats->syncp); | |
c5aff182 TP |
1649 | } else { |
1650 | dev->stats.tx_dropped++; | |
1651 | dev_kfree_skb_any(skb); | |
1652 | } | |
1653 | ||
c5aff182 TP |
1654 | return NETDEV_TX_OK; |
1655 | } | |
1656 | ||
1657 | ||
1658 | /* Free tx resources, when resetting a port */ | |
1659 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
1660 | struct mvneta_tx_queue *txq) | |
1661 | ||
1662 | { | |
1663 | int tx_done = txq->count; | |
1664 | ||
1665 | mvneta_txq_bufs_free(pp, txq, tx_done); | |
1666 | ||
1667 | /* reset txq */ | |
1668 | txq->count = 0; | |
1669 | txq->txq_put_index = 0; | |
1670 | txq->txq_get_index = 0; | |
1671 | } | |
1672 | ||
6c498974 | 1673 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
1674 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
1675 | */ | |
c5aff182 TP |
1676 | static u32 mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done, |
1677 | int *tx_todo) | |
1678 | { | |
1679 | struct mvneta_tx_queue *txq; | |
1680 | u32 tx_done = 0; | |
1681 | struct netdev_queue *nq; | |
1682 | ||
1683 | *tx_todo = 0; | |
6c498974 | 1684 | while (cause_tx_done) { |
c5aff182 | 1685 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
1686 | |
1687 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1688 | __netif_tx_lock(nq, smp_processor_id()); | |
1689 | ||
1690 | if (txq->count) { | |
1691 | tx_done += mvneta_txq_done(pp, txq); | |
1692 | *tx_todo += txq->count; | |
1693 | } | |
1694 | ||
1695 | __netif_tx_unlock(nq); | |
1696 | cause_tx_done &= ~((1 << txq->id)); | |
1697 | } | |
1698 | ||
1699 | return tx_done; | |
1700 | } | |
1701 | ||
6a20c175 | 1702 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
1703 | * according to hw spec, different than generic crc8 algorithm |
1704 | */ | |
1705 | static int mvneta_addr_crc(unsigned char *addr) | |
1706 | { | |
1707 | int crc = 0; | |
1708 | int i; | |
1709 | ||
1710 | for (i = 0; i < ETH_ALEN; i++) { | |
1711 | int j; | |
1712 | ||
1713 | crc = (crc ^ addr[i]) << 8; | |
1714 | for (j = 7; j >= 0; j--) { | |
1715 | if (crc & (0x100 << j)) | |
1716 | crc ^= 0x107 << j; | |
1717 | } | |
1718 | } | |
1719 | ||
1720 | return crc; | |
1721 | } | |
1722 | ||
1723 | /* This method controls the net device special MAC multicast support. | |
1724 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
1725 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
1726 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1727 | * Table entries in the DA-Filter table. This method set the Special | |
1728 | * Multicast Table appropriate entry. | |
1729 | */ | |
1730 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
1731 | unsigned char last_byte, | |
1732 | int queue) | |
1733 | { | |
1734 | unsigned int smc_table_reg; | |
1735 | unsigned int tbl_offset; | |
1736 | unsigned int reg_offset; | |
1737 | ||
1738 | /* Register offset from SMC table base */ | |
1739 | tbl_offset = (last_byte / 4); | |
1740 | /* Entry offset within the above reg */ | |
1741 | reg_offset = last_byte % 4; | |
1742 | ||
1743 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
1744 | + tbl_offset * 4)); | |
1745 | ||
1746 | if (queue == -1) | |
1747 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1748 | else { | |
1749 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1750 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1751 | } | |
1752 | ||
1753 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
1754 | smc_table_reg); | |
1755 | } | |
1756 | ||
1757 | /* This method controls the network device Other MAC multicast support. | |
1758 | * The Other Multicast Table is used for multicast of another type. | |
1759 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
1760 | * in the DA-Filter table. | |
1761 | * The method gets the CRC-8 value from the calling routine and | |
1762 | * sets the Other Multicast Table appropriate entry according to the | |
1763 | * specified CRC-8 . | |
1764 | */ | |
1765 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
1766 | unsigned char crc8, | |
1767 | int queue) | |
1768 | { | |
1769 | unsigned int omc_table_reg; | |
1770 | unsigned int tbl_offset; | |
1771 | unsigned int reg_offset; | |
1772 | ||
1773 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
1774 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
1775 | ||
1776 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
1777 | ||
1778 | if (queue == -1) { | |
1779 | /* Clear accepts frame bit at specified Other DA table entry */ | |
1780 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1781 | } else { | |
1782 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
1783 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1784 | } | |
1785 | ||
1786 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
1787 | } | |
1788 | ||
1789 | /* The network device supports multicast using two tables: | |
1790 | * 1) Special Multicast Table for MAC addresses of the form | |
1791 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
1792 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1793 | * Table entries in the DA-Filter table. | |
1794 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
1795 | * is used as an index to the Other Multicast Table entries in the | |
1796 | * DA-Filter table. | |
1797 | */ | |
1798 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
1799 | int queue) | |
1800 | { | |
1801 | unsigned char crc_result = 0; | |
1802 | ||
1803 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
1804 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | crc_result = mvneta_addr_crc(p_addr); | |
1809 | if (queue == -1) { | |
1810 | if (pp->mcast_count[crc_result] == 0) { | |
1811 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
1812 | crc_result); | |
1813 | return -EINVAL; | |
1814 | } | |
1815 | ||
1816 | pp->mcast_count[crc_result]--; | |
1817 | if (pp->mcast_count[crc_result] != 0) { | |
1818 | netdev_info(pp->dev, | |
1819 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
1820 | pp->mcast_count[crc_result], crc_result); | |
1821 | return -EINVAL; | |
1822 | } | |
1823 | } else | |
1824 | pp->mcast_count[crc_result]++; | |
1825 | ||
1826 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | /* Configure Fitering mode of Ethernet port */ | |
1832 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
1833 | int is_promisc) | |
1834 | { | |
1835 | u32 port_cfg_reg, val; | |
1836 | ||
1837 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
1838 | ||
1839 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
1840 | ||
1841 | /* Set / Clear UPM bit in port configuration register */ | |
1842 | if (is_promisc) { | |
1843 | /* Accept all Unicast addresses */ | |
1844 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
1845 | val |= MVNETA_FORCE_UNI; | |
1846 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
1847 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
1848 | } else { | |
1849 | /* Reject all Unicast addresses */ | |
1850 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
1851 | val &= ~MVNETA_FORCE_UNI; | |
1852 | } | |
1853 | ||
1854 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
1855 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
1856 | } | |
1857 | ||
1858 | /* register unicast and multicast addresses */ | |
1859 | static void mvneta_set_rx_mode(struct net_device *dev) | |
1860 | { | |
1861 | struct mvneta_port *pp = netdev_priv(dev); | |
1862 | struct netdev_hw_addr *ha; | |
1863 | ||
1864 | if (dev->flags & IFF_PROMISC) { | |
1865 | /* Accept all: Multicast + Unicast */ | |
1866 | mvneta_rx_unicast_promisc_set(pp, 1); | |
1867 | mvneta_set_ucast_table(pp, rxq_def); | |
1868 | mvneta_set_special_mcast_table(pp, rxq_def); | |
1869 | mvneta_set_other_mcast_table(pp, rxq_def); | |
1870 | } else { | |
1871 | /* Accept single Unicast */ | |
1872 | mvneta_rx_unicast_promisc_set(pp, 0); | |
1873 | mvneta_set_ucast_table(pp, -1); | |
1874 | mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); | |
1875 | ||
1876 | if (dev->flags & IFF_ALLMULTI) { | |
1877 | /* Accept all multicast */ | |
1878 | mvneta_set_special_mcast_table(pp, rxq_def); | |
1879 | mvneta_set_other_mcast_table(pp, rxq_def); | |
1880 | } else { | |
1881 | /* Accept only initialized multicast */ | |
1882 | mvneta_set_special_mcast_table(pp, -1); | |
1883 | mvneta_set_other_mcast_table(pp, -1); | |
1884 | ||
1885 | if (!netdev_mc_empty(dev)) { | |
1886 | netdev_for_each_mc_addr(ha, dev) { | |
1887 | mvneta_mcast_addr_set(pp, ha->addr, | |
1888 | rxq_def); | |
1889 | } | |
1890 | } | |
1891 | } | |
1892 | } | |
1893 | } | |
1894 | ||
1895 | /* Interrupt handling - the callback for request_irq() */ | |
1896 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
1897 | { | |
1898 | struct mvneta_port *pp = (struct mvneta_port *)dev_id; | |
1899 | ||
1900 | /* Mask all interrupts */ | |
1901 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1902 | ||
1903 | napi_schedule(&pp->napi); | |
1904 | ||
1905 | return IRQ_HANDLED; | |
1906 | } | |
1907 | ||
1908 | /* NAPI handler | |
1909 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
1910 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
1911 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
1912 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
1913 | * Each CPU has its own causeRxTx register | |
1914 | */ | |
1915 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
1916 | { | |
1917 | int rx_done = 0; | |
1918 | u32 cause_rx_tx; | |
1919 | unsigned long flags; | |
1920 | struct mvneta_port *pp = netdev_priv(napi->dev); | |
1921 | ||
1922 | if (!netif_running(pp->dev)) { | |
1923 | napi_complete(napi); | |
1924 | return rx_done; | |
1925 | } | |
1926 | ||
1927 | /* Read cause register */ | |
1928 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) & | |
71f6d1b3 | 1929 | (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); |
1930 | ||
1931 | /* Release Tx descriptors */ | |
1932 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
1933 | int tx_todo = 0; | |
1934 | ||
1935 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL), &tx_todo); | |
1936 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; | |
1937 | } | |
c5aff182 | 1938 | |
6a20c175 | 1939 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
1940 | * RX packets |
1941 | */ | |
1942 | cause_rx_tx |= pp->cause_rx_tx; | |
1943 | if (rxq_number > 1) { | |
71f6d1b3 | 1944 | while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) { |
c5aff182 TP |
1945 | int count; |
1946 | struct mvneta_rx_queue *rxq; | |
1947 | /* get rx queue number from cause_rx_tx */ | |
1948 | rxq = mvneta_rx_policy(pp, cause_rx_tx); | |
1949 | if (!rxq) | |
1950 | break; | |
1951 | ||
1952 | /* process the packet in that rx queue */ | |
1953 | count = mvneta_rx(pp, budget, rxq); | |
1954 | rx_done += count; | |
1955 | budget -= count; | |
1956 | if (budget > 0) { | |
6a20c175 TP |
1957 | /* set off the rx bit of the |
1958 | * corresponding bit in the cause rx | |
1959 | * tx register, so that next iteration | |
1960 | * will find the next rx queue where | |
1961 | * packets are received on | |
1962 | */ | |
c5aff182 TP |
1963 | cause_rx_tx &= ~((1 << rxq->id) << 8); |
1964 | } | |
1965 | } | |
1966 | } else { | |
1967 | rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); | |
1968 | budget -= rx_done; | |
1969 | } | |
1970 | ||
1971 | if (budget > 0) { | |
1972 | cause_rx_tx = 0; | |
1973 | napi_complete(napi); | |
1974 | local_irq_save(flags); | |
1975 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
71f6d1b3 | 1976 | MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); |
c5aff182 TP |
1977 | local_irq_restore(flags); |
1978 | } | |
1979 | ||
1980 | pp->cause_rx_tx = cause_rx_tx; | |
1981 | return rx_done; | |
1982 | } | |
1983 | ||
c5aff182 TP |
1984 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
1985 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
1986 | int num) | |
1987 | { | |
c5aff182 TP |
1988 | int i; |
1989 | ||
1990 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 1991 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
1992 | if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { | |
1993 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", | |
c5aff182 TP |
1994 | __func__, rxq->id, i, num); |
1995 | break; | |
1996 | } | |
c5aff182 TP |
1997 | } |
1998 | ||
1999 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
2000 | * get packets) |
2001 | */ | |
c5aff182 TP |
2002 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
2003 | ||
2004 | return i; | |
2005 | } | |
2006 | ||
2007 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
2008 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
2009 | { | |
2010 | int queue; | |
2011 | ||
2012 | /* free the skb's in the hal tx ring */ | |
2013 | for (queue = 0; queue < txq_number; queue++) | |
2014 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
2015 | ||
2016 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
2017 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
2018 | } | |
2019 | ||
2020 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
2021 | { | |
2022 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
2023 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
2024 | } | |
2025 | ||
2026 | /* Rx/Tx queue initialization/cleanup methods */ | |
2027 | ||
2028 | /* Create a specified RX queue */ | |
2029 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
2030 | struct mvneta_rx_queue *rxq) | |
2031 | ||
2032 | { | |
2033 | rxq->size = pp->rx_ring_size; | |
2034 | ||
2035 | /* Allocate memory for RX descriptors */ | |
2036 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2037 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2038 | &rxq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2039 | if (rxq->descs == NULL) |
c5aff182 | 2040 | return -ENOMEM; |
c5aff182 TP |
2041 | |
2042 | BUG_ON(rxq->descs != | |
2043 | PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | |
2044 | ||
2045 | rxq->last_desc = rxq->size - 1; | |
2046 | ||
2047 | /* Set Rx descriptors queue starting address */ | |
2048 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
2049 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
2050 | ||
2051 | /* Set Offset */ | |
2052 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); | |
2053 | ||
2054 | /* Set coalescing pkts and time */ | |
2055 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2056 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2057 | ||
2058 | /* Fill RXQ with buffers from RX pool */ | |
2059 | mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); | |
2060 | mvneta_rxq_bm_disable(pp, rxq); | |
2061 | mvneta_rxq_fill(pp, rxq, rxq->size); | |
2062 | ||
2063 | return 0; | |
2064 | } | |
2065 | ||
2066 | /* Cleanup Rx queue */ | |
2067 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
2068 | struct mvneta_rx_queue *rxq) | |
2069 | { | |
2070 | mvneta_rxq_drop_pkts(pp, rxq); | |
2071 | ||
2072 | if (rxq->descs) | |
2073 | dma_free_coherent(pp->dev->dev.parent, | |
2074 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2075 | rxq->descs, | |
2076 | rxq->descs_phys); | |
2077 | ||
2078 | rxq->descs = NULL; | |
2079 | rxq->last_desc = 0; | |
2080 | rxq->next_desc_to_proc = 0; | |
2081 | rxq->descs_phys = 0; | |
2082 | } | |
2083 | ||
2084 | /* Create and initialize a tx queue */ | |
2085 | static int mvneta_txq_init(struct mvneta_port *pp, | |
2086 | struct mvneta_tx_queue *txq) | |
2087 | { | |
2088 | txq->size = pp->tx_ring_size; | |
2089 | ||
2090 | /* Allocate memory for TX descriptors */ | |
2091 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2092 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2093 | &txq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2094 | if (txq->descs == NULL) |
c5aff182 | 2095 | return -ENOMEM; |
c5aff182 TP |
2096 | |
2097 | /* Make sure descriptor address is cache line size aligned */ | |
2098 | BUG_ON(txq->descs != | |
2099 | PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | |
2100 | ||
2101 | txq->last_desc = txq->size - 1; | |
2102 | ||
2103 | /* Set maximum bandwidth for enabled TXQs */ | |
2104 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
2105 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
2106 | ||
2107 | /* Set Tx descriptors queue starting address */ | |
2108 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
2109 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
2110 | ||
2111 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); | |
2112 | if (txq->tx_skb == NULL) { | |
2113 | dma_free_coherent(pp->dev->dev.parent, | |
2114 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2115 | txq->descs, txq->descs_phys); | |
2116 | return -ENOMEM; | |
2117 | } | |
2118 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
2119 | ||
2120 | return 0; | |
2121 | } | |
2122 | ||
2123 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
2124 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
2125 | struct mvneta_tx_queue *txq) | |
2126 | { | |
2127 | kfree(txq->tx_skb); | |
2128 | ||
2129 | if (txq->descs) | |
2130 | dma_free_coherent(pp->dev->dev.parent, | |
2131 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2132 | txq->descs, txq->descs_phys); | |
2133 | ||
2134 | txq->descs = NULL; | |
2135 | txq->last_desc = 0; | |
2136 | txq->next_desc_to_proc = 0; | |
2137 | txq->descs_phys = 0; | |
2138 | ||
2139 | /* Set minimum bandwidth for disabled TXQs */ | |
2140 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
2141 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
2142 | ||
2143 | /* Set Tx descriptors queue starting address and size */ | |
2144 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
2145 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
2146 | } | |
2147 | ||
2148 | /* Cleanup all Tx queues */ | |
2149 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
2150 | { | |
2151 | int queue; | |
2152 | ||
2153 | for (queue = 0; queue < txq_number; queue++) | |
2154 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
2155 | } | |
2156 | ||
2157 | /* Cleanup all Rx queues */ | |
2158 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
2159 | { | |
2160 | int queue; | |
2161 | ||
2162 | for (queue = 0; queue < rxq_number; queue++) | |
2163 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
2164 | } | |
2165 | ||
2166 | ||
2167 | /* Init all Rx queues */ | |
2168 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
2169 | { | |
2170 | int queue; | |
2171 | ||
2172 | for (queue = 0; queue < rxq_number; queue++) { | |
2173 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
2174 | if (err) { | |
2175 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
2176 | __func__, queue); | |
2177 | mvneta_cleanup_rxqs(pp); | |
2178 | return err; | |
2179 | } | |
2180 | } | |
2181 | ||
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | /* Init all tx queues */ | |
2186 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
2187 | { | |
2188 | int queue; | |
2189 | ||
2190 | for (queue = 0; queue < txq_number; queue++) { | |
2191 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
2192 | if (err) { | |
2193 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
2194 | __func__, queue); | |
2195 | mvneta_cleanup_txqs(pp); | |
2196 | return err; | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | return 0; | |
2201 | } | |
2202 | ||
2203 | static void mvneta_start_dev(struct mvneta_port *pp) | |
2204 | { | |
2205 | mvneta_max_rx_size_set(pp, pp->pkt_size); | |
2206 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
2207 | ||
2208 | /* start the Rx/Tx activity */ | |
2209 | mvneta_port_enable(pp); | |
2210 | ||
2211 | /* Enable polling on the port */ | |
2212 | napi_enable(&pp->napi); | |
2213 | ||
2214 | /* Unmask interrupts */ | |
2215 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
71f6d1b3 | 2216 | MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); |
c5aff182 TP |
2217 | |
2218 | phy_start(pp->phy_dev); | |
2219 | netif_tx_start_all_queues(pp->dev); | |
2220 | } | |
2221 | ||
2222 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
2223 | { | |
2224 | phy_stop(pp->phy_dev); | |
2225 | ||
2226 | napi_disable(&pp->napi); | |
2227 | ||
2228 | netif_carrier_off(pp->dev); | |
2229 | ||
2230 | mvneta_port_down(pp); | |
2231 | netif_tx_stop_all_queues(pp->dev); | |
2232 | ||
2233 | /* Stop the port activity */ | |
2234 | mvneta_port_disable(pp); | |
2235 | ||
2236 | /* Clear all ethernet port interrupts */ | |
2237 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2238 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
2239 | ||
2240 | /* Mask all ethernet port interrupts */ | |
2241 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2242 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
2243 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
2244 | ||
2245 | mvneta_tx_reset(pp); | |
2246 | mvneta_rx_reset(pp); | |
2247 | } | |
2248 | ||
c5aff182 TP |
2249 | /* Return positive if MTU is valid */ |
2250 | static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) | |
2251 | { | |
2252 | if (mtu < 68) { | |
2253 | netdev_err(dev, "cannot change mtu to less than 68\n"); | |
2254 | return -EINVAL; | |
2255 | } | |
2256 | ||
6a20c175 | 2257 | /* 9676 == 9700 - 20 and rounding to 8 */ |
c5aff182 TP |
2258 | if (mtu > 9676) { |
2259 | netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); | |
2260 | mtu = 9676; | |
2261 | } | |
2262 | ||
2263 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { | |
2264 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
2265 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
2266 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
2267 | } | |
2268 | ||
2269 | return mtu; | |
2270 | } | |
2271 | ||
2272 | /* Change the device mtu */ | |
2273 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
2274 | { | |
2275 | struct mvneta_port *pp = netdev_priv(dev); | |
2276 | int ret; | |
2277 | ||
2278 | mtu = mvneta_check_mtu_valid(dev, mtu); | |
2279 | if (mtu < 0) | |
2280 | return -EINVAL; | |
2281 | ||
2282 | dev->mtu = mtu; | |
2283 | ||
2284 | if (!netif_running(dev)) | |
2285 | return 0; | |
2286 | ||
6a20c175 | 2287 | /* The interface is running, so we have to force a |
c5aff182 TP |
2288 | * reallocation of the RXQs |
2289 | */ | |
2290 | mvneta_stop_dev(pp); | |
2291 | ||
2292 | mvneta_cleanup_txqs(pp); | |
2293 | mvneta_cleanup_rxqs(pp); | |
2294 | ||
2295 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); | |
8ec2cd48 | 2296 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
2297 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
2298 | |
2299 | ret = mvneta_setup_rxqs(pp); | |
2300 | if (ret) { | |
2301 | netdev_err(pp->dev, "unable to setup rxqs after MTU change\n"); | |
2302 | return ret; | |
2303 | } | |
2304 | ||
2305 | mvneta_setup_txqs(pp); | |
2306 | ||
2307 | mvneta_start_dev(pp); | |
2308 | mvneta_port_up(pp); | |
2309 | ||
2310 | return 0; | |
2311 | } | |
2312 | ||
8cc3e439 TP |
2313 | /* Get mac address */ |
2314 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
2315 | { | |
2316 | u32 mac_addr_l, mac_addr_h; | |
2317 | ||
2318 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
2319 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
2320 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
2321 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
2322 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
2323 | addr[3] = mac_addr_h & 0xFF; | |
2324 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
2325 | addr[5] = mac_addr_l & 0xFF; | |
2326 | } | |
2327 | ||
c5aff182 TP |
2328 | /* Handle setting mac address */ |
2329 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
2330 | { | |
2331 | struct mvneta_port *pp = netdev_priv(dev); | |
2332 | u8 *mac = addr + 2; | |
2333 | int i; | |
2334 | ||
2335 | if (netif_running(dev)) | |
2336 | return -EBUSY; | |
2337 | ||
2338 | /* Remove previous address table entry */ | |
2339 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
2340 | ||
2341 | /* Set new addr in hw */ | |
2342 | mvneta_mac_addr_set(pp, mac, rxq_def); | |
2343 | ||
2344 | /* Set addr in the device */ | |
2345 | for (i = 0; i < ETH_ALEN; i++) | |
2346 | dev->dev_addr[i] = mac[i]; | |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
2351 | static void mvneta_adjust_link(struct net_device *ndev) | |
2352 | { | |
2353 | struct mvneta_port *pp = netdev_priv(ndev); | |
2354 | struct phy_device *phydev = pp->phy_dev; | |
2355 | int status_change = 0; | |
2356 | ||
2357 | if (phydev->link) { | |
2358 | if ((pp->speed != phydev->speed) || | |
2359 | (pp->duplex != phydev->duplex)) { | |
2360 | u32 val; | |
2361 | ||
2362 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
2363 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
2364 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
71408602 TP |
2365 | MVNETA_GMAC_CONFIG_FULL_DUPLEX | |
2366 | MVNETA_GMAC_AN_SPEED_EN | | |
2367 | MVNETA_GMAC_AN_DUPLEX_EN); | |
c5aff182 TP |
2368 | |
2369 | if (phydev->duplex) | |
2370 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
2371 | ||
2372 | if (phydev->speed == SPEED_1000) | |
2373 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
2374 | else | |
2375 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
2376 | ||
2377 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
2378 | ||
2379 | pp->duplex = phydev->duplex; | |
2380 | pp->speed = phydev->speed; | |
2381 | } | |
2382 | } | |
2383 | ||
2384 | if (phydev->link != pp->link) { | |
2385 | if (!phydev->link) { | |
2386 | pp->duplex = -1; | |
2387 | pp->speed = 0; | |
2388 | } | |
2389 | ||
2390 | pp->link = phydev->link; | |
2391 | status_change = 1; | |
2392 | } | |
2393 | ||
2394 | if (status_change) { | |
2395 | if (phydev->link) { | |
2396 | u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
2397 | val |= (MVNETA_GMAC_FORCE_LINK_PASS | | |
2398 | MVNETA_GMAC_FORCE_LINK_DOWN); | |
2399 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
2400 | mvneta_port_up(pp); | |
2401 | netdev_info(pp->dev, "link up\n"); | |
2402 | } else { | |
2403 | mvneta_port_down(pp); | |
2404 | netdev_info(pp->dev, "link down\n"); | |
2405 | } | |
2406 | } | |
2407 | } | |
2408 | ||
2409 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
2410 | { | |
2411 | struct phy_device *phy_dev; | |
2412 | ||
2413 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, | |
2414 | pp->phy_interface); | |
2415 | if (!phy_dev) { | |
2416 | netdev_err(pp->dev, "could not find the PHY\n"); | |
2417 | return -ENODEV; | |
2418 | } | |
2419 | ||
2420 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
2421 | phy_dev->advertising = phy_dev->supported; | |
2422 | ||
2423 | pp->phy_dev = phy_dev; | |
2424 | pp->link = 0; | |
2425 | pp->duplex = 0; | |
2426 | pp->speed = 0; | |
2427 | ||
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
2432 | { | |
2433 | phy_disconnect(pp->phy_dev); | |
2434 | pp->phy_dev = NULL; | |
2435 | } | |
2436 | ||
2437 | static int mvneta_open(struct net_device *dev) | |
2438 | { | |
2439 | struct mvneta_port *pp = netdev_priv(dev); | |
2440 | int ret; | |
2441 | ||
2442 | mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); | |
2443 | ||
2444 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); | |
8ec2cd48 | 2445 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
2446 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
2447 | |
2448 | ret = mvneta_setup_rxqs(pp); | |
2449 | if (ret) | |
2450 | return ret; | |
2451 | ||
2452 | ret = mvneta_setup_txqs(pp); | |
2453 | if (ret) | |
2454 | goto err_cleanup_rxqs; | |
2455 | ||
2456 | /* Connect to port interrupt line */ | |
2457 | ret = request_irq(pp->dev->irq, mvneta_isr, 0, | |
2458 | MVNETA_DRIVER_NAME, pp); | |
2459 | if (ret) { | |
2460 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
2461 | goto err_cleanup_txqs; | |
2462 | } | |
2463 | ||
2464 | /* In default link is down */ | |
2465 | netif_carrier_off(pp->dev); | |
2466 | ||
2467 | ret = mvneta_mdio_probe(pp); | |
2468 | if (ret < 0) { | |
2469 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
2470 | goto err_free_irq; | |
2471 | } | |
2472 | ||
2473 | mvneta_start_dev(pp); | |
2474 | ||
2475 | return 0; | |
2476 | ||
2477 | err_free_irq: | |
2478 | free_irq(pp->dev->irq, pp); | |
2479 | err_cleanup_txqs: | |
2480 | mvneta_cleanup_txqs(pp); | |
2481 | err_cleanup_rxqs: | |
2482 | mvneta_cleanup_rxqs(pp); | |
2483 | return ret; | |
2484 | } | |
2485 | ||
2486 | /* Stop the port, free port interrupt line */ | |
2487 | static int mvneta_stop(struct net_device *dev) | |
2488 | { | |
2489 | struct mvneta_port *pp = netdev_priv(dev); | |
2490 | ||
2491 | mvneta_stop_dev(pp); | |
2492 | mvneta_mdio_remove(pp); | |
2493 | free_irq(dev->irq, pp); | |
2494 | mvneta_cleanup_rxqs(pp); | |
2495 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
2496 | |
2497 | return 0; | |
2498 | } | |
2499 | ||
15f59456 TP |
2500 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2501 | { | |
2502 | struct mvneta_port *pp = netdev_priv(dev); | |
2503 | int ret; | |
2504 | ||
2505 | if (!pp->phy_dev) | |
2506 | return -ENOTSUPP; | |
2507 | ||
2508 | ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd); | |
2509 | if (!ret) | |
2510 | mvneta_adjust_link(dev); | |
2511 | ||
2512 | return ret; | |
2513 | } | |
2514 | ||
c5aff182 TP |
2515 | /* Ethtool methods */ |
2516 | ||
2517 | /* Get settings (phy address, speed) for ethtools */ | |
2518 | int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2519 | { | |
2520 | struct mvneta_port *pp = netdev_priv(dev); | |
2521 | ||
2522 | if (!pp->phy_dev) | |
2523 | return -ENODEV; | |
2524 | ||
2525 | return phy_ethtool_gset(pp->phy_dev, cmd); | |
2526 | } | |
2527 | ||
2528 | /* Set settings (phy address, speed) for ethtools */ | |
2529 | int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2530 | { | |
2531 | struct mvneta_port *pp = netdev_priv(dev); | |
2532 | ||
2533 | if (!pp->phy_dev) | |
2534 | return -ENODEV; | |
2535 | ||
2536 | return phy_ethtool_sset(pp->phy_dev, cmd); | |
2537 | } | |
2538 | ||
2539 | /* Set interrupt coalescing for ethtools */ | |
2540 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
2541 | struct ethtool_coalesce *c) | |
2542 | { | |
2543 | struct mvneta_port *pp = netdev_priv(dev); | |
2544 | int queue; | |
2545 | ||
2546 | for (queue = 0; queue < rxq_number; queue++) { | |
2547 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
2548 | rxq->time_coal = c->rx_coalesce_usecs; | |
2549 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
2550 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2551 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2552 | } | |
2553 | ||
2554 | for (queue = 0; queue < txq_number; queue++) { | |
2555 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
2556 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
2557 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
2558 | } | |
2559 | ||
2560 | return 0; | |
2561 | } | |
2562 | ||
2563 | /* get coalescing for ethtools */ | |
2564 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
2565 | struct ethtool_coalesce *c) | |
2566 | { | |
2567 | struct mvneta_port *pp = netdev_priv(dev); | |
2568 | ||
2569 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
2570 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
2571 | ||
2572 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | ||
2577 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
2578 | struct ethtool_drvinfo *drvinfo) | |
2579 | { | |
2580 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
2581 | sizeof(drvinfo->driver)); | |
2582 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
2583 | sizeof(drvinfo->version)); | |
2584 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
2585 | sizeof(drvinfo->bus_info)); | |
2586 | } | |
2587 | ||
2588 | ||
2589 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
2590 | struct ethtool_ringparam *ring) | |
2591 | { | |
2592 | struct mvneta_port *pp = netdev_priv(netdev); | |
2593 | ||
2594 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
2595 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
2596 | ring->rx_pending = pp->rx_ring_size; | |
2597 | ring->tx_pending = pp->tx_ring_size; | |
2598 | } | |
2599 | ||
2600 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
2601 | struct ethtool_ringparam *ring) | |
2602 | { | |
2603 | struct mvneta_port *pp = netdev_priv(dev); | |
2604 | ||
2605 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
2606 | return -EINVAL; | |
2607 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
2608 | ring->rx_pending : MVNETA_MAX_RXD; | |
2609 | pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ? | |
2610 | ring->tx_pending : MVNETA_MAX_TXD; | |
2611 | ||
2612 | if (netif_running(dev)) { | |
2613 | mvneta_stop(dev); | |
2614 | if (mvneta_open(dev)) { | |
2615 | netdev_err(dev, | |
2616 | "error on opening device after ring param change\n"); | |
2617 | return -ENOMEM; | |
2618 | } | |
2619 | } | |
2620 | ||
2621 | return 0; | |
2622 | } | |
2623 | ||
2624 | static const struct net_device_ops mvneta_netdev_ops = { | |
2625 | .ndo_open = mvneta_open, | |
2626 | .ndo_stop = mvneta_stop, | |
2627 | .ndo_start_xmit = mvneta_tx, | |
2628 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
2629 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
2630 | .ndo_change_mtu = mvneta_change_mtu, | |
c5aff182 | 2631 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 2632 | .ndo_do_ioctl = mvneta_ioctl, |
c5aff182 TP |
2633 | }; |
2634 | ||
2635 | const struct ethtool_ops mvneta_eth_tool_ops = { | |
2636 | .get_link = ethtool_op_get_link, | |
2637 | .get_settings = mvneta_ethtool_get_settings, | |
2638 | .set_settings = mvneta_ethtool_set_settings, | |
2639 | .set_coalesce = mvneta_ethtool_set_coalesce, | |
2640 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
2641 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
2642 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
2643 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
2644 | }; | |
2645 | ||
2646 | /* Initialize hw */ | |
03ce758e | 2647 | static int mvneta_init(struct mvneta_port *pp, int phy_addr) |
c5aff182 TP |
2648 | { |
2649 | int queue; | |
2650 | ||
2651 | /* Disable port */ | |
2652 | mvneta_port_disable(pp); | |
2653 | ||
2654 | /* Set port default values */ | |
2655 | mvneta_defaults_set(pp); | |
2656 | ||
2657 | pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), | |
2658 | GFP_KERNEL); | |
2659 | if (!pp->txqs) | |
2660 | return -ENOMEM; | |
2661 | ||
2662 | /* Initialize TX descriptor rings */ | |
2663 | for (queue = 0; queue < txq_number; queue++) { | |
2664 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
2665 | txq->id = queue; | |
2666 | txq->size = pp->tx_ring_size; | |
2667 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
2668 | } | |
2669 | ||
2670 | pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), | |
2671 | GFP_KERNEL); | |
2672 | if (!pp->rxqs) { | |
2673 | kfree(pp->txqs); | |
2674 | return -ENOMEM; | |
2675 | } | |
2676 | ||
2677 | /* Create Rx descriptor rings */ | |
2678 | for (queue = 0; queue < rxq_number; queue++) { | |
2679 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
2680 | rxq->id = queue; | |
2681 | rxq->size = pp->rx_ring_size; | |
2682 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
2683 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
2684 | } | |
2685 | ||
2686 | return 0; | |
2687 | } | |
2688 | ||
70eeaf98 | 2689 | static void mvneta_deinit(struct mvneta_port *pp) |
c5aff182 TP |
2690 | { |
2691 | kfree(pp->txqs); | |
2692 | kfree(pp->rxqs); | |
2693 | } | |
2694 | ||
2695 | /* platform glue : initialize decoding windows */ | |
03ce758e GK |
2696 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
2697 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
2698 | { |
2699 | u32 win_enable; | |
2700 | u32 win_protect; | |
2701 | int i; | |
2702 | ||
2703 | for (i = 0; i < 6; i++) { | |
2704 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
2705 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
2706 | ||
2707 | if (i < 4) | |
2708 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
2709 | } | |
2710 | ||
2711 | win_enable = 0x3f; | |
2712 | win_protect = 0; | |
2713 | ||
2714 | for (i = 0; i < dram->num_cs; i++) { | |
2715 | const struct mbus_dram_window *cs = dram->cs + i; | |
2716 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | | |
2717 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); | |
2718 | ||
2719 | mvreg_write(pp, MVNETA_WIN_SIZE(i), | |
2720 | (cs->size - 1) & 0xffff0000); | |
2721 | ||
2722 | win_enable &= ~(1 << i); | |
2723 | win_protect |= 3 << (2 * i); | |
2724 | } | |
2725 | ||
2726 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
2727 | } | |
2728 | ||
2729 | /* Power up the port */ | |
03ce758e | 2730 | static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 TP |
2731 | { |
2732 | u32 val; | |
2733 | ||
2734 | /* MAC Cause register should be cleared */ | |
2735 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
2736 | ||
2737 | if (phy_mode == PHY_INTERFACE_MODE_SGMII) | |
2738 | mvneta_port_sgmii_config(pp); | |
2739 | ||
2740 | mvneta_gmac_rgmii_set(pp, 1); | |
2741 | ||
2742 | /* Cancel Port Reset */ | |
2743 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
2744 | val &= ~MVNETA_GMAC2_PORT_RESET; | |
2745 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
2746 | ||
2747 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
2748 | MVNETA_GMAC2_PORT_RESET) != 0) | |
2749 | continue; | |
2750 | } | |
2751 | ||
2752 | /* Device initialization routine */ | |
03ce758e | 2753 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 TP |
2754 | { |
2755 | const struct mbus_dram_target_info *dram_target_info; | |
2756 | struct device_node *dn = pdev->dev.of_node; | |
2757 | struct device_node *phy_node; | |
189dd626 | 2758 | u32 phy_addr; |
c5aff182 TP |
2759 | struct mvneta_port *pp; |
2760 | struct net_device *dev; | |
8cc3e439 TP |
2761 | const char *dt_mac_addr; |
2762 | char hw_mac_addr[ETH_ALEN]; | |
2763 | const char *mac_from; | |
c5aff182 TP |
2764 | int phy_mode; |
2765 | int err; | |
74c41b04 | 2766 | int cpu; |
c5aff182 | 2767 | |
6a20c175 | 2768 | /* Our multiqueue support is not complete, so for now, only |
c5aff182 TP |
2769 | * allow the usage of the first RX queue |
2770 | */ | |
2771 | if (rxq_def != 0) { | |
2772 | dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def); | |
2773 | return -EINVAL; | |
2774 | } | |
2775 | ||
ee40a116 | 2776 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
c5aff182 TP |
2777 | if (!dev) |
2778 | return -ENOMEM; | |
2779 | ||
2780 | dev->irq = irq_of_parse_and_map(dn, 0); | |
2781 | if (dev->irq == 0) { | |
2782 | err = -EINVAL; | |
2783 | goto err_free_netdev; | |
2784 | } | |
2785 | ||
2786 | phy_node = of_parse_phandle(dn, "phy", 0); | |
2787 | if (!phy_node) { | |
2788 | dev_err(&pdev->dev, "no associated PHY\n"); | |
2789 | err = -ENODEV; | |
2790 | goto err_free_irq; | |
2791 | } | |
2792 | ||
2793 | phy_mode = of_get_phy_mode(dn); | |
2794 | if (phy_mode < 0) { | |
2795 | dev_err(&pdev->dev, "incorrect phy-mode\n"); | |
2796 | err = -EINVAL; | |
2797 | goto err_free_irq; | |
2798 | } | |
2799 | ||
c5aff182 TP |
2800 | dev->tx_queue_len = MVNETA_MAX_TXD; |
2801 | dev->watchdog_timeo = 5 * HZ; | |
2802 | dev->netdev_ops = &mvneta_netdev_ops; | |
2803 | ||
2804 | SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops); | |
2805 | ||
2806 | pp = netdev_priv(dev); | |
2807 | ||
c5aff182 | 2808 | pp->weight = MVNETA_RX_POLL_WEIGHT; |
c5aff182 TP |
2809 | pp->phy_node = phy_node; |
2810 | pp->phy_interface = phy_mode; | |
2811 | ||
189dd626 TP |
2812 | pp->clk = devm_clk_get(&pdev->dev, NULL); |
2813 | if (IS_ERR(pp->clk)) { | |
2814 | err = PTR_ERR(pp->clk); | |
5445eaf3 | 2815 | goto err_free_irq; |
189dd626 TP |
2816 | } |
2817 | ||
2818 | clk_prepare_enable(pp->clk); | |
2819 | ||
5445eaf3 AP |
2820 | pp->base = of_iomap(dn, 0); |
2821 | if (pp->base == NULL) { | |
2822 | err = -ENOMEM; | |
2823 | goto err_clk; | |
2824 | } | |
2825 | ||
74c41b04 | 2826 | /* Alloc per-cpu stats */ |
2827 | pp->stats = alloc_percpu(struct mvneta_pcpu_stats); | |
2828 | if (!pp->stats) { | |
2829 | err = -ENOMEM; | |
2830 | goto err_unmap; | |
2831 | } | |
2832 | ||
2833 | for_each_possible_cpu(cpu) { | |
2834 | struct mvneta_pcpu_stats *stats; | |
2835 | stats = per_cpu_ptr(pp->stats, cpu); | |
2836 | u64_stats_init(&stats->syncp); | |
2837 | } | |
2838 | ||
8cc3e439 | 2839 | dt_mac_addr = of_get_mac_address(dn); |
6c7a9a3c | 2840 | if (dt_mac_addr) { |
8cc3e439 TP |
2841 | mac_from = "device tree"; |
2842 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); | |
2843 | } else { | |
2844 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
2845 | if (is_valid_ether_addr(hw_mac_addr)) { | |
2846 | mac_from = "hardware"; | |
2847 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
2848 | } else { | |
2849 | mac_from = "random"; | |
2850 | eth_hw_addr_random(dev); | |
2851 | } | |
2852 | } | |
2853 | ||
c5aff182 TP |
2854 | pp->tx_ring_size = MVNETA_MAX_TXD; |
2855 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
2856 | ||
2857 | pp->dev = dev; | |
2858 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2859 | ||
2860 | err = mvneta_init(pp, phy_addr); | |
2861 | if (err < 0) { | |
2862 | dev_err(&pdev->dev, "can't init eth hal\n"); | |
74c41b04 | 2863 | goto err_free_stats; |
c5aff182 TP |
2864 | } |
2865 | mvneta_port_power_up(pp, phy_mode); | |
2866 | ||
2867 | dram_target_info = mv_mbus_dram_info(); | |
2868 | if (dram_target_info) | |
2869 | mvneta_conf_mbus_windows(pp, dram_target_info); | |
2870 | ||
2871 | netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight); | |
2872 | ||
b50b72de | 2873 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
2874 | dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM; | |
2875 | dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM; | |
2876 | dev->priv_flags |= IFF_UNICAST_FLT; | |
2877 | ||
c5aff182 TP |
2878 | err = register_netdev(dev); |
2879 | if (err < 0) { | |
2880 | dev_err(&pdev->dev, "failed to register\n"); | |
2881 | goto err_deinit; | |
2882 | } | |
2883 | ||
8cc3e439 TP |
2884 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
2885 | dev->dev_addr); | |
c5aff182 TP |
2886 | |
2887 | platform_set_drvdata(pdev, pp->dev); | |
2888 | ||
2889 | return 0; | |
2890 | ||
2891 | err_deinit: | |
2892 | mvneta_deinit(pp); | |
74c41b04 | 2893 | err_free_stats: |
2894 | free_percpu(pp->stats); | |
c5aff182 TP |
2895 | err_unmap: |
2896 | iounmap(pp->base); | |
5445eaf3 AP |
2897 | err_clk: |
2898 | clk_disable_unprepare(pp->clk); | |
c5aff182 TP |
2899 | err_free_irq: |
2900 | irq_dispose_mapping(dev->irq); | |
2901 | err_free_netdev: | |
2902 | free_netdev(dev); | |
2903 | return err; | |
2904 | } | |
2905 | ||
2906 | /* Device removal routine */ | |
03ce758e | 2907 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
2908 | { |
2909 | struct net_device *dev = platform_get_drvdata(pdev); | |
2910 | struct mvneta_port *pp = netdev_priv(dev); | |
2911 | ||
2912 | unregister_netdev(dev); | |
2913 | mvneta_deinit(pp); | |
189dd626 | 2914 | clk_disable_unprepare(pp->clk); |
74c41b04 | 2915 | free_percpu(pp->stats); |
c5aff182 TP |
2916 | iounmap(pp->base); |
2917 | irq_dispose_mapping(dev->irq); | |
2918 | free_netdev(dev); | |
2919 | ||
c5aff182 TP |
2920 | return 0; |
2921 | } | |
2922 | ||
2923 | static const struct of_device_id mvneta_match[] = { | |
2924 | { .compatible = "marvell,armada-370-neta" }, | |
2925 | { } | |
2926 | }; | |
2927 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
2928 | ||
2929 | static struct platform_driver mvneta_driver = { | |
2930 | .probe = mvneta_probe, | |
03ce758e | 2931 | .remove = mvneta_remove, |
c5aff182 TP |
2932 | .driver = { |
2933 | .name = MVNETA_DRIVER_NAME, | |
2934 | .of_match_table = mvneta_match, | |
2935 | }, | |
2936 | }; | |
2937 | ||
2938 | module_platform_driver(mvneta_driver); | |
2939 | ||
2940 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
2941 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
2942 | MODULE_LICENSE("GPL"); | |
2943 | ||
2944 | module_param(rxq_number, int, S_IRUGO); | |
2945 | module_param(txq_number, int, S_IRUGO); | |
2946 | ||
2947 | module_param(rxq_def, int, S_IRUGO); |