]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'net-smc-fixes'
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / marvell / mvpp2 / mvpp2_main.c
CommitLineData
f1e37e31 1// SPDX-License-Identifier: GPL-2.0
3f518509
MW		 2/*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
3f518509
MW		 8 */
9
a75edc7c 10#include <linux/acpi.h>
3f518509
MW		 11#include <linux/kernel.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/platform_device.h>
15#include <linux/skbuff.h>
16#include <linux/inetdevice.h>
17#include <linux/mbus.h>
18#include <linux/module.h>
f84bf386 19#include <linux/mfd/syscon.h>
3f518509
MW		 20#include <linux/interrupt.h>
21#include <linux/cpumask.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_mdio.h>
25#include <linux/of_net.h>
26#include <linux/of_address.h>
faca9247 27#include <linux/of_device.h>
3f518509 28#include <linux/phy.h>
4bb04326 29#include <linux/phylink.h>
542897d9 30#include <linux/phy/phy.h>
3f518509 31#include <linux/clk.h>
edc660fa
MW		 32#include <linux/hrtimer.h>
33#include <linux/ktime.h>
f84bf386 34#include <linux/regmap.h>
3f518509
MW		 35#include <uapi/linux/ppp_defs.h>
36#include <net/ip.h>
37#include <net/ipv6.h>
186cd4d4 38#include <net/tso.h>
3f518509 39
db9d7d36
MC		 40#include "mvpp2.h"
41#include "mvpp2_prs.h"
42#include "mvpp2_cls.h"
a786841d 43
01d04936
SC		 44enum mvpp2_bm_pool_log_num {
45 MVPP2_BM_SHORT,
46 MVPP2_BM_LONG,
576193f2 47 MVPP2_BM_JUMBO,
01d04936 48 MVPP2_BM_POOLS_NUM
3f518509
MW		 49};
50
db9d7d36
MC		 51static struct {
52 int pkt_size;
53 int buf_num;
54} mvpp2_pools[MVPP2_BM_POOLS_NUM];
3f518509 55
db9d7d36
MC		 56/* The prototype is added here to be used in start_dev when using ACPI. This
57 * will be removed once phylink is used for all modes (dt+ACPI).
58 */
59static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
60 const struct phylink_link_state *state);
41948ccb
AT		 61static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
62 phy_interface_t interface, struct phy_device *phy);
10fea26c 63
db9d7d36
MC		 64/* Queue modes */
65#define MVPP2_QDIST_SINGLE_MODE 0
66#define MVPP2_QDIST_MULTI_MODE 1
3f518509 67
3f6aaf72 68static int queue_mode = MVPP2_QDIST_MULTI_MODE;
3f518509 69
db9d7d36
MC		 70module_param(queue_mode, int, 0444);
71MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
3f518509 72
db9d7d36 73/* Utility/helper methods */
3f518509 74
db9d7d36
MC		 75void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
76{
77 writel(data, priv->swth_base[0] + offset);
3f518509
MW		 78}
79
db9d7d36 80u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
3f518509 81{
db9d7d36 82 return readl(priv->swth_base[0] + offset);
3f518509
MW		 83}
84
db9d7d36 85u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
3f518509 86{
db9d7d36 87 return readl_relaxed(priv->swth_base[0] + offset);
3f518509 88}
db9d7d36
MC		 89/* These accessors should be used to access:
90 *
91 * - per-CPU registers, where each CPU has its own copy of the
92 * register.
93 *
94 * MVPP2_BM_VIRT_ALLOC_REG
95 * MVPP2_BM_ADDR_HIGH_ALLOC
96 * MVPP22_BM_ADDR_HIGH_RLS_REG
97 * MVPP2_BM_VIRT_RLS_REG
98 * MVPP2_ISR_RX_TX_CAUSE_REG
99 * MVPP2_ISR_RX_TX_MASK_REG
100 * MVPP2_TXQ_NUM_REG
101 * MVPP2_AGGR_TXQ_UPDATE_REG
102 * MVPP2_TXQ_RSVD_REQ_REG
103 * MVPP2_TXQ_RSVD_RSLT_REG
104 * MVPP2_TXQ_SENT_REG
105 * MVPP2_RXQ_NUM_REG
106 *
107 * - global registers that must be accessed through a specific CPU
108 * window, because they are related to an access to a per-CPU
109 * register
110 *
111 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
112 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
113 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
114 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
115 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
116 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
117 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
118 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
119 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
120 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
121 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
122 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
123 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
124 */
125void mvpp2_percpu_write(struct mvpp2 *priv, int cpu,
126 u32 offset, u32 data)
127{
128 writel(data, priv->swth_base[cpu] + offset);
3f518509
MW		 129}
130
db9d7d36
MC		 131u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu,
132 u32 offset)
3f518509 133{
db9d7d36
MC		 134 return readl(priv->swth_base[cpu] + offset);
135}
3f518509 136
db9d7d36
MC		 137void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu,
138 u32 offset, u32 data)
139{
140 writel_relaxed(data, priv->swth_base[cpu] + offset);
141}
0c6d9b44 142
fe083b3f 143static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, int cpu,
db9d7d36
MC		 144 u32 offset)
145{
146 return readl_relaxed(priv->swth_base[cpu] + offset);
147}
3f518509 148
db9d7d36
MC		 149static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
150 struct mvpp2_tx_desc *tx_desc)
151{
152 if (port->priv->hw_version == MVPP21)
7b9c7d7d 153 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
db9d7d36 154 else
7b9c7d7d
MC		 155 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
156 MVPP2_DESC_DMA_MASK;
db9d7d36 157}
3f518509 158
db9d7d36
MC		 159static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
160 struct mvpp2_tx_desc *tx_desc,
161 dma_addr_t dma_addr)
162{
163 dma_addr_t addr, offset;
3f518509 164
db9d7d36
MC		 165 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
166 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
3f518509 167
db9d7d36 168 if (port->priv->hw_version == MVPP21) {
7b9c7d7d 169 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
db9d7d36 170 tx_desc->pp21.packet_offset = offset;
0c6d9b44 171 } else {
7b9c7d7d 172 __le64 val = cpu_to_le64(addr);
3f518509 173
7b9c7d7d 174 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
db9d7d36
MC		 175 tx_desc->pp22.buf_dma_addr_ptp |= val;
176 tx_desc->pp22.packet_offset = offset;
177 }
3f518509
MW		 178}
179
db9d7d36
MC		 180static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
181 struct mvpp2_tx_desc *tx_desc)
3f518509 182{
db9d7d36 183 if (port->priv->hw_version == MVPP21)
7b9c7d7d 184 return le16_to_cpu(tx_desc->pp21.data_size);
db9d7d36 185 else
7b9c7d7d 186 return le16_to_cpu(tx_desc->pp22.data_size);
3f518509
MW		 187}
188
db9d7d36
MC		 189static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
190 struct mvpp2_tx_desc *tx_desc,
191 size_t size)
3f518509 192{
db9d7d36 193 if (port->priv->hw_version == MVPP21)
7b9c7d7d 194 tx_desc->pp21.data_size = cpu_to_le16(size);
db9d7d36 195 else
7b9c7d7d 196 tx_desc->pp22.data_size = cpu_to_le16(size);
3f518509
MW		 197}
198
db9d7d36
MC		 199static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
200 struct mvpp2_tx_desc *tx_desc,
201 unsigned int txq)
3f518509 202{
db9d7d36
MC		 203 if (port->priv->hw_version == MVPP21)
204 tx_desc->pp21.phys_txq = txq;
205 else
206 tx_desc->pp22.phys_txq = txq;
3f518509
MW		 207}
208
db9d7d36
MC		 209static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
210 struct mvpp2_tx_desc *tx_desc,
211 unsigned int command)
3f518509 212{
db9d7d36 213 if (port->priv->hw_version == MVPP21)
7b9c7d7d 214 tx_desc->pp21.command = cpu_to_le32(command);
db9d7d36 215 else
7b9c7d7d 216 tx_desc->pp22.command = cpu_to_le32(command);
db9d7d36 217}
3f518509 218
db9d7d36
MC		 219static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
220 struct mvpp2_tx_desc *tx_desc)
221{
222 if (port->priv->hw_version == MVPP21)
223 return tx_desc->pp21.packet_offset;
224 else
225 return tx_desc->pp22.packet_offset;
226}
3f518509 227
db9d7d36
MC		 228static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
229 struct mvpp2_rx_desc *rx_desc)
230{
231 if (port->priv->hw_version == MVPP21)
7b9c7d7d 232 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
db9d7d36 233 else
7b9c7d7d
MC		 234 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
235 MVPP2_DESC_DMA_MASK;
db9d7d36 236}
3f518509 237
db9d7d36
MC		 238static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
239 struct mvpp2_rx_desc *rx_desc)
240{
241 if (port->priv->hw_version == MVPP21)
7b9c7d7d 242 return le32_to_cpu(rx_desc->pp21.buf_cookie);
db9d7d36 243 else
7b9c7d7d
MC		 244 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
245 MVPP2_DESC_DMA_MASK;
db9d7d36 246}
3f518509 247
db9d7d36
MC		 248static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
249 struct mvpp2_rx_desc *rx_desc)
250{
251 if (port->priv->hw_version == MVPP21)
7b9c7d7d 252 return le16_to_cpu(rx_desc->pp21.data_size);
db9d7d36 253 else
7b9c7d7d 254 return le16_to_cpu(rx_desc->pp22.data_size);
db9d7d36 255}
3f518509 256
db9d7d36
MC		 257static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
258 struct mvpp2_rx_desc *rx_desc)
259{
260 if (port->priv->hw_version == MVPP21)
7b9c7d7d 261 return le32_to_cpu(rx_desc->pp21.status);
db9d7d36 262 else
7b9c7d7d 263 return le32_to_cpu(rx_desc->pp22.status);
3f518509
MW		 264}
265
db9d7d36 266static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
3f518509 267{
db9d7d36
MC		 268 txq_pcpu->txq_get_index++;
269 if (txq_pcpu->txq_get_index == txq_pcpu->size)
270 txq_pcpu->txq_get_index = 0;
271}
3f518509 272
db9d7d36
MC		 273static void mvpp2_txq_inc_put(struct mvpp2_port *port,
274 struct mvpp2_txq_pcpu *txq_pcpu,
275 struct sk_buff *skb,
276 struct mvpp2_tx_desc *tx_desc)
277{
278 struct mvpp2_txq_pcpu_buf *tx_buf =
279 txq_pcpu->buffs + txq_pcpu->txq_put_index;
280 tx_buf->skb = skb;
281 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
282 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
283 mvpp2_txdesc_offset_get(port, tx_desc);
284 txq_pcpu->txq_put_index++;
285 if (txq_pcpu->txq_put_index == txq_pcpu->size)
286 txq_pcpu->txq_put_index = 0;
287}
3f518509 288
db9d7d36
MC		 289/* Get number of physical egress port */
290static inline int mvpp2_egress_port(struct mvpp2_port *port)
291{
292 return MVPP2_MAX_TCONT + port->id;
293}
3f518509 294
db9d7d36
MC		 295/* Get number of physical TXQ */
296static inline int mvpp2_txq_phys(int port, int txq)
297{
298 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
3f518509
MW		 299}
300
0e037281
TP		 301static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
302{
303 if (likely(pool->frag_size <= PAGE_SIZE))
304 return netdev_alloc_frag(pool->frag_size);
305 else
306 return kmalloc(pool->frag_size, GFP_ATOMIC);
307}
308
309static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
310{
311 if (likely(pool->frag_size <= PAGE_SIZE))
312 skb_free_frag(data);
313 else
314 kfree(data);
315}
316
3f518509
MW		 317/* Buffer Manager configuration routines */
318
319/* Create pool */
320static int mvpp2_bm_pool_create(struct platform_device *pdev,
321 struct mvpp2 *priv,
322 struct mvpp2_bm_pool *bm_pool, int size)
323{
3f518509
MW		 324 u32 val;
325
d01524d8
TP		 326 /* Number of buffer pointers must be a multiple of 16, as per
327 * hardware constraints
328 */
329 if (!IS_ALIGNED(size, 16))
330 return -EINVAL;
331
332 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
333 * bytes per buffer pointer
334 */
335 if (priv->hw_version == MVPP21)
336 bm_pool->size_bytes = 2 * sizeof(u32) * size;
337 else
338 bm_pool->size_bytes = 2 * sizeof(u64) * size;
339
340 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
20396136 341 &bm_pool->dma_addr,
3f518509
MW		 342 GFP_KERNEL);
343 if (!bm_pool->virt_addr)
344 return -ENOMEM;
345
d3158807
TP		 346 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
347 MVPP2_BM_POOL_PTR_ALIGN)) {
d01524d8
TP		 348 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
349 bm_pool->virt_addr, bm_pool->dma_addr);
3f518509
MW		 350 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
351 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
352 return -ENOMEM;
353 }
354
355 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
d01524d8 356 lower_32_bits(bm_pool->dma_addr));
3f518509
MW		 357 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
358
359 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
360 val |= MVPP2_BM_START_MASK;
361 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
362
3f518509
MW		 363 bm_pool->size = size;
364 bm_pool->pkt_size = 0;
365 bm_pool->buf_num = 0;
3f518509
MW		 366
367 return 0;
368}
369
370/* Set pool buffer size */
371static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
372 struct mvpp2_bm_pool *bm_pool,
373 int buf_size)
374{
375 u32 val;
376
377 bm_pool->buf_size = buf_size;
378
379 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
380 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
381}
382
d01524d8
TP		 383static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
384 struct mvpp2_bm_pool *bm_pool,
385 dma_addr_t *dma_addr,
386 phys_addr_t *phys_addr)
387{
a704bb5c 388 int cpu = get_cpu();
a786841d
TP		 389
390 *dma_addr = mvpp2_percpu_read(priv, cpu,
391 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
392 *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG);
d01524d8
TP		 393
394 if (priv->hw_version == MVPP22) {
395 u32 val;
396 u32 dma_addr_highbits, phys_addr_highbits;
397
a786841d 398 val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC);
d01524d8
TP		 399 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
400 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
401 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
402
403 if (sizeof(dma_addr_t) == 8)
404 *dma_addr |= (u64)dma_addr_highbits << 32;
405
406 if (sizeof(phys_addr_t) == 8)
407 *phys_addr |= (u64)phys_addr_highbits << 32;
408 }
a704bb5c
TP		 409
410 put_cpu();
d01524d8
TP		 411}
412
7861f12b 413/* Free all buffers from the pool */
4229d502 414static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
effbf5f5 415 struct mvpp2_bm_pool *bm_pool, int buf_num)
3f518509
MW		 416{
417 int i;
418
effbf5f5
SC		 419 if (buf_num > bm_pool->buf_num) {
420 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
421 bm_pool->id, buf_num);
422 buf_num = bm_pool->buf_num;
423 }
424
425 for (i = 0; i < buf_num; i++) {
20396136 426 dma_addr_t buf_dma_addr;
4e4a105f
TP		 427 phys_addr_t buf_phys_addr;
428 void *data;
3f518509 429
d01524d8
TP		 430 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
431 &buf_dma_addr, &buf_phys_addr);
4229d502 432
20396136 433 dma_unmap_single(dev, buf_dma_addr,
4229d502
MW		 434 bm_pool->buf_size, DMA_FROM_DEVICE);
435
4e4a105f
TP		 436 data = (void *)phys_to_virt(buf_phys_addr);
437 if (!data)
3f518509 438 break;
0e037281 439
4e4a105f 440 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 441 }
442
443 /* Update BM driver with number of buffers removed from pool */
444 bm_pool->buf_num -= i;
3f518509
MW		 445}
446
effbf5f5 447/* Check number of buffers in BM pool */
6e61e10a 448static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
effbf5f5
SC		 449{
450 int buf_num = 0;
451
452 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
453 MVPP22_BM_POOL_PTRS_NUM_MASK;
454 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
455 MVPP2_BM_BPPI_PTR_NUM_MASK;
456
457 /* HW has one buffer ready which is not reflected in the counters */
458 if (buf_num)
459 buf_num += 1;
460
461 return buf_num;
462}
463
3f518509
MW		 464/* Cleanup pool */
465static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
466 struct mvpp2 *priv,
467 struct mvpp2_bm_pool *bm_pool)
468{
effbf5f5 469 int buf_num;
3f518509
MW		 470 u32 val;
471
effbf5f5
SC		 472 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
473 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
474
475 /* Check buffer counters after free */
476 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
477 if (buf_num) {
478 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
479 bm_pool->id, bm_pool->buf_num);
3f518509
MW		 480 return 0;
481 }
482
483 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
484 val |= MVPP2_BM_STOP_MASK;
485 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
486
d01524d8 487 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
3f518509 488 bm_pool->virt_addr,
20396136 489 bm_pool->dma_addr);
3f518509
MW		 490 return 0;
491}
492
493static int mvpp2_bm_pools_init(struct platform_device *pdev,
494 struct mvpp2 *priv)
495{
496 int i, err, size;
497 struct mvpp2_bm_pool *bm_pool;
498
499 /* Create all pools with maximum size */
500 size = MVPP2_BM_POOL_SIZE_MAX;
501 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
502 bm_pool = &priv->bm_pools[i];
503 bm_pool->id = i;
504 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
505 if (err)
506 goto err_unroll_pools;
507 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
508 }
509 return 0;
510
511err_unroll_pools:
512 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
513 for (i = i - 1; i >= 0; i--)
514 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
515 return err;
516}
517
518static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
519{
520 int i, err;
521
522 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
523 /* Mask BM all interrupts */
524 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
525 /* Clear BM cause register */
526 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
527 }
528
529 /* Allocate and initialize BM pools */
530 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
81f915eb 531 sizeof(*priv->bm_pools), GFP_KERNEL);
3f518509
MW		 532 if (!priv->bm_pools)
533 return -ENOMEM;
534
535 err = mvpp2_bm_pools_init(pdev, priv);
536 if (err < 0)
537 return err;
538 return 0;
539}
540
01d04936
SC		 541static void mvpp2_setup_bm_pool(void)
542{
543 /* Short pool */
544 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
545 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
546
547 /* Long pool */
548 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
549 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
576193f2
SC		 550
551 /* Jumbo pool */
552 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
553 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
01d04936
SC		 554}
555
3f518509
MW		 556/* Attach long pool to rxq */
557static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
558 int lrxq, int long_pool)
559{
5eac892a 560 u32 val, mask;
3f518509
MW		 561 int prxq;
562
563 /* Get queue physical ID */
564 prxq = port->rxqs[lrxq]->id;
565
5eac892a
TP		 566 if (port->priv->hw_version == MVPP21)
567 mask = MVPP21_RXQ_POOL_LONG_MASK;
568 else
569 mask = MVPP22_RXQ_POOL_LONG_MASK;
3f518509 570
5eac892a
TP		 571 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
572 val &= ~mask;
573 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
3f518509
MW		 574 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
575}
576
577/* Attach short pool to rxq */
578static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
579 int lrxq, int short_pool)
580{
5eac892a 581 u32 val, mask;
3f518509
MW		 582 int prxq;
583
584 /* Get queue physical ID */
585 prxq = port->rxqs[lrxq]->id;
586
5eac892a
TP		 587 if (port->priv->hw_version == MVPP21)
588 mask = MVPP21_RXQ_POOL_SHORT_MASK;
589 else
590 mask = MVPP22_RXQ_POOL_SHORT_MASK;
3f518509 591
5eac892a
TP		 592 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
593 val &= ~mask;
594 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
3f518509
MW		 595 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
596}
597
0e037281
TP		 598static void *mvpp2_buf_alloc(struct mvpp2_port *port,
599 struct mvpp2_bm_pool *bm_pool,
20396136 600 dma_addr_t *buf_dma_addr,
4e4a105f 601 phys_addr_t *buf_phys_addr,
0e037281 602 gfp_t gfp_mask)
3f518509 603{
20396136 604 dma_addr_t dma_addr;
0e037281 605 void *data;
3f518509 606
0e037281
TP		 607 data = mvpp2_frag_alloc(bm_pool);
608 if (!data)
3f518509
MW		 609 return NULL;
610
20396136
TP		 611 dma_addr = dma_map_single(port->dev->dev.parent, data,
612 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
613 DMA_FROM_DEVICE);
614 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
0e037281 615 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 616 return NULL;
617 }
20396136 618 *buf_dma_addr = dma_addr;
4e4a105f 619 *buf_phys_addr = virt_to_phys(data);
3f518509 620
0e037281 621 return data;
3f518509
MW		 622}
623
3f518509
MW		 624/* Release buffer to BM */
625static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
20396136 626 dma_addr_t buf_dma_addr,
4e4a105f 627 phys_addr_t buf_phys_addr)
3f518509 628{
a704bb5c 629 int cpu = get_cpu();
a786841d 630
d01524d8
TP		 631 if (port->priv->hw_version == MVPP22) {
632 u32 val = 0;
633
634 if (sizeof(dma_addr_t) == 8)
635 val |= upper_32_bits(buf_dma_addr) &
636 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
637
638 if (sizeof(phys_addr_t) == 8)
639 val |= (upper_32_bits(buf_phys_addr)
640 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
641 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
642
cdcfeb0f
YM		 643 mvpp2_percpu_write_relaxed(port->priv, cpu,
644 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
d01524d8
TP		 645 }
646
4e4a105f
TP		 647 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
648 * returned in the "cookie" field of the RX
649 * descriptor. Instead of storing the virtual address, we
650 * store the physical address
651 */
cdcfeb0f
YM		 652 mvpp2_percpu_write_relaxed(port->priv, cpu,
653 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
654 mvpp2_percpu_write_relaxed(port->priv, cpu,
655 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
a704bb5c
TP		 656
657 put_cpu();
3f518509
MW		 658}
659
3f518509
MW		 660/* Allocate buffers for the pool */
661static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
662 struct mvpp2_bm_pool *bm_pool, int buf_num)
663{
3f518509 664 int i, buf_size, total_size;
20396136 665 dma_addr_t dma_addr;
4e4a105f 666 phys_addr_t phys_addr;
0e037281 667 void *buf;
3f518509
MW		 668
669 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
670 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
671
672 if (buf_num < 0 ||
673 (buf_num + bm_pool->buf_num > bm_pool->size)) {
674 netdev_err(port->dev,
675 "cannot allocate %d buffers for pool %d\n",
676 buf_num, bm_pool->id);
677 return 0;
678 }
679
3f518509 680 for (i = 0; i < buf_num; i++) {
4e4a105f
TP		 681 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
682 &phys_addr, GFP_KERNEL);
0e037281 683 if (!buf)
3f518509
MW		 684 break;
685
20396136 686 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
4e4a105f 687 phys_addr);
3f518509
MW		 688 }
689
690 /* Update BM driver with number of buffers added to pool */
691 bm_pool->buf_num += i;
3f518509
MW		 692
693 netdev_dbg(port->dev,
01d04936 694 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3f518509
MW		 695 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
696
697 netdev_dbg(port->dev,
01d04936 698 "pool %d: %d of %d buffers added\n",
3f518509
MW		 699 bm_pool->id, i, buf_num);
700 return i;
701}
702
703/* Notify the driver that BM pool is being used as specific type and return the
704 * pool pointer on success
705 */
706static struct mvpp2_bm_pool *
01d04936 707mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
3f518509 708{
3f518509
MW		 709 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
710 int num;
711
01d04936
SC		 712 if (pool >= MVPP2_BM_POOLS_NUM) {
713 netdev_err(port->dev, "Invalid pool %d\n", pool);
3f518509
MW		 714 return NULL;
715 }
716
3f518509
MW		 717 /* Allocate buffers in case BM pool is used as long pool, but packet
718 * size doesn't match MTU or BM pool hasn't being used yet
719 */
01d04936 720 if (new_pool->pkt_size == 0) {
3f518509
MW		 721 int pkts_num;
722
723 /* Set default buffer number or free all the buffers in case
724 * the pool is not empty
725 */
726 pkts_num = new_pool->buf_num;
727 if (pkts_num == 0)
01d04936 728 pkts_num = mvpp2_pools[pool].buf_num;
3f518509 729 else
4229d502 730 mvpp2_bm_bufs_free(port->dev->dev.parent,
effbf5f5 731 port->priv, new_pool, pkts_num);
3f518509
MW		 732
733 new_pool->pkt_size = pkt_size;
0e037281
TP		 734 new_pool->frag_size =
735 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
736 MVPP2_SKB_SHINFO_SIZE;
3f518509
MW		 737
738 /* Allocate buffers for this pool */
739 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
740 if (num != pkts_num) {
741 WARN(1, "pool %d: %d of %d allocated\n",
742 new_pool->id, num, pkts_num);
3f518509
MW		 743 return NULL;
744 }
745 }
746
747 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
748 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
749
3f518509
MW		 750 return new_pool;
751}
752
753/* Initialize pools for swf */
754static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
755{
3f518509 756 int rxq;
576193f2
SC		 757 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
758
759 /* If port pkt_size is higher than 1518B:
760 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
761 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
762 */
763 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
764 long_log_pool = MVPP2_BM_JUMBO;
765 short_log_pool = MVPP2_BM_LONG;
766 } else {
767 long_log_pool = MVPP2_BM_LONG;
768 short_log_pool = MVPP2_BM_SHORT;
769 }
3f518509
MW		 770
771 if (!port->pool_long) {
772 port->pool_long =
576193f2
SC		 773 mvpp2_bm_pool_use(port, long_log_pool,
774 mvpp2_pools[long_log_pool].pkt_size);
3f518509
MW		 775 if (!port->pool_long)
776 return -ENOMEM;
777
576193f2 778 port->pool_long->port_map |= BIT(port->id);
3f518509 779
09f83975 780 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 781 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
782 }
783
784 if (!port->pool_short) {
785 port->pool_short =
576193f2 786 mvpp2_bm_pool_use(port, short_log_pool,
e2e03164 787 mvpp2_pools[short_log_pool].pkt_size);
3f518509
MW		 788 if (!port->pool_short)
789 return -ENOMEM;
790
576193f2 791 port->pool_short->port_map |= BIT(port->id);
3f518509 792
09f83975 793 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 794 mvpp2_rxq_short_pool_set(port, rxq,
795 port->pool_short->id);
796 }
797
798 return 0;
799}
800
801static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
802{
803 struct mvpp2_port *port = netdev_priv(dev);
576193f2
SC		 804 enum mvpp2_bm_pool_log_num new_long_pool;
805 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3f518509 806
576193f2
SC		 807 /* If port MTU is higher than 1518B:
808 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
809 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
810 */
811 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
812 new_long_pool = MVPP2_BM_JUMBO;
813 else
814 new_long_pool = MVPP2_BM_LONG;
815
816 if (new_long_pool != port->pool_long->id) {
817 /* Remove port from old short & long pool */
818 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
819 port->pool_long->pkt_size);
820 port->pool_long->port_map &= ~BIT(port->id);
821 port->pool_long = NULL;
822
823 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
824 port->pool_short->pkt_size);
825 port->pool_short->port_map &= ~BIT(port->id);
826 port->pool_short = NULL;
827
828 port->pkt_size = pkt_size;
829
830 /* Add port to new short & long pool */
831 mvpp2_swf_bm_pool_init(port);
832
833 /* Update L4 checksum when jumbo enable/disable on port */
834 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
835 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
836 dev->hw_features &= ~(NETIF_F_IP_CSUM |
837 NETIF_F_IPV6_CSUM);
838 } else {
839 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
840 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
841 }
3f518509
MW		 842 }
843
3f518509 844 dev->mtu = mtu;
576193f2
SC		 845 dev->wanted_features = dev->features;
846
3f518509
MW		 847 netdev_update_features(dev);
848 return 0;
849}
850
851static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
852{
591f4cfa
TP		 853 int i, sw_thread_mask = 0;
854
855 for (i = 0; i < port->nqvecs; i++)
856 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
3f518509 857
3f518509 858 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa 859 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
3f518509
MW		 860}
861
862static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
863{
591f4cfa
TP		 864 int i, sw_thread_mask = 0;
865
866 for (i = 0; i < port->nqvecs; i++)
867 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
868
869 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
870 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
871}
872
873static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
874{
875 struct mvpp2_port *port = qvec->port;
3f518509 876
3f518509 877 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa
TP		 878 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
879}
880
881static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
882{
883 struct mvpp2_port *port = qvec->port;
884
885 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
886 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
3f518509
MW		 887}
888
e0af22d9
TP		 889/* Mask the current CPU's Rx/Tx interrupts
890 * Called by on_each_cpu(), guaranteed to run with migration disabled,
891 * using smp_processor_id() is OK.
892 */
3f518509
MW		 893static void mvpp2_interrupts_mask(void *arg)
894{
895 struct mvpp2_port *port = arg;
896
a786841d
TP		 897 mvpp2_percpu_write(port->priv, smp_processor_id(),
898 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
3f518509
MW		 899}
900
e0af22d9
TP		 901/* Unmask the current CPU's Rx/Tx interrupts.
902 * Called by on_each_cpu(), guaranteed to run with migration disabled,
903 * using smp_processor_id() is OK.
904 */
3f518509
MW		 905static void mvpp2_interrupts_unmask(void *arg)
906{
907 struct mvpp2_port *port = arg;
213f428f
TP		 908 u32 val;
909
910 val = MVPP2_CAUSE_MISC_SUM_MASK |
911 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
912 if (port->has_tx_irqs)
913 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3f518509 914
a786841d 915 mvpp2_percpu_write(port->priv, smp_processor_id(),
213f428f
TP		 916 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
917}
918
919static void
920mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
921{
922 u32 val;
923 int i;
924
925 if (port->priv->hw_version != MVPP22)
926 return;
927
928 if (mask)
929 val = 0;
930 else
931 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
932
933 for (i = 0; i < port->nqvecs; i++) {
934 struct mvpp2_queue_vector *v = port->qvecs + i;
935
936 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
937 continue;
938
939 mvpp2_percpu_write(port->priv, v->sw_thread_id,
940 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
941 }
3f518509
MW		 942}
943
944/* Port configuration routines */
945
f84bf386
AT		 946static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
947{
948 struct mvpp2 *priv = port->priv;
949 u32 val;
950
951 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
952 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
953 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
954
955 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
956 if (port->gop_id == 2)
957 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
958 else if (port->gop_id == 3)
959 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
960 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
961}
962
963static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
964{
965 struct mvpp2 *priv = port->priv;
966 u32 val;
967
968 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
969 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
970 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
971 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
972
973 if (port->gop_id > 1) {
974 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
975 if (port->gop_id == 2)
976 val &= ~GENCONF_CTRL0_PORT0_RGMII;
977 else if (port->gop_id == 3)
978 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
979 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
980 }
981}
982
983static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
984{
985 struct mvpp2 *priv = port->priv;
986 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
987 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
988 u32 val;
989
990 /* XPCS */
991 val = readl(xpcs + MVPP22_XPCS_CFG0);
992 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
993 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
994 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
995 writel(val, xpcs + MVPP22_XPCS_CFG0);
996
997 /* MPCS */
998 val = readl(mpcs + MVPP22_MPCS_CTRL);
999 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1000 writel(val, mpcs + MVPP22_MPCS_CTRL);
1001
1002 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1003 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |
1004 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1005 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1006 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1007
1008 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1009 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;
1010 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1011}
1012
1013static int mvpp22_gop_init(struct mvpp2_port *port)
1014{
1015 struct mvpp2 *priv = port->priv;
1016 u32 val;
1017
1018 if (!priv->sysctrl_base)
1019 return 0;
1020
1021 switch (port->phy_interface) {
1022 case PHY_INTERFACE_MODE_RGMII:
1023 case PHY_INTERFACE_MODE_RGMII_ID:
1024 case PHY_INTERFACE_MODE_RGMII_RXID:
1025 case PHY_INTERFACE_MODE_RGMII_TXID:
1026 if (port->gop_id == 0)
1027 goto invalid_conf;
1028 mvpp22_gop_init_rgmii(port);
1029 break;
1030 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a 1031 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 1032 case PHY_INTERFACE_MODE_2500BASEX:
f84bf386
AT		 1033 mvpp22_gop_init_sgmii(port);
1034 break;
1035 case PHY_INTERFACE_MODE_10GKR:
1036 if (port->gop_id != 0)
1037 goto invalid_conf;
1038 mvpp22_gop_init_10gkr(port);
1039 break;
1040 default:
1041 goto unsupported_conf;
1042 }
1043
1044 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1045 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1046 GENCONF_PORT_CTRL1_EN(port->gop_id);
1047 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1048
1049 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1050 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1051 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1052
1053 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1054 val |= GENCONF_SOFT_RESET1_GOP;
1055 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1056
1057unsupported_conf:
1058 return 0;
1059
1060invalid_conf:
1061 netdev_err(port->dev, "Invalid port configuration\n");
1062 return -EINVAL;
1063}
1064
fd3651b2
AT		 1065static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1066{
1067 u32 val;
1068
1069 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 1070 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1071 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1072 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 1073 /* Enable the GMAC link status irq for this port */
1074 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1075 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1076 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1077 }
1078
1079 if (port->gop_id == 0) {
1080 /* Enable the XLG/GIG irqs for this port */
1081 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1082 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
1083 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1084 else
1085 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1086 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1087 }
1088}
1089
1090static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1091{
1092 u32 val;
1093
1094 if (port->gop_id == 0) {
1095 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1096 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
a3302baa 1097 MVPP22_XLG_EXT_INT_MASK_GIG);
fd3651b2
AT		 1098 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1099 }
1100
1101 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 1102 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1103 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1104 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 1105 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1106 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1107 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1108 }
1109}
1110
1111static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1112{
1113 u32 val;
1114
1115 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 1116 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1117 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1118 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 1119 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1120 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1121 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1122 }
1123
1124 if (port->gop_id == 0) {
1125 val = readl(port->base + MVPP22_XLG_INT_MASK);
1126 val |= MVPP22_XLG_INT_MASK_LINK;
1127 writel(val, port->base + MVPP22_XLG_INT_MASK);
1128 }
1129
1130 mvpp22_gop_unmask_irq(port);
1131}
1132
a6fe31de
AT		 1133/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1134 *
1135 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1136 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1137 * differ.
1138 *
1139 * The COMPHY configures the serdes lanes regardless of the actual use of the
1140 * lanes by the physical layer. This is why configurations like
1141 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1142 */
542897d9
AT		 1143static int mvpp22_comphy_init(struct mvpp2_port *port)
1144{
1145 enum phy_mode mode;
1146 int ret;
1147
1148 if (!port->comphy)
1149 return 0;
1150
1151 switch (port->phy_interface) {
1152 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a 1153 case PHY_INTERFACE_MODE_1000BASEX:
542897d9
AT		 1154 mode = PHY_MODE_SGMII;
1155 break;
a6fe31de
AT		 1156 case PHY_INTERFACE_MODE_2500BASEX:
1157 mode = PHY_MODE_2500SGMII;
1158 break;
542897d9
AT		 1159 case PHY_INTERFACE_MODE_10GKR:
1160 mode = PHY_MODE_10GKR;
1161 break;
1162 default:
1163 return -EINVAL;
1164 }
1165
1166 ret = phy_set_mode(port->comphy, mode);
1167 if (ret)
1168 return ret;
1169
1170 return phy_power_on(port->comphy);
1171}
1172
3f518509
MW		 1173static void mvpp2_port_enable(struct mvpp2_port *port)
1174{
1175 u32 val;
1176
725757ae
AT		 1177 /* Only GOP port 0 has an XLG MAC */
1178 if (port->gop_id == 0 &&
1179 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1180 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1181 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1182 val |= MVPP22_XLG_CTRL0_PORT_EN |
1183 MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1184 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1185 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1186 } else {
1187 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1188 val |= MVPP2_GMAC_PORT_EN_MASK;
1189 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1190 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1191 }
3f518509
MW		 1192}
1193
1194static void mvpp2_port_disable(struct mvpp2_port *port)
1195{
1196 u32 val;
1197
725757ae
AT		 1198 /* Only GOP port 0 has an XLG MAC */
1199 if (port->gop_id == 0 &&
1200 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1201 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1202 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4bb04326
AT		 1203 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1204 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1205
1206 /* Disable & reset should be done separately */
1207 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
725757ae
AT		 1208 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1209 } else {
1210 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1211 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1212 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1213 }
3f518509
MW		 1214}
1215
1216/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1217static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1218{
1219 u32 val;
1220
1221 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1222 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1223 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1224}
1225
1226/* Configure loopback port */
4bb04326
AT		 1227static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1228 const struct phylink_link_state *state)
3f518509
MW		 1229{
1230 u32 val;
1231
1232 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1233
4bb04326 1234 if (state->speed == 1000)
3f518509
MW		 1235 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1236 else
1237 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1238
d97c9f4a 1239 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1240 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1241 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
3f518509
MW		 1242 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1243 else
1244 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1245
1246 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1247}
1248
118d6298
MR		 1249struct mvpp2_ethtool_counter {
1250 unsigned int offset;
1251 const char string[ETH_GSTRING_LEN];
1252 bool reg_is_64b;
1253};
1254
1255static u64 mvpp2_read_count(struct mvpp2_port *port,
1256 const struct mvpp2_ethtool_counter *counter)
1257{
1258 u64 val;
1259
1260 val = readl(port->stats_base + counter->offset);
1261 if (counter->reg_is_64b)
1262 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1263
1264 return val;
1265}
1266
1267/* Due to the fact that software statistics and hardware statistics are, by
1268 * design, incremented at different moments in the chain of packet processing,
1269 * it is very likely that incoming packets could have been dropped after being
1270 * counted by hardware but before reaching software statistics (most probably
1271 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1272 * are added in between as well as TSO skb will be split and header bytes added.
1273 * Hence, statistics gathered from userspace with ifconfig (software) and
1274 * ethtool (hardware) cannot be compared.
1275 */
1276static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = {
1277 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1278 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1279 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1280 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1281 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1282 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1283 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1284 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1285 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1286 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1287 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1288 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1289 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1290 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1291 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1292 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1293 { MVPP2_MIB_FC_SENT, "fc_sent" },
1294 { MVPP2_MIB_FC_RCVD, "fc_received" },
1295 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1296 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1297 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1298 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1299 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1300 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1301 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1302 { MVPP2_MIB_COLLISION, "collision" },
1303 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1304};
1305
1306static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1307 u8 *data)
1308{
1309 if (sset == ETH_SS_STATS) {
1310 int i;
1311
1312 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1313 memcpy(data + i * ETH_GSTRING_LEN,
1314 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN);
1315 }
1316}
1317
1318static void mvpp2_gather_hw_statistics(struct work_struct *work)
1319{
1320 struct delayed_work *del_work = to_delayed_work(work);
e5c500eb
MR		 1321 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1322 stats_work);
118d6298 1323 u64 *pstats;
e5c500eb 1324 int i;
118d6298 1325
e5c500eb 1326 mutex_lock(&port->gather_stats_lock);
118d6298 1327
e5c500eb
MR		 1328 pstats = port->ethtool_stats;
1329 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1330 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
118d6298
MR		 1331
1332 /* No need to read again the counters right after this function if it
1333 * was called asynchronously by the user (ie. use of ethtool).
1334 */
e5c500eb
MR		 1335 cancel_delayed_work(&port->stats_work);
1336 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
118d6298
MR		 1337 MVPP2_MIB_COUNTERS_STATS_DELAY);
1338
e5c500eb 1339 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1340}
1341
1342static void mvpp2_ethtool_get_stats(struct net_device *dev,
1343 struct ethtool_stats *stats, u64 *data)
1344{
1345 struct mvpp2_port *port = netdev_priv(dev);
1346
e5c500eb
MR		 1347 /* Update statistics for the given port, then take the lock to avoid
1348 * concurrent accesses on the ethtool_stats structure during its copy.
1349 */
1350 mvpp2_gather_hw_statistics(&port->stats_work.work);
118d6298 1351
e5c500eb 1352 mutex_lock(&port->gather_stats_lock);
118d6298
MR		 1353 memcpy(data, port->ethtool_stats,
1354 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs));
e5c500eb 1355 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1356}
1357
1358static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1359{
1360 if (sset == ETH_SS_STATS)
1361 return ARRAY_SIZE(mvpp2_ethtool_regs);
1362
1363 return -EOPNOTSUPP;
1364}
1365
3f518509
MW		 1366static void mvpp2_port_reset(struct mvpp2_port *port)
1367{
1368 u32 val;
118d6298
MR		 1369 unsigned int i;
1370
1371 /* Read the GOP statistics to reset the hardware counters */
1372 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1373 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
3f518509
MW		 1374
1375 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1376 ~MVPP2_GMAC_PORT_RESET_MASK;
1377 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1378
1379 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1380 MVPP2_GMAC_PORT_RESET_MASK)
1381 continue;
1382}
1383
1384/* Change maximum receive size of the port */
1385static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1386{
1387 u32 val;
1388
1389 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1390 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1391 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1392 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1393 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1394}
1395
76eb1b1d
SC		 1396/* Change maximum receive size of the port */
1397static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1398{
1399 u32 val;
1400
1401 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1402 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1403 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
ec15ecde 1404 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
76eb1b1d
SC		 1405 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1406}
1407
3f518509
MW		 1408/* Set defaults to the MVPP2 port */
1409static void mvpp2_defaults_set(struct mvpp2_port *port)
1410{
1411 int tx_port_num, val, queue, ptxq, lrxq;
1412
3d9017d9 1413 if (port->priv->hw_version == MVPP21) {
3d9017d9
TP		 1414 /* Update TX FIFO MIN Threshold */
1415 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1416 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1417 /* Min. TX threshold must be less than minimal packet length */
1418 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1419 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1420 }
3f518509
MW		 1421
1422 /* Disable Legacy WRR, Disable EJP, Release from reset */
1423 tx_port_num = mvpp2_egress_port(port);
1424 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1425 tx_port_num);
1426 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1427
1428 /* Close bandwidth for all queues */
1429 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
1430 ptxq = mvpp2_txq_phys(port->id, queue);
1431 mvpp2_write(port->priv,
1432 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
1433 }
1434
1435 /* Set refill period to 1 usec, refill tokens
1436 * and bucket size to maximum
1437 */
1438 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1439 port->priv->tclk / USEC_PER_SEC);
1440 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1441 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1442 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1443 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1444 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1445 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1446 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1447
1448 /* Set MaximumLowLatencyPacketSize value to 256 */
1449 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1450 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1451 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1452
1453 /* Enable Rx cache snoop */
09f83975 1454 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1455 queue = port->rxqs[lrxq]->id;
1456 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1457 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1458 MVPP2_SNOOP_BUF_HDR_MASK;
1459 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1460 }
1461
1462 /* At default, mask all interrupts to all present cpus */
1463 mvpp2_interrupts_disable(port);
1464}
1465
1466/* Enable/disable receiving packets */
1467static void mvpp2_ingress_enable(struct mvpp2_port *port)
1468{
1469 u32 val;
1470 int lrxq, queue;
1471
09f83975 1472 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1473 queue = port->rxqs[lrxq]->id;
1474 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1475 val &= ~MVPP2_RXQ_DISABLE_MASK;
1476 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1477 }
1478}
1479
1480static void mvpp2_ingress_disable(struct mvpp2_port *port)
1481{
1482 u32 val;
1483 int lrxq, queue;
1484
09f83975 1485 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1486 queue = port->rxqs[lrxq]->id;
1487 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1488 val |= MVPP2_RXQ_DISABLE_MASK;
1489 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1490 }
1491}
1492
1493/* Enable transmit via physical egress queue
1494 * - HW starts take descriptors from DRAM
1495 */
1496static void mvpp2_egress_enable(struct mvpp2_port *port)
1497{
1498 u32 qmap;
1499 int queue;
1500 int tx_port_num = mvpp2_egress_port(port);
1501
1502 /* Enable all initialized TXs. */
1503 qmap = 0;
09f83975 1504 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1505 struct mvpp2_tx_queue *txq = port->txqs[queue];
1506
dbbb2f03 1507 if (txq->descs)
3f518509
MW		 1508 qmap |= (1 << queue);
1509 }
1510
1511 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1512 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1513}
1514
1515/* Disable transmit via physical egress queue
1516 * - HW doesn't take descriptors from DRAM
1517 */
1518static void mvpp2_egress_disable(struct mvpp2_port *port)
1519{
1520 u32 reg_data;
1521 int delay;
1522 int tx_port_num = mvpp2_egress_port(port);
1523
1524 /* Issue stop command for active channels only */
1525 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1526 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1527 MVPP2_TXP_SCHED_ENQ_MASK;
1528 if (reg_data != 0)
1529 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1530 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1531
1532 /* Wait for all Tx activity to terminate. */
1533 delay = 0;
1534 do {
1535 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1536 netdev_warn(port->dev,
1537 "Tx stop timed out, status=0x%08x\n",
1538 reg_data);
1539 break;
1540 }
1541 mdelay(1);
1542 delay++;
1543
1544 /* Check port TX Command register that all
1545 * Tx queues are stopped
1546 */
1547 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1548 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1549}
1550
1551/* Rx descriptors helper methods */
1552
1553/* Get number of Rx descriptors occupied by received packets */
1554static inline int
1555mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1556{
1557 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1558
1559 return val & MVPP2_RXQ_OCCUPIED_MASK;
1560}
1561
1562/* Update Rx queue status with the number of occupied and available
1563 * Rx descriptor slots.
1564 */
1565static inline void
1566mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1567 int used_count, int free_count)
1568{
1569 /* Decrement the number of used descriptors and increment count
1570 * increment the number of free descriptors.
1571 */
1572 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1573
1574 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1575}
1576
1577/* Get pointer to next RX descriptor to be processed by SW */
1578static inline struct mvpp2_rx_desc *
1579mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1580{
1581 int rx_desc = rxq->next_desc_to_proc;
1582
1583 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1584 prefetch(rxq->descs + rxq->next_desc_to_proc);
1585 return rxq->descs + rx_desc;
1586}
1587
1588/* Set rx queue offset */
1589static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1590 int prxq, int offset)
1591{
1592 u32 val;
1593
1594 /* Convert offset from bytes to units of 32 bytes */
1595 offset = offset >> 5;
1596
1597 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1598 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1599
1600 /* Offset is in */
1601 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1602 MVPP2_RXQ_PACKET_OFFSET_MASK);
1603
1604 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1605}
1606
3f518509
MW		 1607/* Tx descriptors helper methods */
1608
3f518509
MW		 1609/* Get pointer to next Tx descriptor to be processed (send) by HW */
1610static struct mvpp2_tx_desc *
1611mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1612{
1613 int tx_desc = txq->next_desc_to_proc;
1614
1615 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1616 return txq->descs + tx_desc;
1617}
1618
e0af22d9
TP		 1619/* Update HW with number of aggregated Tx descriptors to be sent
1620 *
1621 * Called only from mvpp2_tx(), so migration is disabled, using
1622 * smp_processor_id() is OK.
1623 */
3f518509
MW		 1624static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1625{
1626 /* aggregated access - relevant TXQ number is written in TX desc */
a786841d
TP		 1627 mvpp2_percpu_write(port->priv, smp_processor_id(),
1628 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3f518509
MW		 1629}
1630
3f518509
MW		 1631/* Check if there are enough free descriptors in aggregated txq.
1632 * If not, update the number of occupied descriptors and repeat the check.
e0af22d9
TP		 1633 *
1634 * Called only from mvpp2_tx(), so migration is disabled, using
1635 * smp_processor_id() is OK.
3f518509
MW		 1636 */
1637static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
1638 struct mvpp2_tx_queue *aggr_txq, int num)
1639{
02856a3b 1640 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
3f518509
MW		 1641 /* Update number of occupied aggregated Tx descriptors */
1642 int cpu = smp_processor_id();
cdcfeb0f
YM		 1643 u32 val = mvpp2_read_relaxed(priv,
1644 MVPP2_AGGR_TXQ_STATUS_REG(cpu));
3f518509
MW		 1645
1646 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
3f518509 1647
914365f1
YM		 1648 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1649 return -ENOMEM;
1650 }
3f518509
MW		 1651 return 0;
1652}
1653
e0af22d9
TP		 1654/* Reserved Tx descriptors allocation request
1655 *
1656 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1657 * only by mvpp2_tx(), so migration is disabled, using
1658 * smp_processor_id() is OK.
1659 */
3f518509
MW		 1660static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv,
1661 struct mvpp2_tx_queue *txq, int num)
1662{
1663 u32 val;
a786841d 1664 int cpu = smp_processor_id();
3f518509
MW		 1665
1666 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
cdcfeb0f 1667 mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val);
3f518509 1668
cdcfeb0f 1669 val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG);
3f518509
MW		 1670
1671 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1672}
1673
1674/* Check if there are enough reserved descriptors for transmission.
1675 * If not, request chunk of reserved descriptors and check again.
1676 */
1677static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv,
1678 struct mvpp2_tx_queue *txq,
1679 struct mvpp2_txq_pcpu *txq_pcpu,
1680 int num)
1681{
1682 int req, cpu, desc_count;
1683
1684 if (txq_pcpu->reserved_num >= num)
1685 return 0;
1686
1687 /* Not enough descriptors reserved! Update the reserved descriptor
1688 * count and check again.
1689 */
1690
1691 desc_count = 0;
1692 /* Compute total of used descriptors */
1693 for_each_present_cpu(cpu) {
1694 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1695
1696 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu);
1697 desc_count += txq_pcpu_aux->count;
1698 desc_count += txq_pcpu_aux->reserved_num;
1699 }
1700
1701 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1702 desc_count += req;
1703
1704 if (desc_count >
1705 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK)))
1706 return -ENOMEM;
1707
1708 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req);
1709
a3302baa 1710 /* OK, the descriptor could have been updated: check again. */
3f518509
MW		 1711 if (txq_pcpu->reserved_num < num)
1712 return -ENOMEM;
1713 return 0;
1714}
1715
1716/* Release the last allocated Tx descriptor. Useful to handle DMA
1717 * mapping failures in the Tx path.
1718 */
1719static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1720{
1721 if (txq->next_desc_to_proc == 0)
1722 txq->next_desc_to_proc = txq->last_desc - 1;
1723 else
1724 txq->next_desc_to_proc--;
1725}
1726
1727/* Set Tx descriptors fields relevant for CSUM calculation */
1728static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
1729 int ip_hdr_len, int l4_proto)
1730{
1731 u32 command;
1732
1733 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1734 * G_L4_chk, L4_type required only for checksum calculation
1735 */
1736 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1737 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1738 command |= MVPP2_TXD_IP_CSUM_DISABLE;
1739
dc734dbe 1740 if (l3_proto == htons(ETH_P_IP)) {
3f518509
MW		 1741 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
1742 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
1743 } else {
1744 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
1745 }
1746
1747 if (l4_proto == IPPROTO_TCP) {
1748 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
1749 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1750 } else if (l4_proto == IPPROTO_UDP) {
1751 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
1752 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1753 } else {
1754 command |= MVPP2_TXD_L4_CSUM_NOT;
1755 }
1756
1757 return command;
1758}
1759
1760/* Get number of sent descriptors and decrement counter.
1761 * The number of sent descriptors is returned.
1762 * Per-CPU access
e0af22d9
TP		 1763 *
1764 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1765 * (migration disabled) and from the TX completion tasklet (migration
1766 * disabled) so using smp_processor_id() is OK.
3f518509
MW		 1767 */
1768static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1769 struct mvpp2_tx_queue *txq)
1770{
1771 u32 val;
1772
1773 /* Reading status reg resets transmitted descriptor counter */
cdcfeb0f
YM		 1774 val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(),
1775 MVPP2_TXQ_SENT_REG(txq->id));
3f518509
MW		 1776
1777 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1778 MVPP2_TRANSMITTED_COUNT_OFFSET;
1779}
1780
e0af22d9
TP		 1781/* Called through on_each_cpu(), so runs on all CPUs, with migration
1782 * disabled, therefore using smp_processor_id() is OK.
1783 */
3f518509
MW		 1784static void mvpp2_txq_sent_counter_clear(void *arg)
1785{
1786 struct mvpp2_port *port = arg;
1787 int queue;
1788
09f83975 1789 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1790 int id = port->txqs[queue]->id;
1791
a786841d
TP		 1792 mvpp2_percpu_read(port->priv, smp_processor_id(),
1793 MVPP2_TXQ_SENT_REG(id));
3f518509
MW		 1794 }
1795}
1796
1797/* Set max sizes for Tx queues */
1798static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1799{
1800 u32 val, size, mtu;
1801 int txq, tx_port_num;
1802
1803 mtu = port->pkt_size * 8;
1804 if (mtu > MVPP2_TXP_MTU_MAX)
1805 mtu = MVPP2_TXP_MTU_MAX;
1806
1807 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1808 mtu = 3 * mtu;
1809
1810 /* Indirect access to registers */
1811 tx_port_num = mvpp2_egress_port(port);
1812 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1813
1814 /* Set MTU */
1815 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1816 val &= ~MVPP2_TXP_MTU_MAX;
1817 val |= mtu;
1818 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1819
1820 /* TXP token size and all TXQs token size must be larger that MTU */
1821 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1822 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1823 if (size < mtu) {
1824 size = mtu;
1825 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1826 val |= size;
1827 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1828 }
1829
09f83975 1830 for (txq = 0; txq < port->ntxqs; txq++) {
3f518509
MW		 1831 val = mvpp2_read(port->priv,
1832 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1833 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1834
1835 if (size < mtu) {
1836 size = mtu;
1837 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1838 val |= size;
1839 mvpp2_write(port->priv,
1840 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
1841 val);
1842 }
1843 }
1844}
1845
1846/* Set the number of packets that will be received before Rx interrupt
1847 * will be generated by HW.
1848 */
1849static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
d63f9e41 1850 struct mvpp2_rx_queue *rxq)
3f518509 1851{
a704bb5c 1852 int cpu = get_cpu();
a786841d 1853
f8b0d5f8
TP		 1854 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
1855 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
3f518509 1856
a786841d
TP		 1857 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
1858 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,
1859 rxq->pkts_coal);
a704bb5c
TP		 1860
1861 put_cpu();
3f518509
MW		 1862}
1863
213f428f
TP		 1864/* For some reason in the LSP this is done on each CPU. Why ? */
1865static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
1866 struct mvpp2_tx_queue *txq)
1867{
1868 int cpu = get_cpu();
1869 u32 val;
1870
1871 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
1872 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
1873
1874 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1875 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
1876 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val);
1877
1878 put_cpu();
1879}
1880
ab42676a
TP		 1881static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
1882{
1883 u64 tmp = (u64)clk_hz * usec;
1884
1885 do_div(tmp, USEC_PER_SEC);
1886
1887 return tmp > U32_MAX ? U32_MAX : tmp;
1888}
1889
1890static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
1891{
1892 u64 tmp = (u64)cycles * USEC_PER_SEC;
1893
1894 do_div(tmp, clk_hz);
1895
1896 return tmp > U32_MAX ? U32_MAX : tmp;
1897}
1898
3f518509
MW		 1899/* Set the time delay in usec before Rx interrupt */
1900static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
d63f9e41 1901 struct mvpp2_rx_queue *rxq)
3f518509 1902{
ab42676a
TP		 1903 unsigned long freq = port->priv->tclk;
1904 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1905
1906 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
1907 rxq->time_coal =
1908 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
1909
1910 /* re-evaluate to get actual register value */
1911 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1912 }
3f518509 1913
3f518509 1914 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
3f518509
MW		 1915}
1916
213f428f
TP		 1917static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
1918{
1919 unsigned long freq = port->priv->tclk;
1920 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1921
1922 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
1923 port->tx_time_coal =
1924 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
1925
1926 /* re-evaluate to get actual register value */
1927 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1928 }
1929
1930 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
1931}
1932
3f518509
MW		 1933/* Free Tx queue skbuffs */
1934static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
1935 struct mvpp2_tx_queue *txq,
1936 struct mvpp2_txq_pcpu *txq_pcpu, int num)
1937{
1938 int i;
1939
1940 for (i = 0; i < num; i++) {
8354491c
TP		 1941 struct mvpp2_txq_pcpu_buf *tx_buf =
1942 txq_pcpu->buffs + txq_pcpu->txq_get_index;
3f518509 1943
20920267
AT		 1944 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
1945 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
1946 tx_buf->size, DMA_TO_DEVICE);
36fb7435
TP		 1947 if (tx_buf->skb)
1948 dev_kfree_skb_any(tx_buf->skb);
1949
1950 mvpp2_txq_inc_get(txq_pcpu);
3f518509
MW		 1951 }
1952}
1953
1954static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
1955 u32 cause)
1956{
1957 int queue = fls(cause) - 1;
1958
1959 return port->rxqs[queue];
1960}
1961
1962static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
1963 u32 cause)
1964{
edc660fa 1965 int queue = fls(cause) - 1;
3f518509
MW		 1966
1967 return port->txqs[queue];
1968}
1969
1970/* Handle end of transmission */
1971static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
1972 struct mvpp2_txq_pcpu *txq_pcpu)
1973{
1974 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
1975 int tx_done;
1976
1977 if (txq_pcpu->cpu != smp_processor_id())
1978 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
1979
1980 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
1981 if (!tx_done)
1982 return;
1983 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
1984
1985 txq_pcpu->count -= tx_done;
1986
1987 if (netif_tx_queue_stopped(nq))
1d17db08 1988 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
3f518509
MW		 1989 netif_tx_wake_queue(nq);
1990}
1991
213f428f
TP		 1992static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
1993 int cpu)
edc660fa
MW		 1994{
1995 struct mvpp2_tx_queue *txq;
1996 struct mvpp2_txq_pcpu *txq_pcpu;
1997 unsigned int tx_todo = 0;
1998
1999 while (cause) {
2000 txq = mvpp2_get_tx_queue(port, cause);
2001 if (!txq)
2002 break;
2003
213f428f 2004 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
edc660fa
MW		 2005
2006 if (txq_pcpu->count) {
2007 mvpp2_txq_done(port, txq, txq_pcpu);
2008 tx_todo += txq_pcpu->count;
2009 }
2010
2011 cause &= ~(1 << txq->log_id);
2012 }
2013 return tx_todo;
2014}
2015
3f518509
MW		 2016/* Rx/Tx queue initialization/cleanup methods */
2017
2018/* Allocate and initialize descriptors for aggr TXQ */
2019static int mvpp2_aggr_txq_init(struct platform_device *pdev,
85affd7e 2020 struct mvpp2_tx_queue *aggr_txq, int cpu,
3f518509
MW		 2021 struct mvpp2 *priv)
2022{
b02f31fb
TP		 2023 u32 txq_dma;
2024
3f518509 2025 /* Allocate memory for TX descriptors */
a154f8e3 2026 aggr_txq->descs = dma_zalloc_coherent(&pdev->dev,
85affd7e 2027 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
20396136 2028 &aggr_txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2029 if (!aggr_txq->descs)
2030 return -ENOMEM;
2031
02856a3b 2032 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
3f518509
MW		 2033
2034 /* Aggr TXQ no reset WA */
2035 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2036 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
2037
b02f31fb
TP		 2038 /* Set Tx descriptors queue starting address indirect
2039 * access
2040 */
2041 if (priv->hw_version == MVPP21)
2042 txq_dma = aggr_txq->descs_dma;
2043 else
2044 txq_dma = aggr_txq->descs_dma >>
2045 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2046
2047 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
85affd7e
AT		 2048 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu),
2049 MVPP2_AGGR_TXQ_SIZE);
3f518509
MW		 2050
2051 return 0;
2052}
2053
2054/* Create a specified Rx queue */
2055static int mvpp2_rxq_init(struct mvpp2_port *port,
2056 struct mvpp2_rx_queue *rxq)
2057
2058{
b02f31fb 2059 u32 rxq_dma;
a786841d 2060 int cpu;
b02f31fb 2061
3f518509
MW		 2062 rxq->size = port->rx_ring_size;
2063
2064 /* Allocate memory for RX descriptors */
2065 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2066 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2067 &rxq->descs_dma, GFP_KERNEL);
3f518509
MW		 2068 if (!rxq->descs)
2069 return -ENOMEM;
2070
3f518509
MW		 2071 rxq->last_desc = rxq->size - 1;
2072
2073 /* Zero occupied and non-occupied counters - direct access */
2074 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2075
2076 /* Set Rx descriptors queue starting address - indirect access */
a704bb5c 2077 cpu = get_cpu();
a786841d 2078 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
b02f31fb
TP		 2079 if (port->priv->hw_version == MVPP21)
2080 rxq_dma = rxq->descs_dma;
2081 else
2082 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
a786841d
TP		 2083 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2084 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2085 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);
a704bb5c 2086 put_cpu();
3f518509
MW		 2087
2088 /* Set Offset */
2089 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2090
2091 /* Set coalescing pkts and time */
d63f9e41
TP		 2092 mvpp2_rx_pkts_coal_set(port, rxq);
2093 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 2094
2095 /* Add number of descriptors ready for receiving packets */
2096 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2097
2098 return 0;
2099}
2100
2101/* Push packets received by the RXQ to BM pool */
2102static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2103 struct mvpp2_rx_queue *rxq)
2104{
2105 int rx_received, i;
2106
2107 rx_received = mvpp2_rxq_received(port, rxq->id);
2108 if (!rx_received)
2109 return;
2110
2111 for (i = 0; i < rx_received; i++) {
2112 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
56b8aae9
TP		 2113 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2114 int pool;
2115
2116 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2117 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2118
7d7627ba 2119 mvpp2_bm_pool_put(port, pool,
ac3dd277
TP		 2120 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2121 mvpp2_rxdesc_cookie_get(port, rx_desc));
3f518509
MW		 2122 }
2123 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2124}
2125
2126/* Cleanup Rx queue */
2127static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2128 struct mvpp2_rx_queue *rxq)
2129{
a786841d
TP		 2130 int cpu;
2131
3f518509
MW		 2132 mvpp2_rxq_drop_pkts(port, rxq);
2133
2134 if (rxq->descs)
2135 dma_free_coherent(port->dev->dev.parent,
2136 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2137 rxq->descs,
20396136 2138 rxq->descs_dma);
3f518509
MW		 2139
2140 rxq->descs = NULL;
2141 rxq->last_desc = 0;
2142 rxq->next_desc_to_proc = 0;
20396136 2143 rxq->descs_dma = 0;
3f518509
MW		 2144
2145 /* Clear Rx descriptors queue starting address and size;
2146 * free descriptor number
2147 */
2148 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
a704bb5c 2149 cpu = get_cpu();
a786841d
TP		 2150 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
2151 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);
2152 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);
a704bb5c 2153 put_cpu();
3f518509
MW		 2154}
2155
2156/* Create and initialize a Tx queue */
2157static int mvpp2_txq_init(struct mvpp2_port *port,
2158 struct mvpp2_tx_queue *txq)
2159{
2160 u32 val;
2161 int cpu, desc, desc_per_txq, tx_port_num;
2162 struct mvpp2_txq_pcpu *txq_pcpu;
2163
2164 txq->size = port->tx_ring_size;
2165
2166 /* Allocate memory for Tx descriptors */
2167 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2168 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2169 &txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2170 if (!txq->descs)
2171 return -ENOMEM;
2172
3f518509
MW		 2173 txq->last_desc = txq->size - 1;
2174
2175 /* Set Tx descriptors queue starting address - indirect access */
a704bb5c 2176 cpu = get_cpu();
a786841d
TP		 2177 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2178 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,
2179 txq->descs_dma);
2180 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG,
2181 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2182 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0);
2183 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG,
2184 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2185 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG);
3f518509 2186 val &= ~MVPP2_TXQ_PENDING_MASK;
a786841d 2187 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val);
3f518509
MW		 2188
2189 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2190 * for each existing TXQ.
2191 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
a3302baa 2192 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3f518509
MW		 2193 */
2194 desc_per_txq = 16;
2195 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2196 (txq->log_id * desc_per_txq);
2197
a786841d
TP		 2198 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,
2199 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2200 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
a704bb5c 2201 put_cpu();
3f518509
MW		 2202
2203 /* WRR / EJP configuration - indirect access */
2204 tx_port_num = mvpp2_egress_port(port);
2205 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2206
2207 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2208 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2209 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2210 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2211 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2212
2213 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2214 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2215 val);
2216
2217 for_each_present_cpu(cpu) {
2218 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2219 txq_pcpu->size = txq->size;
02c91ece
ME		 2220 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2221 sizeof(*txq_pcpu->buffs),
2222 GFP_KERNEL);
8354491c 2223 if (!txq_pcpu->buffs)
ba2d8d88 2224 return -ENOMEM;
3f518509
MW		 2225
2226 txq_pcpu->count = 0;
2227 txq_pcpu->reserved_num = 0;
2228 txq_pcpu->txq_put_index = 0;
2229 txq_pcpu->txq_get_index = 0;
b70d4a51 2230 txq_pcpu->tso_headers = NULL;
186cd4d4 2231
1d17db08
AT		 2232 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2233 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2234
186cd4d4
AT		 2235 txq_pcpu->tso_headers =
2236 dma_alloc_coherent(port->dev->dev.parent,
822eaf7c 2237 txq_pcpu->size * TSO_HEADER_SIZE,
186cd4d4
AT		 2238 &txq_pcpu->tso_headers_dma,
2239 GFP_KERNEL);
2240 if (!txq_pcpu->tso_headers)
ba2d8d88 2241 return -ENOMEM;
3f518509
MW		 2242 }
2243
2244 return 0;
2245}
2246
2247/* Free allocated TXQ resources */
2248static void mvpp2_txq_deinit(struct mvpp2_port *port,
2249 struct mvpp2_tx_queue *txq)
2250{
2251 struct mvpp2_txq_pcpu *txq_pcpu;
2252 int cpu;
2253
2254 for_each_present_cpu(cpu) {
2255 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
8354491c 2256 kfree(txq_pcpu->buffs);
186cd4d4 2257
b70d4a51
AT		 2258 if (txq_pcpu->tso_headers)
2259 dma_free_coherent(port->dev->dev.parent,
2260 txq_pcpu->size * TSO_HEADER_SIZE,
2261 txq_pcpu->tso_headers,
2262 txq_pcpu->tso_headers_dma);
2263
2264 txq_pcpu->tso_headers = NULL;
3f518509
MW		 2265 }
2266
2267 if (txq->descs)
2268 dma_free_coherent(port->dev->dev.parent,
2269 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2270 txq->descs, txq->descs_dma);
3f518509
MW		 2271
2272 txq->descs = NULL;
2273 txq->last_desc = 0;
2274 txq->next_desc_to_proc = 0;
20396136 2275 txq->descs_dma = 0;
3f518509
MW		 2276
2277 /* Set minimum bandwidth for disabled TXQs */
2278 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
2279
2280 /* Set Tx descriptors queue starting address and size */
a704bb5c 2281 cpu = get_cpu();
a786841d
TP		 2282 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2283 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);
2284 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);
a704bb5c 2285 put_cpu();
3f518509
MW		 2286}
2287
2288/* Cleanup Tx ports */
2289static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2290{
2291 struct mvpp2_txq_pcpu *txq_pcpu;
2292 int delay, pending, cpu;
2293 u32 val;
2294
a704bb5c 2295 cpu = get_cpu();
a786841d
TP		 2296 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2297 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);
3f518509 2298 val |= MVPP2_TXQ_DRAIN_EN_MASK;
a786841d 2299 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
3f518509
MW		 2300
2301 /* The napi queue has been stopped so wait for all packets
2302 * to be transmitted.
2303 */
2304 delay = 0;
2305 do {
2306 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2307 netdev_warn(port->dev,
2308 "port %d: cleaning queue %d timed out\n",
2309 port->id, txq->log_id);
2310 break;
2311 }
2312 mdelay(1);
2313 delay++;
2314
a786841d
TP		 2315 pending = mvpp2_percpu_read(port->priv, cpu,
2316 MVPP2_TXQ_PENDING_REG);
2317 pending &= MVPP2_TXQ_PENDING_MASK;
3f518509
MW		 2318 } while (pending);
2319
2320 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
a786841d 2321 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
a704bb5c 2322 put_cpu();
3f518509
MW		 2323
2324 for_each_present_cpu(cpu) {
2325 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2326
2327 /* Release all packets */
2328 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2329
2330 /* Reset queue */
2331 txq_pcpu->count = 0;
2332 txq_pcpu->txq_put_index = 0;
2333 txq_pcpu->txq_get_index = 0;
2334 }
2335}
2336
2337/* Cleanup all Tx queues */
2338static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2339{
2340 struct mvpp2_tx_queue *txq;
2341 int queue;
2342 u32 val;
2343
2344 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2345
2346 /* Reset Tx ports and delete Tx queues */
2347 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2348 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2349
09f83975 2350 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2351 txq = port->txqs[queue];
2352 mvpp2_txq_clean(port, txq);
2353 mvpp2_txq_deinit(port, txq);
2354 }
2355
2356 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2357
2358 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2359 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2360}
2361
2362/* Cleanup all Rx queues */
2363static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2364{
2365 int queue;
2366
09f83975 2367 for (queue = 0; queue < port->nrxqs; queue++)
3f518509
MW		 2368 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2369}
2370
2371/* Init all Rx queues for port */
2372static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2373{
2374 int queue, err;
2375
09f83975 2376 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 2377 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2378 if (err)
2379 goto err_cleanup;
2380 }
2381 return 0;
2382
2383err_cleanup:
2384 mvpp2_cleanup_rxqs(port);
2385 return err;
2386}
2387
2388/* Init all tx queues for port */
2389static int mvpp2_setup_txqs(struct mvpp2_port *port)
2390{
2391 struct mvpp2_tx_queue *txq;
2392 int queue, err;
2393
09f83975 2394 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2395 txq = port->txqs[queue];
2396 err = mvpp2_txq_init(port, txq);
2397 if (err)
2398 goto err_cleanup;
2399 }
2400
213f428f
TP		 2401 if (port->has_tx_irqs) {
2402 mvpp2_tx_time_coal_set(port);
2403 for (queue = 0; queue < port->ntxqs; queue++) {
2404 txq = port->txqs[queue];
2405 mvpp2_tx_pkts_coal_set(port, txq);
2406 }
2407 }
2408
3f518509
MW		 2409 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2410 return 0;
2411
2412err_cleanup:
2413 mvpp2_cleanup_txqs(port);
2414 return err;
2415}
2416
2417/* The callback for per-port interrupt */
2418static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2419{
591f4cfa 2420 struct mvpp2_queue_vector *qv = dev_id;
3f518509 2421
591f4cfa 2422 mvpp2_qvec_interrupt_disable(qv);
3f518509 2423
591f4cfa 2424 napi_schedule(&qv->napi);
3f518509
MW		 2425
2426 return IRQ_HANDLED;
2427}
2428
fd3651b2
AT		 2429/* Per-port interrupt for link status changes */
2430static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2431{
2432 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2433 struct net_device *dev = port->dev;
2434 bool event = false, link = false;
2435 u32 val;
2436
2437 mvpp22_gop_mask_irq(port);
2438
2439 if (port->gop_id == 0 &&
2440 port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
2441 val = readl(port->base + MVPP22_XLG_INT_STAT);
2442 if (val & MVPP22_XLG_INT_STAT_LINK) {
2443 event = true;
2444 val = readl(port->base + MVPP22_XLG_STATUS);
2445 if (val & MVPP22_XLG_STATUS_LINK_UP)
2446 link = true;
2447 }
2448 } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 2449 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 2450 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
2451 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 2452 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2453 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2454 event = true;
2455 val = readl(port->base + MVPP2_GMAC_STATUS0);
2456 if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2457 link = true;
2458 }
2459 }
2460
4bb04326
AT		 2461 if (port->phylink) {
2462 phylink_mac_change(port->phylink, link);
2463 goto handled;
2464 }
2465
fd3651b2
AT		 2466 if (!netif_running(dev) || !event)
2467 goto handled;
2468
2469 if (link) {
2470 mvpp2_interrupts_enable(port);
2471
2472 mvpp2_egress_enable(port);
2473 mvpp2_ingress_enable(port);
2474 netif_carrier_on(dev);
2475 netif_tx_wake_all_queues(dev);
2476 } else {
2477 netif_tx_stop_all_queues(dev);
2478 netif_carrier_off(dev);
2479 mvpp2_ingress_disable(port);
2480 mvpp2_egress_disable(port);
2481
2482 mvpp2_interrupts_disable(port);
2483 }
2484
2485handled:
2486 mvpp22_gop_unmask_irq(port);
2487 return IRQ_HANDLED;
2488}
2489
edc660fa
MW		 2490static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2491{
2492 ktime_t interval;
2493
2494 if (!port_pcpu->timer_scheduled) {
2495 port_pcpu->timer_scheduled = true;
8b0e1953 2496 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
edc660fa
MW		 2497 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2498 HRTIMER_MODE_REL_PINNED);
2499 }
2500}
2501
2502static void mvpp2_tx_proc_cb(unsigned long data)
2503{
2504 struct net_device *dev = (struct net_device *)data;
2505 struct mvpp2_port *port = netdev_priv(dev);
2506 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
2507 unsigned int tx_todo, cause;
2508
2509 if (!netif_running(dev))
2510 return;
2511 port_pcpu->timer_scheduled = false;
2512
2513 /* Process all the Tx queues */
09f83975 2514 cause = (1 << port->ntxqs) - 1;
213f428f 2515 tx_todo = mvpp2_tx_done(port, cause, smp_processor_id());
edc660fa
MW		 2516
2517 /* Set the timer in case not all the packets were processed */
2518 if (tx_todo)
2519 mvpp2_timer_set(port_pcpu);
2520}
2521
2522static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2523{
2524 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2525 struct mvpp2_port_pcpu,
2526 tx_done_timer);
2527
2528 tasklet_schedule(&port_pcpu->tx_done_tasklet);
2529
2530 return HRTIMER_NORESTART;
2531}
2532
3f518509
MW		 2533/* Main RX/TX processing routines */
2534
2535/* Display more error info */
2536static void mvpp2_rx_error(struct mvpp2_port *port,
2537 struct mvpp2_rx_desc *rx_desc)
2538{
ac3dd277
TP		 2539 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2540 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
934e0f83 2541 char *err_str = NULL;
3f518509
MW		 2542
2543 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2544 case MVPP2_RXD_ERR_CRC:
934e0f83 2545 err_str = "crc";
3f518509
MW		 2546 break;
2547 case MVPP2_RXD_ERR_OVERRUN:
934e0f83 2548 err_str = "overrun";
3f518509
MW		 2549 break;
2550 case MVPP2_RXD_ERR_RESOURCE:
934e0f83 2551 err_str = "resource";
3f518509
MW		 2552 break;
2553 }
934e0f83
YM		 2554 if (err_str && net_ratelimit())
2555 netdev_err(port->dev,
2556 "bad rx status %08x (%s error), size=%zu\n",
2557 status, err_str, sz);
3f518509
MW		 2558}
2559
2560/* Handle RX checksum offload */
2561static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2562 struct sk_buff *skb)
2563{
2564 if (((status & MVPP2_RXD_L3_IP4) &&
2565 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2566 (status & MVPP2_RXD_L3_IP6))
2567 if (((status & MVPP2_RXD_L4_UDP) ||
2568 (status & MVPP2_RXD_L4_TCP)) &&
2569 (status & MVPP2_RXD_L4_CSUM_OK)) {
2570 skb->csum = 0;
2571 skb->ip_summed = CHECKSUM_UNNECESSARY;
2572 return;
2573 }
2574
2575 skb->ip_summed = CHECKSUM_NONE;
2576}
2577
2578/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2579static int mvpp2_rx_refill(struct mvpp2_port *port,
56b8aae9 2580 struct mvpp2_bm_pool *bm_pool, int pool)
3f518509 2581{
20396136 2582 dma_addr_t dma_addr;
4e4a105f 2583 phys_addr_t phys_addr;
0e037281 2584 void *buf;
3f518509 2585
3f518509 2586 /* No recycle or too many buffers are in use, so allocate a new skb */
4e4a105f
TP		 2587 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2588 GFP_ATOMIC);
0e037281 2589 if (!buf)
3f518509
MW		 2590 return -ENOMEM;
2591
7d7627ba 2592 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
7ef7e1d9 2593
3f518509
MW		 2594 return 0;
2595}
2596
2597/* Handle tx checksum */
2598static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2599{
2600 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2601 int ip_hdr_len = 0;
2602 u8 l4_proto;
2603
2604 if (skb->protocol == htons(ETH_P_IP)) {
2605 struct iphdr *ip4h = ip_hdr(skb);
2606
2607 /* Calculate IPv4 checksum and L4 checksum */
2608 ip_hdr_len = ip4h->ihl;
2609 l4_proto = ip4h->protocol;
2610 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2611 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2612
2613 /* Read l4_protocol from one of IPv6 extra headers */
2614 if (skb_network_header_len(skb) > 0)
2615 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2616 l4_proto = ip6h->nexthdr;
2617 } else {
2618 return MVPP2_TXD_L4_CSUM_NOT;
2619 }
2620
2621 return mvpp2_txq_desc_csum(skb_network_offset(skb),
2622 skb->protocol, ip_hdr_len, l4_proto);
2623 }
2624
2625 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2626}
2627
3f518509 2628/* Main rx processing */
591f4cfa
TP		 2629static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2630 int rx_todo, struct mvpp2_rx_queue *rxq)
3f518509
MW		 2631{
2632 struct net_device *dev = port->dev;
b5015854
MW		 2633 int rx_received;
2634 int rx_done = 0;
3f518509
MW		 2635 u32 rcvd_pkts = 0;
2636 u32 rcvd_bytes = 0;
2637
2638 /* Get number of received packets and clamp the to-do */
2639 rx_received = mvpp2_rxq_received(port, rxq->id);
2640 if (rx_todo > rx_received)
2641 rx_todo = rx_received;
2642
b5015854 2643 while (rx_done < rx_todo) {
3f518509
MW		 2644 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2645 struct mvpp2_bm_pool *bm_pool;
2646 struct sk_buff *skb;
0e037281 2647 unsigned int frag_size;
20396136 2648 dma_addr_t dma_addr;
ac3dd277 2649 phys_addr_t phys_addr;
56b8aae9 2650 u32 rx_status;
3f518509 2651 int pool, rx_bytes, err;
0e037281 2652 void *data;
3f518509 2653
b5015854 2654 rx_done++;
ac3dd277
TP		 2655 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2656 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2657 rx_bytes -= MVPP2_MH_SIZE;
2658 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2659 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2660 data = (void *)phys_to_virt(phys_addr);
2661
56b8aae9
TP		 2662 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2663 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2664 bm_pool = &port->priv->bm_pools[pool];
3f518509
MW		 2665
2666 /* In case of an error, release the requested buffer pointer
2667 * to the Buffer Manager. This request process is controlled
2668 * by the hardware, and the information about the buffer is
2669 * comprised by the RX descriptor.
2670 */
2671 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
8a52488b 2672err_drop_frame:
3f518509
MW		 2673 dev->stats.rx_errors++;
2674 mvpp2_rx_error(port, rx_desc);
b5015854 2675 /* Return the buffer to the pool */
7d7627ba 2676 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3f518509
MW		 2677 continue;
2678 }
2679
0e037281
TP		 2680 if (bm_pool->frag_size > PAGE_SIZE)
2681 frag_size = 0;
2682 else
2683 frag_size = bm_pool->frag_size;
2684
2685 skb = build_skb(data, frag_size);
2686 if (!skb) {
2687 netdev_warn(port->dev, "skb build failed\n");
2688 goto err_drop_frame;
2689 }
3f518509 2690
56b8aae9 2691 err = mvpp2_rx_refill(port, bm_pool, pool);
b5015854
MW		 2692 if (err) {
2693 netdev_err(port->dev, "failed to refill BM pools\n");
2694 goto err_drop_frame;
2695 }
2696
20396136 2697 dma_unmap_single(dev->dev.parent, dma_addr,
4229d502
MW		 2698 bm_pool->buf_size, DMA_FROM_DEVICE);
2699
3f518509
MW		 2700 rcvd_pkts++;
2701 rcvd_bytes += rx_bytes;
3f518509 2702
0e037281 2703 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
3f518509
MW		 2704 skb_put(skb, rx_bytes);
2705 skb->protocol = eth_type_trans(skb, dev);
2706 mvpp2_rx_csum(port, rx_status, skb);
2707
591f4cfa 2708 napi_gro_receive(napi, skb);
3f518509
MW		 2709 }
2710
2711 if (rcvd_pkts) {
2712 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2713
2714 u64_stats_update_begin(&stats->syncp);
2715 stats->rx_packets += rcvd_pkts;
2716 stats->rx_bytes += rcvd_bytes;
2717 u64_stats_update_end(&stats->syncp);
2718 }
2719
2720 /* Update Rx queue management counters */
2721 wmb();
b5015854 2722 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
3f518509
MW		 2723
2724 return rx_todo;
2725}
2726
2727static inline void
ac3dd277 2728tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3f518509
MW		 2729 struct mvpp2_tx_desc *desc)
2730{
20920267
AT		 2731 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
2732
ac3dd277
TP		 2733 dma_addr_t buf_dma_addr =
2734 mvpp2_txdesc_dma_addr_get(port, desc);
2735 size_t buf_sz =
2736 mvpp2_txdesc_size_get(port, desc);
20920267
AT		 2737 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2738 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2739 buf_sz, DMA_TO_DEVICE);
3f518509
MW		 2740 mvpp2_txq_desc_put(txq);
2741}
2742
2743/* Handle tx fragmentation processing */
2744static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2745 struct mvpp2_tx_queue *aggr_txq,
2746 struct mvpp2_tx_queue *txq)
2747{
2748 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
2749 struct mvpp2_tx_desc *tx_desc;
2750 int i;
20396136 2751 dma_addr_t buf_dma_addr;
3f518509
MW		 2752
2753 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2754 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2755 void *addr = page_address(frag->page.p) + frag->page_offset;
2756
2757 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 2758 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2759 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
3f518509 2760
20396136 2761 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
a3302baa 2762 frag->size, DMA_TO_DEVICE);
20396136 2763 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
3f518509 2764 mvpp2_txq_desc_put(txq);
32bae631 2765 goto cleanup;
3f518509
MW		 2766 }
2767
6eb5d375 2768 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 2769
2770 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2771 /* Last descriptor */
ac3dd277
TP		 2772 mvpp2_txdesc_cmd_set(port, tx_desc,
2773 MVPP2_TXD_L_DESC);
2774 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 2775 } else {
2776 /* Descriptor in the middle: Not First, Not Last */
ac3dd277
TP		 2777 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2778 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 2779 }
2780 }
2781
2782 return 0;
32bae631 2783cleanup:
3f518509
MW		 2784 /* Release all descriptors that were used to map fragments of
2785 * this packet, as well as the corresponding DMA mappings
2786 */
2787 for (i = i - 1; i >= 0; i--) {
2788 tx_desc = txq->descs + i;
ac3dd277 2789 tx_desc_unmap_put(port, txq, tx_desc);
3f518509
MW		 2790 }
2791
2792 return -ENOMEM;
2793}
2794
186cd4d4
AT		 2795static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2796 struct net_device *dev,
2797 struct mvpp2_tx_queue *txq,
2798 struct mvpp2_tx_queue *aggr_txq,
2799 struct mvpp2_txq_pcpu *txq_pcpu,
2800 int hdr_sz)
2801{
2802 struct mvpp2_port *port = netdev_priv(dev);
2803 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2804 dma_addr_t addr;
2805
2806 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2807 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2808
2809 addr = txq_pcpu->tso_headers_dma +
2810 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
6eb5d375 2811 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
186cd4d4
AT		 2812
2813 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2814 MVPP2_TXD_F_DESC |
2815 MVPP2_TXD_PADDING_DISABLE);
2816 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2817}
2818
2819static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2820 struct net_device *dev, struct tso_t *tso,
2821 struct mvpp2_tx_queue *txq,
2822 struct mvpp2_tx_queue *aggr_txq,
2823 struct mvpp2_txq_pcpu *txq_pcpu,
2824 int sz, bool left, bool last)
2825{
2826 struct mvpp2_port *port = netdev_priv(dev);
2827 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2828 dma_addr_t buf_dma_addr;
2829
2830 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2831 mvpp2_txdesc_size_set(port, tx_desc, sz);
2832
2833 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
2834 DMA_TO_DEVICE);
2835 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2836 mvpp2_txq_desc_put(txq);
2837 return -ENOMEM;
2838 }
2839
6eb5d375 2840 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
186cd4d4
AT		 2841
2842 if (!left) {
2843 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
2844 if (last) {
2845 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2846 return 0;
2847 }
2848 } else {
2849 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2850 }
2851
2852 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2853 return 0;
2854}
2855
2856static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
2857 struct mvpp2_tx_queue *txq,
2858 struct mvpp2_tx_queue *aggr_txq,
2859 struct mvpp2_txq_pcpu *txq_pcpu)
2860{
2861 struct mvpp2_port *port = netdev_priv(dev);
2862 struct tso_t tso;
2863 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
2864 int i, len, descs = 0;
2865
2866 /* Check number of available descriptors */
2867 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq,
2868 tso_count_descs(skb)) ||
2869 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu,
2870 tso_count_descs(skb)))
2871 return 0;
2872
2873 tso_start(skb, &tso);
2874 len = skb->len - hdr_sz;
2875 while (len > 0) {
2876 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
2877 char *hdr = txq_pcpu->tso_headers +
2878 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2879
2880 len -= left;
2881 descs++;
2882
2883 tso_build_hdr(skb, hdr, &tso, left, len == 0);
2884 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
2885
2886 while (left > 0) {
2887 int sz = min_t(int, tso.size, left);
2888 left -= sz;
2889 descs++;
2890
2891 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
2892 txq_pcpu, sz, left, len == 0))
2893 goto release;
2894 tso_build_data(skb, &tso, sz);
2895 }
2896 }
2897
2898 return descs;
2899
2900release:
2901 for (i = descs - 1; i >= 0; i--) {
2902 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
2903 tx_desc_unmap_put(port, txq, tx_desc);
2904 }
2905 return 0;
2906}
2907
3f518509
MW		 2908/* Main tx processing */
2909static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
2910{
2911 struct mvpp2_port *port = netdev_priv(dev);
2912 struct mvpp2_tx_queue *txq, *aggr_txq;
2913 struct mvpp2_txq_pcpu *txq_pcpu;
2914 struct mvpp2_tx_desc *tx_desc;
20396136 2915 dma_addr_t buf_dma_addr;
3f518509
MW		 2916 int frags = 0;
2917 u16 txq_id;
2918 u32 tx_cmd;
2919
2920 txq_id = skb_get_queue_mapping(skb);
2921 txq = port->txqs[txq_id];
2922 txq_pcpu = this_cpu_ptr(txq->pcpu);
2923 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
2924
186cd4d4
AT		 2925 if (skb_is_gso(skb)) {
2926 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
2927 goto out;
2928 }
3f518509
MW		 2929 frags = skb_shinfo(skb)->nr_frags + 1;
2930
2931 /* Check number of available descriptors */
2932 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) ||
2933 mvpp2_txq_reserved_desc_num_proc(port->priv, txq,
2934 txq_pcpu, frags)) {
2935 frags = 0;
2936 goto out;
2937 }
2938
2939 /* Get a descriptor for the first part of the packet */
2940 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 2941 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2942 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3f518509 2943
20396136 2944 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
ac3dd277 2945 skb_headlen(skb), DMA_TO_DEVICE);
20396136 2946 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3f518509
MW		 2947 mvpp2_txq_desc_put(txq);
2948 frags = 0;
2949 goto out;
2950 }
ac3dd277 2951
6eb5d375 2952 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 2953
2954 tx_cmd = mvpp2_skb_tx_csum(port, skb);
2955
2956 if (frags == 1) {
2957 /* First and Last descriptor */
2958 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
ac3dd277
TP		 2959 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
2960 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 2961 } else {
2962 /* First but not Last */
2963 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
ac3dd277
TP		 2964 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
2965 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 2966
2967 /* Continue with other skb fragments */
2968 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
ac3dd277 2969 tx_desc_unmap_put(port, txq, tx_desc);
3f518509 2970 frags = 0;
3f518509
MW		 2971 }
2972 }
2973
3f518509
MW		 2974out:
2975 if (frags > 0) {
2976 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
186cd4d4
AT		 2977 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2978
2979 txq_pcpu->reserved_num -= frags;
2980 txq_pcpu->count += frags;
2981 aggr_txq->count += frags;
2982
2983 /* Enable transmit */
2984 wmb();
2985 mvpp2_aggr_txq_pend_desc_add(port, frags);
2986
1d17db08 2987 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
186cd4d4 2988 netif_tx_stop_queue(nq);
3f518509
MW		 2989
2990 u64_stats_update_begin(&stats->syncp);
2991 stats->tx_packets++;
2992 stats->tx_bytes += skb->len;
2993 u64_stats_update_end(&stats->syncp);
2994 } else {
2995 dev->stats.tx_dropped++;
2996 dev_kfree_skb_any(skb);
2997 }
2998
edc660fa 2999 /* Finalize TX processing */
082297e6 3000 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
edc660fa
MW		 3001 mvpp2_txq_done(port, txq, txq_pcpu);
3002
3003 /* Set the timer in case not all frags were processed */
213f428f
TP		 3004 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3005 txq_pcpu->count > 0) {
edc660fa
MW		 3006 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
3007
3008 mvpp2_timer_set(port_pcpu);
3009 }
3010
3f518509
MW		 3011 return NETDEV_TX_OK;
3012}
3013
3014static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3015{
3016 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3017 netdev_err(dev, "FCS error\n");
3018 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3019 netdev_err(dev, "rx fifo overrun error\n");
3020 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3021 netdev_err(dev, "tx fifo underrun error\n");
3022}
3023
edc660fa 3024static int mvpp2_poll(struct napi_struct *napi, int budget)
3f518509 3025{
213f428f 3026 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
edc660fa
MW		 3027 int rx_done = 0;
3028 struct mvpp2_port *port = netdev_priv(napi->dev);
591f4cfa 3029 struct mvpp2_queue_vector *qv;
a786841d 3030 int cpu = smp_processor_id();
3f518509 3031
591f4cfa
TP		 3032 qv = container_of(napi, struct mvpp2_queue_vector, napi);
3033
3f518509
MW		 3034 /* Rx/Tx cause register
3035 *
3036 * Bits 0-15: each bit indicates received packets on the Rx queue
3037 * (bit 0 is for Rx queue 0).
3038 *
3039 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3040 * (bit 16 is for Tx queue 0).
3041 *
3042 * Each CPU has its own Rx/Tx cause register
3043 */
cdcfeb0f
YM		 3044 cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id,
3045 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3f518509 3046
213f428f 3047 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3f518509
MW		 3048 if (cause_misc) {
3049 mvpp2_cause_error(port->dev, cause_misc);
3050
3051 /* Clear the cause register */
3052 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
a786841d
TP		 3053 mvpp2_percpu_write(port->priv, cpu,
3054 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3055 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3f518509
MW		 3056 }
3057
213f428f
TP		 3058 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3059 if (cause_tx) {
3060 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3061 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3062 }
3f518509
MW		 3063
3064 /* Process RX packets */
213f428f
TP		 3065 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
3066 cause_rx <<= qv->first_rxq;
591f4cfa 3067 cause_rx |= qv->pending_cause_rx;
3f518509
MW		 3068 while (cause_rx && budget > 0) {
3069 int count;
3070 struct mvpp2_rx_queue *rxq;
3071
3072 rxq = mvpp2_get_rx_queue(port, cause_rx);
3073 if (!rxq)
3074 break;
3075
591f4cfa 3076 count = mvpp2_rx(port, napi, budget, rxq);
3f518509
MW		 3077 rx_done += count;
3078 budget -= count;
3079 if (budget > 0) {
3080 /* Clear the bit associated to this Rx queue
3081 * so that next iteration will continue from
3082 * the next Rx queue.
3083 */
3084 cause_rx &= ~(1 << rxq->logic_rxq);
3085 }
3086 }
3087
3088 if (budget > 0) {
3089 cause_rx = 0;
6ad20165 3090 napi_complete_done(napi, rx_done);
3f518509 3091
591f4cfa 3092 mvpp2_qvec_interrupt_enable(qv);
3f518509 3093 }
591f4cfa 3094 qv->pending_cause_rx = cause_rx;
3f518509
MW		 3095 return rx_done;
3096}
3097
4bb04326 3098static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3f518509 3099{
4bb04326
AT		 3100 u32 ctrl3;
3101
3102 /* comphy reconfiguration */
3103 mvpp22_comphy_init(port);
3104
3105 /* gop reconfiguration */
3106 mvpp22_gop_init(port);
3107
3108 /* Only GOP port 0 has an XLG MAC */
3109 if (port->gop_id == 0) {
3110 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3111 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3112
3113 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3114 port->phy_interface == PHY_INTERFACE_MODE_10GKR)
3115 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3116 else
3117 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3118
3119 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3120 }
8e07269d 3121
76eb1b1d
SC		 3122 if (port->gop_id == 0 &&
3123 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3124 port->phy_interface == PHY_INTERFACE_MODE_10GKR))
3125 mvpp2_xlg_max_rx_size_set(port);
3126 else
3127 mvpp2_gmac_max_rx_size_set(port);
4bb04326
AT		 3128}
3129
3130/* Set hw internals when starting port */
3131static void mvpp2_start_dev(struct mvpp2_port *port)
3132{
3133 int i;
76eb1b1d 3134
3f518509
MW		 3135 mvpp2_txp_max_tx_size_set(port);
3136
591f4cfa
TP		 3137 for (i = 0; i < port->nqvecs; i++)
3138 napi_enable(&port->qvecs[i].napi);
3f518509
MW		 3139
3140 /* Enable interrupts on all CPUs */
3141 mvpp2_interrupts_enable(port);
3142
4bb04326
AT		 3143 if (port->priv->hw_version == MVPP22)
3144 mvpp22_mode_reconfigure(port);
3145
3146 if (port->phylink) {
41948ccb 3147 netif_carrier_off(port->dev);
4bb04326
AT		 3148 phylink_start(port->phylink);
3149 } else {
3150 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3151 * configured manually when the interface is started. This will
3152 * be removed as soon as the phylink ACPI support lands in.
3153 */
3154 struct phylink_link_state state = {
3155 .interface = port->phy_interface,
4bb04326
AT		 3156 };
3157 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
41948ccb
AT		 3158 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface,
3159 NULL);
542897d9 3160 }
f84bf386 3161
3f518509
MW		 3162 netif_tx_start_all_queues(port->dev);
3163}
3164
3165/* Set hw internals when stopping port */
3166static void mvpp2_stop_dev(struct mvpp2_port *port)
3167{
591f4cfa 3168 int i;
8e07269d 3169
3f518509
MW		 3170 /* Disable interrupts on all CPUs */
3171 mvpp2_interrupts_disable(port);
3172
591f4cfa
TP		 3173 for (i = 0; i < port->nqvecs; i++)
3174 napi_disable(&port->qvecs[i].napi);
3f518509 3175
4bb04326
AT		 3176 if (port->phylink)
3177 phylink_stop(port->phylink);
542897d9 3178 phy_power_off(port->comphy);
3f518509
MW		 3179}
3180
3f518509
MW		 3181static int mvpp2_check_ringparam_valid(struct net_device *dev,
3182 struct ethtool_ringparam *ring)
3183{
3184 u16 new_rx_pending = ring->rx_pending;
3185 u16 new_tx_pending = ring->tx_pending;
3186
3187 if (ring->rx_pending == 0 || ring->tx_pending == 0)
3188 return -EINVAL;
3189
7cf87e4a
YM		 3190 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3191 new_rx_pending = MVPP2_MAX_RXD_MAX;
3f518509
MW		 3192 else if (!IS_ALIGNED(ring->rx_pending, 16))
3193 new_rx_pending = ALIGN(ring->rx_pending, 16);
3194
7cf87e4a
YM		 3195 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3196 new_tx_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3197 else if (!IS_ALIGNED(ring->tx_pending, 32))
3198 new_tx_pending = ALIGN(ring->tx_pending, 32);
3199
76e583c5
AT		 3200 /* The Tx ring size cannot be smaller than the minimum number of
3201 * descriptors needed for TSO.
3202 */
3203 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3204 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3205
3f518509
MW		 3206 if (ring->rx_pending != new_rx_pending) {
3207 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3208 ring->rx_pending, new_rx_pending);
3209 ring->rx_pending = new_rx_pending;
3210 }
3211
3212 if (ring->tx_pending != new_tx_pending) {
3213 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3214 ring->tx_pending, new_tx_pending);
3215 ring->tx_pending = new_tx_pending;
3216 }
3217
3218 return 0;
3219}
3220
26975821 3221static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3f518509
MW		 3222{
3223 u32 mac_addr_l, mac_addr_m, mac_addr_h;
3224
3225 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3226 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3227 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3228 addr[0] = (mac_addr_h >> 24) & 0xFF;
3229 addr[1] = (mac_addr_h >> 16) & 0xFF;
3230 addr[2] = (mac_addr_h >> 8) & 0xFF;
3231 addr[3] = mac_addr_h & 0xFF;
3232 addr[4] = mac_addr_m & 0xFF;
3233 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3234}
3235
591f4cfa
TP		 3236static int mvpp2_irqs_init(struct mvpp2_port *port)
3237{
3238 int err, i;
3239
3240 for (i = 0; i < port->nqvecs; i++) {
3241 struct mvpp2_queue_vector *qv = port->qvecs + i;
3242
13c249a9
MZ		 3243 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3244 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
3245
591f4cfa
TP		 3246 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3247 if (err)
3248 goto err;
213f428f
TP		 3249
3250 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3251 irq_set_affinity_hint(qv->irq,
3252 cpumask_of(qv->sw_thread_id));
591f4cfa
TP		 3253 }
3254
3255 return 0;
3256err:
3257 for (i = 0; i < port->nqvecs; i++) {
3258 struct mvpp2_queue_vector *qv = port->qvecs + i;
3259
213f428f 3260 irq_set_affinity_hint(qv->irq, NULL);
591f4cfa
TP		 3261 free_irq(qv->irq, qv);
3262 }
3263
3264 return err;
3265}
3266
3267static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3268{
3269 int i;
3270
3271 for (i = 0; i < port->nqvecs; i++) {
3272 struct mvpp2_queue_vector *qv = port->qvecs + i;
3273
213f428f 3274 irq_set_affinity_hint(qv->irq, NULL);
13c249a9 3275 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
591f4cfa
TP		 3276 free_irq(qv->irq, qv);
3277 }
3278}
3279
4c4a5686
YM		 3280static bool mvpp22_rss_is_supported(void)
3281{
3282 return queue_mode == MVPP2_QDIST_MULTI_MODE;
3283}
3284
3f518509
MW		 3285static int mvpp2_open(struct net_device *dev)
3286{
3287 struct mvpp2_port *port = netdev_priv(dev);
fd3651b2 3288 struct mvpp2 *priv = port->priv;
3f518509
MW		 3289 unsigned char mac_bcast[ETH_ALEN] = {
3290 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4bb04326 3291 bool valid = false;
3f518509
MW		 3292 int err;
3293
ce2a27c7 3294 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3f518509
MW		 3295 if (err) {
3296 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3297 return err;
3298 }
ce2a27c7 3299 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3f518509 3300 if (err) {
ce2a27c7 3301 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3f518509
MW		 3302 return err;
3303 }
3304 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3305 if (err) {
3306 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3307 return err;
3308 }
3309 err = mvpp2_prs_def_flow(port);
3310 if (err) {
3311 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3312 return err;
3313 }
3314
3315 /* Allocate the Rx/Tx queues */
3316 err = mvpp2_setup_rxqs(port);
3317 if (err) {
3318 netdev_err(port->dev, "cannot allocate Rx queues\n");
3319 return err;
3320 }
3321
3322 err = mvpp2_setup_txqs(port);
3323 if (err) {
3324 netdev_err(port->dev, "cannot allocate Tx queues\n");
3325 goto err_cleanup_rxqs;
3326 }
3327
591f4cfa 3328 err = mvpp2_irqs_init(port);
3f518509 3329 if (err) {
591f4cfa 3330 netdev_err(port->dev, "cannot init IRQs\n");
3f518509
MW		 3331 goto err_cleanup_txqs;
3332 }
3333
4bb04326
AT		 3334 /* Phylink isn't supported yet in ACPI mode */
3335 if (port->of_node) {
3336 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3337 if (err) {
3338 netdev_err(port->dev, "could not attach PHY (%d)\n",
3339 err);
3340 goto err_free_irq;
3341 }
3342
3343 valid = true;
3344 }
3345
3346 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
fd3651b2
AT		 3347 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3348 dev->name, port);
3349 if (err) {
3350 netdev_err(port->dev, "cannot request link IRQ %d\n",
3351 port->link_irq);
3352 goto err_free_irq;
3353 }
3354
3355 mvpp22_gop_setup_irq(port);
fd3651b2 3356
4bb04326
AT		 3357 /* In default link is down */
3358 netif_carrier_off(port->dev);
3f518509 3359
4bb04326
AT		 3360 valid = true;
3361 } else {
3362 port->link_irq = 0;
3363 }
3364
3365 if (!valid) {
3366 netdev_err(port->dev,
3367 "invalid configuration: no dt or link IRQ");
3368 goto err_free_irq;
3369 }
3f518509
MW		 3370
3371 /* Unmask interrupts on all CPUs */
3372 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
213f428f 3373 mvpp2_shared_interrupt_mask_unmask(port, false);
3f518509
MW		 3374
3375 mvpp2_start_dev(port);
3376
118d6298 3377 /* Start hardware statistics gathering */
e5c500eb 3378 queue_delayed_work(priv->stats_queue, &port->stats_work,
118d6298
MR		 3379 MVPP2_MIB_COUNTERS_STATS_DELAY);
3380
3f518509
MW		 3381 return 0;
3382
3383err_free_irq:
591f4cfa 3384 mvpp2_irqs_deinit(port);
3f518509
MW		 3385err_cleanup_txqs:
3386 mvpp2_cleanup_txqs(port);
3387err_cleanup_rxqs:
3388 mvpp2_cleanup_rxqs(port);
3389 return err;
3390}
3391
3392static int mvpp2_stop(struct net_device *dev)
3393{
3394 struct mvpp2_port *port = netdev_priv(dev);
edc660fa
MW		 3395 struct mvpp2_port_pcpu *port_pcpu;
3396 int cpu;
3f518509
MW		 3397
3398 mvpp2_stop_dev(port);
3f518509
MW		 3399
3400 /* Mask interrupts on all CPUs */
3401 on_each_cpu(mvpp2_interrupts_mask, port, 1);
213f428f 3402 mvpp2_shared_interrupt_mask_unmask(port, true);
3f518509 3403
4bb04326
AT		 3404 if (port->phylink)
3405 phylink_disconnect_phy(port->phylink);
3406 if (port->link_irq)
fd3651b2
AT		 3407 free_irq(port->link_irq, port);
3408
591f4cfa 3409 mvpp2_irqs_deinit(port);
213f428f
TP		 3410 if (!port->has_tx_irqs) {
3411 for_each_present_cpu(cpu) {
3412 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
edc660fa 3413
213f428f
TP		 3414 hrtimer_cancel(&port_pcpu->tx_done_timer);
3415 port_pcpu->timer_scheduled = false;
3416 tasklet_kill(&port_pcpu->tx_done_tasklet);
3417 }
edc660fa 3418 }
3f518509
MW		 3419 mvpp2_cleanup_rxqs(port);
3420 mvpp2_cleanup_txqs(port);
3421
e5c500eb 3422 cancel_delayed_work_sync(&port->stats_work);
118d6298 3423
3f518509
MW		 3424 return 0;
3425}
3426
10fea26c
MC		 3427static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3428 struct netdev_hw_addr_list *list)
3f518509 3429{
3f518509 3430 struct netdev_hw_addr *ha;
10fea26c
MC		 3431 int ret;
3432
3433 netdev_hw_addr_list_for_each(ha, list) {
3434 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3435 if (ret)
3436 return ret;
3f518509 3437 }
56beda3d 3438
10fea26c
MC		 3439 return 0;
3440}
3441
3442static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3443{
3444 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
56beda3d 3445 mvpp2_prs_vid_enable_filtering(port);
10fea26c
MC		 3446 else
3447 mvpp2_prs_vid_disable_filtering(port);
3448
3449 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3450 MVPP2_PRS_L2_UNI_CAST, enable);
3451
3452 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3453 MVPP2_PRS_L2_MULTI_CAST, enable);
3454}
3455
3456static void mvpp2_set_rx_mode(struct net_device *dev)
3457{
3458 struct mvpp2_port *port = netdev_priv(dev);
3459
3460 /* Clear the whole UC and MC list */
3461 mvpp2_prs_mac_del_all(port);
3462
3463 if (dev->flags & IFF_PROMISC) {
3464 mvpp2_set_rx_promisc(port, true);
3465 return;
3466 }
3467
3468 mvpp2_set_rx_promisc(port, false);
3469
3470 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3471 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3472 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3473 MVPP2_PRS_L2_UNI_CAST, true);
3474
3475 if (dev->flags & IFF_ALLMULTI) {
3476 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3477 MVPP2_PRS_L2_MULTI_CAST, true);
3478 return;
3479 }
3480
3481 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3482 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3483 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3484 MVPP2_PRS_L2_MULTI_CAST, true);
3f518509
MW		 3485}
3486
3487static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3488{
3f518509
MW		 3489 const struct sockaddr *addr = p;
3490 int err;
3491
5b0ab2f4
YM		 3492 if (!is_valid_ether_addr(addr->sa_data))
3493 return -EADDRNOTAVAIL;
3f518509
MW		 3494
3495 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5b0ab2f4
YM		 3496 if (err) {
3497 /* Reconfigure parser accept the original MAC address */
3498 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3499 netdev_err(dev, "failed to change MAC address\n");
3500 }
3f518509
MW		 3501 return err;
3502}
3503
3504static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3505{
3506 struct mvpp2_port *port = netdev_priv(dev);
3507 int err;
3508
5777987e
JW		 3509 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3510 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3511 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3512 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3f518509
MW		 3513 }
3514
3515 if (!netif_running(dev)) {
3516 err = mvpp2_bm_update_mtu(dev, mtu);
3517 if (!err) {
3518 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3519 return 0;
3520 }
3521
3522 /* Reconfigure BM to the original MTU */
3523 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3524 if (err)
c1175547 3525 goto log_error;
3f518509
MW		 3526 }
3527
3528 mvpp2_stop_dev(port);
3529
3530 err = mvpp2_bm_update_mtu(dev, mtu);
3531 if (!err) {
3532 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3533 goto out_start;
3534 }
3535
3536 /* Reconfigure BM to the original MTU */
3537 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3538 if (err)
c1175547 3539 goto log_error;
3f518509
MW		 3540
3541out_start:
3542 mvpp2_start_dev(port);
3543 mvpp2_egress_enable(port);
3544 mvpp2_ingress_enable(port);
3545
3546 return 0;
c1175547 3547log_error:
dfd4240a 3548 netdev_err(dev, "failed to change MTU\n");
3f518509
MW		 3549 return err;
3550}
3551
bc1f4470 3552static void
3f518509
MW		 3553mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3554{
3555 struct mvpp2_port *port = netdev_priv(dev);
3556 unsigned int start;
3557 int cpu;
3558
3559 for_each_possible_cpu(cpu) {
3560 struct mvpp2_pcpu_stats *cpu_stats;
3561 u64 rx_packets;
3562 u64 rx_bytes;
3563 u64 tx_packets;
3564 u64 tx_bytes;
3565
3566 cpu_stats = per_cpu_ptr(port->stats, cpu);
3567 do {
3568 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3569 rx_packets = cpu_stats->rx_packets;
3570 rx_bytes = cpu_stats->rx_bytes;
3571 tx_packets = cpu_stats->tx_packets;
3572 tx_bytes = cpu_stats->tx_bytes;
3573 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3574
3575 stats->rx_packets += rx_packets;
3576 stats->rx_bytes += rx_bytes;
3577 stats->tx_packets += tx_packets;
3578 stats->tx_bytes += tx_bytes;
3579 }
3580
3581 stats->rx_errors = dev->stats.rx_errors;
3582 stats->rx_dropped = dev->stats.rx_dropped;
3583 stats->tx_dropped = dev->stats.tx_dropped;
3f518509
MW		 3584}
3585
bd695a5f
TP		 3586static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3587{
4bb04326 3588 struct mvpp2_port *port = netdev_priv(dev);
bd695a5f 3589
4bb04326 3590 if (!port->phylink)
bd695a5f
TP		 3591 return -ENOTSUPP;
3592
4bb04326 3593 return phylink_mii_ioctl(port->phylink, ifr, cmd);
bd695a5f
TP		 3594}
3595
56beda3d
MC		 3596static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3597{
3598 struct mvpp2_port *port = netdev_priv(dev);
3599 int ret;
3600
3601 ret = mvpp2_prs_vid_entry_add(port, vid);
3602 if (ret)
3603 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3604 MVPP2_PRS_VLAN_FILT_MAX - 1);
3605 return ret;
3606}
3607
3608static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3609{
3610 struct mvpp2_port *port = netdev_priv(dev);
3611
3612 mvpp2_prs_vid_entry_remove(port, vid);
3613 return 0;
3614}
3615
3616static int mvpp2_set_features(struct net_device *dev,
3617 netdev_features_t features)
3618{
3619 netdev_features_t changed = dev->features ^ features;
3620 struct mvpp2_port *port = netdev_priv(dev);
3621
3622 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3623 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3624 mvpp2_prs_vid_enable_filtering(port);
3625 } else {
3626 /* Invalidate all registered VID filters for this
3627 * port
3628 */
3629 mvpp2_prs_vid_remove_all(port);
3630
3631 mvpp2_prs_vid_disable_filtering(port);
3632 }
3633 }
3634
d33ec452
MC		 3635 if (changed & NETIF_F_RXHASH) {
3636 if (features & NETIF_F_RXHASH)
3637 mvpp22_rss_enable(port);
3638 else
3639 mvpp22_rss_disable(port);
3640 }
3641
56beda3d
MC		 3642 return 0;
3643}
3644
3f518509
MW		 3645/* Ethtool methods */
3646
4bb04326
AT		 3647static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3648{
3649 struct mvpp2_port *port = netdev_priv(dev);
3650
3651 if (!port->phylink)
3652 return -ENOTSUPP;
3653
3654 return phylink_ethtool_nway_reset(port->phylink);
3655}
3656
3f518509
MW		 3657/* Set interrupt coalescing for ethtools */
3658static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3659 struct ethtool_coalesce *c)
3660{
3661 struct mvpp2_port *port = netdev_priv(dev);
3662 int queue;
3663
09f83975 3664 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 3665 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3666
3667 rxq->time_coal = c->rx_coalesce_usecs;
3668 rxq->pkts_coal = c->rx_max_coalesced_frames;
d63f9e41
TP		 3669 mvpp2_rx_pkts_coal_set(port, rxq);
3670 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 3671 }
3672
213f428f
TP		 3673 if (port->has_tx_irqs) {
3674 port->tx_time_coal = c->tx_coalesce_usecs;
3675 mvpp2_tx_time_coal_set(port);
3676 }
3677
09f83975 3678 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 3679 struct mvpp2_tx_queue *txq = port->txqs[queue];
3680
3681 txq->done_pkts_coal = c->tx_max_coalesced_frames;
213f428f
TP		 3682
3683 if (port->has_tx_irqs)
3684 mvpp2_tx_pkts_coal_set(port, txq);
3f518509
MW		 3685 }
3686
3f518509
MW		 3687 return 0;
3688}
3689
3690/* get coalescing for ethtools */
3691static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3692 struct ethtool_coalesce *c)
3693{
3694 struct mvpp2_port *port = netdev_priv(dev);
3695
385c284f
AT		 3696 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
3697 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3698 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
24b28ccb 3699 c->tx_coalesce_usecs = port->tx_time_coal;
3f518509
MW		 3700 return 0;
3701}
3702
3703static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3704 struct ethtool_drvinfo *drvinfo)
3705{
3706 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3707 sizeof(drvinfo->driver));
3708 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3709 sizeof(drvinfo->version));
3710 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3711 sizeof(drvinfo->bus_info));
3712}
3713
3714static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3715 struct ethtool_ringparam *ring)
3716{
3717 struct mvpp2_port *port = netdev_priv(dev);
3718
7cf87e4a
YM		 3719 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3720 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3721 ring->rx_pending = port->rx_ring_size;
3722 ring->tx_pending = port->tx_ring_size;
3723}
3724
3725static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3726 struct ethtool_ringparam *ring)
3727{
3728 struct mvpp2_port *port = netdev_priv(dev);
3729 u16 prev_rx_ring_size = port->rx_ring_size;
3730 u16 prev_tx_ring_size = port->tx_ring_size;
3731 int err;
3732
3733 err = mvpp2_check_ringparam_valid(dev, ring);
3734 if (err)
3735 return err;
3736
3737 if (!netif_running(dev)) {
3738 port->rx_ring_size = ring->rx_pending;
3739 port->tx_ring_size = ring->tx_pending;
3740 return 0;
3741 }
3742
3743 /* The interface is running, so we have to force a
3744 * reallocation of the queues
3745 */
3746 mvpp2_stop_dev(port);
3747 mvpp2_cleanup_rxqs(port);
3748 mvpp2_cleanup_txqs(port);
3749
3750 port->rx_ring_size = ring->rx_pending;
3751 port->tx_ring_size = ring->tx_pending;
3752
3753 err = mvpp2_setup_rxqs(port);
3754 if (err) {
3755 /* Reallocate Rx queues with the original ring size */
3756 port->rx_ring_size = prev_rx_ring_size;
3757 ring->rx_pending = prev_rx_ring_size;
3758 err = mvpp2_setup_rxqs(port);
3759 if (err)
3760 goto err_out;
3761 }
3762 err = mvpp2_setup_txqs(port);
3763 if (err) {
3764 /* Reallocate Tx queues with the original ring size */
3765 port->tx_ring_size = prev_tx_ring_size;
3766 ring->tx_pending = prev_tx_ring_size;
3767 err = mvpp2_setup_txqs(port);
3768 if (err)
3769 goto err_clean_rxqs;
3770 }
3771
3772 mvpp2_start_dev(port);
3773 mvpp2_egress_enable(port);
3774 mvpp2_ingress_enable(port);
3775
3776 return 0;
3777
3778err_clean_rxqs:
3779 mvpp2_cleanup_rxqs(port);
3780err_out:
dfd4240a 3781 netdev_err(dev, "failed to change ring parameters");
3f518509
MW		 3782 return err;
3783}
3784
4bb04326
AT		 3785static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3786 struct ethtool_pauseparam *pause)
3787{
3788 struct mvpp2_port *port = netdev_priv(dev);
3789
3790 if (!port->phylink)
3791 return;
3792
3793 phylink_ethtool_get_pauseparam(port->phylink, pause);
3794}
3795
3796static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3797 struct ethtool_pauseparam *pause)
3798{
3799 struct mvpp2_port *port = netdev_priv(dev);
3800
3801 if (!port->phylink)
3802 return -ENOTSUPP;
3803
3804 return phylink_ethtool_set_pauseparam(port->phylink, pause);
3805}
3806
3807static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
3808 struct ethtool_link_ksettings *cmd)
3809{
3810 struct mvpp2_port *port = netdev_priv(dev);
3811
3812 if (!port->phylink)
3813 return -ENOTSUPP;
3814
3815 return phylink_ethtool_ksettings_get(port->phylink, cmd);
3816}
3817
3818static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
3819 const struct ethtool_link_ksettings *cmd)
3820{
3821 struct mvpp2_port *port = netdev_priv(dev);
3822
3823 if (!port->phylink)
3824 return -ENOTSUPP;
3825
3826 return phylink_ethtool_ksettings_set(port->phylink, cmd);
3827}
3828
8179642b
AT		 3829static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
3830 struct ethtool_rxnfc *info, u32 *rules)
3831{
3832 struct mvpp2_port *port = netdev_priv(dev);
436d4fdb 3833 int ret = 0;
8179642b
AT		 3834
3835 if (!mvpp22_rss_is_supported())
3836 return -EOPNOTSUPP;
3837
3838 switch (info->cmd) {
436d4fdb
MC		 3839 case ETHTOOL_GRXFH:
3840 ret = mvpp2_ethtool_rxfh_get(port, info);
3841 break;
8179642b
AT		 3842 case ETHTOOL_GRXRINGS:
3843 info->data = port->nrxqs;
3844 break;
3845 default:
3846 return -ENOTSUPP;
3847 }
3848
436d4fdb
MC		 3849 return ret;
3850}
3851
3852static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
3853 struct ethtool_rxnfc *info)
3854{
3855 struct mvpp2_port *port = netdev_priv(dev);
3856 int ret = 0;
3857
3858 if (!mvpp22_rss_is_supported())
3859 return -EOPNOTSUPP;
3860
3861 switch (info->cmd) {
3862 case ETHTOOL_SRXFH:
3863 ret = mvpp2_ethtool_rxfh_set(port, info);
3864 break;
3865 default:
3866 return -EOPNOTSUPP;
3867 }
3868 return ret;
8179642b
AT		 3869}
3870
3871static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
3872{
3873 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
3874}
3875
3876static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3877 u8 *hfunc)
3878{
3879 struct mvpp2_port *port = netdev_priv(dev);
3880
3881 if (!mvpp22_rss_is_supported())
3882 return -EOPNOTSUPP;
3883
3884 if (indir)
3885 memcpy(indir, port->indir,
3886 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3887
3888 if (hfunc)
3889 *hfunc = ETH_RSS_HASH_CRC32;
3890
3891 return 0;
3892}
3893
3894static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3895 const u8 *key, const u8 hfunc)
3896{
3897 struct mvpp2_port *port = netdev_priv(dev);
3898
3899 if (!mvpp22_rss_is_supported())
3900 return -EOPNOTSUPP;
3901
3902 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
3903 return -EOPNOTSUPP;
3904
3905 if (key)
3906 return -EOPNOTSUPP;
3907
3908 if (indir) {
3909 memcpy(port->indir, indir,
3910 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3911 mvpp22_rss_fill_table(port, port->id);
3912 }
3913
3914 return 0;
3915}
3916
3f518509
MW		 3917/* Device ops */
3918
3919static const struct net_device_ops mvpp2_netdev_ops = {
3920 .ndo_open = mvpp2_open,
3921 .ndo_stop = mvpp2_stop,
3922 .ndo_start_xmit = mvpp2_tx,
3923 .ndo_set_rx_mode = mvpp2_set_rx_mode,
3924 .ndo_set_mac_address = mvpp2_set_mac_address,
3925 .ndo_change_mtu = mvpp2_change_mtu,
3926 .ndo_get_stats64 = mvpp2_get_stats64,
bd695a5f 3927 .ndo_do_ioctl = mvpp2_ioctl,
56beda3d
MC		 3928 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
3929 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
3930 .ndo_set_features = mvpp2_set_features,
3f518509
MW		 3931};
3932
3933static const struct ethtool_ops mvpp2_eth_tool_ops = {
4bb04326 3934 .nway_reset = mvpp2_ethtool_nway_reset,
dcd3e73a
AT		 3935 .get_link = ethtool_op_get_link,
3936 .set_coalesce = mvpp2_ethtool_set_coalesce,
3937 .get_coalesce = mvpp2_ethtool_get_coalesce,
3938 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
3939 .get_ringparam = mvpp2_ethtool_get_ringparam,
3940 .set_ringparam = mvpp2_ethtool_set_ringparam,
3941 .get_strings = mvpp2_ethtool_get_strings,
3942 .get_ethtool_stats = mvpp2_ethtool_get_stats,
3943 .get_sset_count = mvpp2_ethtool_get_sset_count,
4bb04326
AT		 3944 .get_pauseparam = mvpp2_ethtool_get_pause_param,
3945 .set_pauseparam = mvpp2_ethtool_set_pause_param,
3946 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
3947 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
8179642b 3948 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
436d4fdb 3949 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
8179642b
AT		 3950 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
3951 .get_rxfh = mvpp2_ethtool_get_rxfh,
3952 .set_rxfh = mvpp2_ethtool_set_rxfh,
3953
3f518509
MW		 3954};
3955
213f428f
TP		 3956/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
3957 * had a single IRQ defined per-port.
3958 */
3959static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
3960 struct device_node *port_node)
591f4cfa
TP		 3961{
3962 struct mvpp2_queue_vector *v = &port->qvecs[0];
3963
3964 v->first_rxq = 0;
3965 v->nrxqs = port->nrxqs;
3966 v->type = MVPP2_QUEUE_VECTOR_SHARED;
3967 v->sw_thread_id = 0;
3968 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
3969 v->port = port;
3970 v->irq = irq_of_parse_and_map(port_node, 0);
3971 if (v->irq <= 0)
3972 return -EINVAL;
3973 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
3974 NAPI_POLL_WEIGHT);
3975
3976 port->nqvecs = 1;
3977
3978 return 0;
3979}
3980
213f428f
TP		 3981static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
3982 struct device_node *port_node)
3983{
3984 struct mvpp2_queue_vector *v;
3985 int i, ret;
3986
3987 port->nqvecs = num_possible_cpus();
3988 if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
3989 port->nqvecs += 1;
3990
3991 for (i = 0; i < port->nqvecs; i++) {
3992 char irqname[16];
3993
3994 v = port->qvecs + i;
3995
3996 v->port = port;
3997 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
3998 v->sw_thread_id = i;
3999 v->sw_thread_mask = BIT(i);
4000
4001 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4002
4003 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
4004 v->first_rxq = i * MVPP2_DEFAULT_RXQ;
4005 v->nrxqs = MVPP2_DEFAULT_RXQ;
4006 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4007 i == (port->nqvecs - 1)) {
4008 v->first_rxq = 0;
4009 v->nrxqs = port->nrxqs;
4010 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4011 strncpy(irqname, "rx-shared", sizeof(irqname));
4012 }
4013
a75edc7c
MW		 4014 if (port_node)
4015 v->irq = of_irq_get_byname(port_node, irqname);
4016 else
4017 v->irq = fwnode_irq_get(port->fwnode, i);
213f428f
TP		 4018 if (v->irq <= 0) {
4019 ret = -EINVAL;
4020 goto err;
4021 }
4022
4023 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4024 NAPI_POLL_WEIGHT);
4025 }
4026
4027 return 0;
4028
4029err:
4030 for (i = 0; i < port->nqvecs; i++)
4031 irq_dispose_mapping(port->qvecs[i].irq);
4032 return ret;
4033}
4034
4035static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4036 struct device_node *port_node)
4037{
4038 if (port->has_tx_irqs)
4039 return mvpp2_multi_queue_vectors_init(port, port_node);
4040 else
4041 return mvpp2_simple_queue_vectors_init(port, port_node);
4042}
4043
591f4cfa
TP		 4044static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4045{
4046 int i;
4047
4048 for (i = 0; i < port->nqvecs; i++)
4049 irq_dispose_mapping(port->qvecs[i].irq);
4050}
4051
4052/* Configure Rx queue group interrupt for this port */
4053static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4054{
4055 struct mvpp2 *priv = port->priv;
4056 u32 val;
4057 int i;
4058
4059 if (priv->hw_version == MVPP21) {
4060 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4061 port->nrxqs);
4062 return;
4063 }
4064
4065 /* Handle the more complicated PPv2.2 case */
4066 for (i = 0; i < port->nqvecs; i++) {
4067 struct mvpp2_queue_vector *qv = port->qvecs + i;
4068
4069 if (!qv->nrxqs)
4070 continue;
4071
4072 val = qv->sw_thread_id;
4073 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4074 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4075
4076 val = qv->first_rxq;
4077 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4078 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4079 }
4080}
4081
3f518509
MW		 4082/* Initialize port HW */
4083static int mvpp2_port_init(struct mvpp2_port *port)
4084{
4085 struct device *dev = port->dev->dev.parent;
4086 struct mvpp2 *priv = port->priv;
4087 struct mvpp2_txq_pcpu *txq_pcpu;
4088 int queue, cpu, err;
4089
09f83975
TP		 4090 /* Checks for hardware constraints */
4091 if (port->first_rxq + port->nrxqs >
59b9a31e 4092 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3f518509
MW		 4093 return -EINVAL;
4094
790d32c6
MC		 4095 if (port->nrxqs % MVPP2_DEFAULT_RXQ ||
4096 port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
09f83975
TP		 4097 return -EINVAL;
4098
3f518509
MW		 4099 /* Disable port */
4100 mvpp2_egress_disable(port);
4101 mvpp2_port_disable(port);
4102
213f428f
TP		 4103 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4104
09f83975 4105 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
3f518509
MW		 4106 GFP_KERNEL);
4107 if (!port->txqs)
4108 return -ENOMEM;
4109
4110 /* Associate physical Tx queues to this port and initialize.
4111 * The mapping is predefined.
4112 */
09f83975 4113 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4114 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4115 struct mvpp2_tx_queue *txq;
4116
4117 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
177c8d1c
CJ		 4118 if (!txq) {
4119 err = -ENOMEM;
4120 goto err_free_percpu;
4121 }
3f518509
MW		 4122
4123 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4124 if (!txq->pcpu) {
4125 err = -ENOMEM;
4126 goto err_free_percpu;
4127 }
4128
4129 txq->id = queue_phy_id;
4130 txq->log_id = queue;
4131 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4132 for_each_present_cpu(cpu) {
4133 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4134 txq_pcpu->cpu = cpu;
4135 }
4136
4137 port->txqs[queue] = txq;
4138 }
4139
09f83975 4140 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
3f518509
MW		 4141 GFP_KERNEL);
4142 if (!port->rxqs) {
4143 err = -ENOMEM;
4144 goto err_free_percpu;
4145 }
4146
4147 /* Allocate and initialize Rx queue for this port */
09f83975 4148 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4149 struct mvpp2_rx_queue *rxq;
4150
4151 /* Map physical Rx queue to port's logical Rx queue */
4152 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
d82b0c21
JZ		 4153 if (!rxq) {
4154 err = -ENOMEM;
3f518509 4155 goto err_free_percpu;
d82b0c21 4156 }
3f518509
MW		 4157 /* Map this Rx queue to a physical queue */
4158 rxq->id = port->first_rxq + queue;
4159 rxq->port = port->id;
4160 rxq->logic_rxq = queue;
4161
4162 port->rxqs[queue] = rxq;
4163 }
4164
591f4cfa 4165 mvpp2_rx_irqs_setup(port);
3f518509
MW		 4166
4167 /* Create Rx descriptor rings */
09f83975 4168 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4169 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4170
4171 rxq->size = port->rx_ring_size;
4172 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4173 rxq->time_coal = MVPP2_RX_COAL_USEC;
4174 }
4175
4176 mvpp2_ingress_disable(port);
4177
4178 /* Port default configuration */
4179 mvpp2_defaults_set(port);
4180
4181 /* Port's classifier configuration */
4182 mvpp2_cls_oversize_rxq_set(port);
4183 mvpp2_cls_port_config(port);
4184
e6e21c02
MC		 4185 if (mvpp22_rss_is_supported())
4186 mvpp22_rss_port_init(port);
4187
3f518509
MW		 4188 /* Provide an initial Rx packet size */
4189 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4190
4191 /* Initialize pools for swf */
4192 err = mvpp2_swf_bm_pool_init(port);
4193 if (err)
4194 goto err_free_percpu;
4195
4196 return 0;
4197
4198err_free_percpu:
09f83975 4199 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4200 if (!port->txqs[queue])
4201 continue;
4202 free_percpu(port->txqs[queue]->pcpu);
4203 }
4204 return err;
4205}
4206
213f428f
TP		 4207/* Checks if the port DT description has the TX interrupts
4208 * described. On PPv2.1, there are no such interrupts. On PPv2.2,
4209 * there are available, but we need to keep support for old DTs.
4210 */
4211static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv,
4212 struct device_node *port_node)
4213{
4214 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1",
4215 "tx-cpu2", "tx-cpu3" };
4216 int ret, i;
4217
4218 if (priv->hw_version == MVPP21)
4219 return false;
4220
4221 for (i = 0; i < 5; i++) {
4222 ret = of_property_match_string(port_node, "interrupt-names",
4223 irqs[i]);
4224 if (ret < 0)
4225 return false;
4226 }
4227
4228 return true;
4229}
4230
3ba8c81e 4231static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
24812221 4232 struct fwnode_handle *fwnode,
3ba8c81e
AT		 4233 char **mac_from)
4234{
4235 struct mvpp2_port *port = netdev_priv(dev);
4236 char hw_mac_addr[ETH_ALEN] = {0};
24812221 4237 char fw_mac_addr[ETH_ALEN];
3ba8c81e 4238
24812221
MW		 4239 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4240 *mac_from = "firmware node";
4241 ether_addr_copy(dev->dev_addr, fw_mac_addr);
688cbaf2
AT		 4242 return;
4243 }
d2a6e48e 4244
688cbaf2
AT		 4245 if (priv->hw_version == MVPP21) {
4246 mvpp21_get_mac_address(port, hw_mac_addr);
4247 if (is_valid_ether_addr(hw_mac_addr)) {
4248 *mac_from = "hardware";
4249 ether_addr_copy(dev->dev_addr, hw_mac_addr);
4250 return;
4251 }
3ba8c81e 4252 }
688cbaf2
AT		 4253
4254 *mac_from = "random";
4255 eth_hw_addr_random(dev);
3ba8c81e
AT		 4256}
4257
4bb04326
AT		 4258static void mvpp2_phylink_validate(struct net_device *dev,
4259 unsigned long *supported,
4260 struct phylink_link_state *state)
4261{
4262 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4263
4264 phylink_set(mask, Autoneg);
4265 phylink_set_port_modes(mask);
4266 phylink_set(mask, Pause);
4267 phylink_set(mask, Asym_Pause);
4268
d97c9f4a
AT		 4269 switch (state->interface) {
4270 case PHY_INTERFACE_MODE_10GKR:
4bb04326
AT		 4271 phylink_set(mask, 10000baseCR_Full);
4272 phylink_set(mask, 10000baseSR_Full);
4273 phylink_set(mask, 10000baseLR_Full);
4274 phylink_set(mask, 10000baseLRM_Full);
4275 phylink_set(mask, 10000baseER_Full);
4276 phylink_set(mask, 10000baseKR_Full);
d97c9f4a
AT		 4277 /* Fall-through */
4278 default:
4279 phylink_set(mask, 10baseT_Half);
4280 phylink_set(mask, 10baseT_Full);
4281 phylink_set(mask, 100baseT_Half);
4282 phylink_set(mask, 100baseT_Full);
4283 phylink_set(mask, 10000baseT_Full);
4284 /* Fall-through */
4285 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 4286 case PHY_INTERFACE_MODE_2500BASEX:
d97c9f4a
AT		 4287 phylink_set(mask, 1000baseT_Full);
4288 phylink_set(mask, 1000baseX_Full);
a6fe31de 4289 phylink_set(mask, 2500baseX_Full);
4bb04326
AT		 4290 }
4291
4292 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4293 bitmap_and(state->advertising, state->advertising, mask,
4294 __ETHTOOL_LINK_MODE_MASK_NBITS);
4295}
4296
4297static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4298 struct phylink_link_state *state)
4299{
4300 u32 val;
4301
4302 state->speed = SPEED_10000;
4303 state->duplex = 1;
4304 state->an_complete = 1;
4305
4306 val = readl(port->base + MVPP22_XLG_STATUS);
4307 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4308
4309 state->pause = 0;
4310 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4311 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4312 state->pause |= MLO_PAUSE_TX;
4313 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4314 state->pause |= MLO_PAUSE_RX;
4315}
4316
4317static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4318 struct phylink_link_state *state)
4319{
4320 u32 val;
4321
4322 val = readl(port->base + MVPP2_GMAC_STATUS0);
4323
4324 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4325 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4326 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4327
d97c9f4a
AT		 4328 switch (port->phy_interface) {
4329 case PHY_INTERFACE_MODE_1000BASEX:
4bb04326 4330 state->speed = SPEED_1000;
d97c9f4a 4331 break;
a6fe31de
AT		 4332 case PHY_INTERFACE_MODE_2500BASEX:
4333 state->speed = SPEED_2500;
4334 break;
d97c9f4a
AT		 4335 default:
4336 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4337 state->speed = SPEED_1000;
4338 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4339 state->speed = SPEED_100;
4340 else
4341 state->speed = SPEED_10;
4342 }
4bb04326
AT		 4343
4344 state->pause = 0;
4345 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4346 state->pause |= MLO_PAUSE_RX;
4347 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4348 state->pause |= MLO_PAUSE_TX;
4349}
4350
4351static int mvpp2_phylink_mac_link_state(struct net_device *dev,
4352 struct phylink_link_state *state)
4353{
4354 struct mvpp2_port *port = netdev_priv(dev);
4355
4356 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4357 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4358 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4359
4360 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4361 mvpp22_xlg_link_state(port, state);
4362 return 1;
4363 }
4364 }
4365
4366 mvpp2_gmac_link_state(port, state);
4367 return 1;
4368}
4369
4370static void mvpp2_mac_an_restart(struct net_device *dev)
4371{
4372 struct mvpp2_port *port = netdev_priv(dev);
4373 u32 val;
4374
4375 if (port->phy_interface != PHY_INTERFACE_MODE_SGMII)
4376 return;
4377
4378 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4379 /* The RESTART_AN bit is cleared by the h/w after restarting the AN
4380 * process.
4381 */
4382 val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG;
4383 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4384}
4385
4386static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4387 const struct phylink_link_state *state)
4388{
4389 u32 ctrl0, ctrl4;
4390
4391 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4392 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4393
4394 if (state->pause & MLO_PAUSE_TX)
4395 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4396 if (state->pause & MLO_PAUSE_RX)
4397 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4398
4399 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
4400 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
4401 MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
4402
4403 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4404 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
4405}
4406
4407static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4408 const struct phylink_link_state *state)
4409{
4410 u32 an, ctrl0, ctrl2, ctrl4;
4411
4412 an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4413 ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4414 ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4415 ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4416
4417 /* Force link down */
4418 an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4419 an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4420 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4421
4422 /* Set the GMAC in a reset state */
4423 ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4424 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4425
4426 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4427 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4428 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4429 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4430 MVPP2_GMAC_FORCE_LINK_DOWN);
4431 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4432 ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
4433
a6fe31de
AT		 4434 if (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4435 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4436 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4437 * they negotiate duplex: they are always operating with a fixed
4438 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4439 * speed and full duplex here.
d97c9f4a
AT		 4440 */
4441 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4442 an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
4443 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4444 } else if (!phy_interface_mode_is_rgmii(state->interface)) {
4bb04326 4445 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
d97c9f4a 4446 }
4bb04326
AT		 4447
4448 if (state->duplex)
4449 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4450 if (phylink_test(state->advertising, Pause))
4451 an |= MVPP2_GMAC_FC_ADV_EN;
4452 if (phylink_test(state->advertising, Asym_Pause))
4453 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4454
d97c9f4a 4455 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 4456 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4457 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4bb04326
AT		 4458 an |= MVPP2_GMAC_IN_BAND_AUTONEG;
4459 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
4460
4461 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4462 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4463 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4464 MVPP22_CTRL4_DP_CLK_SEL |
4465 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4466
4467 if (state->pause & MLO_PAUSE_TX)
4468 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4469 if (state->pause & MLO_PAUSE_RX)
4470 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4471 } else if (phy_interface_mode_is_rgmii(state->interface)) {
4472 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS;
4473
4474 if (state->speed == SPEED_1000)
4475 an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4476 else if (state->speed == SPEED_100)
4477 an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4478
4479 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4480 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4481 MVPP22_CTRL4_SYNC_BYPASS_DIS |
4482 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4483 }
4484
4485 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4486 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4487 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4488 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4489}
4490
4491static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
4492 const struct phylink_link_state *state)
4493{
4494 struct mvpp2_port *port = netdev_priv(dev);
4495
4496 /* Check for invalid configuration */
4497 if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
4498 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4499 return;
4500 }
4501
4bb04326
AT		 4502 /* Make sure the port is disabled when reconfiguring the mode */
4503 mvpp2_port_disable(port);
4504
4505 if (port->priv->hw_version == MVPP22 &&
4506 port->phy_interface != state->interface) {
4507 port->phy_interface = state->interface;
4508
4509 /* Reconfigure the serdes lanes */
4510 phy_power_off(port->comphy);
4511 mvpp22_mode_reconfigure(port);
4512 }
4513
4514 /* mac (re)configuration */
4515 if (state->interface == PHY_INTERFACE_MODE_10GKR)
4516 mvpp2_xlg_config(port, mode, state);
4517 else if (phy_interface_mode_is_rgmii(state->interface) ||
d97c9f4a 4518 state->interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 4519 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4520 state->interface == PHY_INTERFACE_MODE_2500BASEX)
4bb04326
AT		 4521 mvpp2_gmac_config(port, mode, state);
4522
4523 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4524 mvpp2_port_loopback_set(port, state);
4525
41948ccb 4526 mvpp2_port_enable(port);
4bb04326
AT		 4527}
4528
4529static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
4530 phy_interface_t interface, struct phy_device *phy)
4531{
4532 struct mvpp2_port *port = netdev_priv(dev);
4533 u32 val;
4534
4535 if (!phylink_autoneg_inband(mode) &&
4536 interface != PHY_INTERFACE_MODE_10GKR) {
4537 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4538 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4539 if (phy_interface_mode_is_rgmii(interface))
4540 val |= MVPP2_GMAC_FORCE_LINK_PASS;
4541 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4542 }
4543
4544 mvpp2_port_enable(port);
4545
4546 mvpp2_egress_enable(port);
4547 mvpp2_ingress_enable(port);
4548 netif_tx_wake_all_queues(dev);
4549}
4550
4551static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
4552 phy_interface_t interface)
4553{
4554 struct mvpp2_port *port = netdev_priv(dev);
4555 u32 val;
4556
4557 if (!phylink_autoneg_inband(mode) &&
4558 interface != PHY_INTERFACE_MODE_10GKR) {
4559 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4560 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4561 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4562 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4563 }
4564
4565 netif_tx_stop_all_queues(dev);
4566 mvpp2_egress_disable(port);
4567 mvpp2_ingress_disable(port);
4568
4569 /* When using link interrupts to notify phylink of a MAC state change,
4570 * we do not want the port to be disabled (we want to receive further
4571 * interrupts, to be notified when the port will have a link later).
4572 */
4573 if (!port->has_phy)
4574 return;
4575
4576 mvpp2_port_disable(port);
4577}
4578
4579static const struct phylink_mac_ops mvpp2_phylink_ops = {
4580 .validate = mvpp2_phylink_validate,
4581 .mac_link_state = mvpp2_phylink_mac_link_state,
4582 .mac_an_restart = mvpp2_mac_an_restart,
4583 .mac_config = mvpp2_mac_config,
4584 .mac_link_up = mvpp2_mac_link_up,
4585 .mac_link_down = mvpp2_mac_link_down,
4586};
4587
3f518509
MW		 4588/* Ports initialization */
4589static int mvpp2_port_probe(struct platform_device *pdev,
24812221 4590 struct fwnode_handle *port_fwnode,
bf147153 4591 struct mvpp2 *priv)
3f518509 4592{
a75edc7c 4593 struct phy *comphy = NULL;
3f518509 4594 struct mvpp2_port *port;
edc660fa 4595 struct mvpp2_port_pcpu *port_pcpu;
24812221 4596 struct device_node *port_node = to_of_node(port_fwnode);
3f518509
MW		 4597 struct net_device *dev;
4598 struct resource *res;
4bb04326 4599 struct phylink *phylink;
3ba8c81e 4600 char *mac_from = "";
09f83975 4601 unsigned int ntxqs, nrxqs;
213f428f 4602 bool has_tx_irqs;
3f518509
MW		 4603 u32 id;
4604 int features;
4605 int phy_mode;
edc660fa 4606 int err, i, cpu;
3f518509 4607
a75edc7c
MW		 4608 if (port_node) {
4609 has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node);
4610 } else {
4611 has_tx_irqs = true;
4612 queue_mode = MVPP2_QDIST_MULTI_MODE;
4613 }
213f428f
TP		 4614
4615 if (!has_tx_irqs)
4616 queue_mode = MVPP2_QDIST_SINGLE_MODE;
4617
09f83975 4618 ntxqs = MVPP2_MAX_TXQ;
213f428f
TP		 4619 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE)
4620 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus();
4621 else
4622 nrxqs = MVPP2_DEFAULT_RXQ;
09f83975
TP		 4623
4624 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
3f518509
MW		 4625 if (!dev)
4626 return -ENOMEM;
4627
24812221 4628 phy_mode = fwnode_get_phy_mode(port_fwnode);
3f518509
MW		 4629 if (phy_mode < 0) {
4630 dev_err(&pdev->dev, "incorrect phy mode\n");
4631 err = phy_mode;
4632 goto err_free_netdev;
4633 }
4634
a75edc7c
MW		 4635 if (port_node) {
4636 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
4637 if (IS_ERR(comphy)) {
4638 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
4639 err = -EPROBE_DEFER;
4640 goto err_free_netdev;
4641 }
4642 comphy = NULL;
542897d9 4643 }
542897d9
AT		 4644 }
4645
24812221 4646 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
3f518509
MW		 4647 err = -EINVAL;
4648 dev_err(&pdev->dev, "missing port-id value\n");
4649 goto err_free_netdev;
4650 }
4651
7cf87e4a 4652 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
3f518509
MW		 4653 dev->watchdog_timeo = 5 * HZ;
4654 dev->netdev_ops = &mvpp2_netdev_ops;
4655 dev->ethtool_ops = &mvpp2_eth_tool_ops;
4656
4657 port = netdev_priv(dev);
591f4cfa 4658 port->dev = dev;
a75edc7c 4659 port->fwnode = port_fwnode;
4bb04326 4660 port->has_phy = !!of_find_property(port_node, "phy", NULL);
09f83975
TP		 4661 port->ntxqs = ntxqs;
4662 port->nrxqs = nrxqs;
213f428f
TP		 4663 port->priv = priv;
4664 port->has_tx_irqs = has_tx_irqs;
3f518509 4665
591f4cfa
TP		 4666 err = mvpp2_queue_vectors_init(port, port_node);
4667 if (err)
3f518509 4668 goto err_free_netdev;
3f518509 4669
a75edc7c
MW		 4670 if (port_node)
4671 port->link_irq = of_irq_get_byname(port_node, "link");
4672 else
4673 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
fd3651b2
AT		 4674 if (port->link_irq == -EPROBE_DEFER) {
4675 err = -EPROBE_DEFER;
4676 goto err_deinit_qvecs;
4677 }
4678 if (port->link_irq <= 0)
4679 /* the link irq is optional */
4680 port->link_irq = 0;
4681
24812221 4682 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
3f518509
MW		 4683 port->flags |= MVPP2_F_LOOPBACK;
4684
3f518509 4685 port->id = id;
59b9a31e 4686 if (priv->hw_version == MVPP21)
09f83975 4687 port->first_rxq = port->id * port->nrxqs;
59b9a31e
TP		 4688 else
4689 port->first_rxq = port->id * priv->max_port_rxqs;
4690
4bb04326 4691 port->of_node = port_node;
3f518509 4692 port->phy_interface = phy_mode;
542897d9 4693 port->comphy = comphy;
3f518509 4694
a786841d
TP		 4695 if (priv->hw_version == MVPP21) {
4696 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
4697 port->base = devm_ioremap_resource(&pdev->dev, res);
4698 if (IS_ERR(port->base)) {
4699 err = PTR_ERR(port->base);
fd3651b2 4700 goto err_free_irq;
a786841d 4701 }
118d6298
MR		 4702
4703 port->stats_base = port->priv->lms_base +
4704 MVPP21_MIB_COUNTERS_OFFSET +
4705 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
a786841d 4706 } else {
24812221
MW		 4707 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
4708 &port->gop_id)) {
a786841d
TP		 4709 err = -EINVAL;
4710 dev_err(&pdev->dev, "missing gop-port-id value\n");
591f4cfa 4711 goto err_deinit_qvecs;
a786841d
TP		 4712 }
4713
4714 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
118d6298
MR		 4715 port->stats_base = port->priv->iface_base +
4716 MVPP22_MIB_COUNTERS_OFFSET +
4717 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
3f518509
MW		 4718 }
4719
118d6298 4720 /* Alloc per-cpu and ethtool stats */
3f518509
MW		 4721 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
4722 if (!port->stats) {
4723 err = -ENOMEM;
fd3651b2 4724 goto err_free_irq;
3f518509
MW		 4725 }
4726
118d6298
MR		 4727 port->ethtool_stats = devm_kcalloc(&pdev->dev,
4728 ARRAY_SIZE(mvpp2_ethtool_regs),
4729 sizeof(u64), GFP_KERNEL);
4730 if (!port->ethtool_stats) {
4731 err = -ENOMEM;
4732 goto err_free_stats;
4733 }
4734
e5c500eb
MR		 4735 mutex_init(&port->gather_stats_lock);
4736 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
4737
24812221 4738 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
3f518509 4739
7cf87e4a
YM		 4740 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
4741 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
3f518509
MW		 4742 SET_NETDEV_DEV(dev, &pdev->dev);
4743
4744 err = mvpp2_port_init(port);
4745 if (err < 0) {
4746 dev_err(&pdev->dev, "failed to init port %d\n", id);
4747 goto err_free_stats;
4748 }
26975821 4749
26975821
TP		 4750 mvpp2_port_periodic_xon_disable(port);
4751
26975821 4752 mvpp2_port_reset(port);
3f518509 4753
edc660fa
MW		 4754 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
4755 if (!port->pcpu) {
4756 err = -ENOMEM;
4757 goto err_free_txq_pcpu;
4758 }
4759
213f428f
TP		 4760 if (!port->has_tx_irqs) {
4761 for_each_present_cpu(cpu) {
4762 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
edc660fa 4763
213f428f
TP		 4764 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
4765 HRTIMER_MODE_REL_PINNED);
4766 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
4767 port_pcpu->timer_scheduled = false;
edc660fa 4768
213f428f
TP		 4769 tasklet_init(&port_pcpu->tx_done_tasklet,
4770 mvpp2_tx_proc_cb,
4771 (unsigned long)dev);
4772 }
edc660fa
MW		 4773 }
4774
381c5671
AT		 4775 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4776 NETIF_F_TSO;
3f518509 4777 dev->features = features | NETIF_F_RXCSUM;
56beda3d
MC		 4778 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
4779 NETIF_F_HW_VLAN_CTAG_FILTER;
576193f2 4780
d33ec452
MC		 4781 if (mvpp22_rss_is_supported())
4782 dev->hw_features |= NETIF_F_RXHASH;
4783
576193f2
SC		 4784 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) {
4785 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4786 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4787 }
4788
3f518509 4789 dev->vlan_features |= features;
1d17db08 4790 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
10fea26c 4791 dev->priv_flags |= IFF_UNICAST_FLT;
3f518509 4792
576193f2 4793 /* MTU range: 68 - 9704 */
5777987e 4794 dev->min_mtu = ETH_MIN_MTU;
576193f2
SC		 4795 /* 9704 == 9728 - 20 and rounding to 8 */
4796 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
c4053ef3 4797 dev->dev.of_node = port_node;
5777987e 4798
4bb04326
AT		 4799 /* Phylink isn't used w/ ACPI as of now */
4800 if (port_node) {
4801 phylink = phylink_create(dev, port_fwnode, phy_mode,
4802 &mvpp2_phylink_ops);
4803 if (IS_ERR(phylink)) {
4804 err = PTR_ERR(phylink);
4805 goto err_free_port_pcpu;
4806 }
4807 port->phylink = phylink;
4808 } else {
4809 port->phylink = NULL;
4810 }
4811
3f518509
MW		 4812 err = register_netdev(dev);
4813 if (err < 0) {
4814 dev_err(&pdev->dev, "failed to register netdev\n");
4bb04326 4815 goto err_phylink;
3f518509
MW		 4816 }
4817 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
4818
bf147153
MW		 4819 priv->port_list[priv->port_count++] = port;
4820
3f518509
MW		 4821 return 0;
4822
4bb04326
AT		 4823err_phylink:
4824 if (port->phylink)
4825 phylink_destroy(port->phylink);
edc660fa
MW		 4826err_free_port_pcpu:
4827 free_percpu(port->pcpu);
3f518509 4828err_free_txq_pcpu:
09f83975 4829 for (i = 0; i < port->ntxqs; i++)
3f518509
MW		 4830 free_percpu(port->txqs[i]->pcpu);
4831err_free_stats:
4832 free_percpu(port->stats);
fd3651b2
AT		 4833err_free_irq:
4834 if (port->link_irq)
4835 irq_dispose_mapping(port->link_irq);
591f4cfa
TP		 4836err_deinit_qvecs:
4837 mvpp2_queue_vectors_deinit(port);
3f518509
MW		 4838err_free_netdev:
4839 free_netdev(dev);
4840 return err;
4841}
4842
4843/* Ports removal routine */
4844static void mvpp2_port_remove(struct mvpp2_port *port)
4845{
4846 int i;
4847
4848 unregister_netdev(port->dev);
4bb04326
AT		 4849 if (port->phylink)
4850 phylink_destroy(port->phylink);
edc660fa 4851 free_percpu(port->pcpu);
3f518509 4852 free_percpu(port->stats);
09f83975 4853 for (i = 0; i < port->ntxqs; i++)
3f518509 4854 free_percpu(port->txqs[i]->pcpu);
591f4cfa 4855 mvpp2_queue_vectors_deinit(port);
fd3651b2
AT		 4856 if (port->link_irq)
4857 irq_dispose_mapping(port->link_irq);
3f518509
MW		 4858 free_netdev(port->dev);
4859}
4860
4861/* Initialize decoding windows */
4862static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4863 struct mvpp2 *priv)
4864{
4865 u32 win_enable;
4866 int i;
4867
4868 for (i = 0; i < 6; i++) {
4869 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4870 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4871
4872 if (i < 4)
4873 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4874 }
4875
4876 win_enable = 0;
4877
4878 for (i = 0; i < dram->num_cs; i++) {
4879 const struct mbus_dram_window *cs = dram->cs + i;
4880
4881 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4882 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4883 dram->mbus_dram_target_id);
4884
4885 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4886 (cs->size - 1) & 0xffff0000);
4887
4888 win_enable |= (1 << i);
4889 }
4890
4891 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4892}
4893
4894/* Initialize Rx FIFO's */
4895static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4896{
4897 int port;
4898
4899 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4900 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
2d1d7df8 4901 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
3f518509 4902 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
2d1d7df8
AT		 4903 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
4904 }
4905
4906 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4907 MVPP2_RX_FIFO_PORT_MIN_PKT);
4908 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4909}
4910
4911static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
4912{
4913 int port;
4914
4915 /* The FIFO size parameters are set depending on the maximum speed a
4916 * given port can handle:
4917 * - Port 0: 10Gbps
4918 * - Port 1: 2.5Gbps
4919 * - Ports 2 and 3: 1Gbps
4920 */
4921
4922 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
4923 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
4924 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
4925 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
4926
4927 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
4928 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
4929 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
4930 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
4931
4932 for (port = 2; port < MVPP2_MAX_PORTS; port++) {
4933 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4934 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
4935 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4936 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
3f518509
MW		 4937 }
4938
4939 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4940 MVPP2_RX_FIFO_PORT_MIN_PKT);
4941 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4942}
4943
93ff130f
YM		 4944/* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
4945 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
4946 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
4947 */
7c10f974
AT		 4948static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
4949{
93ff130f 4950 int port, size, thrs;
7c10f974 4951
93ff130f
YM		 4952 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4953 if (port == 0) {
4954 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
4955 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
4956 } else {
4957 size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
4958 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
4959 }
4960 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
4961 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
4962 }
7c10f974
AT		 4963}
4964
6763ce31
TP		 4965static void mvpp2_axi_init(struct mvpp2 *priv)
4966{
4967 u32 val, rdval, wrval;
4968
4969 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4970
4971 /* AXI Bridge Configuration */
4972
4973 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4974 << MVPP22_AXI_ATTR_CACHE_OFFS;
4975 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4976 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4977
4978 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4979 << MVPP22_AXI_ATTR_CACHE_OFFS;
4980 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4981 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4982
4983 /* BM */
4984 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4985 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4986
4987 /* Descriptors */
4988 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4989 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4990 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4991 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4992
4993 /* Buffer Data */
4994 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4995 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4996
4997 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4998 << MVPP22_AXI_CODE_CACHE_OFFS;
4999 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5000 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5001 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5002 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5003
5004 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5005 << MVPP22_AXI_CODE_CACHE_OFFS;
5006 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5007 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5008
5009 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5010
5011 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5012 << MVPP22_AXI_CODE_CACHE_OFFS;
5013 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5014 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5015
5016 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5017}
5018
3f518509
MW		 5019/* Initialize network controller common part HW */
5020static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5021{
5022 const struct mbus_dram_target_info *dram_target_info;
5023 int err, i;
08a23755 5024 u32 val;
3f518509 5025
3f518509
MW		 5026 /* MBUS windows configuration */
5027 dram_target_info = mv_mbus_dram_info();
5028 if (dram_target_info)
5029 mvpp2_conf_mbus_windows(dram_target_info, priv);
5030
6763ce31
TP		 5031 if (priv->hw_version == MVPP22)
5032 mvpp2_axi_init(priv);
5033
08a23755 5034 /* Disable HW PHY polling */
26975821
TP		 5035 if (priv->hw_version == MVPP21) {
5036 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5037 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5038 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5039 } else {
5040 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5041 val &= ~MVPP22_SMI_POLLING_EN;
5042 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5043 }
08a23755 5044
3f518509
MW		 5045 /* Allocate and initialize aggregated TXQs */
5046 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(),
d7ce3cec 5047 sizeof(*priv->aggr_txqs),
3f518509
MW		 5048 GFP_KERNEL);
5049 if (!priv->aggr_txqs)
5050 return -ENOMEM;
5051
5052 for_each_present_cpu(i) {
5053 priv->aggr_txqs[i].id = i;
5054 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
85affd7e 5055 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
3f518509
MW		 5056 if (err < 0)
5057 return err;
5058 }
5059
7c10f974
AT		 5060 /* Fifo Init */
5061 if (priv->hw_version == MVPP21) {
2d1d7df8 5062 mvpp2_rx_fifo_init(priv);
7c10f974 5063 } else {
2d1d7df8 5064 mvpp22_rx_fifo_init(priv);
7c10f974
AT		 5065 mvpp22_tx_fifo_init(priv);
5066 }
3f518509 5067
26975821
TP		 5068 if (priv->hw_version == MVPP21)
5069 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5070 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3f518509
MW		 5071
5072 /* Allow cache snoop when transmiting packets */
5073 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5074
5075 /* Buffer Manager initialization */
5076 err = mvpp2_bm_init(pdev, priv);
5077 if (err < 0)
5078 return err;
5079
5080 /* Parser default initialization */
5081 err = mvpp2_prs_default_init(pdev, priv);
5082 if (err < 0)
5083 return err;
5084
5085 /* Classifier default initialization */
5086 mvpp2_cls_init(priv);
5087
5088 return 0;
5089}
5090
5091static int mvpp2_probe(struct platform_device *pdev)
5092{
a75edc7c 5093 const struct acpi_device_id *acpi_id;
24812221
MW		 5094 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5095 struct fwnode_handle *port_fwnode;
3f518509
MW		 5096 struct mvpp2 *priv;
5097 struct resource *res;
a786841d 5098 void __iomem *base;
118d6298 5099 int i;
3f518509
MW		 5100 int err;
5101
0b92e594 5102 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
3f518509
MW		 5103 if (!priv)
5104 return -ENOMEM;
5105
a75edc7c
MW		 5106 if (has_acpi_companion(&pdev->dev)) {
5107 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5108 &pdev->dev);
5109 priv->hw_version = (unsigned long)acpi_id->driver_data;
5110 } else {
5111 priv->hw_version =
5112 (unsigned long)of_device_get_match_data(&pdev->dev);
5113 }
faca9247 5114
1e27a628
MC		 5115 /* multi queue mode isn't supported on PPV2.1, fallback to single
5116 * mode
5117 */
5118 if (priv->hw_version == MVPP21)
5119 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5120
3f518509 5121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a786841d
TP		 5122 base = devm_ioremap_resource(&pdev->dev, res);
5123 if (IS_ERR(base))
5124 return PTR_ERR(base);
5125
5126 if (priv->hw_version == MVPP21) {
5127 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5128 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5129 if (IS_ERR(priv->lms_base))
5130 return PTR_ERR(priv->lms_base);
5131 } else {
5132 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
a75edc7c
MW		 5133 if (has_acpi_companion(&pdev->dev)) {
5134 /* In case the MDIO memory region is declared in
5135 * the ACPI, it can already appear as 'in-use'
5136 * in the OS. Because it is overlapped by second
5137 * region of the network controller, make
5138 * sure it is released, before requesting it again.
5139 * The care is taken by mvpp2 driver to avoid
5140 * concurrent access to this memory region.
5141 */
5142 release_resource(res);
5143 }
a786841d
TP		 5144 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5145 if (IS_ERR(priv->iface_base))
5146 return PTR_ERR(priv->iface_base);
a75edc7c 5147 }
f84bf386 5148
a75edc7c 5149 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
f84bf386
AT		 5150 priv->sysctrl_base =
5151 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5152 "marvell,system-controller");
5153 if (IS_ERR(priv->sysctrl_base))
5154 /* The system controller regmap is optional for dt
5155 * compatibility reasons. When not provided, the
5156 * configuration of the GoP relies on the
5157 * firmware/bootloader.
5158 */
5159 priv->sysctrl_base = NULL;
a786841d
TP		 5160 }
5161
01d04936
SC		 5162 mvpp2_setup_bm_pool();
5163
df089aa0 5164 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
a786841d
TP		 5165 u32 addr_space_sz;
5166
5167 addr_space_sz = (priv->hw_version == MVPP21 ?
5168 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
df089aa0 5169 priv->swth_base[i] = base + i * addr_space_sz;
a786841d 5170 }
3f518509 5171
59b9a31e
TP		 5172 if (priv->hw_version == MVPP21)
5173 priv->max_port_rxqs = 8;
5174 else
5175 priv->max_port_rxqs = 32;
5176
a75edc7c
MW		 5177 if (dev_of_node(&pdev->dev)) {
5178 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5179 if (IS_ERR(priv->pp_clk))
5180 return PTR_ERR(priv->pp_clk);
5181 err = clk_prepare_enable(priv->pp_clk);
5182 if (err < 0)
5183 return err;
3f518509 5184
a75edc7c
MW		 5185 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5186 if (IS_ERR(priv->gop_clk)) {
5187 err = PTR_ERR(priv->gop_clk);
5188 goto err_pp_clk;
fceb55d4 5189 }
a75edc7c 5190 err = clk_prepare_enable(priv->gop_clk);
fceb55d4 5191 if (err < 0)
a75edc7c
MW		 5192 goto err_pp_clk;
5193
5194 if (priv->hw_version == MVPP22) {
5195 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5196 if (IS_ERR(priv->mg_clk)) {
5197 err = PTR_ERR(priv->mg_clk);
5198 goto err_gop_clk;
5199 }
5200
5201 err = clk_prepare_enable(priv->mg_clk);
5202 if (err < 0)
5203 goto err_gop_clk;
9af771ce
MC		 5204
5205 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5206 if (IS_ERR(priv->mg_core_clk)) {
5207 priv->mg_core_clk = NULL;
5208 } else {
5209 err = clk_prepare_enable(priv->mg_core_clk);
5210 if (err < 0)
5211 goto err_mg_clk;
5212 }
a75edc7c 5213 }
4792ea04
GC		 5214
5215 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5216 if (IS_ERR(priv->axi_clk)) {
5217 err = PTR_ERR(priv->axi_clk);
5218 if (err == -EPROBE_DEFER)
9af771ce 5219 goto err_mg_core_clk;
4792ea04
GC		 5220 priv->axi_clk = NULL;
5221 } else {
5222 err = clk_prepare_enable(priv->axi_clk);
5223 if (err < 0)
9af771ce 5224 goto err_mg_core_clk;
4792ea04 5225 }
fceb55d4 5226
a75edc7c
MW		 5227 /* Get system's tclk rate */
5228 priv->tclk = clk_get_rate(priv->pp_clk);
5229 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5230 &priv->tclk)) {
5231 dev_err(&pdev->dev, "missing clock-frequency value\n");
5232 return -EINVAL;
5233 }
3f518509 5234
2067e0a1 5235 if (priv->hw_version == MVPP22) {
da42bb27 5236 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
2067e0a1 5237 if (err)
45f972ad 5238 goto err_axi_clk;
2067e0a1
TP		 5239 /* Sadly, the BM pools all share the same register to
5240 * store the high 32 bits of their address. So they
5241 * must all have the same high 32 bits, which forces
5242 * us to restrict coherent memory to DMA_BIT_MASK(32).
5243 */
5244 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5245 if (err)
45f972ad 5246 goto err_axi_clk;
2067e0a1
TP		 5247 }
5248
3f518509
MW		 5249 /* Initialize network controller */
5250 err = mvpp2_init(pdev, priv);
5251 if (err < 0) {
5252 dev_err(&pdev->dev, "failed to initialize controller\n");
45f972ad 5253 goto err_axi_clk;
3f518509
MW		 5254 }
5255
3f518509 5256 /* Initialize ports */
24812221
MW		 5257 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5258 err = mvpp2_port_probe(pdev, port_fwnode, priv);
3f518509 5259 if (err < 0)
26146b0e 5260 goto err_port_probe;
bf147153
MW		 5261 }
5262
5263 if (priv->port_count == 0) {
5264 dev_err(&pdev->dev, "no ports enabled\n");
5265 err = -ENODEV;
45f972ad 5266 goto err_axi_clk;
3f518509
MW		 5267 }
5268
118d6298
MR		 5269 /* Statistics must be gathered regularly because some of them (like
5270 * packets counters) are 32-bit registers and could overflow quite
5271 * quickly. For instance, a 10Gb link used at full bandwidth with the
5272 * smallest packets (64B) will overflow a 32-bit counter in less than
5273 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5274 */
118d6298
MR		 5275 snprintf(priv->queue_name, sizeof(priv->queue_name),
5276 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5277 priv->port_count > 1 ? "+" : "");
5278 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5279 if (!priv->stats_queue) {
5280 err = -ENOMEM;
26146b0e 5281 goto err_port_probe;
118d6298
MR		 5282 }
5283
21da57a2
MC		 5284 mvpp2_dbgfs_init(priv, pdev->name);
5285
3f518509
MW		 5286 platform_set_drvdata(pdev, priv);
5287 return 0;
5288
26146b0e
AT		 5289err_port_probe:
5290 i = 0;
24812221 5291 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
26146b0e
AT		 5292 if (priv->port_list[i])
5293 mvpp2_port_remove(priv->port_list[i]);
5294 i++;
5295 }
45f972ad 5296err_axi_clk:
4792ea04 5297 clk_disable_unprepare(priv->axi_clk);
9af771ce
MC		 5298
5299err_mg_core_clk:
5300 if (priv->hw_version == MVPP22)
5301 clk_disable_unprepare(priv->mg_core_clk);
45f972ad 5302err_mg_clk:
fceb55d4
TP		 5303 if (priv->hw_version == MVPP22)
5304 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5305err_gop_clk:
5306 clk_disable_unprepare(priv->gop_clk);
5307err_pp_clk:
5308 clk_disable_unprepare(priv->pp_clk);
5309 return err;
5310}
5311
5312static int mvpp2_remove(struct platform_device *pdev)
5313{
5314 struct mvpp2 *priv = platform_get_drvdata(pdev);
24812221
MW		 5315 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5316 struct fwnode_handle *port_fwnode;
3f518509
MW		 5317 int i = 0;
5318
21da57a2
MC		 5319 mvpp2_dbgfs_cleanup(priv);
5320
e5c500eb 5321 flush_workqueue(priv->stats_queue);
118d6298 5322 destroy_workqueue(priv->stats_queue);
118d6298 5323
24812221 5324 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
e5c500eb
MR		 5325 if (priv->port_list[i]) {
5326 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
3f518509 5327 mvpp2_port_remove(priv->port_list[i]);
e5c500eb 5328 }
3f518509
MW		 5329 i++;
5330 }
5331
5332 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5333 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5334
5335 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5336 }
5337
5338 for_each_present_cpu(i) {
5339 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5340
5341 dma_free_coherent(&pdev->dev,
5342 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5343 aggr_txq->descs,
20396136 5344 aggr_txq->descs_dma);
3f518509
MW		 5345 }
5346
a75edc7c
MW		 5347 if (is_acpi_node(port_fwnode))
5348 return 0;
5349
4792ea04 5350 clk_disable_unprepare(priv->axi_clk);
9af771ce 5351 clk_disable_unprepare(priv->mg_core_clk);
fceb55d4 5352 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5353 clk_disable_unprepare(priv->pp_clk);
5354 clk_disable_unprepare(priv->gop_clk);
5355
5356 return 0;
5357}
5358
5359static const struct of_device_id mvpp2_match[] = {
faca9247
TP		 5360 {
5361 .compatible = "marvell,armada-375-pp2",
5362 .data = (void *)MVPP21,
5363 },
fc5e1550
TP		 5364 {
5365 .compatible = "marvell,armada-7k-pp22",
5366 .data = (void *)MVPP22,
5367 },
3f518509
MW		 5368 { }
5369};
5370MODULE_DEVICE_TABLE(of, mvpp2_match);
5371
a75edc7c
MW		 5372static const struct acpi_device_id mvpp2_acpi_match[] = {
5373 { "MRVL0110", MVPP22 },
5374 { },
5375};
5376MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5377
3f518509
MW		 5378static struct platform_driver mvpp2_driver = {
5379 .probe = mvpp2_probe,
5380 .remove = mvpp2_remove,
5381 .driver = {
5382 .name = MVPP2_DRIVER_NAME,
5383 .of_match_table = mvpp2_match,
a75edc7c 5384 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
3f518509
MW		 5385 },
5386};
5387
5388module_platform_driver(mvpp2_driver);
5389
5390MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5391MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
c634099d 5392MODULE_LICENSE("GPL v2");
Ubuntu Focal Linux kernel mirror