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net: mvpp2: make the per-cpu helpers static
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / marvell / mvpp2 / mvpp2_main.c
CommitLineData
f1e37e31 1// SPDX-License-Identifier: GPL-2.0
3f518509
MW		 2/*
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Marcin Wojtas <mw@semihalf.com>
3f518509
MW		 8 */
9
a75edc7c 10#include <linux/acpi.h>
3f518509
MW		 11#include <linux/kernel.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/platform_device.h>
15#include <linux/skbuff.h>
16#include <linux/inetdevice.h>
17#include <linux/mbus.h>
18#include <linux/module.h>
f84bf386 19#include <linux/mfd/syscon.h>
3f518509
MW		 20#include <linux/interrupt.h>
21#include <linux/cpumask.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_mdio.h>
25#include <linux/of_net.h>
26#include <linux/of_address.h>
faca9247 27#include <linux/of_device.h>
3f518509 28#include <linux/phy.h>
4bb04326 29#include <linux/phylink.h>
542897d9 30#include <linux/phy/phy.h>
3f518509 31#include <linux/clk.h>
edc660fa
MW		 32#include <linux/hrtimer.h>
33#include <linux/ktime.h>
f84bf386 34#include <linux/regmap.h>
3f518509
MW		 35#include <uapi/linux/ppp_defs.h>
36#include <net/ip.h>
37#include <net/ipv6.h>
186cd4d4 38#include <net/tso.h>
3f518509 39
db9d7d36
MC		 40#include "mvpp2.h"
41#include "mvpp2_prs.h"
42#include "mvpp2_cls.h"
a786841d 43
01d04936
SC		 44enum mvpp2_bm_pool_log_num {
45 MVPP2_BM_SHORT,
46 MVPP2_BM_LONG,
576193f2 47 MVPP2_BM_JUMBO,
01d04936 48 MVPP2_BM_POOLS_NUM
3f518509
MW		 49};
50
db9d7d36
MC		 51static struct {
52 int pkt_size;
53 int buf_num;
54} mvpp2_pools[MVPP2_BM_POOLS_NUM];
3f518509 55
db9d7d36
MC		 56/* The prototype is added here to be used in start_dev when using ACPI. This
57 * will be removed once phylink is used for all modes (dt+ACPI).
58 */
59static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
60 const struct phylink_link_state *state);
41948ccb
AT		 61static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
62 phy_interface_t interface, struct phy_device *phy);
10fea26c 63
db9d7d36
MC		 64/* Queue modes */
65#define MVPP2_QDIST_SINGLE_MODE 0
66#define MVPP2_QDIST_MULTI_MODE 1
3f518509 67
3f6aaf72 68static int queue_mode = MVPP2_QDIST_MULTI_MODE;
3f518509 69
db9d7d36
MC		 70module_param(queue_mode, int, 0444);
71MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
3f518509 72
db9d7d36 73/* Utility/helper methods */
3f518509 74
db9d7d36
MC		 75void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
76{
77 writel(data, priv->swth_base[0] + offset);
3f518509
MW		 78}
79
db9d7d36 80u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
3f518509 81{
db9d7d36 82 return readl(priv->swth_base[0] + offset);
3f518509
MW		 83}
84
db9d7d36 85u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
3f518509 86{
db9d7d36 87 return readl_relaxed(priv->swth_base[0] + offset);
3f518509 88}
db9d7d36
MC		 89/* These accessors should be used to access:
90 *
91 * - per-CPU registers, where each CPU has its own copy of the
92 * register.
93 *
94 * MVPP2_BM_VIRT_ALLOC_REG
95 * MVPP2_BM_ADDR_HIGH_ALLOC
96 * MVPP22_BM_ADDR_HIGH_RLS_REG
97 * MVPP2_BM_VIRT_RLS_REG
98 * MVPP2_ISR_RX_TX_CAUSE_REG
99 * MVPP2_ISR_RX_TX_MASK_REG
100 * MVPP2_TXQ_NUM_REG
101 * MVPP2_AGGR_TXQ_UPDATE_REG
102 * MVPP2_TXQ_RSVD_REQ_REG
103 * MVPP2_TXQ_RSVD_RSLT_REG
104 * MVPP2_TXQ_SENT_REG
105 * MVPP2_RXQ_NUM_REG
106 *
107 * - global registers that must be accessed through a specific CPU
108 * window, because they are related to an access to a per-CPU
109 * register
110 *
111 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
112 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
113 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
114 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
115 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
116 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
117 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
118 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
119 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
120 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
121 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
122 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
123 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
124 */
ecfed8d9 125static void mvpp2_percpu_write(struct mvpp2 *priv, unsigned int cpu,
db9d7d36
MC		 126 u32 offset, u32 data)
127{
128 writel(data, priv->swth_base[cpu] + offset);
3f518509
MW		 129}
130
ecfed8d9 131static u32 mvpp2_percpu_read(struct mvpp2 *priv, unsigned int cpu,
db9d7d36 132 u32 offset)
3f518509 133{
db9d7d36
MC		 134 return readl(priv->swth_base[cpu] + offset);
135}
3f518509 136
ecfed8d9 137static void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, unsigned int cpu,
db9d7d36
MC		 138 u32 offset, u32 data)
139{
140 writel_relaxed(data, priv->swth_base[cpu] + offset);
141}
0c6d9b44 142
850623b3 143static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, unsigned int cpu,
db9d7d36
MC		 144 u32 offset)
145{
146 return readl_relaxed(priv->swth_base[cpu] + offset);
147}
3f518509 148
db9d7d36
MC		 149static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
150 struct mvpp2_tx_desc *tx_desc)
151{
152 if (port->priv->hw_version == MVPP21)
7b9c7d7d 153 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
db9d7d36 154 else
7b9c7d7d
MC		 155 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
156 MVPP2_DESC_DMA_MASK;
db9d7d36 157}
3f518509 158
db9d7d36
MC		 159static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
160 struct mvpp2_tx_desc *tx_desc,
161 dma_addr_t dma_addr)
162{
163 dma_addr_t addr, offset;
3f518509 164
db9d7d36
MC		 165 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
166 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
3f518509 167
db9d7d36 168 if (port->priv->hw_version == MVPP21) {
7b9c7d7d 169 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
db9d7d36 170 tx_desc->pp21.packet_offset = offset;
0c6d9b44 171 } else {
7b9c7d7d 172 __le64 val = cpu_to_le64(addr);
3f518509 173
7b9c7d7d 174 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
db9d7d36
MC		 175 tx_desc->pp22.buf_dma_addr_ptp |= val;
176 tx_desc->pp22.packet_offset = offset;
177 }
3f518509
MW		 178}
179
db9d7d36
MC		 180static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
181 struct mvpp2_tx_desc *tx_desc)
3f518509 182{
db9d7d36 183 if (port->priv->hw_version == MVPP21)
7b9c7d7d 184 return le16_to_cpu(tx_desc->pp21.data_size);
db9d7d36 185 else
7b9c7d7d 186 return le16_to_cpu(tx_desc->pp22.data_size);
3f518509
MW		 187}
188
db9d7d36
MC		 189static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
190 struct mvpp2_tx_desc *tx_desc,
191 size_t size)
3f518509 192{
db9d7d36 193 if (port->priv->hw_version == MVPP21)
7b9c7d7d 194 tx_desc->pp21.data_size = cpu_to_le16(size);
db9d7d36 195 else
7b9c7d7d 196 tx_desc->pp22.data_size = cpu_to_le16(size);
3f518509
MW		 197}
198
db9d7d36
MC		 199static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
200 struct mvpp2_tx_desc *tx_desc,
201 unsigned int txq)
3f518509 202{
db9d7d36
MC		 203 if (port->priv->hw_version == MVPP21)
204 tx_desc->pp21.phys_txq = txq;
205 else
206 tx_desc->pp22.phys_txq = txq;
3f518509
MW		 207}
208
db9d7d36
MC		 209static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
210 struct mvpp2_tx_desc *tx_desc,
211 unsigned int command)
3f518509 212{
db9d7d36 213 if (port->priv->hw_version == MVPP21)
7b9c7d7d 214 tx_desc->pp21.command = cpu_to_le32(command);
db9d7d36 215 else
7b9c7d7d 216 tx_desc->pp22.command = cpu_to_le32(command);
db9d7d36 217}
3f518509 218
db9d7d36
MC		 219static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
220 struct mvpp2_tx_desc *tx_desc)
221{
222 if (port->priv->hw_version == MVPP21)
223 return tx_desc->pp21.packet_offset;
224 else
225 return tx_desc->pp22.packet_offset;
226}
3f518509 227
db9d7d36
MC		 228static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
229 struct mvpp2_rx_desc *rx_desc)
230{
231 if (port->priv->hw_version == MVPP21)
7b9c7d7d 232 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
db9d7d36 233 else
7b9c7d7d
MC		 234 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
235 MVPP2_DESC_DMA_MASK;
db9d7d36 236}
3f518509 237
db9d7d36
MC		 238static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
239 struct mvpp2_rx_desc *rx_desc)
240{
241 if (port->priv->hw_version == MVPP21)
7b9c7d7d 242 return le32_to_cpu(rx_desc->pp21.buf_cookie);
db9d7d36 243 else
7b9c7d7d
MC		 244 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
245 MVPP2_DESC_DMA_MASK;
db9d7d36 246}
3f518509 247
db9d7d36
MC		 248static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
249 struct mvpp2_rx_desc *rx_desc)
250{
251 if (port->priv->hw_version == MVPP21)
7b9c7d7d 252 return le16_to_cpu(rx_desc->pp21.data_size);
db9d7d36 253 else
7b9c7d7d 254 return le16_to_cpu(rx_desc->pp22.data_size);
db9d7d36 255}
3f518509 256
db9d7d36
MC		 257static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
258 struct mvpp2_rx_desc *rx_desc)
259{
260 if (port->priv->hw_version == MVPP21)
7b9c7d7d 261 return le32_to_cpu(rx_desc->pp21.status);
db9d7d36 262 else
7b9c7d7d 263 return le32_to_cpu(rx_desc->pp22.status);
3f518509
MW		 264}
265
db9d7d36 266static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
3f518509 267{
db9d7d36
MC		 268 txq_pcpu->txq_get_index++;
269 if (txq_pcpu->txq_get_index == txq_pcpu->size)
270 txq_pcpu->txq_get_index = 0;
271}
3f518509 272
db9d7d36
MC		 273static void mvpp2_txq_inc_put(struct mvpp2_port *port,
274 struct mvpp2_txq_pcpu *txq_pcpu,
275 struct sk_buff *skb,
276 struct mvpp2_tx_desc *tx_desc)
277{
278 struct mvpp2_txq_pcpu_buf *tx_buf =
279 txq_pcpu->buffs + txq_pcpu->txq_put_index;
280 tx_buf->skb = skb;
281 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
282 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
283 mvpp2_txdesc_offset_get(port, tx_desc);
284 txq_pcpu->txq_put_index++;
285 if (txq_pcpu->txq_put_index == txq_pcpu->size)
286 txq_pcpu->txq_put_index = 0;
287}
3f518509 288
db9d7d36
MC		 289/* Get number of physical egress port */
290static inline int mvpp2_egress_port(struct mvpp2_port *port)
291{
292 return MVPP2_MAX_TCONT + port->id;
293}
3f518509 294
db9d7d36
MC		 295/* Get number of physical TXQ */
296static inline int mvpp2_txq_phys(int port, int txq)
297{
298 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
3f518509
MW		 299}
300
0e037281
TP		 301static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
302{
303 if (likely(pool->frag_size <= PAGE_SIZE))
304 return netdev_alloc_frag(pool->frag_size);
305 else
306 return kmalloc(pool->frag_size, GFP_ATOMIC);
307}
308
309static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
310{
311 if (likely(pool->frag_size <= PAGE_SIZE))
312 skb_free_frag(data);
313 else
314 kfree(data);
315}
316
3f518509
MW		 317/* Buffer Manager configuration routines */
318
319/* Create pool */
320static int mvpp2_bm_pool_create(struct platform_device *pdev,
321 struct mvpp2 *priv,
322 struct mvpp2_bm_pool *bm_pool, int size)
323{
3f518509
MW		 324 u32 val;
325
d01524d8
TP		 326 /* Number of buffer pointers must be a multiple of 16, as per
327 * hardware constraints
328 */
329 if (!IS_ALIGNED(size, 16))
330 return -EINVAL;
331
332 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
333 * bytes per buffer pointer
334 */
335 if (priv->hw_version == MVPP21)
336 bm_pool->size_bytes = 2 * sizeof(u32) * size;
337 else
338 bm_pool->size_bytes = 2 * sizeof(u64) * size;
339
340 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
20396136 341 &bm_pool->dma_addr,
3f518509
MW		 342 GFP_KERNEL);
343 if (!bm_pool->virt_addr)
344 return -ENOMEM;
345
d3158807
TP		 346 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
347 MVPP2_BM_POOL_PTR_ALIGN)) {
d01524d8
TP		 348 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
349 bm_pool->virt_addr, bm_pool->dma_addr);
3f518509
MW		 350 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
351 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
352 return -ENOMEM;
353 }
354
355 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
d01524d8 356 lower_32_bits(bm_pool->dma_addr));
3f518509
MW		 357 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
358
359 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
360 val |= MVPP2_BM_START_MASK;
361 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
362
3f518509
MW		 363 bm_pool->size = size;
364 bm_pool->pkt_size = 0;
365 bm_pool->buf_num = 0;
3f518509
MW		 366
367 return 0;
368}
369
370/* Set pool buffer size */
371static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
372 struct mvpp2_bm_pool *bm_pool,
373 int buf_size)
374{
375 u32 val;
376
377 bm_pool->buf_size = buf_size;
378
379 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
380 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
381}
382
d01524d8
TP		 383static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
384 struct mvpp2_bm_pool *bm_pool,
385 dma_addr_t *dma_addr,
386 phys_addr_t *phys_addr)
387{
850623b3 388 unsigned int cpu = get_cpu();
a786841d
TP		 389
390 *dma_addr = mvpp2_percpu_read(priv, cpu,
391 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
392 *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG);
d01524d8
TP		 393
394 if (priv->hw_version == MVPP22) {
395 u32 val;
396 u32 dma_addr_highbits, phys_addr_highbits;
397
a786841d 398 val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC);
d01524d8
TP		 399 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
400 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
401 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
402
403 if (sizeof(dma_addr_t) == 8)
404 *dma_addr |= (u64)dma_addr_highbits << 32;
405
406 if (sizeof(phys_addr_t) == 8)
407 *phys_addr |= (u64)phys_addr_highbits << 32;
408 }
a704bb5c
TP		 409
410 put_cpu();
d01524d8
TP		 411}
412
7861f12b 413/* Free all buffers from the pool */
4229d502 414static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
effbf5f5 415 struct mvpp2_bm_pool *bm_pool, int buf_num)
3f518509
MW		 416{
417 int i;
418
effbf5f5
SC		 419 if (buf_num > bm_pool->buf_num) {
420 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
421 bm_pool->id, buf_num);
422 buf_num = bm_pool->buf_num;
423 }
424
425 for (i = 0; i < buf_num; i++) {
20396136 426 dma_addr_t buf_dma_addr;
4e4a105f
TP		 427 phys_addr_t buf_phys_addr;
428 void *data;
3f518509 429
d01524d8
TP		 430 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
431 &buf_dma_addr, &buf_phys_addr);
4229d502 432
20396136 433 dma_unmap_single(dev, buf_dma_addr,
4229d502
MW		 434 bm_pool->buf_size, DMA_FROM_DEVICE);
435
4e4a105f
TP		 436 data = (void *)phys_to_virt(buf_phys_addr);
437 if (!data)
3f518509 438 break;
0e037281 439
4e4a105f 440 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 441 }
442
443 /* Update BM driver with number of buffers removed from pool */
444 bm_pool->buf_num -= i;
3f518509
MW		 445}
446
effbf5f5 447/* Check number of buffers in BM pool */
6e61e10a 448static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
effbf5f5
SC		 449{
450 int buf_num = 0;
451
452 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
453 MVPP22_BM_POOL_PTRS_NUM_MASK;
454 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
455 MVPP2_BM_BPPI_PTR_NUM_MASK;
456
457 /* HW has one buffer ready which is not reflected in the counters */
458 if (buf_num)
459 buf_num += 1;
460
461 return buf_num;
462}
463
3f518509
MW		 464/* Cleanup pool */
465static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
466 struct mvpp2 *priv,
467 struct mvpp2_bm_pool *bm_pool)
468{
effbf5f5 469 int buf_num;
3f518509
MW		 470 u32 val;
471
effbf5f5
SC		 472 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
473 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
474
475 /* Check buffer counters after free */
476 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
477 if (buf_num) {
478 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
479 bm_pool->id, bm_pool->buf_num);
3f518509
MW		 480 return 0;
481 }
482
483 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
484 val |= MVPP2_BM_STOP_MASK;
485 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
486
d01524d8 487 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
3f518509 488 bm_pool->virt_addr,
20396136 489 bm_pool->dma_addr);
3f518509
MW		 490 return 0;
491}
492
493static int mvpp2_bm_pools_init(struct platform_device *pdev,
494 struct mvpp2 *priv)
495{
496 int i, err, size;
497 struct mvpp2_bm_pool *bm_pool;
498
499 /* Create all pools with maximum size */
500 size = MVPP2_BM_POOL_SIZE_MAX;
501 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
502 bm_pool = &priv->bm_pools[i];
503 bm_pool->id = i;
504 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
505 if (err)
506 goto err_unroll_pools;
507 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
508 }
509 return 0;
510
511err_unroll_pools:
512 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
513 for (i = i - 1; i >= 0; i--)
514 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
515 return err;
516}
517
518static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
519{
520 int i, err;
521
522 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
523 /* Mask BM all interrupts */
524 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
525 /* Clear BM cause register */
526 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
527 }
528
529 /* Allocate and initialize BM pools */
530 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
81f915eb 531 sizeof(*priv->bm_pools), GFP_KERNEL);
3f518509
MW		 532 if (!priv->bm_pools)
533 return -ENOMEM;
534
535 err = mvpp2_bm_pools_init(pdev, priv);
536 if (err < 0)
537 return err;
538 return 0;
539}
540
01d04936
SC		 541static void mvpp2_setup_bm_pool(void)
542{
543 /* Short pool */
544 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
545 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
546
547 /* Long pool */
548 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
549 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
576193f2
SC		 550
551 /* Jumbo pool */
552 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
553 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
01d04936
SC		 554}
555
3f518509
MW		 556/* Attach long pool to rxq */
557static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
558 int lrxq, int long_pool)
559{
5eac892a 560 u32 val, mask;
3f518509
MW		 561 int prxq;
562
563 /* Get queue physical ID */
564 prxq = port->rxqs[lrxq]->id;
565
5eac892a
TP		 566 if (port->priv->hw_version == MVPP21)
567 mask = MVPP21_RXQ_POOL_LONG_MASK;
568 else
569 mask = MVPP22_RXQ_POOL_LONG_MASK;
3f518509 570
5eac892a
TP		 571 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
572 val &= ~mask;
573 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
3f518509
MW		 574 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
575}
576
577/* Attach short pool to rxq */
578static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
579 int lrxq, int short_pool)
580{
5eac892a 581 u32 val, mask;
3f518509
MW		 582 int prxq;
583
584 /* Get queue physical ID */
585 prxq = port->rxqs[lrxq]->id;
586
5eac892a
TP		 587 if (port->priv->hw_version == MVPP21)
588 mask = MVPP21_RXQ_POOL_SHORT_MASK;
589 else
590 mask = MVPP22_RXQ_POOL_SHORT_MASK;
3f518509 591
5eac892a
TP		 592 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
593 val &= ~mask;
594 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
3f518509
MW		 595 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
596}
597
0e037281
TP		 598static void *mvpp2_buf_alloc(struct mvpp2_port *port,
599 struct mvpp2_bm_pool *bm_pool,
20396136 600 dma_addr_t *buf_dma_addr,
4e4a105f 601 phys_addr_t *buf_phys_addr,
0e037281 602 gfp_t gfp_mask)
3f518509 603{
20396136 604 dma_addr_t dma_addr;
0e037281 605 void *data;
3f518509 606
0e037281
TP		 607 data = mvpp2_frag_alloc(bm_pool);
608 if (!data)
3f518509
MW		 609 return NULL;
610
20396136
TP		 611 dma_addr = dma_map_single(port->dev->dev.parent, data,
612 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
613 DMA_FROM_DEVICE);
614 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
0e037281 615 mvpp2_frag_free(bm_pool, data);
3f518509
MW		 616 return NULL;
617 }
20396136 618 *buf_dma_addr = dma_addr;
4e4a105f 619 *buf_phys_addr = virt_to_phys(data);
3f518509 620
0e037281 621 return data;
3f518509
MW		 622}
623
3f518509
MW		 624/* Release buffer to BM */
625static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
20396136 626 dma_addr_t buf_dma_addr,
4e4a105f 627 phys_addr_t buf_phys_addr)
3f518509 628{
850623b3 629 unsigned int cpu = get_cpu();
a786841d 630
d01524d8
TP		 631 if (port->priv->hw_version == MVPP22) {
632 u32 val = 0;
633
634 if (sizeof(dma_addr_t) == 8)
635 val |= upper_32_bits(buf_dma_addr) &
636 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
637
638 if (sizeof(phys_addr_t) == 8)
639 val |= (upper_32_bits(buf_phys_addr)
640 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
641 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
642
cdcfeb0f
YM		 643 mvpp2_percpu_write_relaxed(port->priv, cpu,
644 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
d01524d8
TP		 645 }
646
4e4a105f
TP		 647 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
648 * returned in the "cookie" field of the RX
649 * descriptor. Instead of storing the virtual address, we
650 * store the physical address
651 */
cdcfeb0f
YM		 652 mvpp2_percpu_write_relaxed(port->priv, cpu,
653 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
654 mvpp2_percpu_write_relaxed(port->priv, cpu,
655 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
a704bb5c
TP		 656
657 put_cpu();
3f518509
MW		 658}
659
3f518509
MW		 660/* Allocate buffers for the pool */
661static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
662 struct mvpp2_bm_pool *bm_pool, int buf_num)
663{
3f518509 664 int i, buf_size, total_size;
20396136 665 dma_addr_t dma_addr;
4e4a105f 666 phys_addr_t phys_addr;
0e037281 667 void *buf;
3f518509
MW		 668
669 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
670 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
671
672 if (buf_num < 0 ||
673 (buf_num + bm_pool->buf_num > bm_pool->size)) {
674 netdev_err(port->dev,
675 "cannot allocate %d buffers for pool %d\n",
676 buf_num, bm_pool->id);
677 return 0;
678 }
679
3f518509 680 for (i = 0; i < buf_num; i++) {
4e4a105f
TP		 681 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
682 &phys_addr, GFP_KERNEL);
0e037281 683 if (!buf)
3f518509
MW		 684 break;
685
20396136 686 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
4e4a105f 687 phys_addr);
3f518509
MW		 688 }
689
690 /* Update BM driver with number of buffers added to pool */
691 bm_pool->buf_num += i;
3f518509
MW		 692
693 netdev_dbg(port->dev,
01d04936 694 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3f518509
MW		 695 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
696
697 netdev_dbg(port->dev,
01d04936 698 "pool %d: %d of %d buffers added\n",
3f518509
MW		 699 bm_pool->id, i, buf_num);
700 return i;
701}
702
703/* Notify the driver that BM pool is being used as specific type and return the
704 * pool pointer on success
705 */
706static struct mvpp2_bm_pool *
01d04936 707mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
3f518509 708{
3f518509
MW		 709 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
710 int num;
711
01d04936
SC		 712 if (pool >= MVPP2_BM_POOLS_NUM) {
713 netdev_err(port->dev, "Invalid pool %d\n", pool);
3f518509
MW		 714 return NULL;
715 }
716
3f518509
MW		 717 /* Allocate buffers in case BM pool is used as long pool, but packet
718 * size doesn't match MTU or BM pool hasn't being used yet
719 */
01d04936 720 if (new_pool->pkt_size == 0) {
3f518509
MW		 721 int pkts_num;
722
723 /* Set default buffer number or free all the buffers in case
724 * the pool is not empty
725 */
726 pkts_num = new_pool->buf_num;
727 if (pkts_num == 0)
01d04936 728 pkts_num = mvpp2_pools[pool].buf_num;
3f518509 729 else
4229d502 730 mvpp2_bm_bufs_free(port->dev->dev.parent,
effbf5f5 731 port->priv, new_pool, pkts_num);
3f518509
MW		 732
733 new_pool->pkt_size = pkt_size;
0e037281
TP		 734 new_pool->frag_size =
735 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
736 MVPP2_SKB_SHINFO_SIZE;
3f518509
MW		 737
738 /* Allocate buffers for this pool */
739 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
740 if (num != pkts_num) {
741 WARN(1, "pool %d: %d of %d allocated\n",
742 new_pool->id, num, pkts_num);
3f518509
MW		 743 return NULL;
744 }
745 }
746
747 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
748 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
749
3f518509
MW		 750 return new_pool;
751}
752
753/* Initialize pools for swf */
754static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
755{
3f518509 756 int rxq;
576193f2
SC		 757 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
758
759 /* If port pkt_size is higher than 1518B:
760 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
761 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
762 */
763 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
764 long_log_pool = MVPP2_BM_JUMBO;
765 short_log_pool = MVPP2_BM_LONG;
766 } else {
767 long_log_pool = MVPP2_BM_LONG;
768 short_log_pool = MVPP2_BM_SHORT;
769 }
3f518509
MW		 770
771 if (!port->pool_long) {
772 port->pool_long =
576193f2
SC		 773 mvpp2_bm_pool_use(port, long_log_pool,
774 mvpp2_pools[long_log_pool].pkt_size);
3f518509
MW		 775 if (!port->pool_long)
776 return -ENOMEM;
777
576193f2 778 port->pool_long->port_map |= BIT(port->id);
3f518509 779
09f83975 780 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 781 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
782 }
783
784 if (!port->pool_short) {
785 port->pool_short =
576193f2 786 mvpp2_bm_pool_use(port, short_log_pool,
e2e03164 787 mvpp2_pools[short_log_pool].pkt_size);
3f518509
MW		 788 if (!port->pool_short)
789 return -ENOMEM;
790
576193f2 791 port->pool_short->port_map |= BIT(port->id);
3f518509 792
09f83975 793 for (rxq = 0; rxq < port->nrxqs; rxq++)
3f518509
MW		 794 mvpp2_rxq_short_pool_set(port, rxq,
795 port->pool_short->id);
796 }
797
798 return 0;
799}
800
801static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
802{
803 struct mvpp2_port *port = netdev_priv(dev);
576193f2
SC		 804 enum mvpp2_bm_pool_log_num new_long_pool;
805 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3f518509 806
576193f2
SC		 807 /* If port MTU is higher than 1518B:
808 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
809 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
810 */
811 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
812 new_long_pool = MVPP2_BM_JUMBO;
813 else
814 new_long_pool = MVPP2_BM_LONG;
815
816 if (new_long_pool != port->pool_long->id) {
817 /* Remove port from old short & long pool */
818 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
819 port->pool_long->pkt_size);
820 port->pool_long->port_map &= ~BIT(port->id);
821 port->pool_long = NULL;
822
823 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
824 port->pool_short->pkt_size);
825 port->pool_short->port_map &= ~BIT(port->id);
826 port->pool_short = NULL;
827
828 port->pkt_size = pkt_size;
829
830 /* Add port to new short & long pool */
831 mvpp2_swf_bm_pool_init(port);
832
833 /* Update L4 checksum when jumbo enable/disable on port */
834 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
835 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
836 dev->hw_features &= ~(NETIF_F_IP_CSUM |
837 NETIF_F_IPV6_CSUM);
838 } else {
839 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
840 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
841 }
3f518509
MW		 842 }
843
3f518509 844 dev->mtu = mtu;
576193f2
SC		 845 dev->wanted_features = dev->features;
846
3f518509
MW		 847 netdev_update_features(dev);
848 return 0;
849}
850
851static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
852{
591f4cfa
TP		 853 int i, sw_thread_mask = 0;
854
855 for (i = 0; i < port->nqvecs; i++)
856 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
3f518509 857
3f518509 858 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa 859 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
3f518509
MW		 860}
861
862static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
863{
591f4cfa
TP		 864 int i, sw_thread_mask = 0;
865
866 for (i = 0; i < port->nqvecs; i++)
867 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
868
869 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
870 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
871}
872
873static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
874{
875 struct mvpp2_port *port = qvec->port;
3f518509 876
3f518509 877 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
591f4cfa
TP		 878 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
879}
880
881static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
882{
883 struct mvpp2_port *port = qvec->port;
884
885 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
886 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
3f518509
MW		 887}
888
e0af22d9
TP		 889/* Mask the current CPU's Rx/Tx interrupts
890 * Called by on_each_cpu(), guaranteed to run with migration disabled,
891 * using smp_processor_id() is OK.
892 */
3f518509
MW		 893static void mvpp2_interrupts_mask(void *arg)
894{
895 struct mvpp2_port *port = arg;
896
a786841d
TP		 897 mvpp2_percpu_write(port->priv, smp_processor_id(),
898 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
3f518509
MW		 899}
900
e0af22d9
TP		 901/* Unmask the current CPU's Rx/Tx interrupts.
902 * Called by on_each_cpu(), guaranteed to run with migration disabled,
903 * using smp_processor_id() is OK.
904 */
3f518509
MW		 905static void mvpp2_interrupts_unmask(void *arg)
906{
907 struct mvpp2_port *port = arg;
213f428f
TP		 908 u32 val;
909
910 val = MVPP2_CAUSE_MISC_SUM_MASK |
70afb58e 911 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
213f428f
TP		 912 if (port->has_tx_irqs)
913 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3f518509 914
a786841d 915 mvpp2_percpu_write(port->priv, smp_processor_id(),
213f428f
TP		 916 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
917}
918
919static void
920mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
921{
922 u32 val;
923 int i;
924
925 if (port->priv->hw_version != MVPP22)
926 return;
927
928 if (mask)
929 val = 0;
930 else
70afb58e 931 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
213f428f
TP		 932
933 for (i = 0; i < port->nqvecs; i++) {
934 struct mvpp2_queue_vector *v = port->qvecs + i;
935
936 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
937 continue;
938
939 mvpp2_percpu_write(port->priv, v->sw_thread_id,
940 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
941 }
3f518509
MW		 942}
943
944/* Port configuration routines */
945
f84bf386
AT		 946static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
947{
948 struct mvpp2 *priv = port->priv;
949 u32 val;
950
951 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
952 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
953 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
954
955 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
956 if (port->gop_id == 2)
957 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
958 else if (port->gop_id == 3)
959 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
960 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
961}
962
963static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
964{
965 struct mvpp2 *priv = port->priv;
966 u32 val;
967
968 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
969 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
970 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
971 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
972
973 if (port->gop_id > 1) {
974 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
975 if (port->gop_id == 2)
976 val &= ~GENCONF_CTRL0_PORT0_RGMII;
977 else if (port->gop_id == 3)
978 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
979 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
980 }
981}
982
983static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
984{
985 struct mvpp2 *priv = port->priv;
986 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
987 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
988 u32 val;
989
990 /* XPCS */
991 val = readl(xpcs + MVPP22_XPCS_CFG0);
992 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
993 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
994 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
995 writel(val, xpcs + MVPP22_XPCS_CFG0);
996
997 /* MPCS */
998 val = readl(mpcs + MVPP22_MPCS_CTRL);
999 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1000 writel(val, mpcs + MVPP22_MPCS_CTRL);
1001
1002 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1003 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |
1004 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1005 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1006 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1007
1008 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1009 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;
1010 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1011}
1012
1013static int mvpp22_gop_init(struct mvpp2_port *port)
1014{
1015 struct mvpp2 *priv = port->priv;
1016 u32 val;
1017
1018 if (!priv->sysctrl_base)
1019 return 0;
1020
1021 switch (port->phy_interface) {
1022 case PHY_INTERFACE_MODE_RGMII:
1023 case PHY_INTERFACE_MODE_RGMII_ID:
1024 case PHY_INTERFACE_MODE_RGMII_RXID:
1025 case PHY_INTERFACE_MODE_RGMII_TXID:
1026 if (port->gop_id == 0)
1027 goto invalid_conf;
1028 mvpp22_gop_init_rgmii(port);
1029 break;
1030 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a 1031 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 1032 case PHY_INTERFACE_MODE_2500BASEX:
f84bf386
AT		 1033 mvpp22_gop_init_sgmii(port);
1034 break;
1035 case PHY_INTERFACE_MODE_10GKR:
1036 if (port->gop_id != 0)
1037 goto invalid_conf;
1038 mvpp22_gop_init_10gkr(port);
1039 break;
1040 default:
1041 goto unsupported_conf;
1042 }
1043
1044 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1045 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1046 GENCONF_PORT_CTRL1_EN(port->gop_id);
1047 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1048
1049 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1050 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1051 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1052
1053 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1054 val |= GENCONF_SOFT_RESET1_GOP;
1055 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1056
1057unsupported_conf:
1058 return 0;
1059
1060invalid_conf:
1061 netdev_err(port->dev, "Invalid port configuration\n");
1062 return -EINVAL;
1063}
1064
fd3651b2
AT		 1065static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1066{
1067 u32 val;
1068
1069 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 1070 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1071 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1072 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 1073 /* Enable the GMAC link status irq for this port */
1074 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1075 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1076 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1077 }
1078
1079 if (port->gop_id == 0) {
1080 /* Enable the XLG/GIG irqs for this port */
1081 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1082 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
1083 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1084 else
1085 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1086 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1087 }
1088}
1089
1090static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1091{
1092 u32 val;
1093
1094 if (port->gop_id == 0) {
1095 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1096 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
a3302baa 1097 MVPP22_XLG_EXT_INT_MASK_GIG);
fd3651b2
AT		 1098 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1099 }
1100
1101 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 1102 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1103 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1104 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 1105 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1106 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1107 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1108 }
1109}
1110
1111static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1112{
1113 u32 val;
1114
1115 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 1116 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1117 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1118 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 1119 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1120 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1121 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1122 }
1123
1124 if (port->gop_id == 0) {
1125 val = readl(port->base + MVPP22_XLG_INT_MASK);
1126 val |= MVPP22_XLG_INT_MASK_LINK;
1127 writel(val, port->base + MVPP22_XLG_INT_MASK);
1128 }
1129
1130 mvpp22_gop_unmask_irq(port);
1131}
1132
a6fe31de
AT		 1133/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1134 *
1135 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1136 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1137 * differ.
1138 *
1139 * The COMPHY configures the serdes lanes regardless of the actual use of the
1140 * lanes by the physical layer. This is why configurations like
1141 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1142 */
542897d9
AT		 1143static int mvpp22_comphy_init(struct mvpp2_port *port)
1144{
1145 enum phy_mode mode;
1146 int ret;
1147
1148 if (!port->comphy)
1149 return 0;
1150
1151 switch (port->phy_interface) {
1152 case PHY_INTERFACE_MODE_SGMII:
d97c9f4a 1153 case PHY_INTERFACE_MODE_1000BASEX:
542897d9
AT		 1154 mode = PHY_MODE_SGMII;
1155 break;
a6fe31de
AT		 1156 case PHY_INTERFACE_MODE_2500BASEX:
1157 mode = PHY_MODE_2500SGMII;
1158 break;
542897d9
AT		 1159 case PHY_INTERFACE_MODE_10GKR:
1160 mode = PHY_MODE_10GKR;
1161 break;
1162 default:
1163 return -EINVAL;
1164 }
1165
1166 ret = phy_set_mode(port->comphy, mode);
1167 if (ret)
1168 return ret;
1169
1170 return phy_power_on(port->comphy);
1171}
1172
3f518509
MW		 1173static void mvpp2_port_enable(struct mvpp2_port *port)
1174{
1175 u32 val;
1176
725757ae
AT		 1177 /* Only GOP port 0 has an XLG MAC */
1178 if (port->gop_id == 0 &&
1179 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1180 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1181 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1182 val |= MVPP22_XLG_CTRL0_PORT_EN |
1183 MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1184 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1185 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1186 } else {
1187 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1188 val |= MVPP2_GMAC_PORT_EN_MASK;
1189 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1190 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1191 }
3f518509
MW		 1192}
1193
1194static void mvpp2_port_disable(struct mvpp2_port *port)
1195{
1196 u32 val;
1197
725757ae
AT		 1198 /* Only GOP port 0 has an XLG MAC */
1199 if (port->gop_id == 0 &&
1200 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1201 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1202 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4bb04326
AT		 1203 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1204 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1205
1206 /* Disable & reset should be done separately */
1207 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
725757ae
AT		 1208 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1209 } else {
1210 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1211 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1212 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1213 }
3f518509
MW		 1214}
1215
1216/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1217static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1218{
1219 u32 val;
1220
1221 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1222 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1223 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1224}
1225
1226/* Configure loopback port */
4bb04326
AT		 1227static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1228 const struct phylink_link_state *state)
3f518509
MW		 1229{
1230 u32 val;
1231
1232 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1233
4bb04326 1234 if (state->speed == 1000)
3f518509
MW		 1235 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1236 else
1237 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1238
d97c9f4a 1239 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 1240 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1241 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
3f518509
MW		 1242 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1243 else
1244 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1245
1246 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1247}
1248
118d6298
MR		 1249struct mvpp2_ethtool_counter {
1250 unsigned int offset;
1251 const char string[ETH_GSTRING_LEN];
1252 bool reg_is_64b;
1253};
1254
1255static u64 mvpp2_read_count(struct mvpp2_port *port,
1256 const struct mvpp2_ethtool_counter *counter)
1257{
1258 u64 val;
1259
1260 val = readl(port->stats_base + counter->offset);
1261 if (counter->reg_is_64b)
1262 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1263
1264 return val;
1265}
1266
1267/* Due to the fact that software statistics and hardware statistics are, by
1268 * design, incremented at different moments in the chain of packet processing,
1269 * it is very likely that incoming packets could have been dropped after being
1270 * counted by hardware but before reaching software statistics (most probably
1271 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1272 * are added in between as well as TSO skb will be split and header bytes added.
1273 * Hence, statistics gathered from userspace with ifconfig (software) and
1274 * ethtool (hardware) cannot be compared.
1275 */
1276static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = {
1277 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1278 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1279 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1280 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1281 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1282 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1283 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1284 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1285 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1286 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1287 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1288 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1289 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1290 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1291 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1292 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1293 { MVPP2_MIB_FC_SENT, "fc_sent" },
1294 { MVPP2_MIB_FC_RCVD, "fc_received" },
1295 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1296 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1297 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1298 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1299 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1300 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1301 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1302 { MVPP2_MIB_COLLISION, "collision" },
1303 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1304};
1305
1306static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1307 u8 *data)
1308{
1309 if (sset == ETH_SS_STATS) {
1310 int i;
1311
1312 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1313 memcpy(data + i * ETH_GSTRING_LEN,
1314 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN);
1315 }
1316}
1317
1318static void mvpp2_gather_hw_statistics(struct work_struct *work)
1319{
1320 struct delayed_work *del_work = to_delayed_work(work);
e5c500eb
MR		 1321 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1322 stats_work);
118d6298 1323 u64 *pstats;
e5c500eb 1324 int i;
118d6298 1325
e5c500eb 1326 mutex_lock(&port->gather_stats_lock);
118d6298 1327
e5c500eb
MR		 1328 pstats = port->ethtool_stats;
1329 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1330 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
118d6298
MR		 1331
1332 /* No need to read again the counters right after this function if it
1333 * was called asynchronously by the user (ie. use of ethtool).
1334 */
e5c500eb
MR		 1335 cancel_delayed_work(&port->stats_work);
1336 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
118d6298
MR		 1337 MVPP2_MIB_COUNTERS_STATS_DELAY);
1338
e5c500eb 1339 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1340}
1341
1342static void mvpp2_ethtool_get_stats(struct net_device *dev,
1343 struct ethtool_stats *stats, u64 *data)
1344{
1345 struct mvpp2_port *port = netdev_priv(dev);
1346
e5c500eb
MR		 1347 /* Update statistics for the given port, then take the lock to avoid
1348 * concurrent accesses on the ethtool_stats structure during its copy.
1349 */
1350 mvpp2_gather_hw_statistics(&port->stats_work.work);
118d6298 1351
e5c500eb 1352 mutex_lock(&port->gather_stats_lock);
118d6298
MR		 1353 memcpy(data, port->ethtool_stats,
1354 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs));
e5c500eb 1355 mutex_unlock(&port->gather_stats_lock);
118d6298
MR		 1356}
1357
1358static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1359{
1360 if (sset == ETH_SS_STATS)
1361 return ARRAY_SIZE(mvpp2_ethtool_regs);
1362
1363 return -EOPNOTSUPP;
1364}
1365
3f518509
MW		 1366static void mvpp2_port_reset(struct mvpp2_port *port)
1367{
1368 u32 val;
118d6298
MR		 1369 unsigned int i;
1370
1371 /* Read the GOP statistics to reset the hardware counters */
1372 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1373 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
3f518509
MW		 1374
1375 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1376 ~MVPP2_GMAC_PORT_RESET_MASK;
1377 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1378
1379 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1380 MVPP2_GMAC_PORT_RESET_MASK)
1381 continue;
1382}
1383
1384/* Change maximum receive size of the port */
1385static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1386{
1387 u32 val;
1388
1389 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1390 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1391 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1392 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1393 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1394}
1395
76eb1b1d
SC		 1396/* Change maximum receive size of the port */
1397static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1398{
1399 u32 val;
1400
1401 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1402 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1403 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
ec15ecde 1404 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
76eb1b1d
SC		 1405 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1406}
1407
3f518509
MW		 1408/* Set defaults to the MVPP2 port */
1409static void mvpp2_defaults_set(struct mvpp2_port *port)
1410{
1411 int tx_port_num, val, queue, ptxq, lrxq;
1412
3d9017d9 1413 if (port->priv->hw_version == MVPP21) {
3d9017d9
TP		 1414 /* Update TX FIFO MIN Threshold */
1415 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1416 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1417 /* Min. TX threshold must be less than minimal packet length */
1418 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1419 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1420 }
3f518509
MW		 1421
1422 /* Disable Legacy WRR, Disable EJP, Release from reset */
1423 tx_port_num = mvpp2_egress_port(port);
1424 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1425 tx_port_num);
1426 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1427
1428 /* Close bandwidth for all queues */
1429 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
1430 ptxq = mvpp2_txq_phys(port->id, queue);
1431 mvpp2_write(port->priv,
1432 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
1433 }
1434
1435 /* Set refill period to 1 usec, refill tokens
1436 * and bucket size to maximum
1437 */
1438 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1439 port->priv->tclk / USEC_PER_SEC);
1440 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1441 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1442 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1443 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1444 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1445 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1446 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1447
1448 /* Set MaximumLowLatencyPacketSize value to 256 */
1449 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1450 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1451 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1452
1453 /* Enable Rx cache snoop */
09f83975 1454 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1455 queue = port->rxqs[lrxq]->id;
1456 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1457 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1458 MVPP2_SNOOP_BUF_HDR_MASK;
1459 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1460 }
1461
1462 /* At default, mask all interrupts to all present cpus */
1463 mvpp2_interrupts_disable(port);
1464}
1465
1466/* Enable/disable receiving packets */
1467static void mvpp2_ingress_enable(struct mvpp2_port *port)
1468{
1469 u32 val;
1470 int lrxq, queue;
1471
09f83975 1472 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1473 queue = port->rxqs[lrxq]->id;
1474 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1475 val &= ~MVPP2_RXQ_DISABLE_MASK;
1476 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1477 }
1478}
1479
1480static void mvpp2_ingress_disable(struct mvpp2_port *port)
1481{
1482 u32 val;
1483 int lrxq, queue;
1484
09f83975 1485 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
3f518509
MW		 1486 queue = port->rxqs[lrxq]->id;
1487 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1488 val |= MVPP2_RXQ_DISABLE_MASK;
1489 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1490 }
1491}
1492
1493/* Enable transmit via physical egress queue
1494 * - HW starts take descriptors from DRAM
1495 */
1496static void mvpp2_egress_enable(struct mvpp2_port *port)
1497{
1498 u32 qmap;
1499 int queue;
1500 int tx_port_num = mvpp2_egress_port(port);
1501
1502 /* Enable all initialized TXs. */
1503 qmap = 0;
09f83975 1504 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1505 struct mvpp2_tx_queue *txq = port->txqs[queue];
1506
dbbb2f03 1507 if (txq->descs)
3f518509
MW		 1508 qmap |= (1 << queue);
1509 }
1510
1511 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1512 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1513}
1514
1515/* Disable transmit via physical egress queue
1516 * - HW doesn't take descriptors from DRAM
1517 */
1518static void mvpp2_egress_disable(struct mvpp2_port *port)
1519{
1520 u32 reg_data;
1521 int delay;
1522 int tx_port_num = mvpp2_egress_port(port);
1523
1524 /* Issue stop command for active channels only */
1525 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1526 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1527 MVPP2_TXP_SCHED_ENQ_MASK;
1528 if (reg_data != 0)
1529 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1530 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1531
1532 /* Wait for all Tx activity to terminate. */
1533 delay = 0;
1534 do {
1535 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1536 netdev_warn(port->dev,
1537 "Tx stop timed out, status=0x%08x\n",
1538 reg_data);
1539 break;
1540 }
1541 mdelay(1);
1542 delay++;
1543
1544 /* Check port TX Command register that all
1545 * Tx queues are stopped
1546 */
1547 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1548 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1549}
1550
1551/* Rx descriptors helper methods */
1552
1553/* Get number of Rx descriptors occupied by received packets */
1554static inline int
1555mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1556{
1557 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1558
1559 return val & MVPP2_RXQ_OCCUPIED_MASK;
1560}
1561
1562/* Update Rx queue status with the number of occupied and available
1563 * Rx descriptor slots.
1564 */
1565static inline void
1566mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1567 int used_count, int free_count)
1568{
1569 /* Decrement the number of used descriptors and increment count
1570 * increment the number of free descriptors.
1571 */
1572 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1573
1574 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1575}
1576
1577/* Get pointer to next RX descriptor to be processed by SW */
1578static inline struct mvpp2_rx_desc *
1579mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1580{
1581 int rx_desc = rxq->next_desc_to_proc;
1582
1583 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1584 prefetch(rxq->descs + rxq->next_desc_to_proc);
1585 return rxq->descs + rx_desc;
1586}
1587
1588/* Set rx queue offset */
1589static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1590 int prxq, int offset)
1591{
1592 u32 val;
1593
1594 /* Convert offset from bytes to units of 32 bytes */
1595 offset = offset >> 5;
1596
1597 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1598 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1599
1600 /* Offset is in */
1601 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1602 MVPP2_RXQ_PACKET_OFFSET_MASK);
1603
1604 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1605}
1606
3f518509
MW		 1607/* Tx descriptors helper methods */
1608
3f518509
MW		 1609/* Get pointer to next Tx descriptor to be processed (send) by HW */
1610static struct mvpp2_tx_desc *
1611mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1612{
1613 int tx_desc = txq->next_desc_to_proc;
1614
1615 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1616 return txq->descs + tx_desc;
1617}
1618
e0af22d9
TP		 1619/* Update HW with number of aggregated Tx descriptors to be sent
1620 *
1621 * Called only from mvpp2_tx(), so migration is disabled, using
1622 * smp_processor_id() is OK.
1623 */
3f518509
MW		 1624static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1625{
1626 /* aggregated access - relevant TXQ number is written in TX desc */
a786841d
TP		 1627 mvpp2_percpu_write(port->priv, smp_processor_id(),
1628 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3f518509
MW		 1629}
1630
3f518509
MW		 1631/* Check if there are enough free descriptors in aggregated txq.
1632 * If not, update the number of occupied descriptors and repeat the check.
e0af22d9
TP		 1633 *
1634 * Called only from mvpp2_tx(), so migration is disabled, using
1635 * smp_processor_id() is OK.
3f518509
MW		 1636 */
1637static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
1638 struct mvpp2_tx_queue *aggr_txq, int num)
1639{
02856a3b 1640 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
3f518509 1641 /* Update number of occupied aggregated Tx descriptors */
850623b3 1642 unsigned int cpu = smp_processor_id();
cdcfeb0f
YM		 1643 u32 val = mvpp2_read_relaxed(priv,
1644 MVPP2_AGGR_TXQ_STATUS_REG(cpu));
3f518509
MW		 1645
1646 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
3f518509 1647
914365f1
YM		 1648 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1649 return -ENOMEM;
1650 }
3f518509
MW		 1651 return 0;
1652}
1653
e0af22d9
TP		 1654/* Reserved Tx descriptors allocation request
1655 *
1656 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1657 * only by mvpp2_tx(), so migration is disabled, using
1658 * smp_processor_id() is OK.
1659 */
3f518509
MW		 1660static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv,
1661 struct mvpp2_tx_queue *txq, int num)
1662{
1663 u32 val;
850623b3 1664 unsigned int cpu = smp_processor_id();
3f518509
MW		 1665
1666 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
cdcfeb0f 1667 mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val);
3f518509 1668
cdcfeb0f 1669 val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG);
3f518509
MW		 1670
1671 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1672}
1673
1674/* Check if there are enough reserved descriptors for transmission.
1675 * If not, request chunk of reserved descriptors and check again.
1676 */
1677static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv,
1678 struct mvpp2_tx_queue *txq,
1679 struct mvpp2_txq_pcpu *txq_pcpu,
1680 int num)
1681{
850623b3
AT		 1682 int req, desc_count;
1683 unsigned int cpu;
3f518509
MW		 1684
1685 if (txq_pcpu->reserved_num >= num)
1686 return 0;
1687
1688 /* Not enough descriptors reserved! Update the reserved descriptor
1689 * count and check again.
1690 */
1691
1692 desc_count = 0;
1693 /* Compute total of used descriptors */
1694 for_each_present_cpu(cpu) {
1695 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1696
1697 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu);
1698 desc_count += txq_pcpu_aux->count;
1699 desc_count += txq_pcpu_aux->reserved_num;
1700 }
1701
1702 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1703 desc_count += req;
1704
1705 if (desc_count >
1706 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK)))
1707 return -ENOMEM;
1708
1709 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req);
1710
a3302baa 1711 /* OK, the descriptor could have been updated: check again. */
3f518509
MW		 1712 if (txq_pcpu->reserved_num < num)
1713 return -ENOMEM;
1714 return 0;
1715}
1716
1717/* Release the last allocated Tx descriptor. Useful to handle DMA
1718 * mapping failures in the Tx path.
1719 */
1720static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1721{
1722 if (txq->next_desc_to_proc == 0)
1723 txq->next_desc_to_proc = txq->last_desc - 1;
1724 else
1725 txq->next_desc_to_proc--;
1726}
1727
1728/* Set Tx descriptors fields relevant for CSUM calculation */
1729static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
1730 int ip_hdr_len, int l4_proto)
1731{
1732 u32 command;
1733
1734 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1735 * G_L4_chk, L4_type required only for checksum calculation
1736 */
1737 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1738 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1739 command |= MVPP2_TXD_IP_CSUM_DISABLE;
1740
dc734dbe 1741 if (l3_proto == htons(ETH_P_IP)) {
3f518509
MW		 1742 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
1743 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
1744 } else {
1745 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
1746 }
1747
1748 if (l4_proto == IPPROTO_TCP) {
1749 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
1750 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1751 } else if (l4_proto == IPPROTO_UDP) {
1752 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
1753 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1754 } else {
1755 command |= MVPP2_TXD_L4_CSUM_NOT;
1756 }
1757
1758 return command;
1759}
1760
1761/* Get number of sent descriptors and decrement counter.
1762 * The number of sent descriptors is returned.
1763 * Per-CPU access
e0af22d9
TP		 1764 *
1765 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1766 * (migration disabled) and from the TX completion tasklet (migration
1767 * disabled) so using smp_processor_id() is OK.
3f518509
MW		 1768 */
1769static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1770 struct mvpp2_tx_queue *txq)
1771{
1772 u32 val;
1773
1774 /* Reading status reg resets transmitted descriptor counter */
cdcfeb0f
YM		 1775 val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(),
1776 MVPP2_TXQ_SENT_REG(txq->id));
3f518509
MW		 1777
1778 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1779 MVPP2_TRANSMITTED_COUNT_OFFSET;
1780}
1781
e0af22d9
TP		 1782/* Called through on_each_cpu(), so runs on all CPUs, with migration
1783 * disabled, therefore using smp_processor_id() is OK.
1784 */
3f518509
MW		 1785static void mvpp2_txq_sent_counter_clear(void *arg)
1786{
1787 struct mvpp2_port *port = arg;
1788 int queue;
1789
09f83975 1790 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 1791 int id = port->txqs[queue]->id;
1792
a786841d
TP		 1793 mvpp2_percpu_read(port->priv, smp_processor_id(),
1794 MVPP2_TXQ_SENT_REG(id));
3f518509
MW		 1795 }
1796}
1797
1798/* Set max sizes for Tx queues */
1799static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1800{
1801 u32 val, size, mtu;
1802 int txq, tx_port_num;
1803
1804 mtu = port->pkt_size * 8;
1805 if (mtu > MVPP2_TXP_MTU_MAX)
1806 mtu = MVPP2_TXP_MTU_MAX;
1807
1808 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1809 mtu = 3 * mtu;
1810
1811 /* Indirect access to registers */
1812 tx_port_num = mvpp2_egress_port(port);
1813 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1814
1815 /* Set MTU */
1816 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1817 val &= ~MVPP2_TXP_MTU_MAX;
1818 val |= mtu;
1819 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1820
1821 /* TXP token size and all TXQs token size must be larger that MTU */
1822 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1823 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1824 if (size < mtu) {
1825 size = mtu;
1826 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1827 val |= size;
1828 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1829 }
1830
09f83975 1831 for (txq = 0; txq < port->ntxqs; txq++) {
3f518509
MW		 1832 val = mvpp2_read(port->priv,
1833 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1834 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1835
1836 if (size < mtu) {
1837 size = mtu;
1838 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1839 val |= size;
1840 mvpp2_write(port->priv,
1841 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
1842 val);
1843 }
1844 }
1845}
1846
1847/* Set the number of packets that will be received before Rx interrupt
1848 * will be generated by HW.
1849 */
1850static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
d63f9e41 1851 struct mvpp2_rx_queue *rxq)
3f518509 1852{
850623b3 1853 unsigned int cpu = get_cpu();
a786841d 1854
f8b0d5f8
TP		 1855 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
1856 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
3f518509 1857
a786841d
TP		 1858 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
1859 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,
1860 rxq->pkts_coal);
a704bb5c
TP		 1861
1862 put_cpu();
3f518509
MW		 1863}
1864
213f428f
TP		 1865/* For some reason in the LSP this is done on each CPU. Why ? */
1866static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
1867 struct mvpp2_tx_queue *txq)
1868{
850623b3 1869 unsigned int cpu = get_cpu();
213f428f
TP		 1870 u32 val;
1871
1872 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
1873 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
1874
1875 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1876 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
1877 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val);
1878
1879 put_cpu();
1880}
1881
ab42676a
TP		 1882static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
1883{
1884 u64 tmp = (u64)clk_hz * usec;
1885
1886 do_div(tmp, USEC_PER_SEC);
1887
1888 return tmp > U32_MAX ? U32_MAX : tmp;
1889}
1890
1891static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
1892{
1893 u64 tmp = (u64)cycles * USEC_PER_SEC;
1894
1895 do_div(tmp, clk_hz);
1896
1897 return tmp > U32_MAX ? U32_MAX : tmp;
1898}
1899
3f518509
MW		 1900/* Set the time delay in usec before Rx interrupt */
1901static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
d63f9e41 1902 struct mvpp2_rx_queue *rxq)
3f518509 1903{
ab42676a
TP		 1904 unsigned long freq = port->priv->tclk;
1905 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1906
1907 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
1908 rxq->time_coal =
1909 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
1910
1911 /* re-evaluate to get actual register value */
1912 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1913 }
3f518509 1914
3f518509 1915 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
3f518509
MW		 1916}
1917
213f428f
TP		 1918static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
1919{
1920 unsigned long freq = port->priv->tclk;
1921 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1922
1923 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
1924 port->tx_time_coal =
1925 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
1926
1927 /* re-evaluate to get actual register value */
1928 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1929 }
1930
1931 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
1932}
1933
3f518509
MW		 1934/* Free Tx queue skbuffs */
1935static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
1936 struct mvpp2_tx_queue *txq,
1937 struct mvpp2_txq_pcpu *txq_pcpu, int num)
1938{
1939 int i;
1940
1941 for (i = 0; i < num; i++) {
8354491c
TP		 1942 struct mvpp2_txq_pcpu_buf *tx_buf =
1943 txq_pcpu->buffs + txq_pcpu->txq_get_index;
3f518509 1944
20920267
AT		 1945 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
1946 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
1947 tx_buf->size, DMA_TO_DEVICE);
36fb7435
TP		 1948 if (tx_buf->skb)
1949 dev_kfree_skb_any(tx_buf->skb);
1950
1951 mvpp2_txq_inc_get(txq_pcpu);
3f518509
MW		 1952 }
1953}
1954
1955static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
1956 u32 cause)
1957{
1958 int queue = fls(cause) - 1;
1959
1960 return port->rxqs[queue];
1961}
1962
1963static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
1964 u32 cause)
1965{
edc660fa 1966 int queue = fls(cause) - 1;
3f518509
MW		 1967
1968 return port->txqs[queue];
1969}
1970
1971/* Handle end of transmission */
1972static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
1973 struct mvpp2_txq_pcpu *txq_pcpu)
1974{
1975 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
1976 int tx_done;
1977
1978 if (txq_pcpu->cpu != smp_processor_id())
1979 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
1980
1981 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
1982 if (!tx_done)
1983 return;
1984 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
1985
1986 txq_pcpu->count -= tx_done;
1987
1988 if (netif_tx_queue_stopped(nq))
1d17db08 1989 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
3f518509
MW		 1990 netif_tx_wake_queue(nq);
1991}
1992
213f428f 1993static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
850623b3 1994 unsigned int cpu)
edc660fa
MW		 1995{
1996 struct mvpp2_tx_queue *txq;
1997 struct mvpp2_txq_pcpu *txq_pcpu;
1998 unsigned int tx_todo = 0;
1999
2000 while (cause) {
2001 txq = mvpp2_get_tx_queue(port, cause);
2002 if (!txq)
2003 break;
2004
213f428f 2005 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
edc660fa
MW		 2006
2007 if (txq_pcpu->count) {
2008 mvpp2_txq_done(port, txq, txq_pcpu);
2009 tx_todo += txq_pcpu->count;
2010 }
2011
2012 cause &= ~(1 << txq->log_id);
2013 }
2014 return tx_todo;
2015}
2016
3f518509
MW		 2017/* Rx/Tx queue initialization/cleanup methods */
2018
2019/* Allocate and initialize descriptors for aggr TXQ */
2020static int mvpp2_aggr_txq_init(struct platform_device *pdev,
850623b3
AT		 2021 struct mvpp2_tx_queue *aggr_txq,
2022 unsigned int cpu, struct mvpp2 *priv)
3f518509 2023{
b02f31fb
TP		 2024 u32 txq_dma;
2025
3f518509 2026 /* Allocate memory for TX descriptors */
a154f8e3 2027 aggr_txq->descs = dma_zalloc_coherent(&pdev->dev,
85affd7e 2028 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
20396136 2029 &aggr_txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2030 if (!aggr_txq->descs)
2031 return -ENOMEM;
2032
02856a3b 2033 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
3f518509
MW		 2034
2035 /* Aggr TXQ no reset WA */
2036 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2037 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
2038
b02f31fb
TP		 2039 /* Set Tx descriptors queue starting address indirect
2040 * access
2041 */
2042 if (priv->hw_version == MVPP21)
2043 txq_dma = aggr_txq->descs_dma;
2044 else
2045 txq_dma = aggr_txq->descs_dma >>
2046 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2047
2048 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
85affd7e
AT		 2049 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu),
2050 MVPP2_AGGR_TXQ_SIZE);
3f518509
MW		 2051
2052 return 0;
2053}
2054
2055/* Create a specified Rx queue */
2056static int mvpp2_rxq_init(struct mvpp2_port *port,
2057 struct mvpp2_rx_queue *rxq)
2058
2059{
850623b3 2060 unsigned int cpu;
b02f31fb
TP		 2061 u32 rxq_dma;
2062
3f518509
MW		 2063 rxq->size = port->rx_ring_size;
2064
2065 /* Allocate memory for RX descriptors */
2066 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2067 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2068 &rxq->descs_dma, GFP_KERNEL);
3f518509
MW		 2069 if (!rxq->descs)
2070 return -ENOMEM;
2071
3f518509
MW		 2072 rxq->last_desc = rxq->size - 1;
2073
2074 /* Zero occupied and non-occupied counters - direct access */
2075 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2076
2077 /* Set Rx descriptors queue starting address - indirect access */
a704bb5c 2078 cpu = get_cpu();
a786841d 2079 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
b02f31fb
TP		 2080 if (port->priv->hw_version == MVPP21)
2081 rxq_dma = rxq->descs_dma;
2082 else
2083 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
a786841d
TP		 2084 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2085 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2086 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);
a704bb5c 2087 put_cpu();
3f518509
MW		 2088
2089 /* Set Offset */
2090 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2091
2092 /* Set coalescing pkts and time */
d63f9e41
TP		 2093 mvpp2_rx_pkts_coal_set(port, rxq);
2094 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 2095
2096 /* Add number of descriptors ready for receiving packets */
2097 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2098
2099 return 0;
2100}
2101
2102/* Push packets received by the RXQ to BM pool */
2103static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2104 struct mvpp2_rx_queue *rxq)
2105{
2106 int rx_received, i;
2107
2108 rx_received = mvpp2_rxq_received(port, rxq->id);
2109 if (!rx_received)
2110 return;
2111
2112 for (i = 0; i < rx_received; i++) {
2113 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
56b8aae9
TP		 2114 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2115 int pool;
2116
2117 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2118 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2119
7d7627ba 2120 mvpp2_bm_pool_put(port, pool,
ac3dd277
TP		 2121 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2122 mvpp2_rxdesc_cookie_get(port, rx_desc));
3f518509
MW		 2123 }
2124 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2125}
2126
2127/* Cleanup Rx queue */
2128static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2129 struct mvpp2_rx_queue *rxq)
2130{
850623b3 2131 unsigned int cpu;
a786841d 2132
3f518509
MW		 2133 mvpp2_rxq_drop_pkts(port, rxq);
2134
2135 if (rxq->descs)
2136 dma_free_coherent(port->dev->dev.parent,
2137 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2138 rxq->descs,
20396136 2139 rxq->descs_dma);
3f518509
MW		 2140
2141 rxq->descs = NULL;
2142 rxq->last_desc = 0;
2143 rxq->next_desc_to_proc = 0;
20396136 2144 rxq->descs_dma = 0;
3f518509
MW		 2145
2146 /* Clear Rx descriptors queue starting address and size;
2147 * free descriptor number
2148 */
2149 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
a704bb5c 2150 cpu = get_cpu();
a786841d
TP		 2151 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
2152 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);
2153 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);
a704bb5c 2154 put_cpu();
3f518509
MW		 2155}
2156
2157/* Create and initialize a Tx queue */
2158static int mvpp2_txq_init(struct mvpp2_port *port,
2159 struct mvpp2_tx_queue *txq)
2160{
2161 u32 val;
850623b3
AT		 2162 unsigned int cpu;
2163 int desc, desc_per_txq, tx_port_num;
3f518509
MW		 2164 struct mvpp2_txq_pcpu *txq_pcpu;
2165
2166 txq->size = port->tx_ring_size;
2167
2168 /* Allocate memory for Tx descriptors */
2169 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2170 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2171 &txq->descs_dma, GFP_KERNEL);
3f518509
MW		 2172 if (!txq->descs)
2173 return -ENOMEM;
2174
3f518509
MW		 2175 txq->last_desc = txq->size - 1;
2176
2177 /* Set Tx descriptors queue starting address - indirect access */
a704bb5c 2178 cpu = get_cpu();
a786841d
TP		 2179 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2180 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,
2181 txq->descs_dma);
2182 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG,
2183 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2184 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0);
2185 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG,
2186 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2187 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG);
3f518509 2188 val &= ~MVPP2_TXQ_PENDING_MASK;
a786841d 2189 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val);
3f518509
MW		 2190
2191 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2192 * for each existing TXQ.
2193 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
a3302baa 2194 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3f518509
MW		 2195 */
2196 desc_per_txq = 16;
2197 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2198 (txq->log_id * desc_per_txq);
2199
a786841d
TP		 2200 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,
2201 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2202 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
a704bb5c 2203 put_cpu();
3f518509
MW		 2204
2205 /* WRR / EJP configuration - indirect access */
2206 tx_port_num = mvpp2_egress_port(port);
2207 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2208
2209 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2210 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2211 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2212 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2213 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2214
2215 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2216 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2217 val);
2218
2219 for_each_present_cpu(cpu) {
2220 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2221 txq_pcpu->size = txq->size;
02c91ece
ME		 2222 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2223 sizeof(*txq_pcpu->buffs),
2224 GFP_KERNEL);
8354491c 2225 if (!txq_pcpu->buffs)
ba2d8d88 2226 return -ENOMEM;
3f518509
MW		 2227
2228 txq_pcpu->count = 0;
2229 txq_pcpu->reserved_num = 0;
2230 txq_pcpu->txq_put_index = 0;
2231 txq_pcpu->txq_get_index = 0;
b70d4a51 2232 txq_pcpu->tso_headers = NULL;
186cd4d4 2233
1d17db08
AT		 2234 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2235 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2236
186cd4d4
AT		 2237 txq_pcpu->tso_headers =
2238 dma_alloc_coherent(port->dev->dev.parent,
822eaf7c 2239 txq_pcpu->size * TSO_HEADER_SIZE,
186cd4d4
AT		 2240 &txq_pcpu->tso_headers_dma,
2241 GFP_KERNEL);
2242 if (!txq_pcpu->tso_headers)
ba2d8d88 2243 return -ENOMEM;
3f518509
MW		 2244 }
2245
2246 return 0;
2247}
2248
2249/* Free allocated TXQ resources */
2250static void mvpp2_txq_deinit(struct mvpp2_port *port,
2251 struct mvpp2_tx_queue *txq)
2252{
2253 struct mvpp2_txq_pcpu *txq_pcpu;
850623b3 2254 unsigned int cpu;
3f518509
MW		 2255
2256 for_each_present_cpu(cpu) {
2257 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
8354491c 2258 kfree(txq_pcpu->buffs);
186cd4d4 2259
b70d4a51
AT		 2260 if (txq_pcpu->tso_headers)
2261 dma_free_coherent(port->dev->dev.parent,
2262 txq_pcpu->size * TSO_HEADER_SIZE,
2263 txq_pcpu->tso_headers,
2264 txq_pcpu->tso_headers_dma);
2265
2266 txq_pcpu->tso_headers = NULL;
3f518509
MW		 2267 }
2268
2269 if (txq->descs)
2270 dma_free_coherent(port->dev->dev.parent,
2271 txq->size * MVPP2_DESC_ALIGNED_SIZE,
20396136 2272 txq->descs, txq->descs_dma);
3f518509
MW		 2273
2274 txq->descs = NULL;
2275 txq->last_desc = 0;
2276 txq->next_desc_to_proc = 0;
20396136 2277 txq->descs_dma = 0;
3f518509
MW		 2278
2279 /* Set minimum bandwidth for disabled TXQs */
2280 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
2281
2282 /* Set Tx descriptors queue starting address and size */
a704bb5c 2283 cpu = get_cpu();
a786841d
TP		 2284 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2285 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);
2286 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);
a704bb5c 2287 put_cpu();
3f518509
MW		 2288}
2289
2290/* Cleanup Tx ports */
2291static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2292{
2293 struct mvpp2_txq_pcpu *txq_pcpu;
850623b3
AT		 2294 int delay, pending;
2295 unsigned int cpu;
3f518509
MW		 2296 u32 val;
2297
a704bb5c 2298 cpu = get_cpu();
a786841d
TP		 2299 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2300 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);
3f518509 2301 val |= MVPP2_TXQ_DRAIN_EN_MASK;
a786841d 2302 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
3f518509
MW		 2303
2304 /* The napi queue has been stopped so wait for all packets
2305 * to be transmitted.
2306 */
2307 delay = 0;
2308 do {
2309 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2310 netdev_warn(port->dev,
2311 "port %d: cleaning queue %d timed out\n",
2312 port->id, txq->log_id);
2313 break;
2314 }
2315 mdelay(1);
2316 delay++;
2317
a786841d
TP		 2318 pending = mvpp2_percpu_read(port->priv, cpu,
2319 MVPP2_TXQ_PENDING_REG);
2320 pending &= MVPP2_TXQ_PENDING_MASK;
3f518509
MW		 2321 } while (pending);
2322
2323 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
a786841d 2324 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
a704bb5c 2325 put_cpu();
3f518509
MW		 2326
2327 for_each_present_cpu(cpu) {
2328 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2329
2330 /* Release all packets */
2331 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2332
2333 /* Reset queue */
2334 txq_pcpu->count = 0;
2335 txq_pcpu->txq_put_index = 0;
2336 txq_pcpu->txq_get_index = 0;
2337 }
2338}
2339
2340/* Cleanup all Tx queues */
2341static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2342{
2343 struct mvpp2_tx_queue *txq;
2344 int queue;
2345 u32 val;
2346
2347 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2348
2349 /* Reset Tx ports and delete Tx queues */
2350 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2351 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2352
09f83975 2353 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2354 txq = port->txqs[queue];
2355 mvpp2_txq_clean(port, txq);
2356 mvpp2_txq_deinit(port, txq);
2357 }
2358
2359 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2360
2361 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2362 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2363}
2364
2365/* Cleanup all Rx queues */
2366static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2367{
2368 int queue;
2369
09f83975 2370 for (queue = 0; queue < port->nrxqs; queue++)
3f518509
MW		 2371 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2372}
2373
2374/* Init all Rx queues for port */
2375static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2376{
2377 int queue, err;
2378
09f83975 2379 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 2380 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2381 if (err)
2382 goto err_cleanup;
2383 }
2384 return 0;
2385
2386err_cleanup:
2387 mvpp2_cleanup_rxqs(port);
2388 return err;
2389}
2390
2391/* Init all tx queues for port */
2392static int mvpp2_setup_txqs(struct mvpp2_port *port)
2393{
2394 struct mvpp2_tx_queue *txq;
2395 int queue, err;
2396
09f83975 2397 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 2398 txq = port->txqs[queue];
2399 err = mvpp2_txq_init(port, txq);
2400 if (err)
2401 goto err_cleanup;
2402 }
2403
213f428f
TP		 2404 if (port->has_tx_irqs) {
2405 mvpp2_tx_time_coal_set(port);
2406 for (queue = 0; queue < port->ntxqs; queue++) {
2407 txq = port->txqs[queue];
2408 mvpp2_tx_pkts_coal_set(port, txq);
2409 }
2410 }
2411
3f518509
MW		 2412 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2413 return 0;
2414
2415err_cleanup:
2416 mvpp2_cleanup_txqs(port);
2417 return err;
2418}
2419
2420/* The callback for per-port interrupt */
2421static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2422{
591f4cfa 2423 struct mvpp2_queue_vector *qv = dev_id;
3f518509 2424
591f4cfa 2425 mvpp2_qvec_interrupt_disable(qv);
3f518509 2426
591f4cfa 2427 napi_schedule(&qv->napi);
3f518509
MW		 2428
2429 return IRQ_HANDLED;
2430}
2431
fd3651b2
AT		 2432/* Per-port interrupt for link status changes */
2433static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2434{
2435 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2436 struct net_device *dev = port->dev;
2437 bool event = false, link = false;
2438 u32 val;
2439
2440 mvpp22_gop_mask_irq(port);
2441
2442 if (port->gop_id == 0 &&
2443 port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
2444 val = readl(port->base + MVPP22_XLG_INT_STAT);
2445 if (val & MVPP22_XLG_INT_STAT_LINK) {
2446 event = true;
2447 val = readl(port->base + MVPP22_XLG_STATUS);
2448 if (val & MVPP22_XLG_STATUS_LINK_UP)
2449 link = true;
2450 }
2451 } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
d97c9f4a 2452 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 2453 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
2454 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
fd3651b2
AT		 2455 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2456 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2457 event = true;
2458 val = readl(port->base + MVPP2_GMAC_STATUS0);
2459 if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2460 link = true;
2461 }
2462 }
2463
4bb04326
AT		 2464 if (port->phylink) {
2465 phylink_mac_change(port->phylink, link);
2466 goto handled;
2467 }
2468
fd3651b2
AT		 2469 if (!netif_running(dev) || !event)
2470 goto handled;
2471
2472 if (link) {
2473 mvpp2_interrupts_enable(port);
2474
2475 mvpp2_egress_enable(port);
2476 mvpp2_ingress_enable(port);
2477 netif_carrier_on(dev);
2478 netif_tx_wake_all_queues(dev);
2479 } else {
2480 netif_tx_stop_all_queues(dev);
2481 netif_carrier_off(dev);
2482 mvpp2_ingress_disable(port);
2483 mvpp2_egress_disable(port);
2484
2485 mvpp2_interrupts_disable(port);
2486 }
2487
2488handled:
2489 mvpp22_gop_unmask_irq(port);
2490 return IRQ_HANDLED;
2491}
2492
edc660fa
MW		 2493static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2494{
2495 ktime_t interval;
2496
2497 if (!port_pcpu->timer_scheduled) {
2498 port_pcpu->timer_scheduled = true;
8b0e1953 2499 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
edc660fa
MW		 2500 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2501 HRTIMER_MODE_REL_PINNED);
2502 }
2503}
2504
2505static void mvpp2_tx_proc_cb(unsigned long data)
2506{
2507 struct net_device *dev = (struct net_device *)data;
2508 struct mvpp2_port *port = netdev_priv(dev);
2509 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
2510 unsigned int tx_todo, cause;
2511
2512 if (!netif_running(dev))
2513 return;
2514 port_pcpu->timer_scheduled = false;
2515
2516 /* Process all the Tx queues */
09f83975 2517 cause = (1 << port->ntxqs) - 1;
213f428f 2518 tx_todo = mvpp2_tx_done(port, cause, smp_processor_id());
edc660fa
MW		 2519
2520 /* Set the timer in case not all the packets were processed */
2521 if (tx_todo)
2522 mvpp2_timer_set(port_pcpu);
2523}
2524
2525static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2526{
2527 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2528 struct mvpp2_port_pcpu,
2529 tx_done_timer);
2530
2531 tasklet_schedule(&port_pcpu->tx_done_tasklet);
2532
2533 return HRTIMER_NORESTART;
2534}
2535
3f518509
MW		 2536/* Main RX/TX processing routines */
2537
2538/* Display more error info */
2539static void mvpp2_rx_error(struct mvpp2_port *port,
2540 struct mvpp2_rx_desc *rx_desc)
2541{
ac3dd277
TP		 2542 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2543 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
934e0f83 2544 char *err_str = NULL;
3f518509
MW		 2545
2546 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2547 case MVPP2_RXD_ERR_CRC:
934e0f83 2548 err_str = "crc";
3f518509
MW		 2549 break;
2550 case MVPP2_RXD_ERR_OVERRUN:
934e0f83 2551 err_str = "overrun";
3f518509
MW		 2552 break;
2553 case MVPP2_RXD_ERR_RESOURCE:
934e0f83 2554 err_str = "resource";
3f518509
MW		 2555 break;
2556 }
934e0f83
YM		 2557 if (err_str && net_ratelimit())
2558 netdev_err(port->dev,
2559 "bad rx status %08x (%s error), size=%zu\n",
2560 status, err_str, sz);
3f518509
MW		 2561}
2562
2563/* Handle RX checksum offload */
2564static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2565 struct sk_buff *skb)
2566{
2567 if (((status & MVPP2_RXD_L3_IP4) &&
2568 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2569 (status & MVPP2_RXD_L3_IP6))
2570 if (((status & MVPP2_RXD_L4_UDP) ||
2571 (status & MVPP2_RXD_L4_TCP)) &&
2572 (status & MVPP2_RXD_L4_CSUM_OK)) {
2573 skb->csum = 0;
2574 skb->ip_summed = CHECKSUM_UNNECESSARY;
2575 return;
2576 }
2577
2578 skb->ip_summed = CHECKSUM_NONE;
2579}
2580
2581/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2582static int mvpp2_rx_refill(struct mvpp2_port *port,
56b8aae9 2583 struct mvpp2_bm_pool *bm_pool, int pool)
3f518509 2584{
20396136 2585 dma_addr_t dma_addr;
4e4a105f 2586 phys_addr_t phys_addr;
0e037281 2587 void *buf;
3f518509 2588
3f518509 2589 /* No recycle or too many buffers are in use, so allocate a new skb */
4e4a105f
TP		 2590 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2591 GFP_ATOMIC);
0e037281 2592 if (!buf)
3f518509
MW		 2593 return -ENOMEM;
2594
7d7627ba 2595 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
7ef7e1d9 2596
3f518509
MW		 2597 return 0;
2598}
2599
2600/* Handle tx checksum */
2601static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2602{
2603 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2604 int ip_hdr_len = 0;
2605 u8 l4_proto;
2606
2607 if (skb->protocol == htons(ETH_P_IP)) {
2608 struct iphdr *ip4h = ip_hdr(skb);
2609
2610 /* Calculate IPv4 checksum and L4 checksum */
2611 ip_hdr_len = ip4h->ihl;
2612 l4_proto = ip4h->protocol;
2613 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2614 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2615
2616 /* Read l4_protocol from one of IPv6 extra headers */
2617 if (skb_network_header_len(skb) > 0)
2618 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2619 l4_proto = ip6h->nexthdr;
2620 } else {
2621 return MVPP2_TXD_L4_CSUM_NOT;
2622 }
2623
2624 return mvpp2_txq_desc_csum(skb_network_offset(skb),
2625 skb->protocol, ip_hdr_len, l4_proto);
2626 }
2627
2628 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2629}
2630
3f518509 2631/* Main rx processing */
591f4cfa
TP		 2632static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2633 int rx_todo, struct mvpp2_rx_queue *rxq)
3f518509
MW		 2634{
2635 struct net_device *dev = port->dev;
b5015854
MW		 2636 int rx_received;
2637 int rx_done = 0;
3f518509
MW		 2638 u32 rcvd_pkts = 0;
2639 u32 rcvd_bytes = 0;
2640
2641 /* Get number of received packets and clamp the to-do */
2642 rx_received = mvpp2_rxq_received(port, rxq->id);
2643 if (rx_todo > rx_received)
2644 rx_todo = rx_received;
2645
b5015854 2646 while (rx_done < rx_todo) {
3f518509
MW		 2647 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2648 struct mvpp2_bm_pool *bm_pool;
2649 struct sk_buff *skb;
0e037281 2650 unsigned int frag_size;
20396136 2651 dma_addr_t dma_addr;
ac3dd277 2652 phys_addr_t phys_addr;
56b8aae9 2653 u32 rx_status;
3f518509 2654 int pool, rx_bytes, err;
0e037281 2655 void *data;
3f518509 2656
b5015854 2657 rx_done++;
ac3dd277
TP		 2658 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2659 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2660 rx_bytes -= MVPP2_MH_SIZE;
2661 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2662 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2663 data = (void *)phys_to_virt(phys_addr);
2664
56b8aae9
TP		 2665 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2666 MVPP2_RXD_BM_POOL_ID_OFFS;
3f518509 2667 bm_pool = &port->priv->bm_pools[pool];
3f518509
MW		 2668
2669 /* In case of an error, release the requested buffer pointer
2670 * to the Buffer Manager. This request process is controlled
2671 * by the hardware, and the information about the buffer is
2672 * comprised by the RX descriptor.
2673 */
2674 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
8a52488b 2675err_drop_frame:
3f518509
MW		 2676 dev->stats.rx_errors++;
2677 mvpp2_rx_error(port, rx_desc);
b5015854 2678 /* Return the buffer to the pool */
7d7627ba 2679 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3f518509
MW		 2680 continue;
2681 }
2682
0e037281
TP		 2683 if (bm_pool->frag_size > PAGE_SIZE)
2684 frag_size = 0;
2685 else
2686 frag_size = bm_pool->frag_size;
2687
2688 skb = build_skb(data, frag_size);
2689 if (!skb) {
2690 netdev_warn(port->dev, "skb build failed\n");
2691 goto err_drop_frame;
2692 }
3f518509 2693
56b8aae9 2694 err = mvpp2_rx_refill(port, bm_pool, pool);
b5015854
MW		 2695 if (err) {
2696 netdev_err(port->dev, "failed to refill BM pools\n");
2697 goto err_drop_frame;
2698 }
2699
20396136 2700 dma_unmap_single(dev->dev.parent, dma_addr,
4229d502
MW		 2701 bm_pool->buf_size, DMA_FROM_DEVICE);
2702
3f518509
MW		 2703 rcvd_pkts++;
2704 rcvd_bytes += rx_bytes;
3f518509 2705
0e037281 2706 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
3f518509
MW		 2707 skb_put(skb, rx_bytes);
2708 skb->protocol = eth_type_trans(skb, dev);
2709 mvpp2_rx_csum(port, rx_status, skb);
2710
591f4cfa 2711 napi_gro_receive(napi, skb);
3f518509
MW		 2712 }
2713
2714 if (rcvd_pkts) {
2715 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2716
2717 u64_stats_update_begin(&stats->syncp);
2718 stats->rx_packets += rcvd_pkts;
2719 stats->rx_bytes += rcvd_bytes;
2720 u64_stats_update_end(&stats->syncp);
2721 }
2722
2723 /* Update Rx queue management counters */
2724 wmb();
b5015854 2725 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
3f518509
MW		 2726
2727 return rx_todo;
2728}
2729
2730static inline void
ac3dd277 2731tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
3f518509
MW		 2732 struct mvpp2_tx_desc *desc)
2733{
20920267
AT		 2734 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
2735
ac3dd277
TP		 2736 dma_addr_t buf_dma_addr =
2737 mvpp2_txdesc_dma_addr_get(port, desc);
2738 size_t buf_sz =
2739 mvpp2_txdesc_size_get(port, desc);
20920267
AT		 2740 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2741 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2742 buf_sz, DMA_TO_DEVICE);
3f518509
MW		 2743 mvpp2_txq_desc_put(txq);
2744}
2745
2746/* Handle tx fragmentation processing */
2747static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2748 struct mvpp2_tx_queue *aggr_txq,
2749 struct mvpp2_tx_queue *txq)
2750{
2751 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
2752 struct mvpp2_tx_desc *tx_desc;
2753 int i;
20396136 2754 dma_addr_t buf_dma_addr;
3f518509
MW		 2755
2756 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2757 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2758 void *addr = page_address(frag->page.p) + frag->page_offset;
2759
2760 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 2761 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2762 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
3f518509 2763
20396136 2764 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
a3302baa 2765 frag->size, DMA_TO_DEVICE);
20396136 2766 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
3f518509 2767 mvpp2_txq_desc_put(txq);
32bae631 2768 goto cleanup;
3f518509
MW		 2769 }
2770
6eb5d375 2771 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 2772
2773 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2774 /* Last descriptor */
ac3dd277
TP		 2775 mvpp2_txdesc_cmd_set(port, tx_desc,
2776 MVPP2_TXD_L_DESC);
2777 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 2778 } else {
2779 /* Descriptor in the middle: Not First, Not Last */
ac3dd277
TP		 2780 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2781 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 2782 }
2783 }
2784
2785 return 0;
32bae631 2786cleanup:
3f518509
MW		 2787 /* Release all descriptors that were used to map fragments of
2788 * this packet, as well as the corresponding DMA mappings
2789 */
2790 for (i = i - 1; i >= 0; i--) {
2791 tx_desc = txq->descs + i;
ac3dd277 2792 tx_desc_unmap_put(port, txq, tx_desc);
3f518509
MW		 2793 }
2794
2795 return -ENOMEM;
2796}
2797
186cd4d4
AT		 2798static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2799 struct net_device *dev,
2800 struct mvpp2_tx_queue *txq,
2801 struct mvpp2_tx_queue *aggr_txq,
2802 struct mvpp2_txq_pcpu *txq_pcpu,
2803 int hdr_sz)
2804{
2805 struct mvpp2_port *port = netdev_priv(dev);
2806 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2807 dma_addr_t addr;
2808
2809 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2810 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2811
2812 addr = txq_pcpu->tso_headers_dma +
2813 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
6eb5d375 2814 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
186cd4d4
AT		 2815
2816 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2817 MVPP2_TXD_F_DESC |
2818 MVPP2_TXD_PADDING_DISABLE);
2819 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2820}
2821
2822static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2823 struct net_device *dev, struct tso_t *tso,
2824 struct mvpp2_tx_queue *txq,
2825 struct mvpp2_tx_queue *aggr_txq,
2826 struct mvpp2_txq_pcpu *txq_pcpu,
2827 int sz, bool left, bool last)
2828{
2829 struct mvpp2_port *port = netdev_priv(dev);
2830 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2831 dma_addr_t buf_dma_addr;
2832
2833 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2834 mvpp2_txdesc_size_set(port, tx_desc, sz);
2835
2836 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
2837 DMA_TO_DEVICE);
2838 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2839 mvpp2_txq_desc_put(txq);
2840 return -ENOMEM;
2841 }
2842
6eb5d375 2843 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
186cd4d4
AT		 2844
2845 if (!left) {
2846 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
2847 if (last) {
2848 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2849 return 0;
2850 }
2851 } else {
2852 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2853 }
2854
2855 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2856 return 0;
2857}
2858
2859static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
2860 struct mvpp2_tx_queue *txq,
2861 struct mvpp2_tx_queue *aggr_txq,
2862 struct mvpp2_txq_pcpu *txq_pcpu)
2863{
2864 struct mvpp2_port *port = netdev_priv(dev);
2865 struct tso_t tso;
2866 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
2867 int i, len, descs = 0;
2868
2869 /* Check number of available descriptors */
2870 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq,
2871 tso_count_descs(skb)) ||
2872 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu,
2873 tso_count_descs(skb)))
2874 return 0;
2875
2876 tso_start(skb, &tso);
2877 len = skb->len - hdr_sz;
2878 while (len > 0) {
2879 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
2880 char *hdr = txq_pcpu->tso_headers +
2881 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2882
2883 len -= left;
2884 descs++;
2885
2886 tso_build_hdr(skb, hdr, &tso, left, len == 0);
2887 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
2888
2889 while (left > 0) {
2890 int sz = min_t(int, tso.size, left);
2891 left -= sz;
2892 descs++;
2893
2894 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
2895 txq_pcpu, sz, left, len == 0))
2896 goto release;
2897 tso_build_data(skb, &tso, sz);
2898 }
2899 }
2900
2901 return descs;
2902
2903release:
2904 for (i = descs - 1; i >= 0; i--) {
2905 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
2906 tx_desc_unmap_put(port, txq, tx_desc);
2907 }
2908 return 0;
2909}
2910
3f518509
MW		 2911/* Main tx processing */
2912static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
2913{
2914 struct mvpp2_port *port = netdev_priv(dev);
2915 struct mvpp2_tx_queue *txq, *aggr_txq;
2916 struct mvpp2_txq_pcpu *txq_pcpu;
2917 struct mvpp2_tx_desc *tx_desc;
20396136 2918 dma_addr_t buf_dma_addr;
3f518509
MW		 2919 int frags = 0;
2920 u16 txq_id;
2921 u32 tx_cmd;
2922
2923 txq_id = skb_get_queue_mapping(skb);
2924 txq = port->txqs[txq_id];
2925 txq_pcpu = this_cpu_ptr(txq->pcpu);
2926 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
2927
186cd4d4
AT		 2928 if (skb_is_gso(skb)) {
2929 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
2930 goto out;
2931 }
3f518509
MW		 2932 frags = skb_shinfo(skb)->nr_frags + 1;
2933
2934 /* Check number of available descriptors */
2935 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) ||
2936 mvpp2_txq_reserved_desc_num_proc(port->priv, txq,
2937 txq_pcpu, frags)) {
2938 frags = 0;
2939 goto out;
2940 }
2941
2942 /* Get a descriptor for the first part of the packet */
2943 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
ac3dd277
TP		 2944 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2945 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
3f518509 2946
20396136 2947 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
ac3dd277 2948 skb_headlen(skb), DMA_TO_DEVICE);
20396136 2949 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3f518509
MW		 2950 mvpp2_txq_desc_put(txq);
2951 frags = 0;
2952 goto out;
2953 }
ac3dd277 2954
6eb5d375 2955 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3f518509
MW		 2956
2957 tx_cmd = mvpp2_skb_tx_csum(port, skb);
2958
2959 if (frags == 1) {
2960 /* First and Last descriptor */
2961 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
ac3dd277
TP		 2962 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
2963 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3f518509
MW		 2964 } else {
2965 /* First but not Last */
2966 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
ac3dd277
TP		 2967 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
2968 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3f518509
MW		 2969
2970 /* Continue with other skb fragments */
2971 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
ac3dd277 2972 tx_desc_unmap_put(port, txq, tx_desc);
3f518509 2973 frags = 0;
3f518509
MW		 2974 }
2975 }
2976
3f518509
MW		 2977out:
2978 if (frags > 0) {
2979 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
186cd4d4
AT		 2980 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2981
2982 txq_pcpu->reserved_num -= frags;
2983 txq_pcpu->count += frags;
2984 aggr_txq->count += frags;
2985
2986 /* Enable transmit */
2987 wmb();
2988 mvpp2_aggr_txq_pend_desc_add(port, frags);
2989
1d17db08 2990 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
186cd4d4 2991 netif_tx_stop_queue(nq);
3f518509
MW		 2992
2993 u64_stats_update_begin(&stats->syncp);
2994 stats->tx_packets++;
2995 stats->tx_bytes += skb->len;
2996 u64_stats_update_end(&stats->syncp);
2997 } else {
2998 dev->stats.tx_dropped++;
2999 dev_kfree_skb_any(skb);
3000 }
3001
edc660fa 3002 /* Finalize TX processing */
082297e6 3003 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
edc660fa
MW		 3004 mvpp2_txq_done(port, txq, txq_pcpu);
3005
3006 /* Set the timer in case not all frags were processed */
213f428f
TP		 3007 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3008 txq_pcpu->count > 0) {
edc660fa
MW		 3009 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
3010
3011 mvpp2_timer_set(port_pcpu);
3012 }
3013
3f518509
MW		 3014 return NETDEV_TX_OK;
3015}
3016
3017static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3018{
3019 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3020 netdev_err(dev, "FCS error\n");
3021 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3022 netdev_err(dev, "rx fifo overrun error\n");
3023 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3024 netdev_err(dev, "tx fifo underrun error\n");
3025}
3026
edc660fa 3027static int mvpp2_poll(struct napi_struct *napi, int budget)
3f518509 3028{
213f428f 3029 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
edc660fa
MW		 3030 int rx_done = 0;
3031 struct mvpp2_port *port = netdev_priv(napi->dev);
591f4cfa 3032 struct mvpp2_queue_vector *qv;
850623b3 3033 unsigned int cpu = smp_processor_id();
3f518509 3034
591f4cfa
TP		 3035 qv = container_of(napi, struct mvpp2_queue_vector, napi);
3036
3f518509
MW		 3037 /* Rx/Tx cause register
3038 *
3039 * Bits 0-15: each bit indicates received packets on the Rx queue
3040 * (bit 0 is for Rx queue 0).
3041 *
3042 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3043 * (bit 16 is for Tx queue 0).
3044 *
3045 * Each CPU has its own Rx/Tx cause register
3046 */
cdcfeb0f
YM		 3047 cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id,
3048 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3f518509 3049
213f428f 3050 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3f518509
MW		 3051 if (cause_misc) {
3052 mvpp2_cause_error(port->dev, cause_misc);
3053
3054 /* Clear the cause register */
3055 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
a786841d
TP		 3056 mvpp2_percpu_write(port->priv, cpu,
3057 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3058 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3f518509
MW		 3059 }
3060
213f428f
TP		 3061 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3062 if (cause_tx) {
3063 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3064 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3065 }
3f518509
MW		 3066
3067 /* Process RX packets */
70afb58e
AT		 3068 cause_rx = cause_rx_tx &
3069 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
213f428f 3070 cause_rx <<= qv->first_rxq;
591f4cfa 3071 cause_rx |= qv->pending_cause_rx;
3f518509
MW		 3072 while (cause_rx && budget > 0) {
3073 int count;
3074 struct mvpp2_rx_queue *rxq;
3075
3076 rxq = mvpp2_get_rx_queue(port, cause_rx);
3077 if (!rxq)
3078 break;
3079
591f4cfa 3080 count = mvpp2_rx(port, napi, budget, rxq);
3f518509
MW		 3081 rx_done += count;
3082 budget -= count;
3083 if (budget > 0) {
3084 /* Clear the bit associated to this Rx queue
3085 * so that next iteration will continue from
3086 * the next Rx queue.
3087 */
3088 cause_rx &= ~(1 << rxq->logic_rxq);
3089 }
3090 }
3091
3092 if (budget > 0) {
3093 cause_rx = 0;
6ad20165 3094 napi_complete_done(napi, rx_done);
3f518509 3095
591f4cfa 3096 mvpp2_qvec_interrupt_enable(qv);
3f518509 3097 }
591f4cfa 3098 qv->pending_cause_rx = cause_rx;
3f518509
MW		 3099 return rx_done;
3100}
3101
4bb04326 3102static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3f518509 3103{
4bb04326
AT		 3104 u32 ctrl3;
3105
3106 /* comphy reconfiguration */
3107 mvpp22_comphy_init(port);
3108
3109 /* gop reconfiguration */
3110 mvpp22_gop_init(port);
3111
3112 /* Only GOP port 0 has an XLG MAC */
3113 if (port->gop_id == 0) {
3114 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3115 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3116
3117 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3118 port->phy_interface == PHY_INTERFACE_MODE_10GKR)
3119 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3120 else
3121 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3122
3123 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3124 }
8e07269d 3125
76eb1b1d
SC		 3126 if (port->gop_id == 0 &&
3127 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3128 port->phy_interface == PHY_INTERFACE_MODE_10GKR))
3129 mvpp2_xlg_max_rx_size_set(port);
3130 else
3131 mvpp2_gmac_max_rx_size_set(port);
4bb04326
AT		 3132}
3133
3134/* Set hw internals when starting port */
3135static void mvpp2_start_dev(struct mvpp2_port *port)
3136{
3137 int i;
76eb1b1d 3138
3f518509
MW		 3139 mvpp2_txp_max_tx_size_set(port);
3140
591f4cfa
TP		 3141 for (i = 0; i < port->nqvecs; i++)
3142 napi_enable(&port->qvecs[i].napi);
3f518509
MW		 3143
3144 /* Enable interrupts on all CPUs */
3145 mvpp2_interrupts_enable(port);
3146
4bb04326
AT		 3147 if (port->priv->hw_version == MVPP22)
3148 mvpp22_mode_reconfigure(port);
3149
3150 if (port->phylink) {
41948ccb 3151 netif_carrier_off(port->dev);
4bb04326
AT		 3152 phylink_start(port->phylink);
3153 } else {
3154 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3155 * configured manually when the interface is started. This will
3156 * be removed as soon as the phylink ACPI support lands in.
3157 */
3158 struct phylink_link_state state = {
3159 .interface = port->phy_interface,
4bb04326
AT		 3160 };
3161 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
41948ccb
AT		 3162 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface,
3163 NULL);
542897d9 3164 }
f84bf386 3165
3f518509
MW		 3166 netif_tx_start_all_queues(port->dev);
3167}
3168
3169/* Set hw internals when stopping port */
3170static void mvpp2_stop_dev(struct mvpp2_port *port)
3171{
591f4cfa 3172 int i;
8e07269d 3173
3f518509
MW		 3174 /* Disable interrupts on all CPUs */
3175 mvpp2_interrupts_disable(port);
3176
591f4cfa
TP		 3177 for (i = 0; i < port->nqvecs; i++)
3178 napi_disable(&port->qvecs[i].napi);
3f518509 3179
4bb04326
AT		 3180 if (port->phylink)
3181 phylink_stop(port->phylink);
542897d9 3182 phy_power_off(port->comphy);
3f518509
MW		 3183}
3184
3f518509
MW		 3185static int mvpp2_check_ringparam_valid(struct net_device *dev,
3186 struct ethtool_ringparam *ring)
3187{
3188 u16 new_rx_pending = ring->rx_pending;
3189 u16 new_tx_pending = ring->tx_pending;
3190
3191 if (ring->rx_pending == 0 || ring->tx_pending == 0)
3192 return -EINVAL;
3193
7cf87e4a
YM		 3194 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3195 new_rx_pending = MVPP2_MAX_RXD_MAX;
3f518509
MW		 3196 else if (!IS_ALIGNED(ring->rx_pending, 16))
3197 new_rx_pending = ALIGN(ring->rx_pending, 16);
3198
7cf87e4a
YM		 3199 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3200 new_tx_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3201 else if (!IS_ALIGNED(ring->tx_pending, 32))
3202 new_tx_pending = ALIGN(ring->tx_pending, 32);
3203
76e583c5
AT		 3204 /* The Tx ring size cannot be smaller than the minimum number of
3205 * descriptors needed for TSO.
3206 */
3207 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3208 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3209
3f518509
MW		 3210 if (ring->rx_pending != new_rx_pending) {
3211 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3212 ring->rx_pending, new_rx_pending);
3213 ring->rx_pending = new_rx_pending;
3214 }
3215
3216 if (ring->tx_pending != new_tx_pending) {
3217 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3218 ring->tx_pending, new_tx_pending);
3219 ring->tx_pending = new_tx_pending;
3220 }
3221
3222 return 0;
3223}
3224
26975821 3225static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3f518509
MW		 3226{
3227 u32 mac_addr_l, mac_addr_m, mac_addr_h;
3228
3229 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3230 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3231 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3232 addr[0] = (mac_addr_h >> 24) & 0xFF;
3233 addr[1] = (mac_addr_h >> 16) & 0xFF;
3234 addr[2] = (mac_addr_h >> 8) & 0xFF;
3235 addr[3] = mac_addr_h & 0xFF;
3236 addr[4] = mac_addr_m & 0xFF;
3237 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3238}
3239
591f4cfa
TP		 3240static int mvpp2_irqs_init(struct mvpp2_port *port)
3241{
3242 int err, i;
3243
3244 for (i = 0; i < port->nqvecs; i++) {
3245 struct mvpp2_queue_vector *qv = port->qvecs + i;
3246
13c249a9
MZ		 3247 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3248 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
3249
591f4cfa
TP		 3250 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3251 if (err)
3252 goto err;
213f428f
TP		 3253
3254 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3255 irq_set_affinity_hint(qv->irq,
3256 cpumask_of(qv->sw_thread_id));
591f4cfa
TP		 3257 }
3258
3259 return 0;
3260err:
3261 for (i = 0; i < port->nqvecs; i++) {
3262 struct mvpp2_queue_vector *qv = port->qvecs + i;
3263
213f428f 3264 irq_set_affinity_hint(qv->irq, NULL);
591f4cfa
TP		 3265 free_irq(qv->irq, qv);
3266 }
3267
3268 return err;
3269}
3270
3271static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3272{
3273 int i;
3274
3275 for (i = 0; i < port->nqvecs; i++) {
3276 struct mvpp2_queue_vector *qv = port->qvecs + i;
3277
213f428f 3278 irq_set_affinity_hint(qv->irq, NULL);
13c249a9 3279 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
591f4cfa
TP		 3280 free_irq(qv->irq, qv);
3281 }
3282}
3283
4c4a5686
YM		 3284static bool mvpp22_rss_is_supported(void)
3285{
3286 return queue_mode == MVPP2_QDIST_MULTI_MODE;
3287}
3288
3f518509
MW		 3289static int mvpp2_open(struct net_device *dev)
3290{
3291 struct mvpp2_port *port = netdev_priv(dev);
fd3651b2 3292 struct mvpp2 *priv = port->priv;
3f518509
MW		 3293 unsigned char mac_bcast[ETH_ALEN] = {
3294 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4bb04326 3295 bool valid = false;
3f518509
MW		 3296 int err;
3297
ce2a27c7 3298 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3f518509
MW		 3299 if (err) {
3300 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3301 return err;
3302 }
ce2a27c7 3303 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3f518509 3304 if (err) {
ce2a27c7 3305 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3f518509
MW		 3306 return err;
3307 }
3308 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3309 if (err) {
3310 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3311 return err;
3312 }
3313 err = mvpp2_prs_def_flow(port);
3314 if (err) {
3315 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3316 return err;
3317 }
3318
3319 /* Allocate the Rx/Tx queues */
3320 err = mvpp2_setup_rxqs(port);
3321 if (err) {
3322 netdev_err(port->dev, "cannot allocate Rx queues\n");
3323 return err;
3324 }
3325
3326 err = mvpp2_setup_txqs(port);
3327 if (err) {
3328 netdev_err(port->dev, "cannot allocate Tx queues\n");
3329 goto err_cleanup_rxqs;
3330 }
3331
591f4cfa 3332 err = mvpp2_irqs_init(port);
3f518509 3333 if (err) {
591f4cfa 3334 netdev_err(port->dev, "cannot init IRQs\n");
3f518509
MW		 3335 goto err_cleanup_txqs;
3336 }
3337
4bb04326
AT		 3338 /* Phylink isn't supported yet in ACPI mode */
3339 if (port->of_node) {
3340 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3341 if (err) {
3342 netdev_err(port->dev, "could not attach PHY (%d)\n",
3343 err);
3344 goto err_free_irq;
3345 }
3346
3347 valid = true;
3348 }
3349
3350 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
fd3651b2
AT		 3351 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3352 dev->name, port);
3353 if (err) {
3354 netdev_err(port->dev, "cannot request link IRQ %d\n",
3355 port->link_irq);
3356 goto err_free_irq;
3357 }
3358
3359 mvpp22_gop_setup_irq(port);
fd3651b2 3360
4bb04326
AT		 3361 /* In default link is down */
3362 netif_carrier_off(port->dev);
3f518509 3363
4bb04326
AT		 3364 valid = true;
3365 } else {
3366 port->link_irq = 0;
3367 }
3368
3369 if (!valid) {
3370 netdev_err(port->dev,
3371 "invalid configuration: no dt or link IRQ");
3372 goto err_free_irq;
3373 }
3f518509
MW		 3374
3375 /* Unmask interrupts on all CPUs */
3376 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
213f428f 3377 mvpp2_shared_interrupt_mask_unmask(port, false);
3f518509
MW		 3378
3379 mvpp2_start_dev(port);
3380
118d6298 3381 /* Start hardware statistics gathering */
e5c500eb 3382 queue_delayed_work(priv->stats_queue, &port->stats_work,
118d6298
MR		 3383 MVPP2_MIB_COUNTERS_STATS_DELAY);
3384
3f518509
MW		 3385 return 0;
3386
3387err_free_irq:
591f4cfa 3388 mvpp2_irqs_deinit(port);
3f518509
MW		 3389err_cleanup_txqs:
3390 mvpp2_cleanup_txqs(port);
3391err_cleanup_rxqs:
3392 mvpp2_cleanup_rxqs(port);
3393 return err;
3394}
3395
3396static int mvpp2_stop(struct net_device *dev)
3397{
3398 struct mvpp2_port *port = netdev_priv(dev);
edc660fa 3399 struct mvpp2_port_pcpu *port_pcpu;
850623b3 3400 unsigned int cpu;
3f518509
MW		 3401
3402 mvpp2_stop_dev(port);
3f518509
MW		 3403
3404 /* Mask interrupts on all CPUs */
3405 on_each_cpu(mvpp2_interrupts_mask, port, 1);
213f428f 3406 mvpp2_shared_interrupt_mask_unmask(port, true);
3f518509 3407
4bb04326
AT		 3408 if (port->phylink)
3409 phylink_disconnect_phy(port->phylink);
3410 if (port->link_irq)
fd3651b2
AT		 3411 free_irq(port->link_irq, port);
3412
591f4cfa 3413 mvpp2_irqs_deinit(port);
213f428f
TP		 3414 if (!port->has_tx_irqs) {
3415 for_each_present_cpu(cpu) {
3416 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
edc660fa 3417
213f428f
TP		 3418 hrtimer_cancel(&port_pcpu->tx_done_timer);
3419 port_pcpu->timer_scheduled = false;
3420 tasklet_kill(&port_pcpu->tx_done_tasklet);
3421 }
edc660fa 3422 }
3f518509
MW		 3423 mvpp2_cleanup_rxqs(port);
3424 mvpp2_cleanup_txqs(port);
3425
e5c500eb 3426 cancel_delayed_work_sync(&port->stats_work);
118d6298 3427
3f518509
MW		 3428 return 0;
3429}
3430
10fea26c
MC		 3431static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3432 struct netdev_hw_addr_list *list)
3f518509 3433{
3f518509 3434 struct netdev_hw_addr *ha;
10fea26c
MC		 3435 int ret;
3436
3437 netdev_hw_addr_list_for_each(ha, list) {
3438 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3439 if (ret)
3440 return ret;
3f518509 3441 }
56beda3d 3442
10fea26c
MC		 3443 return 0;
3444}
3445
3446static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3447{
3448 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
56beda3d 3449 mvpp2_prs_vid_enable_filtering(port);
10fea26c
MC		 3450 else
3451 mvpp2_prs_vid_disable_filtering(port);
3452
3453 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3454 MVPP2_PRS_L2_UNI_CAST, enable);
3455
3456 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3457 MVPP2_PRS_L2_MULTI_CAST, enable);
3458}
3459
3460static void mvpp2_set_rx_mode(struct net_device *dev)
3461{
3462 struct mvpp2_port *port = netdev_priv(dev);
3463
3464 /* Clear the whole UC and MC list */
3465 mvpp2_prs_mac_del_all(port);
3466
3467 if (dev->flags & IFF_PROMISC) {
3468 mvpp2_set_rx_promisc(port, true);
3469 return;
3470 }
3471
3472 mvpp2_set_rx_promisc(port, false);
3473
3474 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3475 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3476 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3477 MVPP2_PRS_L2_UNI_CAST, true);
3478
3479 if (dev->flags & IFF_ALLMULTI) {
3480 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3481 MVPP2_PRS_L2_MULTI_CAST, true);
3482 return;
3483 }
3484
3485 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3486 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3487 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3488 MVPP2_PRS_L2_MULTI_CAST, true);
3f518509
MW		 3489}
3490
3491static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3492{
3f518509
MW		 3493 const struct sockaddr *addr = p;
3494 int err;
3495
5b0ab2f4
YM		 3496 if (!is_valid_ether_addr(addr->sa_data))
3497 return -EADDRNOTAVAIL;
3f518509
MW		 3498
3499 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5b0ab2f4
YM		 3500 if (err) {
3501 /* Reconfigure parser accept the original MAC address */
3502 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3503 netdev_err(dev, "failed to change MAC address\n");
3504 }
3f518509
MW		 3505 return err;
3506}
3507
3508static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3509{
3510 struct mvpp2_port *port = netdev_priv(dev);
3511 int err;
3512
5777987e
JW		 3513 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3514 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3515 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3516 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3f518509
MW		 3517 }
3518
3519 if (!netif_running(dev)) {
3520 err = mvpp2_bm_update_mtu(dev, mtu);
3521 if (!err) {
3522 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3523 return 0;
3524 }
3525
3526 /* Reconfigure BM to the original MTU */
3527 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3528 if (err)
c1175547 3529 goto log_error;
3f518509
MW		 3530 }
3531
3532 mvpp2_stop_dev(port);
3533
3534 err = mvpp2_bm_update_mtu(dev, mtu);
3535 if (!err) {
3536 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3537 goto out_start;
3538 }
3539
3540 /* Reconfigure BM to the original MTU */
3541 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3542 if (err)
c1175547 3543 goto log_error;
3f518509
MW		 3544
3545out_start:
3546 mvpp2_start_dev(port);
3547 mvpp2_egress_enable(port);
3548 mvpp2_ingress_enable(port);
3549
3550 return 0;
c1175547 3551log_error:
dfd4240a 3552 netdev_err(dev, "failed to change MTU\n");
3f518509
MW		 3553 return err;
3554}
3555
bc1f4470 3556static void
3f518509
MW		 3557mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3558{
3559 struct mvpp2_port *port = netdev_priv(dev);
3560 unsigned int start;
850623b3 3561 unsigned int cpu;
3f518509
MW		 3562
3563 for_each_possible_cpu(cpu) {
3564 struct mvpp2_pcpu_stats *cpu_stats;
3565 u64 rx_packets;
3566 u64 rx_bytes;
3567 u64 tx_packets;
3568 u64 tx_bytes;
3569
3570 cpu_stats = per_cpu_ptr(port->stats, cpu);
3571 do {
3572 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3573 rx_packets = cpu_stats->rx_packets;
3574 rx_bytes = cpu_stats->rx_bytes;
3575 tx_packets = cpu_stats->tx_packets;
3576 tx_bytes = cpu_stats->tx_bytes;
3577 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3578
3579 stats->rx_packets += rx_packets;
3580 stats->rx_bytes += rx_bytes;
3581 stats->tx_packets += tx_packets;
3582 stats->tx_bytes += tx_bytes;
3583 }
3584
3585 stats->rx_errors = dev->stats.rx_errors;
3586 stats->rx_dropped = dev->stats.rx_dropped;
3587 stats->tx_dropped = dev->stats.tx_dropped;
3f518509
MW		 3588}
3589
bd695a5f
TP		 3590static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3591{
4bb04326 3592 struct mvpp2_port *port = netdev_priv(dev);
bd695a5f 3593
4bb04326 3594 if (!port->phylink)
bd695a5f
TP		 3595 return -ENOTSUPP;
3596
4bb04326 3597 return phylink_mii_ioctl(port->phylink, ifr, cmd);
bd695a5f
TP		 3598}
3599
56beda3d
MC		 3600static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3601{
3602 struct mvpp2_port *port = netdev_priv(dev);
3603 int ret;
3604
3605 ret = mvpp2_prs_vid_entry_add(port, vid);
3606 if (ret)
3607 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3608 MVPP2_PRS_VLAN_FILT_MAX - 1);
3609 return ret;
3610}
3611
3612static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3613{
3614 struct mvpp2_port *port = netdev_priv(dev);
3615
3616 mvpp2_prs_vid_entry_remove(port, vid);
3617 return 0;
3618}
3619
3620static int mvpp2_set_features(struct net_device *dev,
3621 netdev_features_t features)
3622{
3623 netdev_features_t changed = dev->features ^ features;
3624 struct mvpp2_port *port = netdev_priv(dev);
3625
3626 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3627 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3628 mvpp2_prs_vid_enable_filtering(port);
3629 } else {
3630 /* Invalidate all registered VID filters for this
3631 * port
3632 */
3633 mvpp2_prs_vid_remove_all(port);
3634
3635 mvpp2_prs_vid_disable_filtering(port);
3636 }
3637 }
3638
d33ec452
MC		 3639 if (changed & NETIF_F_RXHASH) {
3640 if (features & NETIF_F_RXHASH)
3641 mvpp22_rss_enable(port);
3642 else
3643 mvpp22_rss_disable(port);
3644 }
3645
56beda3d
MC		 3646 return 0;
3647}
3648
3f518509
MW		 3649/* Ethtool methods */
3650
4bb04326
AT		 3651static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3652{
3653 struct mvpp2_port *port = netdev_priv(dev);
3654
3655 if (!port->phylink)
3656 return -ENOTSUPP;
3657
3658 return phylink_ethtool_nway_reset(port->phylink);
3659}
3660
3f518509
MW		 3661/* Set interrupt coalescing for ethtools */
3662static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3663 struct ethtool_coalesce *c)
3664{
3665 struct mvpp2_port *port = netdev_priv(dev);
3666 int queue;
3667
09f83975 3668 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 3669 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3670
3671 rxq->time_coal = c->rx_coalesce_usecs;
3672 rxq->pkts_coal = c->rx_max_coalesced_frames;
d63f9e41
TP		 3673 mvpp2_rx_pkts_coal_set(port, rxq);
3674 mvpp2_rx_time_coal_set(port, rxq);
3f518509
MW		 3675 }
3676
213f428f
TP		 3677 if (port->has_tx_irqs) {
3678 port->tx_time_coal = c->tx_coalesce_usecs;
3679 mvpp2_tx_time_coal_set(port);
3680 }
3681
09f83975 3682 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 3683 struct mvpp2_tx_queue *txq = port->txqs[queue];
3684
3685 txq->done_pkts_coal = c->tx_max_coalesced_frames;
213f428f
TP		 3686
3687 if (port->has_tx_irqs)
3688 mvpp2_tx_pkts_coal_set(port, txq);
3f518509
MW		 3689 }
3690
3f518509
MW		 3691 return 0;
3692}
3693
3694/* get coalescing for ethtools */
3695static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3696 struct ethtool_coalesce *c)
3697{
3698 struct mvpp2_port *port = netdev_priv(dev);
3699
385c284f
AT		 3700 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
3701 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3702 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
24b28ccb 3703 c->tx_coalesce_usecs = port->tx_time_coal;
3f518509
MW		 3704 return 0;
3705}
3706
3707static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3708 struct ethtool_drvinfo *drvinfo)
3709{
3710 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3711 sizeof(drvinfo->driver));
3712 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3713 sizeof(drvinfo->version));
3714 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3715 sizeof(drvinfo->bus_info));
3716}
3717
3718static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3719 struct ethtool_ringparam *ring)
3720{
3721 struct mvpp2_port *port = netdev_priv(dev);
3722
7cf87e4a
YM		 3723 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3724 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3f518509
MW		 3725 ring->rx_pending = port->rx_ring_size;
3726 ring->tx_pending = port->tx_ring_size;
3727}
3728
3729static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3730 struct ethtool_ringparam *ring)
3731{
3732 struct mvpp2_port *port = netdev_priv(dev);
3733 u16 prev_rx_ring_size = port->rx_ring_size;
3734 u16 prev_tx_ring_size = port->tx_ring_size;
3735 int err;
3736
3737 err = mvpp2_check_ringparam_valid(dev, ring);
3738 if (err)
3739 return err;
3740
3741 if (!netif_running(dev)) {
3742 port->rx_ring_size = ring->rx_pending;
3743 port->tx_ring_size = ring->tx_pending;
3744 return 0;
3745 }
3746
3747 /* The interface is running, so we have to force a
3748 * reallocation of the queues
3749 */
3750 mvpp2_stop_dev(port);
3751 mvpp2_cleanup_rxqs(port);
3752 mvpp2_cleanup_txqs(port);
3753
3754 port->rx_ring_size = ring->rx_pending;
3755 port->tx_ring_size = ring->tx_pending;
3756
3757 err = mvpp2_setup_rxqs(port);
3758 if (err) {
3759 /* Reallocate Rx queues with the original ring size */
3760 port->rx_ring_size = prev_rx_ring_size;
3761 ring->rx_pending = prev_rx_ring_size;
3762 err = mvpp2_setup_rxqs(port);
3763 if (err)
3764 goto err_out;
3765 }
3766 err = mvpp2_setup_txqs(port);
3767 if (err) {
3768 /* Reallocate Tx queues with the original ring size */
3769 port->tx_ring_size = prev_tx_ring_size;
3770 ring->tx_pending = prev_tx_ring_size;
3771 err = mvpp2_setup_txqs(port);
3772 if (err)
3773 goto err_clean_rxqs;
3774 }
3775
3776 mvpp2_start_dev(port);
3777 mvpp2_egress_enable(port);
3778 mvpp2_ingress_enable(port);
3779
3780 return 0;
3781
3782err_clean_rxqs:
3783 mvpp2_cleanup_rxqs(port);
3784err_out:
dfd4240a 3785 netdev_err(dev, "failed to change ring parameters");
3f518509
MW		 3786 return err;
3787}
3788
4bb04326
AT		 3789static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3790 struct ethtool_pauseparam *pause)
3791{
3792 struct mvpp2_port *port = netdev_priv(dev);
3793
3794 if (!port->phylink)
3795 return;
3796
3797 phylink_ethtool_get_pauseparam(port->phylink, pause);
3798}
3799
3800static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3801 struct ethtool_pauseparam *pause)
3802{
3803 struct mvpp2_port *port = netdev_priv(dev);
3804
3805 if (!port->phylink)
3806 return -ENOTSUPP;
3807
3808 return phylink_ethtool_set_pauseparam(port->phylink, pause);
3809}
3810
3811static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
3812 struct ethtool_link_ksettings *cmd)
3813{
3814 struct mvpp2_port *port = netdev_priv(dev);
3815
3816 if (!port->phylink)
3817 return -ENOTSUPP;
3818
3819 return phylink_ethtool_ksettings_get(port->phylink, cmd);
3820}
3821
3822static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
3823 const struct ethtool_link_ksettings *cmd)
3824{
3825 struct mvpp2_port *port = netdev_priv(dev);
3826
3827 if (!port->phylink)
3828 return -ENOTSUPP;
3829
3830 return phylink_ethtool_ksettings_set(port->phylink, cmd);
3831}
3832
8179642b
AT		 3833static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
3834 struct ethtool_rxnfc *info, u32 *rules)
3835{
3836 struct mvpp2_port *port = netdev_priv(dev);
436d4fdb 3837 int ret = 0;
8179642b
AT		 3838
3839 if (!mvpp22_rss_is_supported())
3840 return -EOPNOTSUPP;
3841
3842 switch (info->cmd) {
436d4fdb
MC		 3843 case ETHTOOL_GRXFH:
3844 ret = mvpp2_ethtool_rxfh_get(port, info);
3845 break;
8179642b
AT		 3846 case ETHTOOL_GRXRINGS:
3847 info->data = port->nrxqs;
3848 break;
3849 default:
3850 return -ENOTSUPP;
3851 }
3852
436d4fdb
MC		 3853 return ret;
3854}
3855
3856static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
3857 struct ethtool_rxnfc *info)
3858{
3859 struct mvpp2_port *port = netdev_priv(dev);
3860 int ret = 0;
3861
3862 if (!mvpp22_rss_is_supported())
3863 return -EOPNOTSUPP;
3864
3865 switch (info->cmd) {
3866 case ETHTOOL_SRXFH:
3867 ret = mvpp2_ethtool_rxfh_set(port, info);
3868 break;
3869 default:
3870 return -EOPNOTSUPP;
3871 }
3872 return ret;
8179642b
AT		 3873}
3874
3875static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
3876{
3877 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
3878}
3879
3880static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3881 u8 *hfunc)
3882{
3883 struct mvpp2_port *port = netdev_priv(dev);
3884
3885 if (!mvpp22_rss_is_supported())
3886 return -EOPNOTSUPP;
3887
3888 if (indir)
3889 memcpy(indir, port->indir,
3890 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3891
3892 if (hfunc)
3893 *hfunc = ETH_RSS_HASH_CRC32;
3894
3895 return 0;
3896}
3897
3898static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3899 const u8 *key, const u8 hfunc)
3900{
3901 struct mvpp2_port *port = netdev_priv(dev);
3902
3903 if (!mvpp22_rss_is_supported())
3904 return -EOPNOTSUPP;
3905
3906 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
3907 return -EOPNOTSUPP;
3908
3909 if (key)
3910 return -EOPNOTSUPP;
3911
3912 if (indir) {
3913 memcpy(port->indir, indir,
3914 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3915 mvpp22_rss_fill_table(port, port->id);
3916 }
3917
3918 return 0;
3919}
3920
3f518509
MW		 3921/* Device ops */
3922
3923static const struct net_device_ops mvpp2_netdev_ops = {
3924 .ndo_open = mvpp2_open,
3925 .ndo_stop = mvpp2_stop,
3926 .ndo_start_xmit = mvpp2_tx,
3927 .ndo_set_rx_mode = mvpp2_set_rx_mode,
3928 .ndo_set_mac_address = mvpp2_set_mac_address,
3929 .ndo_change_mtu = mvpp2_change_mtu,
3930 .ndo_get_stats64 = mvpp2_get_stats64,
bd695a5f 3931 .ndo_do_ioctl = mvpp2_ioctl,
56beda3d
MC		 3932 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
3933 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
3934 .ndo_set_features = mvpp2_set_features,
3f518509
MW		 3935};
3936
3937static const struct ethtool_ops mvpp2_eth_tool_ops = {
4bb04326 3938 .nway_reset = mvpp2_ethtool_nway_reset,
dcd3e73a
AT		 3939 .get_link = ethtool_op_get_link,
3940 .set_coalesce = mvpp2_ethtool_set_coalesce,
3941 .get_coalesce = mvpp2_ethtool_get_coalesce,
3942 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
3943 .get_ringparam = mvpp2_ethtool_get_ringparam,
3944 .set_ringparam = mvpp2_ethtool_set_ringparam,
3945 .get_strings = mvpp2_ethtool_get_strings,
3946 .get_ethtool_stats = mvpp2_ethtool_get_stats,
3947 .get_sset_count = mvpp2_ethtool_get_sset_count,
4bb04326
AT		 3948 .get_pauseparam = mvpp2_ethtool_get_pause_param,
3949 .set_pauseparam = mvpp2_ethtool_set_pause_param,
3950 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
3951 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
8179642b 3952 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
436d4fdb 3953 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
8179642b
AT		 3954 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
3955 .get_rxfh = mvpp2_ethtool_get_rxfh,
3956 .set_rxfh = mvpp2_ethtool_set_rxfh,
3957
3f518509
MW		 3958};
3959
213f428f
TP		 3960/* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
3961 * had a single IRQ defined per-port.
3962 */
3963static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
3964 struct device_node *port_node)
591f4cfa
TP		 3965{
3966 struct mvpp2_queue_vector *v = &port->qvecs[0];
3967
3968 v->first_rxq = 0;
3969 v->nrxqs = port->nrxqs;
3970 v->type = MVPP2_QUEUE_VECTOR_SHARED;
3971 v->sw_thread_id = 0;
3972 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
3973 v->port = port;
3974 v->irq = irq_of_parse_and_map(port_node, 0);
3975 if (v->irq <= 0)
3976 return -EINVAL;
3977 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
3978 NAPI_POLL_WEIGHT);
3979
3980 port->nqvecs = 1;
3981
3982 return 0;
3983}
3984
213f428f
TP		 3985static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
3986 struct device_node *port_node)
3987{
3988 struct mvpp2_queue_vector *v;
3989 int i, ret;
3990
3991 port->nqvecs = num_possible_cpus();
3992 if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
3993 port->nqvecs += 1;
3994
3995 for (i = 0; i < port->nqvecs; i++) {
3996 char irqname[16];
3997
3998 v = port->qvecs + i;
3999
4000 v->port = port;
4001 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4002 v->sw_thread_id = i;
4003 v->sw_thread_mask = BIT(i);
4004
a9aac385
AT		 4005 if (port->flags & MVPP2_F_DT_COMPAT)
4006 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4007 else
4008 snprintf(irqname, sizeof(irqname), "hif%d", i);
213f428f
TP		 4009
4010 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
4011 v->first_rxq = i * MVPP2_DEFAULT_RXQ;
4012 v->nrxqs = MVPP2_DEFAULT_RXQ;
4013 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4014 i == (port->nqvecs - 1)) {
4015 v->first_rxq = 0;
4016 v->nrxqs = port->nrxqs;
4017 v->type = MVPP2_QUEUE_VECTOR_SHARED;
a9aac385
AT		 4018
4019 if (port->flags & MVPP2_F_DT_COMPAT)
4020 strncpy(irqname, "rx-shared", sizeof(irqname));
213f428f
TP		 4021 }
4022
a75edc7c
MW		 4023 if (port_node)
4024 v->irq = of_irq_get_byname(port_node, irqname);
4025 else
4026 v->irq = fwnode_irq_get(port->fwnode, i);
213f428f
TP		 4027 if (v->irq <= 0) {
4028 ret = -EINVAL;
4029 goto err;
4030 }
4031
4032 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4033 NAPI_POLL_WEIGHT);
4034 }
4035
4036 return 0;
4037
4038err:
4039 for (i = 0; i < port->nqvecs; i++)
4040 irq_dispose_mapping(port->qvecs[i].irq);
4041 return ret;
4042}
4043
4044static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4045 struct device_node *port_node)
4046{
4047 if (port->has_tx_irqs)
4048 return mvpp2_multi_queue_vectors_init(port, port_node);
4049 else
4050 return mvpp2_simple_queue_vectors_init(port, port_node);
4051}
4052
591f4cfa
TP		 4053static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4054{
4055 int i;
4056
4057 for (i = 0; i < port->nqvecs; i++)
4058 irq_dispose_mapping(port->qvecs[i].irq);
4059}
4060
4061/* Configure Rx queue group interrupt for this port */
4062static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4063{
4064 struct mvpp2 *priv = port->priv;
4065 u32 val;
4066 int i;
4067
4068 if (priv->hw_version == MVPP21) {
4069 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4070 port->nrxqs);
4071 return;
4072 }
4073
4074 /* Handle the more complicated PPv2.2 case */
4075 for (i = 0; i < port->nqvecs; i++) {
4076 struct mvpp2_queue_vector *qv = port->qvecs + i;
4077
4078 if (!qv->nrxqs)
4079 continue;
4080
4081 val = qv->sw_thread_id;
4082 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4083 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4084
4085 val = qv->first_rxq;
4086 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4087 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4088 }
4089}
4090
3f518509
MW		 4091/* Initialize port HW */
4092static int mvpp2_port_init(struct mvpp2_port *port)
4093{
4094 struct device *dev = port->dev->dev.parent;
4095 struct mvpp2 *priv = port->priv;
4096 struct mvpp2_txq_pcpu *txq_pcpu;
850623b3
AT		 4097 unsigned int cpu;
4098 int queue, err;
3f518509 4099
09f83975
TP		 4100 /* Checks for hardware constraints */
4101 if (port->first_rxq + port->nrxqs >
59b9a31e 4102 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3f518509
MW		 4103 return -EINVAL;
4104
790d32c6
MC		 4105 if (port->nrxqs % MVPP2_DEFAULT_RXQ ||
4106 port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
09f83975
TP		 4107 return -EINVAL;
4108
3f518509
MW		 4109 /* Disable port */
4110 mvpp2_egress_disable(port);
4111 mvpp2_port_disable(port);
4112
213f428f
TP		 4113 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4114
09f83975 4115 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
3f518509
MW		 4116 GFP_KERNEL);
4117 if (!port->txqs)
4118 return -ENOMEM;
4119
4120 /* Associate physical Tx queues to this port and initialize.
4121 * The mapping is predefined.
4122 */
09f83975 4123 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4124 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4125 struct mvpp2_tx_queue *txq;
4126
4127 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
177c8d1c
CJ		 4128 if (!txq) {
4129 err = -ENOMEM;
4130 goto err_free_percpu;
4131 }
3f518509
MW		 4132
4133 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4134 if (!txq->pcpu) {
4135 err = -ENOMEM;
4136 goto err_free_percpu;
4137 }
4138
4139 txq->id = queue_phy_id;
4140 txq->log_id = queue;
4141 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4142 for_each_present_cpu(cpu) {
4143 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4144 txq_pcpu->cpu = cpu;
4145 }
4146
4147 port->txqs[queue] = txq;
4148 }
4149
09f83975 4150 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
3f518509
MW		 4151 GFP_KERNEL);
4152 if (!port->rxqs) {
4153 err = -ENOMEM;
4154 goto err_free_percpu;
4155 }
4156
4157 /* Allocate and initialize Rx queue for this port */
09f83975 4158 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4159 struct mvpp2_rx_queue *rxq;
4160
4161 /* Map physical Rx queue to port's logical Rx queue */
4162 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
d82b0c21
JZ		 4163 if (!rxq) {
4164 err = -ENOMEM;
3f518509 4165 goto err_free_percpu;
d82b0c21 4166 }
3f518509
MW		 4167 /* Map this Rx queue to a physical queue */
4168 rxq->id = port->first_rxq + queue;
4169 rxq->port = port->id;
4170 rxq->logic_rxq = queue;
4171
4172 port->rxqs[queue] = rxq;
4173 }
4174
591f4cfa 4175 mvpp2_rx_irqs_setup(port);
3f518509
MW		 4176
4177 /* Create Rx descriptor rings */
09f83975 4178 for (queue = 0; queue < port->nrxqs; queue++) {
3f518509
MW		 4179 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4180
4181 rxq->size = port->rx_ring_size;
4182 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4183 rxq->time_coal = MVPP2_RX_COAL_USEC;
4184 }
4185
4186 mvpp2_ingress_disable(port);
4187
4188 /* Port default configuration */
4189 mvpp2_defaults_set(port);
4190
4191 /* Port's classifier configuration */
4192 mvpp2_cls_oversize_rxq_set(port);
4193 mvpp2_cls_port_config(port);
4194
e6e21c02
MC		 4195 if (mvpp22_rss_is_supported())
4196 mvpp22_rss_port_init(port);
4197
3f518509
MW		 4198 /* Provide an initial Rx packet size */
4199 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4200
4201 /* Initialize pools for swf */
4202 err = mvpp2_swf_bm_pool_init(port);
4203 if (err)
4204 goto err_free_percpu;
4205
4206 return 0;
4207
4208err_free_percpu:
09f83975 4209 for (queue = 0; queue < port->ntxqs; queue++) {
3f518509
MW		 4210 if (!port->txqs[queue])
4211 continue;
4212 free_percpu(port->txqs[queue]->pcpu);
4213 }
4214 return err;
4215}
4216
a9aac385
AT		 4217static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
4218 unsigned long *flags)
4219{
4220 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
4221 "tx-cpu3" };
4222 int i;
4223
4224 for (i = 0; i < 5; i++)
4225 if (of_property_match_string(port_node, "interrupt-names",
4226 irqs[i]) < 0)
4227 return false;
4228
4229 *flags |= MVPP2_F_DT_COMPAT;
4230 return true;
4231}
4232
4233/* Checks if the port dt description has the required Tx interrupts:
4234 * - PPv2.1: there are no such interrupts.
4235 * - PPv2.2:
4236 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
4237 * - The new ones have: "hifX" with X in [0..8]
4238 *
4239 * All those variants are supported to keep the backward compatibility.
213f428f 4240 */
a9aac385
AT		 4241static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
4242 struct device_node *port_node,
4243 unsigned long *flags)
213f428f 4244{
a9aac385
AT		 4245 char name[5];
4246 int i;
213f428f 4247
fd4a1056
AT		 4248 /* ACPI */
4249 if (!port_node)
4250 return true;
4251
213f428f
TP		 4252 if (priv->hw_version == MVPP21)
4253 return false;
4254
a9aac385
AT		 4255 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
4256 return true;
4257
4258 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
4259 snprintf(name, 5, "hif%d", i);
4260 if (of_property_match_string(port_node, "interrupt-names",
4261 name) < 0)
213f428f
TP		 4262 return false;
4263 }
4264
4265 return true;
4266}
4267
3ba8c81e 4268static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
24812221 4269 struct fwnode_handle *fwnode,
3ba8c81e
AT		 4270 char **mac_from)
4271{
4272 struct mvpp2_port *port = netdev_priv(dev);
4273 char hw_mac_addr[ETH_ALEN] = {0};
24812221 4274 char fw_mac_addr[ETH_ALEN];
3ba8c81e 4275
24812221
MW		 4276 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4277 *mac_from = "firmware node";
4278 ether_addr_copy(dev->dev_addr, fw_mac_addr);
688cbaf2
AT		 4279 return;
4280 }
d2a6e48e 4281
688cbaf2
AT		 4282 if (priv->hw_version == MVPP21) {
4283 mvpp21_get_mac_address(port, hw_mac_addr);
4284 if (is_valid_ether_addr(hw_mac_addr)) {
4285 *mac_from = "hardware";
4286 ether_addr_copy(dev->dev_addr, hw_mac_addr);
4287 return;
4288 }
3ba8c81e 4289 }
688cbaf2
AT		 4290
4291 *mac_from = "random";
4292 eth_hw_addr_random(dev);
3ba8c81e
AT		 4293}
4294
4bb04326
AT		 4295static void mvpp2_phylink_validate(struct net_device *dev,
4296 unsigned long *supported,
4297 struct phylink_link_state *state)
4298{
4299 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4300
4301 phylink_set(mask, Autoneg);
4302 phylink_set_port_modes(mask);
4303 phylink_set(mask, Pause);
4304 phylink_set(mask, Asym_Pause);
4305
d97c9f4a
AT		 4306 switch (state->interface) {
4307 case PHY_INTERFACE_MODE_10GKR:
4bb04326
AT		 4308 phylink_set(mask, 10000baseCR_Full);
4309 phylink_set(mask, 10000baseSR_Full);
4310 phylink_set(mask, 10000baseLR_Full);
4311 phylink_set(mask, 10000baseLRM_Full);
4312 phylink_set(mask, 10000baseER_Full);
4313 phylink_set(mask, 10000baseKR_Full);
d97c9f4a
AT		 4314 /* Fall-through */
4315 default:
4316 phylink_set(mask, 10baseT_Half);
4317 phylink_set(mask, 10baseT_Full);
4318 phylink_set(mask, 100baseT_Half);
4319 phylink_set(mask, 100baseT_Full);
4320 phylink_set(mask, 10000baseT_Full);
4321 /* Fall-through */
4322 case PHY_INTERFACE_MODE_1000BASEX:
a6fe31de 4323 case PHY_INTERFACE_MODE_2500BASEX:
d97c9f4a
AT		 4324 phylink_set(mask, 1000baseT_Full);
4325 phylink_set(mask, 1000baseX_Full);
a6fe31de 4326 phylink_set(mask, 2500baseX_Full);
4bb04326
AT		 4327 }
4328
4329 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4330 bitmap_and(state->advertising, state->advertising, mask,
4331 __ETHTOOL_LINK_MODE_MASK_NBITS);
4332}
4333
4334static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4335 struct phylink_link_state *state)
4336{
4337 u32 val;
4338
4339 state->speed = SPEED_10000;
4340 state->duplex = 1;
4341 state->an_complete = 1;
4342
4343 val = readl(port->base + MVPP22_XLG_STATUS);
4344 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4345
4346 state->pause = 0;
4347 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4348 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4349 state->pause |= MLO_PAUSE_TX;
4350 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4351 state->pause |= MLO_PAUSE_RX;
4352}
4353
4354static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4355 struct phylink_link_state *state)
4356{
4357 u32 val;
4358
4359 val = readl(port->base + MVPP2_GMAC_STATUS0);
4360
4361 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4362 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4363 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4364
d97c9f4a
AT		 4365 switch (port->phy_interface) {
4366 case PHY_INTERFACE_MODE_1000BASEX:
4bb04326 4367 state->speed = SPEED_1000;
d97c9f4a 4368 break;
a6fe31de
AT		 4369 case PHY_INTERFACE_MODE_2500BASEX:
4370 state->speed = SPEED_2500;
4371 break;
d97c9f4a
AT		 4372 default:
4373 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4374 state->speed = SPEED_1000;
4375 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4376 state->speed = SPEED_100;
4377 else
4378 state->speed = SPEED_10;
4379 }
4bb04326
AT		 4380
4381 state->pause = 0;
4382 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4383 state->pause |= MLO_PAUSE_RX;
4384 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4385 state->pause |= MLO_PAUSE_TX;
4386}
4387
4388static int mvpp2_phylink_mac_link_state(struct net_device *dev,
4389 struct phylink_link_state *state)
4390{
4391 struct mvpp2_port *port = netdev_priv(dev);
4392
4393 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4394 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4395 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4396
4397 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4398 mvpp22_xlg_link_state(port, state);
4399 return 1;
4400 }
4401 }
4402
4403 mvpp2_gmac_link_state(port, state);
4404 return 1;
4405}
4406
4407static void mvpp2_mac_an_restart(struct net_device *dev)
4408{
4409 struct mvpp2_port *port = netdev_priv(dev);
4410 u32 val;
4411
4412 if (port->phy_interface != PHY_INTERFACE_MODE_SGMII)
4413 return;
4414
4415 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4416 /* The RESTART_AN bit is cleared by the h/w after restarting the AN
4417 * process.
4418 */
4419 val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG;
4420 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4421}
4422
4423static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4424 const struct phylink_link_state *state)
4425{
4426 u32 ctrl0, ctrl4;
4427
4428 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4429 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4430
4431 if (state->pause & MLO_PAUSE_TX)
4432 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4433 if (state->pause & MLO_PAUSE_RX)
4434 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4435
4436 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
4437 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
4438 MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
4439
4440 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4441 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
4442}
4443
4444static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4445 const struct phylink_link_state *state)
4446{
4447 u32 an, ctrl0, ctrl2, ctrl4;
4448
4449 an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4450 ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4451 ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4452 ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4453
4454 /* Force link down */
4455 an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4456 an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4457 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4458
4459 /* Set the GMAC in a reset state */
4460 ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4461 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4462
4463 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4464 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4465 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4466 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4467 MVPP2_GMAC_FORCE_LINK_DOWN);
4468 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4469 ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
4470
a6fe31de
AT		 4471 if (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4472 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4473 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4474 * they negotiate duplex: they are always operating with a fixed
4475 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4476 * speed and full duplex here.
d97c9f4a
AT		 4477 */
4478 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4479 an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
4480 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4481 } else if (!phy_interface_mode_is_rgmii(state->interface)) {
4bb04326 4482 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
d97c9f4a 4483 }
4bb04326
AT		 4484
4485 if (state->duplex)
4486 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4487 if (phylink_test(state->advertising, Pause))
4488 an |= MVPP2_GMAC_FC_ADV_EN;
4489 if (phylink_test(state->advertising, Asym_Pause))
4490 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4491
d97c9f4a 4492 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 4493 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4494 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4bb04326
AT		 4495 an |= MVPP2_GMAC_IN_BAND_AUTONEG;
4496 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
4497
4498 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4499 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4500 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4501 MVPP22_CTRL4_DP_CLK_SEL |
4502 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4503
4504 if (state->pause & MLO_PAUSE_TX)
4505 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4506 if (state->pause & MLO_PAUSE_RX)
4507 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4508 } else if (phy_interface_mode_is_rgmii(state->interface)) {
4509 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS;
4510
4511 if (state->speed == SPEED_1000)
4512 an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4513 else if (state->speed == SPEED_100)
4514 an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4515
4516 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4517 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4518 MVPP22_CTRL4_SYNC_BYPASS_DIS |
4519 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4520 }
4521
4522 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4523 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4524 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4525 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4526}
4527
4528static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
4529 const struct phylink_link_state *state)
4530{
4531 struct mvpp2_port *port = netdev_priv(dev);
4532
4533 /* Check for invalid configuration */
4534 if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
4535 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4536 return;
4537 }
4538
4bb04326
AT		 4539 /* Make sure the port is disabled when reconfiguring the mode */
4540 mvpp2_port_disable(port);
4541
4542 if (port->priv->hw_version == MVPP22 &&
4543 port->phy_interface != state->interface) {
4544 port->phy_interface = state->interface;
4545
4546 /* Reconfigure the serdes lanes */
4547 phy_power_off(port->comphy);
4548 mvpp22_mode_reconfigure(port);
4549 }
4550
4551 /* mac (re)configuration */
4552 if (state->interface == PHY_INTERFACE_MODE_10GKR)
4553 mvpp2_xlg_config(port, mode, state);
4554 else if (phy_interface_mode_is_rgmii(state->interface) ||
d97c9f4a 4555 state->interface == PHY_INTERFACE_MODE_SGMII ||
a6fe31de
AT		 4556 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4557 state->interface == PHY_INTERFACE_MODE_2500BASEX)
4bb04326
AT		 4558 mvpp2_gmac_config(port, mode, state);
4559
4560 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4561 mvpp2_port_loopback_set(port, state);
4562
41948ccb 4563 mvpp2_port_enable(port);
4bb04326
AT		 4564}
4565
4566static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
4567 phy_interface_t interface, struct phy_device *phy)
4568{
4569 struct mvpp2_port *port = netdev_priv(dev);
4570 u32 val;
4571
4572 if (!phylink_autoneg_inband(mode) &&
4573 interface != PHY_INTERFACE_MODE_10GKR) {
4574 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4575 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4576 if (phy_interface_mode_is_rgmii(interface))
4577 val |= MVPP2_GMAC_FORCE_LINK_PASS;
4578 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4579 }
4580
4581 mvpp2_port_enable(port);
4582
4583 mvpp2_egress_enable(port);
4584 mvpp2_ingress_enable(port);
4585 netif_tx_wake_all_queues(dev);
4586}
4587
4588static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
4589 phy_interface_t interface)
4590{
4591 struct mvpp2_port *port = netdev_priv(dev);
4592 u32 val;
4593
4594 if (!phylink_autoneg_inband(mode) &&
4595 interface != PHY_INTERFACE_MODE_10GKR) {
4596 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4597 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4598 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4599 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4600 }
4601
4602 netif_tx_stop_all_queues(dev);
4603 mvpp2_egress_disable(port);
4604 mvpp2_ingress_disable(port);
4605
4606 /* When using link interrupts to notify phylink of a MAC state change,
4607 * we do not want the port to be disabled (we want to receive further
4608 * interrupts, to be notified when the port will have a link later).
4609 */
4610 if (!port->has_phy)
4611 return;
4612
4613 mvpp2_port_disable(port);
4614}
4615
4616static const struct phylink_mac_ops mvpp2_phylink_ops = {
4617 .validate = mvpp2_phylink_validate,
4618 .mac_link_state = mvpp2_phylink_mac_link_state,
4619 .mac_an_restart = mvpp2_mac_an_restart,
4620 .mac_config = mvpp2_mac_config,
4621 .mac_link_up = mvpp2_mac_link_up,
4622 .mac_link_down = mvpp2_mac_link_down,
4623};
4624
3f518509
MW		 4625/* Ports initialization */
4626static int mvpp2_port_probe(struct platform_device *pdev,
24812221 4627 struct fwnode_handle *port_fwnode,
bf147153 4628 struct mvpp2 *priv)
3f518509 4629{
a75edc7c 4630 struct phy *comphy = NULL;
3f518509 4631 struct mvpp2_port *port;
edc660fa 4632 struct mvpp2_port_pcpu *port_pcpu;
24812221 4633 struct device_node *port_node = to_of_node(port_fwnode);
3f518509
MW		 4634 struct net_device *dev;
4635 struct resource *res;
4bb04326 4636 struct phylink *phylink;
3ba8c81e 4637 char *mac_from = "";
850623b3 4638 unsigned int ntxqs, nrxqs, cpu;
a9aac385 4639 unsigned long flags = 0;
213f428f 4640 bool has_tx_irqs;
3f518509
MW		 4641 u32 id;
4642 int features;
4643 int phy_mode;
850623b3 4644 int err, i;
3f518509 4645
fd4a1056
AT		 4646 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
4647 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
4648 dev_err(&pdev->dev,
4649 "not enough IRQs to support multi queue mode\n");
4650 return -EINVAL;
a75edc7c 4651 }
213f428f 4652
09f83975 4653 ntxqs = MVPP2_MAX_TXQ;
213f428f
TP		 4654 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE)
4655 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus();
4656 else
4657 nrxqs = MVPP2_DEFAULT_RXQ;
09f83975
TP		 4658
4659 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
3f518509
MW		 4660 if (!dev)
4661 return -ENOMEM;
4662
24812221 4663 phy_mode = fwnode_get_phy_mode(port_fwnode);
3f518509
MW		 4664 if (phy_mode < 0) {
4665 dev_err(&pdev->dev, "incorrect phy mode\n");
4666 err = phy_mode;
4667 goto err_free_netdev;
4668 }
4669
a75edc7c
MW		 4670 if (port_node) {
4671 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
4672 if (IS_ERR(comphy)) {
4673 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
4674 err = -EPROBE_DEFER;
4675 goto err_free_netdev;
4676 }
4677 comphy = NULL;
542897d9 4678 }
542897d9
AT		 4679 }
4680
24812221 4681 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
3f518509
MW		 4682 err = -EINVAL;
4683 dev_err(&pdev->dev, "missing port-id value\n");
4684 goto err_free_netdev;
4685 }
4686
7cf87e4a 4687 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
3f518509
MW		 4688 dev->watchdog_timeo = 5 * HZ;
4689 dev->netdev_ops = &mvpp2_netdev_ops;
4690 dev->ethtool_ops = &mvpp2_eth_tool_ops;
4691
4692 port = netdev_priv(dev);
591f4cfa 4693 port->dev = dev;
a75edc7c 4694 port->fwnode = port_fwnode;
4bb04326 4695 port->has_phy = !!of_find_property(port_node, "phy", NULL);
09f83975
TP		 4696 port->ntxqs = ntxqs;
4697 port->nrxqs = nrxqs;
213f428f
TP		 4698 port->priv = priv;
4699 port->has_tx_irqs = has_tx_irqs;
a9aac385 4700 port->flags = flags;
3f518509 4701
591f4cfa
TP		 4702 err = mvpp2_queue_vectors_init(port, port_node);
4703 if (err)
3f518509 4704 goto err_free_netdev;
3f518509 4705
a75edc7c
MW		 4706 if (port_node)
4707 port->link_irq = of_irq_get_byname(port_node, "link");
4708 else
4709 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
fd3651b2
AT		 4710 if (port->link_irq == -EPROBE_DEFER) {
4711 err = -EPROBE_DEFER;
4712 goto err_deinit_qvecs;
4713 }
4714 if (port->link_irq <= 0)
4715 /* the link irq is optional */
4716 port->link_irq = 0;
4717
24812221 4718 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
3f518509
MW		 4719 port->flags |= MVPP2_F_LOOPBACK;
4720
3f518509 4721 port->id = id;
59b9a31e 4722 if (priv->hw_version == MVPP21)
09f83975 4723 port->first_rxq = port->id * port->nrxqs;
59b9a31e
TP		 4724 else
4725 port->first_rxq = port->id * priv->max_port_rxqs;
4726
4bb04326 4727 port->of_node = port_node;
3f518509 4728 port->phy_interface = phy_mode;
542897d9 4729 port->comphy = comphy;
3f518509 4730
a786841d
TP		 4731 if (priv->hw_version == MVPP21) {
4732 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
4733 port->base = devm_ioremap_resource(&pdev->dev, res);
4734 if (IS_ERR(port->base)) {
4735 err = PTR_ERR(port->base);
fd3651b2 4736 goto err_free_irq;
a786841d 4737 }
118d6298
MR		 4738
4739 port->stats_base = port->priv->lms_base +
4740 MVPP21_MIB_COUNTERS_OFFSET +
4741 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
a786841d 4742 } else {
24812221
MW		 4743 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
4744 &port->gop_id)) {
a786841d
TP		 4745 err = -EINVAL;
4746 dev_err(&pdev->dev, "missing gop-port-id value\n");
591f4cfa 4747 goto err_deinit_qvecs;
a786841d
TP		 4748 }
4749
4750 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
118d6298
MR		 4751 port->stats_base = port->priv->iface_base +
4752 MVPP22_MIB_COUNTERS_OFFSET +
4753 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
3f518509
MW		 4754 }
4755
118d6298 4756 /* Alloc per-cpu and ethtool stats */
3f518509
MW		 4757 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
4758 if (!port->stats) {
4759 err = -ENOMEM;
fd3651b2 4760 goto err_free_irq;
3f518509
MW		 4761 }
4762
118d6298
MR		 4763 port->ethtool_stats = devm_kcalloc(&pdev->dev,
4764 ARRAY_SIZE(mvpp2_ethtool_regs),
4765 sizeof(u64), GFP_KERNEL);
4766 if (!port->ethtool_stats) {
4767 err = -ENOMEM;
4768 goto err_free_stats;
4769 }
4770
e5c500eb
MR		 4771 mutex_init(&port->gather_stats_lock);
4772 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
4773
24812221 4774 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
3f518509 4775
7cf87e4a
YM		 4776 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
4777 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
3f518509
MW		 4778 SET_NETDEV_DEV(dev, &pdev->dev);
4779
4780 err = mvpp2_port_init(port);
4781 if (err < 0) {
4782 dev_err(&pdev->dev, "failed to init port %d\n", id);
4783 goto err_free_stats;
4784 }
26975821 4785
26975821
TP		 4786 mvpp2_port_periodic_xon_disable(port);
4787
26975821 4788 mvpp2_port_reset(port);
3f518509 4789
edc660fa
MW		 4790 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
4791 if (!port->pcpu) {
4792 err = -ENOMEM;
4793 goto err_free_txq_pcpu;
4794 }
4795
213f428f
TP		 4796 if (!port->has_tx_irqs) {
4797 for_each_present_cpu(cpu) {
4798 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
edc660fa 4799
213f428f
TP		 4800 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
4801 HRTIMER_MODE_REL_PINNED);
4802 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
4803 port_pcpu->timer_scheduled = false;
edc660fa 4804
213f428f
TP		 4805 tasklet_init(&port_pcpu->tx_done_tasklet,
4806 mvpp2_tx_proc_cb,
4807 (unsigned long)dev);
4808 }
edc660fa
MW		 4809 }
4810
381c5671
AT		 4811 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4812 NETIF_F_TSO;
3f518509 4813 dev->features = features | NETIF_F_RXCSUM;
56beda3d
MC		 4814 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
4815 NETIF_F_HW_VLAN_CTAG_FILTER;
576193f2 4816
d33ec452
MC		 4817 if (mvpp22_rss_is_supported())
4818 dev->hw_features |= NETIF_F_RXHASH;
4819
576193f2
SC		 4820 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) {
4821 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4822 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4823 }
4824
3f518509 4825 dev->vlan_features |= features;
1d17db08 4826 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
10fea26c 4827 dev->priv_flags |= IFF_UNICAST_FLT;
3f518509 4828
576193f2 4829 /* MTU range: 68 - 9704 */
5777987e 4830 dev->min_mtu = ETH_MIN_MTU;
576193f2
SC		 4831 /* 9704 == 9728 - 20 and rounding to 8 */
4832 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
c4053ef3 4833 dev->dev.of_node = port_node;
5777987e 4834
4bb04326
AT		 4835 /* Phylink isn't used w/ ACPI as of now */
4836 if (port_node) {
4837 phylink = phylink_create(dev, port_fwnode, phy_mode,
4838 &mvpp2_phylink_ops);
4839 if (IS_ERR(phylink)) {
4840 err = PTR_ERR(phylink);
4841 goto err_free_port_pcpu;
4842 }
4843 port->phylink = phylink;
4844 } else {
4845 port->phylink = NULL;
4846 }
4847
3f518509
MW		 4848 err = register_netdev(dev);
4849 if (err < 0) {
4850 dev_err(&pdev->dev, "failed to register netdev\n");
4bb04326 4851 goto err_phylink;
3f518509
MW		 4852 }
4853 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
4854
bf147153
MW		 4855 priv->port_list[priv->port_count++] = port;
4856
3f518509
MW		 4857 return 0;
4858
4bb04326
AT		 4859err_phylink:
4860 if (port->phylink)
4861 phylink_destroy(port->phylink);
edc660fa
MW		 4862err_free_port_pcpu:
4863 free_percpu(port->pcpu);
3f518509 4864err_free_txq_pcpu:
09f83975 4865 for (i = 0; i < port->ntxqs; i++)
3f518509
MW		 4866 free_percpu(port->txqs[i]->pcpu);
4867err_free_stats:
4868 free_percpu(port->stats);
fd3651b2
AT		 4869err_free_irq:
4870 if (port->link_irq)
4871 irq_dispose_mapping(port->link_irq);
591f4cfa
TP		 4872err_deinit_qvecs:
4873 mvpp2_queue_vectors_deinit(port);
3f518509
MW		 4874err_free_netdev:
4875 free_netdev(dev);
4876 return err;
4877}
4878
4879/* Ports removal routine */
4880static void mvpp2_port_remove(struct mvpp2_port *port)
4881{
4882 int i;
4883
4884 unregister_netdev(port->dev);
4bb04326
AT		 4885 if (port->phylink)
4886 phylink_destroy(port->phylink);
edc660fa 4887 free_percpu(port->pcpu);
3f518509 4888 free_percpu(port->stats);
09f83975 4889 for (i = 0; i < port->ntxqs; i++)
3f518509 4890 free_percpu(port->txqs[i]->pcpu);
591f4cfa 4891 mvpp2_queue_vectors_deinit(port);
fd3651b2
AT		 4892 if (port->link_irq)
4893 irq_dispose_mapping(port->link_irq);
3f518509
MW		 4894 free_netdev(port->dev);
4895}
4896
4897/* Initialize decoding windows */
4898static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4899 struct mvpp2 *priv)
4900{
4901 u32 win_enable;
4902 int i;
4903
4904 for (i = 0; i < 6; i++) {
4905 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4906 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4907
4908 if (i < 4)
4909 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4910 }
4911
4912 win_enable = 0;
4913
4914 for (i = 0; i < dram->num_cs; i++) {
4915 const struct mbus_dram_window *cs = dram->cs + i;
4916
4917 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4918 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4919 dram->mbus_dram_target_id);
4920
4921 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4922 (cs->size - 1) & 0xffff0000);
4923
4924 win_enable |= (1 << i);
4925 }
4926
4927 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4928}
4929
4930/* Initialize Rx FIFO's */
4931static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4932{
4933 int port;
4934
4935 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4936 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
2d1d7df8 4937 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
3f518509 4938 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
2d1d7df8
AT		 4939 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
4940 }
4941
4942 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4943 MVPP2_RX_FIFO_PORT_MIN_PKT);
4944 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4945}
4946
4947static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
4948{
4949 int port;
4950
4951 /* The FIFO size parameters are set depending on the maximum speed a
4952 * given port can handle:
4953 * - Port 0: 10Gbps
4954 * - Port 1: 2.5Gbps
4955 * - Ports 2 and 3: 1Gbps
4956 */
4957
4958 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
4959 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
4960 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
4961 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
4962
4963 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
4964 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
4965 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
4966 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
4967
4968 for (port = 2; port < MVPP2_MAX_PORTS; port++) {
4969 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4970 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
4971 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4972 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
3f518509
MW		 4973 }
4974
4975 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4976 MVPP2_RX_FIFO_PORT_MIN_PKT);
4977 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4978}
4979
93ff130f
YM		 4980/* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
4981 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
4982 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
4983 */
7c10f974
AT		 4984static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
4985{
93ff130f 4986 int port, size, thrs;
7c10f974 4987
93ff130f
YM		 4988 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4989 if (port == 0) {
4990 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
4991 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
4992 } else {
4993 size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
4994 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
4995 }
4996 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
4997 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
4998 }
7c10f974
AT		 4999}
5000
6763ce31
TP		 5001static void mvpp2_axi_init(struct mvpp2 *priv)
5002{
5003 u32 val, rdval, wrval;
5004
5005 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
5006
5007 /* AXI Bridge Configuration */
5008
5009 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
5010 << MVPP22_AXI_ATTR_CACHE_OFFS;
5011 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5012 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5013
5014 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5015 << MVPP22_AXI_ATTR_CACHE_OFFS;
5016 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5017 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5018
5019 /* BM */
5020 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5021 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5022
5023 /* Descriptors */
5024 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5025 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5026 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5027 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5028
5029 /* Buffer Data */
5030 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5031 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5032
5033 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5034 << MVPP22_AXI_CODE_CACHE_OFFS;
5035 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5036 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5037 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5038 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5039
5040 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5041 << MVPP22_AXI_CODE_CACHE_OFFS;
5042 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5043 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5044
5045 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5046
5047 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5048 << MVPP22_AXI_CODE_CACHE_OFFS;
5049 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5050 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5051
5052 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5053}
5054
3f518509
MW		 5055/* Initialize network controller common part HW */
5056static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5057{
5058 const struct mbus_dram_target_info *dram_target_info;
5059 int err, i;
08a23755 5060 u32 val;
3f518509 5061
3f518509
MW		 5062 /* MBUS windows configuration */
5063 dram_target_info = mv_mbus_dram_info();
5064 if (dram_target_info)
5065 mvpp2_conf_mbus_windows(dram_target_info, priv);
5066
6763ce31
TP		 5067 if (priv->hw_version == MVPP22)
5068 mvpp2_axi_init(priv);
5069
08a23755 5070 /* Disable HW PHY polling */
26975821
TP		 5071 if (priv->hw_version == MVPP21) {
5072 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5073 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5074 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5075 } else {
5076 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5077 val &= ~MVPP22_SMI_POLLING_EN;
5078 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5079 }
08a23755 5080
3f518509
MW		 5081 /* Allocate and initialize aggregated TXQs */
5082 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(),
d7ce3cec 5083 sizeof(*priv->aggr_txqs),
3f518509
MW		 5084 GFP_KERNEL);
5085 if (!priv->aggr_txqs)
5086 return -ENOMEM;
5087
5088 for_each_present_cpu(i) {
5089 priv->aggr_txqs[i].id = i;
5090 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
85affd7e 5091 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
3f518509
MW		 5092 if (err < 0)
5093 return err;
5094 }
5095
7c10f974
AT		 5096 /* Fifo Init */
5097 if (priv->hw_version == MVPP21) {
2d1d7df8 5098 mvpp2_rx_fifo_init(priv);
7c10f974 5099 } else {
2d1d7df8 5100 mvpp22_rx_fifo_init(priv);
7c10f974
AT		 5101 mvpp22_tx_fifo_init(priv);
5102 }
3f518509 5103
26975821
TP		 5104 if (priv->hw_version == MVPP21)
5105 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5106 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3f518509
MW		 5107
5108 /* Allow cache snoop when transmiting packets */
5109 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5110
5111 /* Buffer Manager initialization */
5112 err = mvpp2_bm_init(pdev, priv);
5113 if (err < 0)
5114 return err;
5115
5116 /* Parser default initialization */
5117 err = mvpp2_prs_default_init(pdev, priv);
5118 if (err < 0)
5119 return err;
5120
5121 /* Classifier default initialization */
5122 mvpp2_cls_init(priv);
5123
5124 return 0;
5125}
5126
5127static int mvpp2_probe(struct platform_device *pdev)
5128{
a75edc7c 5129 const struct acpi_device_id *acpi_id;
24812221
MW		 5130 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5131 struct fwnode_handle *port_fwnode;
3f518509
MW		 5132 struct mvpp2 *priv;
5133 struct resource *res;
a786841d 5134 void __iomem *base;
118d6298 5135 int i;
3f518509
MW		 5136 int err;
5137
0b92e594 5138 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
3f518509
MW		 5139 if (!priv)
5140 return -ENOMEM;
5141
a75edc7c
MW		 5142 if (has_acpi_companion(&pdev->dev)) {
5143 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5144 &pdev->dev);
5145 priv->hw_version = (unsigned long)acpi_id->driver_data;
5146 } else {
5147 priv->hw_version =
5148 (unsigned long)of_device_get_match_data(&pdev->dev);
5149 }
faca9247 5150
1e27a628
MC		 5151 /* multi queue mode isn't supported on PPV2.1, fallback to single
5152 * mode
5153 */
5154 if (priv->hw_version == MVPP21)
5155 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5156
3f518509 5157 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a786841d
TP		 5158 base = devm_ioremap_resource(&pdev->dev, res);
5159 if (IS_ERR(base))
5160 return PTR_ERR(base);
5161
5162 if (priv->hw_version == MVPP21) {
5163 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5164 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5165 if (IS_ERR(priv->lms_base))
5166 return PTR_ERR(priv->lms_base);
5167 } else {
5168 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
a75edc7c
MW		 5169 if (has_acpi_companion(&pdev->dev)) {
5170 /* In case the MDIO memory region is declared in
5171 * the ACPI, it can already appear as 'in-use'
5172 * in the OS. Because it is overlapped by second
5173 * region of the network controller, make
5174 * sure it is released, before requesting it again.
5175 * The care is taken by mvpp2 driver to avoid
5176 * concurrent access to this memory region.
5177 */
5178 release_resource(res);
5179 }
a786841d
TP		 5180 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5181 if (IS_ERR(priv->iface_base))
5182 return PTR_ERR(priv->iface_base);
a75edc7c 5183 }
f84bf386 5184
a75edc7c 5185 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
f84bf386
AT		 5186 priv->sysctrl_base =
5187 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5188 "marvell,system-controller");
5189 if (IS_ERR(priv->sysctrl_base))
5190 /* The system controller regmap is optional for dt
5191 * compatibility reasons. When not provided, the
5192 * configuration of the GoP relies on the
5193 * firmware/bootloader.
5194 */
5195 priv->sysctrl_base = NULL;
a786841d
TP		 5196 }
5197
01d04936
SC		 5198 mvpp2_setup_bm_pool();
5199
df089aa0 5200 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
a786841d
TP		 5201 u32 addr_space_sz;
5202
5203 addr_space_sz = (priv->hw_version == MVPP21 ?
5204 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
df089aa0 5205 priv->swth_base[i] = base + i * addr_space_sz;
a786841d 5206 }
3f518509 5207
59b9a31e
TP		 5208 if (priv->hw_version == MVPP21)
5209 priv->max_port_rxqs = 8;
5210 else
5211 priv->max_port_rxqs = 32;
5212
a75edc7c
MW		 5213 if (dev_of_node(&pdev->dev)) {
5214 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5215 if (IS_ERR(priv->pp_clk))
5216 return PTR_ERR(priv->pp_clk);
5217 err = clk_prepare_enable(priv->pp_clk);
5218 if (err < 0)
5219 return err;
3f518509 5220
a75edc7c
MW		 5221 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5222 if (IS_ERR(priv->gop_clk)) {
5223 err = PTR_ERR(priv->gop_clk);
5224 goto err_pp_clk;
fceb55d4 5225 }
a75edc7c 5226 err = clk_prepare_enable(priv->gop_clk);
fceb55d4 5227 if (err < 0)
a75edc7c
MW		 5228 goto err_pp_clk;
5229
5230 if (priv->hw_version == MVPP22) {
5231 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5232 if (IS_ERR(priv->mg_clk)) {
5233 err = PTR_ERR(priv->mg_clk);
5234 goto err_gop_clk;
5235 }
5236
5237 err = clk_prepare_enable(priv->mg_clk);
5238 if (err < 0)
5239 goto err_gop_clk;
9af771ce
MC		 5240
5241 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5242 if (IS_ERR(priv->mg_core_clk)) {
5243 priv->mg_core_clk = NULL;
5244 } else {
5245 err = clk_prepare_enable(priv->mg_core_clk);
5246 if (err < 0)
5247 goto err_mg_clk;
5248 }
a75edc7c 5249 }
4792ea04
GC		 5250
5251 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5252 if (IS_ERR(priv->axi_clk)) {
5253 err = PTR_ERR(priv->axi_clk);
5254 if (err == -EPROBE_DEFER)
9af771ce 5255 goto err_mg_core_clk;
4792ea04
GC		 5256 priv->axi_clk = NULL;
5257 } else {
5258 err = clk_prepare_enable(priv->axi_clk);
5259 if (err < 0)
9af771ce 5260 goto err_mg_core_clk;
4792ea04 5261 }
fceb55d4 5262
a75edc7c
MW		 5263 /* Get system's tclk rate */
5264 priv->tclk = clk_get_rate(priv->pp_clk);
5265 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5266 &priv->tclk)) {
5267 dev_err(&pdev->dev, "missing clock-frequency value\n");
5268 return -EINVAL;
5269 }
3f518509 5270
2067e0a1 5271 if (priv->hw_version == MVPP22) {
da42bb27 5272 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
2067e0a1 5273 if (err)
45f972ad 5274 goto err_axi_clk;
2067e0a1
TP		 5275 /* Sadly, the BM pools all share the same register to
5276 * store the high 32 bits of their address. So they
5277 * must all have the same high 32 bits, which forces
5278 * us to restrict coherent memory to DMA_BIT_MASK(32).
5279 */
5280 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5281 if (err)
45f972ad 5282 goto err_axi_clk;
2067e0a1
TP		 5283 }
5284
3f518509
MW		 5285 /* Initialize network controller */
5286 err = mvpp2_init(pdev, priv);
5287 if (err < 0) {
5288 dev_err(&pdev->dev, "failed to initialize controller\n");
45f972ad 5289 goto err_axi_clk;
3f518509
MW		 5290 }
5291
3f518509 5292 /* Initialize ports */
24812221
MW		 5293 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5294 err = mvpp2_port_probe(pdev, port_fwnode, priv);
3f518509 5295 if (err < 0)
26146b0e 5296 goto err_port_probe;
bf147153
MW		 5297 }
5298
5299 if (priv->port_count == 0) {
5300 dev_err(&pdev->dev, "no ports enabled\n");
5301 err = -ENODEV;
45f972ad 5302 goto err_axi_clk;
3f518509
MW		 5303 }
5304
118d6298
MR		 5305 /* Statistics must be gathered regularly because some of them (like
5306 * packets counters) are 32-bit registers and could overflow quite
5307 * quickly. For instance, a 10Gb link used at full bandwidth with the
5308 * smallest packets (64B) will overflow a 32-bit counter in less than
5309 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5310 */
118d6298
MR		 5311 snprintf(priv->queue_name, sizeof(priv->queue_name),
5312 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5313 priv->port_count > 1 ? "+" : "");
5314 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5315 if (!priv->stats_queue) {
5316 err = -ENOMEM;
26146b0e 5317 goto err_port_probe;
118d6298
MR		 5318 }
5319
21da57a2
MC		 5320 mvpp2_dbgfs_init(priv, pdev->name);
5321
3f518509
MW		 5322 platform_set_drvdata(pdev, priv);
5323 return 0;
5324
26146b0e
AT		 5325err_port_probe:
5326 i = 0;
24812221 5327 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
26146b0e
AT		 5328 if (priv->port_list[i])
5329 mvpp2_port_remove(priv->port_list[i]);
5330 i++;
5331 }
45f972ad 5332err_axi_clk:
4792ea04 5333 clk_disable_unprepare(priv->axi_clk);
9af771ce
MC		 5334
5335err_mg_core_clk:
5336 if (priv->hw_version == MVPP22)
5337 clk_disable_unprepare(priv->mg_core_clk);
45f972ad 5338err_mg_clk:
fceb55d4
TP		 5339 if (priv->hw_version == MVPP22)
5340 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5341err_gop_clk:
5342 clk_disable_unprepare(priv->gop_clk);
5343err_pp_clk:
5344 clk_disable_unprepare(priv->pp_clk);
5345 return err;
5346}
5347
5348static int mvpp2_remove(struct platform_device *pdev)
5349{
5350 struct mvpp2 *priv = platform_get_drvdata(pdev);
24812221
MW		 5351 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5352 struct fwnode_handle *port_fwnode;
3f518509
MW		 5353 int i = 0;
5354
21da57a2
MC		 5355 mvpp2_dbgfs_cleanup(priv);
5356
e5c500eb 5357 flush_workqueue(priv->stats_queue);
118d6298 5358 destroy_workqueue(priv->stats_queue);
118d6298 5359
24812221 5360 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
e5c500eb
MR		 5361 if (priv->port_list[i]) {
5362 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
3f518509 5363 mvpp2_port_remove(priv->port_list[i]);
e5c500eb 5364 }
3f518509
MW		 5365 i++;
5366 }
5367
5368 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5369 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5370
5371 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5372 }
5373
5374 for_each_present_cpu(i) {
5375 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5376
5377 dma_free_coherent(&pdev->dev,
5378 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5379 aggr_txq->descs,
20396136 5380 aggr_txq->descs_dma);
3f518509
MW		 5381 }
5382
a75edc7c
MW		 5383 if (is_acpi_node(port_fwnode))
5384 return 0;
5385
4792ea04 5386 clk_disable_unprepare(priv->axi_clk);
9af771ce 5387 clk_disable_unprepare(priv->mg_core_clk);
fceb55d4 5388 clk_disable_unprepare(priv->mg_clk);
3f518509
MW		 5389 clk_disable_unprepare(priv->pp_clk);
5390 clk_disable_unprepare(priv->gop_clk);
5391
5392 return 0;
5393}
5394
5395static const struct of_device_id mvpp2_match[] = {
faca9247
TP		 5396 {
5397 .compatible = "marvell,armada-375-pp2",
5398 .data = (void *)MVPP21,
5399 },
fc5e1550
TP		 5400 {
5401 .compatible = "marvell,armada-7k-pp22",
5402 .data = (void *)MVPP22,
5403 },
3f518509
MW		 5404 { }
5405};
5406MODULE_DEVICE_TABLE(of, mvpp2_match);
5407
a75edc7c
MW		 5408static const struct acpi_device_id mvpp2_acpi_match[] = {
5409 { "MRVL0110", MVPP22 },
5410 { },
5411};
5412MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5413
3f518509
MW		 5414static struct platform_driver mvpp2_driver = {
5415 .probe = mvpp2_probe,
5416 .remove = mvpp2_remove,
5417 .driver = {
5418 .name = MVPP2_DRIVER_NAME,
5419 .of_match_table = mvpp2_match,
a75edc7c 5420 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
3f518509
MW		 5421 },
5422};
5423
5424module_platform_driver(mvpp2_driver);
5425
5426MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5427MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
c634099d 5428MODULE_LICENSE("GPL v2");
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