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3f518509 MW |
1 | /* |
2 | * Driver for Marvell PPv2 network controller for Armada 375 SoC. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Marcin Wojtas <mw@semihalf.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/skbuff.h> | |
18 | #include <linux/inetdevice.h> | |
19 | #include <linux/mbus.h> | |
20 | #include <linux/module.h> | |
f84bf386 | 21 | #include <linux/mfd/syscon.h> |
3f518509 MW |
22 | #include <linux/interrupt.h> |
23 | #include <linux/cpumask.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_irq.h> | |
26 | #include <linux/of_mdio.h> | |
27 | #include <linux/of_net.h> | |
28 | #include <linux/of_address.h> | |
faca9247 | 29 | #include <linux/of_device.h> |
3f518509 | 30 | #include <linux/phy.h> |
542897d9 | 31 | #include <linux/phy/phy.h> |
3f518509 | 32 | #include <linux/clk.h> |
edc660fa MW |
33 | #include <linux/hrtimer.h> |
34 | #include <linux/ktime.h> | |
f84bf386 | 35 | #include <linux/regmap.h> |
3f518509 MW |
36 | #include <uapi/linux/ppp_defs.h> |
37 | #include <net/ip.h> | |
38 | #include <net/ipv6.h> | |
186cd4d4 | 39 | #include <net/tso.h> |
3f518509 MW |
40 | |
41 | /* RX Fifo Registers */ | |
42 | #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) | |
43 | #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) | |
44 | #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 | |
45 | #define MVPP2_RX_FIFO_INIT_REG 0x64 | |
46 | ||
47 | /* RX DMA Top Registers */ | |
48 | #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) | |
49 | #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) | |
50 | #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) | |
51 | #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) | |
52 | #define MVPP2_POOL_BUF_SIZE_OFFSET 5 | |
53 | #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) | |
54 | #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff | |
55 | #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) | |
56 | #define MVPP2_RXQ_POOL_SHORT_OFFS 20 | |
5eac892a TP |
57 | #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 |
58 | #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 | |
3f518509 | 59 | #define MVPP2_RXQ_POOL_LONG_OFFS 24 |
5eac892a TP |
60 | #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 |
61 | #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 | |
3f518509 MW |
62 | #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 |
63 | #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 | |
64 | #define MVPP2_RXQ_DISABLE_MASK BIT(31) | |
65 | ||
66 | /* Parser Registers */ | |
67 | #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 | |
68 | #define MVPP2_PRS_PORT_LU_MAX 0xf | |
69 | #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) | |
70 | #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) | |
71 | #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) | |
72 | #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) | |
73 | #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
74 | #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) | |
75 | #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) | |
76 | #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
77 | #define MVPP2_PRS_TCAM_IDX_REG 0x1100 | |
78 | #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) | |
79 | #define MVPP2_PRS_TCAM_INV_MASK BIT(31) | |
80 | #define MVPP2_PRS_SRAM_IDX_REG 0x1200 | |
81 | #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) | |
82 | #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 | |
83 | #define MVPP2_PRS_TCAM_EN_MASK BIT(0) | |
84 | ||
85 | /* Classifier Registers */ | |
86 | #define MVPP2_CLS_MODE_REG 0x1800 | |
87 | #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) | |
88 | #define MVPP2_CLS_PORT_WAY_REG 0x1810 | |
89 | #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) | |
90 | #define MVPP2_CLS_LKP_INDEX_REG 0x1814 | |
91 | #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 | |
92 | #define MVPP2_CLS_LKP_TBL_REG 0x1818 | |
93 | #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff | |
94 | #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) | |
95 | #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 | |
96 | #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 | |
97 | #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 | |
98 | #define MVPP2_CLS_FLOW_TBL2_REG 0x182c | |
99 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) | |
100 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 | |
101 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 | |
102 | #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) | |
103 | #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 | |
104 | #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) | |
105 | ||
106 | /* Descriptor Manager Top Registers */ | |
107 | #define MVPP2_RXQ_NUM_REG 0x2040 | |
108 | #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 | |
b02f31fb | 109 | #define MVPP22_DESC_ADDR_OFFS 8 |
3f518509 MW |
110 | #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 |
111 | #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 | |
112 | #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) | |
113 | #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 | |
114 | #define MVPP2_RXQ_NUM_NEW_OFFSET 16 | |
115 | #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) | |
116 | #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff | |
117 | #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 | |
118 | #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 | |
119 | #define MVPP2_RXQ_THRESH_REG 0x204c | |
120 | #define MVPP2_OCCUPIED_THRESH_OFFSET 0 | |
121 | #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff | |
122 | #define MVPP2_RXQ_INDEX_REG 0x2050 | |
123 | #define MVPP2_TXQ_NUM_REG 0x2080 | |
124 | #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 | |
125 | #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 | |
126 | #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 | |
213f428f TP |
127 | #define MVPP2_TXQ_THRESH_REG 0x2094 |
128 | #define MVPP2_TXQ_THRESH_OFFSET 16 | |
129 | #define MVPP2_TXQ_THRESH_MASK 0x3fff | |
3f518509 | 130 | #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 |
3f518509 MW |
131 | #define MVPP2_TXQ_INDEX_REG 0x2098 |
132 | #define MVPP2_TXQ_PREF_BUF_REG 0x209c | |
133 | #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) | |
134 | #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) | |
135 | #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) | |
136 | #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) | |
137 | #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) | |
138 | #define MVPP2_TXQ_PENDING_REG 0x20a0 | |
139 | #define MVPP2_TXQ_PENDING_MASK 0x3fff | |
140 | #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 | |
141 | #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) | |
142 | #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 | |
143 | #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 | |
144 | #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 | |
145 | #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 | |
146 | #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 | |
147 | #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff | |
148 | #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 | |
149 | #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 | |
150 | #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) | |
b02f31fb | 151 | #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 |
3f518509 MW |
152 | #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) |
153 | #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 | |
154 | #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) | |
155 | #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff | |
156 | #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) | |
157 | ||
158 | /* MBUS bridge registers */ | |
159 | #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) | |
160 | #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) | |
161 | #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) | |
162 | #define MVPP2_BASE_ADDR_ENABLE 0x4060 | |
163 | ||
6763ce31 TP |
164 | /* AXI Bridge Registers */ |
165 | #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 | |
166 | #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 | |
167 | #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 | |
168 | #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 | |
169 | #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 | |
170 | #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c | |
171 | #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 | |
172 | #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 | |
173 | #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 | |
174 | #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 | |
175 | #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 | |
176 | #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 | |
177 | ||
178 | /* Values for AXI Bridge registers */ | |
179 | #define MVPP22_AXI_ATTR_CACHE_OFFS 0 | |
180 | #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 | |
181 | ||
182 | #define MVPP22_AXI_CODE_CACHE_OFFS 0 | |
183 | #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 | |
184 | ||
185 | #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 | |
186 | #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 | |
187 | #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb | |
188 | ||
189 | #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 | |
190 | #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 | |
191 | ||
3f518509 | 192 | /* Interrupt Cause and Mask registers */ |
213f428f TP |
193 | #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) |
194 | #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 | |
195 | ||
3f518509 | 196 | #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) |
ab42676a | 197 | #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 |
eb1e93a1 | 198 | #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) |
a73fef10 | 199 | |
81b6630f | 200 | #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 |
a73fef10 | 201 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf |
81b6630f AT |
202 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
203 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 | |
a73fef10 TP |
204 | |
205 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf | |
81b6630f | 206 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
a73fef10 | 207 | |
81b6630f AT |
208 | #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 |
209 | #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f | |
210 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 | |
211 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 | |
a73fef10 | 212 | |
3f518509 MW |
213 | #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) |
214 | #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) | |
215 | #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) | |
216 | #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) | |
217 | #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
218 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 | |
213f428f | 219 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 |
3f518509 MW |
220 | #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) |
221 | #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) | |
222 | #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) | |
223 | #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) | |
224 | #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) | |
225 | #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) | |
226 | #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) | |
227 | #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc | |
228 | #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
229 | #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 | |
230 | #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) | |
231 | #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 | |
232 | ||
233 | /* Buffer Manager registers */ | |
234 | #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) | |
235 | #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 | |
236 | #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) | |
237 | #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 | |
238 | #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) | |
239 | #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 | |
240 | #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) | |
241 | #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 | |
242 | #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) | |
243 | #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) | |
244 | #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff | |
245 | #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) | |
246 | #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) | |
247 | #define MVPP2_BM_START_MASK BIT(0) | |
248 | #define MVPP2_BM_STOP_MASK BIT(1) | |
249 | #define MVPP2_BM_STATE_MASK BIT(4) | |
250 | #define MVPP2_BM_LOW_THRESH_OFFS 8 | |
251 | #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 | |
252 | #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ | |
253 | MVPP2_BM_LOW_THRESH_OFFS) | |
254 | #define MVPP2_BM_HIGH_THRESH_OFFS 16 | |
255 | #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 | |
256 | #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ | |
257 | MVPP2_BM_HIGH_THRESH_OFFS) | |
258 | #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) | |
259 | #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) | |
260 | #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) | |
261 | #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) | |
262 | #define MVPP2_BM_BPPE_FULL_MASK BIT(3) | |
263 | #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) | |
264 | #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) | |
265 | #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) | |
266 | #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) | |
267 | #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 | |
d01524d8 TP |
268 | #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 |
269 | #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff | |
270 | #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 | |
271 | #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 | |
3f518509 MW |
272 | #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) |
273 | #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) | |
274 | #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) | |
275 | #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) | |
276 | #define MVPP2_BM_VIRT_RLS_REG 0x64c0 | |
d01524d8 TP |
277 | #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 |
278 | #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff | |
81b6630f | 279 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 |
d01524d8 | 280 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 |
3f518509 MW |
281 | |
282 | /* TX Scheduler registers */ | |
283 | #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 | |
284 | #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 | |
285 | #define MVPP2_TXP_SCHED_ENQ_MASK 0xff | |
286 | #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 | |
287 | #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 | |
288 | #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 | |
289 | #define MVPP2_TXP_SCHED_MTU_REG 0x801c | |
290 | #define MVPP2_TXP_MTU_MAX 0x7FFFF | |
291 | #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 | |
292 | #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff | |
293 | #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
294 | #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) | |
295 | #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 | |
296 | #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff | |
297 | #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) | |
298 | #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff | |
299 | #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
300 | #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) | |
301 | #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) | |
302 | #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
303 | #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) | |
304 | #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff | |
305 | ||
306 | /* TX general registers */ | |
307 | #define MVPP2_TX_SNOOP_REG 0x8800 | |
308 | #define MVPP2_TX_PORT_FLUSH_REG 0x8810 | |
309 | #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) | |
310 | ||
311 | /* LMS registers */ | |
312 | #define MVPP2_SRC_ADDR_MIDDLE 0x24 | |
313 | #define MVPP2_SRC_ADDR_HIGH 0x28 | |
08a23755 MW |
314 | #define MVPP2_PHY_AN_CFG0_REG 0x34 |
315 | #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) | |
3f518509 | 316 | #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c |
31d7677b | 317 | #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 |
3f518509 MW |
318 | |
319 | /* Per-port registers */ | |
320 | #define MVPP2_GMAC_CTRL_0_REG 0x0 | |
81b6630f | 321 | #define MVPP2_GMAC_PORT_EN_MASK BIT(0) |
3919357f | 322 | #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) |
81b6630f AT |
323 | #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 |
324 | #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
325 | #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) | |
3f518509 | 326 | #define MVPP2_GMAC_CTRL_1_REG 0x4 |
81b6630f AT |
327 | #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) |
328 | #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) | |
329 | #define MVPP2_GMAC_PCS_LB_EN_BIT 6 | |
330 | #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) | |
331 | #define MVPP2_GMAC_SA_LOW_OFFS 7 | |
3f518509 | 332 | #define MVPP2_GMAC_CTRL_2_REG 0x8 |
81b6630f | 333 | #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) |
3919357f | 334 | #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) |
81b6630f | 335 | #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) |
c7dfc8c8 | 336 | #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) |
3919357f | 337 | #define MVPP2_GMAC_DISABLE_PADDING BIT(5) |
81b6630f | 338 | #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) |
3f518509 | 339 | #define MVPP2_GMAC_AUTONEG_CONFIG 0xc |
81b6630f AT |
340 | #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) |
341 | #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) | |
3919357f AT |
342 | #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) |
343 | #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) | |
81b6630f AT |
344 | #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) |
345 | #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) | |
346 | #define MVPP2_GMAC_AN_SPEED_EN BIT(7) | |
347 | #define MVPP2_GMAC_FC_ADV_EN BIT(9) | |
3919357f | 348 | #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) |
81b6630f AT |
349 | #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
350 | #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) | |
fd3651b2 AT |
351 | #define MVPP2_GMAC_STATUS0 0x10 |
352 | #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) | |
3f518509 | 353 | #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c |
81b6630f AT |
354 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 |
355 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 | |
356 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ | |
3f518509 | 357 | MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) |
fd3651b2 AT |
358 | #define MVPP22_GMAC_INT_STAT 0x20 |
359 | #define MVPP22_GMAC_INT_STAT_LINK BIT(1) | |
360 | #define MVPP22_GMAC_INT_MASK 0x24 | |
361 | #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) | |
26975821 | 362 | #define MVPP22_GMAC_CTRL_4_REG 0x90 |
81b6630f AT |
363 | #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) |
364 | #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) | |
1068ec79 | 365 | #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) |
81b6630f | 366 | #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) |
fd3651b2 AT |
367 | #define MVPP22_GMAC_INT_SUM_MASK 0xa4 |
368 | #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) | |
26975821 TP |
369 | |
370 | /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, | |
371 | * relative to port->base. | |
372 | */ | |
725757ae | 373 | #define MVPP22_XLG_CTRL0_REG 0x100 |
81b6630f AT |
374 | #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) |
375 | #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) | |
77321959 | 376 | #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) |
81b6630f | 377 | #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) |
76eb1b1d | 378 | #define MVPP22_XLG_CTRL1_REG 0x104 |
ec15ecde | 379 | #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 |
76eb1b1d | 380 | #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff |
fd3651b2 AT |
381 | #define MVPP22_XLG_STATUS 0x10c |
382 | #define MVPP22_XLG_STATUS_LINK_UP BIT(0) | |
383 | #define MVPP22_XLG_INT_STAT 0x114 | |
384 | #define MVPP22_XLG_INT_STAT_LINK BIT(1) | |
385 | #define MVPP22_XLG_INT_MASK 0x118 | |
386 | #define MVPP22_XLG_INT_MASK_LINK BIT(1) | |
26975821 | 387 | #define MVPP22_XLG_CTRL3_REG 0x11c |
81b6630f AT |
388 | #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) |
389 | #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) | |
390 | #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) | |
fd3651b2 AT |
391 | #define MVPP22_XLG_EXT_INT_MASK 0x15c |
392 | #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) | |
393 | #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) | |
77321959 AT |
394 | #define MVPP22_XLG_CTRL4_REG 0x184 |
395 | #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) | |
396 | #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) | |
397 | #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) | |
398 | ||
26975821 TP |
399 | /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ |
400 | #define MVPP22_SMI_MISC_CFG_REG 0x1204 | |
81b6630f | 401 | #define MVPP22_SMI_POLLING_EN BIT(10) |
3f518509 | 402 | |
a786841d TP |
403 | #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) |
404 | ||
3f518509 MW |
405 | #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
406 | ||
407 | /* Descriptor ring Macros */ | |
408 | #define MVPP2_QUEUE_NEXT_DESC(q, index) \ | |
409 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
410 | ||
f84bf386 AT |
411 | /* XPCS registers. PPv2.2 only */ |
412 | #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) | |
413 | #define MVPP22_MPCS_CTRL 0x14 | |
414 | #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) | |
415 | #define MVPP22_MPCS_CLK_RESET 0x14c | |
416 | #define MAC_CLK_RESET_SD_TX BIT(0) | |
417 | #define MAC_CLK_RESET_SD_RX BIT(1) | |
418 | #define MAC_CLK_RESET_MAC BIT(2) | |
419 | #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) | |
420 | #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) | |
421 | ||
422 | /* XPCS registers. PPv2.2 only */ | |
423 | #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) | |
424 | #define MVPP22_XPCS_CFG0 0x0 | |
425 | #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) | |
426 | #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) | |
427 | ||
428 | /* System controller registers. Accessed through a regmap. */ | |
429 | #define GENCONF_SOFT_RESET1 0x1108 | |
430 | #define GENCONF_SOFT_RESET1_GOP BIT(6) | |
431 | #define GENCONF_PORT_CTRL0 0x1110 | |
432 | #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) | |
433 | #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) | |
434 | #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) | |
435 | #define GENCONF_PORT_CTRL1 0x1114 | |
436 | #define GENCONF_PORT_CTRL1_EN(p) BIT(p) | |
437 | #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) | |
438 | #define GENCONF_CTRL0 0x1120 | |
439 | #define GENCONF_CTRL0_PORT0_RGMII BIT(0) | |
440 | #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) | |
441 | #define GENCONF_CTRL0_PORT1_RGMII BIT(2) | |
442 | ||
3f518509 MW |
443 | /* Various constants */ |
444 | ||
445 | /* Coalescing */ | |
446 | #define MVPP2_TXDONE_COAL_PKTS_THRESH 15 | |
edc660fa | 447 | #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL |
213f428f | 448 | #define MVPP2_TXDONE_COAL_USEC 1000 |
3f518509 MW |
449 | #define MVPP2_RX_COAL_PKTS 32 |
450 | #define MVPP2_RX_COAL_USEC 100 | |
451 | ||
452 | /* The two bytes Marvell header. Either contains a special value used | |
453 | * by Marvell switches when a specific hardware mode is enabled (not | |
454 | * supported by this driver) or is filled automatically by zeroes on | |
455 | * the RX side. Those two bytes being at the front of the Ethernet | |
456 | * header, they allow to have the IP header aligned on a 4 bytes | |
457 | * boundary automatically: the hardware skips those two bytes on its | |
458 | * own. | |
459 | */ | |
460 | #define MVPP2_MH_SIZE 2 | |
461 | #define MVPP2_ETH_TYPE_LEN 2 | |
462 | #define MVPP2_PPPOE_HDR_SIZE 8 | |
463 | #define MVPP2_VLAN_TAG_LEN 4 | |
464 | ||
465 | /* Lbtd 802.3 type */ | |
466 | #define MVPP2_IP_LBDT_TYPE 0xfffa | |
467 | ||
3f518509 MW |
468 | #define MVPP2_TX_CSUM_MAX_SIZE 9800 |
469 | ||
470 | /* Timeout constants */ | |
471 | #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 | |
472 | #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 | |
473 | ||
474 | #define MVPP2_TX_MTU_MAX 0x7ffff | |
475 | ||
476 | /* Maximum number of T-CONTs of PON port */ | |
477 | #define MVPP2_MAX_TCONT 16 | |
478 | ||
479 | /* Maximum number of supported ports */ | |
480 | #define MVPP2_MAX_PORTS 4 | |
481 | ||
482 | /* Maximum number of TXQs used by single port */ | |
483 | #define MVPP2_MAX_TXQ 8 | |
484 | ||
3f518509 MW |
485 | /* Dfault number of RXQs in use */ |
486 | #define MVPP2_DEFAULT_RXQ 4 | |
487 | ||
3f518509 MW |
488 | /* Max number of Rx descriptors */ |
489 | #define MVPP2_MAX_RXD 128 | |
490 | ||
491 | /* Max number of Tx descriptors */ | |
492 | #define MVPP2_MAX_TXD 1024 | |
493 | ||
494 | /* Amount of Tx descriptors that can be reserved at once by CPU */ | |
495 | #define MVPP2_CPU_DESC_CHUNK 64 | |
496 | ||
497 | /* Max number of Tx descriptors in each aggregated queue */ | |
498 | #define MVPP2_AGGR_TXQ_SIZE 256 | |
499 | ||
500 | /* Descriptor aligned size */ | |
501 | #define MVPP2_DESC_ALIGNED_SIZE 32 | |
502 | ||
503 | /* Descriptor alignment mask */ | |
504 | #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) | |
505 | ||
506 | /* RX FIFO constants */ | |
507 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000 | |
508 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80 | |
509 | #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 | |
510 | ||
511 | /* RX buffer constants */ | |
512 | #define MVPP2_SKB_SHINFO_SIZE \ | |
513 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) | |
514 | ||
515 | #define MVPP2_RX_PKT_SIZE(mtu) \ | |
516 | ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ | |
4a0a12d2 | 517 | ETH_HLEN + ETH_FCS_LEN, cache_line_size()) |
3f518509 MW |
518 | |
519 | #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) | |
520 | #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) | |
521 | #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ | |
522 | ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) | |
523 | ||
524 | #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) | |
525 | ||
526 | /* IPv6 max L3 address size */ | |
527 | #define MVPP2_MAX_L3_ADDR_SIZE 16 | |
528 | ||
529 | /* Port flags */ | |
530 | #define MVPP2_F_LOOPBACK BIT(0) | |
531 | ||
532 | /* Marvell tag types */ | |
533 | enum mvpp2_tag_type { | |
534 | MVPP2_TAG_TYPE_NONE = 0, | |
535 | MVPP2_TAG_TYPE_MH = 1, | |
536 | MVPP2_TAG_TYPE_DSA = 2, | |
537 | MVPP2_TAG_TYPE_EDSA = 3, | |
538 | MVPP2_TAG_TYPE_VLAN = 4, | |
539 | MVPP2_TAG_TYPE_LAST = 5 | |
540 | }; | |
541 | ||
542 | /* Parser constants */ | |
543 | #define MVPP2_PRS_TCAM_SRAM_SIZE 256 | |
544 | #define MVPP2_PRS_TCAM_WORDS 6 | |
545 | #define MVPP2_PRS_SRAM_WORDS 4 | |
546 | #define MVPP2_PRS_FLOW_ID_SIZE 64 | |
547 | #define MVPP2_PRS_FLOW_ID_MASK 0x3f | |
548 | #define MVPP2_PRS_TCAM_ENTRY_INVALID 1 | |
549 | #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) | |
550 | #define MVPP2_PRS_IPV4_HEAD 0x40 | |
551 | #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 | |
552 | #define MVPP2_PRS_IPV4_MC 0xe0 | |
553 | #define MVPP2_PRS_IPV4_MC_MASK 0xf0 | |
554 | #define MVPP2_PRS_IPV4_BC_MASK 0xff | |
555 | #define MVPP2_PRS_IPV4_IHL 0x5 | |
556 | #define MVPP2_PRS_IPV4_IHL_MASK 0xf | |
557 | #define MVPP2_PRS_IPV6_MC 0xff | |
558 | #define MVPP2_PRS_IPV6_MC_MASK 0xff | |
559 | #define MVPP2_PRS_IPV6_HOP_MASK 0xff | |
560 | #define MVPP2_PRS_TCAM_PROTO_MASK 0xff | |
561 | #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f | |
562 | #define MVPP2_PRS_DBL_VLANS_MAX 100 | |
563 | ||
564 | /* Tcam structure: | |
565 | * - lookup ID - 4 bits | |
566 | * - port ID - 1 byte | |
567 | * - additional information - 1 byte | |
568 | * - header data - 8 bytes | |
569 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). | |
570 | */ | |
571 | #define MVPP2_PRS_AI_BITS 8 | |
572 | #define MVPP2_PRS_PORT_MASK 0xff | |
573 | #define MVPP2_PRS_LU_MASK 0xf | |
574 | #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \ | |
575 | (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) | |
576 | #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \ | |
577 | (((offs) * 2) - ((offs) % 2) + 2) | |
578 | #define MVPP2_PRS_TCAM_AI_BYTE 16 | |
579 | #define MVPP2_PRS_TCAM_PORT_BYTE 17 | |
580 | #define MVPP2_PRS_TCAM_LU_BYTE 20 | |
581 | #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) | |
582 | #define MVPP2_PRS_TCAM_INV_WORD 5 | |
583 | /* Tcam entries ID */ | |
584 | #define MVPP2_PE_DROP_ALL 0 | |
585 | #define MVPP2_PE_FIRST_FREE_TID 1 | |
586 | #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31) | |
587 | #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) | |
588 | #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29) | |
589 | #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) | |
590 | #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27) | |
591 | #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26) | |
592 | #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19) | |
593 | #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) | |
594 | #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) | |
595 | #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) | |
596 | #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) | |
597 | #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) | |
598 | #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13) | |
599 | #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12) | |
600 | #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11) | |
601 | #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10) | |
602 | #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9) | |
603 | #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8) | |
604 | #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7) | |
605 | #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6) | |
606 | #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5) | |
607 | #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4) | |
608 | #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3) | |
609 | #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) | |
610 | #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
611 | ||
612 | /* Sram structure | |
613 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). | |
614 | */ | |
615 | #define MVPP2_PRS_SRAM_RI_OFFS 0 | |
616 | #define MVPP2_PRS_SRAM_RI_WORD 0 | |
617 | #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 | |
618 | #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 | |
619 | #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 | |
620 | #define MVPP2_PRS_SRAM_SHIFT_OFFS 64 | |
621 | #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 | |
622 | #define MVPP2_PRS_SRAM_UDF_OFFS 73 | |
623 | #define MVPP2_PRS_SRAM_UDF_BITS 8 | |
624 | #define MVPP2_PRS_SRAM_UDF_MASK 0xff | |
625 | #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 | |
626 | #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 | |
627 | #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 | |
628 | #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 | |
629 | #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 | |
630 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 | |
631 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 | |
632 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 | |
633 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 | |
634 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 | |
635 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 | |
636 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 | |
637 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 | |
638 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 | |
639 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 | |
640 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 | |
641 | #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 | |
642 | #define MVPP2_PRS_SRAM_AI_OFFS 90 | |
643 | #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 | |
644 | #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 | |
645 | #define MVPP2_PRS_SRAM_AI_MASK 0xff | |
646 | #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 | |
647 | #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf | |
648 | #define MVPP2_PRS_SRAM_LU_DONE_BIT 110 | |
649 | #define MVPP2_PRS_SRAM_LU_GEN_BIT 111 | |
650 | ||
651 | /* Sram result info bits assignment */ | |
652 | #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 | |
653 | #define MVPP2_PRS_RI_DSA_MASK 0x2 | |
8138affc TP |
654 | #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) |
655 | #define MVPP2_PRS_RI_VLAN_NONE 0x0 | |
3f518509 MW |
656 | #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) |
657 | #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) | |
658 | #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) | |
659 | #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 | |
660 | #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) | |
8138affc TP |
661 | #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) |
662 | #define MVPP2_PRS_RI_L2_UCAST 0x0 | |
3f518509 MW |
663 | #define MVPP2_PRS_RI_L2_MCAST BIT(9) |
664 | #define MVPP2_PRS_RI_L2_BCAST BIT(10) | |
665 | #define MVPP2_PRS_RI_PPPOE_MASK 0x800 | |
8138affc TP |
666 | #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) |
667 | #define MVPP2_PRS_RI_L3_UN 0x0 | |
3f518509 MW |
668 | #define MVPP2_PRS_RI_L3_IP4 BIT(12) |
669 | #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) | |
670 | #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) | |
671 | #define MVPP2_PRS_RI_L3_IP6 BIT(14) | |
672 | #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) | |
673 | #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) | |
8138affc TP |
674 | #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) |
675 | #define MVPP2_PRS_RI_L3_UCAST 0x0 | |
3f518509 MW |
676 | #define MVPP2_PRS_RI_L3_MCAST BIT(15) |
677 | #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) | |
678 | #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 | |
aff3da39 | 679 | #define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17) |
3f518509 MW |
680 | #define MVPP2_PRS_RI_UDF3_MASK 0x300000 |
681 | #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) | |
682 | #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 | |
683 | #define MVPP2_PRS_RI_L4_TCP BIT(22) | |
684 | #define MVPP2_PRS_RI_L4_UDP BIT(23) | |
685 | #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) | |
686 | #define MVPP2_PRS_RI_UDF7_MASK 0x60000000 | |
687 | #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) | |
688 | #define MVPP2_PRS_RI_DROP_MASK 0x80000000 | |
689 | ||
690 | /* Sram additional info bits assignment */ | |
691 | #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) | |
692 | #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) | |
693 | #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) | |
694 | #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) | |
695 | #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) | |
696 | #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) | |
697 | #define MVPP2_PRS_SINGLE_VLAN_AI 0 | |
698 | #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) | |
699 | ||
700 | /* DSA/EDSA type */ | |
701 | #define MVPP2_PRS_TAGGED true | |
702 | #define MVPP2_PRS_UNTAGGED false | |
703 | #define MVPP2_PRS_EDSA true | |
704 | #define MVPP2_PRS_DSA false | |
705 | ||
706 | /* MAC entries, shadow udf */ | |
707 | enum mvpp2_prs_udf { | |
708 | MVPP2_PRS_UDF_MAC_DEF, | |
709 | MVPP2_PRS_UDF_MAC_RANGE, | |
710 | MVPP2_PRS_UDF_L2_DEF, | |
711 | MVPP2_PRS_UDF_L2_DEF_COPY, | |
712 | MVPP2_PRS_UDF_L2_USER, | |
713 | }; | |
714 | ||
715 | /* Lookup ID */ | |
716 | enum mvpp2_prs_lookup { | |
717 | MVPP2_PRS_LU_MH, | |
718 | MVPP2_PRS_LU_MAC, | |
719 | MVPP2_PRS_LU_DSA, | |
720 | MVPP2_PRS_LU_VLAN, | |
721 | MVPP2_PRS_LU_L2, | |
722 | MVPP2_PRS_LU_PPPOE, | |
723 | MVPP2_PRS_LU_IP4, | |
724 | MVPP2_PRS_LU_IP6, | |
725 | MVPP2_PRS_LU_FLOWS, | |
726 | MVPP2_PRS_LU_LAST, | |
727 | }; | |
728 | ||
729 | /* L3 cast enum */ | |
730 | enum mvpp2_prs_l3_cast { | |
731 | MVPP2_PRS_L3_UNI_CAST, | |
732 | MVPP2_PRS_L3_MULTI_CAST, | |
733 | MVPP2_PRS_L3_BROAD_CAST | |
734 | }; | |
735 | ||
736 | /* Classifier constants */ | |
737 | #define MVPP2_CLS_FLOWS_TBL_SIZE 512 | |
738 | #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 | |
739 | #define MVPP2_CLS_LKP_TBL_SIZE 64 | |
740 | ||
741 | /* BM constants */ | |
742 | #define MVPP2_BM_POOLS_NUM 8 | |
743 | #define MVPP2_BM_LONG_BUF_NUM 1024 | |
744 | #define MVPP2_BM_SHORT_BUF_NUM 2048 | |
745 | #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) | |
746 | #define MVPP2_BM_POOL_PTR_ALIGN 128 | |
747 | #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port) | |
748 | #define MVPP2_BM_SWF_SHORT_POOL 3 | |
749 | ||
750 | /* BM cookie (32 bits) definition */ | |
751 | #define MVPP2_BM_COOKIE_POOL_OFFS 8 | |
752 | #define MVPP2_BM_COOKIE_CPU_OFFS 24 | |
753 | ||
754 | /* BM short pool packet size | |
755 | * These value assure that for SWF the total number | |
756 | * of bytes allocated for each buffer will be 512 | |
757 | */ | |
758 | #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512) | |
759 | ||
a786841d TP |
760 | #define MVPP21_ADDR_SPACE_SZ 0 |
761 | #define MVPP22_ADDR_SPACE_SZ SZ_64K | |
762 | ||
df089aa0 | 763 | #define MVPP2_MAX_THREADS 8 |
591f4cfa | 764 | #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS |
a786841d | 765 | |
3f518509 MW |
766 | enum mvpp2_bm_type { |
767 | MVPP2_BM_FREE, | |
768 | MVPP2_BM_SWF_LONG, | |
769 | MVPP2_BM_SWF_SHORT | |
770 | }; | |
771 | ||
772 | /* Definitions */ | |
773 | ||
774 | /* Shared Packet Processor resources */ | |
775 | struct mvpp2 { | |
776 | /* Shared registers' base addresses */ | |
3f518509 | 777 | void __iomem *lms_base; |
a786841d TP |
778 | void __iomem *iface_base; |
779 | ||
df089aa0 TP |
780 | /* On PPv2.2, each "software thread" can access the base |
781 | * register through a separate address space, each 64 KB apart | |
782 | * from each other. Typically, such address spaces will be | |
783 | * used per CPU. | |
a786841d | 784 | */ |
df089aa0 | 785 | void __iomem *swth_base[MVPP2_MAX_THREADS]; |
3f518509 | 786 | |
f84bf386 AT |
787 | /* On PPv2.2, some port control registers are located into the system |
788 | * controller space. These registers are accessible through a regmap. | |
789 | */ | |
790 | struct regmap *sysctrl_base; | |
791 | ||
3f518509 MW |
792 | /* Common clocks */ |
793 | struct clk *pp_clk; | |
794 | struct clk *gop_clk; | |
fceb55d4 | 795 | struct clk *mg_clk; |
4792ea04 | 796 | struct clk *axi_clk; |
3f518509 MW |
797 | |
798 | /* List of pointers to port structures */ | |
799 | struct mvpp2_port **port_list; | |
800 | ||
801 | /* Aggregated TXQs */ | |
802 | struct mvpp2_tx_queue *aggr_txqs; | |
803 | ||
804 | /* BM pools */ | |
805 | struct mvpp2_bm_pool *bm_pools; | |
806 | ||
807 | /* PRS shadow table */ | |
808 | struct mvpp2_prs_shadow *prs_shadow; | |
809 | /* PRS auxiliary table for double vlan entries control */ | |
810 | bool *prs_double_vlans; | |
811 | ||
812 | /* Tclk value */ | |
813 | u32 tclk; | |
faca9247 TP |
814 | |
815 | /* HW version */ | |
816 | enum { MVPP21, MVPP22 } hw_version; | |
59b9a31e TP |
817 | |
818 | /* Maximum number of RXQs per port */ | |
819 | unsigned int max_port_rxqs; | |
3f518509 MW |
820 | }; |
821 | ||
822 | struct mvpp2_pcpu_stats { | |
823 | struct u64_stats_sync syncp; | |
824 | u64 rx_packets; | |
825 | u64 rx_bytes; | |
826 | u64 tx_packets; | |
827 | u64 tx_bytes; | |
828 | }; | |
829 | ||
edc660fa MW |
830 | /* Per-CPU port control */ |
831 | struct mvpp2_port_pcpu { | |
832 | struct hrtimer tx_done_timer; | |
833 | bool timer_scheduled; | |
834 | /* Tasklet for egress finalization */ | |
835 | struct tasklet_struct tx_done_tasklet; | |
836 | }; | |
837 | ||
591f4cfa TP |
838 | struct mvpp2_queue_vector { |
839 | int irq; | |
840 | struct napi_struct napi; | |
841 | enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; | |
842 | int sw_thread_id; | |
843 | u16 sw_thread_mask; | |
844 | int first_rxq; | |
845 | int nrxqs; | |
846 | u32 pending_cause_rx; | |
847 | struct mvpp2_port *port; | |
848 | }; | |
849 | ||
3f518509 MW |
850 | struct mvpp2_port { |
851 | u8 id; | |
852 | ||
a786841d TP |
853 | /* Index of the port from the "group of ports" complex point |
854 | * of view | |
855 | */ | |
856 | int gop_id; | |
857 | ||
fd3651b2 AT |
858 | int link_irq; |
859 | ||
3f518509 MW |
860 | struct mvpp2 *priv; |
861 | ||
862 | /* Per-port registers' base address */ | |
863 | void __iomem *base; | |
864 | ||
865 | struct mvpp2_rx_queue **rxqs; | |
09f83975 | 866 | unsigned int nrxqs; |
3f518509 | 867 | struct mvpp2_tx_queue **txqs; |
09f83975 | 868 | unsigned int ntxqs; |
3f518509 MW |
869 | struct net_device *dev; |
870 | ||
871 | int pkt_size; | |
872 | ||
edc660fa MW |
873 | /* Per-CPU port control */ |
874 | struct mvpp2_port_pcpu __percpu *pcpu; | |
875 | ||
3f518509 MW |
876 | /* Flags */ |
877 | unsigned long flags; | |
878 | ||
879 | u16 tx_ring_size; | |
880 | u16 rx_ring_size; | |
881 | struct mvpp2_pcpu_stats __percpu *stats; | |
882 | ||
3f518509 MW |
883 | phy_interface_t phy_interface; |
884 | struct device_node *phy_node; | |
542897d9 | 885 | struct phy *comphy; |
3f518509 MW |
886 | unsigned int link; |
887 | unsigned int duplex; | |
888 | unsigned int speed; | |
889 | ||
890 | struct mvpp2_bm_pool *pool_long; | |
891 | struct mvpp2_bm_pool *pool_short; | |
892 | ||
893 | /* Index of first port's physical RXQ */ | |
894 | u8 first_rxq; | |
591f4cfa TP |
895 | |
896 | struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; | |
897 | unsigned int nqvecs; | |
213f428f TP |
898 | bool has_tx_irqs; |
899 | ||
900 | u32 tx_time_coal; | |
3f518509 MW |
901 | }; |
902 | ||
903 | /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the | |
904 | * layout of the transmit and reception DMA descriptors, and their | |
905 | * layout is therefore defined by the hardware design | |
906 | */ | |
907 | ||
908 | #define MVPP2_TXD_L3_OFF_SHIFT 0 | |
909 | #define MVPP2_TXD_IP_HLEN_SHIFT 8 | |
910 | #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) | |
911 | #define MVPP2_TXD_L4_CSUM_NOT BIT(14) | |
912 | #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) | |
913 | #define MVPP2_TXD_PADDING_DISABLE BIT(23) | |
914 | #define MVPP2_TXD_L4_UDP BIT(24) | |
915 | #define MVPP2_TXD_L3_IP6 BIT(26) | |
916 | #define MVPP2_TXD_L_DESC BIT(28) | |
917 | #define MVPP2_TXD_F_DESC BIT(29) | |
918 | ||
919 | #define MVPP2_RXD_ERR_SUMMARY BIT(15) | |
920 | #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) | |
921 | #define MVPP2_RXD_ERR_CRC 0x0 | |
922 | #define MVPP2_RXD_ERR_OVERRUN BIT(13) | |
923 | #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) | |
924 | #define MVPP2_RXD_BM_POOL_ID_OFFS 16 | |
925 | #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) | |
926 | #define MVPP2_RXD_HWF_SYNC BIT(21) | |
927 | #define MVPP2_RXD_L4_CSUM_OK BIT(22) | |
928 | #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) | |
929 | #define MVPP2_RXD_L4_TCP BIT(25) | |
930 | #define MVPP2_RXD_L4_UDP BIT(26) | |
931 | #define MVPP2_RXD_L3_IP4 BIT(28) | |
932 | #define MVPP2_RXD_L3_IP6 BIT(30) | |
933 | #define MVPP2_RXD_BUF_HDR BIT(31) | |
934 | ||
054f6372 TP |
935 | /* HW TX descriptor for PPv2.1 */ |
936 | struct mvpp21_tx_desc { | |
3f518509 MW |
937 | u32 command; /* Options used by HW for packet transmitting.*/ |
938 | u8 packet_offset; /* the offset from the buffer beginning */ | |
939 | u8 phys_txq; /* destination queue ID */ | |
940 | u16 data_size; /* data size of transmitted packet in bytes */ | |
20396136 | 941 | u32 buf_dma_addr; /* physical addr of transmitted buffer */ |
3f518509 MW |
942 | u32 buf_cookie; /* cookie for access to TX buffer in tx path */ |
943 | u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ | |
944 | u32 reserved2; /* reserved (for future use) */ | |
945 | }; | |
946 | ||
054f6372 TP |
947 | /* HW RX descriptor for PPv2.1 */ |
948 | struct mvpp21_rx_desc { | |
3f518509 MW |
949 | u32 status; /* info about received packet */ |
950 | u16 reserved1; /* parser_info (for future use, PnC) */ | |
951 | u16 data_size; /* size of received packet in bytes */ | |
20396136 | 952 | u32 buf_dma_addr; /* physical address of the buffer */ |
3f518509 MW |
953 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
954 | u16 reserved2; /* gem_port_id (for future use, PON) */ | |
955 | u16 reserved3; /* csum_l4 (for future use, PnC) */ | |
956 | u8 reserved4; /* bm_qset (for future use, BM) */ | |
957 | u8 reserved5; | |
958 | u16 reserved6; /* classify_info (for future use, PnC) */ | |
959 | u32 reserved7; /* flow_id (for future use, PnC) */ | |
960 | u32 reserved8; | |
961 | }; | |
962 | ||
e7c5359f TP |
963 | /* HW TX descriptor for PPv2.2 */ |
964 | struct mvpp22_tx_desc { | |
965 | u32 command; | |
966 | u8 packet_offset; | |
967 | u8 phys_txq; | |
968 | u16 data_size; | |
969 | u64 reserved1; | |
970 | u64 buf_dma_addr_ptp; | |
971 | u64 buf_cookie_misc; | |
972 | }; | |
973 | ||
974 | /* HW RX descriptor for PPv2.2 */ | |
975 | struct mvpp22_rx_desc { | |
976 | u32 status; | |
977 | u16 reserved1; | |
978 | u16 data_size; | |
979 | u32 reserved2; | |
980 | u32 reserved3; | |
981 | u64 buf_dma_addr_key_hash; | |
982 | u64 buf_cookie_misc; | |
983 | }; | |
984 | ||
054f6372 TP |
985 | /* Opaque type used by the driver to manipulate the HW TX and RX |
986 | * descriptors | |
987 | */ | |
988 | struct mvpp2_tx_desc { | |
989 | union { | |
990 | struct mvpp21_tx_desc pp21; | |
e7c5359f | 991 | struct mvpp22_tx_desc pp22; |
054f6372 TP |
992 | }; |
993 | }; | |
994 | ||
995 | struct mvpp2_rx_desc { | |
996 | union { | |
997 | struct mvpp21_rx_desc pp21; | |
e7c5359f | 998 | struct mvpp22_rx_desc pp22; |
054f6372 TP |
999 | }; |
1000 | }; | |
1001 | ||
8354491c TP |
1002 | struct mvpp2_txq_pcpu_buf { |
1003 | /* Transmitted SKB */ | |
1004 | struct sk_buff *skb; | |
1005 | ||
1006 | /* Physical address of transmitted buffer */ | |
20396136 | 1007 | dma_addr_t dma; |
8354491c TP |
1008 | |
1009 | /* Size transmitted */ | |
1010 | size_t size; | |
1011 | }; | |
1012 | ||
3f518509 MW |
1013 | /* Per-CPU Tx queue control */ |
1014 | struct mvpp2_txq_pcpu { | |
1015 | int cpu; | |
1016 | ||
1017 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
1018 | int size; | |
1019 | ||
1020 | /* Number of currently used Tx DMA descriptor in the | |
1021 | * descriptor ring | |
1022 | */ | |
1023 | int count; | |
1024 | ||
1025 | /* Number of Tx DMA descriptors reserved for each CPU */ | |
1026 | int reserved_num; | |
1027 | ||
8354491c TP |
1028 | /* Infos about transmitted buffers */ |
1029 | struct mvpp2_txq_pcpu_buf *buffs; | |
71ce391d | 1030 | |
3f518509 MW |
1031 | /* Index of last TX DMA descriptor that was inserted */ |
1032 | int txq_put_index; | |
1033 | ||
1034 | /* Index of the TX DMA descriptor to be cleaned up */ | |
1035 | int txq_get_index; | |
186cd4d4 AT |
1036 | |
1037 | /* DMA buffer for TSO headers */ | |
1038 | char *tso_headers; | |
1039 | dma_addr_t tso_headers_dma; | |
3f518509 MW |
1040 | }; |
1041 | ||
1042 | struct mvpp2_tx_queue { | |
1043 | /* Physical number of this Tx queue */ | |
1044 | u8 id; | |
1045 | ||
1046 | /* Logical number of this Tx queue */ | |
1047 | u8 log_id; | |
1048 | ||
1049 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
1050 | int size; | |
1051 | ||
1052 | /* Number of currently used Tx DMA descriptor in the descriptor ring */ | |
1053 | int count; | |
1054 | ||
1055 | /* Per-CPU control of physical Tx queues */ | |
1056 | struct mvpp2_txq_pcpu __percpu *pcpu; | |
1057 | ||
3f518509 MW |
1058 | u32 done_pkts_coal; |
1059 | ||
1060 | /* Virtual address of thex Tx DMA descriptors array */ | |
1061 | struct mvpp2_tx_desc *descs; | |
1062 | ||
1063 | /* DMA address of the Tx DMA descriptors array */ | |
20396136 | 1064 | dma_addr_t descs_dma; |
3f518509 MW |
1065 | |
1066 | /* Index of the last Tx DMA descriptor */ | |
1067 | int last_desc; | |
1068 | ||
1069 | /* Index of the next Tx DMA descriptor to process */ | |
1070 | int next_desc_to_proc; | |
1071 | }; | |
1072 | ||
1073 | struct mvpp2_rx_queue { | |
1074 | /* RX queue number, in the range 0-31 for physical RXQs */ | |
1075 | u8 id; | |
1076 | ||
1077 | /* Num of rx descriptors in the rx descriptor ring */ | |
1078 | int size; | |
1079 | ||
1080 | u32 pkts_coal; | |
1081 | u32 time_coal; | |
1082 | ||
1083 | /* Virtual address of the RX DMA descriptors array */ | |
1084 | struct mvpp2_rx_desc *descs; | |
1085 | ||
1086 | /* DMA address of the RX DMA descriptors array */ | |
20396136 | 1087 | dma_addr_t descs_dma; |
3f518509 MW |
1088 | |
1089 | /* Index of the last RX DMA descriptor */ | |
1090 | int last_desc; | |
1091 | ||
1092 | /* Index of the next RX DMA descriptor to process */ | |
1093 | int next_desc_to_proc; | |
1094 | ||
1095 | /* ID of port to which physical RXQ is mapped */ | |
1096 | int port; | |
1097 | ||
1098 | /* Port's logic RXQ number to which physical RXQ is mapped */ | |
1099 | int logic_rxq; | |
1100 | }; | |
1101 | ||
1102 | union mvpp2_prs_tcam_entry { | |
1103 | u32 word[MVPP2_PRS_TCAM_WORDS]; | |
1104 | u8 byte[MVPP2_PRS_TCAM_WORDS * 4]; | |
1105 | }; | |
1106 | ||
1107 | union mvpp2_prs_sram_entry { | |
1108 | u32 word[MVPP2_PRS_SRAM_WORDS]; | |
1109 | u8 byte[MVPP2_PRS_SRAM_WORDS * 4]; | |
1110 | }; | |
1111 | ||
1112 | struct mvpp2_prs_entry { | |
1113 | u32 index; | |
1114 | union mvpp2_prs_tcam_entry tcam; | |
1115 | union mvpp2_prs_sram_entry sram; | |
1116 | }; | |
1117 | ||
1118 | struct mvpp2_prs_shadow { | |
1119 | bool valid; | |
1120 | bool finish; | |
1121 | ||
1122 | /* Lookup ID */ | |
1123 | int lu; | |
1124 | ||
1125 | /* User defined offset */ | |
1126 | int udf; | |
1127 | ||
1128 | /* Result info */ | |
1129 | u32 ri; | |
1130 | u32 ri_mask; | |
1131 | }; | |
1132 | ||
1133 | struct mvpp2_cls_flow_entry { | |
1134 | u32 index; | |
1135 | u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS]; | |
1136 | }; | |
1137 | ||
1138 | struct mvpp2_cls_lookup_entry { | |
1139 | u32 lkpid; | |
1140 | u32 way; | |
1141 | u32 data; | |
1142 | }; | |
1143 | ||
1144 | struct mvpp2_bm_pool { | |
1145 | /* Pool number in the range 0-7 */ | |
1146 | int id; | |
1147 | enum mvpp2_bm_type type; | |
1148 | ||
1149 | /* Buffer Pointers Pool External (BPPE) size */ | |
1150 | int size; | |
d01524d8 TP |
1151 | /* BPPE size in bytes */ |
1152 | int size_bytes; | |
3f518509 MW |
1153 | /* Number of buffers for this pool */ |
1154 | int buf_num; | |
1155 | /* Pool buffer size */ | |
1156 | int buf_size; | |
1157 | /* Packet size */ | |
1158 | int pkt_size; | |
0e037281 | 1159 | int frag_size; |
3f518509 MW |
1160 | |
1161 | /* BPPE virtual base address */ | |
1162 | u32 *virt_addr; | |
20396136 TP |
1163 | /* BPPE DMA base address */ |
1164 | dma_addr_t dma_addr; | |
3f518509 MW |
1165 | |
1166 | /* Ports using BM pool */ | |
1167 | u32 port_map; | |
3f518509 MW |
1168 | }; |
1169 | ||
213f428f TP |
1170 | /* Queue modes */ |
1171 | #define MVPP2_QDIST_SINGLE_MODE 0 | |
1172 | #define MVPP2_QDIST_MULTI_MODE 1 | |
1173 | ||
1174 | static int queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
1175 | ||
1176 | module_param(queue_mode, int, 0444); | |
1177 | MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); | |
1178 | ||
3f518509 MW |
1179 | #define MVPP2_DRIVER_NAME "mvpp2" |
1180 | #define MVPP2_DRIVER_VERSION "1.0" | |
1181 | ||
1182 | /* Utility/helper methods */ | |
1183 | ||
1184 | static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) | |
1185 | { | |
df089aa0 | 1186 | writel(data, priv->swth_base[0] + offset); |
3f518509 MW |
1187 | } |
1188 | ||
1189 | static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) | |
1190 | { | |
df089aa0 | 1191 | return readl(priv->swth_base[0] + offset); |
a786841d TP |
1192 | } |
1193 | ||
1194 | /* These accessors should be used to access: | |
1195 | * | |
1196 | * - per-CPU registers, where each CPU has its own copy of the | |
1197 | * register. | |
1198 | * | |
1199 | * MVPP2_BM_VIRT_ALLOC_REG | |
1200 | * MVPP2_BM_ADDR_HIGH_ALLOC | |
1201 | * MVPP22_BM_ADDR_HIGH_RLS_REG | |
1202 | * MVPP2_BM_VIRT_RLS_REG | |
1203 | * MVPP2_ISR_RX_TX_CAUSE_REG | |
1204 | * MVPP2_ISR_RX_TX_MASK_REG | |
1205 | * MVPP2_TXQ_NUM_REG | |
1206 | * MVPP2_AGGR_TXQ_UPDATE_REG | |
1207 | * MVPP2_TXQ_RSVD_REQ_REG | |
1208 | * MVPP2_TXQ_RSVD_RSLT_REG | |
1209 | * MVPP2_TXQ_SENT_REG | |
1210 | * MVPP2_RXQ_NUM_REG | |
1211 | * | |
1212 | * - global registers that must be accessed through a specific CPU | |
1213 | * window, because they are related to an access to a per-CPU | |
1214 | * register | |
1215 | * | |
1216 | * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) | |
1217 | * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) | |
1218 | * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) | |
1219 | * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) | |
1220 | * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) | |
1221 | * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) | |
1222 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1223 | * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) | |
1224 | * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) | |
1225 | * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) | |
1226 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1227 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1228 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1229 | */ | |
1230 | static void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, | |
1231 | u32 offset, u32 data) | |
1232 | { | |
df089aa0 | 1233 | writel(data, priv->swth_base[cpu] + offset); |
a786841d TP |
1234 | } |
1235 | ||
1236 | static u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, | |
1237 | u32 offset) | |
1238 | { | |
df089aa0 | 1239 | return readl(priv->swth_base[cpu] + offset); |
3f518509 MW |
1240 | } |
1241 | ||
ac3dd277 TP |
1242 | static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, |
1243 | struct mvpp2_tx_desc *tx_desc) | |
1244 | { | |
e7c5359f TP |
1245 | if (port->priv->hw_version == MVPP21) |
1246 | return tx_desc->pp21.buf_dma_addr; | |
1247 | else | |
1248 | return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1249 | } |
1250 | ||
1251 | static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, | |
1252 | struct mvpp2_tx_desc *tx_desc, | |
1253 | dma_addr_t dma_addr) | |
1254 | { | |
e7c5359f TP |
1255 | if (port->priv->hw_version == MVPP21) { |
1256 | tx_desc->pp21.buf_dma_addr = dma_addr; | |
1257 | } else { | |
1258 | u64 val = (u64)dma_addr; | |
1259 | ||
1260 | tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); | |
1261 | tx_desc->pp22.buf_dma_addr_ptp |= val; | |
1262 | } | |
ac3dd277 TP |
1263 | } |
1264 | ||
1265 | static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, | |
1266 | struct mvpp2_tx_desc *tx_desc) | |
1267 | { | |
e7c5359f TP |
1268 | if (port->priv->hw_version == MVPP21) |
1269 | return tx_desc->pp21.data_size; | |
1270 | else | |
1271 | return tx_desc->pp22.data_size; | |
ac3dd277 TP |
1272 | } |
1273 | ||
1274 | static void mvpp2_txdesc_size_set(struct mvpp2_port *port, | |
1275 | struct mvpp2_tx_desc *tx_desc, | |
1276 | size_t size) | |
1277 | { | |
e7c5359f TP |
1278 | if (port->priv->hw_version == MVPP21) |
1279 | tx_desc->pp21.data_size = size; | |
1280 | else | |
1281 | tx_desc->pp22.data_size = size; | |
ac3dd277 TP |
1282 | } |
1283 | ||
1284 | static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, | |
1285 | struct mvpp2_tx_desc *tx_desc, | |
1286 | unsigned int txq) | |
1287 | { | |
e7c5359f TP |
1288 | if (port->priv->hw_version == MVPP21) |
1289 | tx_desc->pp21.phys_txq = txq; | |
1290 | else | |
1291 | tx_desc->pp22.phys_txq = txq; | |
ac3dd277 TP |
1292 | } |
1293 | ||
1294 | static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, | |
1295 | struct mvpp2_tx_desc *tx_desc, | |
1296 | unsigned int command) | |
1297 | { | |
e7c5359f TP |
1298 | if (port->priv->hw_version == MVPP21) |
1299 | tx_desc->pp21.command = command; | |
1300 | else | |
1301 | tx_desc->pp22.command = command; | |
ac3dd277 TP |
1302 | } |
1303 | ||
1304 | static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, | |
1305 | struct mvpp2_tx_desc *tx_desc, | |
1306 | unsigned int offset) | |
1307 | { | |
e7c5359f TP |
1308 | if (port->priv->hw_version == MVPP21) |
1309 | tx_desc->pp21.packet_offset = offset; | |
1310 | else | |
1311 | tx_desc->pp22.packet_offset = offset; | |
ac3dd277 TP |
1312 | } |
1313 | ||
1314 | static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, | |
1315 | struct mvpp2_tx_desc *tx_desc) | |
1316 | { | |
e7c5359f TP |
1317 | if (port->priv->hw_version == MVPP21) |
1318 | return tx_desc->pp21.packet_offset; | |
1319 | else | |
1320 | return tx_desc->pp22.packet_offset; | |
ac3dd277 TP |
1321 | } |
1322 | ||
1323 | static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, | |
1324 | struct mvpp2_rx_desc *rx_desc) | |
1325 | { | |
e7c5359f TP |
1326 | if (port->priv->hw_version == MVPP21) |
1327 | return rx_desc->pp21.buf_dma_addr; | |
1328 | else | |
1329 | return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1330 | } |
1331 | ||
1332 | static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, | |
1333 | struct mvpp2_rx_desc *rx_desc) | |
1334 | { | |
e7c5359f TP |
1335 | if (port->priv->hw_version == MVPP21) |
1336 | return rx_desc->pp21.buf_cookie; | |
1337 | else | |
1338 | return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1339 | } |
1340 | ||
1341 | static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, | |
1342 | struct mvpp2_rx_desc *rx_desc) | |
1343 | { | |
e7c5359f TP |
1344 | if (port->priv->hw_version == MVPP21) |
1345 | return rx_desc->pp21.data_size; | |
1346 | else | |
1347 | return rx_desc->pp22.data_size; | |
ac3dd277 TP |
1348 | } |
1349 | ||
1350 | static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, | |
1351 | struct mvpp2_rx_desc *rx_desc) | |
1352 | { | |
e7c5359f TP |
1353 | if (port->priv->hw_version == MVPP21) |
1354 | return rx_desc->pp21.status; | |
1355 | else | |
1356 | return rx_desc->pp22.status; | |
ac3dd277 TP |
1357 | } |
1358 | ||
3f518509 MW |
1359 | static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) |
1360 | { | |
1361 | txq_pcpu->txq_get_index++; | |
1362 | if (txq_pcpu->txq_get_index == txq_pcpu->size) | |
1363 | txq_pcpu->txq_get_index = 0; | |
1364 | } | |
1365 | ||
ac3dd277 TP |
1366 | static void mvpp2_txq_inc_put(struct mvpp2_port *port, |
1367 | struct mvpp2_txq_pcpu *txq_pcpu, | |
71ce391d MW |
1368 | struct sk_buff *skb, |
1369 | struct mvpp2_tx_desc *tx_desc) | |
3f518509 | 1370 | { |
8354491c TP |
1371 | struct mvpp2_txq_pcpu_buf *tx_buf = |
1372 | txq_pcpu->buffs + txq_pcpu->txq_put_index; | |
1373 | tx_buf->skb = skb; | |
ac3dd277 TP |
1374 | tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); |
1375 | tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + | |
1376 | mvpp2_txdesc_offset_get(port, tx_desc); | |
3f518509 MW |
1377 | txq_pcpu->txq_put_index++; |
1378 | if (txq_pcpu->txq_put_index == txq_pcpu->size) | |
1379 | txq_pcpu->txq_put_index = 0; | |
1380 | } | |
1381 | ||
1382 | /* Get number of physical egress port */ | |
1383 | static inline int mvpp2_egress_port(struct mvpp2_port *port) | |
1384 | { | |
1385 | return MVPP2_MAX_TCONT + port->id; | |
1386 | } | |
1387 | ||
1388 | /* Get number of physical TXQ */ | |
1389 | static inline int mvpp2_txq_phys(int port, int txq) | |
1390 | { | |
1391 | return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; | |
1392 | } | |
1393 | ||
1394 | /* Parser configuration routines */ | |
1395 | ||
1396 | /* Update parser tcam and sram hw entries */ | |
1397 | static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1398 | { | |
1399 | int i; | |
1400 | ||
1401 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1402 | return -EINVAL; | |
1403 | ||
1404 | /* Clear entry invalidation bit */ | |
1405 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; | |
1406 | ||
1407 | /* Write tcam index - indirect access */ | |
1408 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1409 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1410 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); | |
1411 | ||
1412 | /* Write sram index - indirect access */ | |
1413 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1414 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1415 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | /* Read tcam entry from hw */ | |
1421 | static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1422 | { | |
1423 | int i; | |
1424 | ||
1425 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1426 | return -EINVAL; | |
1427 | ||
1428 | /* Write tcam index - indirect access */ | |
1429 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1430 | ||
1431 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, | |
1432 | MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD)); | |
1433 | if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) | |
1434 | return MVPP2_PRS_TCAM_ENTRY_INVALID; | |
1435 | ||
1436 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1437 | pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); | |
1438 | ||
1439 | /* Write sram index - indirect access */ | |
1440 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1441 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1442 | pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | /* Invalidate tcam hw entry */ | |
1448 | static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index) | |
1449 | { | |
1450 | /* Write index - indirect access */ | |
1451 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
1452 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), | |
1453 | MVPP2_PRS_TCAM_INV_MASK); | |
1454 | } | |
1455 | ||
1456 | /* Enable shadow table entry and set its lookup ID */ | |
1457 | static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) | |
1458 | { | |
1459 | priv->prs_shadow[index].valid = true; | |
1460 | priv->prs_shadow[index].lu = lu; | |
1461 | } | |
1462 | ||
1463 | /* Update ri fields in shadow table entry */ | |
1464 | static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index, | |
1465 | unsigned int ri, unsigned int ri_mask) | |
1466 | { | |
1467 | priv->prs_shadow[index].ri_mask = ri_mask; | |
1468 | priv->prs_shadow[index].ri = ri; | |
1469 | } | |
1470 | ||
1471 | /* Update lookup field in tcam sw entry */ | |
1472 | static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) | |
1473 | { | |
1474 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE); | |
1475 | ||
1476 | pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; | |
1477 | pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; | |
1478 | } | |
1479 | ||
1480 | /* Update mask for single port in tcam sw entry */ | |
1481 | static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, | |
1482 | unsigned int port, bool add) | |
1483 | { | |
1484 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1485 | ||
1486 | if (add) | |
1487 | pe->tcam.byte[enable_off] &= ~(1 << port); | |
1488 | else | |
1489 | pe->tcam.byte[enable_off] |= 1 << port; | |
1490 | } | |
1491 | ||
1492 | /* Update port map in tcam sw entry */ | |
1493 | static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, | |
1494 | unsigned int ports) | |
1495 | { | |
1496 | unsigned char port_mask = MVPP2_PRS_PORT_MASK; | |
1497 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1498 | ||
1499 | pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; | |
1500 | pe->tcam.byte[enable_off] &= ~port_mask; | |
1501 | pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; | |
1502 | } | |
1503 | ||
1504 | /* Obtain port map from tcam sw entry */ | |
1505 | static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) | |
1506 | { | |
1507 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1508 | ||
1509 | return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; | |
1510 | } | |
1511 | ||
1512 | /* Set byte of data and its enable bits in tcam sw entry */ | |
1513 | static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, | |
1514 | unsigned int offs, unsigned char byte, | |
1515 | unsigned char enable) | |
1516 | { | |
1517 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; | |
1518 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; | |
1519 | } | |
1520 | ||
1521 | /* Get byte of data and its enable bits from tcam sw entry */ | |
1522 | static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, | |
1523 | unsigned int offs, unsigned char *byte, | |
1524 | unsigned char *enable) | |
1525 | { | |
1526 | *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; | |
1527 | *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; | |
1528 | } | |
1529 | ||
1530 | /* Compare tcam data bytes with a pattern */ | |
1531 | static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, | |
1532 | u16 data) | |
1533 | { | |
1534 | int off = MVPP2_PRS_TCAM_DATA_BYTE(offs); | |
1535 | u16 tcam_data; | |
1536 | ||
1537 | tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off]; | |
1538 | if (tcam_data != data) | |
1539 | return false; | |
1540 | return true; | |
1541 | } | |
1542 | ||
1543 | /* Update ai bits in tcam sw entry */ | |
1544 | static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, | |
1545 | unsigned int bits, unsigned int enable) | |
1546 | { | |
1547 | int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE; | |
1548 | ||
1549 | for (i = 0; i < MVPP2_PRS_AI_BITS; i++) { | |
1550 | ||
1551 | if (!(enable & BIT(i))) | |
1552 | continue; | |
1553 | ||
1554 | if (bits & BIT(i)) | |
1555 | pe->tcam.byte[ai_idx] |= 1 << i; | |
1556 | else | |
1557 | pe->tcam.byte[ai_idx] &= ~(1 << i); | |
1558 | } | |
1559 | ||
1560 | pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; | |
1561 | } | |
1562 | ||
1563 | /* Get ai bits from tcam sw entry */ | |
1564 | static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) | |
1565 | { | |
1566 | return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; | |
1567 | } | |
1568 | ||
1569 | /* Set ethertype in tcam sw entry */ | |
1570 | static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, | |
1571 | unsigned short ethertype) | |
1572 | { | |
1573 | mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); | |
1574 | mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); | |
1575 | } | |
1576 | ||
1577 | /* Set bits in sram sw entry */ | |
1578 | static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, | |
1579 | int val) | |
1580 | { | |
1581 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); | |
1582 | } | |
1583 | ||
1584 | /* Clear bits in sram sw entry */ | |
1585 | static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, | |
1586 | int val) | |
1587 | { | |
1588 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); | |
1589 | } | |
1590 | ||
1591 | /* Update ri bits in sram sw entry */ | |
1592 | static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, | |
1593 | unsigned int bits, unsigned int mask) | |
1594 | { | |
1595 | unsigned int i; | |
1596 | ||
1597 | for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) { | |
1598 | int ri_off = MVPP2_PRS_SRAM_RI_OFFS; | |
1599 | ||
1600 | if (!(mask & BIT(i))) | |
1601 | continue; | |
1602 | ||
1603 | if (bits & BIT(i)) | |
1604 | mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); | |
1605 | else | |
1606 | mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); | |
1607 | ||
1608 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); | |
1609 | } | |
1610 | } | |
1611 | ||
1612 | /* Obtain ri bits from sram sw entry */ | |
1613 | static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) | |
1614 | { | |
1615 | return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; | |
1616 | } | |
1617 | ||
1618 | /* Update ai bits in sram sw entry */ | |
1619 | static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, | |
1620 | unsigned int bits, unsigned int mask) | |
1621 | { | |
1622 | unsigned int i; | |
1623 | int ai_off = MVPP2_PRS_SRAM_AI_OFFS; | |
1624 | ||
1625 | for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) { | |
1626 | ||
1627 | if (!(mask & BIT(i))) | |
1628 | continue; | |
1629 | ||
1630 | if (bits & BIT(i)) | |
1631 | mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); | |
1632 | else | |
1633 | mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); | |
1634 | ||
1635 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | /* Read ai bits from sram sw entry */ | |
1640 | static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) | |
1641 | { | |
1642 | u8 bits; | |
1643 | int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS); | |
1644 | int ai_en_off = ai_off + 1; | |
1645 | int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8; | |
1646 | ||
1647 | bits = (pe->sram.byte[ai_off] >> ai_shift) | | |
1648 | (pe->sram.byte[ai_en_off] << (8 - ai_shift)); | |
1649 | ||
1650 | return bits; | |
1651 | } | |
1652 | ||
1653 | /* In sram sw entry set lookup ID field of the tcam key to be used in the next | |
1654 | * lookup interation | |
1655 | */ | |
1656 | static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, | |
1657 | unsigned int lu) | |
1658 | { | |
1659 | int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS; | |
1660 | ||
1661 | mvpp2_prs_sram_bits_clear(pe, sram_next_off, | |
1662 | MVPP2_PRS_SRAM_NEXT_LU_MASK); | |
1663 | mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); | |
1664 | } | |
1665 | ||
1666 | /* In the sram sw entry set sign and value of the next lookup offset | |
1667 | * and the offset value generated to the classifier | |
1668 | */ | |
1669 | static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, | |
1670 | unsigned int op) | |
1671 | { | |
1672 | /* Set sign */ | |
1673 | if (shift < 0) { | |
1674 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1675 | shift = 0 - shift; | |
1676 | } else { | |
1677 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1678 | } | |
1679 | ||
1680 | /* Set value */ | |
1681 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = | |
1682 | (unsigned char)shift; | |
1683 | ||
1684 | /* Reset and set operation */ | |
1685 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, | |
1686 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK); | |
1687 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); | |
1688 | ||
1689 | /* Set base offset as current */ | |
1690 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1691 | } | |
1692 | ||
1693 | /* In the sram sw entry set sign and value of the user defined offset | |
1694 | * generated to the classifier | |
1695 | */ | |
1696 | static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, | |
1697 | unsigned int type, int offset, | |
1698 | unsigned int op) | |
1699 | { | |
1700 | /* Set sign */ | |
1701 | if (offset < 0) { | |
1702 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1703 | offset = 0 - offset; | |
1704 | } else { | |
1705 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1706 | } | |
1707 | ||
1708 | /* Set value */ | |
1709 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, | |
1710 | MVPP2_PRS_SRAM_UDF_MASK); | |
1711 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); | |
1712 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1713 | MVPP2_PRS_SRAM_UDF_BITS)] &= | |
1714 | ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1715 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1716 | MVPP2_PRS_SRAM_UDF_BITS)] |= | |
1717 | (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1718 | ||
1719 | /* Set offset type */ | |
1720 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, | |
1721 | MVPP2_PRS_SRAM_UDF_TYPE_MASK); | |
1722 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); | |
1723 | ||
1724 | /* Set offset operation */ | |
1725 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, | |
1726 | MVPP2_PRS_SRAM_OP_SEL_UDF_MASK); | |
1727 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); | |
1728 | ||
1729 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1730 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &= | |
1731 | ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >> | |
1732 | (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1733 | ||
1734 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1735 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |= | |
1736 | (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1737 | ||
1738 | /* Set base offset as current */ | |
1739 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1740 | } | |
1741 | ||
1742 | /* Find parser flow entry */ | |
1743 | static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow) | |
1744 | { | |
1745 | struct mvpp2_prs_entry *pe; | |
1746 | int tid; | |
1747 | ||
1748 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
1749 | if (!pe) | |
1750 | return NULL; | |
1751 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); | |
1752 | ||
1753 | /* Go through the all entires with MVPP2_PRS_LU_FLOWS */ | |
1754 | for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { | |
1755 | u8 bits; | |
1756 | ||
1757 | if (!priv->prs_shadow[tid].valid || | |
1758 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) | |
1759 | continue; | |
1760 | ||
1761 | pe->index = tid; | |
1762 | mvpp2_prs_hw_read(priv, pe); | |
1763 | bits = mvpp2_prs_sram_ai_get(pe); | |
1764 | ||
1765 | /* Sram store classification lookup ID in AI bits [5:0] */ | |
1766 | if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow) | |
1767 | return pe; | |
1768 | } | |
1769 | kfree(pe); | |
1770 | ||
1771 | return NULL; | |
1772 | } | |
1773 | ||
1774 | /* Return first free tcam index, seeking from start to end */ | |
1775 | static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, | |
1776 | unsigned char end) | |
1777 | { | |
1778 | int tid; | |
1779 | ||
1780 | if (start > end) | |
1781 | swap(start, end); | |
1782 | ||
1783 | if (end >= MVPP2_PRS_TCAM_SRAM_SIZE) | |
1784 | end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; | |
1785 | ||
1786 | for (tid = start; tid <= end; tid++) { | |
1787 | if (!priv->prs_shadow[tid].valid) | |
1788 | return tid; | |
1789 | } | |
1790 | ||
1791 | return -EINVAL; | |
1792 | } | |
1793 | ||
1794 | /* Enable/disable dropping all mac da's */ | |
1795 | static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) | |
1796 | { | |
1797 | struct mvpp2_prs_entry pe; | |
1798 | ||
1799 | if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { | |
1800 | /* Entry exist - update port only */ | |
1801 | pe.index = MVPP2_PE_DROP_ALL; | |
1802 | mvpp2_prs_hw_read(priv, &pe); | |
1803 | } else { | |
1804 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1805 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1806 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1807 | pe.index = MVPP2_PE_DROP_ALL; | |
1808 | ||
1809 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
1810 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
1811 | MVPP2_PRS_RI_DROP_MASK); | |
1812 | ||
1813 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
1814 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
1815 | ||
1816 | /* Update shadow table */ | |
1817 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1818 | ||
1819 | /* Mask all ports */ | |
1820 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1821 | } | |
1822 | ||
1823 | /* Update port mask */ | |
1824 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1825 | ||
1826 | mvpp2_prs_hw_write(priv, &pe); | |
1827 | } | |
1828 | ||
1829 | /* Set port to promiscuous mode */ | |
1830 | static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) | |
1831 | { | |
1832 | struct mvpp2_prs_entry pe; | |
1833 | ||
dbedd44e | 1834 | /* Promiscuous mode - Accept unknown packets */ |
3f518509 MW |
1835 | |
1836 | if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) { | |
1837 | /* Entry exist - update port only */ | |
1838 | pe.index = MVPP2_PE_MAC_PROMISCUOUS; | |
1839 | mvpp2_prs_hw_read(priv, &pe); | |
1840 | } else { | |
1841 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1842 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1843 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1844 | pe.index = MVPP2_PE_MAC_PROMISCUOUS; | |
1845 | ||
1846 | /* Continue - set next lookup */ | |
1847 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
1848 | ||
1849 | /* Set result info bits */ | |
1850 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, | |
1851 | MVPP2_PRS_RI_L2_CAST_MASK); | |
1852 | ||
1853 | /* Shift to ethertype */ | |
1854 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
1855 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1856 | ||
1857 | /* Mask all ports */ | |
1858 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1859 | ||
1860 | /* Update shadow table */ | |
1861 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1862 | } | |
1863 | ||
1864 | /* Update port mask */ | |
1865 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1866 | ||
1867 | mvpp2_prs_hw_write(priv, &pe); | |
1868 | } | |
1869 | ||
1870 | /* Accept multicast */ | |
1871 | static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, | |
1872 | bool add) | |
1873 | { | |
1874 | struct mvpp2_prs_entry pe; | |
1875 | unsigned char da_mc; | |
1876 | ||
1877 | /* Ethernet multicast address first byte is | |
1878 | * 0x01 for IPv4 and 0x33 for IPv6 | |
1879 | */ | |
1880 | da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33; | |
1881 | ||
1882 | if (priv->prs_shadow[index].valid) { | |
1883 | /* Entry exist - update port only */ | |
1884 | pe.index = index; | |
1885 | mvpp2_prs_hw_read(priv, &pe); | |
1886 | } else { | |
1887 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1888 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1889 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1890 | pe.index = index; | |
1891 | ||
1892 | /* Continue - set next lookup */ | |
1893 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
1894 | ||
1895 | /* Set result info bits */ | |
1896 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, | |
1897 | MVPP2_PRS_RI_L2_CAST_MASK); | |
1898 | ||
1899 | /* Update tcam entry data first byte */ | |
1900 | mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); | |
1901 | ||
1902 | /* Shift to ethertype */ | |
1903 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
1904 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1905 | ||
1906 | /* Mask all ports */ | |
1907 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1908 | ||
1909 | /* Update shadow table */ | |
1910 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1911 | } | |
1912 | ||
1913 | /* Update port mask */ | |
1914 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1915 | ||
1916 | mvpp2_prs_hw_write(priv, &pe); | |
1917 | } | |
1918 | ||
1919 | /* Set entry for dsa packets */ | |
1920 | static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add, | |
1921 | bool tagged, bool extend) | |
1922 | { | |
1923 | struct mvpp2_prs_entry pe; | |
1924 | int tid, shift; | |
1925 | ||
1926 | if (extend) { | |
1927 | tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED; | |
1928 | shift = 8; | |
1929 | } else { | |
1930 | tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED; | |
1931 | shift = 4; | |
1932 | } | |
1933 | ||
1934 | if (priv->prs_shadow[tid].valid) { | |
1935 | /* Entry exist - update port only */ | |
1936 | pe.index = tid; | |
1937 | mvpp2_prs_hw_read(priv, &pe); | |
1938 | } else { | |
1939 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1940 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1941 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
1942 | pe.index = tid; | |
1943 | ||
1944 | /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/ | |
1945 | mvpp2_prs_sram_shift_set(&pe, shift, | |
1946 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1947 | ||
1948 | /* Update shadow table */ | |
1949 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
1950 | ||
1951 | if (tagged) { | |
1952 | /* Set tagged bit in DSA tag */ | |
1953 | mvpp2_prs_tcam_data_byte_set(&pe, 0, | |
1954 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, | |
1955 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
1956 | /* Clear all ai bits for next iteration */ | |
1957 | mvpp2_prs_sram_ai_update(&pe, 0, | |
1958 | MVPP2_PRS_SRAM_AI_MASK); | |
1959 | /* If packet is tagged continue check vlans */ | |
1960 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
1961 | } else { | |
1962 | /* Set result info bits to 'no vlans' */ | |
1963 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
1964 | MVPP2_PRS_RI_VLAN_MASK); | |
1965 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
1966 | } | |
1967 | ||
1968 | /* Mask all ports */ | |
1969 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1970 | } | |
1971 | ||
1972 | /* Update port mask */ | |
1973 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1974 | ||
1975 | mvpp2_prs_hw_write(priv, &pe); | |
1976 | } | |
1977 | ||
1978 | /* Set entry for dsa ethertype */ | |
1979 | static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port, | |
1980 | bool add, bool tagged, bool extend) | |
1981 | { | |
1982 | struct mvpp2_prs_entry pe; | |
1983 | int tid, shift, port_mask; | |
1984 | ||
1985 | if (extend) { | |
1986 | tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED : | |
1987 | MVPP2_PE_ETYPE_EDSA_UNTAGGED; | |
1988 | port_mask = 0; | |
1989 | shift = 8; | |
1990 | } else { | |
1991 | tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED : | |
1992 | MVPP2_PE_ETYPE_DSA_UNTAGGED; | |
1993 | port_mask = MVPP2_PRS_PORT_MASK; | |
1994 | shift = 4; | |
1995 | } | |
1996 | ||
1997 | if (priv->prs_shadow[tid].valid) { | |
1998 | /* Entry exist - update port only */ | |
1999 | pe.index = tid; | |
2000 | mvpp2_prs_hw_read(priv, &pe); | |
2001 | } else { | |
2002 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2003 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2004 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2005 | pe.index = tid; | |
2006 | ||
2007 | /* Set ethertype */ | |
2008 | mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); | |
2009 | mvpp2_prs_match_etype(&pe, 2, 0); | |
2010 | ||
2011 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, | |
2012 | MVPP2_PRS_RI_DSA_MASK); | |
2013 | /* Shift ethertype + 2 byte reserved + tag*/ | |
2014 | mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, | |
2015 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2016 | ||
2017 | /* Update shadow table */ | |
2018 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
2019 | ||
2020 | if (tagged) { | |
2021 | /* Set tagged bit in DSA tag */ | |
2022 | mvpp2_prs_tcam_data_byte_set(&pe, | |
2023 | MVPP2_ETH_TYPE_LEN + 2 + 3, | |
2024 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, | |
2025 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
2026 | /* Clear all ai bits for next iteration */ | |
2027 | mvpp2_prs_sram_ai_update(&pe, 0, | |
2028 | MVPP2_PRS_SRAM_AI_MASK); | |
2029 | /* If packet is tagged continue check vlans */ | |
2030 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2031 | } else { | |
2032 | /* Set result info bits to 'no vlans' */ | |
2033 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2034 | MVPP2_PRS_RI_VLAN_MASK); | |
2035 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2036 | } | |
2037 | /* Mask/unmask all ports, depending on dsa type */ | |
2038 | mvpp2_prs_tcam_port_map_set(&pe, port_mask); | |
2039 | } | |
2040 | ||
2041 | /* Update port mask */ | |
2042 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2043 | ||
2044 | mvpp2_prs_hw_write(priv, &pe); | |
2045 | } | |
2046 | ||
2047 | /* Search for existing single/triple vlan entry */ | |
2048 | static struct mvpp2_prs_entry *mvpp2_prs_vlan_find(struct mvpp2 *priv, | |
2049 | unsigned short tpid, int ai) | |
2050 | { | |
2051 | struct mvpp2_prs_entry *pe; | |
2052 | int tid; | |
2053 | ||
2054 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2055 | if (!pe) | |
2056 | return NULL; | |
2057 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2058 | ||
2059 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ | |
2060 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2061 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2062 | unsigned int ri_bits, ai_bits; | |
2063 | bool match; | |
2064 | ||
2065 | if (!priv->prs_shadow[tid].valid || | |
2066 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2067 | continue; | |
2068 | ||
2069 | pe->index = tid; | |
2070 | ||
2071 | mvpp2_prs_hw_read(priv, pe); | |
2072 | match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid)); | |
2073 | if (!match) | |
2074 | continue; | |
2075 | ||
2076 | /* Get vlan type */ | |
2077 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2078 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; | |
2079 | ||
2080 | /* Get current ai value from tcam */ | |
2081 | ai_bits = mvpp2_prs_tcam_ai_get(pe); | |
2082 | /* Clear double vlan bit */ | |
2083 | ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2084 | ||
2085 | if (ai != ai_bits) | |
2086 | continue; | |
2087 | ||
2088 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2089 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2090 | return pe; | |
2091 | } | |
2092 | kfree(pe); | |
2093 | ||
2094 | return NULL; | |
2095 | } | |
2096 | ||
2097 | /* Add/update single/triple vlan entry */ | |
2098 | static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai, | |
2099 | unsigned int port_map) | |
2100 | { | |
2101 | struct mvpp2_prs_entry *pe; | |
2102 | int tid_aux, tid; | |
43737473 | 2103 | int ret = 0; |
3f518509 MW |
2104 | |
2105 | pe = mvpp2_prs_vlan_find(priv, tpid, ai); | |
2106 | ||
2107 | if (!pe) { | |
2108 | /* Create new tcam entry */ | |
2109 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID, | |
2110 | MVPP2_PE_FIRST_FREE_TID); | |
2111 | if (tid < 0) | |
2112 | return tid; | |
2113 | ||
2114 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2115 | if (!pe) | |
2116 | return -ENOMEM; | |
2117 | ||
2118 | /* Get last double vlan tid */ | |
2119 | for (tid_aux = MVPP2_PE_LAST_FREE_TID; | |
2120 | tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) { | |
2121 | unsigned int ri_bits; | |
2122 | ||
2123 | if (!priv->prs_shadow[tid_aux].valid || | |
2124 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2125 | continue; | |
2126 | ||
2127 | pe->index = tid_aux; | |
2128 | mvpp2_prs_hw_read(priv, pe); | |
2129 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2130 | if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) == | |
2131 | MVPP2_PRS_RI_VLAN_DOUBLE) | |
2132 | break; | |
2133 | } | |
2134 | ||
43737473 SM |
2135 | if (tid <= tid_aux) { |
2136 | ret = -EINVAL; | |
f9fd0e34 | 2137 | goto free_pe; |
43737473 | 2138 | } |
3f518509 | 2139 | |
bd6aaf55 | 2140 | memset(pe, 0, sizeof(*pe)); |
3f518509 MW |
2141 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); |
2142 | pe->index = tid; | |
2143 | ||
2144 | mvpp2_prs_match_etype(pe, 0, tpid); | |
2145 | ||
2146 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2); | |
2147 | /* Shift 4 bytes - skip 1 vlan tag */ | |
2148 | mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN, | |
2149 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2150 | /* Clear all ai bits for next iteration */ | |
2151 | mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2152 | ||
2153 | if (ai == MVPP2_PRS_SINGLE_VLAN_AI) { | |
2154 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE, | |
2155 | MVPP2_PRS_RI_VLAN_MASK); | |
2156 | } else { | |
2157 | ai |= MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2158 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE, | |
2159 | MVPP2_PRS_RI_VLAN_MASK); | |
2160 | } | |
2161 | mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK); | |
2162 | ||
2163 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); | |
2164 | } | |
2165 | /* Update ports' mask */ | |
2166 | mvpp2_prs_tcam_port_map_set(pe, port_map); | |
2167 | ||
2168 | mvpp2_prs_hw_write(priv, pe); | |
f9fd0e34 | 2169 | free_pe: |
3f518509 MW |
2170 | kfree(pe); |
2171 | ||
43737473 | 2172 | return ret; |
3f518509 MW |
2173 | } |
2174 | ||
2175 | /* Get first free double vlan ai number */ | |
2176 | static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv) | |
2177 | { | |
2178 | int i; | |
2179 | ||
2180 | for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) { | |
2181 | if (!priv->prs_double_vlans[i]) | |
2182 | return i; | |
2183 | } | |
2184 | ||
2185 | return -EINVAL; | |
2186 | } | |
2187 | ||
2188 | /* Search for existing double vlan entry */ | |
2189 | static struct mvpp2_prs_entry *mvpp2_prs_double_vlan_find(struct mvpp2 *priv, | |
2190 | unsigned short tpid1, | |
2191 | unsigned short tpid2) | |
2192 | { | |
2193 | struct mvpp2_prs_entry *pe; | |
2194 | int tid; | |
2195 | ||
2196 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2197 | if (!pe) | |
2198 | return NULL; | |
2199 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2200 | ||
2201 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ | |
2202 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2203 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2204 | unsigned int ri_mask; | |
2205 | bool match; | |
2206 | ||
2207 | if (!priv->prs_shadow[tid].valid || | |
2208 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2209 | continue; | |
2210 | ||
2211 | pe->index = tid; | |
2212 | mvpp2_prs_hw_read(priv, pe); | |
2213 | ||
2214 | match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1)) | |
2215 | && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2)); | |
2216 | ||
2217 | if (!match) | |
2218 | continue; | |
2219 | ||
2220 | ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK; | |
2221 | if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE) | |
2222 | return pe; | |
2223 | } | |
2224 | kfree(pe); | |
2225 | ||
2226 | return NULL; | |
2227 | } | |
2228 | ||
2229 | /* Add or update double vlan entry */ | |
2230 | static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1, | |
2231 | unsigned short tpid2, | |
2232 | unsigned int port_map) | |
2233 | { | |
2234 | struct mvpp2_prs_entry *pe; | |
43737473 | 2235 | int tid_aux, tid, ai, ret = 0; |
3f518509 MW |
2236 | |
2237 | pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); | |
2238 | ||
2239 | if (!pe) { | |
2240 | /* Create new tcam entry */ | |
2241 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2242 | MVPP2_PE_LAST_FREE_TID); | |
2243 | if (tid < 0) | |
2244 | return tid; | |
2245 | ||
2246 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2247 | if (!pe) | |
2248 | return -ENOMEM; | |
2249 | ||
2250 | /* Set ai value for new double vlan entry */ | |
2251 | ai = mvpp2_prs_double_vlan_ai_free_get(priv); | |
43737473 SM |
2252 | if (ai < 0) { |
2253 | ret = ai; | |
c9a7e120 | 2254 | goto free_pe; |
43737473 | 2255 | } |
3f518509 MW |
2256 | |
2257 | /* Get first single/triple vlan tid */ | |
2258 | for (tid_aux = MVPP2_PE_FIRST_FREE_TID; | |
2259 | tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) { | |
2260 | unsigned int ri_bits; | |
2261 | ||
2262 | if (!priv->prs_shadow[tid_aux].valid || | |
2263 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2264 | continue; | |
2265 | ||
2266 | pe->index = tid_aux; | |
2267 | mvpp2_prs_hw_read(priv, pe); | |
2268 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2269 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; | |
2270 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2271 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2272 | break; | |
2273 | } | |
2274 | ||
43737473 SM |
2275 | if (tid >= tid_aux) { |
2276 | ret = -ERANGE; | |
c9a7e120 | 2277 | goto free_pe; |
43737473 | 2278 | } |
3f518509 | 2279 | |
bd6aaf55 | 2280 | memset(pe, 0, sizeof(*pe)); |
3f518509 MW |
2281 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); |
2282 | pe->index = tid; | |
2283 | ||
2284 | priv->prs_double_vlans[ai] = true; | |
2285 | ||
2286 | mvpp2_prs_match_etype(pe, 0, tpid1); | |
2287 | mvpp2_prs_match_etype(pe, 4, tpid2); | |
2288 | ||
2289 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2290 | /* Shift 8 bytes - skip 2 vlan tags */ | |
2291 | mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN, | |
2292 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2293 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
2294 | MVPP2_PRS_RI_VLAN_MASK); | |
2295 | mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, | |
2296 | MVPP2_PRS_SRAM_AI_MASK); | |
2297 | ||
2298 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); | |
2299 | } | |
2300 | ||
2301 | /* Update ports' mask */ | |
2302 | mvpp2_prs_tcam_port_map_set(pe, port_map); | |
2303 | mvpp2_prs_hw_write(priv, pe); | |
c9a7e120 | 2304 | free_pe: |
3f518509 | 2305 | kfree(pe); |
43737473 | 2306 | return ret; |
3f518509 MW |
2307 | } |
2308 | ||
2309 | /* IPv4 header parsing for fragmentation and L4 offset */ | |
2310 | static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, | |
2311 | unsigned int ri, unsigned int ri_mask) | |
2312 | { | |
2313 | struct mvpp2_prs_entry pe; | |
2314 | int tid; | |
2315 | ||
2316 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2317 | (proto != IPPROTO_IGMP)) | |
2318 | return -EINVAL; | |
2319 | ||
aff3da39 | 2320 | /* Not fragmented packet */ |
3f518509 MW |
2321 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, |
2322 | MVPP2_PE_LAST_FREE_TID); | |
2323 | if (tid < 0) | |
2324 | return tid; | |
2325 | ||
c5b2ce24 | 2326 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2327 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2328 | pe.index = tid; | |
2329 | ||
2330 | /* Set next lu to IPv4 */ | |
2331 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2332 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2333 | /* Set L4 offset */ | |
2334 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2335 | sizeof(struct iphdr) - 4, | |
2336 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2337 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2338 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
aff3da39 SC |
2339 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); |
2340 | ||
2341 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, | |
2342 | MVPP2_PRS_TCAM_PROTO_MASK_L); | |
2343 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, | |
2344 | MVPP2_PRS_TCAM_PROTO_MASK); | |
3f518509 MW |
2345 | |
2346 | mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2347 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2348 | /* Unmask all ports */ | |
2349 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2350 | ||
2351 | /* Update shadow table and hw entry */ | |
2352 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2353 | mvpp2_prs_hw_write(priv, &pe); | |
2354 | ||
aff3da39 | 2355 | /* Fragmented packet */ |
3f518509 MW |
2356 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, |
2357 | MVPP2_PE_LAST_FREE_TID); | |
2358 | if (tid < 0) | |
2359 | return tid; | |
2360 | ||
2361 | pe.index = tid; | |
2362 | /* Clear ri before updating */ | |
2363 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2364 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2365 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2366 | ||
aff3da39 SC |
2367 | mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, |
2368 | ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); | |
2369 | ||
2370 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); | |
2371 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); | |
3f518509 MW |
2372 | |
2373 | /* Update shadow table and hw entry */ | |
2374 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2375 | mvpp2_prs_hw_write(priv, &pe); | |
2376 | ||
2377 | return 0; | |
2378 | } | |
2379 | ||
2380 | /* IPv4 L3 multicast or broadcast */ | |
2381 | static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2382 | { | |
2383 | struct mvpp2_prs_entry pe; | |
2384 | int mask, tid; | |
2385 | ||
2386 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2387 | MVPP2_PE_LAST_FREE_TID); | |
2388 | if (tid < 0) | |
2389 | return tid; | |
2390 | ||
c5b2ce24 | 2391 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2392 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2393 | pe.index = tid; | |
2394 | ||
2395 | switch (l3_cast) { | |
2396 | case MVPP2_PRS_L3_MULTI_CAST: | |
2397 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, | |
2398 | MVPP2_PRS_IPV4_MC_MASK); | |
2399 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2400 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2401 | break; | |
2402 | case MVPP2_PRS_L3_BROAD_CAST: | |
2403 | mask = MVPP2_PRS_IPV4_BC_MASK; | |
2404 | mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); | |
2405 | mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); | |
2406 | mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); | |
2407 | mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); | |
2408 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, | |
2409 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2410 | break; | |
2411 | default: | |
2412 | return -EINVAL; | |
2413 | } | |
2414 | ||
2415 | /* Finished: go to flowid generation */ | |
2416 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2417 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2418 | ||
2419 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2420 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2421 | /* Unmask all ports */ | |
2422 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2423 | ||
2424 | /* Update shadow table and hw entry */ | |
2425 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2426 | mvpp2_prs_hw_write(priv, &pe); | |
2427 | ||
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | /* Set entries for protocols over IPv6 */ | |
2432 | static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto, | |
2433 | unsigned int ri, unsigned int ri_mask) | |
2434 | { | |
2435 | struct mvpp2_prs_entry pe; | |
2436 | int tid; | |
2437 | ||
2438 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2439 | (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP)) | |
2440 | return -EINVAL; | |
2441 | ||
2442 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2443 | MVPP2_PE_LAST_FREE_TID); | |
2444 | if (tid < 0) | |
2445 | return tid; | |
2446 | ||
c5b2ce24 | 2447 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2448 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2449 | pe.index = tid; | |
2450 | ||
2451 | /* Finished: go to flowid generation */ | |
2452 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2453 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2454 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2455 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2456 | sizeof(struct ipv6hdr) - 6, | |
2457 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2458 | ||
2459 | mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2460 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2461 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2462 | /* Unmask all ports */ | |
2463 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2464 | ||
2465 | /* Write HW */ | |
2466 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2467 | mvpp2_prs_hw_write(priv, &pe); | |
2468 | ||
2469 | return 0; | |
2470 | } | |
2471 | ||
2472 | /* IPv6 L3 multicast entry */ | |
2473 | static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2474 | { | |
2475 | struct mvpp2_prs_entry pe; | |
2476 | int tid; | |
2477 | ||
2478 | if (l3_cast != MVPP2_PRS_L3_MULTI_CAST) | |
2479 | return -EINVAL; | |
2480 | ||
2481 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2482 | MVPP2_PE_LAST_FREE_TID); | |
2483 | if (tid < 0) | |
2484 | return tid; | |
2485 | ||
c5b2ce24 | 2486 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2487 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2488 | pe.index = tid; | |
2489 | ||
2490 | /* Finished: go to flowid generation */ | |
2491 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2492 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2493 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2494 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2495 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2496 | /* Shift back to IPv6 NH */ | |
2497 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2498 | ||
2499 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, | |
2500 | MVPP2_PRS_IPV6_MC_MASK); | |
2501 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2502 | /* Unmask all ports */ | |
2503 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2504 | ||
2505 | /* Update shadow table and hw entry */ | |
2506 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2507 | mvpp2_prs_hw_write(priv, &pe); | |
2508 | ||
2509 | return 0; | |
2510 | } | |
2511 | ||
2512 | /* Parser per-port initialization */ | |
2513 | static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, | |
2514 | int lu_max, int offset) | |
2515 | { | |
2516 | u32 val; | |
2517 | ||
2518 | /* Set lookup ID */ | |
2519 | val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG); | |
2520 | val &= ~MVPP2_PRS_PORT_LU_MASK(port); | |
2521 | val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); | |
2522 | mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); | |
2523 | ||
2524 | /* Set maximum number of loops for packet received from port */ | |
2525 | val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); | |
2526 | val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); | |
2527 | val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); | |
2528 | mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); | |
2529 | ||
2530 | /* Set initial offset for packet header extraction for the first | |
2531 | * searching loop | |
2532 | */ | |
2533 | val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); | |
2534 | val &= ~MVPP2_PRS_INIT_OFF_MASK(port); | |
2535 | val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); | |
2536 | mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); | |
2537 | } | |
2538 | ||
2539 | /* Default flow entries initialization for all ports */ | |
2540 | static void mvpp2_prs_def_flow_init(struct mvpp2 *priv) | |
2541 | { | |
2542 | struct mvpp2_prs_entry pe; | |
2543 | int port; | |
2544 | ||
2545 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
c5b2ce24 | 2546 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2547 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); |
2548 | pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; | |
2549 | ||
2550 | /* Mask all ports */ | |
2551 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2552 | ||
2553 | /* Set flow ID*/ | |
2554 | mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); | |
2555 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
2556 | ||
2557 | /* Update shadow table and hw entry */ | |
2558 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); | |
2559 | mvpp2_prs_hw_write(priv, &pe); | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | /* Set default entry for Marvell Header field */ | |
2564 | static void mvpp2_prs_mh_init(struct mvpp2 *priv) | |
2565 | { | |
2566 | struct mvpp2_prs_entry pe; | |
2567 | ||
c5b2ce24 | 2568 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2569 | |
2570 | pe.index = MVPP2_PE_MH_DEFAULT; | |
2571 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); | |
2572 | mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, | |
2573 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2574 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2575 | ||
2576 | /* Unmask all ports */ | |
2577 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2578 | ||
2579 | /* Update shadow table and hw entry */ | |
2580 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); | |
2581 | mvpp2_prs_hw_write(priv, &pe); | |
2582 | } | |
2583 | ||
2584 | /* Set default entires (place holder) for promiscuous, non-promiscuous and | |
2585 | * multicast MAC addresses | |
2586 | */ | |
2587 | static void mvpp2_prs_mac_init(struct mvpp2 *priv) | |
2588 | { | |
2589 | struct mvpp2_prs_entry pe; | |
2590 | ||
c5b2ce24 | 2591 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2592 | |
2593 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
2594 | pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; | |
2595 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2596 | ||
2597 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
2598 | MVPP2_PRS_RI_DROP_MASK); | |
2599 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2600 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2601 | ||
2602 | /* Unmask all ports */ | |
2603 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2604 | ||
2605 | /* Update shadow table and hw entry */ | |
2606 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2607 | mvpp2_prs_hw_write(priv, &pe); | |
2608 | ||
2609 | /* place holders only - no ports */ | |
2610 | mvpp2_prs_mac_drop_all_set(priv, 0, false); | |
2611 | mvpp2_prs_mac_promisc_set(priv, 0, false); | |
2612 | mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false); | |
2613 | mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false); | |
2614 | } | |
2615 | ||
2616 | /* Set default entries for various types of dsa packets */ | |
2617 | static void mvpp2_prs_dsa_init(struct mvpp2 *priv) | |
2618 | { | |
2619 | struct mvpp2_prs_entry pe; | |
2620 | ||
2621 | /* None tagged EDSA entry - place holder */ | |
2622 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2623 | MVPP2_PRS_EDSA); | |
2624 | ||
2625 | /* Tagged EDSA entry - place holder */ | |
2626 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2627 | ||
2628 | /* None tagged DSA entry - place holder */ | |
2629 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2630 | MVPP2_PRS_DSA); | |
2631 | ||
2632 | /* Tagged DSA entry - place holder */ | |
2633 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2634 | ||
2635 | /* None tagged EDSA ethertype entry - place holder*/ | |
2636 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2637 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
2638 | ||
2639 | /* Tagged EDSA ethertype entry - place holder*/ | |
2640 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2641 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2642 | ||
2643 | /* None tagged DSA ethertype entry */ | |
2644 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2645 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
2646 | ||
2647 | /* Tagged DSA ethertype entry */ | |
2648 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2649 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2650 | ||
2651 | /* Set default entry, in case DSA or EDSA tag not found */ | |
c5b2ce24 | 2652 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2653 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2654 | pe.index = MVPP2_PE_DSA_DEFAULT; | |
2655 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2656 | ||
2657 | /* Shift 0 bytes */ | |
2658 | mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2659 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2660 | ||
2661 | /* Clear all sram ai bits for next iteration */ | |
2662 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2663 | ||
2664 | /* Unmask all ports */ | |
2665 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2666 | ||
2667 | mvpp2_prs_hw_write(priv, &pe); | |
2668 | } | |
2669 | ||
2670 | /* Match basic ethertypes */ | |
2671 | static int mvpp2_prs_etype_init(struct mvpp2 *priv) | |
2672 | { | |
2673 | struct mvpp2_prs_entry pe; | |
2674 | int tid; | |
2675 | ||
2676 | /* Ethertype: PPPoE */ | |
2677 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2678 | MVPP2_PE_LAST_FREE_TID); | |
2679 | if (tid < 0) | |
2680 | return tid; | |
2681 | ||
c5b2ce24 | 2682 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2683 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2684 | pe.index = tid; | |
2685 | ||
2686 | mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); | |
2687 | ||
2688 | mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, | |
2689 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2690 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); | |
2691 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, | |
2692 | MVPP2_PRS_RI_PPPOE_MASK); | |
2693 | ||
2694 | /* Update shadow table and hw entry */ | |
2695 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2696 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2697 | priv->prs_shadow[pe.index].finish = false; | |
2698 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, | |
2699 | MVPP2_PRS_RI_PPPOE_MASK); | |
2700 | mvpp2_prs_hw_write(priv, &pe); | |
2701 | ||
2702 | /* Ethertype: ARP */ | |
2703 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2704 | MVPP2_PE_LAST_FREE_TID); | |
2705 | if (tid < 0) | |
2706 | return tid; | |
2707 | ||
c5b2ce24 | 2708 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2709 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2710 | pe.index = tid; | |
2711 | ||
2712 | mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); | |
2713 | ||
2714 | /* Generate flow in the next iteration*/ | |
2715 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2716 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2717 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, | |
2718 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2719 | /* Set L3 offset */ | |
2720 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2721 | MVPP2_ETH_TYPE_LEN, | |
2722 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2723 | ||
2724 | /* Update shadow table and hw entry */ | |
2725 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2726 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2727 | priv->prs_shadow[pe.index].finish = true; | |
2728 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, | |
2729 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2730 | mvpp2_prs_hw_write(priv, &pe); | |
2731 | ||
2732 | /* Ethertype: LBTD */ | |
2733 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2734 | MVPP2_PE_LAST_FREE_TID); | |
2735 | if (tid < 0) | |
2736 | return tid; | |
2737 | ||
c5b2ce24 | 2738 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2739 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2740 | pe.index = tid; | |
2741 | ||
2742 | mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); | |
2743 | ||
2744 | /* Generate flow in the next iteration*/ | |
2745 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2746 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2747 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2748 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2749 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2750 | MVPP2_PRS_RI_UDF3_MASK); | |
2751 | /* Set L3 offset */ | |
2752 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2753 | MVPP2_ETH_TYPE_LEN, | |
2754 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2755 | ||
2756 | /* Update shadow table and hw entry */ | |
2757 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2758 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2759 | priv->prs_shadow[pe.index].finish = true; | |
2760 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2761 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2762 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2763 | MVPP2_PRS_RI_UDF3_MASK); | |
2764 | mvpp2_prs_hw_write(priv, &pe); | |
2765 | ||
2766 | /* Ethertype: IPv4 without options */ | |
2767 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2768 | MVPP2_PE_LAST_FREE_TID); | |
2769 | if (tid < 0) | |
2770 | return tid; | |
2771 | ||
c5b2ce24 | 2772 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2773 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2774 | pe.index = tid; | |
2775 | ||
2776 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); | |
2777 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2778 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
2779 | MVPP2_PRS_IPV4_HEAD_MASK | | |
2780 | MVPP2_PRS_IPV4_IHL_MASK); | |
2781 | ||
2782 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2783 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
2784 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2785 | /* Skip eth_type + 4 bytes of IP header */ | |
2786 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2787 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2788 | /* Set L3 offset */ | |
2789 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2790 | MVPP2_ETH_TYPE_LEN, | |
2791 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2792 | ||
2793 | /* Update shadow table and hw entry */ | |
2794 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2795 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2796 | priv->prs_shadow[pe.index].finish = false; | |
2797 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, | |
2798 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2799 | mvpp2_prs_hw_write(priv, &pe); | |
2800 | ||
2801 | /* Ethertype: IPv4 with options */ | |
2802 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2803 | MVPP2_PE_LAST_FREE_TID); | |
2804 | if (tid < 0) | |
2805 | return tid; | |
2806 | ||
2807 | pe.index = tid; | |
2808 | ||
2809 | /* Clear tcam data before updating */ | |
2810 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
2811 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
2812 | ||
2813 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2814 | MVPP2_PRS_IPV4_HEAD, | |
2815 | MVPP2_PRS_IPV4_HEAD_MASK); | |
2816 | ||
2817 | /* Clear ri before updating */ | |
2818 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2819 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2820 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
2821 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2822 | ||
2823 | /* Update shadow table and hw entry */ | |
2824 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2825 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2826 | priv->prs_shadow[pe.index].finish = false; | |
2827 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, | |
2828 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2829 | mvpp2_prs_hw_write(priv, &pe); | |
2830 | ||
2831 | /* Ethertype: IPv6 without options */ | |
2832 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2833 | MVPP2_PE_LAST_FREE_TID); | |
2834 | if (tid < 0) | |
2835 | return tid; | |
2836 | ||
c5b2ce24 | 2837 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2838 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2839 | pe.index = tid; | |
2840 | ||
2841 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); | |
2842 | ||
2843 | /* Skip DIP of IPV6 header */ | |
2844 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + | |
2845 | MVPP2_MAX_L3_ADDR_SIZE, | |
2846 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2847 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2848 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
2849 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2850 | /* Set L3 offset */ | |
2851 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2852 | MVPP2_ETH_TYPE_LEN, | |
2853 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2854 | ||
2855 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2856 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2857 | priv->prs_shadow[pe.index].finish = false; | |
2858 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, | |
2859 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2860 | mvpp2_prs_hw_write(priv, &pe); | |
2861 | ||
2862 | /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ | |
2863 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
2864 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2865 | pe.index = MVPP2_PE_ETH_TYPE_UN; | |
2866 | ||
2867 | /* Unmask all ports */ | |
2868 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2869 | ||
2870 | /* Generate flow in the next iteration*/ | |
2871 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2872 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2873 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
2874 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2875 | /* Set L3 offset even it's unknown L3 */ | |
2876 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2877 | MVPP2_ETH_TYPE_LEN, | |
2878 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2879 | ||
2880 | /* Update shadow table and hw entry */ | |
2881 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2882 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2883 | priv->prs_shadow[pe.index].finish = true; | |
2884 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, | |
2885 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2886 | mvpp2_prs_hw_write(priv, &pe); | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | /* Configure vlan entries and detect up to 2 successive VLAN tags. | |
2892 | * Possible options: | |
2893 | * 0x8100, 0x88A8 | |
2894 | * 0x8100, 0x8100 | |
2895 | * 0x8100 | |
2896 | * 0x88A8 | |
2897 | */ | |
2898 | static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv) | |
2899 | { | |
2900 | struct mvpp2_prs_entry pe; | |
2901 | int err; | |
2902 | ||
2903 | priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool), | |
2904 | MVPP2_PRS_DBL_VLANS_MAX, | |
2905 | GFP_KERNEL); | |
2906 | if (!priv->prs_double_vlans) | |
2907 | return -ENOMEM; | |
2908 | ||
2909 | /* Double VLAN: 0x8100, 0x88A8 */ | |
2910 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD, | |
2911 | MVPP2_PRS_PORT_MASK); | |
2912 | if (err) | |
2913 | return err; | |
2914 | ||
2915 | /* Double VLAN: 0x8100, 0x8100 */ | |
2916 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q, | |
2917 | MVPP2_PRS_PORT_MASK); | |
2918 | if (err) | |
2919 | return err; | |
2920 | ||
2921 | /* Single VLAN: 0x88a8 */ | |
2922 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI, | |
2923 | MVPP2_PRS_PORT_MASK); | |
2924 | if (err) | |
2925 | return err; | |
2926 | ||
2927 | /* Single VLAN: 0x8100 */ | |
2928 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI, | |
2929 | MVPP2_PRS_PORT_MASK); | |
2930 | if (err) | |
2931 | return err; | |
2932 | ||
2933 | /* Set default double vlan entry */ | |
c5b2ce24 | 2934 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2935 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
2936 | pe.index = MVPP2_PE_VLAN_DBL; | |
2937 | ||
2938 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2939 | /* Clear ai for next iterations */ | |
2940 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2941 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
2942 | MVPP2_PRS_RI_VLAN_MASK); | |
2943 | ||
2944 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, | |
2945 | MVPP2_PRS_DBL_VLAN_AI_BIT); | |
2946 | /* Unmask all ports */ | |
2947 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2948 | ||
2949 | /* Update shadow table and hw entry */ | |
2950 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
2951 | mvpp2_prs_hw_write(priv, &pe); | |
2952 | ||
2953 | /* Set default vlan none entry */ | |
c5b2ce24 | 2954 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2955 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
2956 | pe.index = MVPP2_PE_VLAN_NONE; | |
2957 | ||
2958 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2959 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2960 | MVPP2_PRS_RI_VLAN_MASK); | |
2961 | ||
2962 | /* Unmask all ports */ | |
2963 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2964 | ||
2965 | /* Update shadow table and hw entry */ | |
2966 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
2967 | mvpp2_prs_hw_write(priv, &pe); | |
2968 | ||
2969 | return 0; | |
2970 | } | |
2971 | ||
2972 | /* Set entries for PPPoE ethertype */ | |
2973 | static int mvpp2_prs_pppoe_init(struct mvpp2 *priv) | |
2974 | { | |
2975 | struct mvpp2_prs_entry pe; | |
2976 | int tid; | |
2977 | ||
2978 | /* IPv4 over PPPoE with options */ | |
2979 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2980 | MVPP2_PE_LAST_FREE_TID); | |
2981 | if (tid < 0) | |
2982 | return tid; | |
2983 | ||
c5b2ce24 | 2984 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2985 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
2986 | pe.index = tid; | |
2987 | ||
2988 | mvpp2_prs_match_etype(&pe, 0, PPP_IP); | |
2989 | ||
2990 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2991 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
2992 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2993 | /* Skip eth_type + 4 bytes of IP header */ | |
2994 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2995 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2996 | /* Set L3 offset */ | |
2997 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2998 | MVPP2_ETH_TYPE_LEN, | |
2999 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3000 | ||
3001 | /* Update shadow table and hw entry */ | |
3002 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3003 | mvpp2_prs_hw_write(priv, &pe); | |
3004 | ||
3005 | /* IPv4 over PPPoE without options */ | |
3006 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3007 | MVPP2_PE_LAST_FREE_TID); | |
3008 | if (tid < 0) | |
3009 | return tid; | |
3010 | ||
3011 | pe.index = tid; | |
3012 | ||
3013 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
3014 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
3015 | MVPP2_PRS_IPV4_HEAD_MASK | | |
3016 | MVPP2_PRS_IPV4_IHL_MASK); | |
3017 | ||
3018 | /* Clear ri before updating */ | |
3019 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
3020 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
3021 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
3022 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3023 | ||
3024 | /* Update shadow table and hw entry */ | |
3025 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3026 | mvpp2_prs_hw_write(priv, &pe); | |
3027 | ||
3028 | /* IPv6 over PPPoE */ | |
3029 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3030 | MVPP2_PE_LAST_FREE_TID); | |
3031 | if (tid < 0) | |
3032 | return tid; | |
3033 | ||
c5b2ce24 | 3034 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3035 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3036 | pe.index = tid; | |
3037 | ||
3038 | mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); | |
3039 | ||
3040 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3041 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
3042 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3043 | /* Skip eth_type + 4 bytes of IPv6 header */ | |
3044 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
3045 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3046 | /* Set L3 offset */ | |
3047 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3048 | MVPP2_ETH_TYPE_LEN, | |
3049 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3050 | ||
3051 | /* Update shadow table and hw entry */ | |
3052 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3053 | mvpp2_prs_hw_write(priv, &pe); | |
3054 | ||
3055 | /* Non-IP over PPPoE */ | |
3056 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3057 | MVPP2_PE_LAST_FREE_TID); | |
3058 | if (tid < 0) | |
3059 | return tid; | |
3060 | ||
c5b2ce24 | 3061 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3062 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3063 | pe.index = tid; | |
3064 | ||
3065 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
3066 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3067 | ||
3068 | /* Finished: go to flowid generation */ | |
3069 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3070 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3071 | /* Set L3 offset even if it's unknown L3 */ | |
3072 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3073 | MVPP2_ETH_TYPE_LEN, | |
3074 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3075 | ||
3076 | /* Update shadow table and hw entry */ | |
3077 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3078 | mvpp2_prs_hw_write(priv, &pe); | |
3079 | ||
3080 | return 0; | |
3081 | } | |
3082 | ||
3083 | /* Initialize entries for IPv4 */ | |
3084 | static int mvpp2_prs_ip4_init(struct mvpp2 *priv) | |
3085 | { | |
3086 | struct mvpp2_prs_entry pe; | |
3087 | int err; | |
3088 | ||
3089 | /* Set entries for TCP, UDP and IGMP over IPv4 */ | |
3090 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP, | |
3091 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3092 | if (err) | |
3093 | return err; | |
3094 | ||
3095 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP, | |
3096 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3097 | if (err) | |
3098 | return err; | |
3099 | ||
3100 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP, | |
3101 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3102 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3103 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3104 | MVPP2_PRS_RI_UDF3_MASK); | |
3105 | if (err) | |
3106 | return err; | |
3107 | ||
3108 | /* IPv4 Broadcast */ | |
3109 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST); | |
3110 | if (err) | |
3111 | return err; | |
3112 | ||
3113 | /* IPv4 Multicast */ | |
3114 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3115 | if (err) | |
3116 | return err; | |
3117 | ||
3118 | /* Default IPv4 entry for unknown protocols */ | |
c5b2ce24 | 3119 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3120 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3121 | pe.index = MVPP2_PE_IP4_PROTO_UN; | |
3122 | ||
3123 | /* Set next lu to IPv4 */ | |
3124 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
3125 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3126 | /* Set L4 offset */ | |
3127 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3128 | sizeof(struct iphdr) - 4, | |
3129 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3130 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3131 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3132 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3133 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3134 | ||
3135 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3136 | /* Unmask all ports */ | |
3137 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3138 | ||
3139 | /* Update shadow table and hw entry */ | |
3140 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3141 | mvpp2_prs_hw_write(priv, &pe); | |
3142 | ||
3143 | /* Default IPv4 entry for unicast address */ | |
c5b2ce24 | 3144 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3145 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3146 | pe.index = MVPP2_PE_IP4_ADDR_UN; | |
3147 | ||
3148 | /* Finished: go to flowid generation */ | |
3149 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3150 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3151 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3152 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3153 | ||
3154 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3155 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3156 | /* Unmask all ports */ | |
3157 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3158 | ||
3159 | /* Update shadow table and hw entry */ | |
3160 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3161 | mvpp2_prs_hw_write(priv, &pe); | |
3162 | ||
3163 | return 0; | |
3164 | } | |
3165 | ||
3166 | /* Initialize entries for IPv6 */ | |
3167 | static int mvpp2_prs_ip6_init(struct mvpp2 *priv) | |
3168 | { | |
3169 | struct mvpp2_prs_entry pe; | |
3170 | int tid, err; | |
3171 | ||
3172 | /* Set entries for TCP, UDP and ICMP over IPv6 */ | |
3173 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP, | |
3174 | MVPP2_PRS_RI_L4_TCP, | |
3175 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3176 | if (err) | |
3177 | return err; | |
3178 | ||
3179 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP, | |
3180 | MVPP2_PRS_RI_L4_UDP, | |
3181 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3182 | if (err) | |
3183 | return err; | |
3184 | ||
3185 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6, | |
3186 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3187 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3188 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3189 | MVPP2_PRS_RI_UDF3_MASK); | |
3190 | if (err) | |
3191 | return err; | |
3192 | ||
3193 | /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */ | |
3194 | /* Result Info: UDF7=1, DS lite */ | |
3195 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP, | |
3196 | MVPP2_PRS_RI_UDF7_IP6_LITE, | |
3197 | MVPP2_PRS_RI_UDF7_MASK); | |
3198 | if (err) | |
3199 | return err; | |
3200 | ||
3201 | /* IPv6 multicast */ | |
3202 | err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3203 | if (err) | |
3204 | return err; | |
3205 | ||
3206 | /* Entry for checking hop limit */ | |
3207 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3208 | MVPP2_PE_LAST_FREE_TID); | |
3209 | if (tid < 0) | |
3210 | return tid; | |
3211 | ||
c5b2ce24 | 3212 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3213 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3214 | pe.index = tid; | |
3215 | ||
3216 | /* Finished: go to flowid generation */ | |
3217 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3218 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3219 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | | |
3220 | MVPP2_PRS_RI_DROP_MASK, | |
3221 | MVPP2_PRS_RI_L3_PROTO_MASK | | |
3222 | MVPP2_PRS_RI_DROP_MASK); | |
3223 | ||
3224 | mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); | |
3225 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3226 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3227 | ||
3228 | /* Update shadow table and hw entry */ | |
3229 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3230 | mvpp2_prs_hw_write(priv, &pe); | |
3231 | ||
3232 | /* Default IPv6 entry for unknown protocols */ | |
c5b2ce24 | 3233 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3234 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3235 | pe.index = MVPP2_PE_IP6_PROTO_UN; | |
3236 | ||
3237 | /* Finished: go to flowid generation */ | |
3238 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3239 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3240 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3241 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3242 | /* Set L4 offset relatively to our current place */ | |
3243 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3244 | sizeof(struct ipv6hdr) - 4, | |
3245 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3246 | ||
3247 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3248 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3249 | /* Unmask all ports */ | |
3250 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3251 | ||
3252 | /* Update shadow table and hw entry */ | |
3253 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3254 | mvpp2_prs_hw_write(priv, &pe); | |
3255 | ||
3256 | /* Default IPv6 entry for unknown ext protocols */ | |
3257 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3258 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3259 | pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; | |
3260 | ||
3261 | /* Finished: go to flowid generation */ | |
3262 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3263 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3264 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3265 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3266 | ||
3267 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, | |
3268 | MVPP2_PRS_IPV6_EXT_AI_BIT); | |
3269 | /* Unmask all ports */ | |
3270 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3271 | ||
3272 | /* Update shadow table and hw entry */ | |
3273 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3274 | mvpp2_prs_hw_write(priv, &pe); | |
3275 | ||
3276 | /* Default IPv6 entry for unicast address */ | |
3277 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3278 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3279 | pe.index = MVPP2_PE_IP6_ADDR_UN; | |
3280 | ||
3281 | /* Finished: go to IPv6 again */ | |
3282 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3283 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3284 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3285 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3286 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3287 | /* Shift back to IPV6 NH */ | |
3288 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3289 | ||
3290 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3291 | /* Unmask all ports */ | |
3292 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3293 | ||
3294 | /* Update shadow table and hw entry */ | |
3295 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
3296 | mvpp2_prs_hw_write(priv, &pe); | |
3297 | ||
3298 | return 0; | |
3299 | } | |
3300 | ||
3301 | /* Parser default initialization */ | |
3302 | static int mvpp2_prs_default_init(struct platform_device *pdev, | |
3303 | struct mvpp2 *priv) | |
3304 | { | |
3305 | int err, index, i; | |
3306 | ||
3307 | /* Enable tcam table */ | |
3308 | mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK); | |
3309 | ||
3310 | /* Clear all tcam and sram entries */ | |
3311 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) { | |
3312 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
3313 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
3314 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0); | |
3315 | ||
3316 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); | |
3317 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
3318 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); | |
3319 | } | |
3320 | ||
3321 | /* Invalidate all tcam entries */ | |
3322 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) | |
3323 | mvpp2_prs_hw_inv(priv, index); | |
3324 | ||
3325 | priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE, | |
37df25e8 | 3326 | sizeof(*priv->prs_shadow), |
3f518509 MW |
3327 | GFP_KERNEL); |
3328 | if (!priv->prs_shadow) | |
3329 | return -ENOMEM; | |
3330 | ||
3331 | /* Always start from lookup = 0 */ | |
3332 | for (index = 0; index < MVPP2_MAX_PORTS; index++) | |
3333 | mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH, | |
3334 | MVPP2_PRS_PORT_LU_MAX, 0); | |
3335 | ||
3336 | mvpp2_prs_def_flow_init(priv); | |
3337 | ||
3338 | mvpp2_prs_mh_init(priv); | |
3339 | ||
3340 | mvpp2_prs_mac_init(priv); | |
3341 | ||
3342 | mvpp2_prs_dsa_init(priv); | |
3343 | ||
3344 | err = mvpp2_prs_etype_init(priv); | |
3345 | if (err) | |
3346 | return err; | |
3347 | ||
3348 | err = mvpp2_prs_vlan_init(pdev, priv); | |
3349 | if (err) | |
3350 | return err; | |
3351 | ||
3352 | err = mvpp2_prs_pppoe_init(priv); | |
3353 | if (err) | |
3354 | return err; | |
3355 | ||
3356 | err = mvpp2_prs_ip6_init(priv); | |
3357 | if (err) | |
3358 | return err; | |
3359 | ||
3360 | err = mvpp2_prs_ip4_init(priv); | |
3361 | if (err) | |
3362 | return err; | |
3363 | ||
3364 | return 0; | |
3365 | } | |
3366 | ||
3367 | /* Compare MAC DA with tcam entry data */ | |
3368 | static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, | |
3369 | const u8 *da, unsigned char *mask) | |
3370 | { | |
3371 | unsigned char tcam_byte, tcam_mask; | |
3372 | int index; | |
3373 | ||
3374 | for (index = 0; index < ETH_ALEN; index++) { | |
3375 | mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); | |
3376 | if (tcam_mask != mask[index]) | |
3377 | return false; | |
3378 | ||
3379 | if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) | |
3380 | return false; | |
3381 | } | |
3382 | ||
3383 | return true; | |
3384 | } | |
3385 | ||
3386 | /* Find tcam entry with matched pair <MAC DA, port> */ | |
3387 | static struct mvpp2_prs_entry * | |
3388 | mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da, | |
3389 | unsigned char *mask, int udf_type) | |
3390 | { | |
3391 | struct mvpp2_prs_entry *pe; | |
3392 | int tid; | |
3393 | ||
3394 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
3395 | if (!pe) | |
3396 | return NULL; | |
3397 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); | |
3398 | ||
3399 | /* Go through the all entires with MVPP2_PRS_LU_MAC */ | |
3400 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3401 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
3402 | unsigned int entry_pmap; | |
3403 | ||
3404 | if (!priv->prs_shadow[tid].valid || | |
3405 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3406 | (priv->prs_shadow[tid].udf != udf_type)) | |
3407 | continue; | |
3408 | ||
3409 | pe->index = tid; | |
3410 | mvpp2_prs_hw_read(priv, pe); | |
3411 | entry_pmap = mvpp2_prs_tcam_port_map_get(pe); | |
3412 | ||
3413 | if (mvpp2_prs_mac_range_equals(pe, da, mask) && | |
3414 | entry_pmap == pmap) | |
3415 | return pe; | |
3416 | } | |
3417 | kfree(pe); | |
3418 | ||
3419 | return NULL; | |
3420 | } | |
3421 | ||
3422 | /* Update parser's mac da entry */ | |
3423 | static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, | |
3424 | const u8 *da, bool add) | |
3425 | { | |
3426 | struct mvpp2_prs_entry *pe; | |
3427 | unsigned int pmap, len, ri; | |
3428 | unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
3429 | int tid; | |
3430 | ||
3431 | /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ | |
3432 | pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, | |
3433 | MVPP2_PRS_UDF_MAC_DEF); | |
3434 | ||
3435 | /* No such entry */ | |
3436 | if (!pe) { | |
3437 | if (!add) | |
3438 | return 0; | |
3439 | ||
3440 | /* Create new TCAM entry */ | |
3441 | /* Find first range mac entry*/ | |
3442 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3443 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) | |
3444 | if (priv->prs_shadow[tid].valid && | |
3445 | (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) && | |
3446 | (priv->prs_shadow[tid].udf == | |
3447 | MVPP2_PRS_UDF_MAC_RANGE)) | |
3448 | break; | |
3449 | ||
3450 | /* Go through the all entries from first to last */ | |
3451 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3452 | tid - 1); | |
3453 | if (tid < 0) | |
3454 | return tid; | |
3455 | ||
3456 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
3457 | if (!pe) | |
c2bb7bc5 | 3458 | return -ENOMEM; |
3f518509 MW |
3459 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); |
3460 | pe->index = tid; | |
3461 | ||
3462 | /* Mask all ports */ | |
3463 | mvpp2_prs_tcam_port_map_set(pe, 0); | |
3464 | } | |
3465 | ||
3466 | /* Update port mask */ | |
3467 | mvpp2_prs_tcam_port_set(pe, port, add); | |
3468 | ||
3469 | /* Invalidate the entry if no ports are left enabled */ | |
3470 | pmap = mvpp2_prs_tcam_port_map_get(pe); | |
3471 | if (pmap == 0) { | |
3472 | if (add) { | |
3473 | kfree(pe); | |
c2bb7bc5 | 3474 | return -EINVAL; |
3f518509 MW |
3475 | } |
3476 | mvpp2_prs_hw_inv(priv, pe->index); | |
3477 | priv->prs_shadow[pe->index].valid = false; | |
3478 | kfree(pe); | |
3479 | return 0; | |
3480 | } | |
3481 | ||
3482 | /* Continue - set next lookup */ | |
3483 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); | |
3484 | ||
3485 | /* Set match on DA */ | |
3486 | len = ETH_ALEN; | |
3487 | while (len--) | |
3488 | mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); | |
3489 | ||
3490 | /* Set result info bits */ | |
3491 | if (is_broadcast_ether_addr(da)) | |
3492 | ri = MVPP2_PRS_RI_L2_BCAST; | |
3493 | else if (is_multicast_ether_addr(da)) | |
3494 | ri = MVPP2_PRS_RI_L2_MCAST; | |
3495 | else | |
3496 | ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK; | |
3497 | ||
3498 | mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | | |
3499 | MVPP2_PRS_RI_MAC_ME_MASK); | |
3500 | mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | | |
3501 | MVPP2_PRS_RI_MAC_ME_MASK); | |
3502 | ||
3503 | /* Shift to ethertype */ | |
3504 | mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, | |
3505 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3506 | ||
3507 | /* Update shadow table and hw entry */ | |
3508 | priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; | |
3509 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); | |
3510 | mvpp2_prs_hw_write(priv, pe); | |
3511 | ||
3512 | kfree(pe); | |
3513 | ||
3514 | return 0; | |
3515 | } | |
3516 | ||
3517 | static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da) | |
3518 | { | |
3519 | struct mvpp2_port *port = netdev_priv(dev); | |
3520 | int err; | |
3521 | ||
3522 | /* Remove old parser entry */ | |
3523 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr, | |
3524 | false); | |
3525 | if (err) | |
3526 | return err; | |
3527 | ||
3528 | /* Add new parser entry */ | |
3529 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); | |
3530 | if (err) | |
3531 | return err; | |
3532 | ||
3533 | /* Set addr in the device */ | |
3534 | ether_addr_copy(dev->dev_addr, da); | |
3535 | ||
3536 | return 0; | |
3537 | } | |
3538 | ||
3539 | /* Delete all port's multicast simple (not range) entries */ | |
3540 | static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port) | |
3541 | { | |
3542 | struct mvpp2_prs_entry pe; | |
3543 | int index, tid; | |
3544 | ||
3545 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3546 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
3547 | unsigned char da[ETH_ALEN], da_mask[ETH_ALEN]; | |
3548 | ||
3549 | if (!priv->prs_shadow[tid].valid || | |
3550 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3551 | (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF)) | |
3552 | continue; | |
3553 | ||
3554 | /* Only simple mac entries */ | |
3555 | pe.index = tid; | |
3556 | mvpp2_prs_hw_read(priv, &pe); | |
3557 | ||
3558 | /* Read mac addr from entry */ | |
3559 | for (index = 0; index < ETH_ALEN; index++) | |
3560 | mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], | |
3561 | &da_mask[index]); | |
3562 | ||
3563 | if (is_multicast_ether_addr(da) && !is_broadcast_ether_addr(da)) | |
3564 | /* Delete this entry */ | |
3565 | mvpp2_prs_mac_da_accept(priv, port, da, false); | |
3566 | } | |
3567 | } | |
3568 | ||
3569 | static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type) | |
3570 | { | |
3571 | switch (type) { | |
3572 | case MVPP2_TAG_TYPE_EDSA: | |
3573 | /* Add port to EDSA entries */ | |
3574 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3575 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3576 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3577 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3578 | /* Remove port from DSA entries */ | |
3579 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3580 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3581 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3582 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3583 | break; | |
3584 | ||
3585 | case MVPP2_TAG_TYPE_DSA: | |
3586 | /* Add port to DSA entries */ | |
3587 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3588 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3589 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3590 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3591 | /* Remove port from EDSA entries */ | |
3592 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3593 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3594 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3595 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3596 | break; | |
3597 | ||
3598 | case MVPP2_TAG_TYPE_MH: | |
3599 | case MVPP2_TAG_TYPE_NONE: | |
3600 | /* Remove port form EDSA and DSA entries */ | |
3601 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3602 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3603 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3604 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3605 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3606 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3607 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3608 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3609 | break; | |
3610 | ||
3611 | default: | |
3612 | if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA)) | |
3613 | return -EINVAL; | |
3614 | } | |
3615 | ||
3616 | return 0; | |
3617 | } | |
3618 | ||
3619 | /* Set prs flow for the port */ | |
3620 | static int mvpp2_prs_def_flow(struct mvpp2_port *port) | |
3621 | { | |
3622 | struct mvpp2_prs_entry *pe; | |
3623 | int tid; | |
3624 | ||
3625 | pe = mvpp2_prs_flow_find(port->priv, port->id); | |
3626 | ||
3627 | /* Such entry not exist */ | |
3628 | if (!pe) { | |
3629 | /* Go through the all entires from last to first */ | |
3630 | tid = mvpp2_prs_tcam_first_free(port->priv, | |
3631 | MVPP2_PE_LAST_FREE_TID, | |
3632 | MVPP2_PE_FIRST_FREE_TID); | |
3633 | if (tid < 0) | |
3634 | return tid; | |
3635 | ||
3636 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
3637 | if (!pe) | |
3638 | return -ENOMEM; | |
3639 | ||
3640 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); | |
3641 | pe->index = tid; | |
3642 | ||
3643 | /* Set flow ID*/ | |
3644 | mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); | |
3645 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
3646 | ||
3647 | /* Update shadow table */ | |
3648 | mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); | |
3649 | } | |
3650 | ||
3651 | mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); | |
3652 | mvpp2_prs_hw_write(port->priv, pe); | |
3653 | kfree(pe); | |
3654 | ||
3655 | return 0; | |
3656 | } | |
3657 | ||
3658 | /* Classifier configuration routines */ | |
3659 | ||
3660 | /* Update classification flow table registers */ | |
3661 | static void mvpp2_cls_flow_write(struct mvpp2 *priv, | |
3662 | struct mvpp2_cls_flow_entry *fe) | |
3663 | { | |
3664 | mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); | |
3665 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); | |
3666 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); | |
3667 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); | |
3668 | } | |
3669 | ||
3670 | /* Update classification lookup table register */ | |
3671 | static void mvpp2_cls_lookup_write(struct mvpp2 *priv, | |
3672 | struct mvpp2_cls_lookup_entry *le) | |
3673 | { | |
3674 | u32 val; | |
3675 | ||
3676 | val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; | |
3677 | mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); | |
3678 | mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); | |
3679 | } | |
3680 | ||
3681 | /* Classifier default initialization */ | |
3682 | static void mvpp2_cls_init(struct mvpp2 *priv) | |
3683 | { | |
3684 | struct mvpp2_cls_lookup_entry le; | |
3685 | struct mvpp2_cls_flow_entry fe; | |
3686 | int index; | |
3687 | ||
3688 | /* Enable classifier */ | |
3689 | mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); | |
3690 | ||
3691 | /* Clear classifier flow table */ | |
e8f967c3 | 3692 | memset(&fe.data, 0, sizeof(fe.data)); |
3f518509 MW |
3693 | for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { |
3694 | fe.index = index; | |
3695 | mvpp2_cls_flow_write(priv, &fe); | |
3696 | } | |
3697 | ||
3698 | /* Clear classifier lookup table */ | |
3699 | le.data = 0; | |
3700 | for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) { | |
3701 | le.lkpid = index; | |
3702 | le.way = 0; | |
3703 | mvpp2_cls_lookup_write(priv, &le); | |
3704 | ||
3705 | le.way = 1; | |
3706 | mvpp2_cls_lookup_write(priv, &le); | |
3707 | } | |
3708 | } | |
3709 | ||
3710 | static void mvpp2_cls_port_config(struct mvpp2_port *port) | |
3711 | { | |
3712 | struct mvpp2_cls_lookup_entry le; | |
3713 | u32 val; | |
3714 | ||
3715 | /* Set way for the port */ | |
3716 | val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); | |
3717 | val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); | |
3718 | mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); | |
3719 | ||
3720 | /* Pick the entry to be accessed in lookup ID decoding table | |
3721 | * according to the way and lkpid. | |
3722 | */ | |
3723 | le.lkpid = port->id; | |
3724 | le.way = 0; | |
3725 | le.data = 0; | |
3726 | ||
3727 | /* Set initial CPU queue for receiving packets */ | |
3728 | le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK; | |
3729 | le.data |= port->first_rxq; | |
3730 | ||
3731 | /* Disable classification engines */ | |
3732 | le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; | |
3733 | ||
3734 | /* Update lookup ID table entry */ | |
3735 | mvpp2_cls_lookup_write(port->priv, &le); | |
3736 | } | |
3737 | ||
3738 | /* Set CPU queue number for oversize packets */ | |
3739 | static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) | |
3740 | { | |
3741 | u32 val; | |
3742 | ||
3743 | mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), | |
3744 | port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); | |
3745 | ||
3746 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), | |
3747 | (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); | |
3748 | ||
3749 | val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); | |
3750 | val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); | |
3751 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); | |
3752 | } | |
3753 | ||
0e037281 TP |
3754 | static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) |
3755 | { | |
3756 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
3757 | return netdev_alloc_frag(pool->frag_size); | |
3758 | else | |
3759 | return kmalloc(pool->frag_size, GFP_ATOMIC); | |
3760 | } | |
3761 | ||
3762 | static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) | |
3763 | { | |
3764 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
3765 | skb_free_frag(data); | |
3766 | else | |
3767 | kfree(data); | |
3768 | } | |
3769 | ||
3f518509 MW |
3770 | /* Buffer Manager configuration routines */ |
3771 | ||
3772 | /* Create pool */ | |
3773 | static int mvpp2_bm_pool_create(struct platform_device *pdev, | |
3774 | struct mvpp2 *priv, | |
3775 | struct mvpp2_bm_pool *bm_pool, int size) | |
3776 | { | |
3f518509 MW |
3777 | u32 val; |
3778 | ||
d01524d8 TP |
3779 | /* Number of buffer pointers must be a multiple of 16, as per |
3780 | * hardware constraints | |
3781 | */ | |
3782 | if (!IS_ALIGNED(size, 16)) | |
3783 | return -EINVAL; | |
3784 | ||
3785 | /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 | |
3786 | * bytes per buffer pointer | |
3787 | */ | |
3788 | if (priv->hw_version == MVPP21) | |
3789 | bm_pool->size_bytes = 2 * sizeof(u32) * size; | |
3790 | else | |
3791 | bm_pool->size_bytes = 2 * sizeof(u64) * size; | |
3792 | ||
3793 | bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, | |
20396136 | 3794 | &bm_pool->dma_addr, |
3f518509 MW |
3795 | GFP_KERNEL); |
3796 | if (!bm_pool->virt_addr) | |
3797 | return -ENOMEM; | |
3798 | ||
d3158807 TP |
3799 | if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, |
3800 | MVPP2_BM_POOL_PTR_ALIGN)) { | |
d01524d8 TP |
3801 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
3802 | bm_pool->virt_addr, bm_pool->dma_addr); | |
3f518509 MW |
3803 | dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", |
3804 | bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); | |
3805 | return -ENOMEM; | |
3806 | } | |
3807 | ||
3808 | mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), | |
d01524d8 | 3809 | lower_32_bits(bm_pool->dma_addr)); |
3f518509 MW |
3810 | mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); |
3811 | ||
3812 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
3813 | val |= MVPP2_BM_START_MASK; | |
3814 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
3815 | ||
3816 | bm_pool->type = MVPP2_BM_FREE; | |
3817 | bm_pool->size = size; | |
3818 | bm_pool->pkt_size = 0; | |
3819 | bm_pool->buf_num = 0; | |
3f518509 MW |
3820 | |
3821 | return 0; | |
3822 | } | |
3823 | ||
3824 | /* Set pool buffer size */ | |
3825 | static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, | |
3826 | struct mvpp2_bm_pool *bm_pool, | |
3827 | int buf_size) | |
3828 | { | |
3829 | u32 val; | |
3830 | ||
3831 | bm_pool->buf_size = buf_size; | |
3832 | ||
3833 | val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); | |
3834 | mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); | |
3835 | } | |
3836 | ||
d01524d8 TP |
3837 | static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, |
3838 | struct mvpp2_bm_pool *bm_pool, | |
3839 | dma_addr_t *dma_addr, | |
3840 | phys_addr_t *phys_addr) | |
3841 | { | |
a704bb5c | 3842 | int cpu = get_cpu(); |
a786841d TP |
3843 | |
3844 | *dma_addr = mvpp2_percpu_read(priv, cpu, | |
3845 | MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); | |
3846 | *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG); | |
d01524d8 TP |
3847 | |
3848 | if (priv->hw_version == MVPP22) { | |
3849 | u32 val; | |
3850 | u32 dma_addr_highbits, phys_addr_highbits; | |
3851 | ||
a786841d | 3852 | val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC); |
d01524d8 TP |
3853 | dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); |
3854 | phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> | |
3855 | MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; | |
3856 | ||
3857 | if (sizeof(dma_addr_t) == 8) | |
3858 | *dma_addr |= (u64)dma_addr_highbits << 32; | |
3859 | ||
3860 | if (sizeof(phys_addr_t) == 8) | |
3861 | *phys_addr |= (u64)phys_addr_highbits << 32; | |
3862 | } | |
a704bb5c TP |
3863 | |
3864 | put_cpu(); | |
d01524d8 TP |
3865 | } |
3866 | ||
7861f12b | 3867 | /* Free all buffers from the pool */ |
4229d502 MW |
3868 | static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, |
3869 | struct mvpp2_bm_pool *bm_pool) | |
3f518509 MW |
3870 | { |
3871 | int i; | |
3872 | ||
7861f12b | 3873 | for (i = 0; i < bm_pool->buf_num; i++) { |
20396136 | 3874 | dma_addr_t buf_dma_addr; |
4e4a105f TP |
3875 | phys_addr_t buf_phys_addr; |
3876 | void *data; | |
3f518509 | 3877 | |
d01524d8 TP |
3878 | mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, |
3879 | &buf_dma_addr, &buf_phys_addr); | |
4229d502 | 3880 | |
20396136 | 3881 | dma_unmap_single(dev, buf_dma_addr, |
4229d502 MW |
3882 | bm_pool->buf_size, DMA_FROM_DEVICE); |
3883 | ||
4e4a105f TP |
3884 | data = (void *)phys_to_virt(buf_phys_addr); |
3885 | if (!data) | |
3f518509 | 3886 | break; |
0e037281 | 3887 | |
4e4a105f | 3888 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
3889 | } |
3890 | ||
3891 | /* Update BM driver with number of buffers removed from pool */ | |
3892 | bm_pool->buf_num -= i; | |
3f518509 MW |
3893 | } |
3894 | ||
3895 | /* Cleanup pool */ | |
3896 | static int mvpp2_bm_pool_destroy(struct platform_device *pdev, | |
3897 | struct mvpp2 *priv, | |
3898 | struct mvpp2_bm_pool *bm_pool) | |
3899 | { | |
3f518509 MW |
3900 | u32 val; |
3901 | ||
4229d502 | 3902 | mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool); |
d74c96c1 | 3903 | if (bm_pool->buf_num) { |
3f518509 MW |
3904 | WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id); |
3905 | return 0; | |
3906 | } | |
3907 | ||
3908 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
3909 | val |= MVPP2_BM_STOP_MASK; | |
3910 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
3911 | ||
d01524d8 | 3912 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
3f518509 | 3913 | bm_pool->virt_addr, |
20396136 | 3914 | bm_pool->dma_addr); |
3f518509 MW |
3915 | return 0; |
3916 | } | |
3917 | ||
3918 | static int mvpp2_bm_pools_init(struct platform_device *pdev, | |
3919 | struct mvpp2 *priv) | |
3920 | { | |
3921 | int i, err, size; | |
3922 | struct mvpp2_bm_pool *bm_pool; | |
3923 | ||
3924 | /* Create all pools with maximum size */ | |
3925 | size = MVPP2_BM_POOL_SIZE_MAX; | |
3926 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
3927 | bm_pool = &priv->bm_pools[i]; | |
3928 | bm_pool->id = i; | |
3929 | err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); | |
3930 | if (err) | |
3931 | goto err_unroll_pools; | |
3932 | mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); | |
3933 | } | |
3934 | return 0; | |
3935 | ||
3936 | err_unroll_pools: | |
3937 | dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); | |
3938 | for (i = i - 1; i >= 0; i--) | |
3939 | mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); | |
3940 | return err; | |
3941 | } | |
3942 | ||
3943 | static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) | |
3944 | { | |
3945 | int i, err; | |
3946 | ||
3947 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
3948 | /* Mask BM all interrupts */ | |
3949 | mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); | |
3950 | /* Clear BM cause register */ | |
3951 | mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); | |
3952 | } | |
3953 | ||
3954 | /* Allocate and initialize BM pools */ | |
3955 | priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, | |
81f915eb | 3956 | sizeof(*priv->bm_pools), GFP_KERNEL); |
3f518509 MW |
3957 | if (!priv->bm_pools) |
3958 | return -ENOMEM; | |
3959 | ||
3960 | err = mvpp2_bm_pools_init(pdev, priv); | |
3961 | if (err < 0) | |
3962 | return err; | |
3963 | return 0; | |
3964 | } | |
3965 | ||
3966 | /* Attach long pool to rxq */ | |
3967 | static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, | |
3968 | int lrxq, int long_pool) | |
3969 | { | |
5eac892a | 3970 | u32 val, mask; |
3f518509 MW |
3971 | int prxq; |
3972 | ||
3973 | /* Get queue physical ID */ | |
3974 | prxq = port->rxqs[lrxq]->id; | |
3975 | ||
5eac892a TP |
3976 | if (port->priv->hw_version == MVPP21) |
3977 | mask = MVPP21_RXQ_POOL_LONG_MASK; | |
3978 | else | |
3979 | mask = MVPP22_RXQ_POOL_LONG_MASK; | |
3f518509 | 3980 | |
5eac892a TP |
3981 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
3982 | val &= ~mask; | |
3983 | val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; | |
3f518509 MW |
3984 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
3985 | } | |
3986 | ||
3987 | /* Attach short pool to rxq */ | |
3988 | static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, | |
3989 | int lrxq, int short_pool) | |
3990 | { | |
5eac892a | 3991 | u32 val, mask; |
3f518509 MW |
3992 | int prxq; |
3993 | ||
3994 | /* Get queue physical ID */ | |
3995 | prxq = port->rxqs[lrxq]->id; | |
3996 | ||
5eac892a TP |
3997 | if (port->priv->hw_version == MVPP21) |
3998 | mask = MVPP21_RXQ_POOL_SHORT_MASK; | |
3999 | else | |
4000 | mask = MVPP22_RXQ_POOL_SHORT_MASK; | |
3f518509 | 4001 | |
5eac892a TP |
4002 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
4003 | val &= ~mask; | |
4004 | val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; | |
3f518509 MW |
4005 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
4006 | } | |
4007 | ||
0e037281 TP |
4008 | static void *mvpp2_buf_alloc(struct mvpp2_port *port, |
4009 | struct mvpp2_bm_pool *bm_pool, | |
20396136 | 4010 | dma_addr_t *buf_dma_addr, |
4e4a105f | 4011 | phys_addr_t *buf_phys_addr, |
0e037281 | 4012 | gfp_t gfp_mask) |
3f518509 | 4013 | { |
20396136 | 4014 | dma_addr_t dma_addr; |
0e037281 | 4015 | void *data; |
3f518509 | 4016 | |
0e037281 TP |
4017 | data = mvpp2_frag_alloc(bm_pool); |
4018 | if (!data) | |
3f518509 MW |
4019 | return NULL; |
4020 | ||
20396136 TP |
4021 | dma_addr = dma_map_single(port->dev->dev.parent, data, |
4022 | MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), | |
4023 | DMA_FROM_DEVICE); | |
4024 | if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { | |
0e037281 | 4025 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
4026 | return NULL; |
4027 | } | |
20396136 | 4028 | *buf_dma_addr = dma_addr; |
4e4a105f | 4029 | *buf_phys_addr = virt_to_phys(data); |
3f518509 | 4030 | |
0e037281 | 4031 | return data; |
3f518509 MW |
4032 | } |
4033 | ||
3f518509 MW |
4034 | /* Release buffer to BM */ |
4035 | static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, | |
20396136 | 4036 | dma_addr_t buf_dma_addr, |
4e4a105f | 4037 | phys_addr_t buf_phys_addr) |
3f518509 | 4038 | { |
a704bb5c | 4039 | int cpu = get_cpu(); |
a786841d | 4040 | |
d01524d8 TP |
4041 | if (port->priv->hw_version == MVPP22) { |
4042 | u32 val = 0; | |
4043 | ||
4044 | if (sizeof(dma_addr_t) == 8) | |
4045 | val |= upper_32_bits(buf_dma_addr) & | |
4046 | MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; | |
4047 | ||
4048 | if (sizeof(phys_addr_t) == 8) | |
4049 | val |= (upper_32_bits(buf_phys_addr) | |
4050 | << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & | |
4051 | MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; | |
4052 | ||
a786841d TP |
4053 | mvpp2_percpu_write(port->priv, cpu, |
4054 | MVPP22_BM_ADDR_HIGH_RLS_REG, val); | |
d01524d8 TP |
4055 | } |
4056 | ||
4e4a105f TP |
4057 | /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply |
4058 | * returned in the "cookie" field of the RX | |
4059 | * descriptor. Instead of storing the virtual address, we | |
4060 | * store the physical address | |
4061 | */ | |
a786841d TP |
4062 | mvpp2_percpu_write(port->priv, cpu, |
4063 | MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); | |
4064 | mvpp2_percpu_write(port->priv, cpu, | |
4065 | MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); | |
a704bb5c TP |
4066 | |
4067 | put_cpu(); | |
3f518509 MW |
4068 | } |
4069 | ||
3f518509 MW |
4070 | /* Allocate buffers for the pool */ |
4071 | static int mvpp2_bm_bufs_add(struct mvpp2_port *port, | |
4072 | struct mvpp2_bm_pool *bm_pool, int buf_num) | |
4073 | { | |
3f518509 | 4074 | int i, buf_size, total_size; |
20396136 | 4075 | dma_addr_t dma_addr; |
4e4a105f | 4076 | phys_addr_t phys_addr; |
0e037281 | 4077 | void *buf; |
3f518509 MW |
4078 | |
4079 | buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); | |
4080 | total_size = MVPP2_RX_TOTAL_SIZE(buf_size); | |
4081 | ||
4082 | if (buf_num < 0 || | |
4083 | (buf_num + bm_pool->buf_num > bm_pool->size)) { | |
4084 | netdev_err(port->dev, | |
4085 | "cannot allocate %d buffers for pool %d\n", | |
4086 | buf_num, bm_pool->id); | |
4087 | return 0; | |
4088 | } | |
4089 | ||
3f518509 | 4090 | for (i = 0; i < buf_num; i++) { |
4e4a105f TP |
4091 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, |
4092 | &phys_addr, GFP_KERNEL); | |
0e037281 | 4093 | if (!buf) |
3f518509 MW |
4094 | break; |
4095 | ||
20396136 | 4096 | mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, |
4e4a105f | 4097 | phys_addr); |
3f518509 MW |
4098 | } |
4099 | ||
4100 | /* Update BM driver with number of buffers added to pool */ | |
4101 | bm_pool->buf_num += i; | |
3f518509 MW |
4102 | |
4103 | netdev_dbg(port->dev, | |
4104 | "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", | |
4105 | bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long", | |
4106 | bm_pool->id, bm_pool->pkt_size, buf_size, total_size); | |
4107 | ||
4108 | netdev_dbg(port->dev, | |
4109 | "%s pool %d: %d of %d buffers added\n", | |
4110 | bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long", | |
4111 | bm_pool->id, i, buf_num); | |
4112 | return i; | |
4113 | } | |
4114 | ||
4115 | /* Notify the driver that BM pool is being used as specific type and return the | |
4116 | * pool pointer on success | |
4117 | */ | |
4118 | static struct mvpp2_bm_pool * | |
4119 | mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, | |
4120 | int pkt_size) | |
4121 | { | |
3f518509 MW |
4122 | struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; |
4123 | int num; | |
4124 | ||
4125 | if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) { | |
4126 | netdev_err(port->dev, "mixing pool types is forbidden\n"); | |
4127 | return NULL; | |
4128 | } | |
4129 | ||
3f518509 MW |
4130 | if (new_pool->type == MVPP2_BM_FREE) |
4131 | new_pool->type = type; | |
4132 | ||
4133 | /* Allocate buffers in case BM pool is used as long pool, but packet | |
4134 | * size doesn't match MTU or BM pool hasn't being used yet | |
4135 | */ | |
4136 | if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) || | |
4137 | (new_pool->pkt_size == 0)) { | |
4138 | int pkts_num; | |
4139 | ||
4140 | /* Set default buffer number or free all the buffers in case | |
4141 | * the pool is not empty | |
4142 | */ | |
4143 | pkts_num = new_pool->buf_num; | |
4144 | if (pkts_num == 0) | |
4145 | pkts_num = type == MVPP2_BM_SWF_LONG ? | |
4146 | MVPP2_BM_LONG_BUF_NUM : | |
4147 | MVPP2_BM_SHORT_BUF_NUM; | |
4148 | else | |
4229d502 MW |
4149 | mvpp2_bm_bufs_free(port->dev->dev.parent, |
4150 | port->priv, new_pool); | |
3f518509 MW |
4151 | |
4152 | new_pool->pkt_size = pkt_size; | |
0e037281 TP |
4153 | new_pool->frag_size = |
4154 | SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + | |
4155 | MVPP2_SKB_SHINFO_SIZE; | |
3f518509 MW |
4156 | |
4157 | /* Allocate buffers for this pool */ | |
4158 | num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); | |
4159 | if (num != pkts_num) { | |
4160 | WARN(1, "pool %d: %d of %d allocated\n", | |
4161 | new_pool->id, num, pkts_num); | |
3f518509 MW |
4162 | return NULL; |
4163 | } | |
4164 | } | |
4165 | ||
4166 | mvpp2_bm_pool_bufsize_set(port->priv, new_pool, | |
4167 | MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); | |
4168 | ||
3f518509 MW |
4169 | return new_pool; |
4170 | } | |
4171 | ||
4172 | /* Initialize pools for swf */ | |
4173 | static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) | |
4174 | { | |
3f518509 MW |
4175 | int rxq; |
4176 | ||
4177 | if (!port->pool_long) { | |
4178 | port->pool_long = | |
4179 | mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), | |
4180 | MVPP2_BM_SWF_LONG, | |
4181 | port->pkt_size); | |
4182 | if (!port->pool_long) | |
4183 | return -ENOMEM; | |
4184 | ||
3f518509 | 4185 | port->pool_long->port_map |= (1 << port->id); |
3f518509 | 4186 | |
09f83975 | 4187 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4188 | mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); |
4189 | } | |
4190 | ||
4191 | if (!port->pool_short) { | |
4192 | port->pool_short = | |
4193 | mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL, | |
4194 | MVPP2_BM_SWF_SHORT, | |
4195 | MVPP2_BM_SHORT_PKT_SIZE); | |
4196 | if (!port->pool_short) | |
4197 | return -ENOMEM; | |
4198 | ||
3f518509 | 4199 | port->pool_short->port_map |= (1 << port->id); |
3f518509 | 4200 | |
09f83975 | 4201 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4202 | mvpp2_rxq_short_pool_set(port, rxq, |
4203 | port->pool_short->id); | |
4204 | } | |
4205 | ||
4206 | return 0; | |
4207 | } | |
4208 | ||
4209 | static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) | |
4210 | { | |
4211 | struct mvpp2_port *port = netdev_priv(dev); | |
4212 | struct mvpp2_bm_pool *port_pool = port->pool_long; | |
4213 | int num, pkts_num = port_pool->buf_num; | |
4214 | int pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
4215 | ||
4216 | /* Update BM pool with new buffer size */ | |
4229d502 | 4217 | mvpp2_bm_bufs_free(dev->dev.parent, port->priv, port_pool); |
d74c96c1 | 4218 | if (port_pool->buf_num) { |
3f518509 MW |
4219 | WARN(1, "cannot free all buffers in pool %d\n", port_pool->id); |
4220 | return -EIO; | |
4221 | } | |
4222 | ||
4223 | port_pool->pkt_size = pkt_size; | |
0e037281 TP |
4224 | port_pool->frag_size = SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + |
4225 | MVPP2_SKB_SHINFO_SIZE; | |
3f518509 MW |
4226 | num = mvpp2_bm_bufs_add(port, port_pool, pkts_num); |
4227 | if (num != pkts_num) { | |
4228 | WARN(1, "pool %d: %d of %d allocated\n", | |
4229 | port_pool->id, num, pkts_num); | |
4230 | return -EIO; | |
4231 | } | |
4232 | ||
4233 | mvpp2_bm_pool_bufsize_set(port->priv, port_pool, | |
4234 | MVPP2_RX_BUF_SIZE(port_pool->pkt_size)); | |
4235 | dev->mtu = mtu; | |
4236 | netdev_update_features(dev); | |
4237 | return 0; | |
4238 | } | |
4239 | ||
4240 | static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) | |
4241 | { | |
591f4cfa TP |
4242 | int i, sw_thread_mask = 0; |
4243 | ||
4244 | for (i = 0; i < port->nqvecs; i++) | |
4245 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
3f518509 | 4246 | |
3f518509 | 4247 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa | 4248 | MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); |
3f518509 MW |
4249 | } |
4250 | ||
4251 | static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) | |
4252 | { | |
591f4cfa TP |
4253 | int i, sw_thread_mask = 0; |
4254 | ||
4255 | for (i = 0; i < port->nqvecs; i++) | |
4256 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
4257 | ||
4258 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4259 | MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); | |
4260 | } | |
4261 | ||
4262 | static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) | |
4263 | { | |
4264 | struct mvpp2_port *port = qvec->port; | |
3f518509 | 4265 | |
3f518509 | 4266 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa TP |
4267 | MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); |
4268 | } | |
4269 | ||
4270 | static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) | |
4271 | { | |
4272 | struct mvpp2_port *port = qvec->port; | |
4273 | ||
4274 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4275 | MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); | |
3f518509 MW |
4276 | } |
4277 | ||
e0af22d9 TP |
4278 | /* Mask the current CPU's Rx/Tx interrupts |
4279 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4280 | * using smp_processor_id() is OK. | |
4281 | */ | |
3f518509 MW |
4282 | static void mvpp2_interrupts_mask(void *arg) |
4283 | { | |
4284 | struct mvpp2_port *port = arg; | |
4285 | ||
a786841d TP |
4286 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
4287 | MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); | |
3f518509 MW |
4288 | } |
4289 | ||
e0af22d9 TP |
4290 | /* Unmask the current CPU's Rx/Tx interrupts. |
4291 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4292 | * using smp_processor_id() is OK. | |
4293 | */ | |
3f518509 MW |
4294 | static void mvpp2_interrupts_unmask(void *arg) |
4295 | { | |
4296 | struct mvpp2_port *port = arg; | |
213f428f TP |
4297 | u32 val; |
4298 | ||
4299 | val = MVPP2_CAUSE_MISC_SUM_MASK | | |
4300 | MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4301 | if (port->has_tx_irqs) | |
4302 | val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; | |
3f518509 | 4303 | |
a786841d | 4304 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
213f428f TP |
4305 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); |
4306 | } | |
4307 | ||
4308 | static void | |
4309 | mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) | |
4310 | { | |
4311 | u32 val; | |
4312 | int i; | |
4313 | ||
4314 | if (port->priv->hw_version != MVPP22) | |
4315 | return; | |
4316 | ||
4317 | if (mask) | |
4318 | val = 0; | |
4319 | else | |
4320 | val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4321 | ||
4322 | for (i = 0; i < port->nqvecs; i++) { | |
4323 | struct mvpp2_queue_vector *v = port->qvecs + i; | |
4324 | ||
4325 | if (v->type != MVPP2_QUEUE_VECTOR_SHARED) | |
4326 | continue; | |
4327 | ||
4328 | mvpp2_percpu_write(port->priv, v->sw_thread_id, | |
4329 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); | |
4330 | } | |
3f518509 MW |
4331 | } |
4332 | ||
4333 | /* Port configuration routines */ | |
4334 | ||
f84bf386 AT |
4335 | static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) |
4336 | { | |
4337 | struct mvpp2 *priv = port->priv; | |
4338 | u32 val; | |
4339 | ||
4340 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4341 | val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; | |
4342 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4343 | ||
4344 | regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); | |
4345 | if (port->gop_id == 2) | |
4346 | val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; | |
4347 | else if (port->gop_id == 3) | |
4348 | val |= GENCONF_CTRL0_PORT1_RGMII_MII; | |
4349 | regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); | |
4350 | } | |
4351 | ||
4352 | static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) | |
4353 | { | |
4354 | struct mvpp2 *priv = port->priv; | |
4355 | u32 val; | |
4356 | ||
4357 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4358 | val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | | |
4359 | GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; | |
4360 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4361 | ||
4362 | if (port->gop_id > 1) { | |
4363 | regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); | |
4364 | if (port->gop_id == 2) | |
4365 | val &= ~GENCONF_CTRL0_PORT0_RGMII; | |
4366 | else if (port->gop_id == 3) | |
4367 | val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; | |
4368 | regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); | |
4369 | } | |
4370 | } | |
4371 | ||
4372 | static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) | |
4373 | { | |
4374 | struct mvpp2 *priv = port->priv; | |
4375 | void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); | |
4376 | void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); | |
4377 | u32 val; | |
4378 | ||
4379 | /* XPCS */ | |
4380 | val = readl(xpcs + MVPP22_XPCS_CFG0); | |
4381 | val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | | |
4382 | MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); | |
4383 | val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); | |
4384 | writel(val, xpcs + MVPP22_XPCS_CFG0); | |
4385 | ||
4386 | /* MPCS */ | |
4387 | val = readl(mpcs + MVPP22_MPCS_CTRL); | |
4388 | val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; | |
4389 | writel(val, mpcs + MVPP22_MPCS_CTRL); | |
4390 | ||
4391 | val = readl(mpcs + MVPP22_MPCS_CLK_RESET); | |
4392 | val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | | |
4393 | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); | |
4394 | val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); | |
4395 | writel(val, mpcs + MVPP22_MPCS_CLK_RESET); | |
4396 | ||
4397 | val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; | |
4398 | val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; | |
4399 | writel(val, mpcs + MVPP22_MPCS_CLK_RESET); | |
4400 | } | |
4401 | ||
4402 | static int mvpp22_gop_init(struct mvpp2_port *port) | |
4403 | { | |
4404 | struct mvpp2 *priv = port->priv; | |
4405 | u32 val; | |
4406 | ||
4407 | if (!priv->sysctrl_base) | |
4408 | return 0; | |
4409 | ||
4410 | switch (port->phy_interface) { | |
4411 | case PHY_INTERFACE_MODE_RGMII: | |
4412 | case PHY_INTERFACE_MODE_RGMII_ID: | |
4413 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
4414 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
4415 | if (port->gop_id == 0) | |
4416 | goto invalid_conf; | |
4417 | mvpp22_gop_init_rgmii(port); | |
4418 | break; | |
4419 | case PHY_INTERFACE_MODE_SGMII: | |
4420 | mvpp22_gop_init_sgmii(port); | |
4421 | break; | |
4422 | case PHY_INTERFACE_MODE_10GKR: | |
4423 | if (port->gop_id != 0) | |
4424 | goto invalid_conf; | |
4425 | mvpp22_gop_init_10gkr(port); | |
4426 | break; | |
4427 | default: | |
4428 | goto unsupported_conf; | |
4429 | } | |
4430 | ||
4431 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); | |
4432 | val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | | |
4433 | GENCONF_PORT_CTRL1_EN(port->gop_id); | |
4434 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); | |
4435 | ||
4436 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4437 | val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; | |
4438 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4439 | ||
4440 | regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); | |
4441 | val |= GENCONF_SOFT_RESET1_GOP; | |
4442 | regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); | |
4443 | ||
4444 | unsupported_conf: | |
4445 | return 0; | |
4446 | ||
4447 | invalid_conf: | |
4448 | netdev_err(port->dev, "Invalid port configuration\n"); | |
4449 | return -EINVAL; | |
4450 | } | |
4451 | ||
fd3651b2 AT |
4452 | static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) |
4453 | { | |
4454 | u32 val; | |
4455 | ||
4456 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4457 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4458 | /* Enable the GMAC link status irq for this port */ | |
4459 | val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4460 | val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; | |
4461 | writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4462 | } | |
4463 | ||
4464 | if (port->gop_id == 0) { | |
4465 | /* Enable the XLG/GIG irqs for this port */ | |
4466 | val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); | |
4467 | if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
4468 | val |= MVPP22_XLG_EXT_INT_MASK_XLG; | |
4469 | else | |
4470 | val |= MVPP22_XLG_EXT_INT_MASK_GIG; | |
4471 | writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); | |
4472 | } | |
4473 | } | |
4474 | ||
4475 | static void mvpp22_gop_mask_irq(struct mvpp2_port *port) | |
4476 | { | |
4477 | u32 val; | |
4478 | ||
4479 | if (port->gop_id == 0) { | |
4480 | val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); | |
4481 | val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | | |
4482 | MVPP22_XLG_EXT_INT_MASK_GIG); | |
4483 | writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); | |
4484 | } | |
4485 | ||
4486 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4487 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4488 | val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4489 | val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; | |
4490 | writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4491 | } | |
4492 | } | |
4493 | ||
4494 | static void mvpp22_gop_setup_irq(struct mvpp2_port *port) | |
4495 | { | |
4496 | u32 val; | |
4497 | ||
4498 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4499 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4500 | val = readl(port->base + MVPP22_GMAC_INT_MASK); | |
4501 | val |= MVPP22_GMAC_INT_MASK_LINK_STAT; | |
4502 | writel(val, port->base + MVPP22_GMAC_INT_MASK); | |
4503 | } | |
4504 | ||
4505 | if (port->gop_id == 0) { | |
4506 | val = readl(port->base + MVPP22_XLG_INT_MASK); | |
4507 | val |= MVPP22_XLG_INT_MASK_LINK; | |
4508 | writel(val, port->base + MVPP22_XLG_INT_MASK); | |
4509 | } | |
4510 | ||
4511 | mvpp22_gop_unmask_irq(port); | |
4512 | } | |
4513 | ||
542897d9 AT |
4514 | static int mvpp22_comphy_init(struct mvpp2_port *port) |
4515 | { | |
4516 | enum phy_mode mode; | |
4517 | int ret; | |
4518 | ||
4519 | if (!port->comphy) | |
4520 | return 0; | |
4521 | ||
4522 | switch (port->phy_interface) { | |
4523 | case PHY_INTERFACE_MODE_SGMII: | |
4524 | mode = PHY_MODE_SGMII; | |
4525 | break; | |
4526 | case PHY_INTERFACE_MODE_10GKR: | |
4527 | mode = PHY_MODE_10GKR; | |
4528 | break; | |
4529 | default: | |
4530 | return -EINVAL; | |
4531 | } | |
4532 | ||
4533 | ret = phy_set_mode(port->comphy, mode); | |
4534 | if (ret) | |
4535 | return ret; | |
4536 | ||
4537 | return phy_power_on(port->comphy); | |
4538 | } | |
4539 | ||
3919357f AT |
4540 | static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) |
4541 | { | |
4542 | u32 val; | |
4543 | ||
4544 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4545 | val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); | |
4546 | val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL | | |
4547 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
4548 | val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; | |
4549 | writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); | |
4550 | ||
4551 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4552 | val |= MVPP2_GMAC_DISABLE_PADDING; | |
4553 | val &= ~MVPP2_GMAC_FLOW_CTRL_MASK; | |
4554 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
1df2270d | 4555 | } else if (phy_interface_mode_is_rgmii(port->phy_interface)) { |
3919357f AT |
4556 | val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); |
4557 | val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | | |
4558 | MVPP22_CTRL4_SYNC_BYPASS_DIS | | |
4559 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
4560 | val &= ~MVPP22_CTRL4_DP_CLK_SEL; | |
4561 | writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); | |
4562 | ||
4563 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4564 | val &= ~MVPP2_GMAC_DISABLE_PADDING; | |
4565 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4566 | } | |
4567 | ||
4568 | /* The port is connected to a copper PHY */ | |
4569 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4570 | val &= ~MVPP2_GMAC_PORT_TYPE_MASK; | |
4571 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4572 | ||
4573 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4574 | val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | | |
4575 | MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | | |
4576 | MVPP2_GMAC_AN_DUPLEX_EN; | |
4577 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
4578 | val |= MVPP2_GMAC_IN_BAND_AUTONEG; | |
4579 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4580 | } | |
4581 | ||
4582 | static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port) | |
4583 | { | |
4584 | u32 val; | |
4585 | ||
4586 | /* Force link down */ | |
4587 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4588 | val &= ~MVPP2_GMAC_FORCE_LINK_PASS; | |
4589 | val |= MVPP2_GMAC_FORCE_LINK_DOWN; | |
4590 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4591 | ||
4592 | /* Set the GMAC in a reset state */ | |
4593 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4594 | val |= MVPP2_GMAC_PORT_RESET_MASK; | |
4595 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4596 | ||
4597 | /* Configure the PCS and in-band AN */ | |
4598 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4599 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4600 | val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; | |
1df2270d | 4601 | } else if (phy_interface_mode_is_rgmii(port->phy_interface)) { |
3919357f | 4602 | val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; |
3919357f AT |
4603 | } |
4604 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4605 | ||
4606 | mvpp2_port_mii_gmac_configure_mode(port); | |
4607 | ||
4608 | /* Unset the GMAC reset state */ | |
4609 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4610 | val &= ~MVPP2_GMAC_PORT_RESET_MASK; | |
4611 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4612 | ||
4613 | /* Stop forcing link down */ | |
4614 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4615 | val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; | |
4616 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4617 | } | |
4618 | ||
77321959 AT |
4619 | static void mvpp2_port_mii_xlg_configure(struct mvpp2_port *port) |
4620 | { | |
4621 | u32 val; | |
4622 | ||
4623 | if (port->gop_id != 0) | |
4624 | return; | |
4625 | ||
4626 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4627 | val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; | |
4628 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
4629 | ||
4630 | val = readl(port->base + MVPP22_XLG_CTRL4_REG); | |
4631 | val &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; | |
4632 | val |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC; | |
4633 | writel(val, port->base + MVPP22_XLG_CTRL4_REG); | |
4634 | } | |
4635 | ||
26975821 TP |
4636 | static void mvpp22_port_mii_set(struct mvpp2_port *port) |
4637 | { | |
4638 | u32 val; | |
4639 | ||
26975821 TP |
4640 | /* Only GOP port 0 has an XLG MAC */ |
4641 | if (port->gop_id == 0) { | |
4642 | val = readl(port->base + MVPP22_XLG_CTRL3_REG); | |
4643 | val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; | |
725757ae AT |
4644 | |
4645 | if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
4646 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
4647 | val |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; | |
4648 | else | |
4649 | val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; | |
4650 | ||
26975821 TP |
4651 | writel(val, port->base + MVPP22_XLG_CTRL3_REG); |
4652 | } | |
26975821 TP |
4653 | } |
4654 | ||
3f518509 MW |
4655 | static void mvpp2_port_mii_set(struct mvpp2_port *port) |
4656 | { | |
26975821 TP |
4657 | if (port->priv->hw_version == MVPP22) |
4658 | mvpp22_port_mii_set(port); | |
4659 | ||
1df2270d | 4660 | if (phy_interface_mode_is_rgmii(port->phy_interface) || |
3919357f AT |
4661 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) |
4662 | mvpp2_port_mii_gmac_configure(port); | |
77321959 AT |
4663 | else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) |
4664 | mvpp2_port_mii_xlg_configure(port); | |
08a23755 | 4665 | } |
3f518509 | 4666 | |
08a23755 MW |
4667 | static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) |
4668 | { | |
4669 | u32 val; | |
4670 | ||
4671 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4672 | val |= MVPP2_GMAC_FC_ADV_EN; | |
4673 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
3f518509 MW |
4674 | } |
4675 | ||
4676 | static void mvpp2_port_enable(struct mvpp2_port *port) | |
4677 | { | |
4678 | u32 val; | |
4679 | ||
725757ae AT |
4680 | /* Only GOP port 0 has an XLG MAC */ |
4681 | if (port->gop_id == 0 && | |
4682 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
4683 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
4684 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4685 | val |= MVPP22_XLG_CTRL0_PORT_EN | | |
4686 | MVPP22_XLG_CTRL0_MAC_RESET_DIS; | |
4687 | val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; | |
4688 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
4689 | } else { | |
4690 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4691 | val |= MVPP2_GMAC_PORT_EN_MASK; | |
4692 | val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; | |
4693 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4694 | } | |
3f518509 MW |
4695 | } |
4696 | ||
4697 | static void mvpp2_port_disable(struct mvpp2_port *port) | |
4698 | { | |
4699 | u32 val; | |
4700 | ||
725757ae AT |
4701 | /* Only GOP port 0 has an XLG MAC */ |
4702 | if (port->gop_id == 0 && | |
4703 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
4704 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
4705 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4706 | val &= ~(MVPP22_XLG_CTRL0_PORT_EN | | |
4707 | MVPP22_XLG_CTRL0_MAC_RESET_DIS); | |
4708 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
4709 | } else { | |
4710 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4711 | val &= ~(MVPP2_GMAC_PORT_EN_MASK); | |
4712 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4713 | } | |
3f518509 MW |
4714 | } |
4715 | ||
4716 | /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ | |
4717 | static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) | |
4718 | { | |
4719 | u32 val; | |
4720 | ||
4721 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & | |
4722 | ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; | |
4723 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
4724 | } | |
4725 | ||
4726 | /* Configure loopback port */ | |
4727 | static void mvpp2_port_loopback_set(struct mvpp2_port *port) | |
4728 | { | |
4729 | u32 val; | |
4730 | ||
4731 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
4732 | ||
4733 | if (port->speed == 1000) | |
4734 | val |= MVPP2_GMAC_GMII_LB_EN_MASK; | |
4735 | else | |
4736 | val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; | |
4737 | ||
4738 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
4739 | val |= MVPP2_GMAC_PCS_LB_EN_MASK; | |
4740 | else | |
4741 | val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; | |
4742 | ||
4743 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
4744 | } | |
4745 | ||
4746 | static void mvpp2_port_reset(struct mvpp2_port *port) | |
4747 | { | |
4748 | u32 val; | |
4749 | ||
4750 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
4751 | ~MVPP2_GMAC_PORT_RESET_MASK; | |
4752 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4753 | ||
4754 | while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
4755 | MVPP2_GMAC_PORT_RESET_MASK) | |
4756 | continue; | |
4757 | } | |
4758 | ||
4759 | /* Change maximum receive size of the port */ | |
4760 | static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) | |
4761 | { | |
4762 | u32 val; | |
4763 | ||
4764 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4765 | val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; | |
4766 | val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
4767 | MVPP2_GMAC_MAX_RX_SIZE_OFFS); | |
4768 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4769 | } | |
4770 | ||
76eb1b1d SC |
4771 | /* Change maximum receive size of the port */ |
4772 | static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) | |
4773 | { | |
4774 | u32 val; | |
4775 | ||
4776 | val = readl(port->base + MVPP22_XLG_CTRL1_REG); | |
4777 | val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; | |
4778 | val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
ec15ecde | 4779 | MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; |
76eb1b1d SC |
4780 | writel(val, port->base + MVPP22_XLG_CTRL1_REG); |
4781 | } | |
4782 | ||
3f518509 MW |
4783 | /* Set defaults to the MVPP2 port */ |
4784 | static void mvpp2_defaults_set(struct mvpp2_port *port) | |
4785 | { | |
4786 | int tx_port_num, val, queue, ptxq, lrxq; | |
4787 | ||
3d9017d9 TP |
4788 | if (port->priv->hw_version == MVPP21) { |
4789 | /* Configure port to loopback if needed */ | |
4790 | if (port->flags & MVPP2_F_LOOPBACK) | |
4791 | mvpp2_port_loopback_set(port); | |
4792 | ||
4793 | /* Update TX FIFO MIN Threshold */ | |
4794 | val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
4795 | val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; | |
4796 | /* Min. TX threshold must be less than minimal packet length */ | |
4797 | val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); | |
4798 | writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
4799 | } | |
3f518509 MW |
4800 | |
4801 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
4802 | tx_port_num = mvpp2_egress_port(port); | |
4803 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, | |
4804 | tx_port_num); | |
4805 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); | |
4806 | ||
4807 | /* Close bandwidth for all queues */ | |
4808 | for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { | |
4809 | ptxq = mvpp2_txq_phys(port->id, queue); | |
4810 | mvpp2_write(port->priv, | |
4811 | MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); | |
4812 | } | |
4813 | ||
4814 | /* Set refill period to 1 usec, refill tokens | |
4815 | * and bucket size to maximum | |
4816 | */ | |
4817 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, | |
4818 | port->priv->tclk / USEC_PER_SEC); | |
4819 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); | |
4820 | val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; | |
4821 | val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); | |
4822 | val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; | |
4823 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); | |
4824 | val = MVPP2_TXP_TOKEN_SIZE_MAX; | |
4825 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
4826 | ||
4827 | /* Set MaximumLowLatencyPacketSize value to 256 */ | |
4828 | mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), | |
4829 | MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | | |
4830 | MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); | |
4831 | ||
4832 | /* Enable Rx cache snoop */ | |
09f83975 | 4833 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
4834 | queue = port->rxqs[lrxq]->id; |
4835 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
4836 | val |= MVPP2_SNOOP_PKT_SIZE_MASK | | |
4837 | MVPP2_SNOOP_BUF_HDR_MASK; | |
4838 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
4839 | } | |
4840 | ||
4841 | /* At default, mask all interrupts to all present cpus */ | |
4842 | mvpp2_interrupts_disable(port); | |
4843 | } | |
4844 | ||
4845 | /* Enable/disable receiving packets */ | |
4846 | static void mvpp2_ingress_enable(struct mvpp2_port *port) | |
4847 | { | |
4848 | u32 val; | |
4849 | int lrxq, queue; | |
4850 | ||
09f83975 | 4851 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
4852 | queue = port->rxqs[lrxq]->id; |
4853 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
4854 | val &= ~MVPP2_RXQ_DISABLE_MASK; | |
4855 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
4856 | } | |
4857 | } | |
4858 | ||
4859 | static void mvpp2_ingress_disable(struct mvpp2_port *port) | |
4860 | { | |
4861 | u32 val; | |
4862 | int lrxq, queue; | |
4863 | ||
09f83975 | 4864 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
4865 | queue = port->rxqs[lrxq]->id; |
4866 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
4867 | val |= MVPP2_RXQ_DISABLE_MASK; | |
4868 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
4869 | } | |
4870 | } | |
4871 | ||
4872 | /* Enable transmit via physical egress queue | |
4873 | * - HW starts take descriptors from DRAM | |
4874 | */ | |
4875 | static void mvpp2_egress_enable(struct mvpp2_port *port) | |
4876 | { | |
4877 | u32 qmap; | |
4878 | int queue; | |
4879 | int tx_port_num = mvpp2_egress_port(port); | |
4880 | ||
4881 | /* Enable all initialized TXs. */ | |
4882 | qmap = 0; | |
09f83975 | 4883 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
4884 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
4885 | ||
dbbb2f03 | 4886 | if (txq->descs) |
3f518509 MW |
4887 | qmap |= (1 << queue); |
4888 | } | |
4889 | ||
4890 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
4891 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); | |
4892 | } | |
4893 | ||
4894 | /* Disable transmit via physical egress queue | |
4895 | * - HW doesn't take descriptors from DRAM | |
4896 | */ | |
4897 | static void mvpp2_egress_disable(struct mvpp2_port *port) | |
4898 | { | |
4899 | u32 reg_data; | |
4900 | int delay; | |
4901 | int tx_port_num = mvpp2_egress_port(port); | |
4902 | ||
4903 | /* Issue stop command for active channels only */ | |
4904 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
4905 | reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & | |
4906 | MVPP2_TXP_SCHED_ENQ_MASK; | |
4907 | if (reg_data != 0) | |
4908 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, | |
4909 | (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); | |
4910 | ||
4911 | /* Wait for all Tx activity to terminate. */ | |
4912 | delay = 0; | |
4913 | do { | |
4914 | if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { | |
4915 | netdev_warn(port->dev, | |
4916 | "Tx stop timed out, status=0x%08x\n", | |
4917 | reg_data); | |
4918 | break; | |
4919 | } | |
4920 | mdelay(1); | |
4921 | delay++; | |
4922 | ||
4923 | /* Check port TX Command register that all | |
4924 | * Tx queues are stopped | |
4925 | */ | |
4926 | reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); | |
4927 | } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); | |
4928 | } | |
4929 | ||
4930 | /* Rx descriptors helper methods */ | |
4931 | ||
4932 | /* Get number of Rx descriptors occupied by received packets */ | |
4933 | static inline int | |
4934 | mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) | |
4935 | { | |
4936 | u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); | |
4937 | ||
4938 | return val & MVPP2_RXQ_OCCUPIED_MASK; | |
4939 | } | |
4940 | ||
4941 | /* Update Rx queue status with the number of occupied and available | |
4942 | * Rx descriptor slots. | |
4943 | */ | |
4944 | static inline void | |
4945 | mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, | |
4946 | int used_count, int free_count) | |
4947 | { | |
4948 | /* Decrement the number of used descriptors and increment count | |
4949 | * increment the number of free descriptors. | |
4950 | */ | |
4951 | u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); | |
4952 | ||
4953 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); | |
4954 | } | |
4955 | ||
4956 | /* Get pointer to next RX descriptor to be processed by SW */ | |
4957 | static inline struct mvpp2_rx_desc * | |
4958 | mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) | |
4959 | { | |
4960 | int rx_desc = rxq->next_desc_to_proc; | |
4961 | ||
4962 | rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); | |
4963 | prefetch(rxq->descs + rxq->next_desc_to_proc); | |
4964 | return rxq->descs + rx_desc; | |
4965 | } | |
4966 | ||
4967 | /* Set rx queue offset */ | |
4968 | static void mvpp2_rxq_offset_set(struct mvpp2_port *port, | |
4969 | int prxq, int offset) | |
4970 | { | |
4971 | u32 val; | |
4972 | ||
4973 | /* Convert offset from bytes to units of 32 bytes */ | |
4974 | offset = offset >> 5; | |
4975 | ||
4976 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); | |
4977 | val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; | |
4978 | ||
4979 | /* Offset is in */ | |
4980 | val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & | |
4981 | MVPP2_RXQ_PACKET_OFFSET_MASK); | |
4982 | ||
4983 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); | |
4984 | } | |
4985 | ||
3f518509 MW |
4986 | /* Tx descriptors helper methods */ |
4987 | ||
3f518509 MW |
4988 | /* Get pointer to next Tx descriptor to be processed (send) by HW */ |
4989 | static struct mvpp2_tx_desc * | |
4990 | mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) | |
4991 | { | |
4992 | int tx_desc = txq->next_desc_to_proc; | |
4993 | ||
4994 | txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); | |
4995 | return txq->descs + tx_desc; | |
4996 | } | |
4997 | ||
e0af22d9 TP |
4998 | /* Update HW with number of aggregated Tx descriptors to be sent |
4999 | * | |
5000 | * Called only from mvpp2_tx(), so migration is disabled, using | |
5001 | * smp_processor_id() is OK. | |
5002 | */ | |
3f518509 MW |
5003 | static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) |
5004 | { | |
5005 | /* aggregated access - relevant TXQ number is written in TX desc */ | |
a786841d TP |
5006 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
5007 | MVPP2_AGGR_TXQ_UPDATE_REG, pending); | |
3f518509 MW |
5008 | } |
5009 | ||
5010 | ||
5011 | /* Check if there are enough free descriptors in aggregated txq. | |
5012 | * If not, update the number of occupied descriptors and repeat the check. | |
e0af22d9 TP |
5013 | * |
5014 | * Called only from mvpp2_tx(), so migration is disabled, using | |
5015 | * smp_processor_id() is OK. | |
3f518509 MW |
5016 | */ |
5017 | static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, | |
5018 | struct mvpp2_tx_queue *aggr_txq, int num) | |
5019 | { | |
5020 | if ((aggr_txq->count + num) > aggr_txq->size) { | |
5021 | /* Update number of occupied aggregated Tx descriptors */ | |
5022 | int cpu = smp_processor_id(); | |
5023 | u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu)); | |
5024 | ||
5025 | aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; | |
5026 | } | |
5027 | ||
5028 | if ((aggr_txq->count + num) > aggr_txq->size) | |
5029 | return -ENOMEM; | |
5030 | ||
5031 | return 0; | |
5032 | } | |
5033 | ||
e0af22d9 TP |
5034 | /* Reserved Tx descriptors allocation request |
5035 | * | |
5036 | * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called | |
5037 | * only by mvpp2_tx(), so migration is disabled, using | |
5038 | * smp_processor_id() is OK. | |
5039 | */ | |
3f518509 MW |
5040 | static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv, |
5041 | struct mvpp2_tx_queue *txq, int num) | |
5042 | { | |
5043 | u32 val; | |
a786841d | 5044 | int cpu = smp_processor_id(); |
3f518509 MW |
5045 | |
5046 | val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; | |
a786841d | 5047 | mvpp2_percpu_write(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); |
3f518509 | 5048 | |
a786841d | 5049 | val = mvpp2_percpu_read(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); |
3f518509 MW |
5050 | |
5051 | return val & MVPP2_TXQ_RSVD_RSLT_MASK; | |
5052 | } | |
5053 | ||
5054 | /* Check if there are enough reserved descriptors for transmission. | |
5055 | * If not, request chunk of reserved descriptors and check again. | |
5056 | */ | |
5057 | static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, | |
5058 | struct mvpp2_tx_queue *txq, | |
5059 | struct mvpp2_txq_pcpu *txq_pcpu, | |
5060 | int num) | |
5061 | { | |
5062 | int req, cpu, desc_count; | |
5063 | ||
5064 | if (txq_pcpu->reserved_num >= num) | |
5065 | return 0; | |
5066 | ||
5067 | /* Not enough descriptors reserved! Update the reserved descriptor | |
5068 | * count and check again. | |
5069 | */ | |
5070 | ||
5071 | desc_count = 0; | |
5072 | /* Compute total of used descriptors */ | |
5073 | for_each_present_cpu(cpu) { | |
5074 | struct mvpp2_txq_pcpu *txq_pcpu_aux; | |
5075 | ||
5076 | txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu); | |
5077 | desc_count += txq_pcpu_aux->count; | |
5078 | desc_count += txq_pcpu_aux->reserved_num; | |
5079 | } | |
5080 | ||
5081 | req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); | |
5082 | desc_count += req; | |
5083 | ||
5084 | if (desc_count > | |
5085 | (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) | |
5086 | return -ENOMEM; | |
5087 | ||
5088 | txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); | |
5089 | ||
5090 | /* OK, the descriptor cound has been updated: check again. */ | |
5091 | if (txq_pcpu->reserved_num < num) | |
5092 | return -ENOMEM; | |
5093 | return 0; | |
5094 | } | |
5095 | ||
5096 | /* Release the last allocated Tx descriptor. Useful to handle DMA | |
5097 | * mapping failures in the Tx path. | |
5098 | */ | |
5099 | static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) | |
5100 | { | |
5101 | if (txq->next_desc_to_proc == 0) | |
5102 | txq->next_desc_to_proc = txq->last_desc - 1; | |
5103 | else | |
5104 | txq->next_desc_to_proc--; | |
5105 | } | |
5106 | ||
5107 | /* Set Tx descriptors fields relevant for CSUM calculation */ | |
5108 | static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto, | |
5109 | int ip_hdr_len, int l4_proto) | |
5110 | { | |
5111 | u32 command; | |
5112 | ||
5113 | /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
5114 | * G_L4_chk, L4_type required only for checksum calculation | |
5115 | */ | |
5116 | command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); | |
5117 | command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); | |
5118 | command |= MVPP2_TXD_IP_CSUM_DISABLE; | |
5119 | ||
5120 | if (l3_proto == swab16(ETH_P_IP)) { | |
5121 | command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ | |
5122 | command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ | |
5123 | } else { | |
5124 | command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ | |
5125 | } | |
5126 | ||
5127 | if (l4_proto == IPPROTO_TCP) { | |
5128 | command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ | |
5129 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
5130 | } else if (l4_proto == IPPROTO_UDP) { | |
5131 | command |= MVPP2_TXD_L4_UDP; /* enable UDP */ | |
5132 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
5133 | } else { | |
5134 | command |= MVPP2_TXD_L4_CSUM_NOT; | |
5135 | } | |
5136 | ||
5137 | return command; | |
5138 | } | |
5139 | ||
5140 | /* Get number of sent descriptors and decrement counter. | |
5141 | * The number of sent descriptors is returned. | |
5142 | * Per-CPU access | |
e0af22d9 TP |
5143 | * |
5144 | * Called only from mvpp2_txq_done(), called from mvpp2_tx() | |
5145 | * (migration disabled) and from the TX completion tasklet (migration | |
5146 | * disabled) so using smp_processor_id() is OK. | |
3f518509 MW |
5147 | */ |
5148 | static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, | |
5149 | struct mvpp2_tx_queue *txq) | |
5150 | { | |
5151 | u32 val; | |
5152 | ||
5153 | /* Reading status reg resets transmitted descriptor counter */ | |
a786841d TP |
5154 | val = mvpp2_percpu_read(port->priv, smp_processor_id(), |
5155 | MVPP2_TXQ_SENT_REG(txq->id)); | |
3f518509 MW |
5156 | |
5157 | return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> | |
5158 | MVPP2_TRANSMITTED_COUNT_OFFSET; | |
5159 | } | |
5160 | ||
e0af22d9 TP |
5161 | /* Called through on_each_cpu(), so runs on all CPUs, with migration |
5162 | * disabled, therefore using smp_processor_id() is OK. | |
5163 | */ | |
3f518509 MW |
5164 | static void mvpp2_txq_sent_counter_clear(void *arg) |
5165 | { | |
5166 | struct mvpp2_port *port = arg; | |
5167 | int queue; | |
5168 | ||
09f83975 | 5169 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5170 | int id = port->txqs[queue]->id; |
5171 | ||
a786841d TP |
5172 | mvpp2_percpu_read(port->priv, smp_processor_id(), |
5173 | MVPP2_TXQ_SENT_REG(id)); | |
3f518509 MW |
5174 | } |
5175 | } | |
5176 | ||
5177 | /* Set max sizes for Tx queues */ | |
5178 | static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) | |
5179 | { | |
5180 | u32 val, size, mtu; | |
5181 | int txq, tx_port_num; | |
5182 | ||
5183 | mtu = port->pkt_size * 8; | |
5184 | if (mtu > MVPP2_TXP_MTU_MAX) | |
5185 | mtu = MVPP2_TXP_MTU_MAX; | |
5186 | ||
5187 | /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ | |
5188 | mtu = 3 * mtu; | |
5189 | ||
5190 | /* Indirect access to registers */ | |
5191 | tx_port_num = mvpp2_egress_port(port); | |
5192 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5193 | ||
5194 | /* Set MTU */ | |
5195 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); | |
5196 | val &= ~MVPP2_TXP_MTU_MAX; | |
5197 | val |= mtu; | |
5198 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); | |
5199 | ||
5200 | /* TXP token size and all TXQs token size must be larger that MTU */ | |
5201 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); | |
5202 | size = val & MVPP2_TXP_TOKEN_SIZE_MAX; | |
5203 | if (size < mtu) { | |
5204 | size = mtu; | |
5205 | val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; | |
5206 | val |= size; | |
5207 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
5208 | } | |
5209 | ||
09f83975 | 5210 | for (txq = 0; txq < port->ntxqs; txq++) { |
3f518509 MW |
5211 | val = mvpp2_read(port->priv, |
5212 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); | |
5213 | size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5214 | ||
5215 | if (size < mtu) { | |
5216 | size = mtu; | |
5217 | val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5218 | val |= size; | |
5219 | mvpp2_write(port->priv, | |
5220 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), | |
5221 | val); | |
5222 | } | |
5223 | } | |
5224 | } | |
5225 | ||
5226 | /* Set the number of packets that will be received before Rx interrupt | |
5227 | * will be generated by HW. | |
5228 | */ | |
5229 | static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 5230 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5231 | { |
a704bb5c | 5232 | int cpu = get_cpu(); |
a786841d | 5233 | |
f8b0d5f8 TP |
5234 | if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) |
5235 | rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; | |
3f518509 | 5236 | |
a786841d TP |
5237 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
5238 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG, | |
5239 | rxq->pkts_coal); | |
a704bb5c TP |
5240 | |
5241 | put_cpu(); | |
3f518509 MW |
5242 | } |
5243 | ||
213f428f TP |
5244 | /* For some reason in the LSP this is done on each CPU. Why ? */ |
5245 | static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, | |
5246 | struct mvpp2_tx_queue *txq) | |
5247 | { | |
5248 | int cpu = get_cpu(); | |
5249 | u32 val; | |
5250 | ||
5251 | if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) | |
5252 | txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; | |
5253 | ||
5254 | val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); | |
5255 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); | |
5256 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val); | |
5257 | ||
5258 | put_cpu(); | |
5259 | } | |
5260 | ||
ab42676a TP |
5261 | static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) |
5262 | { | |
5263 | u64 tmp = (u64)clk_hz * usec; | |
5264 | ||
5265 | do_div(tmp, USEC_PER_SEC); | |
5266 | ||
5267 | return tmp > U32_MAX ? U32_MAX : tmp; | |
5268 | } | |
5269 | ||
5270 | static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) | |
5271 | { | |
5272 | u64 tmp = (u64)cycles * USEC_PER_SEC; | |
5273 | ||
5274 | do_div(tmp, clk_hz); | |
5275 | ||
5276 | return tmp > U32_MAX ? U32_MAX : tmp; | |
5277 | } | |
5278 | ||
3f518509 MW |
5279 | /* Set the time delay in usec before Rx interrupt */ |
5280 | static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 5281 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5282 | { |
ab42676a TP |
5283 | unsigned long freq = port->priv->tclk; |
5284 | u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5285 | ||
5286 | if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { | |
5287 | rxq->time_coal = | |
5288 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); | |
5289 | ||
5290 | /* re-evaluate to get actual register value */ | |
5291 | val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5292 | } | |
3f518509 | 5293 | |
3f518509 | 5294 | mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); |
3f518509 MW |
5295 | } |
5296 | ||
213f428f TP |
5297 | static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) |
5298 | { | |
5299 | unsigned long freq = port->priv->tclk; | |
5300 | u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5301 | ||
5302 | if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { | |
5303 | port->tx_time_coal = | |
5304 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); | |
5305 | ||
5306 | /* re-evaluate to get actual register value */ | |
5307 | val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5308 | } | |
5309 | ||
5310 | mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); | |
5311 | } | |
5312 | ||
3f518509 MW |
5313 | /* Free Tx queue skbuffs */ |
5314 | static void mvpp2_txq_bufs_free(struct mvpp2_port *port, | |
5315 | struct mvpp2_tx_queue *txq, | |
5316 | struct mvpp2_txq_pcpu *txq_pcpu, int num) | |
5317 | { | |
5318 | int i; | |
5319 | ||
5320 | for (i = 0; i < num; i++) { | |
8354491c TP |
5321 | struct mvpp2_txq_pcpu_buf *tx_buf = |
5322 | txq_pcpu->buffs + txq_pcpu->txq_get_index; | |
3f518509 | 5323 | |
20396136 | 5324 | dma_unmap_single(port->dev->dev.parent, tx_buf->dma, |
8354491c | 5325 | tx_buf->size, DMA_TO_DEVICE); |
36fb7435 TP |
5326 | if (tx_buf->skb) |
5327 | dev_kfree_skb_any(tx_buf->skb); | |
5328 | ||
5329 | mvpp2_txq_inc_get(txq_pcpu); | |
3f518509 MW |
5330 | } |
5331 | } | |
5332 | ||
5333 | static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, | |
5334 | u32 cause) | |
5335 | { | |
5336 | int queue = fls(cause) - 1; | |
5337 | ||
5338 | return port->rxqs[queue]; | |
5339 | } | |
5340 | ||
5341 | static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, | |
5342 | u32 cause) | |
5343 | { | |
edc660fa | 5344 | int queue = fls(cause) - 1; |
3f518509 MW |
5345 | |
5346 | return port->txqs[queue]; | |
5347 | } | |
5348 | ||
5349 | /* Handle end of transmission */ | |
5350 | static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, | |
5351 | struct mvpp2_txq_pcpu *txq_pcpu) | |
5352 | { | |
5353 | struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); | |
5354 | int tx_done; | |
5355 | ||
5356 | if (txq_pcpu->cpu != smp_processor_id()) | |
5357 | netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); | |
5358 | ||
5359 | tx_done = mvpp2_txq_sent_desc_proc(port, txq); | |
5360 | if (!tx_done) | |
5361 | return; | |
5362 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); | |
5363 | ||
5364 | txq_pcpu->count -= tx_done; | |
5365 | ||
5366 | if (netif_tx_queue_stopped(nq)) | |
5367 | if (txq_pcpu->size - txq_pcpu->count >= MAX_SKB_FRAGS + 1) | |
5368 | netif_tx_wake_queue(nq); | |
5369 | } | |
5370 | ||
213f428f TP |
5371 | static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, |
5372 | int cpu) | |
edc660fa MW |
5373 | { |
5374 | struct mvpp2_tx_queue *txq; | |
5375 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5376 | unsigned int tx_todo = 0; | |
5377 | ||
5378 | while (cause) { | |
5379 | txq = mvpp2_get_tx_queue(port, cause); | |
5380 | if (!txq) | |
5381 | break; | |
5382 | ||
213f428f | 5383 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); |
edc660fa MW |
5384 | |
5385 | if (txq_pcpu->count) { | |
5386 | mvpp2_txq_done(port, txq, txq_pcpu); | |
5387 | tx_todo += txq_pcpu->count; | |
5388 | } | |
5389 | ||
5390 | cause &= ~(1 << txq->log_id); | |
5391 | } | |
5392 | return tx_todo; | |
5393 | } | |
5394 | ||
3f518509 MW |
5395 | /* Rx/Tx queue initialization/cleanup methods */ |
5396 | ||
5397 | /* Allocate and initialize descriptors for aggr TXQ */ | |
5398 | static int mvpp2_aggr_txq_init(struct platform_device *pdev, | |
85affd7e | 5399 | struct mvpp2_tx_queue *aggr_txq, int cpu, |
3f518509 MW |
5400 | struct mvpp2 *priv) |
5401 | { | |
b02f31fb TP |
5402 | u32 txq_dma; |
5403 | ||
3f518509 MW |
5404 | /* Allocate memory for TX descriptors */ |
5405 | aggr_txq->descs = dma_alloc_coherent(&pdev->dev, | |
85affd7e | 5406 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, |
20396136 | 5407 | &aggr_txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5408 | if (!aggr_txq->descs) |
5409 | return -ENOMEM; | |
5410 | ||
3f518509 MW |
5411 | aggr_txq->last_desc = aggr_txq->size - 1; |
5412 | ||
5413 | /* Aggr TXQ no reset WA */ | |
5414 | aggr_txq->next_desc_to_proc = mvpp2_read(priv, | |
5415 | MVPP2_AGGR_TXQ_INDEX_REG(cpu)); | |
5416 | ||
b02f31fb TP |
5417 | /* Set Tx descriptors queue starting address indirect |
5418 | * access | |
5419 | */ | |
5420 | if (priv->hw_version == MVPP21) | |
5421 | txq_dma = aggr_txq->descs_dma; | |
5422 | else | |
5423 | txq_dma = aggr_txq->descs_dma >> | |
5424 | MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; | |
5425 | ||
5426 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); | |
85affd7e AT |
5427 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), |
5428 | MVPP2_AGGR_TXQ_SIZE); | |
3f518509 MW |
5429 | |
5430 | return 0; | |
5431 | } | |
5432 | ||
5433 | /* Create a specified Rx queue */ | |
5434 | static int mvpp2_rxq_init(struct mvpp2_port *port, | |
5435 | struct mvpp2_rx_queue *rxq) | |
5436 | ||
5437 | { | |
b02f31fb | 5438 | u32 rxq_dma; |
a786841d | 5439 | int cpu; |
b02f31fb | 5440 | |
3f518509 MW |
5441 | rxq->size = port->rx_ring_size; |
5442 | ||
5443 | /* Allocate memory for RX descriptors */ | |
5444 | rxq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
5445 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5446 | &rxq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5447 | if (!rxq->descs) |
5448 | return -ENOMEM; | |
5449 | ||
3f518509 MW |
5450 | rxq->last_desc = rxq->size - 1; |
5451 | ||
5452 | /* Zero occupied and non-occupied counters - direct access */ | |
5453 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
5454 | ||
5455 | /* Set Rx descriptors queue starting address - indirect access */ | |
a704bb5c | 5456 | cpu = get_cpu(); |
a786841d | 5457 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
b02f31fb TP |
5458 | if (port->priv->hw_version == MVPP21) |
5459 | rxq_dma = rxq->descs_dma; | |
5460 | else | |
5461 | rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; | |
a786841d TP |
5462 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); |
5463 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); | |
5464 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0); | |
a704bb5c | 5465 | put_cpu(); |
3f518509 MW |
5466 | |
5467 | /* Set Offset */ | |
5468 | mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); | |
5469 | ||
5470 | /* Set coalescing pkts and time */ | |
d63f9e41 TP |
5471 | mvpp2_rx_pkts_coal_set(port, rxq); |
5472 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
5473 | |
5474 | /* Add number of descriptors ready for receiving packets */ | |
5475 | mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); | |
5476 | ||
5477 | return 0; | |
5478 | } | |
5479 | ||
5480 | /* Push packets received by the RXQ to BM pool */ | |
5481 | static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, | |
5482 | struct mvpp2_rx_queue *rxq) | |
5483 | { | |
5484 | int rx_received, i; | |
5485 | ||
5486 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
5487 | if (!rx_received) | |
5488 | return; | |
5489 | ||
5490 | for (i = 0; i < rx_received; i++) { | |
5491 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); | |
56b8aae9 TP |
5492 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
5493 | int pool; | |
5494 | ||
5495 | pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> | |
5496 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 5497 | |
7d7627ba | 5498 | mvpp2_bm_pool_put(port, pool, |
ac3dd277 TP |
5499 | mvpp2_rxdesc_dma_addr_get(port, rx_desc), |
5500 | mvpp2_rxdesc_cookie_get(port, rx_desc)); | |
3f518509 MW |
5501 | } |
5502 | mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); | |
5503 | } | |
5504 | ||
5505 | /* Cleanup Rx queue */ | |
5506 | static void mvpp2_rxq_deinit(struct mvpp2_port *port, | |
5507 | struct mvpp2_rx_queue *rxq) | |
5508 | { | |
a786841d TP |
5509 | int cpu; |
5510 | ||
3f518509 MW |
5511 | mvpp2_rxq_drop_pkts(port, rxq); |
5512 | ||
5513 | if (rxq->descs) | |
5514 | dma_free_coherent(port->dev->dev.parent, | |
5515 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
5516 | rxq->descs, | |
20396136 | 5517 | rxq->descs_dma); |
3f518509 MW |
5518 | |
5519 | rxq->descs = NULL; | |
5520 | rxq->last_desc = 0; | |
5521 | rxq->next_desc_to_proc = 0; | |
20396136 | 5522 | rxq->descs_dma = 0; |
3f518509 MW |
5523 | |
5524 | /* Clear Rx descriptors queue starting address and size; | |
5525 | * free descriptor number | |
5526 | */ | |
5527 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
a704bb5c | 5528 | cpu = get_cpu(); |
a786841d TP |
5529 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
5530 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0); | |
5531 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 5532 | put_cpu(); |
3f518509 MW |
5533 | } |
5534 | ||
5535 | /* Create and initialize a Tx queue */ | |
5536 | static int mvpp2_txq_init(struct mvpp2_port *port, | |
5537 | struct mvpp2_tx_queue *txq) | |
5538 | { | |
5539 | u32 val; | |
5540 | int cpu, desc, desc_per_txq, tx_port_num; | |
5541 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5542 | ||
5543 | txq->size = port->tx_ring_size; | |
5544 | ||
5545 | /* Allocate memory for Tx descriptors */ | |
5546 | txq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
5547 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5548 | &txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5549 | if (!txq->descs) |
5550 | return -ENOMEM; | |
5551 | ||
3f518509 MW |
5552 | txq->last_desc = txq->size - 1; |
5553 | ||
5554 | /* Set Tx descriptors queue starting address - indirect access */ | |
a704bb5c | 5555 | cpu = get_cpu(); |
a786841d TP |
5556 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5557 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, | |
5558 | txq->descs_dma); | |
5559 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, | |
5560 | txq->size & MVPP2_TXQ_DESC_SIZE_MASK); | |
5561 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0); | |
5562 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG, | |
5563 | txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); | |
5564 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG); | |
3f518509 | 5565 | val &= ~MVPP2_TXQ_PENDING_MASK; |
a786841d | 5566 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val); |
3f518509 MW |
5567 | |
5568 | /* Calculate base address in prefetch buffer. We reserve 16 descriptors | |
5569 | * for each existing TXQ. | |
5570 | * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT | |
5571 | * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS | |
5572 | */ | |
5573 | desc_per_txq = 16; | |
5574 | desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + | |
5575 | (txq->log_id * desc_per_txq); | |
5576 | ||
a786841d TP |
5577 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, |
5578 | MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | | |
5579 | MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); | |
a704bb5c | 5580 | put_cpu(); |
3f518509 MW |
5581 | |
5582 | /* WRR / EJP configuration - indirect access */ | |
5583 | tx_port_num = mvpp2_egress_port(port); | |
5584 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5585 | ||
5586 | val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); | |
5587 | val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; | |
5588 | val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); | |
5589 | val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; | |
5590 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); | |
5591 | ||
5592 | val = MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5593 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), | |
5594 | val); | |
5595 | ||
5596 | for_each_present_cpu(cpu) { | |
5597 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
5598 | txq_pcpu->size = txq->size; | |
02c91ece ME |
5599 | txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, |
5600 | sizeof(*txq_pcpu->buffs), | |
5601 | GFP_KERNEL); | |
8354491c | 5602 | if (!txq_pcpu->buffs) |
20b1e16e | 5603 | goto cleanup; |
3f518509 MW |
5604 | |
5605 | txq_pcpu->count = 0; | |
5606 | txq_pcpu->reserved_num = 0; | |
5607 | txq_pcpu->txq_put_index = 0; | |
5608 | txq_pcpu->txq_get_index = 0; | |
186cd4d4 AT |
5609 | |
5610 | txq_pcpu->tso_headers = | |
5611 | dma_alloc_coherent(port->dev->dev.parent, | |
5612 | MVPP2_AGGR_TXQ_SIZE * TSO_HEADER_SIZE, | |
5613 | &txq_pcpu->tso_headers_dma, | |
5614 | GFP_KERNEL); | |
5615 | if (!txq_pcpu->tso_headers) | |
5616 | goto cleanup; | |
3f518509 MW |
5617 | } |
5618 | ||
5619 | return 0; | |
20b1e16e | 5620 | cleanup: |
71ce391d MW |
5621 | for_each_present_cpu(cpu) { |
5622 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8354491c | 5623 | kfree(txq_pcpu->buffs); |
186cd4d4 AT |
5624 | |
5625 | dma_free_coherent(port->dev->dev.parent, | |
5626 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, | |
5627 | txq_pcpu->tso_headers, | |
5628 | txq_pcpu->tso_headers_dma); | |
71ce391d MW |
5629 | } |
5630 | ||
5631 | dma_free_coherent(port->dev->dev.parent, | |
5632 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5633 | txq->descs, txq->descs_dma); |
71ce391d MW |
5634 | |
5635 | return -ENOMEM; | |
3f518509 MW |
5636 | } |
5637 | ||
5638 | /* Free allocated TXQ resources */ | |
5639 | static void mvpp2_txq_deinit(struct mvpp2_port *port, | |
5640 | struct mvpp2_tx_queue *txq) | |
5641 | { | |
5642 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5643 | int cpu; | |
5644 | ||
5645 | for_each_present_cpu(cpu) { | |
5646 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8354491c | 5647 | kfree(txq_pcpu->buffs); |
186cd4d4 AT |
5648 | |
5649 | dma_free_coherent(port->dev->dev.parent, | |
5650 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, | |
5651 | txq_pcpu->tso_headers, | |
5652 | txq_pcpu->tso_headers_dma); | |
3f518509 MW |
5653 | } |
5654 | ||
5655 | if (txq->descs) | |
5656 | dma_free_coherent(port->dev->dev.parent, | |
5657 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5658 | txq->descs, txq->descs_dma); |
3f518509 MW |
5659 | |
5660 | txq->descs = NULL; | |
5661 | txq->last_desc = 0; | |
5662 | txq->next_desc_to_proc = 0; | |
20396136 | 5663 | txq->descs_dma = 0; |
3f518509 MW |
5664 | |
5665 | /* Set minimum bandwidth for disabled TXQs */ | |
5666 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); | |
5667 | ||
5668 | /* Set Tx descriptors queue starting address and size */ | |
a704bb5c | 5669 | cpu = get_cpu(); |
a786841d TP |
5670 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5671 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0); | |
5672 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 5673 | put_cpu(); |
3f518509 MW |
5674 | } |
5675 | ||
5676 | /* Cleanup Tx ports */ | |
5677 | static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) | |
5678 | { | |
5679 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5680 | int delay, pending, cpu; | |
5681 | u32 val; | |
5682 | ||
a704bb5c | 5683 | cpu = get_cpu(); |
a786841d TP |
5684 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5685 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG); | |
3f518509 | 5686 | val |= MVPP2_TXQ_DRAIN_EN_MASK; |
a786841d | 5687 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
3f518509 MW |
5688 | |
5689 | /* The napi queue has been stopped so wait for all packets | |
5690 | * to be transmitted. | |
5691 | */ | |
5692 | delay = 0; | |
5693 | do { | |
5694 | if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { | |
5695 | netdev_warn(port->dev, | |
5696 | "port %d: cleaning queue %d timed out\n", | |
5697 | port->id, txq->log_id); | |
5698 | break; | |
5699 | } | |
5700 | mdelay(1); | |
5701 | delay++; | |
5702 | ||
a786841d TP |
5703 | pending = mvpp2_percpu_read(port->priv, cpu, |
5704 | MVPP2_TXQ_PENDING_REG); | |
5705 | pending &= MVPP2_TXQ_PENDING_MASK; | |
3f518509 MW |
5706 | } while (pending); |
5707 | ||
5708 | val &= ~MVPP2_TXQ_DRAIN_EN_MASK; | |
a786841d | 5709 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
a704bb5c | 5710 | put_cpu(); |
3f518509 MW |
5711 | |
5712 | for_each_present_cpu(cpu) { | |
5713 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
5714 | ||
5715 | /* Release all packets */ | |
5716 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); | |
5717 | ||
5718 | /* Reset queue */ | |
5719 | txq_pcpu->count = 0; | |
5720 | txq_pcpu->txq_put_index = 0; | |
5721 | txq_pcpu->txq_get_index = 0; | |
5722 | } | |
5723 | } | |
5724 | ||
5725 | /* Cleanup all Tx queues */ | |
5726 | static void mvpp2_cleanup_txqs(struct mvpp2_port *port) | |
5727 | { | |
5728 | struct mvpp2_tx_queue *txq; | |
5729 | int queue; | |
5730 | u32 val; | |
5731 | ||
5732 | val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); | |
5733 | ||
5734 | /* Reset Tx ports and delete Tx queues */ | |
5735 | val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
5736 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
5737 | ||
09f83975 | 5738 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5739 | txq = port->txqs[queue]; |
5740 | mvpp2_txq_clean(port, txq); | |
5741 | mvpp2_txq_deinit(port, txq); | |
5742 | } | |
5743 | ||
5744 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); | |
5745 | ||
5746 | val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
5747 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
5748 | } | |
5749 | ||
5750 | /* Cleanup all Rx queues */ | |
5751 | static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) | |
5752 | { | |
5753 | int queue; | |
5754 | ||
09f83975 | 5755 | for (queue = 0; queue < port->nrxqs; queue++) |
3f518509 MW |
5756 | mvpp2_rxq_deinit(port, port->rxqs[queue]); |
5757 | } | |
5758 | ||
5759 | /* Init all Rx queues for port */ | |
5760 | static int mvpp2_setup_rxqs(struct mvpp2_port *port) | |
5761 | { | |
5762 | int queue, err; | |
5763 | ||
09f83975 | 5764 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
5765 | err = mvpp2_rxq_init(port, port->rxqs[queue]); |
5766 | if (err) | |
5767 | goto err_cleanup; | |
5768 | } | |
5769 | return 0; | |
5770 | ||
5771 | err_cleanup: | |
5772 | mvpp2_cleanup_rxqs(port); | |
5773 | return err; | |
5774 | } | |
5775 | ||
5776 | /* Init all tx queues for port */ | |
5777 | static int mvpp2_setup_txqs(struct mvpp2_port *port) | |
5778 | { | |
5779 | struct mvpp2_tx_queue *txq; | |
5780 | int queue, err; | |
5781 | ||
09f83975 | 5782 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5783 | txq = port->txqs[queue]; |
5784 | err = mvpp2_txq_init(port, txq); | |
5785 | if (err) | |
5786 | goto err_cleanup; | |
5787 | } | |
5788 | ||
213f428f TP |
5789 | if (port->has_tx_irqs) { |
5790 | mvpp2_tx_time_coal_set(port); | |
5791 | for (queue = 0; queue < port->ntxqs; queue++) { | |
5792 | txq = port->txqs[queue]; | |
5793 | mvpp2_tx_pkts_coal_set(port, txq); | |
5794 | } | |
5795 | } | |
5796 | ||
3f518509 MW |
5797 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); |
5798 | return 0; | |
5799 | ||
5800 | err_cleanup: | |
5801 | mvpp2_cleanup_txqs(port); | |
5802 | return err; | |
5803 | } | |
5804 | ||
5805 | /* The callback for per-port interrupt */ | |
5806 | static irqreturn_t mvpp2_isr(int irq, void *dev_id) | |
5807 | { | |
591f4cfa | 5808 | struct mvpp2_queue_vector *qv = dev_id; |
3f518509 | 5809 | |
591f4cfa | 5810 | mvpp2_qvec_interrupt_disable(qv); |
3f518509 | 5811 | |
591f4cfa | 5812 | napi_schedule(&qv->napi); |
3f518509 MW |
5813 | |
5814 | return IRQ_HANDLED; | |
5815 | } | |
5816 | ||
fd3651b2 AT |
5817 | /* Per-port interrupt for link status changes */ |
5818 | static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) | |
5819 | { | |
5820 | struct mvpp2_port *port = (struct mvpp2_port *)dev_id; | |
5821 | struct net_device *dev = port->dev; | |
5822 | bool event = false, link = false; | |
5823 | u32 val; | |
5824 | ||
5825 | mvpp22_gop_mask_irq(port); | |
5826 | ||
5827 | if (port->gop_id == 0 && | |
5828 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) { | |
5829 | val = readl(port->base + MVPP22_XLG_INT_STAT); | |
5830 | if (val & MVPP22_XLG_INT_STAT_LINK) { | |
5831 | event = true; | |
5832 | val = readl(port->base + MVPP22_XLG_STATUS); | |
5833 | if (val & MVPP22_XLG_STATUS_LINK_UP) | |
5834 | link = true; | |
5835 | } | |
5836 | } else if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
5837 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
5838 | val = readl(port->base + MVPP22_GMAC_INT_STAT); | |
5839 | if (val & MVPP22_GMAC_INT_STAT_LINK) { | |
5840 | event = true; | |
5841 | val = readl(port->base + MVPP2_GMAC_STATUS0); | |
5842 | if (val & MVPP2_GMAC_STATUS0_LINK_UP) | |
5843 | link = true; | |
5844 | } | |
5845 | } | |
5846 | ||
5847 | if (!netif_running(dev) || !event) | |
5848 | goto handled; | |
5849 | ||
5850 | if (link) { | |
5851 | mvpp2_interrupts_enable(port); | |
5852 | ||
5853 | mvpp2_egress_enable(port); | |
5854 | mvpp2_ingress_enable(port); | |
5855 | netif_carrier_on(dev); | |
5856 | netif_tx_wake_all_queues(dev); | |
5857 | } else { | |
5858 | netif_tx_stop_all_queues(dev); | |
5859 | netif_carrier_off(dev); | |
5860 | mvpp2_ingress_disable(port); | |
5861 | mvpp2_egress_disable(port); | |
5862 | ||
5863 | mvpp2_interrupts_disable(port); | |
5864 | } | |
5865 | ||
5866 | handled: | |
5867 | mvpp22_gop_unmask_irq(port); | |
5868 | return IRQ_HANDLED; | |
5869 | } | |
5870 | ||
65a2c09a AT |
5871 | static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port, |
5872 | struct phy_device *phydev) | |
5873 | { | |
5874 | u32 val; | |
5875 | ||
5876 | if (port->phy_interface != PHY_INTERFACE_MODE_RGMII && | |
5877 | port->phy_interface != PHY_INTERFACE_MODE_RGMII_ID && | |
5878 | port->phy_interface != PHY_INTERFACE_MODE_RGMII_RXID && | |
5879 | port->phy_interface != PHY_INTERFACE_MODE_RGMII_TXID && | |
5880 | port->phy_interface != PHY_INTERFACE_MODE_SGMII) | |
5881 | return; | |
5882 | ||
5883 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5884 | val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | | |
5885 | MVPP2_GMAC_CONFIG_GMII_SPEED | | |
5886 | MVPP2_GMAC_CONFIG_FULL_DUPLEX | | |
5887 | MVPP2_GMAC_AN_SPEED_EN | | |
5888 | MVPP2_GMAC_AN_DUPLEX_EN); | |
5889 | ||
5890 | if (phydev->duplex) | |
5891 | val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; | |
5892 | ||
5893 | if (phydev->speed == SPEED_1000) | |
5894 | val |= MVPP2_GMAC_CONFIG_GMII_SPEED; | |
5895 | else if (phydev->speed == SPEED_100) | |
5896 | val |= MVPP2_GMAC_CONFIG_MII_SPEED; | |
5897 | ||
5898 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
65a2c09a AT |
5899 | } |
5900 | ||
3f518509 MW |
5901 | /* Adjust link */ |
5902 | static void mvpp2_link_event(struct net_device *dev) | |
5903 | { | |
5904 | struct mvpp2_port *port = netdev_priv(dev); | |
8e07269d | 5905 | struct phy_device *phydev = dev->phydev; |
89273bc0 | 5906 | bool link_reconfigured = false; |
3f518509 MW |
5907 | u32 val; |
5908 | ||
5909 | if (phydev->link) { | |
89273bc0 AT |
5910 | if (port->phy_interface != phydev->interface && port->comphy) { |
5911 | /* disable current port for reconfiguration */ | |
5912 | mvpp2_interrupts_disable(port); | |
5913 | netif_carrier_off(port->dev); | |
5914 | mvpp2_port_disable(port); | |
5915 | phy_power_off(port->comphy); | |
5916 | ||
5917 | /* comphy reconfiguration */ | |
5918 | port->phy_interface = phydev->interface; | |
5919 | mvpp22_comphy_init(port); | |
5920 | ||
5921 | /* gop/mac reconfiguration */ | |
5922 | mvpp22_gop_init(port); | |
5923 | mvpp2_port_mii_set(port); | |
5924 | ||
5925 | link_reconfigured = true; | |
5926 | } | |
5927 | ||
3f518509 MW |
5928 | if ((port->speed != phydev->speed) || |
5929 | (port->duplex != phydev->duplex)) { | |
65a2c09a | 5930 | mvpp2_gmac_set_autoneg(port, phydev); |
3f518509 MW |
5931 | |
5932 | port->duplex = phydev->duplex; | |
5933 | port->speed = phydev->speed; | |
5934 | } | |
5935 | } | |
5936 | ||
89273bc0 | 5937 | if (phydev->link != port->link || link_reconfigured) { |
3f518509 | 5938 | port->link = phydev->link; |
3f518509 | 5939 | |
3f518509 | 5940 | if (phydev->link) { |
65a2c09a AT |
5941 | if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || |
5942 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
5943 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
5944 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID || | |
5945 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
5946 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5947 | val |= (MVPP2_GMAC_FORCE_LINK_PASS | | |
5948 | MVPP2_GMAC_FORCE_LINK_DOWN); | |
5949 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5950 | } | |
f55744ad AT |
5951 | |
5952 | mvpp2_interrupts_enable(port); | |
5953 | mvpp2_port_enable(port); | |
5954 | ||
3f518509 MW |
5955 | mvpp2_egress_enable(port); |
5956 | mvpp2_ingress_enable(port); | |
f55744ad AT |
5957 | netif_carrier_on(dev); |
5958 | netif_tx_wake_all_queues(dev); | |
3f518509 | 5959 | } else { |
968b211c AT |
5960 | port->duplex = -1; |
5961 | port->speed = 0; | |
5962 | ||
f55744ad AT |
5963 | netif_tx_stop_all_queues(dev); |
5964 | netif_carrier_off(dev); | |
3f518509 MW |
5965 | mvpp2_ingress_disable(port); |
5966 | mvpp2_egress_disable(port); | |
f55744ad AT |
5967 | |
5968 | mvpp2_port_disable(port); | |
5969 | mvpp2_interrupts_disable(port); | |
3f518509 | 5970 | } |
968b211c | 5971 | |
3f518509 MW |
5972 | phy_print_status(phydev); |
5973 | } | |
5974 | } | |
5975 | ||
edc660fa MW |
5976 | static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) |
5977 | { | |
5978 | ktime_t interval; | |
5979 | ||
5980 | if (!port_pcpu->timer_scheduled) { | |
5981 | port_pcpu->timer_scheduled = true; | |
8b0e1953 | 5982 | interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; |
edc660fa MW |
5983 | hrtimer_start(&port_pcpu->tx_done_timer, interval, |
5984 | HRTIMER_MODE_REL_PINNED); | |
5985 | } | |
5986 | } | |
5987 | ||
5988 | static void mvpp2_tx_proc_cb(unsigned long data) | |
5989 | { | |
5990 | struct net_device *dev = (struct net_device *)data; | |
5991 | struct mvpp2_port *port = netdev_priv(dev); | |
5992 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); | |
5993 | unsigned int tx_todo, cause; | |
5994 | ||
5995 | if (!netif_running(dev)) | |
5996 | return; | |
5997 | port_pcpu->timer_scheduled = false; | |
5998 | ||
5999 | /* Process all the Tx queues */ | |
09f83975 | 6000 | cause = (1 << port->ntxqs) - 1; |
213f428f | 6001 | tx_todo = mvpp2_tx_done(port, cause, smp_processor_id()); |
edc660fa MW |
6002 | |
6003 | /* Set the timer in case not all the packets were processed */ | |
6004 | if (tx_todo) | |
6005 | mvpp2_timer_set(port_pcpu); | |
6006 | } | |
6007 | ||
6008 | static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) | |
6009 | { | |
6010 | struct mvpp2_port_pcpu *port_pcpu = container_of(timer, | |
6011 | struct mvpp2_port_pcpu, | |
6012 | tx_done_timer); | |
6013 | ||
6014 | tasklet_schedule(&port_pcpu->tx_done_tasklet); | |
6015 | ||
6016 | return HRTIMER_NORESTART; | |
6017 | } | |
6018 | ||
3f518509 MW |
6019 | /* Main RX/TX processing routines */ |
6020 | ||
6021 | /* Display more error info */ | |
6022 | static void mvpp2_rx_error(struct mvpp2_port *port, | |
6023 | struct mvpp2_rx_desc *rx_desc) | |
6024 | { | |
ac3dd277 TP |
6025 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
6026 | size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); | |
3f518509 MW |
6027 | |
6028 | switch (status & MVPP2_RXD_ERR_CODE_MASK) { | |
6029 | case MVPP2_RXD_ERR_CRC: | |
ac3dd277 TP |
6030 | netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", |
6031 | status, sz); | |
3f518509 MW |
6032 | break; |
6033 | case MVPP2_RXD_ERR_OVERRUN: | |
ac3dd277 TP |
6034 | netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", |
6035 | status, sz); | |
3f518509 MW |
6036 | break; |
6037 | case MVPP2_RXD_ERR_RESOURCE: | |
ac3dd277 TP |
6038 | netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", |
6039 | status, sz); | |
3f518509 MW |
6040 | break; |
6041 | } | |
6042 | } | |
6043 | ||
6044 | /* Handle RX checksum offload */ | |
6045 | static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, | |
6046 | struct sk_buff *skb) | |
6047 | { | |
6048 | if (((status & MVPP2_RXD_L3_IP4) && | |
6049 | !(status & MVPP2_RXD_IP4_HEADER_ERR)) || | |
6050 | (status & MVPP2_RXD_L3_IP6)) | |
6051 | if (((status & MVPP2_RXD_L4_UDP) || | |
6052 | (status & MVPP2_RXD_L4_TCP)) && | |
6053 | (status & MVPP2_RXD_L4_CSUM_OK)) { | |
6054 | skb->csum = 0; | |
6055 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
6056 | return; | |
6057 | } | |
6058 | ||
6059 | skb->ip_summed = CHECKSUM_NONE; | |
6060 | } | |
6061 | ||
6062 | /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ | |
6063 | static int mvpp2_rx_refill(struct mvpp2_port *port, | |
56b8aae9 | 6064 | struct mvpp2_bm_pool *bm_pool, int pool) |
3f518509 | 6065 | { |
20396136 | 6066 | dma_addr_t dma_addr; |
4e4a105f | 6067 | phys_addr_t phys_addr; |
0e037281 | 6068 | void *buf; |
3f518509 | 6069 | |
3f518509 | 6070 | /* No recycle or too many buffers are in use, so allocate a new skb */ |
4e4a105f TP |
6071 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, |
6072 | GFP_ATOMIC); | |
0e037281 | 6073 | if (!buf) |
3f518509 MW |
6074 | return -ENOMEM; |
6075 | ||
7d7627ba | 6076 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
7ef7e1d9 | 6077 | |
3f518509 MW |
6078 | return 0; |
6079 | } | |
6080 | ||
6081 | /* Handle tx checksum */ | |
6082 | static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) | |
6083 | { | |
6084 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6085 | int ip_hdr_len = 0; | |
6086 | u8 l4_proto; | |
6087 | ||
6088 | if (skb->protocol == htons(ETH_P_IP)) { | |
6089 | struct iphdr *ip4h = ip_hdr(skb); | |
6090 | ||
6091 | /* Calculate IPv4 checksum and L4 checksum */ | |
6092 | ip_hdr_len = ip4h->ihl; | |
6093 | l4_proto = ip4h->protocol; | |
6094 | } else if (skb->protocol == htons(ETH_P_IPV6)) { | |
6095 | struct ipv6hdr *ip6h = ipv6_hdr(skb); | |
6096 | ||
6097 | /* Read l4_protocol from one of IPv6 extra headers */ | |
6098 | if (skb_network_header_len(skb) > 0) | |
6099 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
6100 | l4_proto = ip6h->nexthdr; | |
6101 | } else { | |
6102 | return MVPP2_TXD_L4_CSUM_NOT; | |
6103 | } | |
6104 | ||
6105 | return mvpp2_txq_desc_csum(skb_network_offset(skb), | |
6106 | skb->protocol, ip_hdr_len, l4_proto); | |
6107 | } | |
6108 | ||
6109 | return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; | |
6110 | } | |
6111 | ||
3f518509 | 6112 | /* Main rx processing */ |
591f4cfa TP |
6113 | static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, |
6114 | int rx_todo, struct mvpp2_rx_queue *rxq) | |
3f518509 MW |
6115 | { |
6116 | struct net_device *dev = port->dev; | |
b5015854 MW |
6117 | int rx_received; |
6118 | int rx_done = 0; | |
3f518509 MW |
6119 | u32 rcvd_pkts = 0; |
6120 | u32 rcvd_bytes = 0; | |
6121 | ||
6122 | /* Get number of received packets and clamp the to-do */ | |
6123 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
6124 | if (rx_todo > rx_received) | |
6125 | rx_todo = rx_received; | |
6126 | ||
b5015854 | 6127 | while (rx_done < rx_todo) { |
3f518509 MW |
6128 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); |
6129 | struct mvpp2_bm_pool *bm_pool; | |
6130 | struct sk_buff *skb; | |
0e037281 | 6131 | unsigned int frag_size; |
20396136 | 6132 | dma_addr_t dma_addr; |
ac3dd277 | 6133 | phys_addr_t phys_addr; |
56b8aae9 | 6134 | u32 rx_status; |
3f518509 | 6135 | int pool, rx_bytes, err; |
0e037281 | 6136 | void *data; |
3f518509 | 6137 | |
b5015854 | 6138 | rx_done++; |
ac3dd277 TP |
6139 | rx_status = mvpp2_rxdesc_status_get(port, rx_desc); |
6140 | rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); | |
6141 | rx_bytes -= MVPP2_MH_SIZE; | |
6142 | dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); | |
6143 | phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); | |
6144 | data = (void *)phys_to_virt(phys_addr); | |
6145 | ||
56b8aae9 TP |
6146 | pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> |
6147 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 6148 | bm_pool = &port->priv->bm_pools[pool]; |
3f518509 MW |
6149 | |
6150 | /* In case of an error, release the requested buffer pointer | |
6151 | * to the Buffer Manager. This request process is controlled | |
6152 | * by the hardware, and the information about the buffer is | |
6153 | * comprised by the RX descriptor. | |
6154 | */ | |
6155 | if (rx_status & MVPP2_RXD_ERR_SUMMARY) { | |
8a52488b | 6156 | err_drop_frame: |
3f518509 MW |
6157 | dev->stats.rx_errors++; |
6158 | mvpp2_rx_error(port, rx_desc); | |
b5015854 | 6159 | /* Return the buffer to the pool */ |
7d7627ba | 6160 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
3f518509 MW |
6161 | continue; |
6162 | } | |
6163 | ||
0e037281 TP |
6164 | if (bm_pool->frag_size > PAGE_SIZE) |
6165 | frag_size = 0; | |
6166 | else | |
6167 | frag_size = bm_pool->frag_size; | |
6168 | ||
6169 | skb = build_skb(data, frag_size); | |
6170 | if (!skb) { | |
6171 | netdev_warn(port->dev, "skb build failed\n"); | |
6172 | goto err_drop_frame; | |
6173 | } | |
3f518509 | 6174 | |
56b8aae9 | 6175 | err = mvpp2_rx_refill(port, bm_pool, pool); |
b5015854 MW |
6176 | if (err) { |
6177 | netdev_err(port->dev, "failed to refill BM pools\n"); | |
6178 | goto err_drop_frame; | |
6179 | } | |
6180 | ||
20396136 | 6181 | dma_unmap_single(dev->dev.parent, dma_addr, |
4229d502 MW |
6182 | bm_pool->buf_size, DMA_FROM_DEVICE); |
6183 | ||
3f518509 MW |
6184 | rcvd_pkts++; |
6185 | rcvd_bytes += rx_bytes; | |
3f518509 | 6186 | |
0e037281 | 6187 | skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); |
3f518509 MW |
6188 | skb_put(skb, rx_bytes); |
6189 | skb->protocol = eth_type_trans(skb, dev); | |
6190 | mvpp2_rx_csum(port, rx_status, skb); | |
6191 | ||
591f4cfa | 6192 | napi_gro_receive(napi, skb); |
3f518509 MW |
6193 | } |
6194 | ||
6195 | if (rcvd_pkts) { | |
6196 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
6197 | ||
6198 | u64_stats_update_begin(&stats->syncp); | |
6199 | stats->rx_packets += rcvd_pkts; | |
6200 | stats->rx_bytes += rcvd_bytes; | |
6201 | u64_stats_update_end(&stats->syncp); | |
6202 | } | |
6203 | ||
6204 | /* Update Rx queue management counters */ | |
6205 | wmb(); | |
b5015854 | 6206 | mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); |
3f518509 MW |
6207 | |
6208 | return rx_todo; | |
6209 | } | |
6210 | ||
6211 | static inline void | |
ac3dd277 | 6212 | tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, |
3f518509 MW |
6213 | struct mvpp2_tx_desc *desc) |
6214 | { | |
ac3dd277 TP |
6215 | dma_addr_t buf_dma_addr = |
6216 | mvpp2_txdesc_dma_addr_get(port, desc); | |
6217 | size_t buf_sz = | |
6218 | mvpp2_txdesc_size_get(port, desc); | |
6219 | dma_unmap_single(port->dev->dev.parent, buf_dma_addr, | |
6220 | buf_sz, DMA_TO_DEVICE); | |
3f518509 MW |
6221 | mvpp2_txq_desc_put(txq); |
6222 | } | |
6223 | ||
6224 | /* Handle tx fragmentation processing */ | |
6225 | static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, | |
6226 | struct mvpp2_tx_queue *aggr_txq, | |
6227 | struct mvpp2_tx_queue *txq) | |
6228 | { | |
6229 | struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); | |
6230 | struct mvpp2_tx_desc *tx_desc; | |
6231 | int i; | |
20396136 | 6232 | dma_addr_t buf_dma_addr; |
3f518509 MW |
6233 | |
6234 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6235 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6236 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
6237 | ||
6238 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
6239 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
6240 | mvpp2_txdesc_size_set(port, tx_desc, frag->size); | |
3f518509 | 6241 | |
20396136 | 6242 | buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, |
ac3dd277 TP |
6243 | frag->size, |
6244 | DMA_TO_DEVICE); | |
20396136 | 6245 | if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { |
3f518509 | 6246 | mvpp2_txq_desc_put(txq); |
32bae631 | 6247 | goto cleanup; |
3f518509 MW |
6248 | } |
6249 | ||
ac3dd277 TP |
6250 | mvpp2_txdesc_offset_set(port, tx_desc, |
6251 | buf_dma_addr & MVPP2_TX_DESC_ALIGN); | |
6252 | mvpp2_txdesc_dma_addr_set(port, tx_desc, | |
6253 | buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); | |
3f518509 MW |
6254 | |
6255 | if (i == (skb_shinfo(skb)->nr_frags - 1)) { | |
6256 | /* Last descriptor */ | |
ac3dd277 TP |
6257 | mvpp2_txdesc_cmd_set(port, tx_desc, |
6258 | MVPP2_TXD_L_DESC); | |
6259 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
6260 | } else { |
6261 | /* Descriptor in the middle: Not First, Not Last */ | |
ac3dd277 TP |
6262 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); |
6263 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
6264 | } |
6265 | } | |
6266 | ||
6267 | return 0; | |
32bae631 | 6268 | cleanup: |
3f518509 MW |
6269 | /* Release all descriptors that were used to map fragments of |
6270 | * this packet, as well as the corresponding DMA mappings | |
6271 | */ | |
6272 | for (i = i - 1; i >= 0; i--) { | |
6273 | tx_desc = txq->descs + i; | |
ac3dd277 | 6274 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 MW |
6275 | } |
6276 | ||
6277 | return -ENOMEM; | |
6278 | } | |
6279 | ||
186cd4d4 AT |
6280 | static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, |
6281 | struct net_device *dev, | |
6282 | struct mvpp2_tx_queue *txq, | |
6283 | struct mvpp2_tx_queue *aggr_txq, | |
6284 | struct mvpp2_txq_pcpu *txq_pcpu, | |
6285 | int hdr_sz) | |
6286 | { | |
6287 | struct mvpp2_port *port = netdev_priv(dev); | |
6288 | struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
6289 | dma_addr_t addr; | |
6290 | ||
6291 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); | |
6292 | mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); | |
6293 | ||
6294 | addr = txq_pcpu->tso_headers_dma + | |
6295 | txq_pcpu->txq_put_index * TSO_HEADER_SIZE; | |
6296 | mvpp2_txdesc_offset_set(port, tx_desc, addr & MVPP2_TX_DESC_ALIGN); | |
6297 | mvpp2_txdesc_dma_addr_set(port, tx_desc, addr & ~MVPP2_TX_DESC_ALIGN); | |
6298 | ||
6299 | mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | | |
6300 | MVPP2_TXD_F_DESC | | |
6301 | MVPP2_TXD_PADDING_DISABLE); | |
6302 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
6303 | } | |
6304 | ||
6305 | static inline int mvpp2_tso_put_data(struct sk_buff *skb, | |
6306 | struct net_device *dev, struct tso_t *tso, | |
6307 | struct mvpp2_tx_queue *txq, | |
6308 | struct mvpp2_tx_queue *aggr_txq, | |
6309 | struct mvpp2_txq_pcpu *txq_pcpu, | |
6310 | int sz, bool left, bool last) | |
6311 | { | |
6312 | struct mvpp2_port *port = netdev_priv(dev); | |
6313 | struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
6314 | dma_addr_t buf_dma_addr; | |
6315 | ||
6316 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); | |
6317 | mvpp2_txdesc_size_set(port, tx_desc, sz); | |
6318 | ||
6319 | buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, | |
6320 | DMA_TO_DEVICE); | |
6321 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { | |
6322 | mvpp2_txq_desc_put(txq); | |
6323 | return -ENOMEM; | |
6324 | } | |
6325 | ||
6326 | mvpp2_txdesc_offset_set(port, tx_desc, | |
6327 | buf_dma_addr & MVPP2_TX_DESC_ALIGN); | |
6328 | mvpp2_txdesc_dma_addr_set(port, tx_desc, | |
6329 | buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); | |
6330 | ||
6331 | if (!left) { | |
6332 | mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); | |
6333 | if (last) { | |
6334 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
6335 | return 0; | |
6336 | } | |
6337 | } else { | |
6338 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); | |
6339 | } | |
6340 | ||
6341 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
6342 | return 0; | |
6343 | } | |
6344 | ||
6345 | static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
6346 | struct mvpp2_tx_queue *txq, | |
6347 | struct mvpp2_tx_queue *aggr_txq, | |
6348 | struct mvpp2_txq_pcpu *txq_pcpu) | |
6349 | { | |
6350 | struct mvpp2_port *port = netdev_priv(dev); | |
6351 | struct tso_t tso; | |
6352 | int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
6353 | int i, len, descs = 0; | |
6354 | ||
6355 | /* Check number of available descriptors */ | |
6356 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, | |
6357 | tso_count_descs(skb)) || | |
6358 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, | |
6359 | tso_count_descs(skb))) | |
6360 | return 0; | |
6361 | ||
6362 | tso_start(skb, &tso); | |
6363 | len = skb->len - hdr_sz; | |
6364 | while (len > 0) { | |
6365 | int left = min_t(int, skb_shinfo(skb)->gso_size, len); | |
6366 | char *hdr = txq_pcpu->tso_headers + | |
6367 | txq_pcpu->txq_put_index * TSO_HEADER_SIZE; | |
6368 | ||
6369 | len -= left; | |
6370 | descs++; | |
6371 | ||
6372 | tso_build_hdr(skb, hdr, &tso, left, len == 0); | |
6373 | mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); | |
6374 | ||
6375 | while (left > 0) { | |
6376 | int sz = min_t(int, tso.size, left); | |
6377 | left -= sz; | |
6378 | descs++; | |
6379 | ||
6380 | if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, | |
6381 | txq_pcpu, sz, left, len == 0)) | |
6382 | goto release; | |
6383 | tso_build_data(skb, &tso, sz); | |
6384 | } | |
6385 | } | |
6386 | ||
6387 | return descs; | |
6388 | ||
6389 | release: | |
6390 | for (i = descs - 1; i >= 0; i--) { | |
6391 | struct mvpp2_tx_desc *tx_desc = txq->descs + i; | |
6392 | tx_desc_unmap_put(port, txq, tx_desc); | |
6393 | } | |
6394 | return 0; | |
6395 | } | |
6396 | ||
3f518509 MW |
6397 | /* Main tx processing */ |
6398 | static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev) | |
6399 | { | |
6400 | struct mvpp2_port *port = netdev_priv(dev); | |
6401 | struct mvpp2_tx_queue *txq, *aggr_txq; | |
6402 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6403 | struct mvpp2_tx_desc *tx_desc; | |
20396136 | 6404 | dma_addr_t buf_dma_addr; |
3f518509 MW |
6405 | int frags = 0; |
6406 | u16 txq_id; | |
6407 | u32 tx_cmd; | |
6408 | ||
6409 | txq_id = skb_get_queue_mapping(skb); | |
6410 | txq = port->txqs[txq_id]; | |
6411 | txq_pcpu = this_cpu_ptr(txq->pcpu); | |
6412 | aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; | |
6413 | ||
186cd4d4 AT |
6414 | if (skb_is_gso(skb)) { |
6415 | frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); | |
6416 | goto out; | |
6417 | } | |
3f518509 MW |
6418 | frags = skb_shinfo(skb)->nr_frags + 1; |
6419 | ||
6420 | /* Check number of available descriptors */ | |
6421 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || | |
6422 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, | |
6423 | txq_pcpu, frags)) { | |
6424 | frags = 0; | |
6425 | goto out; | |
6426 | } | |
6427 | ||
6428 | /* Get a descriptor for the first part of the packet */ | |
6429 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
6430 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
6431 | mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); | |
3f518509 | 6432 | |
20396136 | 6433 | buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, |
ac3dd277 | 6434 | skb_headlen(skb), DMA_TO_DEVICE); |
20396136 | 6435 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { |
3f518509 MW |
6436 | mvpp2_txq_desc_put(txq); |
6437 | frags = 0; | |
6438 | goto out; | |
6439 | } | |
ac3dd277 TP |
6440 | |
6441 | mvpp2_txdesc_offset_set(port, tx_desc, | |
6442 | buf_dma_addr & MVPP2_TX_DESC_ALIGN); | |
6443 | mvpp2_txdesc_dma_addr_set(port, tx_desc, | |
6444 | buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); | |
3f518509 MW |
6445 | |
6446 | tx_cmd = mvpp2_skb_tx_csum(port, skb); | |
6447 | ||
6448 | if (frags == 1) { | |
6449 | /* First and Last descriptor */ | |
6450 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; | |
ac3dd277 TP |
6451 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
6452 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
6453 | } else { |
6454 | /* First but not Last */ | |
6455 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; | |
ac3dd277 TP |
6456 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
6457 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
6458 | |
6459 | /* Continue with other skb fragments */ | |
6460 | if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { | |
ac3dd277 | 6461 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 MW |
6462 | frags = 0; |
6463 | goto out; | |
6464 | } | |
6465 | } | |
6466 | ||
3f518509 MW |
6467 | out: |
6468 | if (frags > 0) { | |
6469 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
186cd4d4 AT |
6470 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
6471 | ||
6472 | txq_pcpu->reserved_num -= frags; | |
6473 | txq_pcpu->count += frags; | |
6474 | aggr_txq->count += frags; | |
6475 | ||
6476 | /* Enable transmit */ | |
6477 | wmb(); | |
6478 | mvpp2_aggr_txq_pend_desc_add(port, frags); | |
6479 | ||
6480 | if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) | |
6481 | netif_tx_stop_queue(nq); | |
3f518509 MW |
6482 | |
6483 | u64_stats_update_begin(&stats->syncp); | |
6484 | stats->tx_packets++; | |
6485 | stats->tx_bytes += skb->len; | |
6486 | u64_stats_update_end(&stats->syncp); | |
6487 | } else { | |
6488 | dev->stats.tx_dropped++; | |
6489 | dev_kfree_skb_any(skb); | |
6490 | } | |
6491 | ||
edc660fa MW |
6492 | /* Finalize TX processing */ |
6493 | if (txq_pcpu->count >= txq->done_pkts_coal) | |
6494 | mvpp2_txq_done(port, txq, txq_pcpu); | |
6495 | ||
6496 | /* Set the timer in case not all frags were processed */ | |
213f428f TP |
6497 | if (!port->has_tx_irqs && txq_pcpu->count <= frags && |
6498 | txq_pcpu->count > 0) { | |
edc660fa MW |
6499 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); |
6500 | ||
6501 | mvpp2_timer_set(port_pcpu); | |
6502 | } | |
6503 | ||
3f518509 MW |
6504 | return NETDEV_TX_OK; |
6505 | } | |
6506 | ||
6507 | static inline void mvpp2_cause_error(struct net_device *dev, int cause) | |
6508 | { | |
6509 | if (cause & MVPP2_CAUSE_FCS_ERR_MASK) | |
6510 | netdev_err(dev, "FCS error\n"); | |
6511 | if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) | |
6512 | netdev_err(dev, "rx fifo overrun error\n"); | |
6513 | if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) | |
6514 | netdev_err(dev, "tx fifo underrun error\n"); | |
6515 | } | |
6516 | ||
edc660fa | 6517 | static int mvpp2_poll(struct napi_struct *napi, int budget) |
3f518509 | 6518 | { |
213f428f | 6519 | u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; |
edc660fa MW |
6520 | int rx_done = 0; |
6521 | struct mvpp2_port *port = netdev_priv(napi->dev); | |
591f4cfa | 6522 | struct mvpp2_queue_vector *qv; |
a786841d | 6523 | int cpu = smp_processor_id(); |
3f518509 | 6524 | |
591f4cfa TP |
6525 | qv = container_of(napi, struct mvpp2_queue_vector, napi); |
6526 | ||
3f518509 MW |
6527 | /* Rx/Tx cause register |
6528 | * | |
6529 | * Bits 0-15: each bit indicates received packets on the Rx queue | |
6530 | * (bit 0 is for Rx queue 0). | |
6531 | * | |
6532 | * Bits 16-23: each bit indicates transmitted packets on the Tx queue | |
6533 | * (bit 16 is for Tx queue 0). | |
6534 | * | |
6535 | * Each CPU has its own Rx/Tx cause register | |
6536 | */ | |
213f428f | 6537 | cause_rx_tx = mvpp2_percpu_read(port->priv, qv->sw_thread_id, |
a786841d | 6538 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); |
3f518509 | 6539 | |
213f428f | 6540 | cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; |
3f518509 MW |
6541 | if (cause_misc) { |
6542 | mvpp2_cause_error(port->dev, cause_misc); | |
6543 | ||
6544 | /* Clear the cause register */ | |
6545 | mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); | |
a786841d TP |
6546 | mvpp2_percpu_write(port->priv, cpu, |
6547 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id), | |
6548 | cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); | |
3f518509 MW |
6549 | } |
6550 | ||
213f428f TP |
6551 | cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; |
6552 | if (cause_tx) { | |
6553 | cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; | |
6554 | mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); | |
6555 | } | |
3f518509 MW |
6556 | |
6557 | /* Process RX packets */ | |
213f428f TP |
6558 | cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; |
6559 | cause_rx <<= qv->first_rxq; | |
591f4cfa | 6560 | cause_rx |= qv->pending_cause_rx; |
3f518509 MW |
6561 | while (cause_rx && budget > 0) { |
6562 | int count; | |
6563 | struct mvpp2_rx_queue *rxq; | |
6564 | ||
6565 | rxq = mvpp2_get_rx_queue(port, cause_rx); | |
6566 | if (!rxq) | |
6567 | break; | |
6568 | ||
591f4cfa | 6569 | count = mvpp2_rx(port, napi, budget, rxq); |
3f518509 MW |
6570 | rx_done += count; |
6571 | budget -= count; | |
6572 | if (budget > 0) { | |
6573 | /* Clear the bit associated to this Rx queue | |
6574 | * so that next iteration will continue from | |
6575 | * the next Rx queue. | |
6576 | */ | |
6577 | cause_rx &= ~(1 << rxq->logic_rxq); | |
6578 | } | |
6579 | } | |
6580 | ||
6581 | if (budget > 0) { | |
6582 | cause_rx = 0; | |
6ad20165 | 6583 | napi_complete_done(napi, rx_done); |
3f518509 | 6584 | |
591f4cfa | 6585 | mvpp2_qvec_interrupt_enable(qv); |
3f518509 | 6586 | } |
591f4cfa | 6587 | qv->pending_cause_rx = cause_rx; |
3f518509 MW |
6588 | return rx_done; |
6589 | } | |
6590 | ||
6591 | /* Set hw internals when starting port */ | |
6592 | static void mvpp2_start_dev(struct mvpp2_port *port) | |
6593 | { | |
8e07269d | 6594 | struct net_device *ndev = port->dev; |
591f4cfa | 6595 | int i; |
8e07269d | 6596 | |
76eb1b1d SC |
6597 | if (port->gop_id == 0 && |
6598 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
6599 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) | |
6600 | mvpp2_xlg_max_rx_size_set(port); | |
6601 | else | |
6602 | mvpp2_gmac_max_rx_size_set(port); | |
6603 | ||
3f518509 MW |
6604 | mvpp2_txp_max_tx_size_set(port); |
6605 | ||
591f4cfa TP |
6606 | for (i = 0; i < port->nqvecs; i++) |
6607 | napi_enable(&port->qvecs[i].napi); | |
3f518509 MW |
6608 | |
6609 | /* Enable interrupts on all CPUs */ | |
6610 | mvpp2_interrupts_enable(port); | |
6611 | ||
542897d9 AT |
6612 | if (port->priv->hw_version == MVPP22) { |
6613 | mvpp22_comphy_init(port); | |
f84bf386 | 6614 | mvpp22_gop_init(port); |
542897d9 | 6615 | } |
f84bf386 | 6616 | |
2055d626 | 6617 | mvpp2_port_mii_set(port); |
3f518509 | 6618 | mvpp2_port_enable(port); |
5997c86b AT |
6619 | if (ndev->phydev) |
6620 | phy_start(ndev->phydev); | |
3f518509 MW |
6621 | netif_tx_start_all_queues(port->dev); |
6622 | } | |
6623 | ||
6624 | /* Set hw internals when stopping port */ | |
6625 | static void mvpp2_stop_dev(struct mvpp2_port *port) | |
6626 | { | |
8e07269d | 6627 | struct net_device *ndev = port->dev; |
591f4cfa | 6628 | int i; |
8e07269d | 6629 | |
3f518509 MW |
6630 | /* Stop new packets from arriving to RXQs */ |
6631 | mvpp2_ingress_disable(port); | |
6632 | ||
6633 | mdelay(10); | |
6634 | ||
6635 | /* Disable interrupts on all CPUs */ | |
6636 | mvpp2_interrupts_disable(port); | |
6637 | ||
591f4cfa TP |
6638 | for (i = 0; i < port->nqvecs; i++) |
6639 | napi_disable(&port->qvecs[i].napi); | |
3f518509 MW |
6640 | |
6641 | netif_carrier_off(port->dev); | |
6642 | netif_tx_stop_all_queues(port->dev); | |
6643 | ||
6644 | mvpp2_egress_disable(port); | |
6645 | mvpp2_port_disable(port); | |
5997c86b AT |
6646 | if (ndev->phydev) |
6647 | phy_stop(ndev->phydev); | |
542897d9 | 6648 | phy_power_off(port->comphy); |
3f518509 MW |
6649 | } |
6650 | ||
3f518509 MW |
6651 | static int mvpp2_check_ringparam_valid(struct net_device *dev, |
6652 | struct ethtool_ringparam *ring) | |
6653 | { | |
6654 | u16 new_rx_pending = ring->rx_pending; | |
6655 | u16 new_tx_pending = ring->tx_pending; | |
6656 | ||
6657 | if (ring->rx_pending == 0 || ring->tx_pending == 0) | |
6658 | return -EINVAL; | |
6659 | ||
6660 | if (ring->rx_pending > MVPP2_MAX_RXD) | |
6661 | new_rx_pending = MVPP2_MAX_RXD; | |
6662 | else if (!IS_ALIGNED(ring->rx_pending, 16)) | |
6663 | new_rx_pending = ALIGN(ring->rx_pending, 16); | |
6664 | ||
6665 | if (ring->tx_pending > MVPP2_MAX_TXD) | |
6666 | new_tx_pending = MVPP2_MAX_TXD; | |
6667 | else if (!IS_ALIGNED(ring->tx_pending, 32)) | |
6668 | new_tx_pending = ALIGN(ring->tx_pending, 32); | |
6669 | ||
6670 | if (ring->rx_pending != new_rx_pending) { | |
6671 | netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", | |
6672 | ring->rx_pending, new_rx_pending); | |
6673 | ring->rx_pending = new_rx_pending; | |
6674 | } | |
6675 | ||
6676 | if (ring->tx_pending != new_tx_pending) { | |
6677 | netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", | |
6678 | ring->tx_pending, new_tx_pending); | |
6679 | ring->tx_pending = new_tx_pending; | |
6680 | } | |
6681 | ||
6682 | return 0; | |
6683 | } | |
6684 | ||
26975821 | 6685 | static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) |
3f518509 MW |
6686 | { |
6687 | u32 mac_addr_l, mac_addr_m, mac_addr_h; | |
6688 | ||
6689 | mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
6690 | mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); | |
6691 | mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); | |
6692 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
6693 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
6694 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
6695 | addr[3] = mac_addr_h & 0xFF; | |
6696 | addr[4] = mac_addr_m & 0xFF; | |
6697 | addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; | |
6698 | } | |
6699 | ||
6700 | static int mvpp2_phy_connect(struct mvpp2_port *port) | |
6701 | { | |
6702 | struct phy_device *phy_dev; | |
6703 | ||
5997c86b AT |
6704 | /* No PHY is attached */ |
6705 | if (!port->phy_node) | |
6706 | return 0; | |
6707 | ||
3f518509 MW |
6708 | phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0, |
6709 | port->phy_interface); | |
6710 | if (!phy_dev) { | |
6711 | netdev_err(port->dev, "cannot connect to phy\n"); | |
6712 | return -ENODEV; | |
6713 | } | |
6714 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
6715 | phy_dev->advertising = phy_dev->supported; | |
6716 | ||
3f518509 MW |
6717 | port->link = 0; |
6718 | port->duplex = 0; | |
6719 | port->speed = 0; | |
6720 | ||
6721 | return 0; | |
6722 | } | |
6723 | ||
6724 | static void mvpp2_phy_disconnect(struct mvpp2_port *port) | |
6725 | { | |
8e07269d PR |
6726 | struct net_device *ndev = port->dev; |
6727 | ||
5997c86b AT |
6728 | if (!ndev->phydev) |
6729 | return; | |
6730 | ||
8e07269d | 6731 | phy_disconnect(ndev->phydev); |
3f518509 MW |
6732 | } |
6733 | ||
591f4cfa TP |
6734 | static int mvpp2_irqs_init(struct mvpp2_port *port) |
6735 | { | |
6736 | int err, i; | |
6737 | ||
6738 | for (i = 0; i < port->nqvecs; i++) { | |
6739 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6740 | ||
6741 | err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); | |
6742 | if (err) | |
6743 | goto err; | |
213f428f TP |
6744 | |
6745 | if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) | |
6746 | irq_set_affinity_hint(qv->irq, | |
6747 | cpumask_of(qv->sw_thread_id)); | |
591f4cfa TP |
6748 | } |
6749 | ||
6750 | return 0; | |
6751 | err: | |
6752 | for (i = 0; i < port->nqvecs; i++) { | |
6753 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6754 | ||
213f428f | 6755 | irq_set_affinity_hint(qv->irq, NULL); |
591f4cfa TP |
6756 | free_irq(qv->irq, qv); |
6757 | } | |
6758 | ||
6759 | return err; | |
6760 | } | |
6761 | ||
6762 | static void mvpp2_irqs_deinit(struct mvpp2_port *port) | |
6763 | { | |
6764 | int i; | |
6765 | ||
6766 | for (i = 0; i < port->nqvecs; i++) { | |
6767 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6768 | ||
213f428f | 6769 | irq_set_affinity_hint(qv->irq, NULL); |
591f4cfa TP |
6770 | free_irq(qv->irq, qv); |
6771 | } | |
6772 | } | |
6773 | ||
3f518509 MW |
6774 | static int mvpp2_open(struct net_device *dev) |
6775 | { | |
6776 | struct mvpp2_port *port = netdev_priv(dev); | |
fd3651b2 | 6777 | struct mvpp2 *priv = port->priv; |
3f518509 MW |
6778 | unsigned char mac_bcast[ETH_ALEN] = { |
6779 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
6780 | int err; | |
6781 | ||
6782 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); | |
6783 | if (err) { | |
6784 | netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); | |
6785 | return err; | |
6786 | } | |
6787 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, | |
6788 | dev->dev_addr, true); | |
6789 | if (err) { | |
6790 | netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n"); | |
6791 | return err; | |
6792 | } | |
6793 | err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); | |
6794 | if (err) { | |
6795 | netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); | |
6796 | return err; | |
6797 | } | |
6798 | err = mvpp2_prs_def_flow(port); | |
6799 | if (err) { | |
6800 | netdev_err(dev, "mvpp2_prs_def_flow failed\n"); | |
6801 | return err; | |
6802 | } | |
6803 | ||
6804 | /* Allocate the Rx/Tx queues */ | |
6805 | err = mvpp2_setup_rxqs(port); | |
6806 | if (err) { | |
6807 | netdev_err(port->dev, "cannot allocate Rx queues\n"); | |
6808 | return err; | |
6809 | } | |
6810 | ||
6811 | err = mvpp2_setup_txqs(port); | |
6812 | if (err) { | |
6813 | netdev_err(port->dev, "cannot allocate Tx queues\n"); | |
6814 | goto err_cleanup_rxqs; | |
6815 | } | |
6816 | ||
591f4cfa | 6817 | err = mvpp2_irqs_init(port); |
3f518509 | 6818 | if (err) { |
591f4cfa | 6819 | netdev_err(port->dev, "cannot init IRQs\n"); |
3f518509 MW |
6820 | goto err_cleanup_txqs; |
6821 | } | |
6822 | ||
fd3651b2 AT |
6823 | if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) { |
6824 | err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, | |
6825 | dev->name, port); | |
6826 | if (err) { | |
6827 | netdev_err(port->dev, "cannot request link IRQ %d\n", | |
6828 | port->link_irq); | |
6829 | goto err_free_irq; | |
6830 | } | |
6831 | ||
6832 | mvpp22_gop_setup_irq(port); | |
6833 | } | |
6834 | ||
3f518509 MW |
6835 | /* In default link is down */ |
6836 | netif_carrier_off(port->dev); | |
6837 | ||
6838 | err = mvpp2_phy_connect(port); | |
6839 | if (err < 0) | |
fd3651b2 | 6840 | goto err_free_link_irq; |
3f518509 MW |
6841 | |
6842 | /* Unmask interrupts on all CPUs */ | |
6843 | on_each_cpu(mvpp2_interrupts_unmask, port, 1); | |
213f428f | 6844 | mvpp2_shared_interrupt_mask_unmask(port, false); |
3f518509 MW |
6845 | |
6846 | mvpp2_start_dev(port); | |
6847 | ||
6848 | return 0; | |
6849 | ||
fd3651b2 AT |
6850 | err_free_link_irq: |
6851 | if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) | |
6852 | free_irq(port->link_irq, port); | |
3f518509 | 6853 | err_free_irq: |
591f4cfa | 6854 | mvpp2_irqs_deinit(port); |
3f518509 MW |
6855 | err_cleanup_txqs: |
6856 | mvpp2_cleanup_txqs(port); | |
6857 | err_cleanup_rxqs: | |
6858 | mvpp2_cleanup_rxqs(port); | |
6859 | return err; | |
6860 | } | |
6861 | ||
6862 | static int mvpp2_stop(struct net_device *dev) | |
6863 | { | |
6864 | struct mvpp2_port *port = netdev_priv(dev); | |
edc660fa | 6865 | struct mvpp2_port_pcpu *port_pcpu; |
fd3651b2 | 6866 | struct mvpp2 *priv = port->priv; |
edc660fa | 6867 | int cpu; |
3f518509 MW |
6868 | |
6869 | mvpp2_stop_dev(port); | |
6870 | mvpp2_phy_disconnect(port); | |
6871 | ||
6872 | /* Mask interrupts on all CPUs */ | |
6873 | on_each_cpu(mvpp2_interrupts_mask, port, 1); | |
213f428f | 6874 | mvpp2_shared_interrupt_mask_unmask(port, true); |
3f518509 | 6875 | |
fd3651b2 AT |
6876 | if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) |
6877 | free_irq(port->link_irq, port); | |
6878 | ||
591f4cfa | 6879 | mvpp2_irqs_deinit(port); |
213f428f TP |
6880 | if (!port->has_tx_irqs) { |
6881 | for_each_present_cpu(cpu) { | |
6882 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 6883 | |
213f428f TP |
6884 | hrtimer_cancel(&port_pcpu->tx_done_timer); |
6885 | port_pcpu->timer_scheduled = false; | |
6886 | tasklet_kill(&port_pcpu->tx_done_tasklet); | |
6887 | } | |
edc660fa | 6888 | } |
3f518509 MW |
6889 | mvpp2_cleanup_rxqs(port); |
6890 | mvpp2_cleanup_txqs(port); | |
6891 | ||
6892 | return 0; | |
6893 | } | |
6894 | ||
6895 | static void mvpp2_set_rx_mode(struct net_device *dev) | |
6896 | { | |
6897 | struct mvpp2_port *port = netdev_priv(dev); | |
6898 | struct mvpp2 *priv = port->priv; | |
6899 | struct netdev_hw_addr *ha; | |
6900 | int id = port->id; | |
6901 | bool allmulti = dev->flags & IFF_ALLMULTI; | |
6902 | ||
6903 | mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC); | |
6904 | mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti); | |
6905 | mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti); | |
6906 | ||
6907 | /* Remove all port->id's mcast enries */ | |
6908 | mvpp2_prs_mcast_del_all(priv, id); | |
6909 | ||
6910 | if (allmulti && !netdev_mc_empty(dev)) { | |
6911 | netdev_for_each_mc_addr(ha, dev) | |
6912 | mvpp2_prs_mac_da_accept(priv, id, ha->addr, true); | |
6913 | } | |
6914 | } | |
6915 | ||
6916 | static int mvpp2_set_mac_address(struct net_device *dev, void *p) | |
6917 | { | |
6918 | struct mvpp2_port *port = netdev_priv(dev); | |
6919 | const struct sockaddr *addr = p; | |
6920 | int err; | |
6921 | ||
6922 | if (!is_valid_ether_addr(addr->sa_data)) { | |
6923 | err = -EADDRNOTAVAIL; | |
c1175547 | 6924 | goto log_error; |
3f518509 MW |
6925 | } |
6926 | ||
6927 | if (!netif_running(dev)) { | |
6928 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
6929 | if (!err) | |
6930 | return 0; | |
6931 | /* Reconfigure parser to accept the original MAC address */ | |
6932 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
6933 | if (err) | |
c1175547 | 6934 | goto log_error; |
3f518509 MW |
6935 | } |
6936 | ||
6937 | mvpp2_stop_dev(port); | |
6938 | ||
6939 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
6940 | if (!err) | |
6941 | goto out_start; | |
6942 | ||
6943 | /* Reconfigure parser accept the original MAC address */ | |
6944 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
6945 | if (err) | |
c1175547 | 6946 | goto log_error; |
3f518509 MW |
6947 | out_start: |
6948 | mvpp2_start_dev(port); | |
6949 | mvpp2_egress_enable(port); | |
6950 | mvpp2_ingress_enable(port); | |
6951 | return 0; | |
c1175547 | 6952 | log_error: |
dfd4240a | 6953 | netdev_err(dev, "failed to change MAC address\n"); |
3f518509 MW |
6954 | return err; |
6955 | } | |
6956 | ||
6957 | static int mvpp2_change_mtu(struct net_device *dev, int mtu) | |
6958 | { | |
6959 | struct mvpp2_port *port = netdev_priv(dev); | |
6960 | int err; | |
6961 | ||
5777987e JW |
6962 | if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { |
6963 | netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, | |
6964 | ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); | |
6965 | mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); | |
3f518509 MW |
6966 | } |
6967 | ||
6968 | if (!netif_running(dev)) { | |
6969 | err = mvpp2_bm_update_mtu(dev, mtu); | |
6970 | if (!err) { | |
6971 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
6972 | return 0; | |
6973 | } | |
6974 | ||
6975 | /* Reconfigure BM to the original MTU */ | |
6976 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
6977 | if (err) | |
c1175547 | 6978 | goto log_error; |
3f518509 MW |
6979 | } |
6980 | ||
6981 | mvpp2_stop_dev(port); | |
6982 | ||
6983 | err = mvpp2_bm_update_mtu(dev, mtu); | |
6984 | if (!err) { | |
6985 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
6986 | goto out_start; | |
6987 | } | |
6988 | ||
6989 | /* Reconfigure BM to the original MTU */ | |
6990 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
6991 | if (err) | |
c1175547 | 6992 | goto log_error; |
3f518509 MW |
6993 | |
6994 | out_start: | |
6995 | mvpp2_start_dev(port); | |
6996 | mvpp2_egress_enable(port); | |
6997 | mvpp2_ingress_enable(port); | |
6998 | ||
6999 | return 0; | |
c1175547 | 7000 | log_error: |
dfd4240a | 7001 | netdev_err(dev, "failed to change MTU\n"); |
3f518509 MW |
7002 | return err; |
7003 | } | |
7004 | ||
bc1f4470 | 7005 | static void |
3f518509 MW |
7006 | mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
7007 | { | |
7008 | struct mvpp2_port *port = netdev_priv(dev); | |
7009 | unsigned int start; | |
7010 | int cpu; | |
7011 | ||
7012 | for_each_possible_cpu(cpu) { | |
7013 | struct mvpp2_pcpu_stats *cpu_stats; | |
7014 | u64 rx_packets; | |
7015 | u64 rx_bytes; | |
7016 | u64 tx_packets; | |
7017 | u64 tx_bytes; | |
7018 | ||
7019 | cpu_stats = per_cpu_ptr(port->stats, cpu); | |
7020 | do { | |
7021 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); | |
7022 | rx_packets = cpu_stats->rx_packets; | |
7023 | rx_bytes = cpu_stats->rx_bytes; | |
7024 | tx_packets = cpu_stats->tx_packets; | |
7025 | tx_bytes = cpu_stats->tx_bytes; | |
7026 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); | |
7027 | ||
7028 | stats->rx_packets += rx_packets; | |
7029 | stats->rx_bytes += rx_bytes; | |
7030 | stats->tx_packets += tx_packets; | |
7031 | stats->tx_bytes += tx_bytes; | |
7032 | } | |
7033 | ||
7034 | stats->rx_errors = dev->stats.rx_errors; | |
7035 | stats->rx_dropped = dev->stats.rx_dropped; | |
7036 | stats->tx_dropped = dev->stats.tx_dropped; | |
3f518509 MW |
7037 | } |
7038 | ||
bd695a5f TP |
7039 | static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
7040 | { | |
bd695a5f TP |
7041 | int ret; |
7042 | ||
8e07269d | 7043 | if (!dev->phydev) |
bd695a5f TP |
7044 | return -ENOTSUPP; |
7045 | ||
8e07269d | 7046 | ret = phy_mii_ioctl(dev->phydev, ifr, cmd); |
bd695a5f TP |
7047 | if (!ret) |
7048 | mvpp2_link_event(dev); | |
7049 | ||
7050 | return ret; | |
7051 | } | |
7052 | ||
3f518509 MW |
7053 | /* Ethtool methods */ |
7054 | ||
3f518509 MW |
7055 | /* Set interrupt coalescing for ethtools */ |
7056 | static int mvpp2_ethtool_set_coalesce(struct net_device *dev, | |
7057 | struct ethtool_coalesce *c) | |
7058 | { | |
7059 | struct mvpp2_port *port = netdev_priv(dev); | |
7060 | int queue; | |
7061 | ||
09f83975 | 7062 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7063 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
7064 | ||
7065 | rxq->time_coal = c->rx_coalesce_usecs; | |
7066 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
d63f9e41 TP |
7067 | mvpp2_rx_pkts_coal_set(port, rxq); |
7068 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
7069 | } |
7070 | ||
213f428f TP |
7071 | if (port->has_tx_irqs) { |
7072 | port->tx_time_coal = c->tx_coalesce_usecs; | |
7073 | mvpp2_tx_time_coal_set(port); | |
7074 | } | |
7075 | ||
09f83975 | 7076 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7077 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
7078 | ||
7079 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
213f428f TP |
7080 | |
7081 | if (port->has_tx_irqs) | |
7082 | mvpp2_tx_pkts_coal_set(port, txq); | |
3f518509 MW |
7083 | } |
7084 | ||
3f518509 MW |
7085 | return 0; |
7086 | } | |
7087 | ||
7088 | /* get coalescing for ethtools */ | |
7089 | static int mvpp2_ethtool_get_coalesce(struct net_device *dev, | |
7090 | struct ethtool_coalesce *c) | |
7091 | { | |
7092 | struct mvpp2_port *port = netdev_priv(dev); | |
7093 | ||
7094 | c->rx_coalesce_usecs = port->rxqs[0]->time_coal; | |
7095 | c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; | |
7096 | c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; | |
7097 | return 0; | |
7098 | } | |
7099 | ||
7100 | static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, | |
7101 | struct ethtool_drvinfo *drvinfo) | |
7102 | { | |
7103 | strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, | |
7104 | sizeof(drvinfo->driver)); | |
7105 | strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, | |
7106 | sizeof(drvinfo->version)); | |
7107 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
7108 | sizeof(drvinfo->bus_info)); | |
7109 | } | |
7110 | ||
7111 | static void mvpp2_ethtool_get_ringparam(struct net_device *dev, | |
7112 | struct ethtool_ringparam *ring) | |
7113 | { | |
7114 | struct mvpp2_port *port = netdev_priv(dev); | |
7115 | ||
7116 | ring->rx_max_pending = MVPP2_MAX_RXD; | |
7117 | ring->tx_max_pending = MVPP2_MAX_TXD; | |
7118 | ring->rx_pending = port->rx_ring_size; | |
7119 | ring->tx_pending = port->tx_ring_size; | |
7120 | } | |
7121 | ||
7122 | static int mvpp2_ethtool_set_ringparam(struct net_device *dev, | |
7123 | struct ethtool_ringparam *ring) | |
7124 | { | |
7125 | struct mvpp2_port *port = netdev_priv(dev); | |
7126 | u16 prev_rx_ring_size = port->rx_ring_size; | |
7127 | u16 prev_tx_ring_size = port->tx_ring_size; | |
7128 | int err; | |
7129 | ||
7130 | err = mvpp2_check_ringparam_valid(dev, ring); | |
7131 | if (err) | |
7132 | return err; | |
7133 | ||
7134 | if (!netif_running(dev)) { | |
7135 | port->rx_ring_size = ring->rx_pending; | |
7136 | port->tx_ring_size = ring->tx_pending; | |
7137 | return 0; | |
7138 | } | |
7139 | ||
7140 | /* The interface is running, so we have to force a | |
7141 | * reallocation of the queues | |
7142 | */ | |
7143 | mvpp2_stop_dev(port); | |
7144 | mvpp2_cleanup_rxqs(port); | |
7145 | mvpp2_cleanup_txqs(port); | |
7146 | ||
7147 | port->rx_ring_size = ring->rx_pending; | |
7148 | port->tx_ring_size = ring->tx_pending; | |
7149 | ||
7150 | err = mvpp2_setup_rxqs(port); | |
7151 | if (err) { | |
7152 | /* Reallocate Rx queues with the original ring size */ | |
7153 | port->rx_ring_size = prev_rx_ring_size; | |
7154 | ring->rx_pending = prev_rx_ring_size; | |
7155 | err = mvpp2_setup_rxqs(port); | |
7156 | if (err) | |
7157 | goto err_out; | |
7158 | } | |
7159 | err = mvpp2_setup_txqs(port); | |
7160 | if (err) { | |
7161 | /* Reallocate Tx queues with the original ring size */ | |
7162 | port->tx_ring_size = prev_tx_ring_size; | |
7163 | ring->tx_pending = prev_tx_ring_size; | |
7164 | err = mvpp2_setup_txqs(port); | |
7165 | if (err) | |
7166 | goto err_clean_rxqs; | |
7167 | } | |
7168 | ||
7169 | mvpp2_start_dev(port); | |
7170 | mvpp2_egress_enable(port); | |
7171 | mvpp2_ingress_enable(port); | |
7172 | ||
7173 | return 0; | |
7174 | ||
7175 | err_clean_rxqs: | |
7176 | mvpp2_cleanup_rxqs(port); | |
7177 | err_out: | |
dfd4240a | 7178 | netdev_err(dev, "failed to change ring parameters"); |
3f518509 MW |
7179 | return err; |
7180 | } | |
7181 | ||
7182 | /* Device ops */ | |
7183 | ||
7184 | static const struct net_device_ops mvpp2_netdev_ops = { | |
7185 | .ndo_open = mvpp2_open, | |
7186 | .ndo_stop = mvpp2_stop, | |
7187 | .ndo_start_xmit = mvpp2_tx, | |
7188 | .ndo_set_rx_mode = mvpp2_set_rx_mode, | |
7189 | .ndo_set_mac_address = mvpp2_set_mac_address, | |
7190 | .ndo_change_mtu = mvpp2_change_mtu, | |
7191 | .ndo_get_stats64 = mvpp2_get_stats64, | |
bd695a5f | 7192 | .ndo_do_ioctl = mvpp2_ioctl, |
3f518509 MW |
7193 | }; |
7194 | ||
7195 | static const struct ethtool_ops mvpp2_eth_tool_ops = { | |
00606c49 | 7196 | .nway_reset = phy_ethtool_nway_reset, |
3f518509 | 7197 | .get_link = ethtool_op_get_link, |
3f518509 MW |
7198 | .set_coalesce = mvpp2_ethtool_set_coalesce, |
7199 | .get_coalesce = mvpp2_ethtool_get_coalesce, | |
7200 | .get_drvinfo = mvpp2_ethtool_get_drvinfo, | |
7201 | .get_ringparam = mvpp2_ethtool_get_ringparam, | |
7202 | .set_ringparam = mvpp2_ethtool_set_ringparam, | |
fb773e97 PR |
7203 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
7204 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
3f518509 MW |
7205 | }; |
7206 | ||
213f428f TP |
7207 | /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that |
7208 | * had a single IRQ defined per-port. | |
7209 | */ | |
7210 | static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, | |
7211 | struct device_node *port_node) | |
591f4cfa TP |
7212 | { |
7213 | struct mvpp2_queue_vector *v = &port->qvecs[0]; | |
7214 | ||
7215 | v->first_rxq = 0; | |
7216 | v->nrxqs = port->nrxqs; | |
7217 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
7218 | v->sw_thread_id = 0; | |
7219 | v->sw_thread_mask = *cpumask_bits(cpu_online_mask); | |
7220 | v->port = port; | |
7221 | v->irq = irq_of_parse_and_map(port_node, 0); | |
7222 | if (v->irq <= 0) | |
7223 | return -EINVAL; | |
7224 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
7225 | NAPI_POLL_WEIGHT); | |
7226 | ||
7227 | port->nqvecs = 1; | |
7228 | ||
7229 | return 0; | |
7230 | } | |
7231 | ||
213f428f TP |
7232 | static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, |
7233 | struct device_node *port_node) | |
7234 | { | |
7235 | struct mvpp2_queue_vector *v; | |
7236 | int i, ret; | |
7237 | ||
7238 | port->nqvecs = num_possible_cpus(); | |
7239 | if (queue_mode == MVPP2_QDIST_SINGLE_MODE) | |
7240 | port->nqvecs += 1; | |
7241 | ||
7242 | for (i = 0; i < port->nqvecs; i++) { | |
7243 | char irqname[16]; | |
7244 | ||
7245 | v = port->qvecs + i; | |
7246 | ||
7247 | v->port = port; | |
7248 | v->type = MVPP2_QUEUE_VECTOR_PRIVATE; | |
7249 | v->sw_thread_id = i; | |
7250 | v->sw_thread_mask = BIT(i); | |
7251 | ||
7252 | snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); | |
7253 | ||
7254 | if (queue_mode == MVPP2_QDIST_MULTI_MODE) { | |
7255 | v->first_rxq = i * MVPP2_DEFAULT_RXQ; | |
7256 | v->nrxqs = MVPP2_DEFAULT_RXQ; | |
7257 | } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && | |
7258 | i == (port->nqvecs - 1)) { | |
7259 | v->first_rxq = 0; | |
7260 | v->nrxqs = port->nrxqs; | |
7261 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
7262 | strncpy(irqname, "rx-shared", sizeof(irqname)); | |
7263 | } | |
7264 | ||
7265 | v->irq = of_irq_get_byname(port_node, irqname); | |
7266 | if (v->irq <= 0) { | |
7267 | ret = -EINVAL; | |
7268 | goto err; | |
7269 | } | |
7270 | ||
7271 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
7272 | NAPI_POLL_WEIGHT); | |
7273 | } | |
7274 | ||
7275 | return 0; | |
7276 | ||
7277 | err: | |
7278 | for (i = 0; i < port->nqvecs; i++) | |
7279 | irq_dispose_mapping(port->qvecs[i].irq); | |
7280 | return ret; | |
7281 | } | |
7282 | ||
7283 | static int mvpp2_queue_vectors_init(struct mvpp2_port *port, | |
7284 | struct device_node *port_node) | |
7285 | { | |
7286 | if (port->has_tx_irqs) | |
7287 | return mvpp2_multi_queue_vectors_init(port, port_node); | |
7288 | else | |
7289 | return mvpp2_simple_queue_vectors_init(port, port_node); | |
7290 | } | |
7291 | ||
591f4cfa TP |
7292 | static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) |
7293 | { | |
7294 | int i; | |
7295 | ||
7296 | for (i = 0; i < port->nqvecs; i++) | |
7297 | irq_dispose_mapping(port->qvecs[i].irq); | |
7298 | } | |
7299 | ||
7300 | /* Configure Rx queue group interrupt for this port */ | |
7301 | static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) | |
7302 | { | |
7303 | struct mvpp2 *priv = port->priv; | |
7304 | u32 val; | |
7305 | int i; | |
7306 | ||
7307 | if (priv->hw_version == MVPP21) { | |
7308 | mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), | |
7309 | port->nrxqs); | |
7310 | return; | |
7311 | } | |
7312 | ||
7313 | /* Handle the more complicated PPv2.2 case */ | |
7314 | for (i = 0; i < port->nqvecs; i++) { | |
7315 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7316 | ||
7317 | if (!qv->nrxqs) | |
7318 | continue; | |
7319 | ||
7320 | val = qv->sw_thread_id; | |
7321 | val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; | |
7322 | mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); | |
7323 | ||
7324 | val = qv->first_rxq; | |
7325 | val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; | |
7326 | mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); | |
7327 | } | |
7328 | } | |
7329 | ||
3f518509 MW |
7330 | /* Initialize port HW */ |
7331 | static int mvpp2_port_init(struct mvpp2_port *port) | |
7332 | { | |
7333 | struct device *dev = port->dev->dev.parent; | |
7334 | struct mvpp2 *priv = port->priv; | |
7335 | struct mvpp2_txq_pcpu *txq_pcpu; | |
7336 | int queue, cpu, err; | |
7337 | ||
09f83975 TP |
7338 | /* Checks for hardware constraints */ |
7339 | if (port->first_rxq + port->nrxqs > | |
59b9a31e | 7340 | MVPP2_MAX_PORTS * priv->max_port_rxqs) |
3f518509 MW |
7341 | return -EINVAL; |
7342 | ||
09f83975 TP |
7343 | if (port->nrxqs % 4 || (port->nrxqs > priv->max_port_rxqs) || |
7344 | (port->ntxqs > MVPP2_MAX_TXQ)) | |
7345 | return -EINVAL; | |
7346 | ||
3f518509 MW |
7347 | /* Disable port */ |
7348 | mvpp2_egress_disable(port); | |
7349 | mvpp2_port_disable(port); | |
7350 | ||
213f428f TP |
7351 | port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; |
7352 | ||
09f83975 | 7353 | port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), |
3f518509 MW |
7354 | GFP_KERNEL); |
7355 | if (!port->txqs) | |
7356 | return -ENOMEM; | |
7357 | ||
7358 | /* Associate physical Tx queues to this port and initialize. | |
7359 | * The mapping is predefined. | |
7360 | */ | |
09f83975 | 7361 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7362 | int queue_phy_id = mvpp2_txq_phys(port->id, queue); |
7363 | struct mvpp2_tx_queue *txq; | |
7364 | ||
7365 | txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); | |
177c8d1c CJ |
7366 | if (!txq) { |
7367 | err = -ENOMEM; | |
7368 | goto err_free_percpu; | |
7369 | } | |
3f518509 MW |
7370 | |
7371 | txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); | |
7372 | if (!txq->pcpu) { | |
7373 | err = -ENOMEM; | |
7374 | goto err_free_percpu; | |
7375 | } | |
7376 | ||
7377 | txq->id = queue_phy_id; | |
7378 | txq->log_id = queue; | |
7379 | txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; | |
7380 | for_each_present_cpu(cpu) { | |
7381 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
7382 | txq_pcpu->cpu = cpu; | |
7383 | } | |
7384 | ||
7385 | port->txqs[queue] = txq; | |
7386 | } | |
7387 | ||
09f83975 | 7388 | port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), |
3f518509 MW |
7389 | GFP_KERNEL); |
7390 | if (!port->rxqs) { | |
7391 | err = -ENOMEM; | |
7392 | goto err_free_percpu; | |
7393 | } | |
7394 | ||
7395 | /* Allocate and initialize Rx queue for this port */ | |
09f83975 | 7396 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7397 | struct mvpp2_rx_queue *rxq; |
7398 | ||
7399 | /* Map physical Rx queue to port's logical Rx queue */ | |
7400 | rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); | |
d82b0c21 JZ |
7401 | if (!rxq) { |
7402 | err = -ENOMEM; | |
3f518509 | 7403 | goto err_free_percpu; |
d82b0c21 | 7404 | } |
3f518509 MW |
7405 | /* Map this Rx queue to a physical queue */ |
7406 | rxq->id = port->first_rxq + queue; | |
7407 | rxq->port = port->id; | |
7408 | rxq->logic_rxq = queue; | |
7409 | ||
7410 | port->rxqs[queue] = rxq; | |
7411 | } | |
7412 | ||
591f4cfa | 7413 | mvpp2_rx_irqs_setup(port); |
3f518509 MW |
7414 | |
7415 | /* Create Rx descriptor rings */ | |
09f83975 | 7416 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7417 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
7418 | ||
7419 | rxq->size = port->rx_ring_size; | |
7420 | rxq->pkts_coal = MVPP2_RX_COAL_PKTS; | |
7421 | rxq->time_coal = MVPP2_RX_COAL_USEC; | |
7422 | } | |
7423 | ||
7424 | mvpp2_ingress_disable(port); | |
7425 | ||
7426 | /* Port default configuration */ | |
7427 | mvpp2_defaults_set(port); | |
7428 | ||
7429 | /* Port's classifier configuration */ | |
7430 | mvpp2_cls_oversize_rxq_set(port); | |
7431 | mvpp2_cls_port_config(port); | |
7432 | ||
7433 | /* Provide an initial Rx packet size */ | |
7434 | port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); | |
7435 | ||
7436 | /* Initialize pools for swf */ | |
7437 | err = mvpp2_swf_bm_pool_init(port); | |
7438 | if (err) | |
7439 | goto err_free_percpu; | |
7440 | ||
7441 | return 0; | |
7442 | ||
7443 | err_free_percpu: | |
09f83975 | 7444 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7445 | if (!port->txqs[queue]) |
7446 | continue; | |
7447 | free_percpu(port->txqs[queue]->pcpu); | |
7448 | } | |
7449 | return err; | |
7450 | } | |
7451 | ||
213f428f TP |
7452 | /* Checks if the port DT description has the TX interrupts |
7453 | * described. On PPv2.1, there are no such interrupts. On PPv2.2, | |
7454 | * there are available, but we need to keep support for old DTs. | |
7455 | */ | |
7456 | static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv, | |
7457 | struct device_node *port_node) | |
7458 | { | |
7459 | char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", | |
7460 | "tx-cpu2", "tx-cpu3" }; | |
7461 | int ret, i; | |
7462 | ||
7463 | if (priv->hw_version == MVPP21) | |
7464 | return false; | |
7465 | ||
7466 | for (i = 0; i < 5; i++) { | |
7467 | ret = of_property_match_string(port_node, "interrupt-names", | |
7468 | irqs[i]); | |
7469 | if (ret < 0) | |
7470 | return false; | |
7471 | } | |
7472 | ||
7473 | return true; | |
7474 | } | |
7475 | ||
3ba8c81e AT |
7476 | static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, |
7477 | struct device_node *port_node, | |
7478 | char **mac_from) | |
7479 | { | |
7480 | struct mvpp2_port *port = netdev_priv(dev); | |
7481 | char hw_mac_addr[ETH_ALEN] = {0}; | |
7482 | const char *dt_mac_addr; | |
7483 | ||
7484 | dt_mac_addr = of_get_mac_address(port_node); | |
7485 | if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) { | |
7486 | *mac_from = "device tree"; | |
7487 | ether_addr_copy(dev->dev_addr, dt_mac_addr); | |
688cbaf2 AT |
7488 | return; |
7489 | } | |
d2a6e48e | 7490 | |
688cbaf2 AT |
7491 | if (priv->hw_version == MVPP21) { |
7492 | mvpp21_get_mac_address(port, hw_mac_addr); | |
7493 | if (is_valid_ether_addr(hw_mac_addr)) { | |
7494 | *mac_from = "hardware"; | |
7495 | ether_addr_copy(dev->dev_addr, hw_mac_addr); | |
7496 | return; | |
7497 | } | |
3ba8c81e | 7498 | } |
688cbaf2 AT |
7499 | |
7500 | *mac_from = "random"; | |
7501 | eth_hw_addr_random(dev); | |
3ba8c81e AT |
7502 | } |
7503 | ||
3f518509 MW |
7504 | /* Ports initialization */ |
7505 | static int mvpp2_port_probe(struct platform_device *pdev, | |
7506 | struct device_node *port_node, | |
6bf69a1d | 7507 | struct mvpp2 *priv, int index) |
3f518509 MW |
7508 | { |
7509 | struct device_node *phy_node; | |
542897d9 | 7510 | struct phy *comphy; |
3f518509 | 7511 | struct mvpp2_port *port; |
edc660fa | 7512 | struct mvpp2_port_pcpu *port_pcpu; |
3f518509 MW |
7513 | struct net_device *dev; |
7514 | struct resource *res; | |
3ba8c81e | 7515 | char *mac_from = ""; |
09f83975 | 7516 | unsigned int ntxqs, nrxqs; |
213f428f | 7517 | bool has_tx_irqs; |
3f518509 MW |
7518 | u32 id; |
7519 | int features; | |
7520 | int phy_mode; | |
edc660fa | 7521 | int err, i, cpu; |
3f518509 | 7522 | |
213f428f TP |
7523 | has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); |
7524 | ||
7525 | if (!has_tx_irqs) | |
7526 | queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
7527 | ||
09f83975 | 7528 | ntxqs = MVPP2_MAX_TXQ; |
213f428f TP |
7529 | if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) |
7530 | nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); | |
7531 | else | |
7532 | nrxqs = MVPP2_DEFAULT_RXQ; | |
09f83975 TP |
7533 | |
7534 | dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); | |
3f518509 MW |
7535 | if (!dev) |
7536 | return -ENOMEM; | |
7537 | ||
7538 | phy_node = of_parse_phandle(port_node, "phy", 0); | |
3f518509 MW |
7539 | phy_mode = of_get_phy_mode(port_node); |
7540 | if (phy_mode < 0) { | |
7541 | dev_err(&pdev->dev, "incorrect phy mode\n"); | |
7542 | err = phy_mode; | |
7543 | goto err_free_netdev; | |
7544 | } | |
7545 | ||
542897d9 AT |
7546 | comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); |
7547 | if (IS_ERR(comphy)) { | |
7548 | if (PTR_ERR(comphy) == -EPROBE_DEFER) { | |
7549 | err = -EPROBE_DEFER; | |
7550 | goto err_free_netdev; | |
7551 | } | |
7552 | comphy = NULL; | |
7553 | } | |
7554 | ||
3f518509 MW |
7555 | if (of_property_read_u32(port_node, "port-id", &id)) { |
7556 | err = -EINVAL; | |
7557 | dev_err(&pdev->dev, "missing port-id value\n"); | |
7558 | goto err_free_netdev; | |
7559 | } | |
7560 | ||
7561 | dev->tx_queue_len = MVPP2_MAX_TXD; | |
7562 | dev->watchdog_timeo = 5 * HZ; | |
7563 | dev->netdev_ops = &mvpp2_netdev_ops; | |
7564 | dev->ethtool_ops = &mvpp2_eth_tool_ops; | |
7565 | ||
7566 | port = netdev_priv(dev); | |
591f4cfa | 7567 | port->dev = dev; |
09f83975 TP |
7568 | port->ntxqs = ntxqs; |
7569 | port->nrxqs = nrxqs; | |
213f428f TP |
7570 | port->priv = priv; |
7571 | port->has_tx_irqs = has_tx_irqs; | |
3f518509 | 7572 | |
591f4cfa TP |
7573 | err = mvpp2_queue_vectors_init(port, port_node); |
7574 | if (err) | |
3f518509 | 7575 | goto err_free_netdev; |
3f518509 | 7576 | |
fd3651b2 AT |
7577 | port->link_irq = of_irq_get_byname(port_node, "link"); |
7578 | if (port->link_irq == -EPROBE_DEFER) { | |
7579 | err = -EPROBE_DEFER; | |
7580 | goto err_deinit_qvecs; | |
7581 | } | |
7582 | if (port->link_irq <= 0) | |
7583 | /* the link irq is optional */ | |
7584 | port->link_irq = 0; | |
7585 | ||
3f518509 MW |
7586 | if (of_property_read_bool(port_node, "marvell,loopback")) |
7587 | port->flags |= MVPP2_F_LOOPBACK; | |
7588 | ||
3f518509 | 7589 | port->id = id; |
59b9a31e | 7590 | if (priv->hw_version == MVPP21) |
09f83975 | 7591 | port->first_rxq = port->id * port->nrxqs; |
59b9a31e TP |
7592 | else |
7593 | port->first_rxq = port->id * priv->max_port_rxqs; | |
7594 | ||
3f518509 MW |
7595 | port->phy_node = phy_node; |
7596 | port->phy_interface = phy_mode; | |
542897d9 | 7597 | port->comphy = comphy; |
3f518509 | 7598 | |
a786841d TP |
7599 | if (priv->hw_version == MVPP21) { |
7600 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); | |
7601 | port->base = devm_ioremap_resource(&pdev->dev, res); | |
7602 | if (IS_ERR(port->base)) { | |
7603 | err = PTR_ERR(port->base); | |
fd3651b2 | 7604 | goto err_free_irq; |
a786841d TP |
7605 | } |
7606 | } else { | |
7607 | if (of_property_read_u32(port_node, "gop-port-id", | |
7608 | &port->gop_id)) { | |
7609 | err = -EINVAL; | |
7610 | dev_err(&pdev->dev, "missing gop-port-id value\n"); | |
591f4cfa | 7611 | goto err_deinit_qvecs; |
a786841d TP |
7612 | } |
7613 | ||
7614 | port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); | |
3f518509 MW |
7615 | } |
7616 | ||
7617 | /* Alloc per-cpu stats */ | |
7618 | port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); | |
7619 | if (!port->stats) { | |
7620 | err = -ENOMEM; | |
fd3651b2 | 7621 | goto err_free_irq; |
3f518509 MW |
7622 | } |
7623 | ||
3ba8c81e | 7624 | mvpp2_port_copy_mac_addr(dev, priv, port_node, &mac_from); |
3f518509 MW |
7625 | |
7626 | port->tx_ring_size = MVPP2_MAX_TXD; | |
7627 | port->rx_ring_size = MVPP2_MAX_RXD; | |
3f518509 MW |
7628 | SET_NETDEV_DEV(dev, &pdev->dev); |
7629 | ||
7630 | err = mvpp2_port_init(port); | |
7631 | if (err < 0) { | |
7632 | dev_err(&pdev->dev, "failed to init port %d\n", id); | |
7633 | goto err_free_stats; | |
7634 | } | |
26975821 | 7635 | |
26975821 TP |
7636 | mvpp2_port_periodic_xon_disable(port); |
7637 | ||
7638 | if (priv->hw_version == MVPP21) | |
7639 | mvpp2_port_fc_adv_enable(port); | |
7640 | ||
7641 | mvpp2_port_reset(port); | |
3f518509 | 7642 | |
edc660fa MW |
7643 | port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); |
7644 | if (!port->pcpu) { | |
7645 | err = -ENOMEM; | |
7646 | goto err_free_txq_pcpu; | |
7647 | } | |
7648 | ||
213f428f TP |
7649 | if (!port->has_tx_irqs) { |
7650 | for_each_present_cpu(cpu) { | |
7651 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 7652 | |
213f428f TP |
7653 | hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, |
7654 | HRTIMER_MODE_REL_PINNED); | |
7655 | port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; | |
7656 | port_pcpu->timer_scheduled = false; | |
edc660fa | 7657 | |
213f428f TP |
7658 | tasklet_init(&port_pcpu->tx_done_tasklet, |
7659 | mvpp2_tx_proc_cb, | |
7660 | (unsigned long)dev); | |
7661 | } | |
edc660fa MW |
7662 | } |
7663 | ||
186cd4d4 | 7664 | features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
3f518509 MW |
7665 | dev->features = features | NETIF_F_RXCSUM; |
7666 | dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO; | |
7667 | dev->vlan_features |= features; | |
7668 | ||
5777987e JW |
7669 | /* MTU range: 68 - 9676 */ |
7670 | dev->min_mtu = ETH_MIN_MTU; | |
7671 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
7672 | dev->max_mtu = 9676; | |
7673 | ||
3f518509 MW |
7674 | err = register_netdev(dev); |
7675 | if (err < 0) { | |
7676 | dev_err(&pdev->dev, "failed to register netdev\n"); | |
edc660fa | 7677 | goto err_free_port_pcpu; |
3f518509 MW |
7678 | } |
7679 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); | |
7680 | ||
6bf69a1d | 7681 | priv->port_list[index] = port; |
3f518509 MW |
7682 | return 0; |
7683 | ||
edc660fa MW |
7684 | err_free_port_pcpu: |
7685 | free_percpu(port->pcpu); | |
3f518509 | 7686 | err_free_txq_pcpu: |
09f83975 | 7687 | for (i = 0; i < port->ntxqs; i++) |
3f518509 MW |
7688 | free_percpu(port->txqs[i]->pcpu); |
7689 | err_free_stats: | |
7690 | free_percpu(port->stats); | |
fd3651b2 AT |
7691 | err_free_irq: |
7692 | if (port->link_irq) | |
7693 | irq_dispose_mapping(port->link_irq); | |
591f4cfa TP |
7694 | err_deinit_qvecs: |
7695 | mvpp2_queue_vectors_deinit(port); | |
3f518509 | 7696 | err_free_netdev: |
ccb80393 | 7697 | of_node_put(phy_node); |
3f518509 MW |
7698 | free_netdev(dev); |
7699 | return err; | |
7700 | } | |
7701 | ||
7702 | /* Ports removal routine */ | |
7703 | static void mvpp2_port_remove(struct mvpp2_port *port) | |
7704 | { | |
7705 | int i; | |
7706 | ||
7707 | unregister_netdev(port->dev); | |
ccb80393 | 7708 | of_node_put(port->phy_node); |
edc660fa | 7709 | free_percpu(port->pcpu); |
3f518509 | 7710 | free_percpu(port->stats); |
09f83975 | 7711 | for (i = 0; i < port->ntxqs; i++) |
3f518509 | 7712 | free_percpu(port->txqs[i]->pcpu); |
591f4cfa | 7713 | mvpp2_queue_vectors_deinit(port); |
fd3651b2 AT |
7714 | if (port->link_irq) |
7715 | irq_dispose_mapping(port->link_irq); | |
3f518509 MW |
7716 | free_netdev(port->dev); |
7717 | } | |
7718 | ||
7719 | /* Initialize decoding windows */ | |
7720 | static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, | |
7721 | struct mvpp2 *priv) | |
7722 | { | |
7723 | u32 win_enable; | |
7724 | int i; | |
7725 | ||
7726 | for (i = 0; i < 6; i++) { | |
7727 | mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); | |
7728 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); | |
7729 | ||
7730 | if (i < 4) | |
7731 | mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); | |
7732 | } | |
7733 | ||
7734 | win_enable = 0; | |
7735 | ||
7736 | for (i = 0; i < dram->num_cs; i++) { | |
7737 | const struct mbus_dram_window *cs = dram->cs + i; | |
7738 | ||
7739 | mvpp2_write(priv, MVPP2_WIN_BASE(i), | |
7740 | (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | | |
7741 | dram->mbus_dram_target_id); | |
7742 | ||
7743 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), | |
7744 | (cs->size - 1) & 0xffff0000); | |
7745 | ||
7746 | win_enable |= (1 << i); | |
7747 | } | |
7748 | ||
7749 | mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); | |
7750 | } | |
7751 | ||
7752 | /* Initialize Rx FIFO's */ | |
7753 | static void mvpp2_rx_fifo_init(struct mvpp2 *priv) | |
7754 | { | |
7755 | int port; | |
7756 | ||
7757 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
7758 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), | |
7759 | MVPP2_RX_FIFO_PORT_DATA_SIZE); | |
7760 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), | |
7761 | MVPP2_RX_FIFO_PORT_ATTR_SIZE); | |
7762 | } | |
7763 | ||
7764 | mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, | |
7765 | MVPP2_RX_FIFO_PORT_MIN_PKT); | |
7766 | mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); | |
7767 | } | |
7768 | ||
6763ce31 TP |
7769 | static void mvpp2_axi_init(struct mvpp2 *priv) |
7770 | { | |
7771 | u32 val, rdval, wrval; | |
7772 | ||
7773 | mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); | |
7774 | ||
7775 | /* AXI Bridge Configuration */ | |
7776 | ||
7777 | rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
7778 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
7779 | rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7780 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
7781 | ||
7782 | wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
7783 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
7784 | wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7785 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
7786 | ||
7787 | /* BM */ | |
7788 | mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); | |
7789 | mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); | |
7790 | ||
7791 | /* Descriptors */ | |
7792 | mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); | |
7793 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); | |
7794 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); | |
7795 | mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); | |
7796 | ||
7797 | /* Buffer Data */ | |
7798 | mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); | |
7799 | mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); | |
7800 | ||
7801 | val = MVPP22_AXI_CODE_CACHE_NON_CACHE | |
7802 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
7803 | val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM | |
7804 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
7805 | mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); | |
7806 | mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); | |
7807 | ||
7808 | val = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
7809 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
7810 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7811 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
7812 | ||
7813 | mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); | |
7814 | ||
7815 | val = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
7816 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
7817 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7818 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
7819 | ||
7820 | mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); | |
7821 | } | |
7822 | ||
3f518509 MW |
7823 | /* Initialize network controller common part HW */ |
7824 | static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) | |
7825 | { | |
7826 | const struct mbus_dram_target_info *dram_target_info; | |
7827 | int err, i; | |
08a23755 | 7828 | u32 val; |
3f518509 | 7829 | |
3f518509 MW |
7830 | /* MBUS windows configuration */ |
7831 | dram_target_info = mv_mbus_dram_info(); | |
7832 | if (dram_target_info) | |
7833 | mvpp2_conf_mbus_windows(dram_target_info, priv); | |
7834 | ||
6763ce31 TP |
7835 | if (priv->hw_version == MVPP22) |
7836 | mvpp2_axi_init(priv); | |
7837 | ||
08a23755 | 7838 | /* Disable HW PHY polling */ |
26975821 TP |
7839 | if (priv->hw_version == MVPP21) { |
7840 | val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
7841 | val |= MVPP2_PHY_AN_STOP_SMI0_MASK; | |
7842 | writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
7843 | } else { | |
7844 | val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
7845 | val &= ~MVPP22_SMI_POLLING_EN; | |
7846 | writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
7847 | } | |
08a23755 | 7848 | |
3f518509 MW |
7849 | /* Allocate and initialize aggregated TXQs */ |
7850 | priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), | |
d7ce3cec | 7851 | sizeof(*priv->aggr_txqs), |
3f518509 MW |
7852 | GFP_KERNEL); |
7853 | if (!priv->aggr_txqs) | |
7854 | return -ENOMEM; | |
7855 | ||
7856 | for_each_present_cpu(i) { | |
7857 | priv->aggr_txqs[i].id = i; | |
7858 | priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; | |
85affd7e | 7859 | err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); |
3f518509 MW |
7860 | if (err < 0) |
7861 | return err; | |
7862 | } | |
7863 | ||
7864 | /* Rx Fifo Init */ | |
7865 | mvpp2_rx_fifo_init(priv); | |
7866 | ||
26975821 TP |
7867 | if (priv->hw_version == MVPP21) |
7868 | writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, | |
7869 | priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); | |
3f518509 MW |
7870 | |
7871 | /* Allow cache snoop when transmiting packets */ | |
7872 | mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); | |
7873 | ||
7874 | /* Buffer Manager initialization */ | |
7875 | err = mvpp2_bm_init(pdev, priv); | |
7876 | if (err < 0) | |
7877 | return err; | |
7878 | ||
7879 | /* Parser default initialization */ | |
7880 | err = mvpp2_prs_default_init(pdev, priv); | |
7881 | if (err < 0) | |
7882 | return err; | |
7883 | ||
7884 | /* Classifier default initialization */ | |
7885 | mvpp2_cls_init(priv); | |
7886 | ||
7887 | return 0; | |
7888 | } | |
7889 | ||
7890 | static int mvpp2_probe(struct platform_device *pdev) | |
7891 | { | |
7892 | struct device_node *dn = pdev->dev.of_node; | |
7893 | struct device_node *port_node; | |
7894 | struct mvpp2 *priv; | |
7895 | struct resource *res; | |
a786841d | 7896 | void __iomem *base; |
df089aa0 | 7897 | int port_count, i; |
3f518509 MW |
7898 | int err; |
7899 | ||
0b92e594 | 7900 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
3f518509 MW |
7901 | if (!priv) |
7902 | return -ENOMEM; | |
7903 | ||
faca9247 TP |
7904 | priv->hw_version = |
7905 | (unsigned long)of_device_get_match_data(&pdev->dev); | |
7906 | ||
3f518509 | 7907 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a786841d TP |
7908 | base = devm_ioremap_resource(&pdev->dev, res); |
7909 | if (IS_ERR(base)) | |
7910 | return PTR_ERR(base); | |
7911 | ||
7912 | if (priv->hw_version == MVPP21) { | |
7913 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
7914 | priv->lms_base = devm_ioremap_resource(&pdev->dev, res); | |
7915 | if (IS_ERR(priv->lms_base)) | |
7916 | return PTR_ERR(priv->lms_base); | |
7917 | } else { | |
7918 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
7919 | priv->iface_base = devm_ioremap_resource(&pdev->dev, res); | |
7920 | if (IS_ERR(priv->iface_base)) | |
7921 | return PTR_ERR(priv->iface_base); | |
f84bf386 AT |
7922 | |
7923 | priv->sysctrl_base = | |
7924 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
7925 | "marvell,system-controller"); | |
7926 | if (IS_ERR(priv->sysctrl_base)) | |
7927 | /* The system controller regmap is optional for dt | |
7928 | * compatibility reasons. When not provided, the | |
7929 | * configuration of the GoP relies on the | |
7930 | * firmware/bootloader. | |
7931 | */ | |
7932 | priv->sysctrl_base = NULL; | |
a786841d TP |
7933 | } |
7934 | ||
df089aa0 | 7935 | for (i = 0; i < MVPP2_MAX_THREADS; i++) { |
a786841d TP |
7936 | u32 addr_space_sz; |
7937 | ||
7938 | addr_space_sz = (priv->hw_version == MVPP21 ? | |
7939 | MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); | |
df089aa0 | 7940 | priv->swth_base[i] = base + i * addr_space_sz; |
a786841d | 7941 | } |
3f518509 | 7942 | |
59b9a31e TP |
7943 | if (priv->hw_version == MVPP21) |
7944 | priv->max_port_rxqs = 8; | |
7945 | else | |
7946 | priv->max_port_rxqs = 32; | |
7947 | ||
3f518509 MW |
7948 | priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); |
7949 | if (IS_ERR(priv->pp_clk)) | |
7950 | return PTR_ERR(priv->pp_clk); | |
7951 | err = clk_prepare_enable(priv->pp_clk); | |
7952 | if (err < 0) | |
7953 | return err; | |
7954 | ||
7955 | priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); | |
7956 | if (IS_ERR(priv->gop_clk)) { | |
7957 | err = PTR_ERR(priv->gop_clk); | |
7958 | goto err_pp_clk; | |
7959 | } | |
7960 | err = clk_prepare_enable(priv->gop_clk); | |
7961 | if (err < 0) | |
7962 | goto err_pp_clk; | |
7963 | ||
fceb55d4 TP |
7964 | if (priv->hw_version == MVPP22) { |
7965 | priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); | |
7966 | if (IS_ERR(priv->mg_clk)) { | |
7967 | err = PTR_ERR(priv->mg_clk); | |
7968 | goto err_gop_clk; | |
7969 | } | |
7970 | ||
7971 | err = clk_prepare_enable(priv->mg_clk); | |
7972 | if (err < 0) | |
7973 | goto err_gop_clk; | |
4792ea04 GC |
7974 | |
7975 | priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); | |
7976 | if (IS_ERR(priv->axi_clk)) { | |
7977 | err = PTR_ERR(priv->axi_clk); | |
7978 | if (err == -EPROBE_DEFER) | |
7979 | goto err_gop_clk; | |
7980 | priv->axi_clk = NULL; | |
7981 | } else { | |
7982 | err = clk_prepare_enable(priv->axi_clk); | |
7983 | if (err < 0) | |
7984 | goto err_gop_clk; | |
7985 | } | |
fceb55d4 TP |
7986 | } |
7987 | ||
3f518509 MW |
7988 | /* Get system's tclk rate */ |
7989 | priv->tclk = clk_get_rate(priv->pp_clk); | |
7990 | ||
2067e0a1 TP |
7991 | if (priv->hw_version == MVPP22) { |
7992 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); | |
7993 | if (err) | |
7994 | goto err_mg_clk; | |
7995 | /* Sadly, the BM pools all share the same register to | |
7996 | * store the high 32 bits of their address. So they | |
7997 | * must all have the same high 32 bits, which forces | |
7998 | * us to restrict coherent memory to DMA_BIT_MASK(32). | |
7999 | */ | |
8000 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
8001 | if (err) | |
8002 | goto err_mg_clk; | |
8003 | } | |
8004 | ||
3f518509 MW |
8005 | /* Initialize network controller */ |
8006 | err = mvpp2_init(pdev, priv); | |
8007 | if (err < 0) { | |
8008 | dev_err(&pdev->dev, "failed to initialize controller\n"); | |
fceb55d4 | 8009 | goto err_mg_clk; |
3f518509 MW |
8010 | } |
8011 | ||
8012 | port_count = of_get_available_child_count(dn); | |
8013 | if (port_count == 0) { | |
8014 | dev_err(&pdev->dev, "no ports enabled\n"); | |
575a1935 | 8015 | err = -ENODEV; |
fceb55d4 | 8016 | goto err_mg_clk; |
3f518509 MW |
8017 | } |
8018 | ||
8019 | priv->port_list = devm_kcalloc(&pdev->dev, port_count, | |
0b92e594 ME |
8020 | sizeof(*priv->port_list), |
8021 | GFP_KERNEL); | |
3f518509 MW |
8022 | if (!priv->port_list) { |
8023 | err = -ENOMEM; | |
fceb55d4 | 8024 | goto err_mg_clk; |
3f518509 MW |
8025 | } |
8026 | ||
8027 | /* Initialize ports */ | |
6bf69a1d | 8028 | i = 0; |
3f518509 | 8029 | for_each_available_child_of_node(dn, port_node) { |
6bf69a1d | 8030 | err = mvpp2_port_probe(pdev, port_node, priv, i); |
3f518509 | 8031 | if (err < 0) |
fceb55d4 | 8032 | goto err_mg_clk; |
6bf69a1d | 8033 | i++; |
3f518509 MW |
8034 | } |
8035 | ||
8036 | platform_set_drvdata(pdev, priv); | |
8037 | return 0; | |
8038 | ||
fceb55d4 | 8039 | err_mg_clk: |
4792ea04 | 8040 | clk_disable_unprepare(priv->axi_clk); |
fceb55d4 TP |
8041 | if (priv->hw_version == MVPP22) |
8042 | clk_disable_unprepare(priv->mg_clk); | |
3f518509 MW |
8043 | err_gop_clk: |
8044 | clk_disable_unprepare(priv->gop_clk); | |
8045 | err_pp_clk: | |
8046 | clk_disable_unprepare(priv->pp_clk); | |
8047 | return err; | |
8048 | } | |
8049 | ||
8050 | static int mvpp2_remove(struct platform_device *pdev) | |
8051 | { | |
8052 | struct mvpp2 *priv = platform_get_drvdata(pdev); | |
8053 | struct device_node *dn = pdev->dev.of_node; | |
8054 | struct device_node *port_node; | |
8055 | int i = 0; | |
8056 | ||
8057 | for_each_available_child_of_node(dn, port_node) { | |
8058 | if (priv->port_list[i]) | |
8059 | mvpp2_port_remove(priv->port_list[i]); | |
8060 | i++; | |
8061 | } | |
8062 | ||
8063 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
8064 | struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; | |
8065 | ||
8066 | mvpp2_bm_pool_destroy(pdev, priv, bm_pool); | |
8067 | } | |
8068 | ||
8069 | for_each_present_cpu(i) { | |
8070 | struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; | |
8071 | ||
8072 | dma_free_coherent(&pdev->dev, | |
8073 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, | |
8074 | aggr_txq->descs, | |
20396136 | 8075 | aggr_txq->descs_dma); |
3f518509 MW |
8076 | } |
8077 | ||
4792ea04 | 8078 | clk_disable_unprepare(priv->axi_clk); |
fceb55d4 | 8079 | clk_disable_unprepare(priv->mg_clk); |
3f518509 MW |
8080 | clk_disable_unprepare(priv->pp_clk); |
8081 | clk_disable_unprepare(priv->gop_clk); | |
8082 | ||
8083 | return 0; | |
8084 | } | |
8085 | ||
8086 | static const struct of_device_id mvpp2_match[] = { | |
faca9247 TP |
8087 | { |
8088 | .compatible = "marvell,armada-375-pp2", | |
8089 | .data = (void *)MVPP21, | |
8090 | }, | |
fc5e1550 TP |
8091 | { |
8092 | .compatible = "marvell,armada-7k-pp22", | |
8093 | .data = (void *)MVPP22, | |
8094 | }, | |
3f518509 MW |
8095 | { } |
8096 | }; | |
8097 | MODULE_DEVICE_TABLE(of, mvpp2_match); | |
8098 | ||
8099 | static struct platform_driver mvpp2_driver = { | |
8100 | .probe = mvpp2_probe, | |
8101 | .remove = mvpp2_remove, | |
8102 | .driver = { | |
8103 | .name = MVPP2_DRIVER_NAME, | |
8104 | .of_match_table = mvpp2_match, | |
8105 | }, | |
8106 | }; | |
8107 | ||
8108 | module_platform_driver(mvpp2_driver); | |
8109 | ||
8110 | MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); | |
8111 | MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); | |
c634099d | 8112 | MODULE_LICENSE("GPL v2"); |