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3f518509 MW |
1 | /* |
2 | * Driver for Marvell PPv2 network controller for Armada 375 SoC. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Marcin Wojtas <mw@semihalf.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/skbuff.h> | |
18 | #include <linux/inetdevice.h> | |
19 | #include <linux/mbus.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/cpumask.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/of_mdio.h> | |
26 | #include <linux/of_net.h> | |
27 | #include <linux/of_address.h> | |
faca9247 | 28 | #include <linux/of_device.h> |
3f518509 MW |
29 | #include <linux/phy.h> |
30 | #include <linux/clk.h> | |
edc660fa MW |
31 | #include <linux/hrtimer.h> |
32 | #include <linux/ktime.h> | |
3f518509 MW |
33 | #include <uapi/linux/ppp_defs.h> |
34 | #include <net/ip.h> | |
35 | #include <net/ipv6.h> | |
36 | ||
37 | /* RX Fifo Registers */ | |
38 | #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) | |
39 | #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) | |
40 | #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 | |
41 | #define MVPP2_RX_FIFO_INIT_REG 0x64 | |
42 | ||
43 | /* RX DMA Top Registers */ | |
44 | #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) | |
45 | #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) | |
46 | #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) | |
47 | #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) | |
48 | #define MVPP2_POOL_BUF_SIZE_OFFSET 5 | |
49 | #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) | |
50 | #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff | |
51 | #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) | |
52 | #define MVPP2_RXQ_POOL_SHORT_OFFS 20 | |
5eac892a TP |
53 | #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 |
54 | #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 | |
3f518509 | 55 | #define MVPP2_RXQ_POOL_LONG_OFFS 24 |
5eac892a TP |
56 | #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 |
57 | #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 | |
3f518509 MW |
58 | #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 |
59 | #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 | |
60 | #define MVPP2_RXQ_DISABLE_MASK BIT(31) | |
61 | ||
62 | /* Parser Registers */ | |
63 | #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 | |
64 | #define MVPP2_PRS_PORT_LU_MAX 0xf | |
65 | #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) | |
66 | #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) | |
67 | #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) | |
68 | #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) | |
69 | #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
70 | #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) | |
71 | #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) | |
72 | #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
73 | #define MVPP2_PRS_TCAM_IDX_REG 0x1100 | |
74 | #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) | |
75 | #define MVPP2_PRS_TCAM_INV_MASK BIT(31) | |
76 | #define MVPP2_PRS_SRAM_IDX_REG 0x1200 | |
77 | #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) | |
78 | #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 | |
79 | #define MVPP2_PRS_TCAM_EN_MASK BIT(0) | |
80 | ||
81 | /* Classifier Registers */ | |
82 | #define MVPP2_CLS_MODE_REG 0x1800 | |
83 | #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) | |
84 | #define MVPP2_CLS_PORT_WAY_REG 0x1810 | |
85 | #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) | |
86 | #define MVPP2_CLS_LKP_INDEX_REG 0x1814 | |
87 | #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 | |
88 | #define MVPP2_CLS_LKP_TBL_REG 0x1818 | |
89 | #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff | |
90 | #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) | |
91 | #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 | |
92 | #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 | |
93 | #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 | |
94 | #define MVPP2_CLS_FLOW_TBL2_REG 0x182c | |
95 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) | |
96 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 | |
97 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 | |
98 | #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) | |
99 | #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 | |
100 | #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) | |
101 | ||
102 | /* Descriptor Manager Top Registers */ | |
103 | #define MVPP2_RXQ_NUM_REG 0x2040 | |
104 | #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 | |
b02f31fb | 105 | #define MVPP22_DESC_ADDR_OFFS 8 |
3f518509 MW |
106 | #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 |
107 | #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 | |
108 | #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) | |
109 | #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 | |
110 | #define MVPP2_RXQ_NUM_NEW_OFFSET 16 | |
111 | #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) | |
112 | #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff | |
113 | #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 | |
114 | #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 | |
115 | #define MVPP2_RXQ_THRESH_REG 0x204c | |
116 | #define MVPP2_OCCUPIED_THRESH_OFFSET 0 | |
117 | #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff | |
118 | #define MVPP2_RXQ_INDEX_REG 0x2050 | |
119 | #define MVPP2_TXQ_NUM_REG 0x2080 | |
120 | #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 | |
121 | #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 | |
122 | #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 | |
213f428f TP |
123 | #define MVPP2_TXQ_THRESH_REG 0x2094 |
124 | #define MVPP2_TXQ_THRESH_OFFSET 16 | |
125 | #define MVPP2_TXQ_THRESH_MASK 0x3fff | |
3f518509 | 126 | #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 |
3f518509 MW |
127 | #define MVPP2_TXQ_INDEX_REG 0x2098 |
128 | #define MVPP2_TXQ_PREF_BUF_REG 0x209c | |
129 | #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) | |
130 | #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) | |
131 | #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) | |
132 | #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) | |
133 | #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) | |
134 | #define MVPP2_TXQ_PENDING_REG 0x20a0 | |
135 | #define MVPP2_TXQ_PENDING_MASK 0x3fff | |
136 | #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 | |
137 | #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) | |
138 | #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 | |
139 | #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 | |
140 | #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 | |
141 | #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 | |
142 | #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 | |
143 | #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff | |
144 | #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 | |
145 | #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 | |
146 | #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) | |
b02f31fb | 147 | #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 |
3f518509 MW |
148 | #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) |
149 | #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 | |
150 | #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) | |
151 | #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff | |
152 | #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) | |
153 | ||
154 | /* MBUS bridge registers */ | |
155 | #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) | |
156 | #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) | |
157 | #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) | |
158 | #define MVPP2_BASE_ADDR_ENABLE 0x4060 | |
159 | ||
6763ce31 TP |
160 | /* AXI Bridge Registers */ |
161 | #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 | |
162 | #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 | |
163 | #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 | |
164 | #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 | |
165 | #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 | |
166 | #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c | |
167 | #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 | |
168 | #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 | |
169 | #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 | |
170 | #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 | |
171 | #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 | |
172 | #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 | |
173 | ||
174 | /* Values for AXI Bridge registers */ | |
175 | #define MVPP22_AXI_ATTR_CACHE_OFFS 0 | |
176 | #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 | |
177 | ||
178 | #define MVPP22_AXI_CODE_CACHE_OFFS 0 | |
179 | #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 | |
180 | ||
181 | #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 | |
182 | #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 | |
183 | #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb | |
184 | ||
185 | #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 | |
186 | #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 | |
187 | ||
3f518509 | 188 | /* Interrupt Cause and Mask registers */ |
213f428f TP |
189 | #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) |
190 | #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 | |
191 | ||
3f518509 | 192 | #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) |
ab42676a | 193 | #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 |
eb1e93a1 | 194 | #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) |
a73fef10 | 195 | |
81b6630f | 196 | #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 |
a73fef10 | 197 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf |
81b6630f AT |
198 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
199 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 | |
a73fef10 TP |
200 | |
201 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf | |
81b6630f | 202 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
a73fef10 | 203 | |
81b6630f AT |
204 | #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 |
205 | #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f | |
206 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 | |
207 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 | |
a73fef10 | 208 | |
3f518509 MW |
209 | #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) |
210 | #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) | |
211 | #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) | |
212 | #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) | |
213 | #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
214 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 | |
213f428f | 215 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 |
3f518509 MW |
216 | #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) |
217 | #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) | |
218 | #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) | |
219 | #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) | |
220 | #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) | |
221 | #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) | |
222 | #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) | |
223 | #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc | |
224 | #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
225 | #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 | |
226 | #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) | |
227 | #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 | |
228 | ||
229 | /* Buffer Manager registers */ | |
230 | #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) | |
231 | #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 | |
232 | #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) | |
233 | #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 | |
234 | #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) | |
235 | #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 | |
236 | #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) | |
237 | #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 | |
238 | #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) | |
239 | #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) | |
240 | #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff | |
241 | #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) | |
242 | #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) | |
243 | #define MVPP2_BM_START_MASK BIT(0) | |
244 | #define MVPP2_BM_STOP_MASK BIT(1) | |
245 | #define MVPP2_BM_STATE_MASK BIT(4) | |
246 | #define MVPP2_BM_LOW_THRESH_OFFS 8 | |
247 | #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 | |
248 | #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ | |
249 | MVPP2_BM_LOW_THRESH_OFFS) | |
250 | #define MVPP2_BM_HIGH_THRESH_OFFS 16 | |
251 | #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 | |
252 | #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ | |
253 | MVPP2_BM_HIGH_THRESH_OFFS) | |
254 | #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) | |
255 | #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) | |
256 | #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) | |
257 | #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) | |
258 | #define MVPP2_BM_BPPE_FULL_MASK BIT(3) | |
259 | #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) | |
260 | #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) | |
261 | #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) | |
262 | #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) | |
263 | #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 | |
d01524d8 TP |
264 | #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 |
265 | #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff | |
266 | #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 | |
267 | #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 | |
3f518509 MW |
268 | #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) |
269 | #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) | |
270 | #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) | |
271 | #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) | |
272 | #define MVPP2_BM_VIRT_RLS_REG 0x64c0 | |
d01524d8 TP |
273 | #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 |
274 | #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff | |
81b6630f | 275 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 |
d01524d8 | 276 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 |
3f518509 MW |
277 | |
278 | /* TX Scheduler registers */ | |
279 | #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 | |
280 | #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 | |
281 | #define MVPP2_TXP_SCHED_ENQ_MASK 0xff | |
282 | #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 | |
283 | #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 | |
284 | #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 | |
285 | #define MVPP2_TXP_SCHED_MTU_REG 0x801c | |
286 | #define MVPP2_TXP_MTU_MAX 0x7FFFF | |
287 | #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 | |
288 | #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff | |
289 | #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
290 | #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) | |
291 | #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 | |
292 | #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff | |
293 | #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) | |
294 | #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff | |
295 | #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
296 | #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) | |
297 | #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) | |
298 | #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
299 | #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) | |
300 | #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff | |
301 | ||
302 | /* TX general registers */ | |
303 | #define MVPP2_TX_SNOOP_REG 0x8800 | |
304 | #define MVPP2_TX_PORT_FLUSH_REG 0x8810 | |
305 | #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) | |
306 | ||
307 | /* LMS registers */ | |
308 | #define MVPP2_SRC_ADDR_MIDDLE 0x24 | |
309 | #define MVPP2_SRC_ADDR_HIGH 0x28 | |
08a23755 MW |
310 | #define MVPP2_PHY_AN_CFG0_REG 0x34 |
311 | #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) | |
3f518509 | 312 | #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c |
31d7677b | 313 | #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 |
3f518509 MW |
314 | |
315 | /* Per-port registers */ | |
316 | #define MVPP2_GMAC_CTRL_0_REG 0x0 | |
81b6630f | 317 | #define MVPP2_GMAC_PORT_EN_MASK BIT(0) |
3919357f | 318 | #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) |
81b6630f AT |
319 | #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 |
320 | #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
321 | #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) | |
3f518509 | 322 | #define MVPP2_GMAC_CTRL_1_REG 0x4 |
81b6630f AT |
323 | #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) |
324 | #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) | |
325 | #define MVPP2_GMAC_PCS_LB_EN_BIT 6 | |
326 | #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) | |
327 | #define MVPP2_GMAC_SA_LOW_OFFS 7 | |
3f518509 | 328 | #define MVPP2_GMAC_CTRL_2_REG 0x8 |
81b6630f | 329 | #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) |
3919357f | 330 | #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) |
81b6630f AT |
331 | #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) |
332 | #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4) | |
3919357f | 333 | #define MVPP2_GMAC_DISABLE_PADDING BIT(5) |
81b6630f | 334 | #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) |
3f518509 | 335 | #define MVPP2_GMAC_AUTONEG_CONFIG 0xc |
81b6630f AT |
336 | #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) |
337 | #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) | |
3919357f AT |
338 | #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) |
339 | #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) | |
81b6630f AT |
340 | #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) |
341 | #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) | |
342 | #define MVPP2_GMAC_AN_SPEED_EN BIT(7) | |
343 | #define MVPP2_GMAC_FC_ADV_EN BIT(9) | |
3919357f | 344 | #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) |
81b6630f AT |
345 | #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
346 | #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) | |
3f518509 | 347 | #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c |
81b6630f AT |
348 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 |
349 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 | |
350 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ | |
3f518509 | 351 | MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) |
26975821 | 352 | #define MVPP22_GMAC_CTRL_4_REG 0x90 |
81b6630f AT |
353 | #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) |
354 | #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) | |
1068ec79 | 355 | #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) |
81b6630f | 356 | #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) |
26975821 TP |
357 | |
358 | /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, | |
359 | * relative to port->base. | |
360 | */ | |
725757ae | 361 | #define MVPP22_XLG_CTRL0_REG 0x100 |
81b6630f AT |
362 | #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) |
363 | #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) | |
77321959 | 364 | #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) |
81b6630f | 365 | #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) |
725757ae | 366 | |
26975821 | 367 | #define MVPP22_XLG_CTRL3_REG 0x11c |
81b6630f AT |
368 | #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) |
369 | #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) | |
370 | #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) | |
26975821 | 371 | |
77321959 AT |
372 | #define MVPP22_XLG_CTRL4_REG 0x184 |
373 | #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) | |
374 | #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) | |
375 | #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) | |
376 | ||
26975821 TP |
377 | /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ |
378 | #define MVPP22_SMI_MISC_CFG_REG 0x1204 | |
81b6630f | 379 | #define MVPP22_SMI_POLLING_EN BIT(10) |
3f518509 | 380 | |
a786841d TP |
381 | #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) |
382 | ||
3f518509 MW |
383 | #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
384 | ||
385 | /* Descriptor ring Macros */ | |
386 | #define MVPP2_QUEUE_NEXT_DESC(q, index) \ | |
387 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
388 | ||
389 | /* Various constants */ | |
390 | ||
391 | /* Coalescing */ | |
392 | #define MVPP2_TXDONE_COAL_PKTS_THRESH 15 | |
edc660fa | 393 | #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL |
213f428f | 394 | #define MVPP2_TXDONE_COAL_USEC 1000 |
3f518509 MW |
395 | #define MVPP2_RX_COAL_PKTS 32 |
396 | #define MVPP2_RX_COAL_USEC 100 | |
397 | ||
398 | /* The two bytes Marvell header. Either contains a special value used | |
399 | * by Marvell switches when a specific hardware mode is enabled (not | |
400 | * supported by this driver) or is filled automatically by zeroes on | |
401 | * the RX side. Those two bytes being at the front of the Ethernet | |
402 | * header, they allow to have the IP header aligned on a 4 bytes | |
403 | * boundary automatically: the hardware skips those two bytes on its | |
404 | * own. | |
405 | */ | |
406 | #define MVPP2_MH_SIZE 2 | |
407 | #define MVPP2_ETH_TYPE_LEN 2 | |
408 | #define MVPP2_PPPOE_HDR_SIZE 8 | |
409 | #define MVPP2_VLAN_TAG_LEN 4 | |
410 | ||
411 | /* Lbtd 802.3 type */ | |
412 | #define MVPP2_IP_LBDT_TYPE 0xfffa | |
413 | ||
3f518509 MW |
414 | #define MVPP2_TX_CSUM_MAX_SIZE 9800 |
415 | ||
416 | /* Timeout constants */ | |
417 | #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 | |
418 | #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 | |
419 | ||
420 | #define MVPP2_TX_MTU_MAX 0x7ffff | |
421 | ||
422 | /* Maximum number of T-CONTs of PON port */ | |
423 | #define MVPP2_MAX_TCONT 16 | |
424 | ||
425 | /* Maximum number of supported ports */ | |
426 | #define MVPP2_MAX_PORTS 4 | |
427 | ||
428 | /* Maximum number of TXQs used by single port */ | |
429 | #define MVPP2_MAX_TXQ 8 | |
430 | ||
3f518509 MW |
431 | /* Dfault number of RXQs in use */ |
432 | #define MVPP2_DEFAULT_RXQ 4 | |
433 | ||
3f518509 MW |
434 | /* Max number of Rx descriptors */ |
435 | #define MVPP2_MAX_RXD 128 | |
436 | ||
437 | /* Max number of Tx descriptors */ | |
438 | #define MVPP2_MAX_TXD 1024 | |
439 | ||
440 | /* Amount of Tx descriptors that can be reserved at once by CPU */ | |
441 | #define MVPP2_CPU_DESC_CHUNK 64 | |
442 | ||
443 | /* Max number of Tx descriptors in each aggregated queue */ | |
444 | #define MVPP2_AGGR_TXQ_SIZE 256 | |
445 | ||
446 | /* Descriptor aligned size */ | |
447 | #define MVPP2_DESC_ALIGNED_SIZE 32 | |
448 | ||
449 | /* Descriptor alignment mask */ | |
450 | #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) | |
451 | ||
452 | /* RX FIFO constants */ | |
453 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000 | |
454 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80 | |
455 | #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 | |
456 | ||
457 | /* RX buffer constants */ | |
458 | #define MVPP2_SKB_SHINFO_SIZE \ | |
459 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) | |
460 | ||
461 | #define MVPP2_RX_PKT_SIZE(mtu) \ | |
462 | ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ | |
4a0a12d2 | 463 | ETH_HLEN + ETH_FCS_LEN, cache_line_size()) |
3f518509 MW |
464 | |
465 | #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) | |
466 | #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) | |
467 | #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ | |
468 | ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) | |
469 | ||
470 | #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) | |
471 | ||
472 | /* IPv6 max L3 address size */ | |
473 | #define MVPP2_MAX_L3_ADDR_SIZE 16 | |
474 | ||
475 | /* Port flags */ | |
476 | #define MVPP2_F_LOOPBACK BIT(0) | |
477 | ||
478 | /* Marvell tag types */ | |
479 | enum mvpp2_tag_type { | |
480 | MVPP2_TAG_TYPE_NONE = 0, | |
481 | MVPP2_TAG_TYPE_MH = 1, | |
482 | MVPP2_TAG_TYPE_DSA = 2, | |
483 | MVPP2_TAG_TYPE_EDSA = 3, | |
484 | MVPP2_TAG_TYPE_VLAN = 4, | |
485 | MVPP2_TAG_TYPE_LAST = 5 | |
486 | }; | |
487 | ||
488 | /* Parser constants */ | |
489 | #define MVPP2_PRS_TCAM_SRAM_SIZE 256 | |
490 | #define MVPP2_PRS_TCAM_WORDS 6 | |
491 | #define MVPP2_PRS_SRAM_WORDS 4 | |
492 | #define MVPP2_PRS_FLOW_ID_SIZE 64 | |
493 | #define MVPP2_PRS_FLOW_ID_MASK 0x3f | |
494 | #define MVPP2_PRS_TCAM_ENTRY_INVALID 1 | |
495 | #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) | |
496 | #define MVPP2_PRS_IPV4_HEAD 0x40 | |
497 | #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 | |
498 | #define MVPP2_PRS_IPV4_MC 0xe0 | |
499 | #define MVPP2_PRS_IPV4_MC_MASK 0xf0 | |
500 | #define MVPP2_PRS_IPV4_BC_MASK 0xff | |
501 | #define MVPP2_PRS_IPV4_IHL 0x5 | |
502 | #define MVPP2_PRS_IPV4_IHL_MASK 0xf | |
503 | #define MVPP2_PRS_IPV6_MC 0xff | |
504 | #define MVPP2_PRS_IPV6_MC_MASK 0xff | |
505 | #define MVPP2_PRS_IPV6_HOP_MASK 0xff | |
506 | #define MVPP2_PRS_TCAM_PROTO_MASK 0xff | |
507 | #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f | |
508 | #define MVPP2_PRS_DBL_VLANS_MAX 100 | |
509 | ||
510 | /* Tcam structure: | |
511 | * - lookup ID - 4 bits | |
512 | * - port ID - 1 byte | |
513 | * - additional information - 1 byte | |
514 | * - header data - 8 bytes | |
515 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). | |
516 | */ | |
517 | #define MVPP2_PRS_AI_BITS 8 | |
518 | #define MVPP2_PRS_PORT_MASK 0xff | |
519 | #define MVPP2_PRS_LU_MASK 0xf | |
520 | #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \ | |
521 | (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) | |
522 | #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \ | |
523 | (((offs) * 2) - ((offs) % 2) + 2) | |
524 | #define MVPP2_PRS_TCAM_AI_BYTE 16 | |
525 | #define MVPP2_PRS_TCAM_PORT_BYTE 17 | |
526 | #define MVPP2_PRS_TCAM_LU_BYTE 20 | |
527 | #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) | |
528 | #define MVPP2_PRS_TCAM_INV_WORD 5 | |
529 | /* Tcam entries ID */ | |
530 | #define MVPP2_PE_DROP_ALL 0 | |
531 | #define MVPP2_PE_FIRST_FREE_TID 1 | |
532 | #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31) | |
533 | #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) | |
534 | #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29) | |
535 | #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) | |
536 | #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27) | |
537 | #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26) | |
538 | #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19) | |
539 | #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) | |
540 | #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) | |
541 | #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) | |
542 | #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) | |
543 | #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) | |
544 | #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13) | |
545 | #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12) | |
546 | #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11) | |
547 | #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10) | |
548 | #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9) | |
549 | #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8) | |
550 | #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7) | |
551 | #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6) | |
552 | #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5) | |
553 | #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4) | |
554 | #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3) | |
555 | #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) | |
556 | #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
557 | ||
558 | /* Sram structure | |
559 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). | |
560 | */ | |
561 | #define MVPP2_PRS_SRAM_RI_OFFS 0 | |
562 | #define MVPP2_PRS_SRAM_RI_WORD 0 | |
563 | #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 | |
564 | #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 | |
565 | #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 | |
566 | #define MVPP2_PRS_SRAM_SHIFT_OFFS 64 | |
567 | #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 | |
568 | #define MVPP2_PRS_SRAM_UDF_OFFS 73 | |
569 | #define MVPP2_PRS_SRAM_UDF_BITS 8 | |
570 | #define MVPP2_PRS_SRAM_UDF_MASK 0xff | |
571 | #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 | |
572 | #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 | |
573 | #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 | |
574 | #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 | |
575 | #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 | |
576 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 | |
577 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 | |
578 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 | |
579 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 | |
580 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 | |
581 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 | |
582 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 | |
583 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 | |
584 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 | |
585 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 | |
586 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 | |
587 | #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 | |
588 | #define MVPP2_PRS_SRAM_AI_OFFS 90 | |
589 | #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 | |
590 | #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 | |
591 | #define MVPP2_PRS_SRAM_AI_MASK 0xff | |
592 | #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 | |
593 | #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf | |
594 | #define MVPP2_PRS_SRAM_LU_DONE_BIT 110 | |
595 | #define MVPP2_PRS_SRAM_LU_GEN_BIT 111 | |
596 | ||
597 | /* Sram result info bits assignment */ | |
598 | #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 | |
599 | #define MVPP2_PRS_RI_DSA_MASK 0x2 | |
8138affc TP |
600 | #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) |
601 | #define MVPP2_PRS_RI_VLAN_NONE 0x0 | |
3f518509 MW |
602 | #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) |
603 | #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) | |
604 | #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) | |
605 | #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 | |
606 | #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) | |
8138affc TP |
607 | #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) |
608 | #define MVPP2_PRS_RI_L2_UCAST 0x0 | |
3f518509 MW |
609 | #define MVPP2_PRS_RI_L2_MCAST BIT(9) |
610 | #define MVPP2_PRS_RI_L2_BCAST BIT(10) | |
611 | #define MVPP2_PRS_RI_PPPOE_MASK 0x800 | |
8138affc TP |
612 | #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) |
613 | #define MVPP2_PRS_RI_L3_UN 0x0 | |
3f518509 MW |
614 | #define MVPP2_PRS_RI_L3_IP4 BIT(12) |
615 | #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) | |
616 | #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) | |
617 | #define MVPP2_PRS_RI_L3_IP6 BIT(14) | |
618 | #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) | |
619 | #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) | |
8138affc TP |
620 | #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) |
621 | #define MVPP2_PRS_RI_L3_UCAST 0x0 | |
3f518509 MW |
622 | #define MVPP2_PRS_RI_L3_MCAST BIT(15) |
623 | #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) | |
624 | #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 | |
625 | #define MVPP2_PRS_RI_UDF3_MASK 0x300000 | |
626 | #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) | |
627 | #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 | |
628 | #define MVPP2_PRS_RI_L4_TCP BIT(22) | |
629 | #define MVPP2_PRS_RI_L4_UDP BIT(23) | |
630 | #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) | |
631 | #define MVPP2_PRS_RI_UDF7_MASK 0x60000000 | |
632 | #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) | |
633 | #define MVPP2_PRS_RI_DROP_MASK 0x80000000 | |
634 | ||
635 | /* Sram additional info bits assignment */ | |
636 | #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) | |
637 | #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) | |
638 | #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) | |
639 | #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) | |
640 | #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) | |
641 | #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) | |
642 | #define MVPP2_PRS_SINGLE_VLAN_AI 0 | |
643 | #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) | |
644 | ||
645 | /* DSA/EDSA type */ | |
646 | #define MVPP2_PRS_TAGGED true | |
647 | #define MVPP2_PRS_UNTAGGED false | |
648 | #define MVPP2_PRS_EDSA true | |
649 | #define MVPP2_PRS_DSA false | |
650 | ||
651 | /* MAC entries, shadow udf */ | |
652 | enum mvpp2_prs_udf { | |
653 | MVPP2_PRS_UDF_MAC_DEF, | |
654 | MVPP2_PRS_UDF_MAC_RANGE, | |
655 | MVPP2_PRS_UDF_L2_DEF, | |
656 | MVPP2_PRS_UDF_L2_DEF_COPY, | |
657 | MVPP2_PRS_UDF_L2_USER, | |
658 | }; | |
659 | ||
660 | /* Lookup ID */ | |
661 | enum mvpp2_prs_lookup { | |
662 | MVPP2_PRS_LU_MH, | |
663 | MVPP2_PRS_LU_MAC, | |
664 | MVPP2_PRS_LU_DSA, | |
665 | MVPP2_PRS_LU_VLAN, | |
666 | MVPP2_PRS_LU_L2, | |
667 | MVPP2_PRS_LU_PPPOE, | |
668 | MVPP2_PRS_LU_IP4, | |
669 | MVPP2_PRS_LU_IP6, | |
670 | MVPP2_PRS_LU_FLOWS, | |
671 | MVPP2_PRS_LU_LAST, | |
672 | }; | |
673 | ||
674 | /* L3 cast enum */ | |
675 | enum mvpp2_prs_l3_cast { | |
676 | MVPP2_PRS_L3_UNI_CAST, | |
677 | MVPP2_PRS_L3_MULTI_CAST, | |
678 | MVPP2_PRS_L3_BROAD_CAST | |
679 | }; | |
680 | ||
681 | /* Classifier constants */ | |
682 | #define MVPP2_CLS_FLOWS_TBL_SIZE 512 | |
683 | #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 | |
684 | #define MVPP2_CLS_LKP_TBL_SIZE 64 | |
685 | ||
686 | /* BM constants */ | |
687 | #define MVPP2_BM_POOLS_NUM 8 | |
688 | #define MVPP2_BM_LONG_BUF_NUM 1024 | |
689 | #define MVPP2_BM_SHORT_BUF_NUM 2048 | |
690 | #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) | |
691 | #define MVPP2_BM_POOL_PTR_ALIGN 128 | |
692 | #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port) | |
693 | #define MVPP2_BM_SWF_SHORT_POOL 3 | |
694 | ||
695 | /* BM cookie (32 bits) definition */ | |
696 | #define MVPP2_BM_COOKIE_POOL_OFFS 8 | |
697 | #define MVPP2_BM_COOKIE_CPU_OFFS 24 | |
698 | ||
699 | /* BM short pool packet size | |
700 | * These value assure that for SWF the total number | |
701 | * of bytes allocated for each buffer will be 512 | |
702 | */ | |
703 | #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512) | |
704 | ||
a786841d TP |
705 | #define MVPP21_ADDR_SPACE_SZ 0 |
706 | #define MVPP22_ADDR_SPACE_SZ SZ_64K | |
707 | ||
df089aa0 | 708 | #define MVPP2_MAX_THREADS 8 |
591f4cfa | 709 | #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS |
a786841d | 710 | |
3f518509 MW |
711 | enum mvpp2_bm_type { |
712 | MVPP2_BM_FREE, | |
713 | MVPP2_BM_SWF_LONG, | |
714 | MVPP2_BM_SWF_SHORT | |
715 | }; | |
716 | ||
717 | /* Definitions */ | |
718 | ||
719 | /* Shared Packet Processor resources */ | |
720 | struct mvpp2 { | |
721 | /* Shared registers' base addresses */ | |
3f518509 | 722 | void __iomem *lms_base; |
a786841d TP |
723 | void __iomem *iface_base; |
724 | ||
df089aa0 TP |
725 | /* On PPv2.2, each "software thread" can access the base |
726 | * register through a separate address space, each 64 KB apart | |
727 | * from each other. Typically, such address spaces will be | |
728 | * used per CPU. | |
a786841d | 729 | */ |
df089aa0 | 730 | void __iomem *swth_base[MVPP2_MAX_THREADS]; |
3f518509 MW |
731 | |
732 | /* Common clocks */ | |
733 | struct clk *pp_clk; | |
734 | struct clk *gop_clk; | |
fceb55d4 | 735 | struct clk *mg_clk; |
3f518509 MW |
736 | |
737 | /* List of pointers to port structures */ | |
738 | struct mvpp2_port **port_list; | |
739 | ||
740 | /* Aggregated TXQs */ | |
741 | struct mvpp2_tx_queue *aggr_txqs; | |
742 | ||
743 | /* BM pools */ | |
744 | struct mvpp2_bm_pool *bm_pools; | |
745 | ||
746 | /* PRS shadow table */ | |
747 | struct mvpp2_prs_shadow *prs_shadow; | |
748 | /* PRS auxiliary table for double vlan entries control */ | |
749 | bool *prs_double_vlans; | |
750 | ||
751 | /* Tclk value */ | |
752 | u32 tclk; | |
faca9247 TP |
753 | |
754 | /* HW version */ | |
755 | enum { MVPP21, MVPP22 } hw_version; | |
59b9a31e TP |
756 | |
757 | /* Maximum number of RXQs per port */ | |
758 | unsigned int max_port_rxqs; | |
3f518509 MW |
759 | }; |
760 | ||
761 | struct mvpp2_pcpu_stats { | |
762 | struct u64_stats_sync syncp; | |
763 | u64 rx_packets; | |
764 | u64 rx_bytes; | |
765 | u64 tx_packets; | |
766 | u64 tx_bytes; | |
767 | }; | |
768 | ||
edc660fa MW |
769 | /* Per-CPU port control */ |
770 | struct mvpp2_port_pcpu { | |
771 | struct hrtimer tx_done_timer; | |
772 | bool timer_scheduled; | |
773 | /* Tasklet for egress finalization */ | |
774 | struct tasklet_struct tx_done_tasklet; | |
775 | }; | |
776 | ||
591f4cfa TP |
777 | struct mvpp2_queue_vector { |
778 | int irq; | |
779 | struct napi_struct napi; | |
780 | enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; | |
781 | int sw_thread_id; | |
782 | u16 sw_thread_mask; | |
783 | int first_rxq; | |
784 | int nrxqs; | |
785 | u32 pending_cause_rx; | |
786 | struct mvpp2_port *port; | |
787 | }; | |
788 | ||
3f518509 MW |
789 | struct mvpp2_port { |
790 | u8 id; | |
791 | ||
a786841d TP |
792 | /* Index of the port from the "group of ports" complex point |
793 | * of view | |
794 | */ | |
795 | int gop_id; | |
796 | ||
3f518509 MW |
797 | struct mvpp2 *priv; |
798 | ||
799 | /* Per-port registers' base address */ | |
800 | void __iomem *base; | |
801 | ||
802 | struct mvpp2_rx_queue **rxqs; | |
09f83975 | 803 | unsigned int nrxqs; |
3f518509 | 804 | struct mvpp2_tx_queue **txqs; |
09f83975 | 805 | unsigned int ntxqs; |
3f518509 MW |
806 | struct net_device *dev; |
807 | ||
808 | int pkt_size; | |
809 | ||
edc660fa MW |
810 | /* Per-CPU port control */ |
811 | struct mvpp2_port_pcpu __percpu *pcpu; | |
812 | ||
3f518509 MW |
813 | /* Flags */ |
814 | unsigned long flags; | |
815 | ||
816 | u16 tx_ring_size; | |
817 | u16 rx_ring_size; | |
818 | struct mvpp2_pcpu_stats __percpu *stats; | |
819 | ||
3f518509 MW |
820 | phy_interface_t phy_interface; |
821 | struct device_node *phy_node; | |
822 | unsigned int link; | |
823 | unsigned int duplex; | |
824 | unsigned int speed; | |
825 | ||
826 | struct mvpp2_bm_pool *pool_long; | |
827 | struct mvpp2_bm_pool *pool_short; | |
828 | ||
829 | /* Index of first port's physical RXQ */ | |
830 | u8 first_rxq; | |
591f4cfa TP |
831 | |
832 | struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; | |
833 | unsigned int nqvecs; | |
213f428f TP |
834 | bool has_tx_irqs; |
835 | ||
836 | u32 tx_time_coal; | |
3f518509 MW |
837 | }; |
838 | ||
839 | /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the | |
840 | * layout of the transmit and reception DMA descriptors, and their | |
841 | * layout is therefore defined by the hardware design | |
842 | */ | |
843 | ||
844 | #define MVPP2_TXD_L3_OFF_SHIFT 0 | |
845 | #define MVPP2_TXD_IP_HLEN_SHIFT 8 | |
846 | #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) | |
847 | #define MVPP2_TXD_L4_CSUM_NOT BIT(14) | |
848 | #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) | |
849 | #define MVPP2_TXD_PADDING_DISABLE BIT(23) | |
850 | #define MVPP2_TXD_L4_UDP BIT(24) | |
851 | #define MVPP2_TXD_L3_IP6 BIT(26) | |
852 | #define MVPP2_TXD_L_DESC BIT(28) | |
853 | #define MVPP2_TXD_F_DESC BIT(29) | |
854 | ||
855 | #define MVPP2_RXD_ERR_SUMMARY BIT(15) | |
856 | #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) | |
857 | #define MVPP2_RXD_ERR_CRC 0x0 | |
858 | #define MVPP2_RXD_ERR_OVERRUN BIT(13) | |
859 | #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) | |
860 | #define MVPP2_RXD_BM_POOL_ID_OFFS 16 | |
861 | #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) | |
862 | #define MVPP2_RXD_HWF_SYNC BIT(21) | |
863 | #define MVPP2_RXD_L4_CSUM_OK BIT(22) | |
864 | #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) | |
865 | #define MVPP2_RXD_L4_TCP BIT(25) | |
866 | #define MVPP2_RXD_L4_UDP BIT(26) | |
867 | #define MVPP2_RXD_L3_IP4 BIT(28) | |
868 | #define MVPP2_RXD_L3_IP6 BIT(30) | |
869 | #define MVPP2_RXD_BUF_HDR BIT(31) | |
870 | ||
054f6372 TP |
871 | /* HW TX descriptor for PPv2.1 */ |
872 | struct mvpp21_tx_desc { | |
3f518509 MW |
873 | u32 command; /* Options used by HW for packet transmitting.*/ |
874 | u8 packet_offset; /* the offset from the buffer beginning */ | |
875 | u8 phys_txq; /* destination queue ID */ | |
876 | u16 data_size; /* data size of transmitted packet in bytes */ | |
20396136 | 877 | u32 buf_dma_addr; /* physical addr of transmitted buffer */ |
3f518509 MW |
878 | u32 buf_cookie; /* cookie for access to TX buffer in tx path */ |
879 | u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ | |
880 | u32 reserved2; /* reserved (for future use) */ | |
881 | }; | |
882 | ||
054f6372 TP |
883 | /* HW RX descriptor for PPv2.1 */ |
884 | struct mvpp21_rx_desc { | |
3f518509 MW |
885 | u32 status; /* info about received packet */ |
886 | u16 reserved1; /* parser_info (for future use, PnC) */ | |
887 | u16 data_size; /* size of received packet in bytes */ | |
20396136 | 888 | u32 buf_dma_addr; /* physical address of the buffer */ |
3f518509 MW |
889 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
890 | u16 reserved2; /* gem_port_id (for future use, PON) */ | |
891 | u16 reserved3; /* csum_l4 (for future use, PnC) */ | |
892 | u8 reserved4; /* bm_qset (for future use, BM) */ | |
893 | u8 reserved5; | |
894 | u16 reserved6; /* classify_info (for future use, PnC) */ | |
895 | u32 reserved7; /* flow_id (for future use, PnC) */ | |
896 | u32 reserved8; | |
897 | }; | |
898 | ||
e7c5359f TP |
899 | /* HW TX descriptor for PPv2.2 */ |
900 | struct mvpp22_tx_desc { | |
901 | u32 command; | |
902 | u8 packet_offset; | |
903 | u8 phys_txq; | |
904 | u16 data_size; | |
905 | u64 reserved1; | |
906 | u64 buf_dma_addr_ptp; | |
907 | u64 buf_cookie_misc; | |
908 | }; | |
909 | ||
910 | /* HW RX descriptor for PPv2.2 */ | |
911 | struct mvpp22_rx_desc { | |
912 | u32 status; | |
913 | u16 reserved1; | |
914 | u16 data_size; | |
915 | u32 reserved2; | |
916 | u32 reserved3; | |
917 | u64 buf_dma_addr_key_hash; | |
918 | u64 buf_cookie_misc; | |
919 | }; | |
920 | ||
054f6372 TP |
921 | /* Opaque type used by the driver to manipulate the HW TX and RX |
922 | * descriptors | |
923 | */ | |
924 | struct mvpp2_tx_desc { | |
925 | union { | |
926 | struct mvpp21_tx_desc pp21; | |
e7c5359f | 927 | struct mvpp22_tx_desc pp22; |
054f6372 TP |
928 | }; |
929 | }; | |
930 | ||
931 | struct mvpp2_rx_desc { | |
932 | union { | |
933 | struct mvpp21_rx_desc pp21; | |
e7c5359f | 934 | struct mvpp22_rx_desc pp22; |
054f6372 TP |
935 | }; |
936 | }; | |
937 | ||
8354491c TP |
938 | struct mvpp2_txq_pcpu_buf { |
939 | /* Transmitted SKB */ | |
940 | struct sk_buff *skb; | |
941 | ||
942 | /* Physical address of transmitted buffer */ | |
20396136 | 943 | dma_addr_t dma; |
8354491c TP |
944 | |
945 | /* Size transmitted */ | |
946 | size_t size; | |
947 | }; | |
948 | ||
3f518509 MW |
949 | /* Per-CPU Tx queue control */ |
950 | struct mvpp2_txq_pcpu { | |
951 | int cpu; | |
952 | ||
953 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
954 | int size; | |
955 | ||
956 | /* Number of currently used Tx DMA descriptor in the | |
957 | * descriptor ring | |
958 | */ | |
959 | int count; | |
960 | ||
961 | /* Number of Tx DMA descriptors reserved for each CPU */ | |
962 | int reserved_num; | |
963 | ||
8354491c TP |
964 | /* Infos about transmitted buffers */ |
965 | struct mvpp2_txq_pcpu_buf *buffs; | |
71ce391d | 966 | |
3f518509 MW |
967 | /* Index of last TX DMA descriptor that was inserted */ |
968 | int txq_put_index; | |
969 | ||
970 | /* Index of the TX DMA descriptor to be cleaned up */ | |
971 | int txq_get_index; | |
972 | }; | |
973 | ||
974 | struct mvpp2_tx_queue { | |
975 | /* Physical number of this Tx queue */ | |
976 | u8 id; | |
977 | ||
978 | /* Logical number of this Tx queue */ | |
979 | u8 log_id; | |
980 | ||
981 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
982 | int size; | |
983 | ||
984 | /* Number of currently used Tx DMA descriptor in the descriptor ring */ | |
985 | int count; | |
986 | ||
987 | /* Per-CPU control of physical Tx queues */ | |
988 | struct mvpp2_txq_pcpu __percpu *pcpu; | |
989 | ||
3f518509 MW |
990 | u32 done_pkts_coal; |
991 | ||
992 | /* Virtual address of thex Tx DMA descriptors array */ | |
993 | struct mvpp2_tx_desc *descs; | |
994 | ||
995 | /* DMA address of the Tx DMA descriptors array */ | |
20396136 | 996 | dma_addr_t descs_dma; |
3f518509 MW |
997 | |
998 | /* Index of the last Tx DMA descriptor */ | |
999 | int last_desc; | |
1000 | ||
1001 | /* Index of the next Tx DMA descriptor to process */ | |
1002 | int next_desc_to_proc; | |
1003 | }; | |
1004 | ||
1005 | struct mvpp2_rx_queue { | |
1006 | /* RX queue number, in the range 0-31 for physical RXQs */ | |
1007 | u8 id; | |
1008 | ||
1009 | /* Num of rx descriptors in the rx descriptor ring */ | |
1010 | int size; | |
1011 | ||
1012 | u32 pkts_coal; | |
1013 | u32 time_coal; | |
1014 | ||
1015 | /* Virtual address of the RX DMA descriptors array */ | |
1016 | struct mvpp2_rx_desc *descs; | |
1017 | ||
1018 | /* DMA address of the RX DMA descriptors array */ | |
20396136 | 1019 | dma_addr_t descs_dma; |
3f518509 MW |
1020 | |
1021 | /* Index of the last RX DMA descriptor */ | |
1022 | int last_desc; | |
1023 | ||
1024 | /* Index of the next RX DMA descriptor to process */ | |
1025 | int next_desc_to_proc; | |
1026 | ||
1027 | /* ID of port to which physical RXQ is mapped */ | |
1028 | int port; | |
1029 | ||
1030 | /* Port's logic RXQ number to which physical RXQ is mapped */ | |
1031 | int logic_rxq; | |
1032 | }; | |
1033 | ||
1034 | union mvpp2_prs_tcam_entry { | |
1035 | u32 word[MVPP2_PRS_TCAM_WORDS]; | |
1036 | u8 byte[MVPP2_PRS_TCAM_WORDS * 4]; | |
1037 | }; | |
1038 | ||
1039 | union mvpp2_prs_sram_entry { | |
1040 | u32 word[MVPP2_PRS_SRAM_WORDS]; | |
1041 | u8 byte[MVPP2_PRS_SRAM_WORDS * 4]; | |
1042 | }; | |
1043 | ||
1044 | struct mvpp2_prs_entry { | |
1045 | u32 index; | |
1046 | union mvpp2_prs_tcam_entry tcam; | |
1047 | union mvpp2_prs_sram_entry sram; | |
1048 | }; | |
1049 | ||
1050 | struct mvpp2_prs_shadow { | |
1051 | bool valid; | |
1052 | bool finish; | |
1053 | ||
1054 | /* Lookup ID */ | |
1055 | int lu; | |
1056 | ||
1057 | /* User defined offset */ | |
1058 | int udf; | |
1059 | ||
1060 | /* Result info */ | |
1061 | u32 ri; | |
1062 | u32 ri_mask; | |
1063 | }; | |
1064 | ||
1065 | struct mvpp2_cls_flow_entry { | |
1066 | u32 index; | |
1067 | u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS]; | |
1068 | }; | |
1069 | ||
1070 | struct mvpp2_cls_lookup_entry { | |
1071 | u32 lkpid; | |
1072 | u32 way; | |
1073 | u32 data; | |
1074 | }; | |
1075 | ||
1076 | struct mvpp2_bm_pool { | |
1077 | /* Pool number in the range 0-7 */ | |
1078 | int id; | |
1079 | enum mvpp2_bm_type type; | |
1080 | ||
1081 | /* Buffer Pointers Pool External (BPPE) size */ | |
1082 | int size; | |
d01524d8 TP |
1083 | /* BPPE size in bytes */ |
1084 | int size_bytes; | |
3f518509 MW |
1085 | /* Number of buffers for this pool */ |
1086 | int buf_num; | |
1087 | /* Pool buffer size */ | |
1088 | int buf_size; | |
1089 | /* Packet size */ | |
1090 | int pkt_size; | |
0e037281 | 1091 | int frag_size; |
3f518509 MW |
1092 | |
1093 | /* BPPE virtual base address */ | |
1094 | u32 *virt_addr; | |
20396136 TP |
1095 | /* BPPE DMA base address */ |
1096 | dma_addr_t dma_addr; | |
3f518509 MW |
1097 | |
1098 | /* Ports using BM pool */ | |
1099 | u32 port_map; | |
3f518509 MW |
1100 | }; |
1101 | ||
213f428f TP |
1102 | /* Queue modes */ |
1103 | #define MVPP2_QDIST_SINGLE_MODE 0 | |
1104 | #define MVPP2_QDIST_MULTI_MODE 1 | |
1105 | ||
1106 | static int queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
1107 | ||
1108 | module_param(queue_mode, int, 0444); | |
1109 | MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); | |
1110 | ||
3f518509 MW |
1111 | #define MVPP2_DRIVER_NAME "mvpp2" |
1112 | #define MVPP2_DRIVER_VERSION "1.0" | |
1113 | ||
1114 | /* Utility/helper methods */ | |
1115 | ||
1116 | static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) | |
1117 | { | |
df089aa0 | 1118 | writel(data, priv->swth_base[0] + offset); |
3f518509 MW |
1119 | } |
1120 | ||
1121 | static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) | |
1122 | { | |
df089aa0 | 1123 | return readl(priv->swth_base[0] + offset); |
a786841d TP |
1124 | } |
1125 | ||
1126 | /* These accessors should be used to access: | |
1127 | * | |
1128 | * - per-CPU registers, where each CPU has its own copy of the | |
1129 | * register. | |
1130 | * | |
1131 | * MVPP2_BM_VIRT_ALLOC_REG | |
1132 | * MVPP2_BM_ADDR_HIGH_ALLOC | |
1133 | * MVPP22_BM_ADDR_HIGH_RLS_REG | |
1134 | * MVPP2_BM_VIRT_RLS_REG | |
1135 | * MVPP2_ISR_RX_TX_CAUSE_REG | |
1136 | * MVPP2_ISR_RX_TX_MASK_REG | |
1137 | * MVPP2_TXQ_NUM_REG | |
1138 | * MVPP2_AGGR_TXQ_UPDATE_REG | |
1139 | * MVPP2_TXQ_RSVD_REQ_REG | |
1140 | * MVPP2_TXQ_RSVD_RSLT_REG | |
1141 | * MVPP2_TXQ_SENT_REG | |
1142 | * MVPP2_RXQ_NUM_REG | |
1143 | * | |
1144 | * - global registers that must be accessed through a specific CPU | |
1145 | * window, because they are related to an access to a per-CPU | |
1146 | * register | |
1147 | * | |
1148 | * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) | |
1149 | * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) | |
1150 | * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) | |
1151 | * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) | |
1152 | * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) | |
1153 | * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) | |
1154 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1155 | * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) | |
1156 | * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) | |
1157 | * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) | |
1158 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1159 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1160 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1161 | */ | |
1162 | static void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, | |
1163 | u32 offset, u32 data) | |
1164 | { | |
df089aa0 | 1165 | writel(data, priv->swth_base[cpu] + offset); |
a786841d TP |
1166 | } |
1167 | ||
1168 | static u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, | |
1169 | u32 offset) | |
1170 | { | |
df089aa0 | 1171 | return readl(priv->swth_base[cpu] + offset); |
3f518509 MW |
1172 | } |
1173 | ||
ac3dd277 TP |
1174 | static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, |
1175 | struct mvpp2_tx_desc *tx_desc) | |
1176 | { | |
e7c5359f TP |
1177 | if (port->priv->hw_version == MVPP21) |
1178 | return tx_desc->pp21.buf_dma_addr; | |
1179 | else | |
1180 | return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1181 | } |
1182 | ||
1183 | static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, | |
1184 | struct mvpp2_tx_desc *tx_desc, | |
1185 | dma_addr_t dma_addr) | |
1186 | { | |
e7c5359f TP |
1187 | if (port->priv->hw_version == MVPP21) { |
1188 | tx_desc->pp21.buf_dma_addr = dma_addr; | |
1189 | } else { | |
1190 | u64 val = (u64)dma_addr; | |
1191 | ||
1192 | tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); | |
1193 | tx_desc->pp22.buf_dma_addr_ptp |= val; | |
1194 | } | |
ac3dd277 TP |
1195 | } |
1196 | ||
1197 | static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, | |
1198 | struct mvpp2_tx_desc *tx_desc) | |
1199 | { | |
e7c5359f TP |
1200 | if (port->priv->hw_version == MVPP21) |
1201 | return tx_desc->pp21.data_size; | |
1202 | else | |
1203 | return tx_desc->pp22.data_size; | |
ac3dd277 TP |
1204 | } |
1205 | ||
1206 | static void mvpp2_txdesc_size_set(struct mvpp2_port *port, | |
1207 | struct mvpp2_tx_desc *tx_desc, | |
1208 | size_t size) | |
1209 | { | |
e7c5359f TP |
1210 | if (port->priv->hw_version == MVPP21) |
1211 | tx_desc->pp21.data_size = size; | |
1212 | else | |
1213 | tx_desc->pp22.data_size = size; | |
ac3dd277 TP |
1214 | } |
1215 | ||
1216 | static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, | |
1217 | struct mvpp2_tx_desc *tx_desc, | |
1218 | unsigned int txq) | |
1219 | { | |
e7c5359f TP |
1220 | if (port->priv->hw_version == MVPP21) |
1221 | tx_desc->pp21.phys_txq = txq; | |
1222 | else | |
1223 | tx_desc->pp22.phys_txq = txq; | |
ac3dd277 TP |
1224 | } |
1225 | ||
1226 | static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, | |
1227 | struct mvpp2_tx_desc *tx_desc, | |
1228 | unsigned int command) | |
1229 | { | |
e7c5359f TP |
1230 | if (port->priv->hw_version == MVPP21) |
1231 | tx_desc->pp21.command = command; | |
1232 | else | |
1233 | tx_desc->pp22.command = command; | |
ac3dd277 TP |
1234 | } |
1235 | ||
1236 | static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, | |
1237 | struct mvpp2_tx_desc *tx_desc, | |
1238 | unsigned int offset) | |
1239 | { | |
e7c5359f TP |
1240 | if (port->priv->hw_version == MVPP21) |
1241 | tx_desc->pp21.packet_offset = offset; | |
1242 | else | |
1243 | tx_desc->pp22.packet_offset = offset; | |
ac3dd277 TP |
1244 | } |
1245 | ||
1246 | static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, | |
1247 | struct mvpp2_tx_desc *tx_desc) | |
1248 | { | |
e7c5359f TP |
1249 | if (port->priv->hw_version == MVPP21) |
1250 | return tx_desc->pp21.packet_offset; | |
1251 | else | |
1252 | return tx_desc->pp22.packet_offset; | |
ac3dd277 TP |
1253 | } |
1254 | ||
1255 | static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, | |
1256 | struct mvpp2_rx_desc *rx_desc) | |
1257 | { | |
e7c5359f TP |
1258 | if (port->priv->hw_version == MVPP21) |
1259 | return rx_desc->pp21.buf_dma_addr; | |
1260 | else | |
1261 | return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1262 | } |
1263 | ||
1264 | static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, | |
1265 | struct mvpp2_rx_desc *rx_desc) | |
1266 | { | |
e7c5359f TP |
1267 | if (port->priv->hw_version == MVPP21) |
1268 | return rx_desc->pp21.buf_cookie; | |
1269 | else | |
1270 | return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); | |
ac3dd277 TP |
1271 | } |
1272 | ||
1273 | static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, | |
1274 | struct mvpp2_rx_desc *rx_desc) | |
1275 | { | |
e7c5359f TP |
1276 | if (port->priv->hw_version == MVPP21) |
1277 | return rx_desc->pp21.data_size; | |
1278 | else | |
1279 | return rx_desc->pp22.data_size; | |
ac3dd277 TP |
1280 | } |
1281 | ||
1282 | static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, | |
1283 | struct mvpp2_rx_desc *rx_desc) | |
1284 | { | |
e7c5359f TP |
1285 | if (port->priv->hw_version == MVPP21) |
1286 | return rx_desc->pp21.status; | |
1287 | else | |
1288 | return rx_desc->pp22.status; | |
ac3dd277 TP |
1289 | } |
1290 | ||
3f518509 MW |
1291 | static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) |
1292 | { | |
1293 | txq_pcpu->txq_get_index++; | |
1294 | if (txq_pcpu->txq_get_index == txq_pcpu->size) | |
1295 | txq_pcpu->txq_get_index = 0; | |
1296 | } | |
1297 | ||
ac3dd277 TP |
1298 | static void mvpp2_txq_inc_put(struct mvpp2_port *port, |
1299 | struct mvpp2_txq_pcpu *txq_pcpu, | |
71ce391d MW |
1300 | struct sk_buff *skb, |
1301 | struct mvpp2_tx_desc *tx_desc) | |
3f518509 | 1302 | { |
8354491c TP |
1303 | struct mvpp2_txq_pcpu_buf *tx_buf = |
1304 | txq_pcpu->buffs + txq_pcpu->txq_put_index; | |
1305 | tx_buf->skb = skb; | |
ac3dd277 TP |
1306 | tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); |
1307 | tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + | |
1308 | mvpp2_txdesc_offset_get(port, tx_desc); | |
3f518509 MW |
1309 | txq_pcpu->txq_put_index++; |
1310 | if (txq_pcpu->txq_put_index == txq_pcpu->size) | |
1311 | txq_pcpu->txq_put_index = 0; | |
1312 | } | |
1313 | ||
1314 | /* Get number of physical egress port */ | |
1315 | static inline int mvpp2_egress_port(struct mvpp2_port *port) | |
1316 | { | |
1317 | return MVPP2_MAX_TCONT + port->id; | |
1318 | } | |
1319 | ||
1320 | /* Get number of physical TXQ */ | |
1321 | static inline int mvpp2_txq_phys(int port, int txq) | |
1322 | { | |
1323 | return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; | |
1324 | } | |
1325 | ||
1326 | /* Parser configuration routines */ | |
1327 | ||
1328 | /* Update parser tcam and sram hw entries */ | |
1329 | static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1330 | { | |
1331 | int i; | |
1332 | ||
1333 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1334 | return -EINVAL; | |
1335 | ||
1336 | /* Clear entry invalidation bit */ | |
1337 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; | |
1338 | ||
1339 | /* Write tcam index - indirect access */ | |
1340 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1341 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1342 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); | |
1343 | ||
1344 | /* Write sram index - indirect access */ | |
1345 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1346 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1347 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); | |
1348 | ||
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | /* Read tcam entry from hw */ | |
1353 | static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1354 | { | |
1355 | int i; | |
1356 | ||
1357 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1358 | return -EINVAL; | |
1359 | ||
1360 | /* Write tcam index - indirect access */ | |
1361 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1362 | ||
1363 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, | |
1364 | MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD)); | |
1365 | if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) | |
1366 | return MVPP2_PRS_TCAM_ENTRY_INVALID; | |
1367 | ||
1368 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1369 | pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); | |
1370 | ||
1371 | /* Write sram index - indirect access */ | |
1372 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1373 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1374 | pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | /* Invalidate tcam hw entry */ | |
1380 | static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index) | |
1381 | { | |
1382 | /* Write index - indirect access */ | |
1383 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
1384 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), | |
1385 | MVPP2_PRS_TCAM_INV_MASK); | |
1386 | } | |
1387 | ||
1388 | /* Enable shadow table entry and set its lookup ID */ | |
1389 | static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) | |
1390 | { | |
1391 | priv->prs_shadow[index].valid = true; | |
1392 | priv->prs_shadow[index].lu = lu; | |
1393 | } | |
1394 | ||
1395 | /* Update ri fields in shadow table entry */ | |
1396 | static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index, | |
1397 | unsigned int ri, unsigned int ri_mask) | |
1398 | { | |
1399 | priv->prs_shadow[index].ri_mask = ri_mask; | |
1400 | priv->prs_shadow[index].ri = ri; | |
1401 | } | |
1402 | ||
1403 | /* Update lookup field in tcam sw entry */ | |
1404 | static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) | |
1405 | { | |
1406 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE); | |
1407 | ||
1408 | pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; | |
1409 | pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; | |
1410 | } | |
1411 | ||
1412 | /* Update mask for single port in tcam sw entry */ | |
1413 | static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, | |
1414 | unsigned int port, bool add) | |
1415 | { | |
1416 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1417 | ||
1418 | if (add) | |
1419 | pe->tcam.byte[enable_off] &= ~(1 << port); | |
1420 | else | |
1421 | pe->tcam.byte[enable_off] |= 1 << port; | |
1422 | } | |
1423 | ||
1424 | /* Update port map in tcam sw entry */ | |
1425 | static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, | |
1426 | unsigned int ports) | |
1427 | { | |
1428 | unsigned char port_mask = MVPP2_PRS_PORT_MASK; | |
1429 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1430 | ||
1431 | pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; | |
1432 | pe->tcam.byte[enable_off] &= ~port_mask; | |
1433 | pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; | |
1434 | } | |
1435 | ||
1436 | /* Obtain port map from tcam sw entry */ | |
1437 | static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) | |
1438 | { | |
1439 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1440 | ||
1441 | return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; | |
1442 | } | |
1443 | ||
1444 | /* Set byte of data and its enable bits in tcam sw entry */ | |
1445 | static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, | |
1446 | unsigned int offs, unsigned char byte, | |
1447 | unsigned char enable) | |
1448 | { | |
1449 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; | |
1450 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; | |
1451 | } | |
1452 | ||
1453 | /* Get byte of data and its enable bits from tcam sw entry */ | |
1454 | static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, | |
1455 | unsigned int offs, unsigned char *byte, | |
1456 | unsigned char *enable) | |
1457 | { | |
1458 | *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; | |
1459 | *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; | |
1460 | } | |
1461 | ||
1462 | /* Compare tcam data bytes with a pattern */ | |
1463 | static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, | |
1464 | u16 data) | |
1465 | { | |
1466 | int off = MVPP2_PRS_TCAM_DATA_BYTE(offs); | |
1467 | u16 tcam_data; | |
1468 | ||
1469 | tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off]; | |
1470 | if (tcam_data != data) | |
1471 | return false; | |
1472 | return true; | |
1473 | } | |
1474 | ||
1475 | /* Update ai bits in tcam sw entry */ | |
1476 | static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, | |
1477 | unsigned int bits, unsigned int enable) | |
1478 | { | |
1479 | int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE; | |
1480 | ||
1481 | for (i = 0; i < MVPP2_PRS_AI_BITS; i++) { | |
1482 | ||
1483 | if (!(enable & BIT(i))) | |
1484 | continue; | |
1485 | ||
1486 | if (bits & BIT(i)) | |
1487 | pe->tcam.byte[ai_idx] |= 1 << i; | |
1488 | else | |
1489 | pe->tcam.byte[ai_idx] &= ~(1 << i); | |
1490 | } | |
1491 | ||
1492 | pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; | |
1493 | } | |
1494 | ||
1495 | /* Get ai bits from tcam sw entry */ | |
1496 | static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) | |
1497 | { | |
1498 | return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; | |
1499 | } | |
1500 | ||
1501 | /* Set ethertype in tcam sw entry */ | |
1502 | static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, | |
1503 | unsigned short ethertype) | |
1504 | { | |
1505 | mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); | |
1506 | mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); | |
1507 | } | |
1508 | ||
1509 | /* Set bits in sram sw entry */ | |
1510 | static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, | |
1511 | int val) | |
1512 | { | |
1513 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); | |
1514 | } | |
1515 | ||
1516 | /* Clear bits in sram sw entry */ | |
1517 | static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, | |
1518 | int val) | |
1519 | { | |
1520 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); | |
1521 | } | |
1522 | ||
1523 | /* Update ri bits in sram sw entry */ | |
1524 | static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, | |
1525 | unsigned int bits, unsigned int mask) | |
1526 | { | |
1527 | unsigned int i; | |
1528 | ||
1529 | for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) { | |
1530 | int ri_off = MVPP2_PRS_SRAM_RI_OFFS; | |
1531 | ||
1532 | if (!(mask & BIT(i))) | |
1533 | continue; | |
1534 | ||
1535 | if (bits & BIT(i)) | |
1536 | mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); | |
1537 | else | |
1538 | mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); | |
1539 | ||
1540 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | /* Obtain ri bits from sram sw entry */ | |
1545 | static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) | |
1546 | { | |
1547 | return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; | |
1548 | } | |
1549 | ||
1550 | /* Update ai bits in sram sw entry */ | |
1551 | static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, | |
1552 | unsigned int bits, unsigned int mask) | |
1553 | { | |
1554 | unsigned int i; | |
1555 | int ai_off = MVPP2_PRS_SRAM_AI_OFFS; | |
1556 | ||
1557 | for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) { | |
1558 | ||
1559 | if (!(mask & BIT(i))) | |
1560 | continue; | |
1561 | ||
1562 | if (bits & BIT(i)) | |
1563 | mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); | |
1564 | else | |
1565 | mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); | |
1566 | ||
1567 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | /* Read ai bits from sram sw entry */ | |
1572 | static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) | |
1573 | { | |
1574 | u8 bits; | |
1575 | int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS); | |
1576 | int ai_en_off = ai_off + 1; | |
1577 | int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8; | |
1578 | ||
1579 | bits = (pe->sram.byte[ai_off] >> ai_shift) | | |
1580 | (pe->sram.byte[ai_en_off] << (8 - ai_shift)); | |
1581 | ||
1582 | return bits; | |
1583 | } | |
1584 | ||
1585 | /* In sram sw entry set lookup ID field of the tcam key to be used in the next | |
1586 | * lookup interation | |
1587 | */ | |
1588 | static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, | |
1589 | unsigned int lu) | |
1590 | { | |
1591 | int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS; | |
1592 | ||
1593 | mvpp2_prs_sram_bits_clear(pe, sram_next_off, | |
1594 | MVPP2_PRS_SRAM_NEXT_LU_MASK); | |
1595 | mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); | |
1596 | } | |
1597 | ||
1598 | /* In the sram sw entry set sign and value of the next lookup offset | |
1599 | * and the offset value generated to the classifier | |
1600 | */ | |
1601 | static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, | |
1602 | unsigned int op) | |
1603 | { | |
1604 | /* Set sign */ | |
1605 | if (shift < 0) { | |
1606 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1607 | shift = 0 - shift; | |
1608 | } else { | |
1609 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1610 | } | |
1611 | ||
1612 | /* Set value */ | |
1613 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = | |
1614 | (unsigned char)shift; | |
1615 | ||
1616 | /* Reset and set operation */ | |
1617 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, | |
1618 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK); | |
1619 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); | |
1620 | ||
1621 | /* Set base offset as current */ | |
1622 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1623 | } | |
1624 | ||
1625 | /* In the sram sw entry set sign and value of the user defined offset | |
1626 | * generated to the classifier | |
1627 | */ | |
1628 | static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, | |
1629 | unsigned int type, int offset, | |
1630 | unsigned int op) | |
1631 | { | |
1632 | /* Set sign */ | |
1633 | if (offset < 0) { | |
1634 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1635 | offset = 0 - offset; | |
1636 | } else { | |
1637 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1638 | } | |
1639 | ||
1640 | /* Set value */ | |
1641 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, | |
1642 | MVPP2_PRS_SRAM_UDF_MASK); | |
1643 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); | |
1644 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1645 | MVPP2_PRS_SRAM_UDF_BITS)] &= | |
1646 | ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1647 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1648 | MVPP2_PRS_SRAM_UDF_BITS)] |= | |
1649 | (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1650 | ||
1651 | /* Set offset type */ | |
1652 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, | |
1653 | MVPP2_PRS_SRAM_UDF_TYPE_MASK); | |
1654 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); | |
1655 | ||
1656 | /* Set offset operation */ | |
1657 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, | |
1658 | MVPP2_PRS_SRAM_OP_SEL_UDF_MASK); | |
1659 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); | |
1660 | ||
1661 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1662 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &= | |
1663 | ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >> | |
1664 | (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1665 | ||
1666 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1667 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |= | |
1668 | (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1669 | ||
1670 | /* Set base offset as current */ | |
1671 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1672 | } | |
1673 | ||
1674 | /* Find parser flow entry */ | |
1675 | static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow) | |
1676 | { | |
1677 | struct mvpp2_prs_entry *pe; | |
1678 | int tid; | |
1679 | ||
1680 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
1681 | if (!pe) | |
1682 | return NULL; | |
1683 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); | |
1684 | ||
1685 | /* Go through the all entires with MVPP2_PRS_LU_FLOWS */ | |
1686 | for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { | |
1687 | u8 bits; | |
1688 | ||
1689 | if (!priv->prs_shadow[tid].valid || | |
1690 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) | |
1691 | continue; | |
1692 | ||
1693 | pe->index = tid; | |
1694 | mvpp2_prs_hw_read(priv, pe); | |
1695 | bits = mvpp2_prs_sram_ai_get(pe); | |
1696 | ||
1697 | /* Sram store classification lookup ID in AI bits [5:0] */ | |
1698 | if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow) | |
1699 | return pe; | |
1700 | } | |
1701 | kfree(pe); | |
1702 | ||
1703 | return NULL; | |
1704 | } | |
1705 | ||
1706 | /* Return first free tcam index, seeking from start to end */ | |
1707 | static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, | |
1708 | unsigned char end) | |
1709 | { | |
1710 | int tid; | |
1711 | ||
1712 | if (start > end) | |
1713 | swap(start, end); | |
1714 | ||
1715 | if (end >= MVPP2_PRS_TCAM_SRAM_SIZE) | |
1716 | end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; | |
1717 | ||
1718 | for (tid = start; tid <= end; tid++) { | |
1719 | if (!priv->prs_shadow[tid].valid) | |
1720 | return tid; | |
1721 | } | |
1722 | ||
1723 | return -EINVAL; | |
1724 | } | |
1725 | ||
1726 | /* Enable/disable dropping all mac da's */ | |
1727 | static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) | |
1728 | { | |
1729 | struct mvpp2_prs_entry pe; | |
1730 | ||
1731 | if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { | |
1732 | /* Entry exist - update port only */ | |
1733 | pe.index = MVPP2_PE_DROP_ALL; | |
1734 | mvpp2_prs_hw_read(priv, &pe); | |
1735 | } else { | |
1736 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1737 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1738 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1739 | pe.index = MVPP2_PE_DROP_ALL; | |
1740 | ||
1741 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
1742 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
1743 | MVPP2_PRS_RI_DROP_MASK); | |
1744 | ||
1745 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
1746 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
1747 | ||
1748 | /* Update shadow table */ | |
1749 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1750 | ||
1751 | /* Mask all ports */ | |
1752 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1753 | } | |
1754 | ||
1755 | /* Update port mask */ | |
1756 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1757 | ||
1758 | mvpp2_prs_hw_write(priv, &pe); | |
1759 | } | |
1760 | ||
1761 | /* Set port to promiscuous mode */ | |
1762 | static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) | |
1763 | { | |
1764 | struct mvpp2_prs_entry pe; | |
1765 | ||
dbedd44e | 1766 | /* Promiscuous mode - Accept unknown packets */ |
3f518509 MW |
1767 | |
1768 | if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) { | |
1769 | /* Entry exist - update port only */ | |
1770 | pe.index = MVPP2_PE_MAC_PROMISCUOUS; | |
1771 | mvpp2_prs_hw_read(priv, &pe); | |
1772 | } else { | |
1773 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1774 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1775 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1776 | pe.index = MVPP2_PE_MAC_PROMISCUOUS; | |
1777 | ||
1778 | /* Continue - set next lookup */ | |
1779 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
1780 | ||
1781 | /* Set result info bits */ | |
1782 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, | |
1783 | MVPP2_PRS_RI_L2_CAST_MASK); | |
1784 | ||
1785 | /* Shift to ethertype */ | |
1786 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
1787 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1788 | ||
1789 | /* Mask all ports */ | |
1790 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1791 | ||
1792 | /* Update shadow table */ | |
1793 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1794 | } | |
1795 | ||
1796 | /* Update port mask */ | |
1797 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1798 | ||
1799 | mvpp2_prs_hw_write(priv, &pe); | |
1800 | } | |
1801 | ||
1802 | /* Accept multicast */ | |
1803 | static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, | |
1804 | bool add) | |
1805 | { | |
1806 | struct mvpp2_prs_entry pe; | |
1807 | unsigned char da_mc; | |
1808 | ||
1809 | /* Ethernet multicast address first byte is | |
1810 | * 0x01 for IPv4 and 0x33 for IPv6 | |
1811 | */ | |
1812 | da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33; | |
1813 | ||
1814 | if (priv->prs_shadow[index].valid) { | |
1815 | /* Entry exist - update port only */ | |
1816 | pe.index = index; | |
1817 | mvpp2_prs_hw_read(priv, &pe); | |
1818 | } else { | |
1819 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1820 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1821 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
1822 | pe.index = index; | |
1823 | ||
1824 | /* Continue - set next lookup */ | |
1825 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
1826 | ||
1827 | /* Set result info bits */ | |
1828 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, | |
1829 | MVPP2_PRS_RI_L2_CAST_MASK); | |
1830 | ||
1831 | /* Update tcam entry data first byte */ | |
1832 | mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); | |
1833 | ||
1834 | /* Shift to ethertype */ | |
1835 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
1836 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1837 | ||
1838 | /* Mask all ports */ | |
1839 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1840 | ||
1841 | /* Update shadow table */ | |
1842 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
1843 | } | |
1844 | ||
1845 | /* Update port mask */ | |
1846 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1847 | ||
1848 | mvpp2_prs_hw_write(priv, &pe); | |
1849 | } | |
1850 | ||
1851 | /* Set entry for dsa packets */ | |
1852 | static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add, | |
1853 | bool tagged, bool extend) | |
1854 | { | |
1855 | struct mvpp2_prs_entry pe; | |
1856 | int tid, shift; | |
1857 | ||
1858 | if (extend) { | |
1859 | tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED; | |
1860 | shift = 8; | |
1861 | } else { | |
1862 | tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED; | |
1863 | shift = 4; | |
1864 | } | |
1865 | ||
1866 | if (priv->prs_shadow[tid].valid) { | |
1867 | /* Entry exist - update port only */ | |
1868 | pe.index = tid; | |
1869 | mvpp2_prs_hw_read(priv, &pe); | |
1870 | } else { | |
1871 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1872 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1873 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
1874 | pe.index = tid; | |
1875 | ||
1876 | /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/ | |
1877 | mvpp2_prs_sram_shift_set(&pe, shift, | |
1878 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1879 | ||
1880 | /* Update shadow table */ | |
1881 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
1882 | ||
1883 | if (tagged) { | |
1884 | /* Set tagged bit in DSA tag */ | |
1885 | mvpp2_prs_tcam_data_byte_set(&pe, 0, | |
1886 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, | |
1887 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
1888 | /* Clear all ai bits for next iteration */ | |
1889 | mvpp2_prs_sram_ai_update(&pe, 0, | |
1890 | MVPP2_PRS_SRAM_AI_MASK); | |
1891 | /* If packet is tagged continue check vlans */ | |
1892 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
1893 | } else { | |
1894 | /* Set result info bits to 'no vlans' */ | |
1895 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
1896 | MVPP2_PRS_RI_VLAN_MASK); | |
1897 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
1898 | } | |
1899 | ||
1900 | /* Mask all ports */ | |
1901 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
1902 | } | |
1903 | ||
1904 | /* Update port mask */ | |
1905 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1906 | ||
1907 | mvpp2_prs_hw_write(priv, &pe); | |
1908 | } | |
1909 | ||
1910 | /* Set entry for dsa ethertype */ | |
1911 | static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port, | |
1912 | bool add, bool tagged, bool extend) | |
1913 | { | |
1914 | struct mvpp2_prs_entry pe; | |
1915 | int tid, shift, port_mask; | |
1916 | ||
1917 | if (extend) { | |
1918 | tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED : | |
1919 | MVPP2_PE_ETYPE_EDSA_UNTAGGED; | |
1920 | port_mask = 0; | |
1921 | shift = 8; | |
1922 | } else { | |
1923 | tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED : | |
1924 | MVPP2_PE_ETYPE_DSA_UNTAGGED; | |
1925 | port_mask = MVPP2_PRS_PORT_MASK; | |
1926 | shift = 4; | |
1927 | } | |
1928 | ||
1929 | if (priv->prs_shadow[tid].valid) { | |
1930 | /* Entry exist - update port only */ | |
1931 | pe.index = tid; | |
1932 | mvpp2_prs_hw_read(priv, &pe); | |
1933 | } else { | |
1934 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 1935 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
1936 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
1937 | pe.index = tid; | |
1938 | ||
1939 | /* Set ethertype */ | |
1940 | mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); | |
1941 | mvpp2_prs_match_etype(&pe, 2, 0); | |
1942 | ||
1943 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, | |
1944 | MVPP2_PRS_RI_DSA_MASK); | |
1945 | /* Shift ethertype + 2 byte reserved + tag*/ | |
1946 | mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, | |
1947 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
1948 | ||
1949 | /* Update shadow table */ | |
1950 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
1951 | ||
1952 | if (tagged) { | |
1953 | /* Set tagged bit in DSA tag */ | |
1954 | mvpp2_prs_tcam_data_byte_set(&pe, | |
1955 | MVPP2_ETH_TYPE_LEN + 2 + 3, | |
1956 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, | |
1957 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
1958 | /* Clear all ai bits for next iteration */ | |
1959 | mvpp2_prs_sram_ai_update(&pe, 0, | |
1960 | MVPP2_PRS_SRAM_AI_MASK); | |
1961 | /* If packet is tagged continue check vlans */ | |
1962 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
1963 | } else { | |
1964 | /* Set result info bits to 'no vlans' */ | |
1965 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
1966 | MVPP2_PRS_RI_VLAN_MASK); | |
1967 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
1968 | } | |
1969 | /* Mask/unmask all ports, depending on dsa type */ | |
1970 | mvpp2_prs_tcam_port_map_set(&pe, port_mask); | |
1971 | } | |
1972 | ||
1973 | /* Update port mask */ | |
1974 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
1975 | ||
1976 | mvpp2_prs_hw_write(priv, &pe); | |
1977 | } | |
1978 | ||
1979 | /* Search for existing single/triple vlan entry */ | |
1980 | static struct mvpp2_prs_entry *mvpp2_prs_vlan_find(struct mvpp2 *priv, | |
1981 | unsigned short tpid, int ai) | |
1982 | { | |
1983 | struct mvpp2_prs_entry *pe; | |
1984 | int tid; | |
1985 | ||
1986 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
1987 | if (!pe) | |
1988 | return NULL; | |
1989 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
1990 | ||
1991 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ | |
1992 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
1993 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
1994 | unsigned int ri_bits, ai_bits; | |
1995 | bool match; | |
1996 | ||
1997 | if (!priv->prs_shadow[tid].valid || | |
1998 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
1999 | continue; | |
2000 | ||
2001 | pe->index = tid; | |
2002 | ||
2003 | mvpp2_prs_hw_read(priv, pe); | |
2004 | match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid)); | |
2005 | if (!match) | |
2006 | continue; | |
2007 | ||
2008 | /* Get vlan type */ | |
2009 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2010 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; | |
2011 | ||
2012 | /* Get current ai value from tcam */ | |
2013 | ai_bits = mvpp2_prs_tcam_ai_get(pe); | |
2014 | /* Clear double vlan bit */ | |
2015 | ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2016 | ||
2017 | if (ai != ai_bits) | |
2018 | continue; | |
2019 | ||
2020 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2021 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2022 | return pe; | |
2023 | } | |
2024 | kfree(pe); | |
2025 | ||
2026 | return NULL; | |
2027 | } | |
2028 | ||
2029 | /* Add/update single/triple vlan entry */ | |
2030 | static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai, | |
2031 | unsigned int port_map) | |
2032 | { | |
2033 | struct mvpp2_prs_entry *pe; | |
2034 | int tid_aux, tid; | |
43737473 | 2035 | int ret = 0; |
3f518509 MW |
2036 | |
2037 | pe = mvpp2_prs_vlan_find(priv, tpid, ai); | |
2038 | ||
2039 | if (!pe) { | |
2040 | /* Create new tcam entry */ | |
2041 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID, | |
2042 | MVPP2_PE_FIRST_FREE_TID); | |
2043 | if (tid < 0) | |
2044 | return tid; | |
2045 | ||
2046 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2047 | if (!pe) | |
2048 | return -ENOMEM; | |
2049 | ||
2050 | /* Get last double vlan tid */ | |
2051 | for (tid_aux = MVPP2_PE_LAST_FREE_TID; | |
2052 | tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) { | |
2053 | unsigned int ri_bits; | |
2054 | ||
2055 | if (!priv->prs_shadow[tid_aux].valid || | |
2056 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2057 | continue; | |
2058 | ||
2059 | pe->index = tid_aux; | |
2060 | mvpp2_prs_hw_read(priv, pe); | |
2061 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2062 | if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) == | |
2063 | MVPP2_PRS_RI_VLAN_DOUBLE) | |
2064 | break; | |
2065 | } | |
2066 | ||
43737473 SM |
2067 | if (tid <= tid_aux) { |
2068 | ret = -EINVAL; | |
f9fd0e34 | 2069 | goto free_pe; |
43737473 | 2070 | } |
3f518509 | 2071 | |
bd6aaf55 | 2072 | memset(pe, 0, sizeof(*pe)); |
3f518509 MW |
2073 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); |
2074 | pe->index = tid; | |
2075 | ||
2076 | mvpp2_prs_match_etype(pe, 0, tpid); | |
2077 | ||
2078 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2); | |
2079 | /* Shift 4 bytes - skip 1 vlan tag */ | |
2080 | mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN, | |
2081 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2082 | /* Clear all ai bits for next iteration */ | |
2083 | mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2084 | ||
2085 | if (ai == MVPP2_PRS_SINGLE_VLAN_AI) { | |
2086 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE, | |
2087 | MVPP2_PRS_RI_VLAN_MASK); | |
2088 | } else { | |
2089 | ai |= MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2090 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE, | |
2091 | MVPP2_PRS_RI_VLAN_MASK); | |
2092 | } | |
2093 | mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK); | |
2094 | ||
2095 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); | |
2096 | } | |
2097 | /* Update ports' mask */ | |
2098 | mvpp2_prs_tcam_port_map_set(pe, port_map); | |
2099 | ||
2100 | mvpp2_prs_hw_write(priv, pe); | |
f9fd0e34 | 2101 | free_pe: |
3f518509 MW |
2102 | kfree(pe); |
2103 | ||
43737473 | 2104 | return ret; |
3f518509 MW |
2105 | } |
2106 | ||
2107 | /* Get first free double vlan ai number */ | |
2108 | static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv) | |
2109 | { | |
2110 | int i; | |
2111 | ||
2112 | for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) { | |
2113 | if (!priv->prs_double_vlans[i]) | |
2114 | return i; | |
2115 | } | |
2116 | ||
2117 | return -EINVAL; | |
2118 | } | |
2119 | ||
2120 | /* Search for existing double vlan entry */ | |
2121 | static struct mvpp2_prs_entry *mvpp2_prs_double_vlan_find(struct mvpp2 *priv, | |
2122 | unsigned short tpid1, | |
2123 | unsigned short tpid2) | |
2124 | { | |
2125 | struct mvpp2_prs_entry *pe; | |
2126 | int tid; | |
2127 | ||
2128 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2129 | if (!pe) | |
2130 | return NULL; | |
2131 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2132 | ||
2133 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ | |
2134 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2135 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2136 | unsigned int ri_mask; | |
2137 | bool match; | |
2138 | ||
2139 | if (!priv->prs_shadow[tid].valid || | |
2140 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2141 | continue; | |
2142 | ||
2143 | pe->index = tid; | |
2144 | mvpp2_prs_hw_read(priv, pe); | |
2145 | ||
2146 | match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1)) | |
2147 | && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2)); | |
2148 | ||
2149 | if (!match) | |
2150 | continue; | |
2151 | ||
2152 | ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK; | |
2153 | if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE) | |
2154 | return pe; | |
2155 | } | |
2156 | kfree(pe); | |
2157 | ||
2158 | return NULL; | |
2159 | } | |
2160 | ||
2161 | /* Add or update double vlan entry */ | |
2162 | static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1, | |
2163 | unsigned short tpid2, | |
2164 | unsigned int port_map) | |
2165 | { | |
2166 | struct mvpp2_prs_entry *pe; | |
43737473 | 2167 | int tid_aux, tid, ai, ret = 0; |
3f518509 MW |
2168 | |
2169 | pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); | |
2170 | ||
2171 | if (!pe) { | |
2172 | /* Create new tcam entry */ | |
2173 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2174 | MVPP2_PE_LAST_FREE_TID); | |
2175 | if (tid < 0) | |
2176 | return tid; | |
2177 | ||
2178 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
2179 | if (!pe) | |
2180 | return -ENOMEM; | |
2181 | ||
2182 | /* Set ai value for new double vlan entry */ | |
2183 | ai = mvpp2_prs_double_vlan_ai_free_get(priv); | |
43737473 SM |
2184 | if (ai < 0) { |
2185 | ret = ai; | |
c9a7e120 | 2186 | goto free_pe; |
43737473 | 2187 | } |
3f518509 MW |
2188 | |
2189 | /* Get first single/triple vlan tid */ | |
2190 | for (tid_aux = MVPP2_PE_FIRST_FREE_TID; | |
2191 | tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) { | |
2192 | unsigned int ri_bits; | |
2193 | ||
2194 | if (!priv->prs_shadow[tid_aux].valid || | |
2195 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2196 | continue; | |
2197 | ||
2198 | pe->index = tid_aux; | |
2199 | mvpp2_prs_hw_read(priv, pe); | |
2200 | ri_bits = mvpp2_prs_sram_ri_get(pe); | |
2201 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; | |
2202 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2203 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2204 | break; | |
2205 | } | |
2206 | ||
43737473 SM |
2207 | if (tid >= tid_aux) { |
2208 | ret = -ERANGE; | |
c9a7e120 | 2209 | goto free_pe; |
43737473 | 2210 | } |
3f518509 | 2211 | |
bd6aaf55 | 2212 | memset(pe, 0, sizeof(*pe)); |
3f518509 MW |
2213 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN); |
2214 | pe->index = tid; | |
2215 | ||
2216 | priv->prs_double_vlans[ai] = true; | |
2217 | ||
2218 | mvpp2_prs_match_etype(pe, 0, tpid1); | |
2219 | mvpp2_prs_match_etype(pe, 4, tpid2); | |
2220 | ||
2221 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN); | |
2222 | /* Shift 8 bytes - skip 2 vlan tags */ | |
2223 | mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN, | |
2224 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2225 | mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
2226 | MVPP2_PRS_RI_VLAN_MASK); | |
2227 | mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, | |
2228 | MVPP2_PRS_SRAM_AI_MASK); | |
2229 | ||
2230 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN); | |
2231 | } | |
2232 | ||
2233 | /* Update ports' mask */ | |
2234 | mvpp2_prs_tcam_port_map_set(pe, port_map); | |
2235 | mvpp2_prs_hw_write(priv, pe); | |
c9a7e120 | 2236 | free_pe: |
3f518509 | 2237 | kfree(pe); |
43737473 | 2238 | return ret; |
3f518509 MW |
2239 | } |
2240 | ||
2241 | /* IPv4 header parsing for fragmentation and L4 offset */ | |
2242 | static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, | |
2243 | unsigned int ri, unsigned int ri_mask) | |
2244 | { | |
2245 | struct mvpp2_prs_entry pe; | |
2246 | int tid; | |
2247 | ||
2248 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2249 | (proto != IPPROTO_IGMP)) | |
2250 | return -EINVAL; | |
2251 | ||
2252 | /* Fragmented packet */ | |
2253 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2254 | MVPP2_PE_LAST_FREE_TID); | |
2255 | if (tid < 0) | |
2256 | return tid; | |
2257 | ||
c5b2ce24 | 2258 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2259 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2260 | pe.index = tid; | |
2261 | ||
2262 | /* Set next lu to IPv4 */ | |
2263 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2264 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2265 | /* Set L4 offset */ | |
2266 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2267 | sizeof(struct iphdr) - 4, | |
2268 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2269 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2270 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2271 | mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK, | |
2272 | ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); | |
2273 | ||
2274 | mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2275 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2276 | /* Unmask all ports */ | |
2277 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2278 | ||
2279 | /* Update shadow table and hw entry */ | |
2280 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2281 | mvpp2_prs_hw_write(priv, &pe); | |
2282 | ||
2283 | /* Not fragmented packet */ | |
2284 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2285 | MVPP2_PE_LAST_FREE_TID); | |
2286 | if (tid < 0) | |
2287 | return tid; | |
2288 | ||
2289 | pe.index = tid; | |
2290 | /* Clear ri before updating */ | |
2291 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2292 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2293 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2294 | ||
2295 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L); | |
2296 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK); | |
2297 | ||
2298 | /* Update shadow table and hw entry */ | |
2299 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2300 | mvpp2_prs_hw_write(priv, &pe); | |
2301 | ||
2302 | return 0; | |
2303 | } | |
2304 | ||
2305 | /* IPv4 L3 multicast or broadcast */ | |
2306 | static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2307 | { | |
2308 | struct mvpp2_prs_entry pe; | |
2309 | int mask, tid; | |
2310 | ||
2311 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2312 | MVPP2_PE_LAST_FREE_TID); | |
2313 | if (tid < 0) | |
2314 | return tid; | |
2315 | ||
c5b2ce24 | 2316 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2317 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2318 | pe.index = tid; | |
2319 | ||
2320 | switch (l3_cast) { | |
2321 | case MVPP2_PRS_L3_MULTI_CAST: | |
2322 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, | |
2323 | MVPP2_PRS_IPV4_MC_MASK); | |
2324 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2325 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2326 | break; | |
2327 | case MVPP2_PRS_L3_BROAD_CAST: | |
2328 | mask = MVPP2_PRS_IPV4_BC_MASK; | |
2329 | mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); | |
2330 | mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); | |
2331 | mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); | |
2332 | mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); | |
2333 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, | |
2334 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2335 | break; | |
2336 | default: | |
2337 | return -EINVAL; | |
2338 | } | |
2339 | ||
2340 | /* Finished: go to flowid generation */ | |
2341 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2342 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2343 | ||
2344 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2345 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2346 | /* Unmask all ports */ | |
2347 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2348 | ||
2349 | /* Update shadow table and hw entry */ | |
2350 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2351 | mvpp2_prs_hw_write(priv, &pe); | |
2352 | ||
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | /* Set entries for protocols over IPv6 */ | |
2357 | static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto, | |
2358 | unsigned int ri, unsigned int ri_mask) | |
2359 | { | |
2360 | struct mvpp2_prs_entry pe; | |
2361 | int tid; | |
2362 | ||
2363 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2364 | (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP)) | |
2365 | return -EINVAL; | |
2366 | ||
2367 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2368 | MVPP2_PE_LAST_FREE_TID); | |
2369 | if (tid < 0) | |
2370 | return tid; | |
2371 | ||
c5b2ce24 | 2372 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2373 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2374 | pe.index = tid; | |
2375 | ||
2376 | /* Finished: go to flowid generation */ | |
2377 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2378 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2379 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2380 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2381 | sizeof(struct ipv6hdr) - 6, | |
2382 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2383 | ||
2384 | mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2385 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2386 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2387 | /* Unmask all ports */ | |
2388 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2389 | ||
2390 | /* Write HW */ | |
2391 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2392 | mvpp2_prs_hw_write(priv, &pe); | |
2393 | ||
2394 | return 0; | |
2395 | } | |
2396 | ||
2397 | /* IPv6 L3 multicast entry */ | |
2398 | static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2399 | { | |
2400 | struct mvpp2_prs_entry pe; | |
2401 | int tid; | |
2402 | ||
2403 | if (l3_cast != MVPP2_PRS_L3_MULTI_CAST) | |
2404 | return -EINVAL; | |
2405 | ||
2406 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2407 | MVPP2_PE_LAST_FREE_TID); | |
2408 | if (tid < 0) | |
2409 | return tid; | |
2410 | ||
c5b2ce24 | 2411 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2412 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2413 | pe.index = tid; | |
2414 | ||
2415 | /* Finished: go to flowid generation */ | |
2416 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2417 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2418 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2419 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2420 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2421 | /* Shift back to IPv6 NH */ | |
2422 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2423 | ||
2424 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, | |
2425 | MVPP2_PRS_IPV6_MC_MASK); | |
2426 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2427 | /* Unmask all ports */ | |
2428 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2429 | ||
2430 | /* Update shadow table and hw entry */ | |
2431 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2432 | mvpp2_prs_hw_write(priv, &pe); | |
2433 | ||
2434 | return 0; | |
2435 | } | |
2436 | ||
2437 | /* Parser per-port initialization */ | |
2438 | static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, | |
2439 | int lu_max, int offset) | |
2440 | { | |
2441 | u32 val; | |
2442 | ||
2443 | /* Set lookup ID */ | |
2444 | val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG); | |
2445 | val &= ~MVPP2_PRS_PORT_LU_MASK(port); | |
2446 | val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); | |
2447 | mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); | |
2448 | ||
2449 | /* Set maximum number of loops for packet received from port */ | |
2450 | val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); | |
2451 | val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); | |
2452 | val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); | |
2453 | mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); | |
2454 | ||
2455 | /* Set initial offset for packet header extraction for the first | |
2456 | * searching loop | |
2457 | */ | |
2458 | val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); | |
2459 | val &= ~MVPP2_PRS_INIT_OFF_MASK(port); | |
2460 | val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); | |
2461 | mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); | |
2462 | } | |
2463 | ||
2464 | /* Default flow entries initialization for all ports */ | |
2465 | static void mvpp2_prs_def_flow_init(struct mvpp2 *priv) | |
2466 | { | |
2467 | struct mvpp2_prs_entry pe; | |
2468 | int port; | |
2469 | ||
2470 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
c5b2ce24 | 2471 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2472 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); |
2473 | pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; | |
2474 | ||
2475 | /* Mask all ports */ | |
2476 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2477 | ||
2478 | /* Set flow ID*/ | |
2479 | mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); | |
2480 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
2481 | ||
2482 | /* Update shadow table and hw entry */ | |
2483 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); | |
2484 | mvpp2_prs_hw_write(priv, &pe); | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | /* Set default entry for Marvell Header field */ | |
2489 | static void mvpp2_prs_mh_init(struct mvpp2 *priv) | |
2490 | { | |
2491 | struct mvpp2_prs_entry pe; | |
2492 | ||
c5b2ce24 | 2493 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2494 | |
2495 | pe.index = MVPP2_PE_MH_DEFAULT; | |
2496 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); | |
2497 | mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, | |
2498 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2499 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2500 | ||
2501 | /* Unmask all ports */ | |
2502 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2503 | ||
2504 | /* Update shadow table and hw entry */ | |
2505 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); | |
2506 | mvpp2_prs_hw_write(priv, &pe); | |
2507 | } | |
2508 | ||
2509 | /* Set default entires (place holder) for promiscuous, non-promiscuous and | |
2510 | * multicast MAC addresses | |
2511 | */ | |
2512 | static void mvpp2_prs_mac_init(struct mvpp2 *priv) | |
2513 | { | |
2514 | struct mvpp2_prs_entry pe; | |
2515 | ||
c5b2ce24 | 2516 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2517 | |
2518 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
2519 | pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; | |
2520 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2521 | ||
2522 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
2523 | MVPP2_PRS_RI_DROP_MASK); | |
2524 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2525 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2526 | ||
2527 | /* Unmask all ports */ | |
2528 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2529 | ||
2530 | /* Update shadow table and hw entry */ | |
2531 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2532 | mvpp2_prs_hw_write(priv, &pe); | |
2533 | ||
2534 | /* place holders only - no ports */ | |
2535 | mvpp2_prs_mac_drop_all_set(priv, 0, false); | |
2536 | mvpp2_prs_mac_promisc_set(priv, 0, false); | |
2537 | mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false); | |
2538 | mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false); | |
2539 | } | |
2540 | ||
2541 | /* Set default entries for various types of dsa packets */ | |
2542 | static void mvpp2_prs_dsa_init(struct mvpp2 *priv) | |
2543 | { | |
2544 | struct mvpp2_prs_entry pe; | |
2545 | ||
2546 | /* None tagged EDSA entry - place holder */ | |
2547 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2548 | MVPP2_PRS_EDSA); | |
2549 | ||
2550 | /* Tagged EDSA entry - place holder */ | |
2551 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2552 | ||
2553 | /* None tagged DSA entry - place holder */ | |
2554 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2555 | MVPP2_PRS_DSA); | |
2556 | ||
2557 | /* Tagged DSA entry - place holder */ | |
2558 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2559 | ||
2560 | /* None tagged EDSA ethertype entry - place holder*/ | |
2561 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2562 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
2563 | ||
2564 | /* Tagged EDSA ethertype entry - place holder*/ | |
2565 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2566 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2567 | ||
2568 | /* None tagged DSA ethertype entry */ | |
2569 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2570 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
2571 | ||
2572 | /* Tagged DSA ethertype entry */ | |
2573 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2574 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2575 | ||
2576 | /* Set default entry, in case DSA or EDSA tag not found */ | |
c5b2ce24 | 2577 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2578 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2579 | pe.index = MVPP2_PE_DSA_DEFAULT; | |
2580 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2581 | ||
2582 | /* Shift 0 bytes */ | |
2583 | mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2584 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2585 | ||
2586 | /* Clear all sram ai bits for next iteration */ | |
2587 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2588 | ||
2589 | /* Unmask all ports */ | |
2590 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2591 | ||
2592 | mvpp2_prs_hw_write(priv, &pe); | |
2593 | } | |
2594 | ||
2595 | /* Match basic ethertypes */ | |
2596 | static int mvpp2_prs_etype_init(struct mvpp2 *priv) | |
2597 | { | |
2598 | struct mvpp2_prs_entry pe; | |
2599 | int tid; | |
2600 | ||
2601 | /* Ethertype: PPPoE */ | |
2602 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2603 | MVPP2_PE_LAST_FREE_TID); | |
2604 | if (tid < 0) | |
2605 | return tid; | |
2606 | ||
c5b2ce24 | 2607 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2608 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2609 | pe.index = tid; | |
2610 | ||
2611 | mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); | |
2612 | ||
2613 | mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, | |
2614 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2615 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); | |
2616 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, | |
2617 | MVPP2_PRS_RI_PPPOE_MASK); | |
2618 | ||
2619 | /* Update shadow table and hw entry */ | |
2620 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2621 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2622 | priv->prs_shadow[pe.index].finish = false; | |
2623 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, | |
2624 | MVPP2_PRS_RI_PPPOE_MASK); | |
2625 | mvpp2_prs_hw_write(priv, &pe); | |
2626 | ||
2627 | /* Ethertype: ARP */ | |
2628 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2629 | MVPP2_PE_LAST_FREE_TID); | |
2630 | if (tid < 0) | |
2631 | return tid; | |
2632 | ||
c5b2ce24 | 2633 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2634 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2635 | pe.index = tid; | |
2636 | ||
2637 | mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); | |
2638 | ||
2639 | /* Generate flow in the next iteration*/ | |
2640 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2641 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2642 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, | |
2643 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2644 | /* Set L3 offset */ | |
2645 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2646 | MVPP2_ETH_TYPE_LEN, | |
2647 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2648 | ||
2649 | /* Update shadow table and hw entry */ | |
2650 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2651 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2652 | priv->prs_shadow[pe.index].finish = true; | |
2653 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, | |
2654 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2655 | mvpp2_prs_hw_write(priv, &pe); | |
2656 | ||
2657 | /* Ethertype: LBTD */ | |
2658 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2659 | MVPP2_PE_LAST_FREE_TID); | |
2660 | if (tid < 0) | |
2661 | return tid; | |
2662 | ||
c5b2ce24 | 2663 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2664 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2665 | pe.index = tid; | |
2666 | ||
2667 | mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); | |
2668 | ||
2669 | /* Generate flow in the next iteration*/ | |
2670 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2671 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2672 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2673 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2674 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2675 | MVPP2_PRS_RI_UDF3_MASK); | |
2676 | /* Set L3 offset */ | |
2677 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2678 | MVPP2_ETH_TYPE_LEN, | |
2679 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2680 | ||
2681 | /* Update shadow table and hw entry */ | |
2682 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2683 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2684 | priv->prs_shadow[pe.index].finish = true; | |
2685 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2686 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2687 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2688 | MVPP2_PRS_RI_UDF3_MASK); | |
2689 | mvpp2_prs_hw_write(priv, &pe); | |
2690 | ||
2691 | /* Ethertype: IPv4 without options */ | |
2692 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2693 | MVPP2_PE_LAST_FREE_TID); | |
2694 | if (tid < 0) | |
2695 | return tid; | |
2696 | ||
c5b2ce24 | 2697 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2698 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2699 | pe.index = tid; | |
2700 | ||
2701 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); | |
2702 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2703 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
2704 | MVPP2_PRS_IPV4_HEAD_MASK | | |
2705 | MVPP2_PRS_IPV4_IHL_MASK); | |
2706 | ||
2707 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2708 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
2709 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2710 | /* Skip eth_type + 4 bytes of IP header */ | |
2711 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2712 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2713 | /* Set L3 offset */ | |
2714 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2715 | MVPP2_ETH_TYPE_LEN, | |
2716 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2717 | ||
2718 | /* Update shadow table and hw entry */ | |
2719 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2720 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2721 | priv->prs_shadow[pe.index].finish = false; | |
2722 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, | |
2723 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2724 | mvpp2_prs_hw_write(priv, &pe); | |
2725 | ||
2726 | /* Ethertype: IPv4 with options */ | |
2727 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2728 | MVPP2_PE_LAST_FREE_TID); | |
2729 | if (tid < 0) | |
2730 | return tid; | |
2731 | ||
2732 | pe.index = tid; | |
2733 | ||
2734 | /* Clear tcam data before updating */ | |
2735 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
2736 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
2737 | ||
2738 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2739 | MVPP2_PRS_IPV4_HEAD, | |
2740 | MVPP2_PRS_IPV4_HEAD_MASK); | |
2741 | ||
2742 | /* Clear ri before updating */ | |
2743 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2744 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2745 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
2746 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2747 | ||
2748 | /* Update shadow table and hw entry */ | |
2749 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2750 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2751 | priv->prs_shadow[pe.index].finish = false; | |
2752 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, | |
2753 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2754 | mvpp2_prs_hw_write(priv, &pe); | |
2755 | ||
2756 | /* Ethertype: IPv6 without options */ | |
2757 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2758 | MVPP2_PE_LAST_FREE_TID); | |
2759 | if (tid < 0) | |
2760 | return tid; | |
2761 | ||
c5b2ce24 | 2762 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2763 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2764 | pe.index = tid; | |
2765 | ||
2766 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); | |
2767 | ||
2768 | /* Skip DIP of IPV6 header */ | |
2769 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + | |
2770 | MVPP2_MAX_L3_ADDR_SIZE, | |
2771 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2772 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2773 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
2774 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2775 | /* Set L3 offset */ | |
2776 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2777 | MVPP2_ETH_TYPE_LEN, | |
2778 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2779 | ||
2780 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2781 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2782 | priv->prs_shadow[pe.index].finish = false; | |
2783 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, | |
2784 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2785 | mvpp2_prs_hw_write(priv, &pe); | |
2786 | ||
2787 | /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ | |
2788 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
2789 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2790 | pe.index = MVPP2_PE_ETH_TYPE_UN; | |
2791 | ||
2792 | /* Unmask all ports */ | |
2793 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2794 | ||
2795 | /* Generate flow in the next iteration*/ | |
2796 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2797 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2798 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
2799 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2800 | /* Set L3 offset even it's unknown L3 */ | |
2801 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2802 | MVPP2_ETH_TYPE_LEN, | |
2803 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2804 | ||
2805 | /* Update shadow table and hw entry */ | |
2806 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2807 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2808 | priv->prs_shadow[pe.index].finish = true; | |
2809 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, | |
2810 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2811 | mvpp2_prs_hw_write(priv, &pe); | |
2812 | ||
2813 | return 0; | |
2814 | } | |
2815 | ||
2816 | /* Configure vlan entries and detect up to 2 successive VLAN tags. | |
2817 | * Possible options: | |
2818 | * 0x8100, 0x88A8 | |
2819 | * 0x8100, 0x8100 | |
2820 | * 0x8100 | |
2821 | * 0x88A8 | |
2822 | */ | |
2823 | static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv) | |
2824 | { | |
2825 | struct mvpp2_prs_entry pe; | |
2826 | int err; | |
2827 | ||
2828 | priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool), | |
2829 | MVPP2_PRS_DBL_VLANS_MAX, | |
2830 | GFP_KERNEL); | |
2831 | if (!priv->prs_double_vlans) | |
2832 | return -ENOMEM; | |
2833 | ||
2834 | /* Double VLAN: 0x8100, 0x88A8 */ | |
2835 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD, | |
2836 | MVPP2_PRS_PORT_MASK); | |
2837 | if (err) | |
2838 | return err; | |
2839 | ||
2840 | /* Double VLAN: 0x8100, 0x8100 */ | |
2841 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q, | |
2842 | MVPP2_PRS_PORT_MASK); | |
2843 | if (err) | |
2844 | return err; | |
2845 | ||
2846 | /* Single VLAN: 0x88a8 */ | |
2847 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI, | |
2848 | MVPP2_PRS_PORT_MASK); | |
2849 | if (err) | |
2850 | return err; | |
2851 | ||
2852 | /* Single VLAN: 0x8100 */ | |
2853 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI, | |
2854 | MVPP2_PRS_PORT_MASK); | |
2855 | if (err) | |
2856 | return err; | |
2857 | ||
2858 | /* Set default double vlan entry */ | |
c5b2ce24 | 2859 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2860 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
2861 | pe.index = MVPP2_PE_VLAN_DBL; | |
2862 | ||
2863 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2864 | /* Clear ai for next iterations */ | |
2865 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2866 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
2867 | MVPP2_PRS_RI_VLAN_MASK); | |
2868 | ||
2869 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, | |
2870 | MVPP2_PRS_DBL_VLAN_AI_BIT); | |
2871 | /* Unmask all ports */ | |
2872 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2873 | ||
2874 | /* Update shadow table and hw entry */ | |
2875 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
2876 | mvpp2_prs_hw_write(priv, &pe); | |
2877 | ||
2878 | /* Set default vlan none entry */ | |
c5b2ce24 | 2879 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2880 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
2881 | pe.index = MVPP2_PE_VLAN_NONE; | |
2882 | ||
2883 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2884 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2885 | MVPP2_PRS_RI_VLAN_MASK); | |
2886 | ||
2887 | /* Unmask all ports */ | |
2888 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2889 | ||
2890 | /* Update shadow table and hw entry */ | |
2891 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
2892 | mvpp2_prs_hw_write(priv, &pe); | |
2893 | ||
2894 | return 0; | |
2895 | } | |
2896 | ||
2897 | /* Set entries for PPPoE ethertype */ | |
2898 | static int mvpp2_prs_pppoe_init(struct mvpp2 *priv) | |
2899 | { | |
2900 | struct mvpp2_prs_entry pe; | |
2901 | int tid; | |
2902 | ||
2903 | /* IPv4 over PPPoE with options */ | |
2904 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2905 | MVPP2_PE_LAST_FREE_TID); | |
2906 | if (tid < 0) | |
2907 | return tid; | |
2908 | ||
c5b2ce24 | 2909 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2910 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
2911 | pe.index = tid; | |
2912 | ||
2913 | mvpp2_prs_match_etype(&pe, 0, PPP_IP); | |
2914 | ||
2915 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2916 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
2917 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2918 | /* Skip eth_type + 4 bytes of IP header */ | |
2919 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2920 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2921 | /* Set L3 offset */ | |
2922 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2923 | MVPP2_ETH_TYPE_LEN, | |
2924 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2925 | ||
2926 | /* Update shadow table and hw entry */ | |
2927 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
2928 | mvpp2_prs_hw_write(priv, &pe); | |
2929 | ||
2930 | /* IPv4 over PPPoE without options */ | |
2931 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2932 | MVPP2_PE_LAST_FREE_TID); | |
2933 | if (tid < 0) | |
2934 | return tid; | |
2935 | ||
2936 | pe.index = tid; | |
2937 | ||
2938 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2939 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
2940 | MVPP2_PRS_IPV4_HEAD_MASK | | |
2941 | MVPP2_PRS_IPV4_IHL_MASK); | |
2942 | ||
2943 | /* Clear ri before updating */ | |
2944 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2945 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2946 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
2947 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2948 | ||
2949 | /* Update shadow table and hw entry */ | |
2950 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
2951 | mvpp2_prs_hw_write(priv, &pe); | |
2952 | ||
2953 | /* IPv6 over PPPoE */ | |
2954 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2955 | MVPP2_PE_LAST_FREE_TID); | |
2956 | if (tid < 0) | |
2957 | return tid; | |
2958 | ||
c5b2ce24 | 2959 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2960 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
2961 | pe.index = tid; | |
2962 | ||
2963 | mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); | |
2964 | ||
2965 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2966 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
2967 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2968 | /* Skip eth_type + 4 bytes of IPv6 header */ | |
2969 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2970 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2971 | /* Set L3 offset */ | |
2972 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2973 | MVPP2_ETH_TYPE_LEN, | |
2974 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2975 | ||
2976 | /* Update shadow table and hw entry */ | |
2977 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
2978 | mvpp2_prs_hw_write(priv, &pe); | |
2979 | ||
2980 | /* Non-IP over PPPoE */ | |
2981 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2982 | MVPP2_PE_LAST_FREE_TID); | |
2983 | if (tid < 0) | |
2984 | return tid; | |
2985 | ||
c5b2ce24 | 2986 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2987 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
2988 | pe.index = tid; | |
2989 | ||
2990 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
2991 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2992 | ||
2993 | /* Finished: go to flowid generation */ | |
2994 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2995 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2996 | /* Set L3 offset even if it's unknown L3 */ | |
2997 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2998 | MVPP2_ETH_TYPE_LEN, | |
2999 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3000 | ||
3001 | /* Update shadow table and hw entry */ | |
3002 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3003 | mvpp2_prs_hw_write(priv, &pe); | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
3008 | /* Initialize entries for IPv4 */ | |
3009 | static int mvpp2_prs_ip4_init(struct mvpp2 *priv) | |
3010 | { | |
3011 | struct mvpp2_prs_entry pe; | |
3012 | int err; | |
3013 | ||
3014 | /* Set entries for TCP, UDP and IGMP over IPv4 */ | |
3015 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP, | |
3016 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3017 | if (err) | |
3018 | return err; | |
3019 | ||
3020 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP, | |
3021 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3022 | if (err) | |
3023 | return err; | |
3024 | ||
3025 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP, | |
3026 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3027 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3028 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3029 | MVPP2_PRS_RI_UDF3_MASK); | |
3030 | if (err) | |
3031 | return err; | |
3032 | ||
3033 | /* IPv4 Broadcast */ | |
3034 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST); | |
3035 | if (err) | |
3036 | return err; | |
3037 | ||
3038 | /* IPv4 Multicast */ | |
3039 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3040 | if (err) | |
3041 | return err; | |
3042 | ||
3043 | /* Default IPv4 entry for unknown protocols */ | |
c5b2ce24 | 3044 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3045 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3046 | pe.index = MVPP2_PE_IP4_PROTO_UN; | |
3047 | ||
3048 | /* Set next lu to IPv4 */ | |
3049 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
3050 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3051 | /* Set L4 offset */ | |
3052 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3053 | sizeof(struct iphdr) - 4, | |
3054 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3055 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3056 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3057 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3058 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3059 | ||
3060 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3061 | /* Unmask all ports */ | |
3062 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3063 | ||
3064 | /* Update shadow table and hw entry */ | |
3065 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3066 | mvpp2_prs_hw_write(priv, &pe); | |
3067 | ||
3068 | /* Default IPv4 entry for unicast address */ | |
c5b2ce24 | 3069 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3070 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3071 | pe.index = MVPP2_PE_IP4_ADDR_UN; | |
3072 | ||
3073 | /* Finished: go to flowid generation */ | |
3074 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3075 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3076 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3077 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3078 | ||
3079 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3080 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3081 | /* Unmask all ports */ | |
3082 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3083 | ||
3084 | /* Update shadow table and hw entry */ | |
3085 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3086 | mvpp2_prs_hw_write(priv, &pe); | |
3087 | ||
3088 | return 0; | |
3089 | } | |
3090 | ||
3091 | /* Initialize entries for IPv6 */ | |
3092 | static int mvpp2_prs_ip6_init(struct mvpp2 *priv) | |
3093 | { | |
3094 | struct mvpp2_prs_entry pe; | |
3095 | int tid, err; | |
3096 | ||
3097 | /* Set entries for TCP, UDP and ICMP over IPv6 */ | |
3098 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP, | |
3099 | MVPP2_PRS_RI_L4_TCP, | |
3100 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3101 | if (err) | |
3102 | return err; | |
3103 | ||
3104 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP, | |
3105 | MVPP2_PRS_RI_L4_UDP, | |
3106 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3107 | if (err) | |
3108 | return err; | |
3109 | ||
3110 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6, | |
3111 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3112 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3113 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3114 | MVPP2_PRS_RI_UDF3_MASK); | |
3115 | if (err) | |
3116 | return err; | |
3117 | ||
3118 | /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */ | |
3119 | /* Result Info: UDF7=1, DS lite */ | |
3120 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP, | |
3121 | MVPP2_PRS_RI_UDF7_IP6_LITE, | |
3122 | MVPP2_PRS_RI_UDF7_MASK); | |
3123 | if (err) | |
3124 | return err; | |
3125 | ||
3126 | /* IPv6 multicast */ | |
3127 | err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3128 | if (err) | |
3129 | return err; | |
3130 | ||
3131 | /* Entry for checking hop limit */ | |
3132 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3133 | MVPP2_PE_LAST_FREE_TID); | |
3134 | if (tid < 0) | |
3135 | return tid; | |
3136 | ||
c5b2ce24 | 3137 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3138 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3139 | pe.index = tid; | |
3140 | ||
3141 | /* Finished: go to flowid generation */ | |
3142 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3143 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3144 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | | |
3145 | MVPP2_PRS_RI_DROP_MASK, | |
3146 | MVPP2_PRS_RI_L3_PROTO_MASK | | |
3147 | MVPP2_PRS_RI_DROP_MASK); | |
3148 | ||
3149 | mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); | |
3150 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3151 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3152 | ||
3153 | /* Update shadow table and hw entry */ | |
3154 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3155 | mvpp2_prs_hw_write(priv, &pe); | |
3156 | ||
3157 | /* Default IPv6 entry for unknown protocols */ | |
c5b2ce24 | 3158 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3159 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3160 | pe.index = MVPP2_PE_IP6_PROTO_UN; | |
3161 | ||
3162 | /* Finished: go to flowid generation */ | |
3163 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3164 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3165 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3166 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3167 | /* Set L4 offset relatively to our current place */ | |
3168 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3169 | sizeof(struct ipv6hdr) - 4, | |
3170 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3171 | ||
3172 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3173 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3174 | /* Unmask all ports */ | |
3175 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3176 | ||
3177 | /* Update shadow table and hw entry */ | |
3178 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3179 | mvpp2_prs_hw_write(priv, &pe); | |
3180 | ||
3181 | /* Default IPv6 entry for unknown ext protocols */ | |
3182 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3183 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3184 | pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; | |
3185 | ||
3186 | /* Finished: go to flowid generation */ | |
3187 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3188 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3189 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3190 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3191 | ||
3192 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, | |
3193 | MVPP2_PRS_IPV6_EXT_AI_BIT); | |
3194 | /* Unmask all ports */ | |
3195 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3196 | ||
3197 | /* Update shadow table and hw entry */ | |
3198 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3199 | mvpp2_prs_hw_write(priv, &pe); | |
3200 | ||
3201 | /* Default IPv6 entry for unicast address */ | |
3202 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3203 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3204 | pe.index = MVPP2_PE_IP6_ADDR_UN; | |
3205 | ||
3206 | /* Finished: go to IPv6 again */ | |
3207 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3208 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3209 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3210 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3211 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3212 | /* Shift back to IPV6 NH */ | |
3213 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3214 | ||
3215 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3216 | /* Unmask all ports */ | |
3217 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3218 | ||
3219 | /* Update shadow table and hw entry */ | |
3220 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
3221 | mvpp2_prs_hw_write(priv, &pe); | |
3222 | ||
3223 | return 0; | |
3224 | } | |
3225 | ||
3226 | /* Parser default initialization */ | |
3227 | static int mvpp2_prs_default_init(struct platform_device *pdev, | |
3228 | struct mvpp2 *priv) | |
3229 | { | |
3230 | int err, index, i; | |
3231 | ||
3232 | /* Enable tcam table */ | |
3233 | mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK); | |
3234 | ||
3235 | /* Clear all tcam and sram entries */ | |
3236 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) { | |
3237 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
3238 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
3239 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0); | |
3240 | ||
3241 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); | |
3242 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
3243 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); | |
3244 | } | |
3245 | ||
3246 | /* Invalidate all tcam entries */ | |
3247 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) | |
3248 | mvpp2_prs_hw_inv(priv, index); | |
3249 | ||
3250 | priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE, | |
37df25e8 | 3251 | sizeof(*priv->prs_shadow), |
3f518509 MW |
3252 | GFP_KERNEL); |
3253 | if (!priv->prs_shadow) | |
3254 | return -ENOMEM; | |
3255 | ||
3256 | /* Always start from lookup = 0 */ | |
3257 | for (index = 0; index < MVPP2_MAX_PORTS; index++) | |
3258 | mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH, | |
3259 | MVPP2_PRS_PORT_LU_MAX, 0); | |
3260 | ||
3261 | mvpp2_prs_def_flow_init(priv); | |
3262 | ||
3263 | mvpp2_prs_mh_init(priv); | |
3264 | ||
3265 | mvpp2_prs_mac_init(priv); | |
3266 | ||
3267 | mvpp2_prs_dsa_init(priv); | |
3268 | ||
3269 | err = mvpp2_prs_etype_init(priv); | |
3270 | if (err) | |
3271 | return err; | |
3272 | ||
3273 | err = mvpp2_prs_vlan_init(pdev, priv); | |
3274 | if (err) | |
3275 | return err; | |
3276 | ||
3277 | err = mvpp2_prs_pppoe_init(priv); | |
3278 | if (err) | |
3279 | return err; | |
3280 | ||
3281 | err = mvpp2_prs_ip6_init(priv); | |
3282 | if (err) | |
3283 | return err; | |
3284 | ||
3285 | err = mvpp2_prs_ip4_init(priv); | |
3286 | if (err) | |
3287 | return err; | |
3288 | ||
3289 | return 0; | |
3290 | } | |
3291 | ||
3292 | /* Compare MAC DA with tcam entry data */ | |
3293 | static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, | |
3294 | const u8 *da, unsigned char *mask) | |
3295 | { | |
3296 | unsigned char tcam_byte, tcam_mask; | |
3297 | int index; | |
3298 | ||
3299 | for (index = 0; index < ETH_ALEN; index++) { | |
3300 | mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); | |
3301 | if (tcam_mask != mask[index]) | |
3302 | return false; | |
3303 | ||
3304 | if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) | |
3305 | return false; | |
3306 | } | |
3307 | ||
3308 | return true; | |
3309 | } | |
3310 | ||
3311 | /* Find tcam entry with matched pair <MAC DA, port> */ | |
3312 | static struct mvpp2_prs_entry * | |
3313 | mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da, | |
3314 | unsigned char *mask, int udf_type) | |
3315 | { | |
3316 | struct mvpp2_prs_entry *pe; | |
3317 | int tid; | |
3318 | ||
3319 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
3320 | if (!pe) | |
3321 | return NULL; | |
3322 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); | |
3323 | ||
3324 | /* Go through the all entires with MVPP2_PRS_LU_MAC */ | |
3325 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3326 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
3327 | unsigned int entry_pmap; | |
3328 | ||
3329 | if (!priv->prs_shadow[tid].valid || | |
3330 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3331 | (priv->prs_shadow[tid].udf != udf_type)) | |
3332 | continue; | |
3333 | ||
3334 | pe->index = tid; | |
3335 | mvpp2_prs_hw_read(priv, pe); | |
3336 | entry_pmap = mvpp2_prs_tcam_port_map_get(pe); | |
3337 | ||
3338 | if (mvpp2_prs_mac_range_equals(pe, da, mask) && | |
3339 | entry_pmap == pmap) | |
3340 | return pe; | |
3341 | } | |
3342 | kfree(pe); | |
3343 | ||
3344 | return NULL; | |
3345 | } | |
3346 | ||
3347 | /* Update parser's mac da entry */ | |
3348 | static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, | |
3349 | const u8 *da, bool add) | |
3350 | { | |
3351 | struct mvpp2_prs_entry *pe; | |
3352 | unsigned int pmap, len, ri; | |
3353 | unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
3354 | int tid; | |
3355 | ||
3356 | /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ | |
3357 | pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, | |
3358 | MVPP2_PRS_UDF_MAC_DEF); | |
3359 | ||
3360 | /* No such entry */ | |
3361 | if (!pe) { | |
3362 | if (!add) | |
3363 | return 0; | |
3364 | ||
3365 | /* Create new TCAM entry */ | |
3366 | /* Find first range mac entry*/ | |
3367 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3368 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) | |
3369 | if (priv->prs_shadow[tid].valid && | |
3370 | (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) && | |
3371 | (priv->prs_shadow[tid].udf == | |
3372 | MVPP2_PRS_UDF_MAC_RANGE)) | |
3373 | break; | |
3374 | ||
3375 | /* Go through the all entries from first to last */ | |
3376 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3377 | tid - 1); | |
3378 | if (tid < 0) | |
3379 | return tid; | |
3380 | ||
3381 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
3382 | if (!pe) | |
c2bb7bc5 | 3383 | return -ENOMEM; |
3f518509 MW |
3384 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); |
3385 | pe->index = tid; | |
3386 | ||
3387 | /* Mask all ports */ | |
3388 | mvpp2_prs_tcam_port_map_set(pe, 0); | |
3389 | } | |
3390 | ||
3391 | /* Update port mask */ | |
3392 | mvpp2_prs_tcam_port_set(pe, port, add); | |
3393 | ||
3394 | /* Invalidate the entry if no ports are left enabled */ | |
3395 | pmap = mvpp2_prs_tcam_port_map_get(pe); | |
3396 | if (pmap == 0) { | |
3397 | if (add) { | |
3398 | kfree(pe); | |
c2bb7bc5 | 3399 | return -EINVAL; |
3f518509 MW |
3400 | } |
3401 | mvpp2_prs_hw_inv(priv, pe->index); | |
3402 | priv->prs_shadow[pe->index].valid = false; | |
3403 | kfree(pe); | |
3404 | return 0; | |
3405 | } | |
3406 | ||
3407 | /* Continue - set next lookup */ | |
3408 | mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); | |
3409 | ||
3410 | /* Set match on DA */ | |
3411 | len = ETH_ALEN; | |
3412 | while (len--) | |
3413 | mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); | |
3414 | ||
3415 | /* Set result info bits */ | |
3416 | if (is_broadcast_ether_addr(da)) | |
3417 | ri = MVPP2_PRS_RI_L2_BCAST; | |
3418 | else if (is_multicast_ether_addr(da)) | |
3419 | ri = MVPP2_PRS_RI_L2_MCAST; | |
3420 | else | |
3421 | ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK; | |
3422 | ||
3423 | mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | | |
3424 | MVPP2_PRS_RI_MAC_ME_MASK); | |
3425 | mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | | |
3426 | MVPP2_PRS_RI_MAC_ME_MASK); | |
3427 | ||
3428 | /* Shift to ethertype */ | |
3429 | mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, | |
3430 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3431 | ||
3432 | /* Update shadow table and hw entry */ | |
3433 | priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; | |
3434 | mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); | |
3435 | mvpp2_prs_hw_write(priv, pe); | |
3436 | ||
3437 | kfree(pe); | |
3438 | ||
3439 | return 0; | |
3440 | } | |
3441 | ||
3442 | static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da) | |
3443 | { | |
3444 | struct mvpp2_port *port = netdev_priv(dev); | |
3445 | int err; | |
3446 | ||
3447 | /* Remove old parser entry */ | |
3448 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr, | |
3449 | false); | |
3450 | if (err) | |
3451 | return err; | |
3452 | ||
3453 | /* Add new parser entry */ | |
3454 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); | |
3455 | if (err) | |
3456 | return err; | |
3457 | ||
3458 | /* Set addr in the device */ | |
3459 | ether_addr_copy(dev->dev_addr, da); | |
3460 | ||
3461 | return 0; | |
3462 | } | |
3463 | ||
3464 | /* Delete all port's multicast simple (not range) entries */ | |
3465 | static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port) | |
3466 | { | |
3467 | struct mvpp2_prs_entry pe; | |
3468 | int index, tid; | |
3469 | ||
3470 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
3471 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
3472 | unsigned char da[ETH_ALEN], da_mask[ETH_ALEN]; | |
3473 | ||
3474 | if (!priv->prs_shadow[tid].valid || | |
3475 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3476 | (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF)) | |
3477 | continue; | |
3478 | ||
3479 | /* Only simple mac entries */ | |
3480 | pe.index = tid; | |
3481 | mvpp2_prs_hw_read(priv, &pe); | |
3482 | ||
3483 | /* Read mac addr from entry */ | |
3484 | for (index = 0; index < ETH_ALEN; index++) | |
3485 | mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], | |
3486 | &da_mask[index]); | |
3487 | ||
3488 | if (is_multicast_ether_addr(da) && !is_broadcast_ether_addr(da)) | |
3489 | /* Delete this entry */ | |
3490 | mvpp2_prs_mac_da_accept(priv, port, da, false); | |
3491 | } | |
3492 | } | |
3493 | ||
3494 | static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type) | |
3495 | { | |
3496 | switch (type) { | |
3497 | case MVPP2_TAG_TYPE_EDSA: | |
3498 | /* Add port to EDSA entries */ | |
3499 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3500 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3501 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3502 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3503 | /* Remove port from DSA entries */ | |
3504 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3505 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3506 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3507 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3508 | break; | |
3509 | ||
3510 | case MVPP2_TAG_TYPE_DSA: | |
3511 | /* Add port to DSA entries */ | |
3512 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3513 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3514 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3515 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3516 | /* Remove port from EDSA entries */ | |
3517 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3518 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3519 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3520 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3521 | break; | |
3522 | ||
3523 | case MVPP2_TAG_TYPE_MH: | |
3524 | case MVPP2_TAG_TYPE_NONE: | |
3525 | /* Remove port form EDSA and DSA entries */ | |
3526 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3527 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3528 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3529 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3530 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3531 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3532 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3533 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3534 | break; | |
3535 | ||
3536 | default: | |
3537 | if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA)) | |
3538 | return -EINVAL; | |
3539 | } | |
3540 | ||
3541 | return 0; | |
3542 | } | |
3543 | ||
3544 | /* Set prs flow for the port */ | |
3545 | static int mvpp2_prs_def_flow(struct mvpp2_port *port) | |
3546 | { | |
3547 | struct mvpp2_prs_entry *pe; | |
3548 | int tid; | |
3549 | ||
3550 | pe = mvpp2_prs_flow_find(port->priv, port->id); | |
3551 | ||
3552 | /* Such entry not exist */ | |
3553 | if (!pe) { | |
3554 | /* Go through the all entires from last to first */ | |
3555 | tid = mvpp2_prs_tcam_first_free(port->priv, | |
3556 | MVPP2_PE_LAST_FREE_TID, | |
3557 | MVPP2_PE_FIRST_FREE_TID); | |
3558 | if (tid < 0) | |
3559 | return tid; | |
3560 | ||
3561 | pe = kzalloc(sizeof(*pe), GFP_KERNEL); | |
3562 | if (!pe) | |
3563 | return -ENOMEM; | |
3564 | ||
3565 | mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); | |
3566 | pe->index = tid; | |
3567 | ||
3568 | /* Set flow ID*/ | |
3569 | mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); | |
3570 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
3571 | ||
3572 | /* Update shadow table */ | |
3573 | mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); | |
3574 | } | |
3575 | ||
3576 | mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); | |
3577 | mvpp2_prs_hw_write(port->priv, pe); | |
3578 | kfree(pe); | |
3579 | ||
3580 | return 0; | |
3581 | } | |
3582 | ||
3583 | /* Classifier configuration routines */ | |
3584 | ||
3585 | /* Update classification flow table registers */ | |
3586 | static void mvpp2_cls_flow_write(struct mvpp2 *priv, | |
3587 | struct mvpp2_cls_flow_entry *fe) | |
3588 | { | |
3589 | mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); | |
3590 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); | |
3591 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); | |
3592 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); | |
3593 | } | |
3594 | ||
3595 | /* Update classification lookup table register */ | |
3596 | static void mvpp2_cls_lookup_write(struct mvpp2 *priv, | |
3597 | struct mvpp2_cls_lookup_entry *le) | |
3598 | { | |
3599 | u32 val; | |
3600 | ||
3601 | val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; | |
3602 | mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); | |
3603 | mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); | |
3604 | } | |
3605 | ||
3606 | /* Classifier default initialization */ | |
3607 | static void mvpp2_cls_init(struct mvpp2 *priv) | |
3608 | { | |
3609 | struct mvpp2_cls_lookup_entry le; | |
3610 | struct mvpp2_cls_flow_entry fe; | |
3611 | int index; | |
3612 | ||
3613 | /* Enable classifier */ | |
3614 | mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); | |
3615 | ||
3616 | /* Clear classifier flow table */ | |
e8f967c3 | 3617 | memset(&fe.data, 0, sizeof(fe.data)); |
3f518509 MW |
3618 | for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { |
3619 | fe.index = index; | |
3620 | mvpp2_cls_flow_write(priv, &fe); | |
3621 | } | |
3622 | ||
3623 | /* Clear classifier lookup table */ | |
3624 | le.data = 0; | |
3625 | for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) { | |
3626 | le.lkpid = index; | |
3627 | le.way = 0; | |
3628 | mvpp2_cls_lookup_write(priv, &le); | |
3629 | ||
3630 | le.way = 1; | |
3631 | mvpp2_cls_lookup_write(priv, &le); | |
3632 | } | |
3633 | } | |
3634 | ||
3635 | static void mvpp2_cls_port_config(struct mvpp2_port *port) | |
3636 | { | |
3637 | struct mvpp2_cls_lookup_entry le; | |
3638 | u32 val; | |
3639 | ||
3640 | /* Set way for the port */ | |
3641 | val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); | |
3642 | val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); | |
3643 | mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); | |
3644 | ||
3645 | /* Pick the entry to be accessed in lookup ID decoding table | |
3646 | * according to the way and lkpid. | |
3647 | */ | |
3648 | le.lkpid = port->id; | |
3649 | le.way = 0; | |
3650 | le.data = 0; | |
3651 | ||
3652 | /* Set initial CPU queue for receiving packets */ | |
3653 | le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK; | |
3654 | le.data |= port->first_rxq; | |
3655 | ||
3656 | /* Disable classification engines */ | |
3657 | le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; | |
3658 | ||
3659 | /* Update lookup ID table entry */ | |
3660 | mvpp2_cls_lookup_write(port->priv, &le); | |
3661 | } | |
3662 | ||
3663 | /* Set CPU queue number for oversize packets */ | |
3664 | static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) | |
3665 | { | |
3666 | u32 val; | |
3667 | ||
3668 | mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), | |
3669 | port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); | |
3670 | ||
3671 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), | |
3672 | (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); | |
3673 | ||
3674 | val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); | |
3675 | val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); | |
3676 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); | |
3677 | } | |
3678 | ||
0e037281 TP |
3679 | static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) |
3680 | { | |
3681 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
3682 | return netdev_alloc_frag(pool->frag_size); | |
3683 | else | |
3684 | return kmalloc(pool->frag_size, GFP_ATOMIC); | |
3685 | } | |
3686 | ||
3687 | static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) | |
3688 | { | |
3689 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
3690 | skb_free_frag(data); | |
3691 | else | |
3692 | kfree(data); | |
3693 | } | |
3694 | ||
3f518509 MW |
3695 | /* Buffer Manager configuration routines */ |
3696 | ||
3697 | /* Create pool */ | |
3698 | static int mvpp2_bm_pool_create(struct platform_device *pdev, | |
3699 | struct mvpp2 *priv, | |
3700 | struct mvpp2_bm_pool *bm_pool, int size) | |
3701 | { | |
3f518509 MW |
3702 | u32 val; |
3703 | ||
d01524d8 TP |
3704 | /* Number of buffer pointers must be a multiple of 16, as per |
3705 | * hardware constraints | |
3706 | */ | |
3707 | if (!IS_ALIGNED(size, 16)) | |
3708 | return -EINVAL; | |
3709 | ||
3710 | /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 | |
3711 | * bytes per buffer pointer | |
3712 | */ | |
3713 | if (priv->hw_version == MVPP21) | |
3714 | bm_pool->size_bytes = 2 * sizeof(u32) * size; | |
3715 | else | |
3716 | bm_pool->size_bytes = 2 * sizeof(u64) * size; | |
3717 | ||
3718 | bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, | |
20396136 | 3719 | &bm_pool->dma_addr, |
3f518509 MW |
3720 | GFP_KERNEL); |
3721 | if (!bm_pool->virt_addr) | |
3722 | return -ENOMEM; | |
3723 | ||
d3158807 TP |
3724 | if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, |
3725 | MVPP2_BM_POOL_PTR_ALIGN)) { | |
d01524d8 TP |
3726 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
3727 | bm_pool->virt_addr, bm_pool->dma_addr); | |
3f518509 MW |
3728 | dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", |
3729 | bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); | |
3730 | return -ENOMEM; | |
3731 | } | |
3732 | ||
3733 | mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), | |
d01524d8 | 3734 | lower_32_bits(bm_pool->dma_addr)); |
3f518509 MW |
3735 | mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); |
3736 | ||
3737 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
3738 | val |= MVPP2_BM_START_MASK; | |
3739 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
3740 | ||
3741 | bm_pool->type = MVPP2_BM_FREE; | |
3742 | bm_pool->size = size; | |
3743 | bm_pool->pkt_size = 0; | |
3744 | bm_pool->buf_num = 0; | |
3f518509 MW |
3745 | |
3746 | return 0; | |
3747 | } | |
3748 | ||
3749 | /* Set pool buffer size */ | |
3750 | static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, | |
3751 | struct mvpp2_bm_pool *bm_pool, | |
3752 | int buf_size) | |
3753 | { | |
3754 | u32 val; | |
3755 | ||
3756 | bm_pool->buf_size = buf_size; | |
3757 | ||
3758 | val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); | |
3759 | mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); | |
3760 | } | |
3761 | ||
d01524d8 TP |
3762 | static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, |
3763 | struct mvpp2_bm_pool *bm_pool, | |
3764 | dma_addr_t *dma_addr, | |
3765 | phys_addr_t *phys_addr) | |
3766 | { | |
a704bb5c | 3767 | int cpu = get_cpu(); |
a786841d TP |
3768 | |
3769 | *dma_addr = mvpp2_percpu_read(priv, cpu, | |
3770 | MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); | |
3771 | *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG); | |
d01524d8 TP |
3772 | |
3773 | if (priv->hw_version == MVPP22) { | |
3774 | u32 val; | |
3775 | u32 dma_addr_highbits, phys_addr_highbits; | |
3776 | ||
a786841d | 3777 | val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC); |
d01524d8 TP |
3778 | dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); |
3779 | phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> | |
3780 | MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; | |
3781 | ||
3782 | if (sizeof(dma_addr_t) == 8) | |
3783 | *dma_addr |= (u64)dma_addr_highbits << 32; | |
3784 | ||
3785 | if (sizeof(phys_addr_t) == 8) | |
3786 | *phys_addr |= (u64)phys_addr_highbits << 32; | |
3787 | } | |
a704bb5c TP |
3788 | |
3789 | put_cpu(); | |
d01524d8 TP |
3790 | } |
3791 | ||
7861f12b | 3792 | /* Free all buffers from the pool */ |
4229d502 MW |
3793 | static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, |
3794 | struct mvpp2_bm_pool *bm_pool) | |
3f518509 MW |
3795 | { |
3796 | int i; | |
3797 | ||
7861f12b | 3798 | for (i = 0; i < bm_pool->buf_num; i++) { |
20396136 | 3799 | dma_addr_t buf_dma_addr; |
4e4a105f TP |
3800 | phys_addr_t buf_phys_addr; |
3801 | void *data; | |
3f518509 | 3802 | |
d01524d8 TP |
3803 | mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, |
3804 | &buf_dma_addr, &buf_phys_addr); | |
4229d502 | 3805 | |
20396136 | 3806 | dma_unmap_single(dev, buf_dma_addr, |
4229d502 MW |
3807 | bm_pool->buf_size, DMA_FROM_DEVICE); |
3808 | ||
4e4a105f TP |
3809 | data = (void *)phys_to_virt(buf_phys_addr); |
3810 | if (!data) | |
3f518509 | 3811 | break; |
0e037281 | 3812 | |
4e4a105f | 3813 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
3814 | } |
3815 | ||
3816 | /* Update BM driver with number of buffers removed from pool */ | |
3817 | bm_pool->buf_num -= i; | |
3f518509 MW |
3818 | } |
3819 | ||
3820 | /* Cleanup pool */ | |
3821 | static int mvpp2_bm_pool_destroy(struct platform_device *pdev, | |
3822 | struct mvpp2 *priv, | |
3823 | struct mvpp2_bm_pool *bm_pool) | |
3824 | { | |
3f518509 MW |
3825 | u32 val; |
3826 | ||
4229d502 | 3827 | mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool); |
d74c96c1 | 3828 | if (bm_pool->buf_num) { |
3f518509 MW |
3829 | WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id); |
3830 | return 0; | |
3831 | } | |
3832 | ||
3833 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
3834 | val |= MVPP2_BM_STOP_MASK; | |
3835 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
3836 | ||
d01524d8 | 3837 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
3f518509 | 3838 | bm_pool->virt_addr, |
20396136 | 3839 | bm_pool->dma_addr); |
3f518509 MW |
3840 | return 0; |
3841 | } | |
3842 | ||
3843 | static int mvpp2_bm_pools_init(struct platform_device *pdev, | |
3844 | struct mvpp2 *priv) | |
3845 | { | |
3846 | int i, err, size; | |
3847 | struct mvpp2_bm_pool *bm_pool; | |
3848 | ||
3849 | /* Create all pools with maximum size */ | |
3850 | size = MVPP2_BM_POOL_SIZE_MAX; | |
3851 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
3852 | bm_pool = &priv->bm_pools[i]; | |
3853 | bm_pool->id = i; | |
3854 | err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); | |
3855 | if (err) | |
3856 | goto err_unroll_pools; | |
3857 | mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); | |
3858 | } | |
3859 | return 0; | |
3860 | ||
3861 | err_unroll_pools: | |
3862 | dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); | |
3863 | for (i = i - 1; i >= 0; i--) | |
3864 | mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); | |
3865 | return err; | |
3866 | } | |
3867 | ||
3868 | static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) | |
3869 | { | |
3870 | int i, err; | |
3871 | ||
3872 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
3873 | /* Mask BM all interrupts */ | |
3874 | mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); | |
3875 | /* Clear BM cause register */ | |
3876 | mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); | |
3877 | } | |
3878 | ||
3879 | /* Allocate and initialize BM pools */ | |
3880 | priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, | |
81f915eb | 3881 | sizeof(*priv->bm_pools), GFP_KERNEL); |
3f518509 MW |
3882 | if (!priv->bm_pools) |
3883 | return -ENOMEM; | |
3884 | ||
3885 | err = mvpp2_bm_pools_init(pdev, priv); | |
3886 | if (err < 0) | |
3887 | return err; | |
3888 | return 0; | |
3889 | } | |
3890 | ||
3891 | /* Attach long pool to rxq */ | |
3892 | static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, | |
3893 | int lrxq, int long_pool) | |
3894 | { | |
5eac892a | 3895 | u32 val, mask; |
3f518509 MW |
3896 | int prxq; |
3897 | ||
3898 | /* Get queue physical ID */ | |
3899 | prxq = port->rxqs[lrxq]->id; | |
3900 | ||
5eac892a TP |
3901 | if (port->priv->hw_version == MVPP21) |
3902 | mask = MVPP21_RXQ_POOL_LONG_MASK; | |
3903 | else | |
3904 | mask = MVPP22_RXQ_POOL_LONG_MASK; | |
3f518509 | 3905 | |
5eac892a TP |
3906 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
3907 | val &= ~mask; | |
3908 | val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; | |
3f518509 MW |
3909 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
3910 | } | |
3911 | ||
3912 | /* Attach short pool to rxq */ | |
3913 | static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, | |
3914 | int lrxq, int short_pool) | |
3915 | { | |
5eac892a | 3916 | u32 val, mask; |
3f518509 MW |
3917 | int prxq; |
3918 | ||
3919 | /* Get queue physical ID */ | |
3920 | prxq = port->rxqs[lrxq]->id; | |
3921 | ||
5eac892a TP |
3922 | if (port->priv->hw_version == MVPP21) |
3923 | mask = MVPP21_RXQ_POOL_SHORT_MASK; | |
3924 | else | |
3925 | mask = MVPP22_RXQ_POOL_SHORT_MASK; | |
3f518509 | 3926 | |
5eac892a TP |
3927 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
3928 | val &= ~mask; | |
3929 | val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; | |
3f518509 MW |
3930 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
3931 | } | |
3932 | ||
0e037281 TP |
3933 | static void *mvpp2_buf_alloc(struct mvpp2_port *port, |
3934 | struct mvpp2_bm_pool *bm_pool, | |
20396136 | 3935 | dma_addr_t *buf_dma_addr, |
4e4a105f | 3936 | phys_addr_t *buf_phys_addr, |
0e037281 | 3937 | gfp_t gfp_mask) |
3f518509 | 3938 | { |
20396136 | 3939 | dma_addr_t dma_addr; |
0e037281 | 3940 | void *data; |
3f518509 | 3941 | |
0e037281 TP |
3942 | data = mvpp2_frag_alloc(bm_pool); |
3943 | if (!data) | |
3f518509 MW |
3944 | return NULL; |
3945 | ||
20396136 TP |
3946 | dma_addr = dma_map_single(port->dev->dev.parent, data, |
3947 | MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), | |
3948 | DMA_FROM_DEVICE); | |
3949 | if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { | |
0e037281 | 3950 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
3951 | return NULL; |
3952 | } | |
20396136 | 3953 | *buf_dma_addr = dma_addr; |
4e4a105f | 3954 | *buf_phys_addr = virt_to_phys(data); |
3f518509 | 3955 | |
0e037281 | 3956 | return data; |
3f518509 MW |
3957 | } |
3958 | ||
3f518509 MW |
3959 | /* Release buffer to BM */ |
3960 | static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, | |
20396136 | 3961 | dma_addr_t buf_dma_addr, |
4e4a105f | 3962 | phys_addr_t buf_phys_addr) |
3f518509 | 3963 | { |
a704bb5c | 3964 | int cpu = get_cpu(); |
a786841d | 3965 | |
d01524d8 TP |
3966 | if (port->priv->hw_version == MVPP22) { |
3967 | u32 val = 0; | |
3968 | ||
3969 | if (sizeof(dma_addr_t) == 8) | |
3970 | val |= upper_32_bits(buf_dma_addr) & | |
3971 | MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; | |
3972 | ||
3973 | if (sizeof(phys_addr_t) == 8) | |
3974 | val |= (upper_32_bits(buf_phys_addr) | |
3975 | << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & | |
3976 | MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; | |
3977 | ||
a786841d TP |
3978 | mvpp2_percpu_write(port->priv, cpu, |
3979 | MVPP22_BM_ADDR_HIGH_RLS_REG, val); | |
d01524d8 TP |
3980 | } |
3981 | ||
4e4a105f TP |
3982 | /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply |
3983 | * returned in the "cookie" field of the RX | |
3984 | * descriptor. Instead of storing the virtual address, we | |
3985 | * store the physical address | |
3986 | */ | |
a786841d TP |
3987 | mvpp2_percpu_write(port->priv, cpu, |
3988 | MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); | |
3989 | mvpp2_percpu_write(port->priv, cpu, | |
3990 | MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); | |
a704bb5c TP |
3991 | |
3992 | put_cpu(); | |
3f518509 MW |
3993 | } |
3994 | ||
3f518509 MW |
3995 | /* Allocate buffers for the pool */ |
3996 | static int mvpp2_bm_bufs_add(struct mvpp2_port *port, | |
3997 | struct mvpp2_bm_pool *bm_pool, int buf_num) | |
3998 | { | |
3f518509 | 3999 | int i, buf_size, total_size; |
20396136 | 4000 | dma_addr_t dma_addr; |
4e4a105f | 4001 | phys_addr_t phys_addr; |
0e037281 | 4002 | void *buf; |
3f518509 MW |
4003 | |
4004 | buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); | |
4005 | total_size = MVPP2_RX_TOTAL_SIZE(buf_size); | |
4006 | ||
4007 | if (buf_num < 0 || | |
4008 | (buf_num + bm_pool->buf_num > bm_pool->size)) { | |
4009 | netdev_err(port->dev, | |
4010 | "cannot allocate %d buffers for pool %d\n", | |
4011 | buf_num, bm_pool->id); | |
4012 | return 0; | |
4013 | } | |
4014 | ||
3f518509 | 4015 | for (i = 0; i < buf_num; i++) { |
4e4a105f TP |
4016 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, |
4017 | &phys_addr, GFP_KERNEL); | |
0e037281 | 4018 | if (!buf) |
3f518509 MW |
4019 | break; |
4020 | ||
20396136 | 4021 | mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, |
4e4a105f | 4022 | phys_addr); |
3f518509 MW |
4023 | } |
4024 | ||
4025 | /* Update BM driver with number of buffers added to pool */ | |
4026 | bm_pool->buf_num += i; | |
3f518509 MW |
4027 | |
4028 | netdev_dbg(port->dev, | |
4029 | "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", | |
4030 | bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long", | |
4031 | bm_pool->id, bm_pool->pkt_size, buf_size, total_size); | |
4032 | ||
4033 | netdev_dbg(port->dev, | |
4034 | "%s pool %d: %d of %d buffers added\n", | |
4035 | bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long", | |
4036 | bm_pool->id, i, buf_num); | |
4037 | return i; | |
4038 | } | |
4039 | ||
4040 | /* Notify the driver that BM pool is being used as specific type and return the | |
4041 | * pool pointer on success | |
4042 | */ | |
4043 | static struct mvpp2_bm_pool * | |
4044 | mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, | |
4045 | int pkt_size) | |
4046 | { | |
3f518509 MW |
4047 | struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; |
4048 | int num; | |
4049 | ||
4050 | if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) { | |
4051 | netdev_err(port->dev, "mixing pool types is forbidden\n"); | |
4052 | return NULL; | |
4053 | } | |
4054 | ||
3f518509 MW |
4055 | if (new_pool->type == MVPP2_BM_FREE) |
4056 | new_pool->type = type; | |
4057 | ||
4058 | /* Allocate buffers in case BM pool is used as long pool, but packet | |
4059 | * size doesn't match MTU or BM pool hasn't being used yet | |
4060 | */ | |
4061 | if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) || | |
4062 | (new_pool->pkt_size == 0)) { | |
4063 | int pkts_num; | |
4064 | ||
4065 | /* Set default buffer number or free all the buffers in case | |
4066 | * the pool is not empty | |
4067 | */ | |
4068 | pkts_num = new_pool->buf_num; | |
4069 | if (pkts_num == 0) | |
4070 | pkts_num = type == MVPP2_BM_SWF_LONG ? | |
4071 | MVPP2_BM_LONG_BUF_NUM : | |
4072 | MVPP2_BM_SHORT_BUF_NUM; | |
4073 | else | |
4229d502 MW |
4074 | mvpp2_bm_bufs_free(port->dev->dev.parent, |
4075 | port->priv, new_pool); | |
3f518509 MW |
4076 | |
4077 | new_pool->pkt_size = pkt_size; | |
0e037281 TP |
4078 | new_pool->frag_size = |
4079 | SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + | |
4080 | MVPP2_SKB_SHINFO_SIZE; | |
3f518509 MW |
4081 | |
4082 | /* Allocate buffers for this pool */ | |
4083 | num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); | |
4084 | if (num != pkts_num) { | |
4085 | WARN(1, "pool %d: %d of %d allocated\n", | |
4086 | new_pool->id, num, pkts_num); | |
3f518509 MW |
4087 | return NULL; |
4088 | } | |
4089 | } | |
4090 | ||
4091 | mvpp2_bm_pool_bufsize_set(port->priv, new_pool, | |
4092 | MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); | |
4093 | ||
3f518509 MW |
4094 | return new_pool; |
4095 | } | |
4096 | ||
4097 | /* Initialize pools for swf */ | |
4098 | static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) | |
4099 | { | |
3f518509 MW |
4100 | int rxq; |
4101 | ||
4102 | if (!port->pool_long) { | |
4103 | port->pool_long = | |
4104 | mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), | |
4105 | MVPP2_BM_SWF_LONG, | |
4106 | port->pkt_size); | |
4107 | if (!port->pool_long) | |
4108 | return -ENOMEM; | |
4109 | ||
3f518509 | 4110 | port->pool_long->port_map |= (1 << port->id); |
3f518509 | 4111 | |
09f83975 | 4112 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4113 | mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); |
4114 | } | |
4115 | ||
4116 | if (!port->pool_short) { | |
4117 | port->pool_short = | |
4118 | mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL, | |
4119 | MVPP2_BM_SWF_SHORT, | |
4120 | MVPP2_BM_SHORT_PKT_SIZE); | |
4121 | if (!port->pool_short) | |
4122 | return -ENOMEM; | |
4123 | ||
3f518509 | 4124 | port->pool_short->port_map |= (1 << port->id); |
3f518509 | 4125 | |
09f83975 | 4126 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4127 | mvpp2_rxq_short_pool_set(port, rxq, |
4128 | port->pool_short->id); | |
4129 | } | |
4130 | ||
4131 | return 0; | |
4132 | } | |
4133 | ||
4134 | static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) | |
4135 | { | |
4136 | struct mvpp2_port *port = netdev_priv(dev); | |
4137 | struct mvpp2_bm_pool *port_pool = port->pool_long; | |
4138 | int num, pkts_num = port_pool->buf_num; | |
4139 | int pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
4140 | ||
4141 | /* Update BM pool with new buffer size */ | |
4229d502 | 4142 | mvpp2_bm_bufs_free(dev->dev.parent, port->priv, port_pool); |
d74c96c1 | 4143 | if (port_pool->buf_num) { |
3f518509 MW |
4144 | WARN(1, "cannot free all buffers in pool %d\n", port_pool->id); |
4145 | return -EIO; | |
4146 | } | |
4147 | ||
4148 | port_pool->pkt_size = pkt_size; | |
0e037281 TP |
4149 | port_pool->frag_size = SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + |
4150 | MVPP2_SKB_SHINFO_SIZE; | |
3f518509 MW |
4151 | num = mvpp2_bm_bufs_add(port, port_pool, pkts_num); |
4152 | if (num != pkts_num) { | |
4153 | WARN(1, "pool %d: %d of %d allocated\n", | |
4154 | port_pool->id, num, pkts_num); | |
4155 | return -EIO; | |
4156 | } | |
4157 | ||
4158 | mvpp2_bm_pool_bufsize_set(port->priv, port_pool, | |
4159 | MVPP2_RX_BUF_SIZE(port_pool->pkt_size)); | |
4160 | dev->mtu = mtu; | |
4161 | netdev_update_features(dev); | |
4162 | return 0; | |
4163 | } | |
4164 | ||
4165 | static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) | |
4166 | { | |
591f4cfa TP |
4167 | int i, sw_thread_mask = 0; |
4168 | ||
4169 | for (i = 0; i < port->nqvecs; i++) | |
4170 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
3f518509 | 4171 | |
3f518509 | 4172 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa | 4173 | MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); |
3f518509 MW |
4174 | } |
4175 | ||
4176 | static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) | |
4177 | { | |
591f4cfa TP |
4178 | int i, sw_thread_mask = 0; |
4179 | ||
4180 | for (i = 0; i < port->nqvecs; i++) | |
4181 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
4182 | ||
4183 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4184 | MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); | |
4185 | } | |
4186 | ||
4187 | static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) | |
4188 | { | |
4189 | struct mvpp2_port *port = qvec->port; | |
3f518509 | 4190 | |
3f518509 | 4191 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa TP |
4192 | MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); |
4193 | } | |
4194 | ||
4195 | static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) | |
4196 | { | |
4197 | struct mvpp2_port *port = qvec->port; | |
4198 | ||
4199 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4200 | MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); | |
3f518509 MW |
4201 | } |
4202 | ||
e0af22d9 TP |
4203 | /* Mask the current CPU's Rx/Tx interrupts |
4204 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4205 | * using smp_processor_id() is OK. | |
4206 | */ | |
3f518509 MW |
4207 | static void mvpp2_interrupts_mask(void *arg) |
4208 | { | |
4209 | struct mvpp2_port *port = arg; | |
4210 | ||
a786841d TP |
4211 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
4212 | MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); | |
3f518509 MW |
4213 | } |
4214 | ||
e0af22d9 TP |
4215 | /* Unmask the current CPU's Rx/Tx interrupts. |
4216 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4217 | * using smp_processor_id() is OK. | |
4218 | */ | |
3f518509 MW |
4219 | static void mvpp2_interrupts_unmask(void *arg) |
4220 | { | |
4221 | struct mvpp2_port *port = arg; | |
213f428f TP |
4222 | u32 val; |
4223 | ||
4224 | val = MVPP2_CAUSE_MISC_SUM_MASK | | |
4225 | MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4226 | if (port->has_tx_irqs) | |
4227 | val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; | |
3f518509 | 4228 | |
a786841d | 4229 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
213f428f TP |
4230 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); |
4231 | } | |
4232 | ||
4233 | static void | |
4234 | mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) | |
4235 | { | |
4236 | u32 val; | |
4237 | int i; | |
4238 | ||
4239 | if (port->priv->hw_version != MVPP22) | |
4240 | return; | |
4241 | ||
4242 | if (mask) | |
4243 | val = 0; | |
4244 | else | |
4245 | val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4246 | ||
4247 | for (i = 0; i < port->nqvecs; i++) { | |
4248 | struct mvpp2_queue_vector *v = port->qvecs + i; | |
4249 | ||
4250 | if (v->type != MVPP2_QUEUE_VECTOR_SHARED) | |
4251 | continue; | |
4252 | ||
4253 | mvpp2_percpu_write(port->priv, v->sw_thread_id, | |
4254 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); | |
4255 | } | |
3f518509 MW |
4256 | } |
4257 | ||
4258 | /* Port configuration routines */ | |
4259 | ||
3919357f AT |
4260 | static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port) |
4261 | { | |
4262 | u32 val; | |
4263 | ||
4264 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4265 | val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); | |
4266 | val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL | | |
4267 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
4268 | val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; | |
4269 | writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); | |
4270 | ||
4271 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4272 | val |= MVPP2_GMAC_DISABLE_PADDING; | |
4273 | val &= ~MVPP2_GMAC_FLOW_CTRL_MASK; | |
4274 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4275 | } else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || | |
4276 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
4277 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
4278 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { | |
4279 | val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); | |
4280 | val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | | |
4281 | MVPP22_CTRL4_SYNC_BYPASS_DIS | | |
4282 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
4283 | val &= ~MVPP22_CTRL4_DP_CLK_SEL; | |
4284 | writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); | |
4285 | ||
4286 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4287 | val &= ~MVPP2_GMAC_DISABLE_PADDING; | |
4288 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4289 | } | |
4290 | ||
4291 | /* The port is connected to a copper PHY */ | |
4292 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4293 | val &= ~MVPP2_GMAC_PORT_TYPE_MASK; | |
4294 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4295 | ||
4296 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4297 | val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | | |
4298 | MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | | |
4299 | MVPP2_GMAC_AN_DUPLEX_EN; | |
4300 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
4301 | val |= MVPP2_GMAC_IN_BAND_AUTONEG; | |
4302 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4303 | } | |
4304 | ||
4305 | static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port) | |
4306 | { | |
4307 | u32 val; | |
4308 | ||
4309 | /* Force link down */ | |
4310 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4311 | val &= ~MVPP2_GMAC_FORCE_LINK_PASS; | |
4312 | val |= MVPP2_GMAC_FORCE_LINK_DOWN; | |
4313 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4314 | ||
4315 | /* Set the GMAC in a reset state */ | |
4316 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4317 | val |= MVPP2_GMAC_PORT_RESET_MASK; | |
4318 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4319 | ||
4320 | /* Configure the PCS and in-band AN */ | |
4321 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4322 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4323 | val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; | |
4324 | } else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || | |
4325 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
4326 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
4327 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { | |
4328 | val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; | |
4329 | val |= MVPP2_GMAC_PORT_RGMII_MASK; | |
4330 | } | |
4331 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4332 | ||
4333 | mvpp2_port_mii_gmac_configure_mode(port); | |
4334 | ||
4335 | /* Unset the GMAC reset state */ | |
4336 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
4337 | val &= ~MVPP2_GMAC_PORT_RESET_MASK; | |
4338 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4339 | ||
4340 | /* Stop forcing link down */ | |
4341 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4342 | val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; | |
4343 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4344 | } | |
4345 | ||
77321959 AT |
4346 | static void mvpp2_port_mii_xlg_configure(struct mvpp2_port *port) |
4347 | { | |
4348 | u32 val; | |
4349 | ||
4350 | if (port->gop_id != 0) | |
4351 | return; | |
4352 | ||
4353 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4354 | val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; | |
4355 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
4356 | ||
4357 | val = readl(port->base + MVPP22_XLG_CTRL4_REG); | |
4358 | val &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; | |
4359 | val |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC; | |
4360 | writel(val, port->base + MVPP22_XLG_CTRL4_REG); | |
4361 | } | |
4362 | ||
26975821 TP |
4363 | static void mvpp22_port_mii_set(struct mvpp2_port *port) |
4364 | { | |
4365 | u32 val; | |
4366 | ||
26975821 TP |
4367 | /* Only GOP port 0 has an XLG MAC */ |
4368 | if (port->gop_id == 0) { | |
4369 | val = readl(port->base + MVPP22_XLG_CTRL3_REG); | |
4370 | val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; | |
725757ae AT |
4371 | |
4372 | if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
4373 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
4374 | val |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; | |
4375 | else | |
4376 | val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; | |
4377 | ||
26975821 TP |
4378 | writel(val, port->base + MVPP22_XLG_CTRL3_REG); |
4379 | } | |
26975821 TP |
4380 | } |
4381 | ||
3f518509 MW |
4382 | static void mvpp2_port_mii_set(struct mvpp2_port *port) |
4383 | { | |
26975821 TP |
4384 | if (port->priv->hw_version == MVPP22) |
4385 | mvpp22_port_mii_set(port); | |
4386 | ||
3919357f AT |
4387 | if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || |
4388 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || | |
4389 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
4390 | port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID || | |
4391 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
4392 | mvpp2_port_mii_gmac_configure(port); | |
77321959 AT |
4393 | else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) |
4394 | mvpp2_port_mii_xlg_configure(port); | |
08a23755 | 4395 | } |
3f518509 | 4396 | |
08a23755 MW |
4397 | static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) |
4398 | { | |
4399 | u32 val; | |
4400 | ||
4401 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
4402 | val |= MVPP2_GMAC_FC_ADV_EN; | |
4403 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
3f518509 MW |
4404 | } |
4405 | ||
4406 | static void mvpp2_port_enable(struct mvpp2_port *port) | |
4407 | { | |
4408 | u32 val; | |
4409 | ||
725757ae AT |
4410 | /* Only GOP port 0 has an XLG MAC */ |
4411 | if (port->gop_id == 0 && | |
4412 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
4413 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
4414 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4415 | val |= MVPP22_XLG_CTRL0_PORT_EN | | |
4416 | MVPP22_XLG_CTRL0_MAC_RESET_DIS; | |
4417 | val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; | |
4418 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
4419 | } else { | |
4420 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4421 | val |= MVPP2_GMAC_PORT_EN_MASK; | |
4422 | val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; | |
4423 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4424 | } | |
3f518509 MW |
4425 | } |
4426 | ||
4427 | static void mvpp2_port_disable(struct mvpp2_port *port) | |
4428 | { | |
4429 | u32 val; | |
4430 | ||
725757ae AT |
4431 | /* Only GOP port 0 has an XLG MAC */ |
4432 | if (port->gop_id == 0 && | |
4433 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
4434 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
4435 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4436 | val &= ~(MVPP22_XLG_CTRL0_PORT_EN | | |
4437 | MVPP22_XLG_CTRL0_MAC_RESET_DIS); | |
4438 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
4439 | } else { | |
4440 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4441 | val &= ~(MVPP2_GMAC_PORT_EN_MASK); | |
4442 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4443 | } | |
3f518509 MW |
4444 | } |
4445 | ||
4446 | /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ | |
4447 | static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) | |
4448 | { | |
4449 | u32 val; | |
4450 | ||
4451 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & | |
4452 | ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; | |
4453 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
4454 | } | |
4455 | ||
4456 | /* Configure loopback port */ | |
4457 | static void mvpp2_port_loopback_set(struct mvpp2_port *port) | |
4458 | { | |
4459 | u32 val; | |
4460 | ||
4461 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
4462 | ||
4463 | if (port->speed == 1000) | |
4464 | val |= MVPP2_GMAC_GMII_LB_EN_MASK; | |
4465 | else | |
4466 | val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; | |
4467 | ||
4468 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
4469 | val |= MVPP2_GMAC_PCS_LB_EN_MASK; | |
4470 | else | |
4471 | val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; | |
4472 | ||
4473 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
4474 | } | |
4475 | ||
4476 | static void mvpp2_port_reset(struct mvpp2_port *port) | |
4477 | { | |
4478 | u32 val; | |
4479 | ||
4480 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
4481 | ~MVPP2_GMAC_PORT_RESET_MASK; | |
4482 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
4483 | ||
4484 | while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
4485 | MVPP2_GMAC_PORT_RESET_MASK) | |
4486 | continue; | |
4487 | } | |
4488 | ||
4489 | /* Change maximum receive size of the port */ | |
4490 | static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) | |
4491 | { | |
4492 | u32 val; | |
4493 | ||
4494 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
4495 | val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; | |
4496 | val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
4497 | MVPP2_GMAC_MAX_RX_SIZE_OFFS); | |
4498 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
4499 | } | |
4500 | ||
4501 | /* Set defaults to the MVPP2 port */ | |
4502 | static void mvpp2_defaults_set(struct mvpp2_port *port) | |
4503 | { | |
4504 | int tx_port_num, val, queue, ptxq, lrxq; | |
4505 | ||
3d9017d9 TP |
4506 | if (port->priv->hw_version == MVPP21) { |
4507 | /* Configure port to loopback if needed */ | |
4508 | if (port->flags & MVPP2_F_LOOPBACK) | |
4509 | mvpp2_port_loopback_set(port); | |
4510 | ||
4511 | /* Update TX FIFO MIN Threshold */ | |
4512 | val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
4513 | val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; | |
4514 | /* Min. TX threshold must be less than minimal packet length */ | |
4515 | val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); | |
4516 | writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
4517 | } | |
3f518509 MW |
4518 | |
4519 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
4520 | tx_port_num = mvpp2_egress_port(port); | |
4521 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, | |
4522 | tx_port_num); | |
4523 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); | |
4524 | ||
4525 | /* Close bandwidth for all queues */ | |
4526 | for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { | |
4527 | ptxq = mvpp2_txq_phys(port->id, queue); | |
4528 | mvpp2_write(port->priv, | |
4529 | MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); | |
4530 | } | |
4531 | ||
4532 | /* Set refill period to 1 usec, refill tokens | |
4533 | * and bucket size to maximum | |
4534 | */ | |
4535 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, | |
4536 | port->priv->tclk / USEC_PER_SEC); | |
4537 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); | |
4538 | val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; | |
4539 | val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); | |
4540 | val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; | |
4541 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); | |
4542 | val = MVPP2_TXP_TOKEN_SIZE_MAX; | |
4543 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
4544 | ||
4545 | /* Set MaximumLowLatencyPacketSize value to 256 */ | |
4546 | mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), | |
4547 | MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | | |
4548 | MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); | |
4549 | ||
4550 | /* Enable Rx cache snoop */ | |
09f83975 | 4551 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
4552 | queue = port->rxqs[lrxq]->id; |
4553 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
4554 | val |= MVPP2_SNOOP_PKT_SIZE_MASK | | |
4555 | MVPP2_SNOOP_BUF_HDR_MASK; | |
4556 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
4557 | } | |
4558 | ||
4559 | /* At default, mask all interrupts to all present cpus */ | |
4560 | mvpp2_interrupts_disable(port); | |
4561 | } | |
4562 | ||
4563 | /* Enable/disable receiving packets */ | |
4564 | static void mvpp2_ingress_enable(struct mvpp2_port *port) | |
4565 | { | |
4566 | u32 val; | |
4567 | int lrxq, queue; | |
4568 | ||
09f83975 | 4569 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
4570 | queue = port->rxqs[lrxq]->id; |
4571 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
4572 | val &= ~MVPP2_RXQ_DISABLE_MASK; | |
4573 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
4574 | } | |
4575 | } | |
4576 | ||
4577 | static void mvpp2_ingress_disable(struct mvpp2_port *port) | |
4578 | { | |
4579 | u32 val; | |
4580 | int lrxq, queue; | |
4581 | ||
09f83975 | 4582 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
4583 | queue = port->rxqs[lrxq]->id; |
4584 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
4585 | val |= MVPP2_RXQ_DISABLE_MASK; | |
4586 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
4587 | } | |
4588 | } | |
4589 | ||
4590 | /* Enable transmit via physical egress queue | |
4591 | * - HW starts take descriptors from DRAM | |
4592 | */ | |
4593 | static void mvpp2_egress_enable(struct mvpp2_port *port) | |
4594 | { | |
4595 | u32 qmap; | |
4596 | int queue; | |
4597 | int tx_port_num = mvpp2_egress_port(port); | |
4598 | ||
4599 | /* Enable all initialized TXs. */ | |
4600 | qmap = 0; | |
09f83975 | 4601 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
4602 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
4603 | ||
dbbb2f03 | 4604 | if (txq->descs) |
3f518509 MW |
4605 | qmap |= (1 << queue); |
4606 | } | |
4607 | ||
4608 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
4609 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); | |
4610 | } | |
4611 | ||
4612 | /* Disable transmit via physical egress queue | |
4613 | * - HW doesn't take descriptors from DRAM | |
4614 | */ | |
4615 | static void mvpp2_egress_disable(struct mvpp2_port *port) | |
4616 | { | |
4617 | u32 reg_data; | |
4618 | int delay; | |
4619 | int tx_port_num = mvpp2_egress_port(port); | |
4620 | ||
4621 | /* Issue stop command for active channels only */ | |
4622 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
4623 | reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & | |
4624 | MVPP2_TXP_SCHED_ENQ_MASK; | |
4625 | if (reg_data != 0) | |
4626 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, | |
4627 | (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); | |
4628 | ||
4629 | /* Wait for all Tx activity to terminate. */ | |
4630 | delay = 0; | |
4631 | do { | |
4632 | if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { | |
4633 | netdev_warn(port->dev, | |
4634 | "Tx stop timed out, status=0x%08x\n", | |
4635 | reg_data); | |
4636 | break; | |
4637 | } | |
4638 | mdelay(1); | |
4639 | delay++; | |
4640 | ||
4641 | /* Check port TX Command register that all | |
4642 | * Tx queues are stopped | |
4643 | */ | |
4644 | reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); | |
4645 | } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); | |
4646 | } | |
4647 | ||
4648 | /* Rx descriptors helper methods */ | |
4649 | ||
4650 | /* Get number of Rx descriptors occupied by received packets */ | |
4651 | static inline int | |
4652 | mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) | |
4653 | { | |
4654 | u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); | |
4655 | ||
4656 | return val & MVPP2_RXQ_OCCUPIED_MASK; | |
4657 | } | |
4658 | ||
4659 | /* Update Rx queue status with the number of occupied and available | |
4660 | * Rx descriptor slots. | |
4661 | */ | |
4662 | static inline void | |
4663 | mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, | |
4664 | int used_count, int free_count) | |
4665 | { | |
4666 | /* Decrement the number of used descriptors and increment count | |
4667 | * increment the number of free descriptors. | |
4668 | */ | |
4669 | u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); | |
4670 | ||
4671 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); | |
4672 | } | |
4673 | ||
4674 | /* Get pointer to next RX descriptor to be processed by SW */ | |
4675 | static inline struct mvpp2_rx_desc * | |
4676 | mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) | |
4677 | { | |
4678 | int rx_desc = rxq->next_desc_to_proc; | |
4679 | ||
4680 | rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); | |
4681 | prefetch(rxq->descs + rxq->next_desc_to_proc); | |
4682 | return rxq->descs + rx_desc; | |
4683 | } | |
4684 | ||
4685 | /* Set rx queue offset */ | |
4686 | static void mvpp2_rxq_offset_set(struct mvpp2_port *port, | |
4687 | int prxq, int offset) | |
4688 | { | |
4689 | u32 val; | |
4690 | ||
4691 | /* Convert offset from bytes to units of 32 bytes */ | |
4692 | offset = offset >> 5; | |
4693 | ||
4694 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); | |
4695 | val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; | |
4696 | ||
4697 | /* Offset is in */ | |
4698 | val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & | |
4699 | MVPP2_RXQ_PACKET_OFFSET_MASK); | |
4700 | ||
4701 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); | |
4702 | } | |
4703 | ||
3f518509 MW |
4704 | /* Tx descriptors helper methods */ |
4705 | ||
3f518509 MW |
4706 | /* Get pointer to next Tx descriptor to be processed (send) by HW */ |
4707 | static struct mvpp2_tx_desc * | |
4708 | mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) | |
4709 | { | |
4710 | int tx_desc = txq->next_desc_to_proc; | |
4711 | ||
4712 | txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); | |
4713 | return txq->descs + tx_desc; | |
4714 | } | |
4715 | ||
e0af22d9 TP |
4716 | /* Update HW with number of aggregated Tx descriptors to be sent |
4717 | * | |
4718 | * Called only from mvpp2_tx(), so migration is disabled, using | |
4719 | * smp_processor_id() is OK. | |
4720 | */ | |
3f518509 MW |
4721 | static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) |
4722 | { | |
4723 | /* aggregated access - relevant TXQ number is written in TX desc */ | |
a786841d TP |
4724 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
4725 | MVPP2_AGGR_TXQ_UPDATE_REG, pending); | |
3f518509 MW |
4726 | } |
4727 | ||
4728 | ||
4729 | /* Check if there are enough free descriptors in aggregated txq. | |
4730 | * If not, update the number of occupied descriptors and repeat the check. | |
e0af22d9 TP |
4731 | * |
4732 | * Called only from mvpp2_tx(), so migration is disabled, using | |
4733 | * smp_processor_id() is OK. | |
3f518509 MW |
4734 | */ |
4735 | static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, | |
4736 | struct mvpp2_tx_queue *aggr_txq, int num) | |
4737 | { | |
4738 | if ((aggr_txq->count + num) > aggr_txq->size) { | |
4739 | /* Update number of occupied aggregated Tx descriptors */ | |
4740 | int cpu = smp_processor_id(); | |
4741 | u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu)); | |
4742 | ||
4743 | aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; | |
4744 | } | |
4745 | ||
4746 | if ((aggr_txq->count + num) > aggr_txq->size) | |
4747 | return -ENOMEM; | |
4748 | ||
4749 | return 0; | |
4750 | } | |
4751 | ||
e0af22d9 TP |
4752 | /* Reserved Tx descriptors allocation request |
4753 | * | |
4754 | * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called | |
4755 | * only by mvpp2_tx(), so migration is disabled, using | |
4756 | * smp_processor_id() is OK. | |
4757 | */ | |
3f518509 MW |
4758 | static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv, |
4759 | struct mvpp2_tx_queue *txq, int num) | |
4760 | { | |
4761 | u32 val; | |
a786841d | 4762 | int cpu = smp_processor_id(); |
3f518509 MW |
4763 | |
4764 | val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; | |
a786841d | 4765 | mvpp2_percpu_write(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); |
3f518509 | 4766 | |
a786841d | 4767 | val = mvpp2_percpu_read(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); |
3f518509 MW |
4768 | |
4769 | return val & MVPP2_TXQ_RSVD_RSLT_MASK; | |
4770 | } | |
4771 | ||
4772 | /* Check if there are enough reserved descriptors for transmission. | |
4773 | * If not, request chunk of reserved descriptors and check again. | |
4774 | */ | |
4775 | static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, | |
4776 | struct mvpp2_tx_queue *txq, | |
4777 | struct mvpp2_txq_pcpu *txq_pcpu, | |
4778 | int num) | |
4779 | { | |
4780 | int req, cpu, desc_count; | |
4781 | ||
4782 | if (txq_pcpu->reserved_num >= num) | |
4783 | return 0; | |
4784 | ||
4785 | /* Not enough descriptors reserved! Update the reserved descriptor | |
4786 | * count and check again. | |
4787 | */ | |
4788 | ||
4789 | desc_count = 0; | |
4790 | /* Compute total of used descriptors */ | |
4791 | for_each_present_cpu(cpu) { | |
4792 | struct mvpp2_txq_pcpu *txq_pcpu_aux; | |
4793 | ||
4794 | txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu); | |
4795 | desc_count += txq_pcpu_aux->count; | |
4796 | desc_count += txq_pcpu_aux->reserved_num; | |
4797 | } | |
4798 | ||
4799 | req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); | |
4800 | desc_count += req; | |
4801 | ||
4802 | if (desc_count > | |
4803 | (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) | |
4804 | return -ENOMEM; | |
4805 | ||
4806 | txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); | |
4807 | ||
4808 | /* OK, the descriptor cound has been updated: check again. */ | |
4809 | if (txq_pcpu->reserved_num < num) | |
4810 | return -ENOMEM; | |
4811 | return 0; | |
4812 | } | |
4813 | ||
4814 | /* Release the last allocated Tx descriptor. Useful to handle DMA | |
4815 | * mapping failures in the Tx path. | |
4816 | */ | |
4817 | static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) | |
4818 | { | |
4819 | if (txq->next_desc_to_proc == 0) | |
4820 | txq->next_desc_to_proc = txq->last_desc - 1; | |
4821 | else | |
4822 | txq->next_desc_to_proc--; | |
4823 | } | |
4824 | ||
4825 | /* Set Tx descriptors fields relevant for CSUM calculation */ | |
4826 | static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto, | |
4827 | int ip_hdr_len, int l4_proto) | |
4828 | { | |
4829 | u32 command; | |
4830 | ||
4831 | /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
4832 | * G_L4_chk, L4_type required only for checksum calculation | |
4833 | */ | |
4834 | command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); | |
4835 | command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); | |
4836 | command |= MVPP2_TXD_IP_CSUM_DISABLE; | |
4837 | ||
4838 | if (l3_proto == swab16(ETH_P_IP)) { | |
4839 | command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ | |
4840 | command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ | |
4841 | } else { | |
4842 | command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ | |
4843 | } | |
4844 | ||
4845 | if (l4_proto == IPPROTO_TCP) { | |
4846 | command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ | |
4847 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
4848 | } else if (l4_proto == IPPROTO_UDP) { | |
4849 | command |= MVPP2_TXD_L4_UDP; /* enable UDP */ | |
4850 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
4851 | } else { | |
4852 | command |= MVPP2_TXD_L4_CSUM_NOT; | |
4853 | } | |
4854 | ||
4855 | return command; | |
4856 | } | |
4857 | ||
4858 | /* Get number of sent descriptors and decrement counter. | |
4859 | * The number of sent descriptors is returned. | |
4860 | * Per-CPU access | |
e0af22d9 TP |
4861 | * |
4862 | * Called only from mvpp2_txq_done(), called from mvpp2_tx() | |
4863 | * (migration disabled) and from the TX completion tasklet (migration | |
4864 | * disabled) so using smp_processor_id() is OK. | |
3f518509 MW |
4865 | */ |
4866 | static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, | |
4867 | struct mvpp2_tx_queue *txq) | |
4868 | { | |
4869 | u32 val; | |
4870 | ||
4871 | /* Reading status reg resets transmitted descriptor counter */ | |
a786841d TP |
4872 | val = mvpp2_percpu_read(port->priv, smp_processor_id(), |
4873 | MVPP2_TXQ_SENT_REG(txq->id)); | |
3f518509 MW |
4874 | |
4875 | return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> | |
4876 | MVPP2_TRANSMITTED_COUNT_OFFSET; | |
4877 | } | |
4878 | ||
e0af22d9 TP |
4879 | /* Called through on_each_cpu(), so runs on all CPUs, with migration |
4880 | * disabled, therefore using smp_processor_id() is OK. | |
4881 | */ | |
3f518509 MW |
4882 | static void mvpp2_txq_sent_counter_clear(void *arg) |
4883 | { | |
4884 | struct mvpp2_port *port = arg; | |
4885 | int queue; | |
4886 | ||
09f83975 | 4887 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
4888 | int id = port->txqs[queue]->id; |
4889 | ||
a786841d TP |
4890 | mvpp2_percpu_read(port->priv, smp_processor_id(), |
4891 | MVPP2_TXQ_SENT_REG(id)); | |
3f518509 MW |
4892 | } |
4893 | } | |
4894 | ||
4895 | /* Set max sizes for Tx queues */ | |
4896 | static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) | |
4897 | { | |
4898 | u32 val, size, mtu; | |
4899 | int txq, tx_port_num; | |
4900 | ||
4901 | mtu = port->pkt_size * 8; | |
4902 | if (mtu > MVPP2_TXP_MTU_MAX) | |
4903 | mtu = MVPP2_TXP_MTU_MAX; | |
4904 | ||
4905 | /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ | |
4906 | mtu = 3 * mtu; | |
4907 | ||
4908 | /* Indirect access to registers */ | |
4909 | tx_port_num = mvpp2_egress_port(port); | |
4910 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
4911 | ||
4912 | /* Set MTU */ | |
4913 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); | |
4914 | val &= ~MVPP2_TXP_MTU_MAX; | |
4915 | val |= mtu; | |
4916 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); | |
4917 | ||
4918 | /* TXP token size and all TXQs token size must be larger that MTU */ | |
4919 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); | |
4920 | size = val & MVPP2_TXP_TOKEN_SIZE_MAX; | |
4921 | if (size < mtu) { | |
4922 | size = mtu; | |
4923 | val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; | |
4924 | val |= size; | |
4925 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
4926 | } | |
4927 | ||
09f83975 | 4928 | for (txq = 0; txq < port->ntxqs; txq++) { |
3f518509 MW |
4929 | val = mvpp2_read(port->priv, |
4930 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); | |
4931 | size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; | |
4932 | ||
4933 | if (size < mtu) { | |
4934 | size = mtu; | |
4935 | val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; | |
4936 | val |= size; | |
4937 | mvpp2_write(port->priv, | |
4938 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), | |
4939 | val); | |
4940 | } | |
4941 | } | |
4942 | } | |
4943 | ||
4944 | /* Set the number of packets that will be received before Rx interrupt | |
4945 | * will be generated by HW. | |
4946 | */ | |
4947 | static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 4948 | struct mvpp2_rx_queue *rxq) |
3f518509 | 4949 | { |
a704bb5c | 4950 | int cpu = get_cpu(); |
a786841d | 4951 | |
f8b0d5f8 TP |
4952 | if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) |
4953 | rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; | |
3f518509 | 4954 | |
a786841d TP |
4955 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
4956 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG, | |
4957 | rxq->pkts_coal); | |
a704bb5c TP |
4958 | |
4959 | put_cpu(); | |
3f518509 MW |
4960 | } |
4961 | ||
213f428f TP |
4962 | /* For some reason in the LSP this is done on each CPU. Why ? */ |
4963 | static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, | |
4964 | struct mvpp2_tx_queue *txq) | |
4965 | { | |
4966 | int cpu = get_cpu(); | |
4967 | u32 val; | |
4968 | ||
4969 | if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) | |
4970 | txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; | |
4971 | ||
4972 | val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); | |
4973 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); | |
4974 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val); | |
4975 | ||
4976 | put_cpu(); | |
4977 | } | |
4978 | ||
ab42676a TP |
4979 | static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) |
4980 | { | |
4981 | u64 tmp = (u64)clk_hz * usec; | |
4982 | ||
4983 | do_div(tmp, USEC_PER_SEC); | |
4984 | ||
4985 | return tmp > U32_MAX ? U32_MAX : tmp; | |
4986 | } | |
4987 | ||
4988 | static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) | |
4989 | { | |
4990 | u64 tmp = (u64)cycles * USEC_PER_SEC; | |
4991 | ||
4992 | do_div(tmp, clk_hz); | |
4993 | ||
4994 | return tmp > U32_MAX ? U32_MAX : tmp; | |
4995 | } | |
4996 | ||
3f518509 MW |
4997 | /* Set the time delay in usec before Rx interrupt */ |
4998 | static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 4999 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5000 | { |
ab42676a TP |
5001 | unsigned long freq = port->priv->tclk; |
5002 | u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5003 | ||
5004 | if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { | |
5005 | rxq->time_coal = | |
5006 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); | |
5007 | ||
5008 | /* re-evaluate to get actual register value */ | |
5009 | val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5010 | } | |
3f518509 | 5011 | |
3f518509 | 5012 | mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); |
3f518509 MW |
5013 | } |
5014 | ||
213f428f TP |
5015 | static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) |
5016 | { | |
5017 | unsigned long freq = port->priv->tclk; | |
5018 | u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5019 | ||
5020 | if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { | |
5021 | port->tx_time_coal = | |
5022 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); | |
5023 | ||
5024 | /* re-evaluate to get actual register value */ | |
5025 | val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5026 | } | |
5027 | ||
5028 | mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); | |
5029 | } | |
5030 | ||
3f518509 MW |
5031 | /* Free Tx queue skbuffs */ |
5032 | static void mvpp2_txq_bufs_free(struct mvpp2_port *port, | |
5033 | struct mvpp2_tx_queue *txq, | |
5034 | struct mvpp2_txq_pcpu *txq_pcpu, int num) | |
5035 | { | |
5036 | int i; | |
5037 | ||
5038 | for (i = 0; i < num; i++) { | |
8354491c TP |
5039 | struct mvpp2_txq_pcpu_buf *tx_buf = |
5040 | txq_pcpu->buffs + txq_pcpu->txq_get_index; | |
3f518509 | 5041 | |
20396136 | 5042 | dma_unmap_single(port->dev->dev.parent, tx_buf->dma, |
8354491c | 5043 | tx_buf->size, DMA_TO_DEVICE); |
36fb7435 TP |
5044 | if (tx_buf->skb) |
5045 | dev_kfree_skb_any(tx_buf->skb); | |
5046 | ||
5047 | mvpp2_txq_inc_get(txq_pcpu); | |
3f518509 MW |
5048 | } |
5049 | } | |
5050 | ||
5051 | static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, | |
5052 | u32 cause) | |
5053 | { | |
5054 | int queue = fls(cause) - 1; | |
5055 | ||
5056 | return port->rxqs[queue]; | |
5057 | } | |
5058 | ||
5059 | static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, | |
5060 | u32 cause) | |
5061 | { | |
edc660fa | 5062 | int queue = fls(cause) - 1; |
3f518509 MW |
5063 | |
5064 | return port->txqs[queue]; | |
5065 | } | |
5066 | ||
5067 | /* Handle end of transmission */ | |
5068 | static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, | |
5069 | struct mvpp2_txq_pcpu *txq_pcpu) | |
5070 | { | |
5071 | struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); | |
5072 | int tx_done; | |
5073 | ||
5074 | if (txq_pcpu->cpu != smp_processor_id()) | |
5075 | netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); | |
5076 | ||
5077 | tx_done = mvpp2_txq_sent_desc_proc(port, txq); | |
5078 | if (!tx_done) | |
5079 | return; | |
5080 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); | |
5081 | ||
5082 | txq_pcpu->count -= tx_done; | |
5083 | ||
5084 | if (netif_tx_queue_stopped(nq)) | |
5085 | if (txq_pcpu->size - txq_pcpu->count >= MAX_SKB_FRAGS + 1) | |
5086 | netif_tx_wake_queue(nq); | |
5087 | } | |
5088 | ||
213f428f TP |
5089 | static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, |
5090 | int cpu) | |
edc660fa MW |
5091 | { |
5092 | struct mvpp2_tx_queue *txq; | |
5093 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5094 | unsigned int tx_todo = 0; | |
5095 | ||
5096 | while (cause) { | |
5097 | txq = mvpp2_get_tx_queue(port, cause); | |
5098 | if (!txq) | |
5099 | break; | |
5100 | ||
213f428f | 5101 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); |
edc660fa MW |
5102 | |
5103 | if (txq_pcpu->count) { | |
5104 | mvpp2_txq_done(port, txq, txq_pcpu); | |
5105 | tx_todo += txq_pcpu->count; | |
5106 | } | |
5107 | ||
5108 | cause &= ~(1 << txq->log_id); | |
5109 | } | |
5110 | return tx_todo; | |
5111 | } | |
5112 | ||
3f518509 MW |
5113 | /* Rx/Tx queue initialization/cleanup methods */ |
5114 | ||
5115 | /* Allocate and initialize descriptors for aggr TXQ */ | |
5116 | static int mvpp2_aggr_txq_init(struct platform_device *pdev, | |
5117 | struct mvpp2_tx_queue *aggr_txq, | |
5118 | int desc_num, int cpu, | |
5119 | struct mvpp2 *priv) | |
5120 | { | |
b02f31fb TP |
5121 | u32 txq_dma; |
5122 | ||
3f518509 MW |
5123 | /* Allocate memory for TX descriptors */ |
5124 | aggr_txq->descs = dma_alloc_coherent(&pdev->dev, | |
5125 | desc_num * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5126 | &aggr_txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5127 | if (!aggr_txq->descs) |
5128 | return -ENOMEM; | |
5129 | ||
3f518509 MW |
5130 | aggr_txq->last_desc = aggr_txq->size - 1; |
5131 | ||
5132 | /* Aggr TXQ no reset WA */ | |
5133 | aggr_txq->next_desc_to_proc = mvpp2_read(priv, | |
5134 | MVPP2_AGGR_TXQ_INDEX_REG(cpu)); | |
5135 | ||
b02f31fb TP |
5136 | /* Set Tx descriptors queue starting address indirect |
5137 | * access | |
5138 | */ | |
5139 | if (priv->hw_version == MVPP21) | |
5140 | txq_dma = aggr_txq->descs_dma; | |
5141 | else | |
5142 | txq_dma = aggr_txq->descs_dma >> | |
5143 | MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; | |
5144 | ||
5145 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); | |
3f518509 MW |
5146 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num); |
5147 | ||
5148 | return 0; | |
5149 | } | |
5150 | ||
5151 | /* Create a specified Rx queue */ | |
5152 | static int mvpp2_rxq_init(struct mvpp2_port *port, | |
5153 | struct mvpp2_rx_queue *rxq) | |
5154 | ||
5155 | { | |
b02f31fb | 5156 | u32 rxq_dma; |
a786841d | 5157 | int cpu; |
b02f31fb | 5158 | |
3f518509 MW |
5159 | rxq->size = port->rx_ring_size; |
5160 | ||
5161 | /* Allocate memory for RX descriptors */ | |
5162 | rxq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
5163 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5164 | &rxq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5165 | if (!rxq->descs) |
5166 | return -ENOMEM; | |
5167 | ||
3f518509 MW |
5168 | rxq->last_desc = rxq->size - 1; |
5169 | ||
5170 | /* Zero occupied and non-occupied counters - direct access */ | |
5171 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
5172 | ||
5173 | /* Set Rx descriptors queue starting address - indirect access */ | |
a704bb5c | 5174 | cpu = get_cpu(); |
a786841d | 5175 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
b02f31fb TP |
5176 | if (port->priv->hw_version == MVPP21) |
5177 | rxq_dma = rxq->descs_dma; | |
5178 | else | |
5179 | rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; | |
a786841d TP |
5180 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); |
5181 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); | |
5182 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0); | |
a704bb5c | 5183 | put_cpu(); |
3f518509 MW |
5184 | |
5185 | /* Set Offset */ | |
5186 | mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); | |
5187 | ||
5188 | /* Set coalescing pkts and time */ | |
d63f9e41 TP |
5189 | mvpp2_rx_pkts_coal_set(port, rxq); |
5190 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
5191 | |
5192 | /* Add number of descriptors ready for receiving packets */ | |
5193 | mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); | |
5194 | ||
5195 | return 0; | |
5196 | } | |
5197 | ||
5198 | /* Push packets received by the RXQ to BM pool */ | |
5199 | static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, | |
5200 | struct mvpp2_rx_queue *rxq) | |
5201 | { | |
5202 | int rx_received, i; | |
5203 | ||
5204 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
5205 | if (!rx_received) | |
5206 | return; | |
5207 | ||
5208 | for (i = 0; i < rx_received; i++) { | |
5209 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); | |
56b8aae9 TP |
5210 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
5211 | int pool; | |
5212 | ||
5213 | pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> | |
5214 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 5215 | |
7d7627ba | 5216 | mvpp2_bm_pool_put(port, pool, |
ac3dd277 TP |
5217 | mvpp2_rxdesc_dma_addr_get(port, rx_desc), |
5218 | mvpp2_rxdesc_cookie_get(port, rx_desc)); | |
3f518509 MW |
5219 | } |
5220 | mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); | |
5221 | } | |
5222 | ||
5223 | /* Cleanup Rx queue */ | |
5224 | static void mvpp2_rxq_deinit(struct mvpp2_port *port, | |
5225 | struct mvpp2_rx_queue *rxq) | |
5226 | { | |
a786841d TP |
5227 | int cpu; |
5228 | ||
3f518509 MW |
5229 | mvpp2_rxq_drop_pkts(port, rxq); |
5230 | ||
5231 | if (rxq->descs) | |
5232 | dma_free_coherent(port->dev->dev.parent, | |
5233 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
5234 | rxq->descs, | |
20396136 | 5235 | rxq->descs_dma); |
3f518509 MW |
5236 | |
5237 | rxq->descs = NULL; | |
5238 | rxq->last_desc = 0; | |
5239 | rxq->next_desc_to_proc = 0; | |
20396136 | 5240 | rxq->descs_dma = 0; |
3f518509 MW |
5241 | |
5242 | /* Clear Rx descriptors queue starting address and size; | |
5243 | * free descriptor number | |
5244 | */ | |
5245 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
a704bb5c | 5246 | cpu = get_cpu(); |
a786841d TP |
5247 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
5248 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0); | |
5249 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 5250 | put_cpu(); |
3f518509 MW |
5251 | } |
5252 | ||
5253 | /* Create and initialize a Tx queue */ | |
5254 | static int mvpp2_txq_init(struct mvpp2_port *port, | |
5255 | struct mvpp2_tx_queue *txq) | |
5256 | { | |
5257 | u32 val; | |
5258 | int cpu, desc, desc_per_txq, tx_port_num; | |
5259 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5260 | ||
5261 | txq->size = port->tx_ring_size; | |
5262 | ||
5263 | /* Allocate memory for Tx descriptors */ | |
5264 | txq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
5265 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5266 | &txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5267 | if (!txq->descs) |
5268 | return -ENOMEM; | |
5269 | ||
3f518509 MW |
5270 | txq->last_desc = txq->size - 1; |
5271 | ||
5272 | /* Set Tx descriptors queue starting address - indirect access */ | |
a704bb5c | 5273 | cpu = get_cpu(); |
a786841d TP |
5274 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5275 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, | |
5276 | txq->descs_dma); | |
5277 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, | |
5278 | txq->size & MVPP2_TXQ_DESC_SIZE_MASK); | |
5279 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0); | |
5280 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG, | |
5281 | txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); | |
5282 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG); | |
3f518509 | 5283 | val &= ~MVPP2_TXQ_PENDING_MASK; |
a786841d | 5284 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val); |
3f518509 MW |
5285 | |
5286 | /* Calculate base address in prefetch buffer. We reserve 16 descriptors | |
5287 | * for each existing TXQ. | |
5288 | * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT | |
5289 | * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS | |
5290 | */ | |
5291 | desc_per_txq = 16; | |
5292 | desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + | |
5293 | (txq->log_id * desc_per_txq); | |
5294 | ||
a786841d TP |
5295 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, |
5296 | MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | | |
5297 | MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); | |
a704bb5c | 5298 | put_cpu(); |
3f518509 MW |
5299 | |
5300 | /* WRR / EJP configuration - indirect access */ | |
5301 | tx_port_num = mvpp2_egress_port(port); | |
5302 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5303 | ||
5304 | val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); | |
5305 | val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; | |
5306 | val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); | |
5307 | val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; | |
5308 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); | |
5309 | ||
5310 | val = MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5311 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), | |
5312 | val); | |
5313 | ||
5314 | for_each_present_cpu(cpu) { | |
5315 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
5316 | txq_pcpu->size = txq->size; | |
02c91ece ME |
5317 | txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, |
5318 | sizeof(*txq_pcpu->buffs), | |
5319 | GFP_KERNEL); | |
8354491c | 5320 | if (!txq_pcpu->buffs) |
20b1e16e | 5321 | goto cleanup; |
3f518509 MW |
5322 | |
5323 | txq_pcpu->count = 0; | |
5324 | txq_pcpu->reserved_num = 0; | |
5325 | txq_pcpu->txq_put_index = 0; | |
5326 | txq_pcpu->txq_get_index = 0; | |
5327 | } | |
5328 | ||
5329 | return 0; | |
20b1e16e | 5330 | cleanup: |
71ce391d MW |
5331 | for_each_present_cpu(cpu) { |
5332 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8354491c | 5333 | kfree(txq_pcpu->buffs); |
71ce391d MW |
5334 | } |
5335 | ||
5336 | dma_free_coherent(port->dev->dev.parent, | |
5337 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5338 | txq->descs, txq->descs_dma); |
71ce391d MW |
5339 | |
5340 | return -ENOMEM; | |
3f518509 MW |
5341 | } |
5342 | ||
5343 | /* Free allocated TXQ resources */ | |
5344 | static void mvpp2_txq_deinit(struct mvpp2_port *port, | |
5345 | struct mvpp2_tx_queue *txq) | |
5346 | { | |
5347 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5348 | int cpu; | |
5349 | ||
5350 | for_each_present_cpu(cpu) { | |
5351 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8354491c | 5352 | kfree(txq_pcpu->buffs); |
3f518509 MW |
5353 | } |
5354 | ||
5355 | if (txq->descs) | |
5356 | dma_free_coherent(port->dev->dev.parent, | |
5357 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5358 | txq->descs, txq->descs_dma); |
3f518509 MW |
5359 | |
5360 | txq->descs = NULL; | |
5361 | txq->last_desc = 0; | |
5362 | txq->next_desc_to_proc = 0; | |
20396136 | 5363 | txq->descs_dma = 0; |
3f518509 MW |
5364 | |
5365 | /* Set minimum bandwidth for disabled TXQs */ | |
5366 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); | |
5367 | ||
5368 | /* Set Tx descriptors queue starting address and size */ | |
a704bb5c | 5369 | cpu = get_cpu(); |
a786841d TP |
5370 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5371 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0); | |
5372 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 5373 | put_cpu(); |
3f518509 MW |
5374 | } |
5375 | ||
5376 | /* Cleanup Tx ports */ | |
5377 | static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) | |
5378 | { | |
5379 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5380 | int delay, pending, cpu; | |
5381 | u32 val; | |
5382 | ||
a704bb5c | 5383 | cpu = get_cpu(); |
a786841d TP |
5384 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5385 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG); | |
3f518509 | 5386 | val |= MVPP2_TXQ_DRAIN_EN_MASK; |
a786841d | 5387 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
3f518509 MW |
5388 | |
5389 | /* The napi queue has been stopped so wait for all packets | |
5390 | * to be transmitted. | |
5391 | */ | |
5392 | delay = 0; | |
5393 | do { | |
5394 | if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { | |
5395 | netdev_warn(port->dev, | |
5396 | "port %d: cleaning queue %d timed out\n", | |
5397 | port->id, txq->log_id); | |
5398 | break; | |
5399 | } | |
5400 | mdelay(1); | |
5401 | delay++; | |
5402 | ||
a786841d TP |
5403 | pending = mvpp2_percpu_read(port->priv, cpu, |
5404 | MVPP2_TXQ_PENDING_REG); | |
5405 | pending &= MVPP2_TXQ_PENDING_MASK; | |
3f518509 MW |
5406 | } while (pending); |
5407 | ||
5408 | val &= ~MVPP2_TXQ_DRAIN_EN_MASK; | |
a786841d | 5409 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
a704bb5c | 5410 | put_cpu(); |
3f518509 MW |
5411 | |
5412 | for_each_present_cpu(cpu) { | |
5413 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
5414 | ||
5415 | /* Release all packets */ | |
5416 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); | |
5417 | ||
5418 | /* Reset queue */ | |
5419 | txq_pcpu->count = 0; | |
5420 | txq_pcpu->txq_put_index = 0; | |
5421 | txq_pcpu->txq_get_index = 0; | |
5422 | } | |
5423 | } | |
5424 | ||
5425 | /* Cleanup all Tx queues */ | |
5426 | static void mvpp2_cleanup_txqs(struct mvpp2_port *port) | |
5427 | { | |
5428 | struct mvpp2_tx_queue *txq; | |
5429 | int queue; | |
5430 | u32 val; | |
5431 | ||
5432 | val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); | |
5433 | ||
5434 | /* Reset Tx ports and delete Tx queues */ | |
5435 | val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
5436 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
5437 | ||
09f83975 | 5438 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5439 | txq = port->txqs[queue]; |
5440 | mvpp2_txq_clean(port, txq); | |
5441 | mvpp2_txq_deinit(port, txq); | |
5442 | } | |
5443 | ||
5444 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); | |
5445 | ||
5446 | val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
5447 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
5448 | } | |
5449 | ||
5450 | /* Cleanup all Rx queues */ | |
5451 | static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) | |
5452 | { | |
5453 | int queue; | |
5454 | ||
09f83975 | 5455 | for (queue = 0; queue < port->nrxqs; queue++) |
3f518509 MW |
5456 | mvpp2_rxq_deinit(port, port->rxqs[queue]); |
5457 | } | |
5458 | ||
5459 | /* Init all Rx queues for port */ | |
5460 | static int mvpp2_setup_rxqs(struct mvpp2_port *port) | |
5461 | { | |
5462 | int queue, err; | |
5463 | ||
09f83975 | 5464 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
5465 | err = mvpp2_rxq_init(port, port->rxqs[queue]); |
5466 | if (err) | |
5467 | goto err_cleanup; | |
5468 | } | |
5469 | return 0; | |
5470 | ||
5471 | err_cleanup: | |
5472 | mvpp2_cleanup_rxqs(port); | |
5473 | return err; | |
5474 | } | |
5475 | ||
5476 | /* Init all tx queues for port */ | |
5477 | static int mvpp2_setup_txqs(struct mvpp2_port *port) | |
5478 | { | |
5479 | struct mvpp2_tx_queue *txq; | |
5480 | int queue, err; | |
5481 | ||
09f83975 | 5482 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5483 | txq = port->txqs[queue]; |
5484 | err = mvpp2_txq_init(port, txq); | |
5485 | if (err) | |
5486 | goto err_cleanup; | |
5487 | } | |
5488 | ||
213f428f TP |
5489 | if (port->has_tx_irqs) { |
5490 | mvpp2_tx_time_coal_set(port); | |
5491 | for (queue = 0; queue < port->ntxqs; queue++) { | |
5492 | txq = port->txqs[queue]; | |
5493 | mvpp2_tx_pkts_coal_set(port, txq); | |
5494 | } | |
5495 | } | |
5496 | ||
3f518509 MW |
5497 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); |
5498 | return 0; | |
5499 | ||
5500 | err_cleanup: | |
5501 | mvpp2_cleanup_txqs(port); | |
5502 | return err; | |
5503 | } | |
5504 | ||
5505 | /* The callback for per-port interrupt */ | |
5506 | static irqreturn_t mvpp2_isr(int irq, void *dev_id) | |
5507 | { | |
591f4cfa | 5508 | struct mvpp2_queue_vector *qv = dev_id; |
3f518509 | 5509 | |
591f4cfa | 5510 | mvpp2_qvec_interrupt_disable(qv); |
3f518509 | 5511 | |
591f4cfa | 5512 | napi_schedule(&qv->napi); |
3f518509 MW |
5513 | |
5514 | return IRQ_HANDLED; | |
5515 | } | |
5516 | ||
5517 | /* Adjust link */ | |
5518 | static void mvpp2_link_event(struct net_device *dev) | |
5519 | { | |
5520 | struct mvpp2_port *port = netdev_priv(dev); | |
8e07269d | 5521 | struct phy_device *phydev = dev->phydev; |
3f518509 MW |
5522 | int status_change = 0; |
5523 | u32 val; | |
5524 | ||
5525 | if (phydev->link) { | |
5526 | if ((port->speed != phydev->speed) || | |
5527 | (port->duplex != phydev->duplex)) { | |
5528 | u32 val; | |
5529 | ||
5530 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5531 | val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | | |
5532 | MVPP2_GMAC_CONFIG_GMII_SPEED | | |
5533 | MVPP2_GMAC_CONFIG_FULL_DUPLEX | | |
5534 | MVPP2_GMAC_AN_SPEED_EN | | |
5535 | MVPP2_GMAC_AN_DUPLEX_EN); | |
5536 | ||
5537 | if (phydev->duplex) | |
5538 | val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; | |
5539 | ||
5540 | if (phydev->speed == SPEED_1000) | |
5541 | val |= MVPP2_GMAC_CONFIG_GMII_SPEED; | |
2add511e | 5542 | else if (phydev->speed == SPEED_100) |
3f518509 MW |
5543 | val |= MVPP2_GMAC_CONFIG_MII_SPEED; |
5544 | ||
5545 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5546 | ||
5547 | port->duplex = phydev->duplex; | |
5548 | port->speed = phydev->speed; | |
5549 | } | |
5550 | } | |
5551 | ||
5552 | if (phydev->link != port->link) { | |
5553 | if (!phydev->link) { | |
5554 | port->duplex = -1; | |
5555 | port->speed = 0; | |
5556 | } | |
5557 | ||
5558 | port->link = phydev->link; | |
5559 | status_change = 1; | |
5560 | } | |
5561 | ||
5562 | if (status_change) { | |
5563 | if (phydev->link) { | |
5564 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5565 | val |= (MVPP2_GMAC_FORCE_LINK_PASS | | |
5566 | MVPP2_GMAC_FORCE_LINK_DOWN); | |
5567 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
5568 | mvpp2_egress_enable(port); | |
5569 | mvpp2_ingress_enable(port); | |
5570 | } else { | |
5571 | mvpp2_ingress_disable(port); | |
5572 | mvpp2_egress_disable(port); | |
5573 | } | |
5574 | phy_print_status(phydev); | |
5575 | } | |
5576 | } | |
5577 | ||
edc660fa MW |
5578 | static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) |
5579 | { | |
5580 | ktime_t interval; | |
5581 | ||
5582 | if (!port_pcpu->timer_scheduled) { | |
5583 | port_pcpu->timer_scheduled = true; | |
8b0e1953 | 5584 | interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; |
edc660fa MW |
5585 | hrtimer_start(&port_pcpu->tx_done_timer, interval, |
5586 | HRTIMER_MODE_REL_PINNED); | |
5587 | } | |
5588 | } | |
5589 | ||
5590 | static void mvpp2_tx_proc_cb(unsigned long data) | |
5591 | { | |
5592 | struct net_device *dev = (struct net_device *)data; | |
5593 | struct mvpp2_port *port = netdev_priv(dev); | |
5594 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); | |
5595 | unsigned int tx_todo, cause; | |
5596 | ||
5597 | if (!netif_running(dev)) | |
5598 | return; | |
5599 | port_pcpu->timer_scheduled = false; | |
5600 | ||
5601 | /* Process all the Tx queues */ | |
09f83975 | 5602 | cause = (1 << port->ntxqs) - 1; |
213f428f | 5603 | tx_todo = mvpp2_tx_done(port, cause, smp_processor_id()); |
edc660fa MW |
5604 | |
5605 | /* Set the timer in case not all the packets were processed */ | |
5606 | if (tx_todo) | |
5607 | mvpp2_timer_set(port_pcpu); | |
5608 | } | |
5609 | ||
5610 | static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) | |
5611 | { | |
5612 | struct mvpp2_port_pcpu *port_pcpu = container_of(timer, | |
5613 | struct mvpp2_port_pcpu, | |
5614 | tx_done_timer); | |
5615 | ||
5616 | tasklet_schedule(&port_pcpu->tx_done_tasklet); | |
5617 | ||
5618 | return HRTIMER_NORESTART; | |
5619 | } | |
5620 | ||
3f518509 MW |
5621 | /* Main RX/TX processing routines */ |
5622 | ||
5623 | /* Display more error info */ | |
5624 | static void mvpp2_rx_error(struct mvpp2_port *port, | |
5625 | struct mvpp2_rx_desc *rx_desc) | |
5626 | { | |
ac3dd277 TP |
5627 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
5628 | size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); | |
3f518509 MW |
5629 | |
5630 | switch (status & MVPP2_RXD_ERR_CODE_MASK) { | |
5631 | case MVPP2_RXD_ERR_CRC: | |
ac3dd277 TP |
5632 | netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", |
5633 | status, sz); | |
3f518509 MW |
5634 | break; |
5635 | case MVPP2_RXD_ERR_OVERRUN: | |
ac3dd277 TP |
5636 | netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", |
5637 | status, sz); | |
3f518509 MW |
5638 | break; |
5639 | case MVPP2_RXD_ERR_RESOURCE: | |
ac3dd277 TP |
5640 | netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", |
5641 | status, sz); | |
3f518509 MW |
5642 | break; |
5643 | } | |
5644 | } | |
5645 | ||
5646 | /* Handle RX checksum offload */ | |
5647 | static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, | |
5648 | struct sk_buff *skb) | |
5649 | { | |
5650 | if (((status & MVPP2_RXD_L3_IP4) && | |
5651 | !(status & MVPP2_RXD_IP4_HEADER_ERR)) || | |
5652 | (status & MVPP2_RXD_L3_IP6)) | |
5653 | if (((status & MVPP2_RXD_L4_UDP) || | |
5654 | (status & MVPP2_RXD_L4_TCP)) && | |
5655 | (status & MVPP2_RXD_L4_CSUM_OK)) { | |
5656 | skb->csum = 0; | |
5657 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5658 | return; | |
5659 | } | |
5660 | ||
5661 | skb->ip_summed = CHECKSUM_NONE; | |
5662 | } | |
5663 | ||
5664 | /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ | |
5665 | static int mvpp2_rx_refill(struct mvpp2_port *port, | |
56b8aae9 | 5666 | struct mvpp2_bm_pool *bm_pool, int pool) |
3f518509 | 5667 | { |
20396136 | 5668 | dma_addr_t dma_addr; |
4e4a105f | 5669 | phys_addr_t phys_addr; |
0e037281 | 5670 | void *buf; |
3f518509 | 5671 | |
3f518509 | 5672 | /* No recycle or too many buffers are in use, so allocate a new skb */ |
4e4a105f TP |
5673 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, |
5674 | GFP_ATOMIC); | |
0e037281 | 5675 | if (!buf) |
3f518509 MW |
5676 | return -ENOMEM; |
5677 | ||
7d7627ba | 5678 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
7ef7e1d9 | 5679 | |
3f518509 MW |
5680 | return 0; |
5681 | } | |
5682 | ||
5683 | /* Handle tx checksum */ | |
5684 | static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) | |
5685 | { | |
5686 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
5687 | int ip_hdr_len = 0; | |
5688 | u8 l4_proto; | |
5689 | ||
5690 | if (skb->protocol == htons(ETH_P_IP)) { | |
5691 | struct iphdr *ip4h = ip_hdr(skb); | |
5692 | ||
5693 | /* Calculate IPv4 checksum and L4 checksum */ | |
5694 | ip_hdr_len = ip4h->ihl; | |
5695 | l4_proto = ip4h->protocol; | |
5696 | } else if (skb->protocol == htons(ETH_P_IPV6)) { | |
5697 | struct ipv6hdr *ip6h = ipv6_hdr(skb); | |
5698 | ||
5699 | /* Read l4_protocol from one of IPv6 extra headers */ | |
5700 | if (skb_network_header_len(skb) > 0) | |
5701 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
5702 | l4_proto = ip6h->nexthdr; | |
5703 | } else { | |
5704 | return MVPP2_TXD_L4_CSUM_NOT; | |
5705 | } | |
5706 | ||
5707 | return mvpp2_txq_desc_csum(skb_network_offset(skb), | |
5708 | skb->protocol, ip_hdr_len, l4_proto); | |
5709 | } | |
5710 | ||
5711 | return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; | |
5712 | } | |
5713 | ||
3f518509 | 5714 | /* Main rx processing */ |
591f4cfa TP |
5715 | static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, |
5716 | int rx_todo, struct mvpp2_rx_queue *rxq) | |
3f518509 MW |
5717 | { |
5718 | struct net_device *dev = port->dev; | |
b5015854 MW |
5719 | int rx_received; |
5720 | int rx_done = 0; | |
3f518509 MW |
5721 | u32 rcvd_pkts = 0; |
5722 | u32 rcvd_bytes = 0; | |
5723 | ||
5724 | /* Get number of received packets and clamp the to-do */ | |
5725 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
5726 | if (rx_todo > rx_received) | |
5727 | rx_todo = rx_received; | |
5728 | ||
b5015854 | 5729 | while (rx_done < rx_todo) { |
3f518509 MW |
5730 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); |
5731 | struct mvpp2_bm_pool *bm_pool; | |
5732 | struct sk_buff *skb; | |
0e037281 | 5733 | unsigned int frag_size; |
20396136 | 5734 | dma_addr_t dma_addr; |
ac3dd277 | 5735 | phys_addr_t phys_addr; |
56b8aae9 | 5736 | u32 rx_status; |
3f518509 | 5737 | int pool, rx_bytes, err; |
0e037281 | 5738 | void *data; |
3f518509 | 5739 | |
b5015854 | 5740 | rx_done++; |
ac3dd277 TP |
5741 | rx_status = mvpp2_rxdesc_status_get(port, rx_desc); |
5742 | rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); | |
5743 | rx_bytes -= MVPP2_MH_SIZE; | |
5744 | dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); | |
5745 | phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); | |
5746 | data = (void *)phys_to_virt(phys_addr); | |
5747 | ||
56b8aae9 TP |
5748 | pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> |
5749 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 5750 | bm_pool = &port->priv->bm_pools[pool]; |
3f518509 MW |
5751 | |
5752 | /* In case of an error, release the requested buffer pointer | |
5753 | * to the Buffer Manager. This request process is controlled | |
5754 | * by the hardware, and the information about the buffer is | |
5755 | * comprised by the RX descriptor. | |
5756 | */ | |
5757 | if (rx_status & MVPP2_RXD_ERR_SUMMARY) { | |
8a52488b | 5758 | err_drop_frame: |
3f518509 MW |
5759 | dev->stats.rx_errors++; |
5760 | mvpp2_rx_error(port, rx_desc); | |
b5015854 | 5761 | /* Return the buffer to the pool */ |
7d7627ba | 5762 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
3f518509 MW |
5763 | continue; |
5764 | } | |
5765 | ||
0e037281 TP |
5766 | if (bm_pool->frag_size > PAGE_SIZE) |
5767 | frag_size = 0; | |
5768 | else | |
5769 | frag_size = bm_pool->frag_size; | |
5770 | ||
5771 | skb = build_skb(data, frag_size); | |
5772 | if (!skb) { | |
5773 | netdev_warn(port->dev, "skb build failed\n"); | |
5774 | goto err_drop_frame; | |
5775 | } | |
3f518509 | 5776 | |
56b8aae9 | 5777 | err = mvpp2_rx_refill(port, bm_pool, pool); |
b5015854 MW |
5778 | if (err) { |
5779 | netdev_err(port->dev, "failed to refill BM pools\n"); | |
5780 | goto err_drop_frame; | |
5781 | } | |
5782 | ||
20396136 | 5783 | dma_unmap_single(dev->dev.parent, dma_addr, |
4229d502 MW |
5784 | bm_pool->buf_size, DMA_FROM_DEVICE); |
5785 | ||
3f518509 MW |
5786 | rcvd_pkts++; |
5787 | rcvd_bytes += rx_bytes; | |
3f518509 | 5788 | |
0e037281 | 5789 | skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); |
3f518509 MW |
5790 | skb_put(skb, rx_bytes); |
5791 | skb->protocol = eth_type_trans(skb, dev); | |
5792 | mvpp2_rx_csum(port, rx_status, skb); | |
5793 | ||
591f4cfa | 5794 | napi_gro_receive(napi, skb); |
3f518509 MW |
5795 | } |
5796 | ||
5797 | if (rcvd_pkts) { | |
5798 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
5799 | ||
5800 | u64_stats_update_begin(&stats->syncp); | |
5801 | stats->rx_packets += rcvd_pkts; | |
5802 | stats->rx_bytes += rcvd_bytes; | |
5803 | u64_stats_update_end(&stats->syncp); | |
5804 | } | |
5805 | ||
5806 | /* Update Rx queue management counters */ | |
5807 | wmb(); | |
b5015854 | 5808 | mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); |
3f518509 MW |
5809 | |
5810 | return rx_todo; | |
5811 | } | |
5812 | ||
5813 | static inline void | |
ac3dd277 | 5814 | tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, |
3f518509 MW |
5815 | struct mvpp2_tx_desc *desc) |
5816 | { | |
ac3dd277 TP |
5817 | dma_addr_t buf_dma_addr = |
5818 | mvpp2_txdesc_dma_addr_get(port, desc); | |
5819 | size_t buf_sz = | |
5820 | mvpp2_txdesc_size_get(port, desc); | |
5821 | dma_unmap_single(port->dev->dev.parent, buf_dma_addr, | |
5822 | buf_sz, DMA_TO_DEVICE); | |
3f518509 MW |
5823 | mvpp2_txq_desc_put(txq); |
5824 | } | |
5825 | ||
5826 | /* Handle tx fragmentation processing */ | |
5827 | static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, | |
5828 | struct mvpp2_tx_queue *aggr_txq, | |
5829 | struct mvpp2_tx_queue *txq) | |
5830 | { | |
5831 | struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); | |
5832 | struct mvpp2_tx_desc *tx_desc; | |
5833 | int i; | |
20396136 | 5834 | dma_addr_t buf_dma_addr; |
3f518509 MW |
5835 | |
5836 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
5837 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5838 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
5839 | ||
5840 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
5841 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
5842 | mvpp2_txdesc_size_set(port, tx_desc, frag->size); | |
3f518509 | 5843 | |
20396136 | 5844 | buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, |
ac3dd277 TP |
5845 | frag->size, |
5846 | DMA_TO_DEVICE); | |
20396136 | 5847 | if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { |
3f518509 | 5848 | mvpp2_txq_desc_put(txq); |
32bae631 | 5849 | goto cleanup; |
3f518509 MW |
5850 | } |
5851 | ||
ac3dd277 TP |
5852 | mvpp2_txdesc_offset_set(port, tx_desc, |
5853 | buf_dma_addr & MVPP2_TX_DESC_ALIGN); | |
5854 | mvpp2_txdesc_dma_addr_set(port, tx_desc, | |
5855 | buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); | |
3f518509 MW |
5856 | |
5857 | if (i == (skb_shinfo(skb)->nr_frags - 1)) { | |
5858 | /* Last descriptor */ | |
ac3dd277 TP |
5859 | mvpp2_txdesc_cmd_set(port, tx_desc, |
5860 | MVPP2_TXD_L_DESC); | |
5861 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
5862 | } else { |
5863 | /* Descriptor in the middle: Not First, Not Last */ | |
ac3dd277 TP |
5864 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); |
5865 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
5866 | } |
5867 | } | |
5868 | ||
5869 | return 0; | |
32bae631 | 5870 | cleanup: |
3f518509 MW |
5871 | /* Release all descriptors that were used to map fragments of |
5872 | * this packet, as well as the corresponding DMA mappings | |
5873 | */ | |
5874 | for (i = i - 1; i >= 0; i--) { | |
5875 | tx_desc = txq->descs + i; | |
ac3dd277 | 5876 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 MW |
5877 | } |
5878 | ||
5879 | return -ENOMEM; | |
5880 | } | |
5881 | ||
5882 | /* Main tx processing */ | |
5883 | static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev) | |
5884 | { | |
5885 | struct mvpp2_port *port = netdev_priv(dev); | |
5886 | struct mvpp2_tx_queue *txq, *aggr_txq; | |
5887 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5888 | struct mvpp2_tx_desc *tx_desc; | |
20396136 | 5889 | dma_addr_t buf_dma_addr; |
3f518509 MW |
5890 | int frags = 0; |
5891 | u16 txq_id; | |
5892 | u32 tx_cmd; | |
5893 | ||
5894 | txq_id = skb_get_queue_mapping(skb); | |
5895 | txq = port->txqs[txq_id]; | |
5896 | txq_pcpu = this_cpu_ptr(txq->pcpu); | |
5897 | aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; | |
5898 | ||
5899 | frags = skb_shinfo(skb)->nr_frags + 1; | |
5900 | ||
5901 | /* Check number of available descriptors */ | |
5902 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || | |
5903 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, | |
5904 | txq_pcpu, frags)) { | |
5905 | frags = 0; | |
5906 | goto out; | |
5907 | } | |
5908 | ||
5909 | /* Get a descriptor for the first part of the packet */ | |
5910 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
5911 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
5912 | mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); | |
3f518509 | 5913 | |
20396136 | 5914 | buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, |
ac3dd277 | 5915 | skb_headlen(skb), DMA_TO_DEVICE); |
20396136 | 5916 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { |
3f518509 MW |
5917 | mvpp2_txq_desc_put(txq); |
5918 | frags = 0; | |
5919 | goto out; | |
5920 | } | |
ac3dd277 TP |
5921 | |
5922 | mvpp2_txdesc_offset_set(port, tx_desc, | |
5923 | buf_dma_addr & MVPP2_TX_DESC_ALIGN); | |
5924 | mvpp2_txdesc_dma_addr_set(port, tx_desc, | |
5925 | buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); | |
3f518509 MW |
5926 | |
5927 | tx_cmd = mvpp2_skb_tx_csum(port, skb); | |
5928 | ||
5929 | if (frags == 1) { | |
5930 | /* First and Last descriptor */ | |
5931 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; | |
ac3dd277 TP |
5932 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
5933 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
5934 | } else { |
5935 | /* First but not Last */ | |
5936 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; | |
ac3dd277 TP |
5937 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
5938 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
5939 | |
5940 | /* Continue with other skb fragments */ | |
5941 | if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { | |
ac3dd277 | 5942 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 MW |
5943 | frags = 0; |
5944 | goto out; | |
5945 | } | |
5946 | } | |
5947 | ||
5948 | txq_pcpu->reserved_num -= frags; | |
5949 | txq_pcpu->count += frags; | |
5950 | aggr_txq->count += frags; | |
5951 | ||
5952 | /* Enable transmit */ | |
5953 | wmb(); | |
5954 | mvpp2_aggr_txq_pend_desc_add(port, frags); | |
5955 | ||
5956 | if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) { | |
5957 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); | |
5958 | ||
5959 | netif_tx_stop_queue(nq); | |
5960 | } | |
5961 | out: | |
5962 | if (frags > 0) { | |
5963 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
5964 | ||
5965 | u64_stats_update_begin(&stats->syncp); | |
5966 | stats->tx_packets++; | |
5967 | stats->tx_bytes += skb->len; | |
5968 | u64_stats_update_end(&stats->syncp); | |
5969 | } else { | |
5970 | dev->stats.tx_dropped++; | |
5971 | dev_kfree_skb_any(skb); | |
5972 | } | |
5973 | ||
edc660fa MW |
5974 | /* Finalize TX processing */ |
5975 | if (txq_pcpu->count >= txq->done_pkts_coal) | |
5976 | mvpp2_txq_done(port, txq, txq_pcpu); | |
5977 | ||
5978 | /* Set the timer in case not all frags were processed */ | |
213f428f TP |
5979 | if (!port->has_tx_irqs && txq_pcpu->count <= frags && |
5980 | txq_pcpu->count > 0) { | |
edc660fa MW |
5981 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); |
5982 | ||
5983 | mvpp2_timer_set(port_pcpu); | |
5984 | } | |
5985 | ||
3f518509 MW |
5986 | return NETDEV_TX_OK; |
5987 | } | |
5988 | ||
5989 | static inline void mvpp2_cause_error(struct net_device *dev, int cause) | |
5990 | { | |
5991 | if (cause & MVPP2_CAUSE_FCS_ERR_MASK) | |
5992 | netdev_err(dev, "FCS error\n"); | |
5993 | if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) | |
5994 | netdev_err(dev, "rx fifo overrun error\n"); | |
5995 | if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) | |
5996 | netdev_err(dev, "tx fifo underrun error\n"); | |
5997 | } | |
5998 | ||
edc660fa | 5999 | static int mvpp2_poll(struct napi_struct *napi, int budget) |
3f518509 | 6000 | { |
213f428f | 6001 | u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; |
edc660fa MW |
6002 | int rx_done = 0; |
6003 | struct mvpp2_port *port = netdev_priv(napi->dev); | |
591f4cfa | 6004 | struct mvpp2_queue_vector *qv; |
a786841d | 6005 | int cpu = smp_processor_id(); |
3f518509 | 6006 | |
591f4cfa TP |
6007 | qv = container_of(napi, struct mvpp2_queue_vector, napi); |
6008 | ||
3f518509 MW |
6009 | /* Rx/Tx cause register |
6010 | * | |
6011 | * Bits 0-15: each bit indicates received packets on the Rx queue | |
6012 | * (bit 0 is for Rx queue 0). | |
6013 | * | |
6014 | * Bits 16-23: each bit indicates transmitted packets on the Tx queue | |
6015 | * (bit 16 is for Tx queue 0). | |
6016 | * | |
6017 | * Each CPU has its own Rx/Tx cause register | |
6018 | */ | |
213f428f | 6019 | cause_rx_tx = mvpp2_percpu_read(port->priv, qv->sw_thread_id, |
a786841d | 6020 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); |
3f518509 | 6021 | |
213f428f | 6022 | cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; |
3f518509 MW |
6023 | if (cause_misc) { |
6024 | mvpp2_cause_error(port->dev, cause_misc); | |
6025 | ||
6026 | /* Clear the cause register */ | |
6027 | mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); | |
a786841d TP |
6028 | mvpp2_percpu_write(port->priv, cpu, |
6029 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id), | |
6030 | cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); | |
3f518509 MW |
6031 | } |
6032 | ||
213f428f TP |
6033 | cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; |
6034 | if (cause_tx) { | |
6035 | cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; | |
6036 | mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); | |
6037 | } | |
3f518509 MW |
6038 | |
6039 | /* Process RX packets */ | |
213f428f TP |
6040 | cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; |
6041 | cause_rx <<= qv->first_rxq; | |
591f4cfa | 6042 | cause_rx |= qv->pending_cause_rx; |
3f518509 MW |
6043 | while (cause_rx && budget > 0) { |
6044 | int count; | |
6045 | struct mvpp2_rx_queue *rxq; | |
6046 | ||
6047 | rxq = mvpp2_get_rx_queue(port, cause_rx); | |
6048 | if (!rxq) | |
6049 | break; | |
6050 | ||
591f4cfa | 6051 | count = mvpp2_rx(port, napi, budget, rxq); |
3f518509 MW |
6052 | rx_done += count; |
6053 | budget -= count; | |
6054 | if (budget > 0) { | |
6055 | /* Clear the bit associated to this Rx queue | |
6056 | * so that next iteration will continue from | |
6057 | * the next Rx queue. | |
6058 | */ | |
6059 | cause_rx &= ~(1 << rxq->logic_rxq); | |
6060 | } | |
6061 | } | |
6062 | ||
6063 | if (budget > 0) { | |
6064 | cause_rx = 0; | |
6ad20165 | 6065 | napi_complete_done(napi, rx_done); |
3f518509 | 6066 | |
591f4cfa | 6067 | mvpp2_qvec_interrupt_enable(qv); |
3f518509 | 6068 | } |
591f4cfa | 6069 | qv->pending_cause_rx = cause_rx; |
3f518509 MW |
6070 | return rx_done; |
6071 | } | |
6072 | ||
6073 | /* Set hw internals when starting port */ | |
6074 | static void mvpp2_start_dev(struct mvpp2_port *port) | |
6075 | { | |
8e07269d | 6076 | struct net_device *ndev = port->dev; |
591f4cfa | 6077 | int i; |
8e07269d | 6078 | |
3f518509 MW |
6079 | mvpp2_gmac_max_rx_size_set(port); |
6080 | mvpp2_txp_max_tx_size_set(port); | |
6081 | ||
591f4cfa TP |
6082 | for (i = 0; i < port->nqvecs; i++) |
6083 | napi_enable(&port->qvecs[i].napi); | |
3f518509 MW |
6084 | |
6085 | /* Enable interrupts on all CPUs */ | |
6086 | mvpp2_interrupts_enable(port); | |
6087 | ||
2055d626 | 6088 | mvpp2_port_mii_set(port); |
3f518509 | 6089 | mvpp2_port_enable(port); |
8e07269d | 6090 | phy_start(ndev->phydev); |
3f518509 MW |
6091 | netif_tx_start_all_queues(port->dev); |
6092 | } | |
6093 | ||
6094 | /* Set hw internals when stopping port */ | |
6095 | static void mvpp2_stop_dev(struct mvpp2_port *port) | |
6096 | { | |
8e07269d | 6097 | struct net_device *ndev = port->dev; |
591f4cfa | 6098 | int i; |
8e07269d | 6099 | |
3f518509 MW |
6100 | /* Stop new packets from arriving to RXQs */ |
6101 | mvpp2_ingress_disable(port); | |
6102 | ||
6103 | mdelay(10); | |
6104 | ||
6105 | /* Disable interrupts on all CPUs */ | |
6106 | mvpp2_interrupts_disable(port); | |
6107 | ||
591f4cfa TP |
6108 | for (i = 0; i < port->nqvecs; i++) |
6109 | napi_disable(&port->qvecs[i].napi); | |
3f518509 MW |
6110 | |
6111 | netif_carrier_off(port->dev); | |
6112 | netif_tx_stop_all_queues(port->dev); | |
6113 | ||
6114 | mvpp2_egress_disable(port); | |
6115 | mvpp2_port_disable(port); | |
8e07269d | 6116 | phy_stop(ndev->phydev); |
3f518509 MW |
6117 | } |
6118 | ||
3f518509 MW |
6119 | static int mvpp2_check_ringparam_valid(struct net_device *dev, |
6120 | struct ethtool_ringparam *ring) | |
6121 | { | |
6122 | u16 new_rx_pending = ring->rx_pending; | |
6123 | u16 new_tx_pending = ring->tx_pending; | |
6124 | ||
6125 | if (ring->rx_pending == 0 || ring->tx_pending == 0) | |
6126 | return -EINVAL; | |
6127 | ||
6128 | if (ring->rx_pending > MVPP2_MAX_RXD) | |
6129 | new_rx_pending = MVPP2_MAX_RXD; | |
6130 | else if (!IS_ALIGNED(ring->rx_pending, 16)) | |
6131 | new_rx_pending = ALIGN(ring->rx_pending, 16); | |
6132 | ||
6133 | if (ring->tx_pending > MVPP2_MAX_TXD) | |
6134 | new_tx_pending = MVPP2_MAX_TXD; | |
6135 | else if (!IS_ALIGNED(ring->tx_pending, 32)) | |
6136 | new_tx_pending = ALIGN(ring->tx_pending, 32); | |
6137 | ||
6138 | if (ring->rx_pending != new_rx_pending) { | |
6139 | netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", | |
6140 | ring->rx_pending, new_rx_pending); | |
6141 | ring->rx_pending = new_rx_pending; | |
6142 | } | |
6143 | ||
6144 | if (ring->tx_pending != new_tx_pending) { | |
6145 | netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", | |
6146 | ring->tx_pending, new_tx_pending); | |
6147 | ring->tx_pending = new_tx_pending; | |
6148 | } | |
6149 | ||
6150 | return 0; | |
6151 | } | |
6152 | ||
26975821 | 6153 | static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) |
3f518509 MW |
6154 | { |
6155 | u32 mac_addr_l, mac_addr_m, mac_addr_h; | |
6156 | ||
6157 | mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
6158 | mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); | |
6159 | mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); | |
6160 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
6161 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
6162 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
6163 | addr[3] = mac_addr_h & 0xFF; | |
6164 | addr[4] = mac_addr_m & 0xFF; | |
6165 | addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; | |
6166 | } | |
6167 | ||
6168 | static int mvpp2_phy_connect(struct mvpp2_port *port) | |
6169 | { | |
6170 | struct phy_device *phy_dev; | |
6171 | ||
6172 | phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0, | |
6173 | port->phy_interface); | |
6174 | if (!phy_dev) { | |
6175 | netdev_err(port->dev, "cannot connect to phy\n"); | |
6176 | return -ENODEV; | |
6177 | } | |
6178 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
6179 | phy_dev->advertising = phy_dev->supported; | |
6180 | ||
3f518509 MW |
6181 | port->link = 0; |
6182 | port->duplex = 0; | |
6183 | port->speed = 0; | |
6184 | ||
6185 | return 0; | |
6186 | } | |
6187 | ||
6188 | static void mvpp2_phy_disconnect(struct mvpp2_port *port) | |
6189 | { | |
8e07269d PR |
6190 | struct net_device *ndev = port->dev; |
6191 | ||
6192 | phy_disconnect(ndev->phydev); | |
3f518509 MW |
6193 | } |
6194 | ||
591f4cfa TP |
6195 | static int mvpp2_irqs_init(struct mvpp2_port *port) |
6196 | { | |
6197 | int err, i; | |
6198 | ||
6199 | for (i = 0; i < port->nqvecs; i++) { | |
6200 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6201 | ||
6202 | err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); | |
6203 | if (err) | |
6204 | goto err; | |
213f428f TP |
6205 | |
6206 | if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) | |
6207 | irq_set_affinity_hint(qv->irq, | |
6208 | cpumask_of(qv->sw_thread_id)); | |
591f4cfa TP |
6209 | } |
6210 | ||
6211 | return 0; | |
6212 | err: | |
6213 | for (i = 0; i < port->nqvecs; i++) { | |
6214 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6215 | ||
213f428f | 6216 | irq_set_affinity_hint(qv->irq, NULL); |
591f4cfa TP |
6217 | free_irq(qv->irq, qv); |
6218 | } | |
6219 | ||
6220 | return err; | |
6221 | } | |
6222 | ||
6223 | static void mvpp2_irqs_deinit(struct mvpp2_port *port) | |
6224 | { | |
6225 | int i; | |
6226 | ||
6227 | for (i = 0; i < port->nqvecs; i++) { | |
6228 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6229 | ||
213f428f | 6230 | irq_set_affinity_hint(qv->irq, NULL); |
591f4cfa TP |
6231 | free_irq(qv->irq, qv); |
6232 | } | |
6233 | } | |
6234 | ||
3f518509 MW |
6235 | static int mvpp2_open(struct net_device *dev) |
6236 | { | |
6237 | struct mvpp2_port *port = netdev_priv(dev); | |
6238 | unsigned char mac_bcast[ETH_ALEN] = { | |
6239 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
6240 | int err; | |
6241 | ||
6242 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); | |
6243 | if (err) { | |
6244 | netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); | |
6245 | return err; | |
6246 | } | |
6247 | err = mvpp2_prs_mac_da_accept(port->priv, port->id, | |
6248 | dev->dev_addr, true); | |
6249 | if (err) { | |
6250 | netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n"); | |
6251 | return err; | |
6252 | } | |
6253 | err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); | |
6254 | if (err) { | |
6255 | netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); | |
6256 | return err; | |
6257 | } | |
6258 | err = mvpp2_prs_def_flow(port); | |
6259 | if (err) { | |
6260 | netdev_err(dev, "mvpp2_prs_def_flow failed\n"); | |
6261 | return err; | |
6262 | } | |
6263 | ||
6264 | /* Allocate the Rx/Tx queues */ | |
6265 | err = mvpp2_setup_rxqs(port); | |
6266 | if (err) { | |
6267 | netdev_err(port->dev, "cannot allocate Rx queues\n"); | |
6268 | return err; | |
6269 | } | |
6270 | ||
6271 | err = mvpp2_setup_txqs(port); | |
6272 | if (err) { | |
6273 | netdev_err(port->dev, "cannot allocate Tx queues\n"); | |
6274 | goto err_cleanup_rxqs; | |
6275 | } | |
6276 | ||
591f4cfa | 6277 | err = mvpp2_irqs_init(port); |
3f518509 | 6278 | if (err) { |
591f4cfa | 6279 | netdev_err(port->dev, "cannot init IRQs\n"); |
3f518509 MW |
6280 | goto err_cleanup_txqs; |
6281 | } | |
6282 | ||
6283 | /* In default link is down */ | |
6284 | netif_carrier_off(port->dev); | |
6285 | ||
6286 | err = mvpp2_phy_connect(port); | |
6287 | if (err < 0) | |
6288 | goto err_free_irq; | |
6289 | ||
6290 | /* Unmask interrupts on all CPUs */ | |
6291 | on_each_cpu(mvpp2_interrupts_unmask, port, 1); | |
213f428f | 6292 | mvpp2_shared_interrupt_mask_unmask(port, false); |
3f518509 MW |
6293 | |
6294 | mvpp2_start_dev(port); | |
6295 | ||
6296 | return 0; | |
6297 | ||
6298 | err_free_irq: | |
591f4cfa | 6299 | mvpp2_irqs_deinit(port); |
3f518509 MW |
6300 | err_cleanup_txqs: |
6301 | mvpp2_cleanup_txqs(port); | |
6302 | err_cleanup_rxqs: | |
6303 | mvpp2_cleanup_rxqs(port); | |
6304 | return err; | |
6305 | } | |
6306 | ||
6307 | static int mvpp2_stop(struct net_device *dev) | |
6308 | { | |
6309 | struct mvpp2_port *port = netdev_priv(dev); | |
edc660fa MW |
6310 | struct mvpp2_port_pcpu *port_pcpu; |
6311 | int cpu; | |
3f518509 MW |
6312 | |
6313 | mvpp2_stop_dev(port); | |
6314 | mvpp2_phy_disconnect(port); | |
6315 | ||
6316 | /* Mask interrupts on all CPUs */ | |
6317 | on_each_cpu(mvpp2_interrupts_mask, port, 1); | |
213f428f | 6318 | mvpp2_shared_interrupt_mask_unmask(port, true); |
3f518509 | 6319 | |
591f4cfa | 6320 | mvpp2_irqs_deinit(port); |
213f428f TP |
6321 | if (!port->has_tx_irqs) { |
6322 | for_each_present_cpu(cpu) { | |
6323 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 6324 | |
213f428f TP |
6325 | hrtimer_cancel(&port_pcpu->tx_done_timer); |
6326 | port_pcpu->timer_scheduled = false; | |
6327 | tasklet_kill(&port_pcpu->tx_done_tasklet); | |
6328 | } | |
edc660fa | 6329 | } |
3f518509 MW |
6330 | mvpp2_cleanup_rxqs(port); |
6331 | mvpp2_cleanup_txqs(port); | |
6332 | ||
6333 | return 0; | |
6334 | } | |
6335 | ||
6336 | static void mvpp2_set_rx_mode(struct net_device *dev) | |
6337 | { | |
6338 | struct mvpp2_port *port = netdev_priv(dev); | |
6339 | struct mvpp2 *priv = port->priv; | |
6340 | struct netdev_hw_addr *ha; | |
6341 | int id = port->id; | |
6342 | bool allmulti = dev->flags & IFF_ALLMULTI; | |
6343 | ||
6344 | mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC); | |
6345 | mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti); | |
6346 | mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti); | |
6347 | ||
6348 | /* Remove all port->id's mcast enries */ | |
6349 | mvpp2_prs_mcast_del_all(priv, id); | |
6350 | ||
6351 | if (allmulti && !netdev_mc_empty(dev)) { | |
6352 | netdev_for_each_mc_addr(ha, dev) | |
6353 | mvpp2_prs_mac_da_accept(priv, id, ha->addr, true); | |
6354 | } | |
6355 | } | |
6356 | ||
6357 | static int mvpp2_set_mac_address(struct net_device *dev, void *p) | |
6358 | { | |
6359 | struct mvpp2_port *port = netdev_priv(dev); | |
6360 | const struct sockaddr *addr = p; | |
6361 | int err; | |
6362 | ||
6363 | if (!is_valid_ether_addr(addr->sa_data)) { | |
6364 | err = -EADDRNOTAVAIL; | |
c1175547 | 6365 | goto log_error; |
3f518509 MW |
6366 | } |
6367 | ||
6368 | if (!netif_running(dev)) { | |
6369 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
6370 | if (!err) | |
6371 | return 0; | |
6372 | /* Reconfigure parser to accept the original MAC address */ | |
6373 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
6374 | if (err) | |
c1175547 | 6375 | goto log_error; |
3f518509 MW |
6376 | } |
6377 | ||
6378 | mvpp2_stop_dev(port); | |
6379 | ||
6380 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
6381 | if (!err) | |
6382 | goto out_start; | |
6383 | ||
6384 | /* Reconfigure parser accept the original MAC address */ | |
6385 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
6386 | if (err) | |
c1175547 | 6387 | goto log_error; |
3f518509 MW |
6388 | out_start: |
6389 | mvpp2_start_dev(port); | |
6390 | mvpp2_egress_enable(port); | |
6391 | mvpp2_ingress_enable(port); | |
6392 | return 0; | |
c1175547 | 6393 | log_error: |
dfd4240a | 6394 | netdev_err(dev, "failed to change MAC address\n"); |
3f518509 MW |
6395 | return err; |
6396 | } | |
6397 | ||
6398 | static int mvpp2_change_mtu(struct net_device *dev, int mtu) | |
6399 | { | |
6400 | struct mvpp2_port *port = netdev_priv(dev); | |
6401 | int err; | |
6402 | ||
5777987e JW |
6403 | if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { |
6404 | netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, | |
6405 | ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); | |
6406 | mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); | |
3f518509 MW |
6407 | } |
6408 | ||
6409 | if (!netif_running(dev)) { | |
6410 | err = mvpp2_bm_update_mtu(dev, mtu); | |
6411 | if (!err) { | |
6412 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
6413 | return 0; | |
6414 | } | |
6415 | ||
6416 | /* Reconfigure BM to the original MTU */ | |
6417 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
6418 | if (err) | |
c1175547 | 6419 | goto log_error; |
3f518509 MW |
6420 | } |
6421 | ||
6422 | mvpp2_stop_dev(port); | |
6423 | ||
6424 | err = mvpp2_bm_update_mtu(dev, mtu); | |
6425 | if (!err) { | |
6426 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
6427 | goto out_start; | |
6428 | } | |
6429 | ||
6430 | /* Reconfigure BM to the original MTU */ | |
6431 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
6432 | if (err) | |
c1175547 | 6433 | goto log_error; |
3f518509 MW |
6434 | |
6435 | out_start: | |
6436 | mvpp2_start_dev(port); | |
6437 | mvpp2_egress_enable(port); | |
6438 | mvpp2_ingress_enable(port); | |
6439 | ||
6440 | return 0; | |
c1175547 | 6441 | log_error: |
dfd4240a | 6442 | netdev_err(dev, "failed to change MTU\n"); |
3f518509 MW |
6443 | return err; |
6444 | } | |
6445 | ||
bc1f4470 | 6446 | static void |
3f518509 MW |
6447 | mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
6448 | { | |
6449 | struct mvpp2_port *port = netdev_priv(dev); | |
6450 | unsigned int start; | |
6451 | int cpu; | |
6452 | ||
6453 | for_each_possible_cpu(cpu) { | |
6454 | struct mvpp2_pcpu_stats *cpu_stats; | |
6455 | u64 rx_packets; | |
6456 | u64 rx_bytes; | |
6457 | u64 tx_packets; | |
6458 | u64 tx_bytes; | |
6459 | ||
6460 | cpu_stats = per_cpu_ptr(port->stats, cpu); | |
6461 | do { | |
6462 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); | |
6463 | rx_packets = cpu_stats->rx_packets; | |
6464 | rx_bytes = cpu_stats->rx_bytes; | |
6465 | tx_packets = cpu_stats->tx_packets; | |
6466 | tx_bytes = cpu_stats->tx_bytes; | |
6467 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); | |
6468 | ||
6469 | stats->rx_packets += rx_packets; | |
6470 | stats->rx_bytes += rx_bytes; | |
6471 | stats->tx_packets += tx_packets; | |
6472 | stats->tx_bytes += tx_bytes; | |
6473 | } | |
6474 | ||
6475 | stats->rx_errors = dev->stats.rx_errors; | |
6476 | stats->rx_dropped = dev->stats.rx_dropped; | |
6477 | stats->tx_dropped = dev->stats.tx_dropped; | |
3f518509 MW |
6478 | } |
6479 | ||
bd695a5f TP |
6480 | static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
6481 | { | |
bd695a5f TP |
6482 | int ret; |
6483 | ||
8e07269d | 6484 | if (!dev->phydev) |
bd695a5f TP |
6485 | return -ENOTSUPP; |
6486 | ||
8e07269d | 6487 | ret = phy_mii_ioctl(dev->phydev, ifr, cmd); |
bd695a5f TP |
6488 | if (!ret) |
6489 | mvpp2_link_event(dev); | |
6490 | ||
6491 | return ret; | |
6492 | } | |
6493 | ||
3f518509 MW |
6494 | /* Ethtool methods */ |
6495 | ||
3f518509 MW |
6496 | /* Set interrupt coalescing for ethtools */ |
6497 | static int mvpp2_ethtool_set_coalesce(struct net_device *dev, | |
6498 | struct ethtool_coalesce *c) | |
6499 | { | |
6500 | struct mvpp2_port *port = netdev_priv(dev); | |
6501 | int queue; | |
6502 | ||
09f83975 | 6503 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
6504 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
6505 | ||
6506 | rxq->time_coal = c->rx_coalesce_usecs; | |
6507 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
d63f9e41 TP |
6508 | mvpp2_rx_pkts_coal_set(port, rxq); |
6509 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
6510 | } |
6511 | ||
213f428f TP |
6512 | if (port->has_tx_irqs) { |
6513 | port->tx_time_coal = c->tx_coalesce_usecs; | |
6514 | mvpp2_tx_time_coal_set(port); | |
6515 | } | |
6516 | ||
09f83975 | 6517 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6518 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
6519 | ||
6520 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
213f428f TP |
6521 | |
6522 | if (port->has_tx_irqs) | |
6523 | mvpp2_tx_pkts_coal_set(port, txq); | |
3f518509 MW |
6524 | } |
6525 | ||
3f518509 MW |
6526 | return 0; |
6527 | } | |
6528 | ||
6529 | /* get coalescing for ethtools */ | |
6530 | static int mvpp2_ethtool_get_coalesce(struct net_device *dev, | |
6531 | struct ethtool_coalesce *c) | |
6532 | { | |
6533 | struct mvpp2_port *port = netdev_priv(dev); | |
6534 | ||
6535 | c->rx_coalesce_usecs = port->rxqs[0]->time_coal; | |
6536 | c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; | |
6537 | c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; | |
6538 | return 0; | |
6539 | } | |
6540 | ||
6541 | static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, | |
6542 | struct ethtool_drvinfo *drvinfo) | |
6543 | { | |
6544 | strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, | |
6545 | sizeof(drvinfo->driver)); | |
6546 | strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, | |
6547 | sizeof(drvinfo->version)); | |
6548 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
6549 | sizeof(drvinfo->bus_info)); | |
6550 | } | |
6551 | ||
6552 | static void mvpp2_ethtool_get_ringparam(struct net_device *dev, | |
6553 | struct ethtool_ringparam *ring) | |
6554 | { | |
6555 | struct mvpp2_port *port = netdev_priv(dev); | |
6556 | ||
6557 | ring->rx_max_pending = MVPP2_MAX_RXD; | |
6558 | ring->tx_max_pending = MVPP2_MAX_TXD; | |
6559 | ring->rx_pending = port->rx_ring_size; | |
6560 | ring->tx_pending = port->tx_ring_size; | |
6561 | } | |
6562 | ||
6563 | static int mvpp2_ethtool_set_ringparam(struct net_device *dev, | |
6564 | struct ethtool_ringparam *ring) | |
6565 | { | |
6566 | struct mvpp2_port *port = netdev_priv(dev); | |
6567 | u16 prev_rx_ring_size = port->rx_ring_size; | |
6568 | u16 prev_tx_ring_size = port->tx_ring_size; | |
6569 | int err; | |
6570 | ||
6571 | err = mvpp2_check_ringparam_valid(dev, ring); | |
6572 | if (err) | |
6573 | return err; | |
6574 | ||
6575 | if (!netif_running(dev)) { | |
6576 | port->rx_ring_size = ring->rx_pending; | |
6577 | port->tx_ring_size = ring->tx_pending; | |
6578 | return 0; | |
6579 | } | |
6580 | ||
6581 | /* The interface is running, so we have to force a | |
6582 | * reallocation of the queues | |
6583 | */ | |
6584 | mvpp2_stop_dev(port); | |
6585 | mvpp2_cleanup_rxqs(port); | |
6586 | mvpp2_cleanup_txqs(port); | |
6587 | ||
6588 | port->rx_ring_size = ring->rx_pending; | |
6589 | port->tx_ring_size = ring->tx_pending; | |
6590 | ||
6591 | err = mvpp2_setup_rxqs(port); | |
6592 | if (err) { | |
6593 | /* Reallocate Rx queues with the original ring size */ | |
6594 | port->rx_ring_size = prev_rx_ring_size; | |
6595 | ring->rx_pending = prev_rx_ring_size; | |
6596 | err = mvpp2_setup_rxqs(port); | |
6597 | if (err) | |
6598 | goto err_out; | |
6599 | } | |
6600 | err = mvpp2_setup_txqs(port); | |
6601 | if (err) { | |
6602 | /* Reallocate Tx queues with the original ring size */ | |
6603 | port->tx_ring_size = prev_tx_ring_size; | |
6604 | ring->tx_pending = prev_tx_ring_size; | |
6605 | err = mvpp2_setup_txqs(port); | |
6606 | if (err) | |
6607 | goto err_clean_rxqs; | |
6608 | } | |
6609 | ||
6610 | mvpp2_start_dev(port); | |
6611 | mvpp2_egress_enable(port); | |
6612 | mvpp2_ingress_enable(port); | |
6613 | ||
6614 | return 0; | |
6615 | ||
6616 | err_clean_rxqs: | |
6617 | mvpp2_cleanup_rxqs(port); | |
6618 | err_out: | |
dfd4240a | 6619 | netdev_err(dev, "failed to change ring parameters"); |
3f518509 MW |
6620 | return err; |
6621 | } | |
6622 | ||
6623 | /* Device ops */ | |
6624 | ||
6625 | static const struct net_device_ops mvpp2_netdev_ops = { | |
6626 | .ndo_open = mvpp2_open, | |
6627 | .ndo_stop = mvpp2_stop, | |
6628 | .ndo_start_xmit = mvpp2_tx, | |
6629 | .ndo_set_rx_mode = mvpp2_set_rx_mode, | |
6630 | .ndo_set_mac_address = mvpp2_set_mac_address, | |
6631 | .ndo_change_mtu = mvpp2_change_mtu, | |
6632 | .ndo_get_stats64 = mvpp2_get_stats64, | |
bd695a5f | 6633 | .ndo_do_ioctl = mvpp2_ioctl, |
3f518509 MW |
6634 | }; |
6635 | ||
6636 | static const struct ethtool_ops mvpp2_eth_tool_ops = { | |
00606c49 | 6637 | .nway_reset = phy_ethtool_nway_reset, |
3f518509 | 6638 | .get_link = ethtool_op_get_link, |
3f518509 MW |
6639 | .set_coalesce = mvpp2_ethtool_set_coalesce, |
6640 | .get_coalesce = mvpp2_ethtool_get_coalesce, | |
6641 | .get_drvinfo = mvpp2_ethtool_get_drvinfo, | |
6642 | .get_ringparam = mvpp2_ethtool_get_ringparam, | |
6643 | .set_ringparam = mvpp2_ethtool_set_ringparam, | |
fb773e97 PR |
6644 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
6645 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
3f518509 MW |
6646 | }; |
6647 | ||
213f428f TP |
6648 | /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that |
6649 | * had a single IRQ defined per-port. | |
6650 | */ | |
6651 | static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, | |
6652 | struct device_node *port_node) | |
591f4cfa TP |
6653 | { |
6654 | struct mvpp2_queue_vector *v = &port->qvecs[0]; | |
6655 | ||
6656 | v->first_rxq = 0; | |
6657 | v->nrxqs = port->nrxqs; | |
6658 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
6659 | v->sw_thread_id = 0; | |
6660 | v->sw_thread_mask = *cpumask_bits(cpu_online_mask); | |
6661 | v->port = port; | |
6662 | v->irq = irq_of_parse_and_map(port_node, 0); | |
6663 | if (v->irq <= 0) | |
6664 | return -EINVAL; | |
6665 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
6666 | NAPI_POLL_WEIGHT); | |
6667 | ||
6668 | port->nqvecs = 1; | |
6669 | ||
6670 | return 0; | |
6671 | } | |
6672 | ||
213f428f TP |
6673 | static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, |
6674 | struct device_node *port_node) | |
6675 | { | |
6676 | struct mvpp2_queue_vector *v; | |
6677 | int i, ret; | |
6678 | ||
6679 | port->nqvecs = num_possible_cpus(); | |
6680 | if (queue_mode == MVPP2_QDIST_SINGLE_MODE) | |
6681 | port->nqvecs += 1; | |
6682 | ||
6683 | for (i = 0; i < port->nqvecs; i++) { | |
6684 | char irqname[16]; | |
6685 | ||
6686 | v = port->qvecs + i; | |
6687 | ||
6688 | v->port = port; | |
6689 | v->type = MVPP2_QUEUE_VECTOR_PRIVATE; | |
6690 | v->sw_thread_id = i; | |
6691 | v->sw_thread_mask = BIT(i); | |
6692 | ||
6693 | snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); | |
6694 | ||
6695 | if (queue_mode == MVPP2_QDIST_MULTI_MODE) { | |
6696 | v->first_rxq = i * MVPP2_DEFAULT_RXQ; | |
6697 | v->nrxqs = MVPP2_DEFAULT_RXQ; | |
6698 | } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && | |
6699 | i == (port->nqvecs - 1)) { | |
6700 | v->first_rxq = 0; | |
6701 | v->nrxqs = port->nrxqs; | |
6702 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
6703 | strncpy(irqname, "rx-shared", sizeof(irqname)); | |
6704 | } | |
6705 | ||
6706 | v->irq = of_irq_get_byname(port_node, irqname); | |
6707 | if (v->irq <= 0) { | |
6708 | ret = -EINVAL; | |
6709 | goto err; | |
6710 | } | |
6711 | ||
6712 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
6713 | NAPI_POLL_WEIGHT); | |
6714 | } | |
6715 | ||
6716 | return 0; | |
6717 | ||
6718 | err: | |
6719 | for (i = 0; i < port->nqvecs; i++) | |
6720 | irq_dispose_mapping(port->qvecs[i].irq); | |
6721 | return ret; | |
6722 | } | |
6723 | ||
6724 | static int mvpp2_queue_vectors_init(struct mvpp2_port *port, | |
6725 | struct device_node *port_node) | |
6726 | { | |
6727 | if (port->has_tx_irqs) | |
6728 | return mvpp2_multi_queue_vectors_init(port, port_node); | |
6729 | else | |
6730 | return mvpp2_simple_queue_vectors_init(port, port_node); | |
6731 | } | |
6732 | ||
591f4cfa TP |
6733 | static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) |
6734 | { | |
6735 | int i; | |
6736 | ||
6737 | for (i = 0; i < port->nqvecs; i++) | |
6738 | irq_dispose_mapping(port->qvecs[i].irq); | |
6739 | } | |
6740 | ||
6741 | /* Configure Rx queue group interrupt for this port */ | |
6742 | static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) | |
6743 | { | |
6744 | struct mvpp2 *priv = port->priv; | |
6745 | u32 val; | |
6746 | int i; | |
6747 | ||
6748 | if (priv->hw_version == MVPP21) { | |
6749 | mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), | |
6750 | port->nrxqs); | |
6751 | return; | |
6752 | } | |
6753 | ||
6754 | /* Handle the more complicated PPv2.2 case */ | |
6755 | for (i = 0; i < port->nqvecs; i++) { | |
6756 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
6757 | ||
6758 | if (!qv->nrxqs) | |
6759 | continue; | |
6760 | ||
6761 | val = qv->sw_thread_id; | |
6762 | val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; | |
6763 | mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); | |
6764 | ||
6765 | val = qv->first_rxq; | |
6766 | val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; | |
6767 | mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); | |
6768 | } | |
6769 | } | |
6770 | ||
3f518509 MW |
6771 | /* Initialize port HW */ |
6772 | static int mvpp2_port_init(struct mvpp2_port *port) | |
6773 | { | |
6774 | struct device *dev = port->dev->dev.parent; | |
6775 | struct mvpp2 *priv = port->priv; | |
6776 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6777 | int queue, cpu, err; | |
6778 | ||
09f83975 TP |
6779 | /* Checks for hardware constraints */ |
6780 | if (port->first_rxq + port->nrxqs > | |
59b9a31e | 6781 | MVPP2_MAX_PORTS * priv->max_port_rxqs) |
3f518509 MW |
6782 | return -EINVAL; |
6783 | ||
09f83975 TP |
6784 | if (port->nrxqs % 4 || (port->nrxqs > priv->max_port_rxqs) || |
6785 | (port->ntxqs > MVPP2_MAX_TXQ)) | |
6786 | return -EINVAL; | |
6787 | ||
3f518509 MW |
6788 | /* Disable port */ |
6789 | mvpp2_egress_disable(port); | |
6790 | mvpp2_port_disable(port); | |
6791 | ||
213f428f TP |
6792 | port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; |
6793 | ||
09f83975 | 6794 | port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), |
3f518509 MW |
6795 | GFP_KERNEL); |
6796 | if (!port->txqs) | |
6797 | return -ENOMEM; | |
6798 | ||
6799 | /* Associate physical Tx queues to this port and initialize. | |
6800 | * The mapping is predefined. | |
6801 | */ | |
09f83975 | 6802 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6803 | int queue_phy_id = mvpp2_txq_phys(port->id, queue); |
6804 | struct mvpp2_tx_queue *txq; | |
6805 | ||
6806 | txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); | |
177c8d1c CJ |
6807 | if (!txq) { |
6808 | err = -ENOMEM; | |
6809 | goto err_free_percpu; | |
6810 | } | |
3f518509 MW |
6811 | |
6812 | txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); | |
6813 | if (!txq->pcpu) { | |
6814 | err = -ENOMEM; | |
6815 | goto err_free_percpu; | |
6816 | } | |
6817 | ||
6818 | txq->id = queue_phy_id; | |
6819 | txq->log_id = queue; | |
6820 | txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; | |
6821 | for_each_present_cpu(cpu) { | |
6822 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
6823 | txq_pcpu->cpu = cpu; | |
6824 | } | |
6825 | ||
6826 | port->txqs[queue] = txq; | |
6827 | } | |
6828 | ||
09f83975 | 6829 | port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), |
3f518509 MW |
6830 | GFP_KERNEL); |
6831 | if (!port->rxqs) { | |
6832 | err = -ENOMEM; | |
6833 | goto err_free_percpu; | |
6834 | } | |
6835 | ||
6836 | /* Allocate and initialize Rx queue for this port */ | |
09f83975 | 6837 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
6838 | struct mvpp2_rx_queue *rxq; |
6839 | ||
6840 | /* Map physical Rx queue to port's logical Rx queue */ | |
6841 | rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); | |
d82b0c21 JZ |
6842 | if (!rxq) { |
6843 | err = -ENOMEM; | |
3f518509 | 6844 | goto err_free_percpu; |
d82b0c21 | 6845 | } |
3f518509 MW |
6846 | /* Map this Rx queue to a physical queue */ |
6847 | rxq->id = port->first_rxq + queue; | |
6848 | rxq->port = port->id; | |
6849 | rxq->logic_rxq = queue; | |
6850 | ||
6851 | port->rxqs[queue] = rxq; | |
6852 | } | |
6853 | ||
591f4cfa | 6854 | mvpp2_rx_irqs_setup(port); |
3f518509 MW |
6855 | |
6856 | /* Create Rx descriptor rings */ | |
09f83975 | 6857 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
6858 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
6859 | ||
6860 | rxq->size = port->rx_ring_size; | |
6861 | rxq->pkts_coal = MVPP2_RX_COAL_PKTS; | |
6862 | rxq->time_coal = MVPP2_RX_COAL_USEC; | |
6863 | } | |
6864 | ||
6865 | mvpp2_ingress_disable(port); | |
6866 | ||
6867 | /* Port default configuration */ | |
6868 | mvpp2_defaults_set(port); | |
6869 | ||
6870 | /* Port's classifier configuration */ | |
6871 | mvpp2_cls_oversize_rxq_set(port); | |
6872 | mvpp2_cls_port_config(port); | |
6873 | ||
6874 | /* Provide an initial Rx packet size */ | |
6875 | port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); | |
6876 | ||
6877 | /* Initialize pools for swf */ | |
6878 | err = mvpp2_swf_bm_pool_init(port); | |
6879 | if (err) | |
6880 | goto err_free_percpu; | |
6881 | ||
6882 | return 0; | |
6883 | ||
6884 | err_free_percpu: | |
09f83975 | 6885 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6886 | if (!port->txqs[queue]) |
6887 | continue; | |
6888 | free_percpu(port->txqs[queue]->pcpu); | |
6889 | } | |
6890 | return err; | |
6891 | } | |
6892 | ||
213f428f TP |
6893 | /* Checks if the port DT description has the TX interrupts |
6894 | * described. On PPv2.1, there are no such interrupts. On PPv2.2, | |
6895 | * there are available, but we need to keep support for old DTs. | |
6896 | */ | |
6897 | static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv, | |
6898 | struct device_node *port_node) | |
6899 | { | |
6900 | char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", | |
6901 | "tx-cpu2", "tx-cpu3" }; | |
6902 | int ret, i; | |
6903 | ||
6904 | if (priv->hw_version == MVPP21) | |
6905 | return false; | |
6906 | ||
6907 | for (i = 0; i < 5; i++) { | |
6908 | ret = of_property_match_string(port_node, "interrupt-names", | |
6909 | irqs[i]); | |
6910 | if (ret < 0) | |
6911 | return false; | |
6912 | } | |
6913 | ||
6914 | return true; | |
6915 | } | |
6916 | ||
3f518509 MW |
6917 | /* Ports initialization */ |
6918 | static int mvpp2_port_probe(struct platform_device *pdev, | |
6919 | struct device_node *port_node, | |
59b9a31e | 6920 | struct mvpp2 *priv) |
3f518509 MW |
6921 | { |
6922 | struct device_node *phy_node; | |
6923 | struct mvpp2_port *port; | |
edc660fa | 6924 | struct mvpp2_port_pcpu *port_pcpu; |
3f518509 MW |
6925 | struct net_device *dev; |
6926 | struct resource *res; | |
6927 | const char *dt_mac_addr; | |
6928 | const char *mac_from; | |
6929 | char hw_mac_addr[ETH_ALEN]; | |
09f83975 | 6930 | unsigned int ntxqs, nrxqs; |
213f428f | 6931 | bool has_tx_irqs; |
3f518509 MW |
6932 | u32 id; |
6933 | int features; | |
6934 | int phy_mode; | |
edc660fa | 6935 | int err, i, cpu; |
3f518509 | 6936 | |
213f428f TP |
6937 | has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); |
6938 | ||
6939 | if (!has_tx_irqs) | |
6940 | queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
6941 | ||
09f83975 | 6942 | ntxqs = MVPP2_MAX_TXQ; |
213f428f TP |
6943 | if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) |
6944 | nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); | |
6945 | else | |
6946 | nrxqs = MVPP2_DEFAULT_RXQ; | |
09f83975 TP |
6947 | |
6948 | dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); | |
3f518509 MW |
6949 | if (!dev) |
6950 | return -ENOMEM; | |
6951 | ||
6952 | phy_node = of_parse_phandle(port_node, "phy", 0); | |
6953 | if (!phy_node) { | |
6954 | dev_err(&pdev->dev, "missing phy\n"); | |
6955 | err = -ENODEV; | |
6956 | goto err_free_netdev; | |
6957 | } | |
6958 | ||
6959 | phy_mode = of_get_phy_mode(port_node); | |
6960 | if (phy_mode < 0) { | |
6961 | dev_err(&pdev->dev, "incorrect phy mode\n"); | |
6962 | err = phy_mode; | |
6963 | goto err_free_netdev; | |
6964 | } | |
6965 | ||
6966 | if (of_property_read_u32(port_node, "port-id", &id)) { | |
6967 | err = -EINVAL; | |
6968 | dev_err(&pdev->dev, "missing port-id value\n"); | |
6969 | goto err_free_netdev; | |
6970 | } | |
6971 | ||
6972 | dev->tx_queue_len = MVPP2_MAX_TXD; | |
6973 | dev->watchdog_timeo = 5 * HZ; | |
6974 | dev->netdev_ops = &mvpp2_netdev_ops; | |
6975 | dev->ethtool_ops = &mvpp2_eth_tool_ops; | |
6976 | ||
6977 | port = netdev_priv(dev); | |
591f4cfa | 6978 | port->dev = dev; |
09f83975 TP |
6979 | port->ntxqs = ntxqs; |
6980 | port->nrxqs = nrxqs; | |
213f428f TP |
6981 | port->priv = priv; |
6982 | port->has_tx_irqs = has_tx_irqs; | |
3f518509 | 6983 | |
591f4cfa TP |
6984 | err = mvpp2_queue_vectors_init(port, port_node); |
6985 | if (err) | |
3f518509 | 6986 | goto err_free_netdev; |
3f518509 MW |
6987 | |
6988 | if (of_property_read_bool(port_node, "marvell,loopback")) | |
6989 | port->flags |= MVPP2_F_LOOPBACK; | |
6990 | ||
3f518509 | 6991 | port->id = id; |
59b9a31e | 6992 | if (priv->hw_version == MVPP21) |
09f83975 | 6993 | port->first_rxq = port->id * port->nrxqs; |
59b9a31e TP |
6994 | else |
6995 | port->first_rxq = port->id * priv->max_port_rxqs; | |
6996 | ||
3f518509 MW |
6997 | port->phy_node = phy_node; |
6998 | port->phy_interface = phy_mode; | |
6999 | ||
a786841d TP |
7000 | if (priv->hw_version == MVPP21) { |
7001 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); | |
7002 | port->base = devm_ioremap_resource(&pdev->dev, res); | |
7003 | if (IS_ERR(port->base)) { | |
7004 | err = PTR_ERR(port->base); | |
591f4cfa | 7005 | goto err_deinit_qvecs; |
a786841d TP |
7006 | } |
7007 | } else { | |
7008 | if (of_property_read_u32(port_node, "gop-port-id", | |
7009 | &port->gop_id)) { | |
7010 | err = -EINVAL; | |
7011 | dev_err(&pdev->dev, "missing gop-port-id value\n"); | |
591f4cfa | 7012 | goto err_deinit_qvecs; |
a786841d TP |
7013 | } |
7014 | ||
7015 | port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); | |
3f518509 MW |
7016 | } |
7017 | ||
7018 | /* Alloc per-cpu stats */ | |
7019 | port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); | |
7020 | if (!port->stats) { | |
7021 | err = -ENOMEM; | |
591f4cfa | 7022 | goto err_deinit_qvecs; |
3f518509 MW |
7023 | } |
7024 | ||
7025 | dt_mac_addr = of_get_mac_address(port_node); | |
7026 | if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) { | |
7027 | mac_from = "device tree"; | |
7028 | ether_addr_copy(dev->dev_addr, dt_mac_addr); | |
7029 | } else { | |
26975821 TP |
7030 | if (priv->hw_version == MVPP21) |
7031 | mvpp21_get_mac_address(port, hw_mac_addr); | |
3f518509 MW |
7032 | if (is_valid_ether_addr(hw_mac_addr)) { |
7033 | mac_from = "hardware"; | |
7034 | ether_addr_copy(dev->dev_addr, hw_mac_addr); | |
7035 | } else { | |
7036 | mac_from = "random"; | |
7037 | eth_hw_addr_random(dev); | |
7038 | } | |
7039 | } | |
7040 | ||
7041 | port->tx_ring_size = MVPP2_MAX_TXD; | |
7042 | port->rx_ring_size = MVPP2_MAX_RXD; | |
3f518509 MW |
7043 | SET_NETDEV_DEV(dev, &pdev->dev); |
7044 | ||
7045 | err = mvpp2_port_init(port); | |
7046 | if (err < 0) { | |
7047 | dev_err(&pdev->dev, "failed to init port %d\n", id); | |
7048 | goto err_free_stats; | |
7049 | } | |
26975821 | 7050 | |
26975821 TP |
7051 | mvpp2_port_periodic_xon_disable(port); |
7052 | ||
7053 | if (priv->hw_version == MVPP21) | |
7054 | mvpp2_port_fc_adv_enable(port); | |
7055 | ||
7056 | mvpp2_port_reset(port); | |
3f518509 | 7057 | |
edc660fa MW |
7058 | port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); |
7059 | if (!port->pcpu) { | |
7060 | err = -ENOMEM; | |
7061 | goto err_free_txq_pcpu; | |
7062 | } | |
7063 | ||
213f428f TP |
7064 | if (!port->has_tx_irqs) { |
7065 | for_each_present_cpu(cpu) { | |
7066 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 7067 | |
213f428f TP |
7068 | hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, |
7069 | HRTIMER_MODE_REL_PINNED); | |
7070 | port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; | |
7071 | port_pcpu->timer_scheduled = false; | |
edc660fa | 7072 | |
213f428f TP |
7073 | tasklet_init(&port_pcpu->tx_done_tasklet, |
7074 | mvpp2_tx_proc_cb, | |
7075 | (unsigned long)dev); | |
7076 | } | |
edc660fa MW |
7077 | } |
7078 | ||
3f518509 MW |
7079 | features = NETIF_F_SG | NETIF_F_IP_CSUM; |
7080 | dev->features = features | NETIF_F_RXCSUM; | |
7081 | dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO; | |
7082 | dev->vlan_features |= features; | |
7083 | ||
5777987e JW |
7084 | /* MTU range: 68 - 9676 */ |
7085 | dev->min_mtu = ETH_MIN_MTU; | |
7086 | /* 9676 == 9700 - 20 and rounding to 8 */ | |
7087 | dev->max_mtu = 9676; | |
7088 | ||
3f518509 MW |
7089 | err = register_netdev(dev); |
7090 | if (err < 0) { | |
7091 | dev_err(&pdev->dev, "failed to register netdev\n"); | |
edc660fa | 7092 | goto err_free_port_pcpu; |
3f518509 MW |
7093 | } |
7094 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); | |
7095 | ||
3f518509 MW |
7096 | priv->port_list[id] = port; |
7097 | return 0; | |
7098 | ||
edc660fa MW |
7099 | err_free_port_pcpu: |
7100 | free_percpu(port->pcpu); | |
3f518509 | 7101 | err_free_txq_pcpu: |
09f83975 | 7102 | for (i = 0; i < port->ntxqs; i++) |
3f518509 MW |
7103 | free_percpu(port->txqs[i]->pcpu); |
7104 | err_free_stats: | |
7105 | free_percpu(port->stats); | |
591f4cfa TP |
7106 | err_deinit_qvecs: |
7107 | mvpp2_queue_vectors_deinit(port); | |
3f518509 | 7108 | err_free_netdev: |
ccb80393 | 7109 | of_node_put(phy_node); |
3f518509 MW |
7110 | free_netdev(dev); |
7111 | return err; | |
7112 | } | |
7113 | ||
7114 | /* Ports removal routine */ | |
7115 | static void mvpp2_port_remove(struct mvpp2_port *port) | |
7116 | { | |
7117 | int i; | |
7118 | ||
7119 | unregister_netdev(port->dev); | |
ccb80393 | 7120 | of_node_put(port->phy_node); |
edc660fa | 7121 | free_percpu(port->pcpu); |
3f518509 | 7122 | free_percpu(port->stats); |
09f83975 | 7123 | for (i = 0; i < port->ntxqs; i++) |
3f518509 | 7124 | free_percpu(port->txqs[i]->pcpu); |
591f4cfa | 7125 | mvpp2_queue_vectors_deinit(port); |
3f518509 MW |
7126 | free_netdev(port->dev); |
7127 | } | |
7128 | ||
7129 | /* Initialize decoding windows */ | |
7130 | static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, | |
7131 | struct mvpp2 *priv) | |
7132 | { | |
7133 | u32 win_enable; | |
7134 | int i; | |
7135 | ||
7136 | for (i = 0; i < 6; i++) { | |
7137 | mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); | |
7138 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); | |
7139 | ||
7140 | if (i < 4) | |
7141 | mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); | |
7142 | } | |
7143 | ||
7144 | win_enable = 0; | |
7145 | ||
7146 | for (i = 0; i < dram->num_cs; i++) { | |
7147 | const struct mbus_dram_window *cs = dram->cs + i; | |
7148 | ||
7149 | mvpp2_write(priv, MVPP2_WIN_BASE(i), | |
7150 | (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | | |
7151 | dram->mbus_dram_target_id); | |
7152 | ||
7153 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), | |
7154 | (cs->size - 1) & 0xffff0000); | |
7155 | ||
7156 | win_enable |= (1 << i); | |
7157 | } | |
7158 | ||
7159 | mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); | |
7160 | } | |
7161 | ||
7162 | /* Initialize Rx FIFO's */ | |
7163 | static void mvpp2_rx_fifo_init(struct mvpp2 *priv) | |
7164 | { | |
7165 | int port; | |
7166 | ||
7167 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
7168 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), | |
7169 | MVPP2_RX_FIFO_PORT_DATA_SIZE); | |
7170 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), | |
7171 | MVPP2_RX_FIFO_PORT_ATTR_SIZE); | |
7172 | } | |
7173 | ||
7174 | mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, | |
7175 | MVPP2_RX_FIFO_PORT_MIN_PKT); | |
7176 | mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); | |
7177 | } | |
7178 | ||
6763ce31 TP |
7179 | static void mvpp2_axi_init(struct mvpp2 *priv) |
7180 | { | |
7181 | u32 val, rdval, wrval; | |
7182 | ||
7183 | mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); | |
7184 | ||
7185 | /* AXI Bridge Configuration */ | |
7186 | ||
7187 | rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
7188 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
7189 | rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7190 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
7191 | ||
7192 | wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
7193 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
7194 | wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7195 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
7196 | ||
7197 | /* BM */ | |
7198 | mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); | |
7199 | mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); | |
7200 | ||
7201 | /* Descriptors */ | |
7202 | mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); | |
7203 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); | |
7204 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); | |
7205 | mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); | |
7206 | ||
7207 | /* Buffer Data */ | |
7208 | mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); | |
7209 | mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); | |
7210 | ||
7211 | val = MVPP22_AXI_CODE_CACHE_NON_CACHE | |
7212 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
7213 | val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM | |
7214 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
7215 | mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); | |
7216 | mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); | |
7217 | ||
7218 | val = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
7219 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
7220 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7221 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
7222 | ||
7223 | mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); | |
7224 | ||
7225 | val = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
7226 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
7227 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
7228 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
7229 | ||
7230 | mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); | |
7231 | } | |
7232 | ||
3f518509 MW |
7233 | /* Initialize network controller common part HW */ |
7234 | static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) | |
7235 | { | |
7236 | const struct mbus_dram_target_info *dram_target_info; | |
7237 | int err, i; | |
08a23755 | 7238 | u32 val; |
3f518509 | 7239 | |
3f518509 MW |
7240 | /* MBUS windows configuration */ |
7241 | dram_target_info = mv_mbus_dram_info(); | |
7242 | if (dram_target_info) | |
7243 | mvpp2_conf_mbus_windows(dram_target_info, priv); | |
7244 | ||
6763ce31 TP |
7245 | if (priv->hw_version == MVPP22) |
7246 | mvpp2_axi_init(priv); | |
7247 | ||
08a23755 | 7248 | /* Disable HW PHY polling */ |
26975821 TP |
7249 | if (priv->hw_version == MVPP21) { |
7250 | val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
7251 | val |= MVPP2_PHY_AN_STOP_SMI0_MASK; | |
7252 | writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
7253 | } else { | |
7254 | val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
7255 | val &= ~MVPP22_SMI_POLLING_EN; | |
7256 | writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
7257 | } | |
08a23755 | 7258 | |
3f518509 MW |
7259 | /* Allocate and initialize aggregated TXQs */ |
7260 | priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), | |
d7ce3cec | 7261 | sizeof(*priv->aggr_txqs), |
3f518509 MW |
7262 | GFP_KERNEL); |
7263 | if (!priv->aggr_txqs) | |
7264 | return -ENOMEM; | |
7265 | ||
7266 | for_each_present_cpu(i) { | |
7267 | priv->aggr_txqs[i].id = i; | |
7268 | priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; | |
7269 | err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], | |
7270 | MVPP2_AGGR_TXQ_SIZE, i, priv); | |
7271 | if (err < 0) | |
7272 | return err; | |
7273 | } | |
7274 | ||
7275 | /* Rx Fifo Init */ | |
7276 | mvpp2_rx_fifo_init(priv); | |
7277 | ||
26975821 TP |
7278 | if (priv->hw_version == MVPP21) |
7279 | writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, | |
7280 | priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); | |
3f518509 MW |
7281 | |
7282 | /* Allow cache snoop when transmiting packets */ | |
7283 | mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); | |
7284 | ||
7285 | /* Buffer Manager initialization */ | |
7286 | err = mvpp2_bm_init(pdev, priv); | |
7287 | if (err < 0) | |
7288 | return err; | |
7289 | ||
7290 | /* Parser default initialization */ | |
7291 | err = mvpp2_prs_default_init(pdev, priv); | |
7292 | if (err < 0) | |
7293 | return err; | |
7294 | ||
7295 | /* Classifier default initialization */ | |
7296 | mvpp2_cls_init(priv); | |
7297 | ||
7298 | return 0; | |
7299 | } | |
7300 | ||
7301 | static int mvpp2_probe(struct platform_device *pdev) | |
7302 | { | |
7303 | struct device_node *dn = pdev->dev.of_node; | |
7304 | struct device_node *port_node; | |
7305 | struct mvpp2 *priv; | |
7306 | struct resource *res; | |
a786841d | 7307 | void __iomem *base; |
df089aa0 | 7308 | int port_count, i; |
3f518509 MW |
7309 | int err; |
7310 | ||
0b92e594 | 7311 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
3f518509 MW |
7312 | if (!priv) |
7313 | return -ENOMEM; | |
7314 | ||
faca9247 TP |
7315 | priv->hw_version = |
7316 | (unsigned long)of_device_get_match_data(&pdev->dev); | |
7317 | ||
3f518509 | 7318 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a786841d TP |
7319 | base = devm_ioremap_resource(&pdev->dev, res); |
7320 | if (IS_ERR(base)) | |
7321 | return PTR_ERR(base); | |
7322 | ||
7323 | if (priv->hw_version == MVPP21) { | |
7324 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
7325 | priv->lms_base = devm_ioremap_resource(&pdev->dev, res); | |
7326 | if (IS_ERR(priv->lms_base)) | |
7327 | return PTR_ERR(priv->lms_base); | |
7328 | } else { | |
7329 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
7330 | priv->iface_base = devm_ioremap_resource(&pdev->dev, res); | |
7331 | if (IS_ERR(priv->iface_base)) | |
7332 | return PTR_ERR(priv->iface_base); | |
7333 | } | |
7334 | ||
df089aa0 | 7335 | for (i = 0; i < MVPP2_MAX_THREADS; i++) { |
a786841d TP |
7336 | u32 addr_space_sz; |
7337 | ||
7338 | addr_space_sz = (priv->hw_version == MVPP21 ? | |
7339 | MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); | |
df089aa0 | 7340 | priv->swth_base[i] = base + i * addr_space_sz; |
a786841d | 7341 | } |
3f518509 | 7342 | |
59b9a31e TP |
7343 | if (priv->hw_version == MVPP21) |
7344 | priv->max_port_rxqs = 8; | |
7345 | else | |
7346 | priv->max_port_rxqs = 32; | |
7347 | ||
3f518509 MW |
7348 | priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); |
7349 | if (IS_ERR(priv->pp_clk)) | |
7350 | return PTR_ERR(priv->pp_clk); | |
7351 | err = clk_prepare_enable(priv->pp_clk); | |
7352 | if (err < 0) | |
7353 | return err; | |
7354 | ||
7355 | priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); | |
7356 | if (IS_ERR(priv->gop_clk)) { | |
7357 | err = PTR_ERR(priv->gop_clk); | |
7358 | goto err_pp_clk; | |
7359 | } | |
7360 | err = clk_prepare_enable(priv->gop_clk); | |
7361 | if (err < 0) | |
7362 | goto err_pp_clk; | |
7363 | ||
fceb55d4 TP |
7364 | if (priv->hw_version == MVPP22) { |
7365 | priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); | |
7366 | if (IS_ERR(priv->mg_clk)) { | |
7367 | err = PTR_ERR(priv->mg_clk); | |
7368 | goto err_gop_clk; | |
7369 | } | |
7370 | ||
7371 | err = clk_prepare_enable(priv->mg_clk); | |
7372 | if (err < 0) | |
7373 | goto err_gop_clk; | |
7374 | } | |
7375 | ||
3f518509 MW |
7376 | /* Get system's tclk rate */ |
7377 | priv->tclk = clk_get_rate(priv->pp_clk); | |
7378 | ||
2067e0a1 TP |
7379 | if (priv->hw_version == MVPP22) { |
7380 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); | |
7381 | if (err) | |
7382 | goto err_mg_clk; | |
7383 | /* Sadly, the BM pools all share the same register to | |
7384 | * store the high 32 bits of their address. So they | |
7385 | * must all have the same high 32 bits, which forces | |
7386 | * us to restrict coherent memory to DMA_BIT_MASK(32). | |
7387 | */ | |
7388 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
7389 | if (err) | |
7390 | goto err_mg_clk; | |
7391 | } | |
7392 | ||
3f518509 MW |
7393 | /* Initialize network controller */ |
7394 | err = mvpp2_init(pdev, priv); | |
7395 | if (err < 0) { | |
7396 | dev_err(&pdev->dev, "failed to initialize controller\n"); | |
fceb55d4 | 7397 | goto err_mg_clk; |
3f518509 MW |
7398 | } |
7399 | ||
7400 | port_count = of_get_available_child_count(dn); | |
7401 | if (port_count == 0) { | |
7402 | dev_err(&pdev->dev, "no ports enabled\n"); | |
575a1935 | 7403 | err = -ENODEV; |
fceb55d4 | 7404 | goto err_mg_clk; |
3f518509 MW |
7405 | } |
7406 | ||
7407 | priv->port_list = devm_kcalloc(&pdev->dev, port_count, | |
0b92e594 ME |
7408 | sizeof(*priv->port_list), |
7409 | GFP_KERNEL); | |
3f518509 MW |
7410 | if (!priv->port_list) { |
7411 | err = -ENOMEM; | |
fceb55d4 | 7412 | goto err_mg_clk; |
3f518509 MW |
7413 | } |
7414 | ||
7415 | /* Initialize ports */ | |
3f518509 | 7416 | for_each_available_child_of_node(dn, port_node) { |
59b9a31e | 7417 | err = mvpp2_port_probe(pdev, port_node, priv); |
3f518509 | 7418 | if (err < 0) |
fceb55d4 | 7419 | goto err_mg_clk; |
3f518509 MW |
7420 | } |
7421 | ||
7422 | platform_set_drvdata(pdev, priv); | |
7423 | return 0; | |
7424 | ||
fceb55d4 TP |
7425 | err_mg_clk: |
7426 | if (priv->hw_version == MVPP22) | |
7427 | clk_disable_unprepare(priv->mg_clk); | |
3f518509 MW |
7428 | err_gop_clk: |
7429 | clk_disable_unprepare(priv->gop_clk); | |
7430 | err_pp_clk: | |
7431 | clk_disable_unprepare(priv->pp_clk); | |
7432 | return err; | |
7433 | } | |
7434 | ||
7435 | static int mvpp2_remove(struct platform_device *pdev) | |
7436 | { | |
7437 | struct mvpp2 *priv = platform_get_drvdata(pdev); | |
7438 | struct device_node *dn = pdev->dev.of_node; | |
7439 | struct device_node *port_node; | |
7440 | int i = 0; | |
7441 | ||
7442 | for_each_available_child_of_node(dn, port_node) { | |
7443 | if (priv->port_list[i]) | |
7444 | mvpp2_port_remove(priv->port_list[i]); | |
7445 | i++; | |
7446 | } | |
7447 | ||
7448 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
7449 | struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; | |
7450 | ||
7451 | mvpp2_bm_pool_destroy(pdev, priv, bm_pool); | |
7452 | } | |
7453 | ||
7454 | for_each_present_cpu(i) { | |
7455 | struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; | |
7456 | ||
7457 | dma_free_coherent(&pdev->dev, | |
7458 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, | |
7459 | aggr_txq->descs, | |
20396136 | 7460 | aggr_txq->descs_dma); |
3f518509 MW |
7461 | } |
7462 | ||
fceb55d4 | 7463 | clk_disable_unprepare(priv->mg_clk); |
3f518509 MW |
7464 | clk_disable_unprepare(priv->pp_clk); |
7465 | clk_disable_unprepare(priv->gop_clk); | |
7466 | ||
7467 | return 0; | |
7468 | } | |
7469 | ||
7470 | static const struct of_device_id mvpp2_match[] = { | |
faca9247 TP |
7471 | { |
7472 | .compatible = "marvell,armada-375-pp2", | |
7473 | .data = (void *)MVPP21, | |
7474 | }, | |
fc5e1550 TP |
7475 | { |
7476 | .compatible = "marvell,armada-7k-pp22", | |
7477 | .data = (void *)MVPP22, | |
7478 | }, | |
3f518509 MW |
7479 | { } |
7480 | }; | |
7481 | MODULE_DEVICE_TABLE(of, mvpp2_match); | |
7482 | ||
7483 | static struct platform_driver mvpp2_driver = { | |
7484 | .probe = mvpp2_probe, | |
7485 | .remove = mvpp2_remove, | |
7486 | .driver = { | |
7487 | .name = MVPP2_DRIVER_NAME, | |
7488 | .of_match_table = mvpp2_match, | |
7489 | }, | |
7490 | }; | |
7491 | ||
7492 | module_platform_driver(mvpp2_driver); | |
7493 | ||
7494 | MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); | |
7495 | MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); | |
c634099d | 7496 | MODULE_LICENSE("GPL v2"); |