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Commit | Line | Data |
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3f518509 MW |
1 | /* |
2 | * Driver for Marvell PPv2 network controller for Armada 375 SoC. | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * | |
6 | * Marcin Wojtas <mw@semihalf.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
a75edc7c | 13 | #include <linux/acpi.h> |
3f518509 MW |
14 | #include <linux/kernel.h> |
15 | #include <linux/netdevice.h> | |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/skbuff.h> | |
19 | #include <linux/inetdevice.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/module.h> | |
f84bf386 | 22 | #include <linux/mfd/syscon.h> |
3f518509 MW |
23 | #include <linux/interrupt.h> |
24 | #include <linux/cpumask.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/of_mdio.h> | |
28 | #include <linux/of_net.h> | |
29 | #include <linux/of_address.h> | |
faca9247 | 30 | #include <linux/of_device.h> |
3f518509 | 31 | #include <linux/phy.h> |
4bb04326 | 32 | #include <linux/phylink.h> |
542897d9 | 33 | #include <linux/phy/phy.h> |
3f518509 | 34 | #include <linux/clk.h> |
edc660fa MW |
35 | #include <linux/hrtimer.h> |
36 | #include <linux/ktime.h> | |
f84bf386 | 37 | #include <linux/regmap.h> |
3f518509 MW |
38 | #include <uapi/linux/ppp_defs.h> |
39 | #include <net/ip.h> | |
40 | #include <net/ipv6.h> | |
186cd4d4 | 41 | #include <net/tso.h> |
3f518509 | 42 | |
7c10f974 | 43 | /* Fifo Registers */ |
3f518509 MW |
44 | #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) |
45 | #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) | |
46 | #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 | |
47 | #define MVPP2_RX_FIFO_INIT_REG 0x64 | |
93ff130f | 48 | #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) |
7c10f974 | 49 | #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) |
3f518509 MW |
50 | |
51 | /* RX DMA Top Registers */ | |
52 | #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) | |
53 | #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) | |
54 | #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) | |
55 | #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) | |
56 | #define MVPP2_POOL_BUF_SIZE_OFFSET 5 | |
57 | #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) | |
58 | #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff | |
59 | #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) | |
60 | #define MVPP2_RXQ_POOL_SHORT_OFFS 20 | |
5eac892a TP |
61 | #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 |
62 | #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 | |
3f518509 | 63 | #define MVPP2_RXQ_POOL_LONG_OFFS 24 |
5eac892a TP |
64 | #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 |
65 | #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 | |
3f518509 MW |
66 | #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 |
67 | #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 | |
68 | #define MVPP2_RXQ_DISABLE_MASK BIT(31) | |
69 | ||
56beda3d MC |
70 | /* Top Registers */ |
71 | #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) | |
72 | #define MVPP2_DSA_EXTENDED BIT(5) | |
73 | ||
3f518509 MW |
74 | /* Parser Registers */ |
75 | #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 | |
76 | #define MVPP2_PRS_PORT_LU_MAX 0xf | |
77 | #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) | |
78 | #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) | |
79 | #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) | |
80 | #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) | |
81 | #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
82 | #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) | |
83 | #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) | |
84 | #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) | |
85 | #define MVPP2_PRS_TCAM_IDX_REG 0x1100 | |
86 | #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) | |
87 | #define MVPP2_PRS_TCAM_INV_MASK BIT(31) | |
88 | #define MVPP2_PRS_SRAM_IDX_REG 0x1200 | |
89 | #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) | |
90 | #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 | |
91 | #define MVPP2_PRS_TCAM_EN_MASK BIT(0) | |
92 | ||
1d7d15d7 AT |
93 | /* RSS Registers */ |
94 | #define MVPP22_RSS_INDEX 0x1500 | |
8a7b741e | 95 | #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) |
1d7d15d7 AT |
96 | #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) |
97 | #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) | |
98 | #define MVPP22_RSS_TABLE_ENTRY 0x1508 | |
99 | #define MVPP22_RSS_TABLE 0x1510 | |
100 | #define MVPP22_RSS_TABLE_POINTER(p) (p) | |
101 | #define MVPP22_RSS_WIDTH 0x150c | |
102 | ||
3f518509 MW |
103 | /* Classifier Registers */ |
104 | #define MVPP2_CLS_MODE_REG 0x1800 | |
105 | #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) | |
106 | #define MVPP2_CLS_PORT_WAY_REG 0x1810 | |
107 | #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) | |
108 | #define MVPP2_CLS_LKP_INDEX_REG 0x1814 | |
109 | #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 | |
110 | #define MVPP2_CLS_LKP_TBL_REG 0x1818 | |
111 | #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff | |
112 | #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) | |
113 | #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 | |
114 | #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 | |
115 | #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 | |
116 | #define MVPP2_CLS_FLOW_TBL2_REG 0x182c | |
117 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) | |
118 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 | |
119 | #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 | |
120 | #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) | |
121 | #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 | |
122 | #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) | |
123 | ||
124 | /* Descriptor Manager Top Registers */ | |
125 | #define MVPP2_RXQ_NUM_REG 0x2040 | |
126 | #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 | |
b02f31fb | 127 | #define MVPP22_DESC_ADDR_OFFS 8 |
3f518509 MW |
128 | #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 |
129 | #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 | |
130 | #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) | |
131 | #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 | |
132 | #define MVPP2_RXQ_NUM_NEW_OFFSET 16 | |
133 | #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) | |
134 | #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff | |
135 | #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 | |
136 | #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 | |
137 | #define MVPP2_RXQ_THRESH_REG 0x204c | |
138 | #define MVPP2_OCCUPIED_THRESH_OFFSET 0 | |
139 | #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff | |
140 | #define MVPP2_RXQ_INDEX_REG 0x2050 | |
141 | #define MVPP2_TXQ_NUM_REG 0x2080 | |
142 | #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 | |
143 | #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 | |
144 | #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 | |
213f428f TP |
145 | #define MVPP2_TXQ_THRESH_REG 0x2094 |
146 | #define MVPP2_TXQ_THRESH_OFFSET 16 | |
147 | #define MVPP2_TXQ_THRESH_MASK 0x3fff | |
3f518509 | 148 | #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 |
3f518509 MW |
149 | #define MVPP2_TXQ_INDEX_REG 0x2098 |
150 | #define MVPP2_TXQ_PREF_BUF_REG 0x209c | |
151 | #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) | |
152 | #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) | |
153 | #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) | |
154 | #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) | |
155 | #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) | |
156 | #define MVPP2_TXQ_PENDING_REG 0x20a0 | |
157 | #define MVPP2_TXQ_PENDING_MASK 0x3fff | |
158 | #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 | |
159 | #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) | |
160 | #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 | |
161 | #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 | |
162 | #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 | |
163 | #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 | |
164 | #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 | |
165 | #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff | |
166 | #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 | |
167 | #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 | |
168 | #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) | |
b02f31fb | 169 | #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 |
3f518509 MW |
170 | #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) |
171 | #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 | |
172 | #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) | |
173 | #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff | |
174 | #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) | |
175 | ||
176 | /* MBUS bridge registers */ | |
177 | #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) | |
178 | #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) | |
179 | #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) | |
180 | #define MVPP2_BASE_ADDR_ENABLE 0x4060 | |
181 | ||
6763ce31 TP |
182 | /* AXI Bridge Registers */ |
183 | #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 | |
184 | #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 | |
185 | #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 | |
186 | #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 | |
187 | #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 | |
188 | #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c | |
189 | #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 | |
190 | #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 | |
191 | #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 | |
192 | #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 | |
193 | #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 | |
194 | #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 | |
195 | ||
196 | /* Values for AXI Bridge registers */ | |
197 | #define MVPP22_AXI_ATTR_CACHE_OFFS 0 | |
198 | #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 | |
199 | ||
200 | #define MVPP22_AXI_CODE_CACHE_OFFS 0 | |
201 | #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 | |
202 | ||
203 | #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 | |
204 | #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 | |
205 | #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb | |
206 | ||
207 | #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 | |
208 | #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 | |
209 | ||
3f518509 | 210 | /* Interrupt Cause and Mask registers */ |
213f428f TP |
211 | #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) |
212 | #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 | |
213 | ||
3f518509 | 214 | #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) |
ab42676a | 215 | #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 |
eb1e93a1 | 216 | #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) |
a73fef10 | 217 | |
81b6630f | 218 | #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 |
a73fef10 | 219 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf |
81b6630f AT |
220 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
221 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 | |
a73fef10 TP |
222 | |
223 | #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf | |
81b6630f | 224 | #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 |
a73fef10 | 225 | |
81b6630f AT |
226 | #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 |
227 | #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f | |
228 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 | |
229 | #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 | |
a73fef10 | 230 | |
3f518509 MW |
231 | #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) |
232 | #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) | |
233 | #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) | |
234 | #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) | |
235 | #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
236 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 | |
213f428f | 237 | #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 |
3f518509 MW |
238 | #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) |
239 | #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) | |
240 | #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) | |
241 | #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) | |
242 | #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) | |
243 | #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) | |
244 | #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) | |
245 | #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc | |
246 | #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff | |
247 | #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 | |
248 | #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) | |
249 | #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 | |
250 | ||
251 | /* Buffer Manager registers */ | |
252 | #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) | |
253 | #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 | |
254 | #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) | |
255 | #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 | |
256 | #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) | |
257 | #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 | |
258 | #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) | |
259 | #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 | |
260 | #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) | |
261 | #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) | |
262 | #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff | |
effbf5f5 | 263 | #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 |
3f518509 MW |
264 | #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) |
265 | #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) | |
266 | #define MVPP2_BM_START_MASK BIT(0) | |
267 | #define MVPP2_BM_STOP_MASK BIT(1) | |
268 | #define MVPP2_BM_STATE_MASK BIT(4) | |
269 | #define MVPP2_BM_LOW_THRESH_OFFS 8 | |
270 | #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 | |
271 | #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ | |
272 | MVPP2_BM_LOW_THRESH_OFFS) | |
273 | #define MVPP2_BM_HIGH_THRESH_OFFS 16 | |
274 | #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 | |
275 | #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ | |
276 | MVPP2_BM_HIGH_THRESH_OFFS) | |
277 | #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) | |
278 | #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) | |
279 | #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) | |
280 | #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) | |
281 | #define MVPP2_BM_BPPE_FULL_MASK BIT(3) | |
282 | #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) | |
283 | #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) | |
284 | #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) | |
285 | #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) | |
286 | #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 | |
d01524d8 TP |
287 | #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 |
288 | #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff | |
289 | #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 | |
290 | #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 | |
3f518509 MW |
291 | #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) |
292 | #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) | |
293 | #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) | |
294 | #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) | |
295 | #define MVPP2_BM_VIRT_RLS_REG 0x64c0 | |
d01524d8 TP |
296 | #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 |
297 | #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff | |
81b6630f | 298 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 |
d01524d8 | 299 | #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 |
3f518509 MW |
300 | |
301 | /* TX Scheduler registers */ | |
302 | #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 | |
303 | #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 | |
304 | #define MVPP2_TXP_SCHED_ENQ_MASK 0xff | |
305 | #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 | |
306 | #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 | |
307 | #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 | |
308 | #define MVPP2_TXP_SCHED_MTU_REG 0x801c | |
309 | #define MVPP2_TXP_MTU_MAX 0x7FFFF | |
310 | #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 | |
311 | #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff | |
312 | #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
313 | #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) | |
314 | #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 | |
315 | #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff | |
316 | #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) | |
317 | #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff | |
318 | #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 | |
319 | #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) | |
320 | #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) | |
321 | #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
322 | #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) | |
323 | #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff | |
324 | ||
325 | /* TX general registers */ | |
326 | #define MVPP2_TX_SNOOP_REG 0x8800 | |
327 | #define MVPP2_TX_PORT_FLUSH_REG 0x8810 | |
328 | #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) | |
329 | ||
330 | /* LMS registers */ | |
331 | #define MVPP2_SRC_ADDR_MIDDLE 0x24 | |
332 | #define MVPP2_SRC_ADDR_HIGH 0x28 | |
08a23755 MW |
333 | #define MVPP2_PHY_AN_CFG0_REG 0x34 |
334 | #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) | |
3f518509 | 335 | #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c |
31d7677b | 336 | #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 |
3f518509 MW |
337 | |
338 | /* Per-port registers */ | |
339 | #define MVPP2_GMAC_CTRL_0_REG 0x0 | |
81b6630f | 340 | #define MVPP2_GMAC_PORT_EN_MASK BIT(0) |
3919357f | 341 | #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) |
81b6630f AT |
342 | #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 |
343 | #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
344 | #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) | |
3f518509 | 345 | #define MVPP2_GMAC_CTRL_1_REG 0x4 |
81b6630f AT |
346 | #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) |
347 | #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) | |
348 | #define MVPP2_GMAC_PCS_LB_EN_BIT 6 | |
349 | #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) | |
350 | #define MVPP2_GMAC_SA_LOW_OFFS 7 | |
3f518509 | 351 | #define MVPP2_GMAC_CTRL_2_REG 0x8 |
81b6630f | 352 | #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) |
3919357f | 353 | #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) |
81b6630f | 354 | #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) |
c7dfc8c8 | 355 | #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) |
3919357f | 356 | #define MVPP2_GMAC_DISABLE_PADDING BIT(5) |
81b6630f | 357 | #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) |
3f518509 | 358 | #define MVPP2_GMAC_AUTONEG_CONFIG 0xc |
81b6630f AT |
359 | #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) |
360 | #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) | |
3919357f AT |
361 | #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) |
362 | #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) | |
4bb04326 | 363 | #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) |
81b6630f AT |
364 | #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) |
365 | #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) | |
366 | #define MVPP2_GMAC_AN_SPEED_EN BIT(7) | |
367 | #define MVPP2_GMAC_FC_ADV_EN BIT(9) | |
4bb04326 | 368 | #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) |
3919357f | 369 | #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) |
81b6630f AT |
370 | #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
371 | #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) | |
fd3651b2 AT |
372 | #define MVPP2_GMAC_STATUS0 0x10 |
373 | #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) | |
4bb04326 AT |
374 | #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) |
375 | #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) | |
376 | #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) | |
377 | #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6) | |
378 | #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7) | |
379 | #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) | |
3f518509 | 380 | #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c |
81b6630f AT |
381 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 |
382 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 | |
383 | #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ | |
3f518509 | 384 | MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) |
fd3651b2 AT |
385 | #define MVPP22_GMAC_INT_STAT 0x20 |
386 | #define MVPP22_GMAC_INT_STAT_LINK BIT(1) | |
387 | #define MVPP22_GMAC_INT_MASK 0x24 | |
388 | #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) | |
26975821 | 389 | #define MVPP22_GMAC_CTRL_4_REG 0x90 |
81b6630f | 390 | #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) |
4bb04326 AT |
391 | #define MVPP22_CTRL4_RX_FC_EN BIT(3) |
392 | #define MVPP22_CTRL4_TX_FC_EN BIT(4) | |
81b6630f | 393 | #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) |
1068ec79 | 394 | #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) |
81b6630f | 395 | #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) |
fd3651b2 AT |
396 | #define MVPP22_GMAC_INT_SUM_MASK 0xa4 |
397 | #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) | |
26975821 TP |
398 | |
399 | /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, | |
400 | * relative to port->base. | |
401 | */ | |
725757ae | 402 | #define MVPP22_XLG_CTRL0_REG 0x100 |
81b6630f AT |
403 | #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) |
404 | #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) | |
77321959 | 405 | #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) |
4bb04326 | 406 | #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) |
81b6630f | 407 | #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) |
76eb1b1d | 408 | #define MVPP22_XLG_CTRL1_REG 0x104 |
ec15ecde | 409 | #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 |
76eb1b1d | 410 | #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff |
fd3651b2 AT |
411 | #define MVPP22_XLG_STATUS 0x10c |
412 | #define MVPP22_XLG_STATUS_LINK_UP BIT(0) | |
413 | #define MVPP22_XLG_INT_STAT 0x114 | |
414 | #define MVPP22_XLG_INT_STAT_LINK BIT(1) | |
415 | #define MVPP22_XLG_INT_MASK 0x118 | |
416 | #define MVPP22_XLG_INT_MASK_LINK BIT(1) | |
26975821 | 417 | #define MVPP22_XLG_CTRL3_REG 0x11c |
81b6630f AT |
418 | #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) |
419 | #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) | |
420 | #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) | |
fd3651b2 AT |
421 | #define MVPP22_XLG_EXT_INT_MASK 0x15c |
422 | #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) | |
423 | #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) | |
77321959 AT |
424 | #define MVPP22_XLG_CTRL4_REG 0x184 |
425 | #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) | |
426 | #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) | |
427 | #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) | |
4bb04326 | 428 | #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) |
77321959 | 429 | |
26975821 TP |
430 | /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ |
431 | #define MVPP22_SMI_MISC_CFG_REG 0x1204 | |
81b6630f | 432 | #define MVPP22_SMI_POLLING_EN BIT(10) |
3f518509 | 433 | |
a786841d TP |
434 | #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) |
435 | ||
3f518509 MW |
436 | #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff |
437 | ||
438 | /* Descriptor ring Macros */ | |
439 | #define MVPP2_QUEUE_NEXT_DESC(q, index) \ | |
440 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
441 | ||
f84bf386 AT |
442 | /* XPCS registers. PPv2.2 only */ |
443 | #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) | |
444 | #define MVPP22_MPCS_CTRL 0x14 | |
445 | #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) | |
446 | #define MVPP22_MPCS_CLK_RESET 0x14c | |
447 | #define MAC_CLK_RESET_SD_TX BIT(0) | |
448 | #define MAC_CLK_RESET_SD_RX BIT(1) | |
449 | #define MAC_CLK_RESET_MAC BIT(2) | |
450 | #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) | |
451 | #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) | |
452 | ||
453 | /* XPCS registers. PPv2.2 only */ | |
454 | #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) | |
455 | #define MVPP22_XPCS_CFG0 0x0 | |
456 | #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) | |
457 | #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) | |
458 | ||
459 | /* System controller registers. Accessed through a regmap. */ | |
460 | #define GENCONF_SOFT_RESET1 0x1108 | |
461 | #define GENCONF_SOFT_RESET1_GOP BIT(6) | |
462 | #define GENCONF_PORT_CTRL0 0x1110 | |
463 | #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) | |
464 | #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) | |
465 | #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) | |
466 | #define GENCONF_PORT_CTRL1 0x1114 | |
467 | #define GENCONF_PORT_CTRL1_EN(p) BIT(p) | |
468 | #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) | |
469 | #define GENCONF_CTRL0 0x1120 | |
470 | #define GENCONF_CTRL0_PORT0_RGMII BIT(0) | |
471 | #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) | |
472 | #define GENCONF_CTRL0_PORT1_RGMII BIT(2) | |
473 | ||
3f518509 MW |
474 | /* Various constants */ |
475 | ||
476 | /* Coalescing */ | |
86162281 | 477 | #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 |
edc660fa | 478 | #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL |
213f428f | 479 | #define MVPP2_TXDONE_COAL_USEC 1000 |
3f518509 | 480 | #define MVPP2_RX_COAL_PKTS 32 |
86162281 | 481 | #define MVPP2_RX_COAL_USEC 64 |
3f518509 MW |
482 | |
483 | /* The two bytes Marvell header. Either contains a special value used | |
484 | * by Marvell switches when a specific hardware mode is enabled (not | |
485 | * supported by this driver) or is filled automatically by zeroes on | |
486 | * the RX side. Those two bytes being at the front of the Ethernet | |
487 | * header, they allow to have the IP header aligned on a 4 bytes | |
488 | * boundary automatically: the hardware skips those two bytes on its | |
489 | * own. | |
490 | */ | |
491 | #define MVPP2_MH_SIZE 2 | |
492 | #define MVPP2_ETH_TYPE_LEN 2 | |
493 | #define MVPP2_PPPOE_HDR_SIZE 8 | |
494 | #define MVPP2_VLAN_TAG_LEN 4 | |
56beda3d | 495 | #define MVPP2_VLAN_TAG_EDSA_LEN 8 |
3f518509 MW |
496 | |
497 | /* Lbtd 802.3 type */ | |
498 | #define MVPP2_IP_LBDT_TYPE 0xfffa | |
499 | ||
3f518509 MW |
500 | #define MVPP2_TX_CSUM_MAX_SIZE 9800 |
501 | ||
502 | /* Timeout constants */ | |
503 | #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 | |
504 | #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 | |
505 | ||
506 | #define MVPP2_TX_MTU_MAX 0x7ffff | |
507 | ||
508 | /* Maximum number of T-CONTs of PON port */ | |
509 | #define MVPP2_MAX_TCONT 16 | |
510 | ||
511 | /* Maximum number of supported ports */ | |
512 | #define MVPP2_MAX_PORTS 4 | |
513 | ||
514 | /* Maximum number of TXQs used by single port */ | |
515 | #define MVPP2_MAX_TXQ 8 | |
516 | ||
1d17db08 AT |
517 | /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO |
518 | * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), | |
519 | * multiply this value by two to count the maximum number of skb descs needed. | |
520 | */ | |
521 | #define MVPP2_MAX_TSO_SEGS 300 | |
522 | #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
523 | ||
3f518509 MW |
524 | /* Dfault number of RXQs in use */ |
525 | #define MVPP2_DEFAULT_RXQ 4 | |
526 | ||
3f518509 | 527 | /* Max number of Rx descriptors */ |
7cf87e4a YM |
528 | #define MVPP2_MAX_RXD_MAX 1024 |
529 | #define MVPP2_MAX_RXD_DFLT 128 | |
3f518509 MW |
530 | |
531 | /* Max number of Tx descriptors */ | |
7cf87e4a YM |
532 | #define MVPP2_MAX_TXD_MAX 2048 |
533 | #define MVPP2_MAX_TXD_DFLT 1024 | |
3f518509 MW |
534 | |
535 | /* Amount of Tx descriptors that can be reserved at once by CPU */ | |
536 | #define MVPP2_CPU_DESC_CHUNK 64 | |
537 | ||
538 | /* Max number of Tx descriptors in each aggregated queue */ | |
539 | #define MVPP2_AGGR_TXQ_SIZE 256 | |
540 | ||
541 | /* Descriptor aligned size */ | |
542 | #define MVPP2_DESC_ALIGNED_SIZE 32 | |
543 | ||
544 | /* Descriptor alignment mask */ | |
545 | #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) | |
546 | ||
547 | /* RX FIFO constants */ | |
2d1d7df8 AT |
548 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 |
549 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 | |
550 | #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 | |
551 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 | |
552 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 | |
553 | #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 | |
554 | #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 | |
3f518509 | 555 | |
7c10f974 AT |
556 | /* TX FIFO constants */ |
557 | #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa | |
558 | #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 | |
93ff130f YM |
559 | #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 |
560 | #define MVPP2_TX_FIFO_THRESHOLD_10KB \ | |
561 | (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) | |
562 | #define MVPP2_TX_FIFO_THRESHOLD_3KB \ | |
563 | (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) | |
7c10f974 | 564 | |
3f518509 MW |
565 | /* RX buffer constants */ |
566 | #define MVPP2_SKB_SHINFO_SIZE \ | |
567 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) | |
568 | ||
569 | #define MVPP2_RX_PKT_SIZE(mtu) \ | |
570 | ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ | |
4a0a12d2 | 571 | ETH_HLEN + ETH_FCS_LEN, cache_line_size()) |
3f518509 MW |
572 | |
573 | #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) | |
574 | #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) | |
575 | #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ | |
576 | ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) | |
577 | ||
578 | #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) | |
579 | ||
580 | /* IPv6 max L3 address size */ | |
581 | #define MVPP2_MAX_L3_ADDR_SIZE 16 | |
582 | ||
583 | /* Port flags */ | |
584 | #define MVPP2_F_LOOPBACK BIT(0) | |
585 | ||
586 | /* Marvell tag types */ | |
587 | enum mvpp2_tag_type { | |
588 | MVPP2_TAG_TYPE_NONE = 0, | |
589 | MVPP2_TAG_TYPE_MH = 1, | |
590 | MVPP2_TAG_TYPE_DSA = 2, | |
591 | MVPP2_TAG_TYPE_EDSA = 3, | |
592 | MVPP2_TAG_TYPE_VLAN = 4, | |
593 | MVPP2_TAG_TYPE_LAST = 5 | |
594 | }; | |
595 | ||
596 | /* Parser constants */ | |
597 | #define MVPP2_PRS_TCAM_SRAM_SIZE 256 | |
598 | #define MVPP2_PRS_TCAM_WORDS 6 | |
599 | #define MVPP2_PRS_SRAM_WORDS 4 | |
600 | #define MVPP2_PRS_FLOW_ID_SIZE 64 | |
601 | #define MVPP2_PRS_FLOW_ID_MASK 0x3f | |
602 | #define MVPP2_PRS_TCAM_ENTRY_INVALID 1 | |
603 | #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) | |
604 | #define MVPP2_PRS_IPV4_HEAD 0x40 | |
605 | #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 | |
606 | #define MVPP2_PRS_IPV4_MC 0xe0 | |
607 | #define MVPP2_PRS_IPV4_MC_MASK 0xf0 | |
608 | #define MVPP2_PRS_IPV4_BC_MASK 0xff | |
609 | #define MVPP2_PRS_IPV4_IHL 0x5 | |
610 | #define MVPP2_PRS_IPV4_IHL_MASK 0xf | |
611 | #define MVPP2_PRS_IPV6_MC 0xff | |
612 | #define MVPP2_PRS_IPV6_MC_MASK 0xff | |
613 | #define MVPP2_PRS_IPV6_HOP_MASK 0xff | |
614 | #define MVPP2_PRS_TCAM_PROTO_MASK 0xff | |
615 | #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f | |
616 | #define MVPP2_PRS_DBL_VLANS_MAX 100 | |
10fea26c MC |
617 | #define MVPP2_PRS_CAST_MASK BIT(0) |
618 | #define MVPP2_PRS_MCAST_VAL BIT(0) | |
619 | #define MVPP2_PRS_UCAST_VAL 0x0 | |
3f518509 MW |
620 | |
621 | /* Tcam structure: | |
622 | * - lookup ID - 4 bits | |
623 | * - port ID - 1 byte | |
624 | * - additional information - 1 byte | |
625 | * - header data - 8 bytes | |
626 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). | |
627 | */ | |
628 | #define MVPP2_PRS_AI_BITS 8 | |
629 | #define MVPP2_PRS_PORT_MASK 0xff | |
630 | #define MVPP2_PRS_LU_MASK 0xf | |
631 | #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \ | |
632 | (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) | |
633 | #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \ | |
634 | (((offs) * 2) - ((offs) % 2) + 2) | |
635 | #define MVPP2_PRS_TCAM_AI_BYTE 16 | |
636 | #define MVPP2_PRS_TCAM_PORT_BYTE 17 | |
637 | #define MVPP2_PRS_TCAM_LU_BYTE 20 | |
638 | #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) | |
639 | #define MVPP2_PRS_TCAM_INV_WORD 5 | |
56beda3d MC |
640 | |
641 | #define MVPP2_PRS_VID_TCAM_BYTE 2 | |
642 | ||
10fea26c MC |
643 | /* TCAM range for unicast and multicast filtering. We have 25 entries per port, |
644 | * with 4 dedicated to UC filtering and the rest to multicast filtering. | |
645 | * Additionnally we reserve one entry for the broadcast address, and one for | |
646 | * each port's own address. | |
647 | */ | |
648 | #define MVPP2_PRS_MAC_UC_MC_FILT_MAX 25 | |
649 | #define MVPP2_PRS_MAC_RANGE_SIZE 80 | |
650 | ||
651 | /* Number of entries per port dedicated to UC and MC filtering */ | |
652 | #define MVPP2_PRS_MAC_UC_FILT_MAX 4 | |
653 | #define MVPP2_PRS_MAC_MC_FILT_MAX (MVPP2_PRS_MAC_UC_MC_FILT_MAX - \ | |
654 | MVPP2_PRS_MAC_UC_FILT_MAX) | |
655 | ||
56beda3d MC |
656 | /* There is a TCAM range reserved for VLAN filtering entries, range size is 33 |
657 | * 10 VLAN ID filter entries per port | |
658 | * 1 default VLAN filter entry per port | |
659 | * It is assumed that there are 3 ports for filter, not including loopback port | |
660 | */ | |
661 | #define MVPP2_PRS_VLAN_FILT_MAX 11 | |
662 | #define MVPP2_PRS_VLAN_FILT_RANGE_SIZE 33 | |
663 | ||
664 | #define MVPP2_PRS_VLAN_FILT_MAX_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 2) | |
665 | #define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 1) | |
666 | ||
3f518509 MW |
667 | /* Tcam entries ID */ |
668 | #define MVPP2_PE_DROP_ALL 0 | |
669 | #define MVPP2_PE_FIRST_FREE_TID 1 | |
56beda3d | 670 | |
10fea26c MC |
671 | /* MAC filtering range */ |
672 | #define MVPP2_PE_MAC_RANGE_END (MVPP2_PE_VID_FILT_RANGE_START - 1) | |
673 | #define MVPP2_PE_MAC_RANGE_START (MVPP2_PE_MAC_RANGE_END - \ | |
674 | MVPP2_PRS_MAC_RANGE_SIZE + 1) | |
56beda3d MC |
675 | /* VLAN filtering range */ |
676 | #define MVPP2_PE_VID_FILT_RANGE_END (MVPP2_PRS_TCAM_SRAM_SIZE - 31) | |
677 | #define MVPP2_PE_VID_FILT_RANGE_START (MVPP2_PE_VID_FILT_RANGE_END - \ | |
678 | MVPP2_PRS_VLAN_FILT_RANGE_SIZE + 1) | |
982e0500 | 679 | #define MVPP2_PE_LAST_FREE_TID (MVPP2_PE_MAC_RANGE_START - 1) |
3f518509 | 680 | #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) |
10fea26c MC |
681 | #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 29) |
682 | #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) | |
683 | #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 27) | |
684 | #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 22) | |
685 | #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 21) | |
686 | #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 20) | |
687 | #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 19) | |
688 | #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) | |
689 | #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) | |
690 | #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) | |
691 | #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) | |
692 | #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) | |
693 | #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 13) | |
694 | #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 12) | |
695 | #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 11) | |
696 | #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 10) | |
697 | #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 9) | |
698 | #define MVPP2_PE_VID_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 8) | |
699 | #define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7) | |
700 | #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 6) | |
701 | #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 5) | |
702 | /* reserved */ | |
703 | #define MVPP2_PE_MAC_MC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 3) | |
704 | #define MVPP2_PE_MAC_UC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) | |
3f518509 MW |
705 | #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) |
706 | ||
56beda3d MC |
707 | #define MVPP2_PRS_VID_PORT_FIRST(port) (MVPP2_PE_VID_FILT_RANGE_START + \ |
708 | ((port) * MVPP2_PRS_VLAN_FILT_MAX)) | |
709 | #define MVPP2_PRS_VID_PORT_LAST(port) (MVPP2_PRS_VID_PORT_FIRST(port) \ | |
710 | + MVPP2_PRS_VLAN_FILT_MAX_ENTRY) | |
711 | /* Index of default vid filter for given port */ | |
712 | #define MVPP2_PRS_VID_PORT_DFLT(port) (MVPP2_PRS_VID_PORT_FIRST(port) \ | |
713 | + MVPP2_PRS_VLAN_FILT_DFLT_ENTRY) | |
714 | ||
3f518509 MW |
715 | /* Sram structure |
716 | * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). | |
717 | */ | |
718 | #define MVPP2_PRS_SRAM_RI_OFFS 0 | |
719 | #define MVPP2_PRS_SRAM_RI_WORD 0 | |
720 | #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 | |
721 | #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 | |
722 | #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 | |
723 | #define MVPP2_PRS_SRAM_SHIFT_OFFS 64 | |
724 | #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 | |
725 | #define MVPP2_PRS_SRAM_UDF_OFFS 73 | |
726 | #define MVPP2_PRS_SRAM_UDF_BITS 8 | |
727 | #define MVPP2_PRS_SRAM_UDF_MASK 0xff | |
728 | #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 | |
729 | #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 | |
730 | #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 | |
731 | #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 | |
732 | #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 | |
733 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 | |
734 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 | |
735 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 | |
736 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 | |
737 | #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 | |
738 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 | |
739 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 | |
740 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 | |
741 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 | |
742 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 | |
743 | #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 | |
744 | #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 | |
745 | #define MVPP2_PRS_SRAM_AI_OFFS 90 | |
746 | #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 | |
747 | #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 | |
748 | #define MVPP2_PRS_SRAM_AI_MASK 0xff | |
749 | #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 | |
750 | #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf | |
751 | #define MVPP2_PRS_SRAM_LU_DONE_BIT 110 | |
752 | #define MVPP2_PRS_SRAM_LU_GEN_BIT 111 | |
753 | ||
754 | /* Sram result info bits assignment */ | |
755 | #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 | |
756 | #define MVPP2_PRS_RI_DSA_MASK 0x2 | |
8138affc TP |
757 | #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) |
758 | #define MVPP2_PRS_RI_VLAN_NONE 0x0 | |
3f518509 MW |
759 | #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) |
760 | #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) | |
761 | #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) | |
762 | #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 | |
763 | #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) | |
8138affc TP |
764 | #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) |
765 | #define MVPP2_PRS_RI_L2_UCAST 0x0 | |
3f518509 MW |
766 | #define MVPP2_PRS_RI_L2_MCAST BIT(9) |
767 | #define MVPP2_PRS_RI_L2_BCAST BIT(10) | |
768 | #define MVPP2_PRS_RI_PPPOE_MASK 0x800 | |
8138affc TP |
769 | #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) |
770 | #define MVPP2_PRS_RI_L3_UN 0x0 | |
3f518509 MW |
771 | #define MVPP2_PRS_RI_L3_IP4 BIT(12) |
772 | #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) | |
773 | #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) | |
774 | #define MVPP2_PRS_RI_L3_IP6 BIT(14) | |
775 | #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) | |
776 | #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) | |
8138affc TP |
777 | #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) |
778 | #define MVPP2_PRS_RI_L3_UCAST 0x0 | |
3f518509 MW |
779 | #define MVPP2_PRS_RI_L3_MCAST BIT(15) |
780 | #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) | |
781 | #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 | |
aff3da39 | 782 | #define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17) |
3f518509 MW |
783 | #define MVPP2_PRS_RI_UDF3_MASK 0x300000 |
784 | #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) | |
785 | #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 | |
786 | #define MVPP2_PRS_RI_L4_TCP BIT(22) | |
787 | #define MVPP2_PRS_RI_L4_UDP BIT(23) | |
788 | #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) | |
789 | #define MVPP2_PRS_RI_UDF7_MASK 0x60000000 | |
790 | #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) | |
791 | #define MVPP2_PRS_RI_DROP_MASK 0x80000000 | |
792 | ||
793 | /* Sram additional info bits assignment */ | |
794 | #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) | |
795 | #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) | |
796 | #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) | |
797 | #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) | |
798 | #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) | |
799 | #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) | |
800 | #define MVPP2_PRS_SINGLE_VLAN_AI 0 | |
801 | #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) | |
56beda3d | 802 | #define MVPP2_PRS_EDSA_VID_AI_BIT BIT(0) |
3f518509 MW |
803 | |
804 | /* DSA/EDSA type */ | |
805 | #define MVPP2_PRS_TAGGED true | |
806 | #define MVPP2_PRS_UNTAGGED false | |
807 | #define MVPP2_PRS_EDSA true | |
808 | #define MVPP2_PRS_DSA false | |
809 | ||
810 | /* MAC entries, shadow udf */ | |
811 | enum mvpp2_prs_udf { | |
812 | MVPP2_PRS_UDF_MAC_DEF, | |
813 | MVPP2_PRS_UDF_MAC_RANGE, | |
814 | MVPP2_PRS_UDF_L2_DEF, | |
815 | MVPP2_PRS_UDF_L2_DEF_COPY, | |
816 | MVPP2_PRS_UDF_L2_USER, | |
817 | }; | |
818 | ||
819 | /* Lookup ID */ | |
820 | enum mvpp2_prs_lookup { | |
821 | MVPP2_PRS_LU_MH, | |
822 | MVPP2_PRS_LU_MAC, | |
823 | MVPP2_PRS_LU_DSA, | |
824 | MVPP2_PRS_LU_VLAN, | |
56beda3d | 825 | MVPP2_PRS_LU_VID, |
3f518509 MW |
826 | MVPP2_PRS_LU_L2, |
827 | MVPP2_PRS_LU_PPPOE, | |
828 | MVPP2_PRS_LU_IP4, | |
829 | MVPP2_PRS_LU_IP6, | |
830 | MVPP2_PRS_LU_FLOWS, | |
831 | MVPP2_PRS_LU_LAST, | |
832 | }; | |
833 | ||
10fea26c MC |
834 | /* L2 cast enum */ |
835 | enum mvpp2_prs_l2_cast { | |
836 | MVPP2_PRS_L2_UNI_CAST, | |
837 | MVPP2_PRS_L2_MULTI_CAST, | |
838 | }; | |
839 | ||
3f518509 MW |
840 | /* L3 cast enum */ |
841 | enum mvpp2_prs_l3_cast { | |
842 | MVPP2_PRS_L3_UNI_CAST, | |
843 | MVPP2_PRS_L3_MULTI_CAST, | |
844 | MVPP2_PRS_L3_BROAD_CAST | |
845 | }; | |
846 | ||
847 | /* Classifier constants */ | |
848 | #define MVPP2_CLS_FLOWS_TBL_SIZE 512 | |
849 | #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 | |
850 | #define MVPP2_CLS_LKP_TBL_SIZE 64 | |
1d7d15d7 AT |
851 | #define MVPP2_CLS_RX_QUEUES 256 |
852 | ||
853 | /* RSS constants */ | |
854 | #define MVPP22_RSS_TABLE_ENTRIES 32 | |
3f518509 MW |
855 | |
856 | /* BM constants */ | |
576193f2 | 857 | #define MVPP2_BM_JUMBO_BUF_NUM 512 |
3f518509 MW |
858 | #define MVPP2_BM_LONG_BUF_NUM 1024 |
859 | #define MVPP2_BM_SHORT_BUF_NUM 2048 | |
860 | #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) | |
861 | #define MVPP2_BM_POOL_PTR_ALIGN 128 | |
3f518509 MW |
862 | |
863 | /* BM cookie (32 bits) definition */ | |
864 | #define MVPP2_BM_COOKIE_POOL_OFFS 8 | |
865 | #define MVPP2_BM_COOKIE_CPU_OFFS 24 | |
866 | ||
01d04936 SC |
867 | #define MVPP2_BM_SHORT_FRAME_SIZE 512 |
868 | #define MVPP2_BM_LONG_FRAME_SIZE 2048 | |
576193f2 | 869 | #define MVPP2_BM_JUMBO_FRAME_SIZE 10240 |
3f518509 MW |
870 | /* BM short pool packet size |
871 | * These value assure that for SWF the total number | |
872 | * of bytes allocated for each buffer will be 512 | |
873 | */ | |
01d04936 SC |
874 | #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) |
875 | #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) | |
576193f2 | 876 | #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) |
3f518509 | 877 | |
a786841d TP |
878 | #define MVPP21_ADDR_SPACE_SZ 0 |
879 | #define MVPP22_ADDR_SPACE_SZ SZ_64K | |
880 | ||
df089aa0 | 881 | #define MVPP2_MAX_THREADS 8 |
591f4cfa | 882 | #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS |
a786841d | 883 | |
01d04936 SC |
884 | enum mvpp2_bm_pool_log_num { |
885 | MVPP2_BM_SHORT, | |
886 | MVPP2_BM_LONG, | |
576193f2 | 887 | MVPP2_BM_JUMBO, |
01d04936 | 888 | MVPP2_BM_POOLS_NUM |
3f518509 MW |
889 | }; |
890 | ||
01d04936 SC |
891 | static struct { |
892 | int pkt_size; | |
893 | int buf_num; | |
894 | } mvpp2_pools[MVPP2_BM_POOLS_NUM]; | |
895 | ||
118d6298 MR |
896 | /* GMAC MIB Counters register definitions */ |
897 | #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 | |
898 | #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 | |
899 | #define MVPP22_MIB_COUNTERS_OFFSET 0x0 | |
900 | #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 | |
901 | ||
902 | #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 | |
903 | #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 | |
904 | #define MVPP2_MIB_CRC_ERRORS_SENT 0xc | |
905 | #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 | |
906 | #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 | |
907 | #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c | |
908 | #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 | |
909 | #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 | |
910 | #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 | |
911 | #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c | |
912 | #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 | |
913 | #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 | |
914 | #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 | |
915 | #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 | |
916 | #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 | |
917 | #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c | |
918 | #define MVPP2_MIB_FC_SENT 0x54 | |
919 | #define MVPP2_MIB_FC_RCVD 0x58 | |
920 | #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c | |
921 | #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 | |
922 | #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 | |
923 | #define MVPP2_MIB_OVERSIZE_RCVD 0x68 | |
924 | #define MVPP2_MIB_JABBER_RCVD 0x6c | |
925 | #define MVPP2_MIB_MAC_RCV_ERROR 0x70 | |
926 | #define MVPP2_MIB_BAD_CRC_EVENT 0x74 | |
927 | #define MVPP2_MIB_COLLISION 0x78 | |
928 | #define MVPP2_MIB_LATE_COLLISION 0x7c | |
929 | ||
930 | #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) | |
931 | ||
da42bb27 MC |
932 | #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) |
933 | ||
3f518509 MW |
934 | /* Definitions */ |
935 | ||
936 | /* Shared Packet Processor resources */ | |
937 | struct mvpp2 { | |
938 | /* Shared registers' base addresses */ | |
3f518509 | 939 | void __iomem *lms_base; |
a786841d TP |
940 | void __iomem *iface_base; |
941 | ||
df089aa0 TP |
942 | /* On PPv2.2, each "software thread" can access the base |
943 | * register through a separate address space, each 64 KB apart | |
944 | * from each other. Typically, such address spaces will be | |
945 | * used per CPU. | |
a786841d | 946 | */ |
df089aa0 | 947 | void __iomem *swth_base[MVPP2_MAX_THREADS]; |
3f518509 | 948 | |
f84bf386 AT |
949 | /* On PPv2.2, some port control registers are located into the system |
950 | * controller space. These registers are accessible through a regmap. | |
951 | */ | |
952 | struct regmap *sysctrl_base; | |
953 | ||
3f518509 MW |
954 | /* Common clocks */ |
955 | struct clk *pp_clk; | |
956 | struct clk *gop_clk; | |
fceb55d4 | 957 | struct clk *mg_clk; |
9af771ce | 958 | struct clk *mg_core_clk; |
4792ea04 | 959 | struct clk *axi_clk; |
3f518509 MW |
960 | |
961 | /* List of pointers to port structures */ | |
118d6298 | 962 | int port_count; |
bf147153 | 963 | struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; |
3f518509 MW |
964 | |
965 | /* Aggregated TXQs */ | |
966 | struct mvpp2_tx_queue *aggr_txqs; | |
967 | ||
968 | /* BM pools */ | |
969 | struct mvpp2_bm_pool *bm_pools; | |
970 | ||
971 | /* PRS shadow table */ | |
972 | struct mvpp2_prs_shadow *prs_shadow; | |
973 | /* PRS auxiliary table for double vlan entries control */ | |
974 | bool *prs_double_vlans; | |
975 | ||
976 | /* Tclk value */ | |
977 | u32 tclk; | |
faca9247 TP |
978 | |
979 | /* HW version */ | |
980 | enum { MVPP21, MVPP22 } hw_version; | |
59b9a31e TP |
981 | |
982 | /* Maximum number of RXQs per port */ | |
983 | unsigned int max_port_rxqs; | |
118d6298 | 984 | |
e5c500eb | 985 | /* Workqueue to gather hardware statistics */ |
118d6298 MR |
986 | char queue_name[30]; |
987 | struct workqueue_struct *stats_queue; | |
3f518509 MW |
988 | }; |
989 | ||
990 | struct mvpp2_pcpu_stats { | |
991 | struct u64_stats_sync syncp; | |
992 | u64 rx_packets; | |
993 | u64 rx_bytes; | |
994 | u64 tx_packets; | |
995 | u64 tx_bytes; | |
996 | }; | |
997 | ||
edc660fa MW |
998 | /* Per-CPU port control */ |
999 | struct mvpp2_port_pcpu { | |
1000 | struct hrtimer tx_done_timer; | |
1001 | bool timer_scheduled; | |
1002 | /* Tasklet for egress finalization */ | |
1003 | struct tasklet_struct tx_done_tasklet; | |
1004 | }; | |
1005 | ||
591f4cfa TP |
1006 | struct mvpp2_queue_vector { |
1007 | int irq; | |
1008 | struct napi_struct napi; | |
1009 | enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; | |
1010 | int sw_thread_id; | |
1011 | u16 sw_thread_mask; | |
1012 | int first_rxq; | |
1013 | int nrxqs; | |
1014 | u32 pending_cause_rx; | |
1015 | struct mvpp2_port *port; | |
1016 | }; | |
1017 | ||
3f518509 MW |
1018 | struct mvpp2_port { |
1019 | u8 id; | |
1020 | ||
a786841d TP |
1021 | /* Index of the port from the "group of ports" complex point |
1022 | * of view | |
1023 | */ | |
1024 | int gop_id; | |
1025 | ||
fd3651b2 AT |
1026 | int link_irq; |
1027 | ||
3f518509 MW |
1028 | struct mvpp2 *priv; |
1029 | ||
24812221 MW |
1030 | /* Firmware node associated to the port */ |
1031 | struct fwnode_handle *fwnode; | |
1032 | ||
4bb04326 AT |
1033 | /* Is a PHY always connected to the port */ |
1034 | bool has_phy; | |
1035 | ||
3f518509 MW |
1036 | /* Per-port registers' base address */ |
1037 | void __iomem *base; | |
118d6298 | 1038 | void __iomem *stats_base; |
3f518509 MW |
1039 | |
1040 | struct mvpp2_rx_queue **rxqs; | |
09f83975 | 1041 | unsigned int nrxqs; |
3f518509 | 1042 | struct mvpp2_tx_queue **txqs; |
09f83975 | 1043 | unsigned int ntxqs; |
3f518509 MW |
1044 | struct net_device *dev; |
1045 | ||
1046 | int pkt_size; | |
1047 | ||
edc660fa MW |
1048 | /* Per-CPU port control */ |
1049 | struct mvpp2_port_pcpu __percpu *pcpu; | |
1050 | ||
3f518509 MW |
1051 | /* Flags */ |
1052 | unsigned long flags; | |
1053 | ||
1054 | u16 tx_ring_size; | |
1055 | u16 rx_ring_size; | |
1056 | struct mvpp2_pcpu_stats __percpu *stats; | |
118d6298 | 1057 | u64 *ethtool_stats; |
3f518509 | 1058 | |
e5c500eb MR |
1059 | /* Per-port work and its lock to gather hardware statistics */ |
1060 | struct mutex gather_stats_lock; | |
1061 | struct delayed_work stats_work; | |
1062 | ||
4bb04326 AT |
1063 | struct device_node *of_node; |
1064 | ||
3f518509 | 1065 | phy_interface_t phy_interface; |
4bb04326 | 1066 | struct phylink *phylink; |
542897d9 | 1067 | struct phy *comphy; |
3f518509 MW |
1068 | |
1069 | struct mvpp2_bm_pool *pool_long; | |
1070 | struct mvpp2_bm_pool *pool_short; | |
1071 | ||
1072 | /* Index of first port's physical RXQ */ | |
1073 | u8 first_rxq; | |
591f4cfa TP |
1074 | |
1075 | struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; | |
1076 | unsigned int nqvecs; | |
213f428f TP |
1077 | bool has_tx_irqs; |
1078 | ||
1079 | u32 tx_time_coal; | |
3f518509 MW |
1080 | }; |
1081 | ||
1082 | /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the | |
1083 | * layout of the transmit and reception DMA descriptors, and their | |
1084 | * layout is therefore defined by the hardware design | |
1085 | */ | |
1086 | ||
1087 | #define MVPP2_TXD_L3_OFF_SHIFT 0 | |
1088 | #define MVPP2_TXD_IP_HLEN_SHIFT 8 | |
1089 | #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) | |
1090 | #define MVPP2_TXD_L4_CSUM_NOT BIT(14) | |
1091 | #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) | |
1092 | #define MVPP2_TXD_PADDING_DISABLE BIT(23) | |
1093 | #define MVPP2_TXD_L4_UDP BIT(24) | |
1094 | #define MVPP2_TXD_L3_IP6 BIT(26) | |
1095 | #define MVPP2_TXD_L_DESC BIT(28) | |
1096 | #define MVPP2_TXD_F_DESC BIT(29) | |
1097 | ||
1098 | #define MVPP2_RXD_ERR_SUMMARY BIT(15) | |
1099 | #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) | |
1100 | #define MVPP2_RXD_ERR_CRC 0x0 | |
1101 | #define MVPP2_RXD_ERR_OVERRUN BIT(13) | |
1102 | #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) | |
1103 | #define MVPP2_RXD_BM_POOL_ID_OFFS 16 | |
1104 | #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) | |
1105 | #define MVPP2_RXD_HWF_SYNC BIT(21) | |
1106 | #define MVPP2_RXD_L4_CSUM_OK BIT(22) | |
1107 | #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) | |
1108 | #define MVPP2_RXD_L4_TCP BIT(25) | |
1109 | #define MVPP2_RXD_L4_UDP BIT(26) | |
1110 | #define MVPP2_RXD_L3_IP4 BIT(28) | |
1111 | #define MVPP2_RXD_L3_IP6 BIT(30) | |
1112 | #define MVPP2_RXD_BUF_HDR BIT(31) | |
1113 | ||
054f6372 TP |
1114 | /* HW TX descriptor for PPv2.1 */ |
1115 | struct mvpp21_tx_desc { | |
3f518509 MW |
1116 | u32 command; /* Options used by HW for packet transmitting.*/ |
1117 | u8 packet_offset; /* the offset from the buffer beginning */ | |
1118 | u8 phys_txq; /* destination queue ID */ | |
1119 | u16 data_size; /* data size of transmitted packet in bytes */ | |
20396136 | 1120 | u32 buf_dma_addr; /* physical addr of transmitted buffer */ |
3f518509 MW |
1121 | u32 buf_cookie; /* cookie for access to TX buffer in tx path */ |
1122 | u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ | |
1123 | u32 reserved2; /* reserved (for future use) */ | |
1124 | }; | |
1125 | ||
054f6372 TP |
1126 | /* HW RX descriptor for PPv2.1 */ |
1127 | struct mvpp21_rx_desc { | |
3f518509 MW |
1128 | u32 status; /* info about received packet */ |
1129 | u16 reserved1; /* parser_info (for future use, PnC) */ | |
1130 | u16 data_size; /* size of received packet in bytes */ | |
20396136 | 1131 | u32 buf_dma_addr; /* physical address of the buffer */ |
3f518509 MW |
1132 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
1133 | u16 reserved2; /* gem_port_id (for future use, PON) */ | |
1134 | u16 reserved3; /* csum_l4 (for future use, PnC) */ | |
1135 | u8 reserved4; /* bm_qset (for future use, BM) */ | |
1136 | u8 reserved5; | |
1137 | u16 reserved6; /* classify_info (for future use, PnC) */ | |
1138 | u32 reserved7; /* flow_id (for future use, PnC) */ | |
1139 | u32 reserved8; | |
1140 | }; | |
1141 | ||
e7c5359f TP |
1142 | /* HW TX descriptor for PPv2.2 */ |
1143 | struct mvpp22_tx_desc { | |
1144 | u32 command; | |
1145 | u8 packet_offset; | |
1146 | u8 phys_txq; | |
1147 | u16 data_size; | |
1148 | u64 reserved1; | |
1149 | u64 buf_dma_addr_ptp; | |
1150 | u64 buf_cookie_misc; | |
1151 | }; | |
1152 | ||
1153 | /* HW RX descriptor for PPv2.2 */ | |
1154 | struct mvpp22_rx_desc { | |
1155 | u32 status; | |
1156 | u16 reserved1; | |
1157 | u16 data_size; | |
1158 | u32 reserved2; | |
1159 | u32 reserved3; | |
1160 | u64 buf_dma_addr_key_hash; | |
1161 | u64 buf_cookie_misc; | |
1162 | }; | |
1163 | ||
054f6372 TP |
1164 | /* Opaque type used by the driver to manipulate the HW TX and RX |
1165 | * descriptors | |
1166 | */ | |
1167 | struct mvpp2_tx_desc { | |
1168 | union { | |
1169 | struct mvpp21_tx_desc pp21; | |
e7c5359f | 1170 | struct mvpp22_tx_desc pp22; |
054f6372 TP |
1171 | }; |
1172 | }; | |
1173 | ||
1174 | struct mvpp2_rx_desc { | |
1175 | union { | |
1176 | struct mvpp21_rx_desc pp21; | |
e7c5359f | 1177 | struct mvpp22_rx_desc pp22; |
054f6372 TP |
1178 | }; |
1179 | }; | |
1180 | ||
8354491c TP |
1181 | struct mvpp2_txq_pcpu_buf { |
1182 | /* Transmitted SKB */ | |
1183 | struct sk_buff *skb; | |
1184 | ||
1185 | /* Physical address of transmitted buffer */ | |
20396136 | 1186 | dma_addr_t dma; |
8354491c TP |
1187 | |
1188 | /* Size transmitted */ | |
1189 | size_t size; | |
1190 | }; | |
1191 | ||
3f518509 MW |
1192 | /* Per-CPU Tx queue control */ |
1193 | struct mvpp2_txq_pcpu { | |
1194 | int cpu; | |
1195 | ||
1196 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
1197 | int size; | |
1198 | ||
1199 | /* Number of currently used Tx DMA descriptor in the | |
1200 | * descriptor ring | |
1201 | */ | |
1202 | int count; | |
1203 | ||
1d17db08 AT |
1204 | int wake_threshold; |
1205 | int stop_threshold; | |
1206 | ||
3f518509 MW |
1207 | /* Number of Tx DMA descriptors reserved for each CPU */ |
1208 | int reserved_num; | |
1209 | ||
8354491c TP |
1210 | /* Infos about transmitted buffers */ |
1211 | struct mvpp2_txq_pcpu_buf *buffs; | |
71ce391d | 1212 | |
3f518509 MW |
1213 | /* Index of last TX DMA descriptor that was inserted */ |
1214 | int txq_put_index; | |
1215 | ||
1216 | /* Index of the TX DMA descriptor to be cleaned up */ | |
1217 | int txq_get_index; | |
186cd4d4 AT |
1218 | |
1219 | /* DMA buffer for TSO headers */ | |
1220 | char *tso_headers; | |
1221 | dma_addr_t tso_headers_dma; | |
3f518509 MW |
1222 | }; |
1223 | ||
1224 | struct mvpp2_tx_queue { | |
1225 | /* Physical number of this Tx queue */ | |
1226 | u8 id; | |
1227 | ||
1228 | /* Logical number of this Tx queue */ | |
1229 | u8 log_id; | |
1230 | ||
1231 | /* Number of Tx DMA descriptors in the descriptor ring */ | |
1232 | int size; | |
1233 | ||
1234 | /* Number of currently used Tx DMA descriptor in the descriptor ring */ | |
1235 | int count; | |
1236 | ||
1237 | /* Per-CPU control of physical Tx queues */ | |
1238 | struct mvpp2_txq_pcpu __percpu *pcpu; | |
1239 | ||
3f518509 MW |
1240 | u32 done_pkts_coal; |
1241 | ||
1242 | /* Virtual address of thex Tx DMA descriptors array */ | |
1243 | struct mvpp2_tx_desc *descs; | |
1244 | ||
1245 | /* DMA address of the Tx DMA descriptors array */ | |
20396136 | 1246 | dma_addr_t descs_dma; |
3f518509 MW |
1247 | |
1248 | /* Index of the last Tx DMA descriptor */ | |
1249 | int last_desc; | |
1250 | ||
1251 | /* Index of the next Tx DMA descriptor to process */ | |
1252 | int next_desc_to_proc; | |
1253 | }; | |
1254 | ||
1255 | struct mvpp2_rx_queue { | |
1256 | /* RX queue number, in the range 0-31 for physical RXQs */ | |
1257 | u8 id; | |
1258 | ||
1259 | /* Num of rx descriptors in the rx descriptor ring */ | |
1260 | int size; | |
1261 | ||
1262 | u32 pkts_coal; | |
1263 | u32 time_coal; | |
1264 | ||
1265 | /* Virtual address of the RX DMA descriptors array */ | |
1266 | struct mvpp2_rx_desc *descs; | |
1267 | ||
1268 | /* DMA address of the RX DMA descriptors array */ | |
20396136 | 1269 | dma_addr_t descs_dma; |
3f518509 MW |
1270 | |
1271 | /* Index of the last RX DMA descriptor */ | |
1272 | int last_desc; | |
1273 | ||
1274 | /* Index of the next RX DMA descriptor to process */ | |
1275 | int next_desc_to_proc; | |
1276 | ||
1277 | /* ID of port to which physical RXQ is mapped */ | |
1278 | int port; | |
1279 | ||
1280 | /* Port's logic RXQ number to which physical RXQ is mapped */ | |
1281 | int logic_rxq; | |
1282 | }; | |
1283 | ||
1284 | union mvpp2_prs_tcam_entry { | |
1285 | u32 word[MVPP2_PRS_TCAM_WORDS]; | |
1286 | u8 byte[MVPP2_PRS_TCAM_WORDS * 4]; | |
1287 | }; | |
1288 | ||
1289 | union mvpp2_prs_sram_entry { | |
1290 | u32 word[MVPP2_PRS_SRAM_WORDS]; | |
1291 | u8 byte[MVPP2_PRS_SRAM_WORDS * 4]; | |
1292 | }; | |
1293 | ||
1294 | struct mvpp2_prs_entry { | |
1295 | u32 index; | |
1296 | union mvpp2_prs_tcam_entry tcam; | |
1297 | union mvpp2_prs_sram_entry sram; | |
1298 | }; | |
1299 | ||
1300 | struct mvpp2_prs_shadow { | |
1301 | bool valid; | |
1302 | bool finish; | |
1303 | ||
1304 | /* Lookup ID */ | |
1305 | int lu; | |
1306 | ||
1307 | /* User defined offset */ | |
1308 | int udf; | |
1309 | ||
1310 | /* Result info */ | |
1311 | u32 ri; | |
1312 | u32 ri_mask; | |
1313 | }; | |
1314 | ||
1315 | struct mvpp2_cls_flow_entry { | |
1316 | u32 index; | |
1317 | u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS]; | |
1318 | }; | |
1319 | ||
1320 | struct mvpp2_cls_lookup_entry { | |
1321 | u32 lkpid; | |
1322 | u32 way; | |
1323 | u32 data; | |
1324 | }; | |
1325 | ||
1326 | struct mvpp2_bm_pool { | |
1327 | /* Pool number in the range 0-7 */ | |
1328 | int id; | |
3f518509 MW |
1329 | |
1330 | /* Buffer Pointers Pool External (BPPE) size */ | |
1331 | int size; | |
d01524d8 TP |
1332 | /* BPPE size in bytes */ |
1333 | int size_bytes; | |
3f518509 MW |
1334 | /* Number of buffers for this pool */ |
1335 | int buf_num; | |
1336 | /* Pool buffer size */ | |
1337 | int buf_size; | |
1338 | /* Packet size */ | |
1339 | int pkt_size; | |
0e037281 | 1340 | int frag_size; |
3f518509 MW |
1341 | |
1342 | /* BPPE virtual base address */ | |
1343 | u32 *virt_addr; | |
20396136 TP |
1344 | /* BPPE DMA base address */ |
1345 | dma_addr_t dma_addr; | |
3f518509 MW |
1346 | |
1347 | /* Ports using BM pool */ | |
1348 | u32 port_map; | |
3f518509 MW |
1349 | }; |
1350 | ||
20920267 AT |
1351 | #define IS_TSO_HEADER(txq_pcpu, addr) \ |
1352 | ((addr) >= (txq_pcpu)->tso_headers_dma && \ | |
1353 | (addr) < (txq_pcpu)->tso_headers_dma + \ | |
1354 | (txq_pcpu)->size * TSO_HEADER_SIZE) | |
1355 | ||
4bb04326 AT |
1356 | /* The prototype is added here to be used in start_dev when using ACPI. This |
1357 | * will be removed once phylink is used for all modes (dt+ACPI). | |
1358 | */ | |
1359 | static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, | |
1360 | const struct phylink_link_state *state); | |
1361 | ||
213f428f TP |
1362 | /* Queue modes */ |
1363 | #define MVPP2_QDIST_SINGLE_MODE 0 | |
1364 | #define MVPP2_QDIST_MULTI_MODE 1 | |
1365 | ||
1366 | static int queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
1367 | ||
1368 | module_param(queue_mode, int, 0444); | |
1369 | MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); | |
1370 | ||
3f518509 MW |
1371 | #define MVPP2_DRIVER_NAME "mvpp2" |
1372 | #define MVPP2_DRIVER_VERSION "1.0" | |
1373 | ||
1374 | /* Utility/helper methods */ | |
1375 | ||
1376 | static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) | |
1377 | { | |
df089aa0 | 1378 | writel(data, priv->swth_base[0] + offset); |
3f518509 MW |
1379 | } |
1380 | ||
1381 | static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) | |
1382 | { | |
df089aa0 | 1383 | return readl(priv->swth_base[0] + offset); |
a786841d TP |
1384 | } |
1385 | ||
cdcfeb0f YM |
1386 | static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) |
1387 | { | |
1388 | return readl_relaxed(priv->swth_base[0] + offset); | |
1389 | } | |
a786841d TP |
1390 | /* These accessors should be used to access: |
1391 | * | |
1392 | * - per-CPU registers, where each CPU has its own copy of the | |
1393 | * register. | |
1394 | * | |
1395 | * MVPP2_BM_VIRT_ALLOC_REG | |
1396 | * MVPP2_BM_ADDR_HIGH_ALLOC | |
1397 | * MVPP22_BM_ADDR_HIGH_RLS_REG | |
1398 | * MVPP2_BM_VIRT_RLS_REG | |
1399 | * MVPP2_ISR_RX_TX_CAUSE_REG | |
1400 | * MVPP2_ISR_RX_TX_MASK_REG | |
1401 | * MVPP2_TXQ_NUM_REG | |
1402 | * MVPP2_AGGR_TXQ_UPDATE_REG | |
1403 | * MVPP2_TXQ_RSVD_REQ_REG | |
1404 | * MVPP2_TXQ_RSVD_RSLT_REG | |
1405 | * MVPP2_TXQ_SENT_REG | |
1406 | * MVPP2_RXQ_NUM_REG | |
1407 | * | |
1408 | * - global registers that must be accessed through a specific CPU | |
1409 | * window, because they are related to an access to a per-CPU | |
1410 | * register | |
1411 | * | |
1412 | * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) | |
1413 | * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) | |
1414 | * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) | |
1415 | * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) | |
1416 | * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) | |
1417 | * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) | |
1418 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1419 | * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) | |
1420 | * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) | |
1421 | * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) | |
1422 | * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) | |
1423 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1424 | * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) | |
1425 | */ | |
1426 | static void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, | |
1427 | u32 offset, u32 data) | |
1428 | { | |
df089aa0 | 1429 | writel(data, priv->swth_base[cpu] + offset); |
a786841d TP |
1430 | } |
1431 | ||
1432 | static u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, | |
1433 | u32 offset) | |
1434 | { | |
df089aa0 | 1435 | return readl(priv->swth_base[cpu] + offset); |
3f518509 MW |
1436 | } |
1437 | ||
cdcfeb0f YM |
1438 | static void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, |
1439 | u32 offset, u32 data) | |
1440 | { | |
1441 | writel_relaxed(data, priv->swth_base[cpu] + offset); | |
1442 | } | |
1443 | ||
1444 | static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, int cpu, | |
1445 | u32 offset) | |
1446 | { | |
1447 | return readl_relaxed(priv->swth_base[cpu] + offset); | |
1448 | } | |
1449 | ||
ac3dd277 TP |
1450 | static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, |
1451 | struct mvpp2_tx_desc *tx_desc) | |
1452 | { | |
e7c5359f TP |
1453 | if (port->priv->hw_version == MVPP21) |
1454 | return tx_desc->pp21.buf_dma_addr; | |
1455 | else | |
da42bb27 | 1456 | return tx_desc->pp22.buf_dma_addr_ptp & MVPP2_DESC_DMA_MASK; |
ac3dd277 TP |
1457 | } |
1458 | ||
1459 | static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, | |
1460 | struct mvpp2_tx_desc *tx_desc, | |
1461 | dma_addr_t dma_addr) | |
1462 | { | |
6eb5d375 AT |
1463 | dma_addr_t addr, offset; |
1464 | ||
1465 | addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; | |
1466 | offset = dma_addr & MVPP2_TX_DESC_ALIGN; | |
1467 | ||
e7c5359f | 1468 | if (port->priv->hw_version == MVPP21) { |
6eb5d375 AT |
1469 | tx_desc->pp21.buf_dma_addr = addr; |
1470 | tx_desc->pp21.packet_offset = offset; | |
e7c5359f | 1471 | } else { |
6eb5d375 | 1472 | u64 val = (u64)addr; |
e7c5359f | 1473 | |
da42bb27 | 1474 | tx_desc->pp22.buf_dma_addr_ptp &= ~MVPP2_DESC_DMA_MASK; |
e7c5359f | 1475 | tx_desc->pp22.buf_dma_addr_ptp |= val; |
6eb5d375 | 1476 | tx_desc->pp22.packet_offset = offset; |
e7c5359f | 1477 | } |
ac3dd277 TP |
1478 | } |
1479 | ||
1480 | static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, | |
1481 | struct mvpp2_tx_desc *tx_desc) | |
1482 | { | |
e7c5359f TP |
1483 | if (port->priv->hw_version == MVPP21) |
1484 | return tx_desc->pp21.data_size; | |
1485 | else | |
1486 | return tx_desc->pp22.data_size; | |
ac3dd277 TP |
1487 | } |
1488 | ||
1489 | static void mvpp2_txdesc_size_set(struct mvpp2_port *port, | |
1490 | struct mvpp2_tx_desc *tx_desc, | |
1491 | size_t size) | |
1492 | { | |
e7c5359f TP |
1493 | if (port->priv->hw_version == MVPP21) |
1494 | tx_desc->pp21.data_size = size; | |
1495 | else | |
1496 | tx_desc->pp22.data_size = size; | |
ac3dd277 TP |
1497 | } |
1498 | ||
1499 | static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, | |
1500 | struct mvpp2_tx_desc *tx_desc, | |
1501 | unsigned int txq) | |
1502 | { | |
e7c5359f TP |
1503 | if (port->priv->hw_version == MVPP21) |
1504 | tx_desc->pp21.phys_txq = txq; | |
1505 | else | |
1506 | tx_desc->pp22.phys_txq = txq; | |
ac3dd277 TP |
1507 | } |
1508 | ||
1509 | static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, | |
1510 | struct mvpp2_tx_desc *tx_desc, | |
1511 | unsigned int command) | |
1512 | { | |
e7c5359f TP |
1513 | if (port->priv->hw_version == MVPP21) |
1514 | tx_desc->pp21.command = command; | |
1515 | else | |
1516 | tx_desc->pp22.command = command; | |
ac3dd277 TP |
1517 | } |
1518 | ||
ac3dd277 TP |
1519 | static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, |
1520 | struct mvpp2_tx_desc *tx_desc) | |
1521 | { | |
e7c5359f TP |
1522 | if (port->priv->hw_version == MVPP21) |
1523 | return tx_desc->pp21.packet_offset; | |
1524 | else | |
1525 | return tx_desc->pp22.packet_offset; | |
ac3dd277 TP |
1526 | } |
1527 | ||
1528 | static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, | |
1529 | struct mvpp2_rx_desc *rx_desc) | |
1530 | { | |
e7c5359f TP |
1531 | if (port->priv->hw_version == MVPP21) |
1532 | return rx_desc->pp21.buf_dma_addr; | |
1533 | else | |
da42bb27 | 1534 | return rx_desc->pp22.buf_dma_addr_key_hash & MVPP2_DESC_DMA_MASK; |
ac3dd277 TP |
1535 | } |
1536 | ||
1537 | static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, | |
1538 | struct mvpp2_rx_desc *rx_desc) | |
1539 | { | |
e7c5359f TP |
1540 | if (port->priv->hw_version == MVPP21) |
1541 | return rx_desc->pp21.buf_cookie; | |
1542 | else | |
da42bb27 | 1543 | return rx_desc->pp22.buf_cookie_misc & MVPP2_DESC_DMA_MASK; |
ac3dd277 TP |
1544 | } |
1545 | ||
1546 | static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, | |
1547 | struct mvpp2_rx_desc *rx_desc) | |
1548 | { | |
e7c5359f TP |
1549 | if (port->priv->hw_version == MVPP21) |
1550 | return rx_desc->pp21.data_size; | |
1551 | else | |
1552 | return rx_desc->pp22.data_size; | |
ac3dd277 TP |
1553 | } |
1554 | ||
1555 | static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, | |
1556 | struct mvpp2_rx_desc *rx_desc) | |
1557 | { | |
e7c5359f TP |
1558 | if (port->priv->hw_version == MVPP21) |
1559 | return rx_desc->pp21.status; | |
1560 | else | |
1561 | return rx_desc->pp22.status; | |
ac3dd277 TP |
1562 | } |
1563 | ||
3f518509 MW |
1564 | static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) |
1565 | { | |
1566 | txq_pcpu->txq_get_index++; | |
1567 | if (txq_pcpu->txq_get_index == txq_pcpu->size) | |
1568 | txq_pcpu->txq_get_index = 0; | |
1569 | } | |
1570 | ||
ac3dd277 TP |
1571 | static void mvpp2_txq_inc_put(struct mvpp2_port *port, |
1572 | struct mvpp2_txq_pcpu *txq_pcpu, | |
71ce391d MW |
1573 | struct sk_buff *skb, |
1574 | struct mvpp2_tx_desc *tx_desc) | |
3f518509 | 1575 | { |
8354491c TP |
1576 | struct mvpp2_txq_pcpu_buf *tx_buf = |
1577 | txq_pcpu->buffs + txq_pcpu->txq_put_index; | |
1578 | tx_buf->skb = skb; | |
ac3dd277 TP |
1579 | tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); |
1580 | tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + | |
1581 | mvpp2_txdesc_offset_get(port, tx_desc); | |
3f518509 MW |
1582 | txq_pcpu->txq_put_index++; |
1583 | if (txq_pcpu->txq_put_index == txq_pcpu->size) | |
1584 | txq_pcpu->txq_put_index = 0; | |
1585 | } | |
1586 | ||
1587 | /* Get number of physical egress port */ | |
1588 | static inline int mvpp2_egress_port(struct mvpp2_port *port) | |
1589 | { | |
1590 | return MVPP2_MAX_TCONT + port->id; | |
1591 | } | |
1592 | ||
1593 | /* Get number of physical TXQ */ | |
1594 | static inline int mvpp2_txq_phys(int port, int txq) | |
1595 | { | |
1596 | return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; | |
1597 | } | |
1598 | ||
1599 | /* Parser configuration routines */ | |
1600 | ||
1601 | /* Update parser tcam and sram hw entries */ | |
1602 | static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) | |
1603 | { | |
1604 | int i; | |
1605 | ||
1606 | if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) | |
1607 | return -EINVAL; | |
1608 | ||
1609 | /* Clear entry invalidation bit */ | |
1610 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; | |
1611 | ||
1612 | /* Write tcam index - indirect access */ | |
1613 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1614 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1615 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); | |
1616 | ||
1617 | /* Write sram index - indirect access */ | |
1618 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1619 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1620 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
47e0e14e MC |
1625 | /* Initialize tcam entry from hw */ |
1626 | static int mvpp2_prs_init_from_hw(struct mvpp2 *priv, | |
1627 | struct mvpp2_prs_entry *pe, int tid) | |
3f518509 MW |
1628 | { |
1629 | int i; | |
1630 | ||
3d92f0b5 | 1631 | if (tid > MVPP2_PRS_TCAM_SRAM_SIZE - 1) |
3f518509 MW |
1632 | return -EINVAL; |
1633 | ||
47e0e14e MC |
1634 | memset(pe, 0, sizeof(*pe)); |
1635 | pe->index = tid; | |
1636 | ||
3f518509 MW |
1637 | /* Write tcam index - indirect access */ |
1638 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); | |
1639 | ||
1640 | pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, | |
1641 | MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD)); | |
1642 | if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) | |
1643 | return MVPP2_PRS_TCAM_ENTRY_INVALID; | |
1644 | ||
1645 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
1646 | pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); | |
1647 | ||
1648 | /* Write sram index - indirect access */ | |
1649 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); | |
1650 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
1651 | pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
1656 | /* Invalidate tcam hw entry */ | |
1657 | static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index) | |
1658 | { | |
1659 | /* Write index - indirect access */ | |
1660 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
1661 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), | |
1662 | MVPP2_PRS_TCAM_INV_MASK); | |
1663 | } | |
1664 | ||
1665 | /* Enable shadow table entry and set its lookup ID */ | |
1666 | static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) | |
1667 | { | |
1668 | priv->prs_shadow[index].valid = true; | |
1669 | priv->prs_shadow[index].lu = lu; | |
1670 | } | |
1671 | ||
1672 | /* Update ri fields in shadow table entry */ | |
1673 | static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index, | |
1674 | unsigned int ri, unsigned int ri_mask) | |
1675 | { | |
1676 | priv->prs_shadow[index].ri_mask = ri_mask; | |
1677 | priv->prs_shadow[index].ri = ri; | |
1678 | } | |
1679 | ||
1680 | /* Update lookup field in tcam sw entry */ | |
1681 | static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) | |
1682 | { | |
1683 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE); | |
1684 | ||
1685 | pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; | |
1686 | pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; | |
1687 | } | |
1688 | ||
1689 | /* Update mask for single port in tcam sw entry */ | |
1690 | static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, | |
1691 | unsigned int port, bool add) | |
1692 | { | |
1693 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1694 | ||
1695 | if (add) | |
1696 | pe->tcam.byte[enable_off] &= ~(1 << port); | |
1697 | else | |
1698 | pe->tcam.byte[enable_off] |= 1 << port; | |
1699 | } | |
1700 | ||
1701 | /* Update port map in tcam sw entry */ | |
1702 | static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, | |
1703 | unsigned int ports) | |
1704 | { | |
1705 | unsigned char port_mask = MVPP2_PRS_PORT_MASK; | |
1706 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1707 | ||
1708 | pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; | |
1709 | pe->tcam.byte[enable_off] &= ~port_mask; | |
1710 | pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; | |
1711 | } | |
1712 | ||
1713 | /* Obtain port map from tcam sw entry */ | |
1714 | static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) | |
1715 | { | |
1716 | int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); | |
1717 | ||
1718 | return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; | |
1719 | } | |
1720 | ||
1721 | /* Set byte of data and its enable bits in tcam sw entry */ | |
1722 | static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, | |
1723 | unsigned int offs, unsigned char byte, | |
1724 | unsigned char enable) | |
1725 | { | |
1726 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; | |
1727 | pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; | |
1728 | } | |
1729 | ||
1730 | /* Get byte of data and its enable bits from tcam sw entry */ | |
1731 | static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, | |
1732 | unsigned int offs, unsigned char *byte, | |
1733 | unsigned char *enable) | |
1734 | { | |
1735 | *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; | |
1736 | *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; | |
1737 | } | |
1738 | ||
1739 | /* Compare tcam data bytes with a pattern */ | |
1740 | static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, | |
1741 | u16 data) | |
1742 | { | |
1743 | int off = MVPP2_PRS_TCAM_DATA_BYTE(offs); | |
1744 | u16 tcam_data; | |
1745 | ||
ef4816f0 | 1746 | tcam_data = (pe->tcam.byte[off + 1] << 8) | pe->tcam.byte[off]; |
3f518509 MW |
1747 | if (tcam_data != data) |
1748 | return false; | |
1749 | return true; | |
1750 | } | |
1751 | ||
1752 | /* Update ai bits in tcam sw entry */ | |
1753 | static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, | |
1754 | unsigned int bits, unsigned int enable) | |
1755 | { | |
1756 | int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE; | |
1757 | ||
1758 | for (i = 0; i < MVPP2_PRS_AI_BITS; i++) { | |
1759 | ||
1760 | if (!(enable & BIT(i))) | |
1761 | continue; | |
1762 | ||
1763 | if (bits & BIT(i)) | |
1764 | pe->tcam.byte[ai_idx] |= 1 << i; | |
1765 | else | |
1766 | pe->tcam.byte[ai_idx] &= ~(1 << i); | |
1767 | } | |
1768 | ||
1769 | pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable; | |
1770 | } | |
1771 | ||
1772 | /* Get ai bits from tcam sw entry */ | |
1773 | static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) | |
1774 | { | |
1775 | return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE]; | |
1776 | } | |
1777 | ||
1778 | /* Set ethertype in tcam sw entry */ | |
1779 | static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, | |
1780 | unsigned short ethertype) | |
1781 | { | |
1782 | mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); | |
1783 | mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); | |
1784 | } | |
1785 | ||
56beda3d MC |
1786 | /* Set vid in tcam sw entry */ |
1787 | static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset, | |
1788 | unsigned short vid) | |
1789 | { | |
1790 | mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf); | |
1791 | mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff); | |
1792 | } | |
1793 | ||
3f518509 MW |
1794 | /* Set bits in sram sw entry */ |
1795 | static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, | |
1796 | int val) | |
1797 | { | |
1798 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); | |
1799 | } | |
1800 | ||
1801 | /* Clear bits in sram sw entry */ | |
1802 | static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, | |
1803 | int val) | |
1804 | { | |
1805 | pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); | |
1806 | } | |
1807 | ||
1808 | /* Update ri bits in sram sw entry */ | |
1809 | static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, | |
1810 | unsigned int bits, unsigned int mask) | |
1811 | { | |
1812 | unsigned int i; | |
1813 | ||
1814 | for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) { | |
1815 | int ri_off = MVPP2_PRS_SRAM_RI_OFFS; | |
1816 | ||
1817 | if (!(mask & BIT(i))) | |
1818 | continue; | |
1819 | ||
1820 | if (bits & BIT(i)) | |
1821 | mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); | |
1822 | else | |
1823 | mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); | |
1824 | ||
1825 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); | |
1826 | } | |
1827 | } | |
1828 | ||
1829 | /* Obtain ri bits from sram sw entry */ | |
1830 | static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) | |
1831 | { | |
1832 | return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD]; | |
1833 | } | |
1834 | ||
1835 | /* Update ai bits in sram sw entry */ | |
1836 | static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, | |
1837 | unsigned int bits, unsigned int mask) | |
1838 | { | |
1839 | unsigned int i; | |
1840 | int ai_off = MVPP2_PRS_SRAM_AI_OFFS; | |
1841 | ||
1842 | for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) { | |
1843 | ||
1844 | if (!(mask & BIT(i))) | |
1845 | continue; | |
1846 | ||
1847 | if (bits & BIT(i)) | |
1848 | mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); | |
1849 | else | |
1850 | mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); | |
1851 | ||
1852 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | /* Read ai bits from sram sw entry */ | |
1857 | static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) | |
1858 | { | |
1859 | u8 bits; | |
1860 | int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS); | |
1861 | int ai_en_off = ai_off + 1; | |
1862 | int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8; | |
1863 | ||
1864 | bits = (pe->sram.byte[ai_off] >> ai_shift) | | |
1865 | (pe->sram.byte[ai_en_off] << (8 - ai_shift)); | |
1866 | ||
1867 | return bits; | |
1868 | } | |
1869 | ||
1870 | /* In sram sw entry set lookup ID field of the tcam key to be used in the next | |
1871 | * lookup interation | |
1872 | */ | |
1873 | static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, | |
1874 | unsigned int lu) | |
1875 | { | |
1876 | int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS; | |
1877 | ||
1878 | mvpp2_prs_sram_bits_clear(pe, sram_next_off, | |
1879 | MVPP2_PRS_SRAM_NEXT_LU_MASK); | |
1880 | mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); | |
1881 | } | |
1882 | ||
1883 | /* In the sram sw entry set sign and value of the next lookup offset | |
1884 | * and the offset value generated to the classifier | |
1885 | */ | |
1886 | static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, | |
1887 | unsigned int op) | |
1888 | { | |
1889 | /* Set sign */ | |
1890 | if (shift < 0) { | |
1891 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1892 | shift = 0 - shift; | |
1893 | } else { | |
1894 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); | |
1895 | } | |
1896 | ||
1897 | /* Set value */ | |
1898 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = | |
1899 | (unsigned char)shift; | |
1900 | ||
1901 | /* Reset and set operation */ | |
1902 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, | |
1903 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK); | |
1904 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); | |
1905 | ||
1906 | /* Set base offset as current */ | |
1907 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1908 | } | |
1909 | ||
1910 | /* In the sram sw entry set sign and value of the user defined offset | |
1911 | * generated to the classifier | |
1912 | */ | |
1913 | static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, | |
1914 | unsigned int type, int offset, | |
1915 | unsigned int op) | |
1916 | { | |
1917 | /* Set sign */ | |
1918 | if (offset < 0) { | |
1919 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1920 | offset = 0 - offset; | |
1921 | } else { | |
1922 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); | |
1923 | } | |
1924 | ||
1925 | /* Set value */ | |
1926 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, | |
1927 | MVPP2_PRS_SRAM_UDF_MASK); | |
1928 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); | |
1929 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1930 | MVPP2_PRS_SRAM_UDF_BITS)] &= | |
1931 | ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1932 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + | |
1933 | MVPP2_PRS_SRAM_UDF_BITS)] |= | |
1934 | (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); | |
1935 | ||
1936 | /* Set offset type */ | |
1937 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, | |
1938 | MVPP2_PRS_SRAM_UDF_TYPE_MASK); | |
1939 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); | |
1940 | ||
1941 | /* Set offset operation */ | |
1942 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, | |
1943 | MVPP2_PRS_SRAM_OP_SEL_UDF_MASK); | |
1944 | mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); | |
1945 | ||
1946 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1947 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &= | |
1948 | ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >> | |
1949 | (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1950 | ||
1951 | pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + | |
1952 | MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |= | |
1953 | (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); | |
1954 | ||
1955 | /* Set base offset as current */ | |
1956 | mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); | |
1957 | } | |
1958 | ||
1959 | /* Find parser flow entry */ | |
0c6d9b44 | 1960 | static int mvpp2_prs_flow_find(struct mvpp2 *priv, int flow) |
3f518509 | 1961 | { |
0c6d9b44 | 1962 | struct mvpp2_prs_entry pe; |
3f518509 MW |
1963 | int tid; |
1964 | ||
3f518509 MW |
1965 | /* Go through the all entires with MVPP2_PRS_LU_FLOWS */ |
1966 | for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { | |
1967 | u8 bits; | |
1968 | ||
1969 | if (!priv->prs_shadow[tid].valid || | |
1970 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) | |
1971 | continue; | |
1972 | ||
0c6d9b44 MC |
1973 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
1974 | bits = mvpp2_prs_sram_ai_get(&pe); | |
3f518509 MW |
1975 | |
1976 | /* Sram store classification lookup ID in AI bits [5:0] */ | |
1977 | if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow) | |
0c6d9b44 | 1978 | return tid; |
3f518509 | 1979 | } |
3f518509 | 1980 | |
0c6d9b44 | 1981 | return -ENOENT; |
3f518509 MW |
1982 | } |
1983 | ||
1984 | /* Return first free tcam index, seeking from start to end */ | |
1985 | static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, | |
1986 | unsigned char end) | |
1987 | { | |
1988 | int tid; | |
1989 | ||
1990 | if (start > end) | |
1991 | swap(start, end); | |
1992 | ||
1993 | if (end >= MVPP2_PRS_TCAM_SRAM_SIZE) | |
1994 | end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; | |
1995 | ||
1996 | for (tid = start; tid <= end; tid++) { | |
1997 | if (!priv->prs_shadow[tid].valid) | |
1998 | return tid; | |
1999 | } | |
2000 | ||
2001 | return -EINVAL; | |
2002 | } | |
2003 | ||
2004 | /* Enable/disable dropping all mac da's */ | |
2005 | static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) | |
2006 | { | |
2007 | struct mvpp2_prs_entry pe; | |
2008 | ||
2009 | if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { | |
2010 | /* Entry exist - update port only */ | |
47e0e14e | 2011 | mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL); |
3f518509 MW |
2012 | } else { |
2013 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2014 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2015 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
2016 | pe.index = MVPP2_PE_DROP_ALL; | |
2017 | ||
2018 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
2019 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
2020 | MVPP2_PRS_RI_DROP_MASK); | |
2021 | ||
2022 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2023 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2024 | ||
2025 | /* Update shadow table */ | |
2026 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2027 | ||
2028 | /* Mask all ports */ | |
2029 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2030 | } | |
2031 | ||
2032 | /* Update port mask */ | |
2033 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2034 | ||
2035 | mvpp2_prs_hw_write(priv, &pe); | |
2036 | } | |
2037 | ||
10fea26c MC |
2038 | /* Set port to unicast or multicast promiscuous mode */ |
2039 | static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, | |
2040 | enum mvpp2_prs_l2_cast l2_cast, bool add) | |
3f518509 MW |
2041 | { |
2042 | struct mvpp2_prs_entry pe; | |
10fea26c MC |
2043 | unsigned char cast_match; |
2044 | unsigned int ri; | |
2045 | int tid; | |
3f518509 | 2046 | |
10fea26c MC |
2047 | if (l2_cast == MVPP2_PRS_L2_UNI_CAST) { |
2048 | cast_match = MVPP2_PRS_UCAST_VAL; | |
2049 | tid = MVPP2_PE_MAC_UC_PROMISCUOUS; | |
2050 | ri = MVPP2_PRS_RI_L2_UCAST; | |
3f518509 | 2051 | } else { |
10fea26c MC |
2052 | cast_match = MVPP2_PRS_MCAST_VAL; |
2053 | tid = MVPP2_PE_MAC_MC_PROMISCUOUS; | |
2054 | ri = MVPP2_PRS_RI_L2_MCAST; | |
3f518509 MW |
2055 | } |
2056 | ||
10fea26c MC |
2057 | /* promiscuous mode - Accept unknown unicast or multicast packets */ |
2058 | if (priv->prs_shadow[tid].valid) { | |
47e0e14e | 2059 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
3f518509 | 2060 | } else { |
c5b2ce24 | 2061 | memset(&pe, 0, sizeof(pe)); |
3f518509 | 2062 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
10fea26c | 2063 | pe.index = tid; |
3f518509 MW |
2064 | |
2065 | /* Continue - set next lookup */ | |
2066 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); | |
2067 | ||
2068 | /* Set result info bits */ | |
10fea26c | 2069 | mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK); |
3f518509 | 2070 | |
10fea26c MC |
2071 | /* Match UC or MC addresses */ |
2072 | mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match, | |
2073 | MVPP2_PRS_CAST_MASK); | |
3f518509 MW |
2074 | |
2075 | /* Shift to ethertype */ | |
2076 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, | |
2077 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2078 | ||
2079 | /* Mask all ports */ | |
2080 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2081 | ||
2082 | /* Update shadow table */ | |
2083 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2084 | } | |
2085 | ||
2086 | /* Update port mask */ | |
2087 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2088 | ||
2089 | mvpp2_prs_hw_write(priv, &pe); | |
2090 | } | |
2091 | ||
2092 | /* Set entry for dsa packets */ | |
2093 | static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add, | |
2094 | bool tagged, bool extend) | |
2095 | { | |
2096 | struct mvpp2_prs_entry pe; | |
2097 | int tid, shift; | |
2098 | ||
2099 | if (extend) { | |
2100 | tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED; | |
2101 | shift = 8; | |
2102 | } else { | |
2103 | tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED; | |
2104 | shift = 4; | |
2105 | } | |
2106 | ||
2107 | if (priv->prs_shadow[tid].valid) { | |
2108 | /* Entry exist - update port only */ | |
47e0e14e | 2109 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
3f518509 MW |
2110 | } else { |
2111 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2112 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2113 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2114 | pe.index = tid; | |
2115 | ||
3f518509 MW |
2116 | /* Update shadow table */ |
2117 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
2118 | ||
2119 | if (tagged) { | |
2120 | /* Set tagged bit in DSA tag */ | |
2121 | mvpp2_prs_tcam_data_byte_set(&pe, 0, | |
56beda3d MC |
2122 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, |
2123 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
2124 | ||
2125 | /* Set ai bits for next iteration */ | |
2126 | if (extend) | |
2127 | mvpp2_prs_sram_ai_update(&pe, 1, | |
2128 | MVPP2_PRS_SRAM_AI_MASK); | |
2129 | else | |
2130 | mvpp2_prs_sram_ai_update(&pe, 0, | |
2131 | MVPP2_PRS_SRAM_AI_MASK); | |
2132 | ||
2133 | /* If packet is tagged continue check vid filtering */ | |
2134 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); | |
3f518509 | 2135 | } else { |
56beda3d MC |
2136 | /* Shift 4 bytes for DSA tag or 8 bytes for EDSA tag*/ |
2137 | mvpp2_prs_sram_shift_set(&pe, shift, | |
2138 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2139 | ||
3f518509 MW |
2140 | /* Set result info bits to 'no vlans' */ |
2141 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2142 | MVPP2_PRS_RI_VLAN_MASK); | |
2143 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2144 | } | |
2145 | ||
2146 | /* Mask all ports */ | |
2147 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2148 | } | |
2149 | ||
2150 | /* Update port mask */ | |
2151 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2152 | ||
2153 | mvpp2_prs_hw_write(priv, &pe); | |
2154 | } | |
2155 | ||
2156 | /* Set entry for dsa ethertype */ | |
2157 | static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port, | |
2158 | bool add, bool tagged, bool extend) | |
2159 | { | |
2160 | struct mvpp2_prs_entry pe; | |
2161 | int tid, shift, port_mask; | |
2162 | ||
2163 | if (extend) { | |
2164 | tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED : | |
2165 | MVPP2_PE_ETYPE_EDSA_UNTAGGED; | |
2166 | port_mask = 0; | |
2167 | shift = 8; | |
2168 | } else { | |
2169 | tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED : | |
2170 | MVPP2_PE_ETYPE_DSA_UNTAGGED; | |
2171 | port_mask = MVPP2_PRS_PORT_MASK; | |
2172 | shift = 4; | |
2173 | } | |
2174 | ||
2175 | if (priv->prs_shadow[tid].valid) { | |
2176 | /* Entry exist - update port only */ | |
47e0e14e | 2177 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
3f518509 MW |
2178 | } else { |
2179 | /* Entry doesn't exist - create new */ | |
c5b2ce24 | 2180 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2181 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2182 | pe.index = tid; | |
2183 | ||
2184 | /* Set ethertype */ | |
2185 | mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); | |
2186 | mvpp2_prs_match_etype(&pe, 2, 0); | |
2187 | ||
2188 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, | |
2189 | MVPP2_PRS_RI_DSA_MASK); | |
2190 | /* Shift ethertype + 2 byte reserved + tag*/ | |
2191 | mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, | |
2192 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2193 | ||
2194 | /* Update shadow table */ | |
2195 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); | |
2196 | ||
2197 | if (tagged) { | |
2198 | /* Set tagged bit in DSA tag */ | |
2199 | mvpp2_prs_tcam_data_byte_set(&pe, | |
2200 | MVPP2_ETH_TYPE_LEN + 2 + 3, | |
2201 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT, | |
2202 | MVPP2_PRS_TCAM_DSA_TAGGED_BIT); | |
2203 | /* Clear all ai bits for next iteration */ | |
2204 | mvpp2_prs_sram_ai_update(&pe, 0, | |
2205 | MVPP2_PRS_SRAM_AI_MASK); | |
2206 | /* If packet is tagged continue check vlans */ | |
2207 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2208 | } else { | |
2209 | /* Set result info bits to 'no vlans' */ | |
2210 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
2211 | MVPP2_PRS_RI_VLAN_MASK); | |
2212 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2213 | } | |
2214 | /* Mask/unmask all ports, depending on dsa type */ | |
2215 | mvpp2_prs_tcam_port_map_set(&pe, port_mask); | |
2216 | } | |
2217 | ||
2218 | /* Update port mask */ | |
2219 | mvpp2_prs_tcam_port_set(&pe, port, add); | |
2220 | ||
2221 | mvpp2_prs_hw_write(priv, &pe); | |
2222 | } | |
2223 | ||
2224 | /* Search for existing single/triple vlan entry */ | |
0c6d9b44 | 2225 | static int mvpp2_prs_vlan_find(struct mvpp2 *priv, unsigned short tpid, int ai) |
3f518509 | 2226 | { |
0c6d9b44 | 2227 | struct mvpp2_prs_entry pe; |
3f518509 MW |
2228 | int tid; |
2229 | ||
3f518509 MW |
2230 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ |
2231 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2232 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2233 | unsigned int ri_bits, ai_bits; | |
2234 | bool match; | |
2235 | ||
2236 | if (!priv->prs_shadow[tid].valid || | |
2237 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2238 | continue; | |
2239 | ||
0c6d9b44 MC |
2240 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
2241 | match = mvpp2_prs_tcam_data_cmp(&pe, 0, swab16(tpid)); | |
3f518509 MW |
2242 | if (!match) |
2243 | continue; | |
2244 | ||
2245 | /* Get vlan type */ | |
0c6d9b44 | 2246 | ri_bits = mvpp2_prs_sram_ri_get(&pe); |
3f518509 MW |
2247 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; |
2248 | ||
2249 | /* Get current ai value from tcam */ | |
0c6d9b44 | 2250 | ai_bits = mvpp2_prs_tcam_ai_get(&pe); |
3f518509 MW |
2251 | /* Clear double vlan bit */ |
2252 | ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT; | |
2253 | ||
2254 | if (ai != ai_bits) | |
2255 | continue; | |
2256 | ||
2257 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2258 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
0c6d9b44 | 2259 | return tid; |
3f518509 | 2260 | } |
3f518509 | 2261 | |
0c6d9b44 | 2262 | return -ENOENT; |
3f518509 MW |
2263 | } |
2264 | ||
2265 | /* Add/update single/triple vlan entry */ | |
2266 | static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai, | |
2267 | unsigned int port_map) | |
2268 | { | |
0c6d9b44 | 2269 | struct mvpp2_prs_entry pe; |
3f518509 | 2270 | int tid_aux, tid; |
43737473 | 2271 | int ret = 0; |
3f518509 | 2272 | |
0c6d9b44 MC |
2273 | memset(&pe, 0, sizeof(pe)); |
2274 | ||
2275 | tid = mvpp2_prs_vlan_find(priv, tpid, ai); | |
3f518509 | 2276 | |
0c6d9b44 | 2277 | if (tid < 0) { |
3f518509 MW |
2278 | /* Create new tcam entry */ |
2279 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID, | |
2280 | MVPP2_PE_FIRST_FREE_TID); | |
2281 | if (tid < 0) | |
2282 | return tid; | |
2283 | ||
3f518509 MW |
2284 | /* Get last double vlan tid */ |
2285 | for (tid_aux = MVPP2_PE_LAST_FREE_TID; | |
2286 | tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) { | |
2287 | unsigned int ri_bits; | |
2288 | ||
2289 | if (!priv->prs_shadow[tid_aux].valid || | |
2290 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2291 | continue; | |
2292 | ||
0c6d9b44 MC |
2293 | mvpp2_prs_init_from_hw(priv, &pe, tid_aux); |
2294 | ri_bits = mvpp2_prs_sram_ri_get(&pe); | |
3f518509 MW |
2295 | if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) == |
2296 | MVPP2_PRS_RI_VLAN_DOUBLE) | |
2297 | break; | |
2298 | } | |
2299 | ||
0c6d9b44 MC |
2300 | if (tid <= tid_aux) |
2301 | return -EINVAL; | |
3f518509 | 2302 | |
0c6d9b44 MC |
2303 | memset(&pe, 0, sizeof(pe)); |
2304 | pe.index = tid; | |
2305 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
3f518509 | 2306 | |
0c6d9b44 | 2307 | mvpp2_prs_match_etype(&pe, 0, tpid); |
3f518509 | 2308 | |
56beda3d | 2309 | /* VLAN tag detected, proceed with VID filtering */ |
0c6d9b44 | 2310 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); |
56beda3d | 2311 | |
3f518509 | 2312 | /* Clear all ai bits for next iteration */ |
0c6d9b44 | 2313 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); |
3f518509 MW |
2314 | |
2315 | if (ai == MVPP2_PRS_SINGLE_VLAN_AI) { | |
0c6d9b44 | 2316 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, |
3f518509 MW |
2317 | MVPP2_PRS_RI_VLAN_MASK); |
2318 | } else { | |
2319 | ai |= MVPP2_PRS_DBL_VLAN_AI_BIT; | |
0c6d9b44 | 2320 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE, |
3f518509 MW |
2321 | MVPP2_PRS_RI_VLAN_MASK); |
2322 | } | |
0c6d9b44 | 2323 | mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK); |
3f518509 | 2324 | |
0c6d9b44 MC |
2325 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); |
2326 | } else { | |
2327 | mvpp2_prs_init_from_hw(priv, &pe, tid); | |
3f518509 MW |
2328 | } |
2329 | /* Update ports' mask */ | |
0c6d9b44 | 2330 | mvpp2_prs_tcam_port_map_set(&pe, port_map); |
3f518509 | 2331 | |
0c6d9b44 | 2332 | mvpp2_prs_hw_write(priv, &pe); |
3f518509 | 2333 | |
43737473 | 2334 | return ret; |
3f518509 MW |
2335 | } |
2336 | ||
2337 | /* Get first free double vlan ai number */ | |
2338 | static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv) | |
2339 | { | |
2340 | int i; | |
2341 | ||
2342 | for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) { | |
2343 | if (!priv->prs_double_vlans[i]) | |
2344 | return i; | |
2345 | } | |
2346 | ||
2347 | return -EINVAL; | |
2348 | } | |
2349 | ||
2350 | /* Search for existing double vlan entry */ | |
0c6d9b44 MC |
2351 | static int mvpp2_prs_double_vlan_find(struct mvpp2 *priv, unsigned short tpid1, |
2352 | unsigned short tpid2) | |
3f518509 | 2353 | { |
0c6d9b44 | 2354 | struct mvpp2_prs_entry pe; |
3f518509 MW |
2355 | int tid; |
2356 | ||
3f518509 MW |
2357 | /* Go through the all entries with MVPP2_PRS_LU_VLAN */ |
2358 | for (tid = MVPP2_PE_FIRST_FREE_TID; | |
2359 | tid <= MVPP2_PE_LAST_FREE_TID; tid++) { | |
2360 | unsigned int ri_mask; | |
2361 | bool match; | |
2362 | ||
2363 | if (!priv->prs_shadow[tid].valid || | |
2364 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN) | |
2365 | continue; | |
2366 | ||
0c6d9b44 | 2367 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
3f518509 | 2368 | |
0c6d9b44 MC |
2369 | match = mvpp2_prs_tcam_data_cmp(&pe, 0, swab16(tpid1)) && |
2370 | mvpp2_prs_tcam_data_cmp(&pe, 4, swab16(tpid2)); | |
3f518509 MW |
2371 | |
2372 | if (!match) | |
2373 | continue; | |
2374 | ||
0c6d9b44 | 2375 | ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK; |
3f518509 | 2376 | if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE) |
0c6d9b44 | 2377 | return tid; |
3f518509 | 2378 | } |
3f518509 | 2379 | |
0c6d9b44 | 2380 | return -ENOENT; |
3f518509 MW |
2381 | } |
2382 | ||
2383 | /* Add or update double vlan entry */ | |
2384 | static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1, | |
2385 | unsigned short tpid2, | |
2386 | unsigned int port_map) | |
2387 | { | |
43737473 | 2388 | int tid_aux, tid, ai, ret = 0; |
0c6d9b44 MC |
2389 | struct mvpp2_prs_entry pe; |
2390 | ||
2391 | memset(&pe, 0, sizeof(pe)); | |
3f518509 | 2392 | |
0c6d9b44 | 2393 | tid = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2); |
3f518509 | 2394 | |
0c6d9b44 | 2395 | if (tid < 0) { |
3f518509 MW |
2396 | /* Create new tcam entry */ |
2397 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2398 | MVPP2_PE_LAST_FREE_TID); | |
2399 | if (tid < 0) | |
2400 | return tid; | |
2401 | ||
3f518509 MW |
2402 | /* Set ai value for new double vlan entry */ |
2403 | ai = mvpp2_prs_double_vlan_ai_free_get(priv); | |
0c6d9b44 MC |
2404 | if (ai < 0) |
2405 | return ai; | |
3f518509 MW |
2406 | |
2407 | /* Get first single/triple vlan tid */ | |
2408 | for (tid_aux = MVPP2_PE_FIRST_FREE_TID; | |
2409 | tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) { | |
2410 | unsigned int ri_bits; | |
2411 | ||
2412 | if (!priv->prs_shadow[tid_aux].valid || | |
2413 | priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN) | |
2414 | continue; | |
2415 | ||
0c6d9b44 MC |
2416 | mvpp2_prs_init_from_hw(priv, &pe, tid_aux); |
2417 | ri_bits = mvpp2_prs_sram_ri_get(&pe); | |
3f518509 MW |
2418 | ri_bits &= MVPP2_PRS_RI_VLAN_MASK; |
2419 | if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE || | |
2420 | ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE) | |
2421 | break; | |
2422 | } | |
2423 | ||
0c6d9b44 MC |
2424 | if (tid >= tid_aux) |
2425 | return -ERANGE; | |
3f518509 | 2426 | |
0c6d9b44 MC |
2427 | memset(&pe, 0, sizeof(pe)); |
2428 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2429 | pe.index = tid; | |
3f518509 MW |
2430 | |
2431 | priv->prs_double_vlans[ai] = true; | |
2432 | ||
0c6d9b44 MC |
2433 | mvpp2_prs_match_etype(&pe, 0, tpid1); |
2434 | mvpp2_prs_match_etype(&pe, 4, tpid2); | |
3f518509 | 2435 | |
0c6d9b44 | 2436 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
56beda3d | 2437 | /* Shift 4 bytes - skip outer vlan tag */ |
0c6d9b44 | 2438 | mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, |
3f518509 | 2439 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); |
0c6d9b44 | 2440 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, |
3f518509 | 2441 | MVPP2_PRS_RI_VLAN_MASK); |
0c6d9b44 | 2442 | mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, |
3f518509 MW |
2443 | MVPP2_PRS_SRAM_AI_MASK); |
2444 | ||
0c6d9b44 MC |
2445 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); |
2446 | } else { | |
2447 | mvpp2_prs_init_from_hw(priv, &pe, tid); | |
3f518509 MW |
2448 | } |
2449 | ||
2450 | /* Update ports' mask */ | |
0c6d9b44 MC |
2451 | mvpp2_prs_tcam_port_map_set(&pe, port_map); |
2452 | mvpp2_prs_hw_write(priv, &pe); | |
2453 | ||
43737473 | 2454 | return ret; |
3f518509 MW |
2455 | } |
2456 | ||
2457 | /* IPv4 header parsing for fragmentation and L4 offset */ | |
2458 | static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto, | |
2459 | unsigned int ri, unsigned int ri_mask) | |
2460 | { | |
2461 | struct mvpp2_prs_entry pe; | |
2462 | int tid; | |
2463 | ||
2464 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2465 | (proto != IPPROTO_IGMP)) | |
2466 | return -EINVAL; | |
2467 | ||
aff3da39 | 2468 | /* Not fragmented packet */ |
3f518509 MW |
2469 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, |
2470 | MVPP2_PE_LAST_FREE_TID); | |
2471 | if (tid < 0) | |
2472 | return tid; | |
2473 | ||
c5b2ce24 | 2474 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2475 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2476 | pe.index = tid; | |
2477 | ||
2478 | /* Set next lu to IPv4 */ | |
2479 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2480 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2481 | /* Set L4 offset */ | |
2482 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2483 | sizeof(struct iphdr) - 4, | |
2484 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2485 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2486 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
aff3da39 SC |
2487 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); |
2488 | ||
2489 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, | |
2490 | MVPP2_PRS_TCAM_PROTO_MASK_L); | |
2491 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, | |
2492 | MVPP2_PRS_TCAM_PROTO_MASK); | |
3f518509 MW |
2493 | |
2494 | mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2495 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2496 | /* Unmask all ports */ | |
2497 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2498 | ||
2499 | /* Update shadow table and hw entry */ | |
2500 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2501 | mvpp2_prs_hw_write(priv, &pe); | |
2502 | ||
aff3da39 | 2503 | /* Fragmented packet */ |
3f518509 MW |
2504 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, |
2505 | MVPP2_PE_LAST_FREE_TID); | |
2506 | if (tid < 0) | |
2507 | return tid; | |
2508 | ||
2509 | pe.index = tid; | |
2510 | /* Clear ri before updating */ | |
2511 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
2512 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
2513 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2514 | ||
aff3da39 SC |
2515 | mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, |
2516 | ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); | |
2517 | ||
2518 | mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); | |
2519 | mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); | |
3f518509 MW |
2520 | |
2521 | /* Update shadow table and hw entry */ | |
2522 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2523 | mvpp2_prs_hw_write(priv, &pe); | |
2524 | ||
2525 | return 0; | |
2526 | } | |
2527 | ||
2528 | /* IPv4 L3 multicast or broadcast */ | |
2529 | static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2530 | { | |
2531 | struct mvpp2_prs_entry pe; | |
2532 | int mask, tid; | |
2533 | ||
2534 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2535 | MVPP2_PE_LAST_FREE_TID); | |
2536 | if (tid < 0) | |
2537 | return tid; | |
2538 | ||
c5b2ce24 | 2539 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2540 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
2541 | pe.index = tid; | |
2542 | ||
2543 | switch (l3_cast) { | |
2544 | case MVPP2_PRS_L3_MULTI_CAST: | |
2545 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, | |
2546 | MVPP2_PRS_IPV4_MC_MASK); | |
2547 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2548 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2549 | break; | |
2550 | case MVPP2_PRS_L3_BROAD_CAST: | |
2551 | mask = MVPP2_PRS_IPV4_BC_MASK; | |
2552 | mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); | |
2553 | mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); | |
2554 | mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); | |
2555 | mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); | |
2556 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, | |
2557 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2558 | break; | |
2559 | default: | |
2560 | return -EINVAL; | |
2561 | } | |
2562 | ||
2563 | /* Finished: go to flowid generation */ | |
2564 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2565 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2566 | ||
2567 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
2568 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
2569 | /* Unmask all ports */ | |
2570 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2571 | ||
2572 | /* Update shadow table and hw entry */ | |
2573 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
2574 | mvpp2_prs_hw_write(priv, &pe); | |
2575 | ||
2576 | return 0; | |
2577 | } | |
2578 | ||
2579 | /* Set entries for protocols over IPv6 */ | |
2580 | static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto, | |
2581 | unsigned int ri, unsigned int ri_mask) | |
2582 | { | |
2583 | struct mvpp2_prs_entry pe; | |
2584 | int tid; | |
2585 | ||
2586 | if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) && | |
2587 | (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP)) | |
2588 | return -EINVAL; | |
2589 | ||
2590 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2591 | MVPP2_PE_LAST_FREE_TID); | |
2592 | if (tid < 0) | |
2593 | return tid; | |
2594 | ||
c5b2ce24 | 2595 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2596 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2597 | pe.index = tid; | |
2598 | ||
2599 | /* Finished: go to flowid generation */ | |
2600 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2601 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2602 | mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); | |
2603 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
2604 | sizeof(struct ipv6hdr) - 6, | |
2605 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2606 | ||
2607 | mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); | |
2608 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2609 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2610 | /* Unmask all ports */ | |
2611 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2612 | ||
2613 | /* Write HW */ | |
2614 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2615 | mvpp2_prs_hw_write(priv, &pe); | |
2616 | ||
2617 | return 0; | |
2618 | } | |
2619 | ||
2620 | /* IPv6 L3 multicast entry */ | |
2621 | static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast) | |
2622 | { | |
2623 | struct mvpp2_prs_entry pe; | |
2624 | int tid; | |
2625 | ||
2626 | if (l3_cast != MVPP2_PRS_L3_MULTI_CAST) | |
2627 | return -EINVAL; | |
2628 | ||
2629 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2630 | MVPP2_PE_LAST_FREE_TID); | |
2631 | if (tid < 0) | |
2632 | return tid; | |
2633 | ||
c5b2ce24 | 2634 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2635 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
2636 | pe.index = tid; | |
2637 | ||
2638 | /* Finished: go to flowid generation */ | |
2639 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
2640 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, | |
2641 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
2642 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
2643 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2644 | /* Shift back to IPv6 NH */ | |
2645 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2646 | ||
2647 | mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, | |
2648 | MVPP2_PRS_IPV6_MC_MASK); | |
2649 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
2650 | /* Unmask all ports */ | |
2651 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2652 | ||
2653 | /* Update shadow table and hw entry */ | |
2654 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
2655 | mvpp2_prs_hw_write(priv, &pe); | |
2656 | ||
2657 | return 0; | |
2658 | } | |
2659 | ||
2660 | /* Parser per-port initialization */ | |
2661 | static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, | |
2662 | int lu_max, int offset) | |
2663 | { | |
2664 | u32 val; | |
2665 | ||
2666 | /* Set lookup ID */ | |
2667 | val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG); | |
2668 | val &= ~MVPP2_PRS_PORT_LU_MASK(port); | |
2669 | val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); | |
2670 | mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); | |
2671 | ||
2672 | /* Set maximum number of loops for packet received from port */ | |
2673 | val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); | |
2674 | val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); | |
2675 | val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); | |
2676 | mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); | |
2677 | ||
2678 | /* Set initial offset for packet header extraction for the first | |
2679 | * searching loop | |
2680 | */ | |
2681 | val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); | |
2682 | val &= ~MVPP2_PRS_INIT_OFF_MASK(port); | |
2683 | val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); | |
2684 | mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); | |
2685 | } | |
2686 | ||
2687 | /* Default flow entries initialization for all ports */ | |
2688 | static void mvpp2_prs_def_flow_init(struct mvpp2 *priv) | |
2689 | { | |
2690 | struct mvpp2_prs_entry pe; | |
2691 | int port; | |
2692 | ||
2693 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
c5b2ce24 | 2694 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2695 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); |
2696 | pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; | |
2697 | ||
2698 | /* Mask all ports */ | |
2699 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
2700 | ||
2701 | /* Set flow ID*/ | |
2702 | mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); | |
2703 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
2704 | ||
2705 | /* Update shadow table and hw entry */ | |
2706 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); | |
2707 | mvpp2_prs_hw_write(priv, &pe); | |
2708 | } | |
2709 | } | |
2710 | ||
2711 | /* Set default entry for Marvell Header field */ | |
2712 | static void mvpp2_prs_mh_init(struct mvpp2 *priv) | |
2713 | { | |
2714 | struct mvpp2_prs_entry pe; | |
2715 | ||
c5b2ce24 | 2716 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2717 | |
2718 | pe.index = MVPP2_PE_MH_DEFAULT; | |
2719 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); | |
2720 | mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, | |
2721 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2722 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2723 | ||
2724 | /* Unmask all ports */ | |
2725 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2726 | ||
2727 | /* Update shadow table and hw entry */ | |
2728 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); | |
2729 | mvpp2_prs_hw_write(priv, &pe); | |
2730 | } | |
2731 | ||
2732 | /* Set default entires (place holder) for promiscuous, non-promiscuous and | |
2733 | * multicast MAC addresses | |
2734 | */ | |
2735 | static void mvpp2_prs_mac_init(struct mvpp2 *priv) | |
2736 | { | |
2737 | struct mvpp2_prs_entry pe; | |
2738 | ||
c5b2ce24 | 2739 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2740 | |
2741 | /* Non-promiscuous mode for all ports - DROP unknown packets */ | |
2742 | pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; | |
2743 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); | |
2744 | ||
2745 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
2746 | MVPP2_PRS_RI_DROP_MASK); | |
2747 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2748 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2749 | ||
2750 | /* Unmask all ports */ | |
2751 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2752 | ||
2753 | /* Update shadow table and hw entry */ | |
2754 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2755 | mvpp2_prs_hw_write(priv, &pe); | |
2756 | ||
10fea26c | 2757 | /* Create dummy entries for drop all and promiscuous modes */ |
3f518509 | 2758 | mvpp2_prs_mac_drop_all_set(priv, 0, false); |
10fea26c MC |
2759 | mvpp2_prs_mac_promisc_set(priv, 0, MVPP2_PRS_L2_UNI_CAST, false); |
2760 | mvpp2_prs_mac_promisc_set(priv, 0, MVPP2_PRS_L2_MULTI_CAST, false); | |
3f518509 MW |
2761 | } |
2762 | ||
2763 | /* Set default entries for various types of dsa packets */ | |
2764 | static void mvpp2_prs_dsa_init(struct mvpp2 *priv) | |
2765 | { | |
2766 | struct mvpp2_prs_entry pe; | |
2767 | ||
2768 | /* None tagged EDSA entry - place holder */ | |
2769 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2770 | MVPP2_PRS_EDSA); | |
2771 | ||
2772 | /* Tagged EDSA entry - place holder */ | |
2773 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2774 | ||
2775 | /* None tagged DSA entry - place holder */ | |
2776 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED, | |
2777 | MVPP2_PRS_DSA); | |
2778 | ||
2779 | /* Tagged DSA entry - place holder */ | |
2780 | mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2781 | ||
2782 | /* None tagged EDSA ethertype entry - place holder*/ | |
2783 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2784 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
2785 | ||
2786 | /* Tagged EDSA ethertype entry - place holder*/ | |
2787 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false, | |
2788 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
2789 | ||
2790 | /* None tagged DSA ethertype entry */ | |
2791 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2792 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
2793 | ||
2794 | /* Tagged DSA ethertype entry */ | |
2795 | mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true, | |
2796 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
2797 | ||
2798 | /* Set default entry, in case DSA or EDSA tag not found */ | |
c5b2ce24 | 2799 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2800 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); |
2801 | pe.index = MVPP2_PE_DSA_DEFAULT; | |
2802 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); | |
2803 | ||
2804 | /* Shift 0 bytes */ | |
2805 | mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2806 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
2807 | ||
2808 | /* Clear all sram ai bits for next iteration */ | |
2809 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2810 | ||
2811 | /* Unmask all ports */ | |
2812 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2813 | ||
2814 | mvpp2_prs_hw_write(priv, &pe); | |
2815 | } | |
2816 | ||
56beda3d MC |
2817 | /* Initialize parser entries for VID filtering */ |
2818 | static void mvpp2_prs_vid_init(struct mvpp2 *priv) | |
2819 | { | |
2820 | struct mvpp2_prs_entry pe; | |
2821 | ||
2822 | memset(&pe, 0, sizeof(pe)); | |
2823 | ||
2824 | /* Set default vid entry */ | |
2825 | pe.index = MVPP2_PE_VID_FLTR_DEFAULT; | |
2826 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
2827 | ||
2828 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT); | |
2829 | ||
2830 | /* Skip VLAN header - Set offset to 4 bytes */ | |
2831 | mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, | |
2832 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2833 | ||
2834 | /* Clear all ai bits for next iteration */ | |
2835 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2836 | ||
2837 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2838 | ||
2839 | /* Unmask all ports */ | |
2840 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2841 | ||
2842 | /* Update shadow table and hw entry */ | |
2843 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
2844 | mvpp2_prs_hw_write(priv, &pe); | |
2845 | ||
2846 | /* Set default vid entry for extended DSA*/ | |
2847 | memset(&pe, 0, sizeof(pe)); | |
2848 | ||
2849 | /* Set default vid entry */ | |
2850 | pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; | |
2851 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
2852 | ||
2853 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT, | |
2854 | MVPP2_PRS_EDSA_VID_AI_BIT); | |
2855 | ||
2856 | /* Skip VLAN header - Set offset to 8 bytes */ | |
2857 | mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN, | |
2858 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2859 | ||
2860 | /* Clear all ai bits for next iteration */ | |
2861 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
2862 | ||
2863 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
2864 | ||
2865 | /* Unmask all ports */ | |
2866 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
2867 | ||
2868 | /* Update shadow table and hw entry */ | |
2869 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
2870 | mvpp2_prs_hw_write(priv, &pe); | |
2871 | } | |
2872 | ||
3f518509 MW |
2873 | /* Match basic ethertypes */ |
2874 | static int mvpp2_prs_etype_init(struct mvpp2 *priv) | |
2875 | { | |
2876 | struct mvpp2_prs_entry pe; | |
2877 | int tid; | |
2878 | ||
2879 | /* Ethertype: PPPoE */ | |
2880 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2881 | MVPP2_PE_LAST_FREE_TID); | |
2882 | if (tid < 0) | |
2883 | return tid; | |
2884 | ||
c5b2ce24 | 2885 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2886 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2887 | pe.index = tid; | |
2888 | ||
2889 | mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); | |
2890 | ||
2891 | mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, | |
2892 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2893 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); | |
2894 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, | |
2895 | MVPP2_PRS_RI_PPPOE_MASK); | |
2896 | ||
2897 | /* Update shadow table and hw entry */ | |
2898 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2899 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2900 | priv->prs_shadow[pe.index].finish = false; | |
2901 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, | |
2902 | MVPP2_PRS_RI_PPPOE_MASK); | |
2903 | mvpp2_prs_hw_write(priv, &pe); | |
2904 | ||
2905 | /* Ethertype: ARP */ | |
2906 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2907 | MVPP2_PE_LAST_FREE_TID); | |
2908 | if (tid < 0) | |
2909 | return tid; | |
2910 | ||
c5b2ce24 | 2911 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2912 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2913 | pe.index = tid; | |
2914 | ||
2915 | mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); | |
2916 | ||
2917 | /* Generate flow in the next iteration*/ | |
2918 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2919 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2920 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, | |
2921 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2922 | /* Set L3 offset */ | |
2923 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2924 | MVPP2_ETH_TYPE_LEN, | |
2925 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2926 | ||
2927 | /* Update shadow table and hw entry */ | |
2928 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2929 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2930 | priv->prs_shadow[pe.index].finish = true; | |
2931 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, | |
2932 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2933 | mvpp2_prs_hw_write(priv, &pe); | |
2934 | ||
2935 | /* Ethertype: LBTD */ | |
2936 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2937 | MVPP2_PE_LAST_FREE_TID); | |
2938 | if (tid < 0) | |
2939 | return tid; | |
2940 | ||
c5b2ce24 | 2941 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2942 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2943 | pe.index = tid; | |
2944 | ||
2945 | mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); | |
2946 | ||
2947 | /* Generate flow in the next iteration*/ | |
2948 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
2949 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
2950 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2951 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2952 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2953 | MVPP2_PRS_RI_UDF3_MASK); | |
2954 | /* Set L3 offset */ | |
2955 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2956 | MVPP2_ETH_TYPE_LEN, | |
2957 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2958 | ||
2959 | /* Update shadow table and hw entry */ | |
2960 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2961 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2962 | priv->prs_shadow[pe.index].finish = true; | |
2963 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
2964 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
2965 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
2966 | MVPP2_PRS_RI_UDF3_MASK); | |
2967 | mvpp2_prs_hw_write(priv, &pe); | |
2968 | ||
2969 | /* Ethertype: IPv4 without options */ | |
2970 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
2971 | MVPP2_PE_LAST_FREE_TID); | |
2972 | if (tid < 0) | |
2973 | return tid; | |
2974 | ||
c5b2ce24 | 2975 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
2976 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
2977 | pe.index = tid; | |
2978 | ||
2979 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); | |
2980 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
2981 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
2982 | MVPP2_PRS_IPV4_HEAD_MASK | | |
2983 | MVPP2_PRS_IPV4_IHL_MASK); | |
2984 | ||
2985 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
2986 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
2987 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
2988 | /* Skip eth_type + 4 bytes of IP header */ | |
2989 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
2990 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
2991 | /* Set L3 offset */ | |
2992 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
2993 | MVPP2_ETH_TYPE_LEN, | |
2994 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
2995 | ||
2996 | /* Update shadow table and hw entry */ | |
2997 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
2998 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
2999 | priv->prs_shadow[pe.index].finish = false; | |
3000 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, | |
3001 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3002 | mvpp2_prs_hw_write(priv, &pe); | |
3003 | ||
3004 | /* Ethertype: IPv4 with options */ | |
3005 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3006 | MVPP2_PE_LAST_FREE_TID); | |
3007 | if (tid < 0) | |
3008 | return tid; | |
3009 | ||
3010 | pe.index = tid; | |
3011 | ||
3012 | /* Clear tcam data before updating */ | |
3013 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
3014 | pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; | |
3015 | ||
3016 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
3017 | MVPP2_PRS_IPV4_HEAD, | |
3018 | MVPP2_PRS_IPV4_HEAD_MASK); | |
3019 | ||
3020 | /* Clear ri before updating */ | |
3021 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
3022 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
3023 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
3024 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3025 | ||
3026 | /* Update shadow table and hw entry */ | |
3027 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3028 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3029 | priv->prs_shadow[pe.index].finish = false; | |
3030 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, | |
3031 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3032 | mvpp2_prs_hw_write(priv, &pe); | |
3033 | ||
3034 | /* Ethertype: IPv6 without options */ | |
3035 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3036 | MVPP2_PE_LAST_FREE_TID); | |
3037 | if (tid < 0) | |
3038 | return tid; | |
3039 | ||
c5b2ce24 | 3040 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3041 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); |
3042 | pe.index = tid; | |
3043 | ||
3044 | mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); | |
3045 | ||
3046 | /* Skip DIP of IPV6 header */ | |
3047 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + | |
3048 | MVPP2_MAX_L3_ADDR_SIZE, | |
3049 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3050 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3051 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
3052 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3053 | /* Set L3 offset */ | |
3054 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3055 | MVPP2_ETH_TYPE_LEN, | |
3056 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3057 | ||
3058 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3059 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3060 | priv->prs_shadow[pe.index].finish = false; | |
3061 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, | |
3062 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3063 | mvpp2_prs_hw_write(priv, &pe); | |
3064 | ||
3065 | /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ | |
3066 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3067 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3068 | pe.index = MVPP2_PE_ETH_TYPE_UN; | |
3069 | ||
3070 | /* Unmask all ports */ | |
3071 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3072 | ||
3073 | /* Generate flow in the next iteration*/ | |
3074 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3075 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3076 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
3077 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3078 | /* Set L3 offset even it's unknown L3 */ | |
3079 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3080 | MVPP2_ETH_TYPE_LEN, | |
3081 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3082 | ||
3083 | /* Update shadow table and hw entry */ | |
3084 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); | |
3085 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; | |
3086 | priv->prs_shadow[pe.index].finish = true; | |
3087 | mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, | |
3088 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3089 | mvpp2_prs_hw_write(priv, &pe); | |
3090 | ||
3091 | return 0; | |
3092 | } | |
3093 | ||
3094 | /* Configure vlan entries and detect up to 2 successive VLAN tags. | |
3095 | * Possible options: | |
3096 | * 0x8100, 0x88A8 | |
3097 | * 0x8100, 0x8100 | |
3098 | * 0x8100 | |
3099 | * 0x88A8 | |
3100 | */ | |
3101 | static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv) | |
3102 | { | |
3103 | struct mvpp2_prs_entry pe; | |
3104 | int err; | |
3105 | ||
3106 | priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool), | |
3107 | MVPP2_PRS_DBL_VLANS_MAX, | |
3108 | GFP_KERNEL); | |
3109 | if (!priv->prs_double_vlans) | |
3110 | return -ENOMEM; | |
3111 | ||
3112 | /* Double VLAN: 0x8100, 0x88A8 */ | |
3113 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD, | |
3114 | MVPP2_PRS_PORT_MASK); | |
3115 | if (err) | |
3116 | return err; | |
3117 | ||
3118 | /* Double VLAN: 0x8100, 0x8100 */ | |
3119 | err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q, | |
3120 | MVPP2_PRS_PORT_MASK); | |
3121 | if (err) | |
3122 | return err; | |
3123 | ||
3124 | /* Single VLAN: 0x88a8 */ | |
3125 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI, | |
3126 | MVPP2_PRS_PORT_MASK); | |
3127 | if (err) | |
3128 | return err; | |
3129 | ||
3130 | /* Single VLAN: 0x8100 */ | |
3131 | err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI, | |
3132 | MVPP2_PRS_PORT_MASK); | |
3133 | if (err) | |
3134 | return err; | |
3135 | ||
3136 | /* Set default double vlan entry */ | |
c5b2ce24 | 3137 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3138 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
3139 | pe.index = MVPP2_PE_VLAN_DBL; | |
3140 | ||
56beda3d MC |
3141 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); |
3142 | ||
3f518509 MW |
3143 | /* Clear ai for next iterations */ |
3144 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
3145 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, | |
3146 | MVPP2_PRS_RI_VLAN_MASK); | |
3147 | ||
3148 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, | |
3149 | MVPP2_PRS_DBL_VLAN_AI_BIT); | |
3150 | /* Unmask all ports */ | |
3151 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3152 | ||
3153 | /* Update shadow table and hw entry */ | |
3154 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
3155 | mvpp2_prs_hw_write(priv, &pe); | |
3156 | ||
3157 | /* Set default vlan none entry */ | |
c5b2ce24 | 3158 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3159 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); |
3160 | pe.index = MVPP2_PE_VLAN_NONE; | |
3161 | ||
3162 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3163 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, | |
3164 | MVPP2_PRS_RI_VLAN_MASK); | |
3165 | ||
3166 | /* Unmask all ports */ | |
3167 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3168 | ||
3169 | /* Update shadow table and hw entry */ | |
3170 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); | |
3171 | mvpp2_prs_hw_write(priv, &pe); | |
3172 | ||
3173 | return 0; | |
3174 | } | |
3175 | ||
3176 | /* Set entries for PPPoE ethertype */ | |
3177 | static int mvpp2_prs_pppoe_init(struct mvpp2 *priv) | |
3178 | { | |
3179 | struct mvpp2_prs_entry pe; | |
3180 | int tid; | |
3181 | ||
3182 | /* IPv4 over PPPoE with options */ | |
3183 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3184 | MVPP2_PE_LAST_FREE_TID); | |
3185 | if (tid < 0) | |
3186 | return tid; | |
3187 | ||
c5b2ce24 | 3188 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3189 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3190 | pe.index = tid; | |
3191 | ||
3192 | mvpp2_prs_match_etype(&pe, 0, PPP_IP); | |
3193 | ||
3194 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
3195 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, | |
3196 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3197 | /* Skip eth_type + 4 bytes of IP header */ | |
3198 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
3199 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3200 | /* Set L3 offset */ | |
3201 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3202 | MVPP2_ETH_TYPE_LEN, | |
3203 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3204 | ||
3205 | /* Update shadow table and hw entry */ | |
3206 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3207 | mvpp2_prs_hw_write(priv, &pe); | |
3208 | ||
3209 | /* IPv4 over PPPoE without options */ | |
3210 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3211 | MVPP2_PE_LAST_FREE_TID); | |
3212 | if (tid < 0) | |
3213 | return tid; | |
3214 | ||
3215 | pe.index = tid; | |
3216 | ||
3217 | mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, | |
3218 | MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, | |
3219 | MVPP2_PRS_IPV4_HEAD_MASK | | |
3220 | MVPP2_PRS_IPV4_IHL_MASK); | |
3221 | ||
3222 | /* Clear ri before updating */ | |
3223 | pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; | |
3224 | pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; | |
3225 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, | |
3226 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3227 | ||
3228 | /* Update shadow table and hw entry */ | |
3229 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3230 | mvpp2_prs_hw_write(priv, &pe); | |
3231 | ||
3232 | /* IPv6 over PPPoE */ | |
3233 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3234 | MVPP2_PE_LAST_FREE_TID); | |
3235 | if (tid < 0) | |
3236 | return tid; | |
3237 | ||
c5b2ce24 | 3238 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3239 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3240 | pe.index = tid; | |
3241 | ||
3242 | mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); | |
3243 | ||
3244 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3245 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, | |
3246 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3247 | /* Skip eth_type + 4 bytes of IPv6 header */ | |
3248 | mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, | |
3249 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3250 | /* Set L3 offset */ | |
3251 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3252 | MVPP2_ETH_TYPE_LEN, | |
3253 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3254 | ||
3255 | /* Update shadow table and hw entry */ | |
3256 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3257 | mvpp2_prs_hw_write(priv, &pe); | |
3258 | ||
3259 | /* Non-IP over PPPoE */ | |
3260 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3261 | MVPP2_PE_LAST_FREE_TID); | |
3262 | if (tid < 0) | |
3263 | return tid; | |
3264 | ||
c5b2ce24 | 3265 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3266 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); |
3267 | pe.index = tid; | |
3268 | ||
3269 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, | |
3270 | MVPP2_PRS_RI_L3_PROTO_MASK); | |
3271 | ||
3272 | /* Finished: go to flowid generation */ | |
3273 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3274 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3275 | /* Set L3 offset even if it's unknown L3 */ | |
3276 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, | |
3277 | MVPP2_ETH_TYPE_LEN, | |
3278 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3279 | ||
3280 | /* Update shadow table and hw entry */ | |
3281 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); | |
3282 | mvpp2_prs_hw_write(priv, &pe); | |
3283 | ||
3284 | return 0; | |
3285 | } | |
3286 | ||
3287 | /* Initialize entries for IPv4 */ | |
3288 | static int mvpp2_prs_ip4_init(struct mvpp2 *priv) | |
3289 | { | |
3290 | struct mvpp2_prs_entry pe; | |
3291 | int err; | |
3292 | ||
3293 | /* Set entries for TCP, UDP and IGMP over IPv4 */ | |
3294 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP, | |
3295 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3296 | if (err) | |
3297 | return err; | |
3298 | ||
3299 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP, | |
3300 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3301 | if (err) | |
3302 | return err; | |
3303 | ||
3304 | err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP, | |
3305 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3306 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3307 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3308 | MVPP2_PRS_RI_UDF3_MASK); | |
3309 | if (err) | |
3310 | return err; | |
3311 | ||
3312 | /* IPv4 Broadcast */ | |
3313 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST); | |
3314 | if (err) | |
3315 | return err; | |
3316 | ||
3317 | /* IPv4 Multicast */ | |
3318 | err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3319 | if (err) | |
3320 | return err; | |
3321 | ||
3322 | /* Default IPv4 entry for unknown protocols */ | |
c5b2ce24 | 3323 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3324 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3325 | pe.index = MVPP2_PE_IP4_PROTO_UN; | |
3326 | ||
3327 | /* Set next lu to IPv4 */ | |
3328 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); | |
3329 | mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3330 | /* Set L4 offset */ | |
3331 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3332 | sizeof(struct iphdr) - 4, | |
3333 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3334 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3335 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3336 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3337 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3338 | ||
3339 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3340 | /* Unmask all ports */ | |
3341 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3342 | ||
3343 | /* Update shadow table and hw entry */ | |
3344 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3345 | mvpp2_prs_hw_write(priv, &pe); | |
3346 | ||
3347 | /* Default IPv4 entry for unicast address */ | |
c5b2ce24 | 3348 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3349 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); |
3350 | pe.index = MVPP2_PE_IP4_ADDR_UN; | |
3351 | ||
3352 | /* Finished: go to flowid generation */ | |
3353 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3354 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3355 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3356 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3357 | ||
3358 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, | |
3359 | MVPP2_PRS_IPV4_DIP_AI_BIT); | |
3360 | /* Unmask all ports */ | |
3361 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3362 | ||
3363 | /* Update shadow table and hw entry */ | |
3364 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3365 | mvpp2_prs_hw_write(priv, &pe); | |
3366 | ||
3367 | return 0; | |
3368 | } | |
3369 | ||
3370 | /* Initialize entries for IPv6 */ | |
3371 | static int mvpp2_prs_ip6_init(struct mvpp2 *priv) | |
3372 | { | |
3373 | struct mvpp2_prs_entry pe; | |
3374 | int tid, err; | |
3375 | ||
3376 | /* Set entries for TCP, UDP and ICMP over IPv6 */ | |
3377 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP, | |
3378 | MVPP2_PRS_RI_L4_TCP, | |
3379 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3380 | if (err) | |
3381 | return err; | |
3382 | ||
3383 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP, | |
3384 | MVPP2_PRS_RI_L4_UDP, | |
3385 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3386 | if (err) | |
3387 | return err; | |
3388 | ||
3389 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6, | |
3390 | MVPP2_PRS_RI_CPU_CODE_RX_SPEC | | |
3391 | MVPP2_PRS_RI_UDF3_RX_SPECIAL, | |
3392 | MVPP2_PRS_RI_CPU_CODE_MASK | | |
3393 | MVPP2_PRS_RI_UDF3_MASK); | |
3394 | if (err) | |
3395 | return err; | |
3396 | ||
3397 | /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */ | |
3398 | /* Result Info: UDF7=1, DS lite */ | |
3399 | err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP, | |
3400 | MVPP2_PRS_RI_UDF7_IP6_LITE, | |
3401 | MVPP2_PRS_RI_UDF7_MASK); | |
3402 | if (err) | |
3403 | return err; | |
3404 | ||
3405 | /* IPv6 multicast */ | |
3406 | err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST); | |
3407 | if (err) | |
3408 | return err; | |
3409 | ||
3410 | /* Entry for checking hop limit */ | |
3411 | tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, | |
3412 | MVPP2_PE_LAST_FREE_TID); | |
3413 | if (tid < 0) | |
3414 | return tid; | |
3415 | ||
c5b2ce24 | 3416 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3417 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3418 | pe.index = tid; | |
3419 | ||
3420 | /* Finished: go to flowid generation */ | |
3421 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3422 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3423 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | | |
3424 | MVPP2_PRS_RI_DROP_MASK, | |
3425 | MVPP2_PRS_RI_L3_PROTO_MASK | | |
3426 | MVPP2_PRS_RI_DROP_MASK); | |
3427 | ||
3428 | mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); | |
3429 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3430 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3431 | ||
3432 | /* Update shadow table and hw entry */ | |
3433 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3434 | mvpp2_prs_hw_write(priv, &pe); | |
3435 | ||
3436 | /* Default IPv6 entry for unknown protocols */ | |
c5b2ce24 | 3437 | memset(&pe, 0, sizeof(pe)); |
3f518509 MW |
3438 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); |
3439 | pe.index = MVPP2_PE_IP6_PROTO_UN; | |
3440 | ||
3441 | /* Finished: go to flowid generation */ | |
3442 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3443 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3444 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3445 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3446 | /* Set L4 offset relatively to our current place */ | |
3447 | mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, | |
3448 | sizeof(struct ipv6hdr) - 4, | |
3449 | MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); | |
3450 | ||
3451 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3452 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3453 | /* Unmask all ports */ | |
3454 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3455 | ||
3456 | /* Update shadow table and hw entry */ | |
3457 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3458 | mvpp2_prs_hw_write(priv, &pe); | |
3459 | ||
3460 | /* Default IPv6 entry for unknown ext protocols */ | |
3461 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3462 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3463 | pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; | |
3464 | ||
3465 | /* Finished: go to flowid generation */ | |
3466 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); | |
3467 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); | |
3468 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, | |
3469 | MVPP2_PRS_RI_L4_PROTO_MASK); | |
3470 | ||
3471 | mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, | |
3472 | MVPP2_PRS_IPV6_EXT_AI_BIT); | |
3473 | /* Unmask all ports */ | |
3474 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3475 | ||
3476 | /* Update shadow table and hw entry */ | |
3477 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); | |
3478 | mvpp2_prs_hw_write(priv, &pe); | |
3479 | ||
3480 | /* Default IPv6 entry for unicast address */ | |
3481 | memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); | |
3482 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3483 | pe.index = MVPP2_PE_IP6_ADDR_UN; | |
3484 | ||
3485 | /* Finished: go to IPv6 again */ | |
3486 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); | |
3487 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, | |
3488 | MVPP2_PRS_RI_L3_ADDR_MASK); | |
3489 | mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, | |
3490 | MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3491 | /* Shift back to IPV6 NH */ | |
3492 | mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3493 | ||
3494 | mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); | |
3495 | /* Unmask all ports */ | |
3496 | mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); | |
3497 | ||
3498 | /* Update shadow table and hw entry */ | |
3499 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); | |
3500 | mvpp2_prs_hw_write(priv, &pe); | |
3501 | ||
3502 | return 0; | |
3503 | } | |
3504 | ||
56beda3d MC |
3505 | /* Find tcam entry with matched pair <vid,port> */ |
3506 | static int mvpp2_prs_vid_range_find(struct mvpp2 *priv, int pmap, u16 vid, | |
3507 | u16 mask) | |
3508 | { | |
3509 | unsigned char byte[2], enable[2]; | |
3510 | struct mvpp2_prs_entry pe; | |
3511 | u16 rvid, rmask; | |
3512 | int tid; | |
3513 | ||
3514 | /* Go through the all entries with MVPP2_PRS_LU_VID */ | |
3515 | for (tid = MVPP2_PE_VID_FILT_RANGE_START; | |
3516 | tid <= MVPP2_PE_VID_FILT_RANGE_END; tid++) { | |
3517 | if (!priv->prs_shadow[tid].valid || | |
3518 | priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VID) | |
3519 | continue; | |
3520 | ||
47e0e14e | 3521 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
0c6d9b44 | 3522 | |
56beda3d MC |
3523 | mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]); |
3524 | mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]); | |
3525 | ||
3526 | rvid = ((byte[0] & 0xf) << 8) + byte[1]; | |
3527 | rmask = ((enable[0] & 0xf) << 8) + enable[1]; | |
3528 | ||
3529 | if (rvid != vid || rmask != mask) | |
3530 | continue; | |
3531 | ||
3532 | return tid; | |
3533 | } | |
3534 | ||
0c6d9b44 | 3535 | return -ENOENT; |
56beda3d MC |
3536 | } |
3537 | ||
3538 | /* Write parser entry for VID filtering */ | |
3539 | static int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid) | |
3540 | { | |
3541 | unsigned int vid_start = MVPP2_PE_VID_FILT_RANGE_START + | |
3542 | port->id * MVPP2_PRS_VLAN_FILT_MAX; | |
3543 | unsigned int mask = 0xfff, reg_val, shift; | |
3544 | struct mvpp2 *priv = port->priv; | |
3545 | struct mvpp2_prs_entry pe; | |
3546 | int tid; | |
3547 | ||
0c6d9b44 MC |
3548 | memset(&pe, 0, sizeof(pe)); |
3549 | ||
56beda3d MC |
3550 | /* Scan TCAM and see if entry with this <vid,port> already exist */ |
3551 | tid = mvpp2_prs_vid_range_find(priv, (1 << port->id), vid, mask); | |
3552 | ||
3553 | reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id)); | |
3554 | if (reg_val & MVPP2_DSA_EXTENDED) | |
3555 | shift = MVPP2_VLAN_TAG_EDSA_LEN; | |
3556 | else | |
3557 | shift = MVPP2_VLAN_TAG_LEN; | |
3558 | ||
3559 | /* No such entry */ | |
0c6d9b44 | 3560 | if (tid < 0) { |
56beda3d MC |
3561 | |
3562 | /* Go through all entries from first to last in vlan range */ | |
3563 | tid = mvpp2_prs_tcam_first_free(priv, vid_start, | |
3564 | vid_start + | |
3565 | MVPP2_PRS_VLAN_FILT_MAX_ENTRY); | |
3566 | ||
3567 | /* There isn't room for a new VID filter */ | |
3568 | if (tid < 0) | |
3569 | return tid; | |
3570 | ||
3571 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
3572 | pe.index = tid; | |
3573 | ||
3574 | /* Mask all ports */ | |
3575 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
3576 | } else { | |
47e0e14e | 3577 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
56beda3d MC |
3578 | } |
3579 | ||
3580 | /* Enable the current port */ | |
3581 | mvpp2_prs_tcam_port_set(&pe, port->id, true); | |
3582 | ||
3583 | /* Continue - set next lookup */ | |
3584 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3585 | ||
3586 | /* Skip VLAN header - Set offset to 4 or 8 bytes */ | |
3587 | mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3588 | ||
3589 | /* Set match on VID */ | |
3590 | mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid); | |
3591 | ||
3592 | /* Clear all ai bits for next iteration */ | |
3593 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
3594 | ||
3595 | /* Update shadow table */ | |
3596 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
3597 | mvpp2_prs_hw_write(priv, &pe); | |
3598 | ||
3599 | return 0; | |
3600 | } | |
3601 | ||
3602 | /* Write parser entry for VID filtering */ | |
3603 | static void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid) | |
3604 | { | |
3605 | struct mvpp2 *priv = port->priv; | |
3606 | int tid; | |
3607 | ||
3608 | /* Scan TCAM and see if entry with this <vid,port> already exist */ | |
3609 | tid = mvpp2_prs_vid_range_find(priv, (1 << port->id), vid, 0xfff); | |
3610 | ||
3611 | /* No such entry */ | |
0c6d9b44 | 3612 | if (tid < 0) |
56beda3d MC |
3613 | return; |
3614 | ||
3615 | mvpp2_prs_hw_inv(priv, tid); | |
3616 | priv->prs_shadow[tid].valid = false; | |
3617 | } | |
3618 | ||
3619 | /* Remove all existing VID filters on this port */ | |
3620 | static void mvpp2_prs_vid_remove_all(struct mvpp2_port *port) | |
3621 | { | |
3622 | struct mvpp2 *priv = port->priv; | |
3623 | int tid; | |
3624 | ||
3625 | for (tid = MVPP2_PRS_VID_PORT_FIRST(port->id); | |
3626 | tid <= MVPP2_PRS_VID_PORT_LAST(port->id); tid++) { | |
3627 | if (priv->prs_shadow[tid].valid) | |
3628 | mvpp2_prs_vid_entry_remove(port, tid); | |
3629 | } | |
3630 | } | |
3631 | ||
3632 | /* Remove VID filering entry for this port */ | |
3633 | static void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port) | |
3634 | { | |
3635 | unsigned int tid = MVPP2_PRS_VID_PORT_DFLT(port->id); | |
3636 | struct mvpp2 *priv = port->priv; | |
3637 | ||
3638 | /* Invalidate the guard entry */ | |
3639 | mvpp2_prs_hw_inv(priv, tid); | |
3640 | ||
3641 | priv->prs_shadow[tid].valid = false; | |
3642 | } | |
3643 | ||
3644 | /* Add guard entry that drops packets when no VID is matched on this port */ | |
3645 | static void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port) | |
3646 | { | |
3647 | unsigned int tid = MVPP2_PRS_VID_PORT_DFLT(port->id); | |
3648 | struct mvpp2 *priv = port->priv; | |
3649 | unsigned int reg_val, shift; | |
3650 | struct mvpp2_prs_entry pe; | |
3651 | ||
3652 | if (priv->prs_shadow[tid].valid) | |
3653 | return; | |
3654 | ||
3655 | memset(&pe, 0, sizeof(pe)); | |
3656 | ||
3657 | pe.index = tid; | |
3658 | ||
3659 | reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id)); | |
3660 | if (reg_val & MVPP2_DSA_EXTENDED) | |
3661 | shift = MVPP2_VLAN_TAG_EDSA_LEN; | |
3662 | else | |
3663 | shift = MVPP2_VLAN_TAG_LEN; | |
3664 | ||
3665 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); | |
3666 | ||
3667 | /* Mask all ports */ | |
3668 | mvpp2_prs_tcam_port_map_set(&pe, 0); | |
3669 | ||
3670 | /* Update port mask */ | |
3671 | mvpp2_prs_tcam_port_set(&pe, port->id, true); | |
3672 | ||
3673 | /* Continue - set next lookup */ | |
3674 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); | |
3675 | ||
3676 | /* Skip VLAN header - Set offset to 4 or 8 bytes */ | |
3677 | mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); | |
3678 | ||
3679 | /* Drop VLAN packets that don't belong to any VIDs on this port */ | |
3680 | mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, | |
3681 | MVPP2_PRS_RI_DROP_MASK); | |
3682 | ||
3683 | /* Clear all ai bits for next iteration */ | |
3684 | mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); | |
3685 | ||
3686 | /* Update shadow table */ | |
3687 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); | |
3688 | mvpp2_prs_hw_write(priv, &pe); | |
3689 | } | |
3690 | ||
3f518509 MW |
3691 | /* Parser default initialization */ |
3692 | static int mvpp2_prs_default_init(struct platform_device *pdev, | |
3693 | struct mvpp2 *priv) | |
3694 | { | |
3695 | int err, index, i; | |
3696 | ||
3697 | /* Enable tcam table */ | |
3698 | mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK); | |
3699 | ||
3700 | /* Clear all tcam and sram entries */ | |
3701 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) { | |
3702 | mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); | |
3703 | for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) | |
3704 | mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0); | |
3705 | ||
3706 | mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); | |
3707 | for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) | |
3708 | mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); | |
3709 | } | |
3710 | ||
3711 | /* Invalidate all tcam entries */ | |
3712 | for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) | |
3713 | mvpp2_prs_hw_inv(priv, index); | |
3714 | ||
3715 | priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE, | |
37df25e8 | 3716 | sizeof(*priv->prs_shadow), |
3f518509 MW |
3717 | GFP_KERNEL); |
3718 | if (!priv->prs_shadow) | |
3719 | return -ENOMEM; | |
3720 | ||
3721 | /* Always start from lookup = 0 */ | |
3722 | for (index = 0; index < MVPP2_MAX_PORTS; index++) | |
3723 | mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH, | |
3724 | MVPP2_PRS_PORT_LU_MAX, 0); | |
3725 | ||
3726 | mvpp2_prs_def_flow_init(priv); | |
3727 | ||
3728 | mvpp2_prs_mh_init(priv); | |
3729 | ||
3730 | mvpp2_prs_mac_init(priv); | |
3731 | ||
3732 | mvpp2_prs_dsa_init(priv); | |
3733 | ||
56beda3d MC |
3734 | mvpp2_prs_vid_init(priv); |
3735 | ||
3f518509 MW |
3736 | err = mvpp2_prs_etype_init(priv); |
3737 | if (err) | |
3738 | return err; | |
3739 | ||
3740 | err = mvpp2_prs_vlan_init(pdev, priv); | |
3741 | if (err) | |
3742 | return err; | |
3743 | ||
3744 | err = mvpp2_prs_pppoe_init(priv); | |
3745 | if (err) | |
3746 | return err; | |
3747 | ||
3748 | err = mvpp2_prs_ip6_init(priv); | |
3749 | if (err) | |
3750 | return err; | |
3751 | ||
3752 | err = mvpp2_prs_ip4_init(priv); | |
3753 | if (err) | |
3754 | return err; | |
3755 | ||
3756 | return 0; | |
3757 | } | |
3758 | ||
3759 | /* Compare MAC DA with tcam entry data */ | |
3760 | static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, | |
3761 | const u8 *da, unsigned char *mask) | |
3762 | { | |
3763 | unsigned char tcam_byte, tcam_mask; | |
3764 | int index; | |
3765 | ||
3766 | for (index = 0; index < ETH_ALEN; index++) { | |
3767 | mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); | |
3768 | if (tcam_mask != mask[index]) | |
3769 | return false; | |
3770 | ||
3771 | if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) | |
3772 | return false; | |
3773 | } | |
3774 | ||
3775 | return true; | |
3776 | } | |
3777 | ||
3778 | /* Find tcam entry with matched pair <MAC DA, port> */ | |
0c6d9b44 | 3779 | static int |
3f518509 MW |
3780 | mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da, |
3781 | unsigned char *mask, int udf_type) | |
3782 | { | |
0c6d9b44 | 3783 | struct mvpp2_prs_entry pe; |
3f518509 MW |
3784 | int tid; |
3785 | ||
3f518509 | 3786 | /* Go through the all entires with MVPP2_PRS_LU_MAC */ |
10fea26c MC |
3787 | for (tid = MVPP2_PE_MAC_RANGE_START; |
3788 | tid <= MVPP2_PE_MAC_RANGE_END; tid++) { | |
3f518509 MW |
3789 | unsigned int entry_pmap; |
3790 | ||
3791 | if (!priv->prs_shadow[tid].valid || | |
3792 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3793 | (priv->prs_shadow[tid].udf != udf_type)) | |
3794 | continue; | |
3795 | ||
0c6d9b44 MC |
3796 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
3797 | entry_pmap = mvpp2_prs_tcam_port_map_get(&pe); | |
3f518509 | 3798 | |
0c6d9b44 | 3799 | if (mvpp2_prs_mac_range_equals(&pe, da, mask) && |
3f518509 | 3800 | entry_pmap == pmap) |
0c6d9b44 | 3801 | return tid; |
3f518509 | 3802 | } |
3f518509 | 3803 | |
0c6d9b44 | 3804 | return -ENOENT; |
3f518509 MW |
3805 | } |
3806 | ||
3807 | /* Update parser's mac da entry */ | |
ce2a27c7 MC |
3808 | static int mvpp2_prs_mac_da_accept(struct mvpp2_port *port, const u8 *da, |
3809 | bool add) | |
3f518509 | 3810 | { |
3f518509 | 3811 | unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
ce2a27c7 MC |
3812 | struct mvpp2 *priv = port->priv; |
3813 | unsigned int pmap, len, ri; | |
0c6d9b44 | 3814 | struct mvpp2_prs_entry pe; |
3f518509 MW |
3815 | int tid; |
3816 | ||
0c6d9b44 MC |
3817 | memset(&pe, 0, sizeof(pe)); |
3818 | ||
3f518509 | 3819 | /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ |
0c6d9b44 MC |
3820 | tid = mvpp2_prs_mac_da_range_find(priv, BIT(port->id), da, mask, |
3821 | MVPP2_PRS_UDF_MAC_DEF); | |
3f518509 MW |
3822 | |
3823 | /* No such entry */ | |
0c6d9b44 | 3824 | if (tid < 0) { |
3f518509 MW |
3825 | if (!add) |
3826 | return 0; | |
3827 | ||
3828 | /* Create new TCAM entry */ | |
3f518509 | 3829 | /* Go through the all entries from first to last */ |
10fea26c MC |
3830 | tid = mvpp2_prs_tcam_first_free(priv, |
3831 | MVPP2_PE_MAC_RANGE_START, | |
3832 | MVPP2_PE_MAC_RANGE_END); | |
3f518509 MW |
3833 | if (tid < 0) |
3834 | return tid; | |
3835 | ||
0c6d9b44 | 3836 | pe.index = tid; |
3f518509 MW |
3837 | |
3838 | /* Mask all ports */ | |
0c6d9b44 MC |
3839 | mvpp2_prs_tcam_port_map_set(&pe, 0); |
3840 | } else { | |
3841 | mvpp2_prs_init_from_hw(priv, &pe, tid); | |
3f518509 MW |
3842 | } |
3843 | ||
0c6d9b44 MC |
3844 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); |
3845 | ||
3f518509 | 3846 | /* Update port mask */ |
0c6d9b44 | 3847 | mvpp2_prs_tcam_port_set(&pe, port->id, add); |
3f518509 MW |
3848 | |
3849 | /* Invalidate the entry if no ports are left enabled */ | |
0c6d9b44 | 3850 | pmap = mvpp2_prs_tcam_port_map_get(&pe); |
3f518509 | 3851 | if (pmap == 0) { |
0c6d9b44 | 3852 | if (add) |
c2bb7bc5 | 3853 | return -EINVAL; |
0c6d9b44 MC |
3854 | |
3855 | mvpp2_prs_hw_inv(priv, pe.index); | |
3856 | priv->prs_shadow[pe.index].valid = false; | |
3f518509 MW |
3857 | return 0; |
3858 | } | |
3859 | ||
3860 | /* Continue - set next lookup */ | |
0c6d9b44 | 3861 | mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); |
3f518509 MW |
3862 | |
3863 | /* Set match on DA */ | |
3864 | len = ETH_ALEN; | |
3865 | while (len--) | |
0c6d9b44 | 3866 | mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); |
3f518509 MW |
3867 | |
3868 | /* Set result info bits */ | |
10fea26c | 3869 | if (is_broadcast_ether_addr(da)) { |
3f518509 | 3870 | ri = MVPP2_PRS_RI_L2_BCAST; |
10fea26c | 3871 | } else if (is_multicast_ether_addr(da)) { |
3f518509 | 3872 | ri = MVPP2_PRS_RI_L2_MCAST; |
10fea26c MC |
3873 | } else { |
3874 | ri = MVPP2_PRS_RI_L2_UCAST; | |
3875 | ||
3876 | if (ether_addr_equal(da, port->dev->dev_addr)) | |
3877 | ri |= MVPP2_PRS_RI_MAC_ME_MASK; | |
3878 | } | |
3f518509 | 3879 | |
0c6d9b44 | 3880 | mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | |
3f518509 | 3881 | MVPP2_PRS_RI_MAC_ME_MASK); |
0c6d9b44 | 3882 | mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK | |
3f518509 MW |
3883 | MVPP2_PRS_RI_MAC_ME_MASK); |
3884 | ||
3885 | /* Shift to ethertype */ | |
0c6d9b44 | 3886 | mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, |
3f518509 MW |
3887 | MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); |
3888 | ||
3889 | /* Update shadow table and hw entry */ | |
0c6d9b44 MC |
3890 | priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF; |
3891 | mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); | |
3892 | mvpp2_prs_hw_write(priv, &pe); | |
3f518509 MW |
3893 | |
3894 | return 0; | |
3895 | } | |
3896 | ||
3897 | static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da) | |
3898 | { | |
3899 | struct mvpp2_port *port = netdev_priv(dev); | |
3900 | int err; | |
3901 | ||
3902 | /* Remove old parser entry */ | |
ce2a27c7 | 3903 | err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, false); |
3f518509 MW |
3904 | if (err) |
3905 | return err; | |
3906 | ||
3907 | /* Add new parser entry */ | |
ce2a27c7 | 3908 | err = mvpp2_prs_mac_da_accept(port, da, true); |
3f518509 MW |
3909 | if (err) |
3910 | return err; | |
3911 | ||
3912 | /* Set addr in the device */ | |
3913 | ether_addr_copy(dev->dev_addr, da); | |
3914 | ||
3915 | return 0; | |
3916 | } | |
3917 | ||
10fea26c | 3918 | static void mvpp2_prs_mac_del_all(struct mvpp2_port *port) |
3f518509 | 3919 | { |
10fea26c | 3920 | struct mvpp2 *priv = port->priv; |
3f518509 | 3921 | struct mvpp2_prs_entry pe; |
10fea26c | 3922 | unsigned long pmap; |
3f518509 MW |
3923 | int index, tid; |
3924 | ||
10fea26c MC |
3925 | for (tid = MVPP2_PE_MAC_RANGE_START; |
3926 | tid <= MVPP2_PE_MAC_RANGE_END; tid++) { | |
3f518509 MW |
3927 | unsigned char da[ETH_ALEN], da_mask[ETH_ALEN]; |
3928 | ||
3929 | if (!priv->prs_shadow[tid].valid || | |
3930 | (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || | |
3931 | (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF)) | |
3932 | continue; | |
3933 | ||
47e0e14e | 3934 | mvpp2_prs_init_from_hw(priv, &pe, tid); |
3f518509 | 3935 | |
10fea26c MC |
3936 | pmap = mvpp2_prs_tcam_port_map_get(&pe); |
3937 | ||
3938 | /* We only want entries active on this port */ | |
3939 | if (!test_bit(port->id, &pmap)) | |
3940 | continue; | |
3941 | ||
3f518509 MW |
3942 | /* Read mac addr from entry */ |
3943 | for (index = 0; index < ETH_ALEN; index++) | |
3944 | mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], | |
3945 | &da_mask[index]); | |
3946 | ||
10fea26c MC |
3947 | /* Special cases : Don't remove broadcast and port's own |
3948 | * address | |
3949 | */ | |
3950 | if (is_broadcast_ether_addr(da) || | |
3951 | ether_addr_equal(da, port->dev->dev_addr)) | |
3952 | continue; | |
3953 | ||
3954 | /* Remove entry from TCAM */ | |
3955 | mvpp2_prs_mac_da_accept(port, da, false); | |
3f518509 MW |
3956 | } |
3957 | } | |
3958 | ||
3959 | static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type) | |
3960 | { | |
3961 | switch (type) { | |
3962 | case MVPP2_TAG_TYPE_EDSA: | |
3963 | /* Add port to EDSA entries */ | |
3964 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3965 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3966 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3967 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3968 | /* Remove port from DSA entries */ | |
3969 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3970 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3971 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3972 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3973 | break; | |
3974 | ||
3975 | case MVPP2_TAG_TYPE_DSA: | |
3976 | /* Add port to DSA entries */ | |
3977 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3978 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3979 | mvpp2_prs_dsa_tag_set(priv, port, true, | |
3980 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3981 | /* Remove port from EDSA entries */ | |
3982 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3983 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3984 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3985 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3986 | break; | |
3987 | ||
3988 | case MVPP2_TAG_TYPE_MH: | |
3989 | case MVPP2_TAG_TYPE_NONE: | |
3990 | /* Remove port form EDSA and DSA entries */ | |
3991 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3992 | MVPP2_PRS_TAGGED, MVPP2_PRS_DSA); | |
3993 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3994 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA); | |
3995 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3996 | MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA); | |
3997 | mvpp2_prs_dsa_tag_set(priv, port, false, | |
3998 | MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA); | |
3999 | break; | |
4000 | ||
4001 | default: | |
4002 | if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA)) | |
4003 | return -EINVAL; | |
4004 | } | |
4005 | ||
4006 | return 0; | |
4007 | } | |
4008 | ||
4009 | /* Set prs flow for the port */ | |
4010 | static int mvpp2_prs_def_flow(struct mvpp2_port *port) | |
4011 | { | |
0c6d9b44 | 4012 | struct mvpp2_prs_entry pe; |
3f518509 MW |
4013 | int tid; |
4014 | ||
0c6d9b44 MC |
4015 | memset(&pe, 0, sizeof(pe)); |
4016 | ||
4017 | tid = mvpp2_prs_flow_find(port->priv, port->id); | |
3f518509 MW |
4018 | |
4019 | /* Such entry not exist */ | |
0c6d9b44 | 4020 | if (tid < 0) { |
3f518509 MW |
4021 | /* Go through the all entires from last to first */ |
4022 | tid = mvpp2_prs_tcam_first_free(port->priv, | |
4023 | MVPP2_PE_LAST_FREE_TID, | |
4024 | MVPP2_PE_FIRST_FREE_TID); | |
4025 | if (tid < 0) | |
4026 | return tid; | |
4027 | ||
0c6d9b44 | 4028 | pe.index = tid; |
3f518509 MW |
4029 | |
4030 | /* Set flow ID*/ | |
0c6d9b44 MC |
4031 | mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK); |
4032 | mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); | |
3f518509 MW |
4033 | |
4034 | /* Update shadow table */ | |
0c6d9b44 MC |
4035 | mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS); |
4036 | } else { | |
4037 | mvpp2_prs_init_from_hw(port->priv, &pe, tid); | |
3f518509 MW |
4038 | } |
4039 | ||
0c6d9b44 MC |
4040 | mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); |
4041 | mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id)); | |
4042 | mvpp2_prs_hw_write(port->priv, &pe); | |
3f518509 MW |
4043 | |
4044 | return 0; | |
4045 | } | |
4046 | ||
4047 | /* Classifier configuration routines */ | |
4048 | ||
4049 | /* Update classification flow table registers */ | |
4050 | static void mvpp2_cls_flow_write(struct mvpp2 *priv, | |
4051 | struct mvpp2_cls_flow_entry *fe) | |
4052 | { | |
4053 | mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); | |
4054 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); | |
4055 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); | |
4056 | mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); | |
4057 | } | |
4058 | ||
4059 | /* Update classification lookup table register */ | |
4060 | static void mvpp2_cls_lookup_write(struct mvpp2 *priv, | |
4061 | struct mvpp2_cls_lookup_entry *le) | |
4062 | { | |
4063 | u32 val; | |
4064 | ||
4065 | val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; | |
4066 | mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); | |
4067 | mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); | |
4068 | } | |
4069 | ||
4070 | /* Classifier default initialization */ | |
4071 | static void mvpp2_cls_init(struct mvpp2 *priv) | |
4072 | { | |
4073 | struct mvpp2_cls_lookup_entry le; | |
4074 | struct mvpp2_cls_flow_entry fe; | |
4075 | int index; | |
4076 | ||
4077 | /* Enable classifier */ | |
4078 | mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); | |
4079 | ||
4080 | /* Clear classifier flow table */ | |
e8f967c3 | 4081 | memset(&fe.data, 0, sizeof(fe.data)); |
3f518509 MW |
4082 | for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { |
4083 | fe.index = index; | |
4084 | mvpp2_cls_flow_write(priv, &fe); | |
4085 | } | |
4086 | ||
4087 | /* Clear classifier lookup table */ | |
4088 | le.data = 0; | |
4089 | for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) { | |
4090 | le.lkpid = index; | |
4091 | le.way = 0; | |
4092 | mvpp2_cls_lookup_write(priv, &le); | |
4093 | ||
4094 | le.way = 1; | |
4095 | mvpp2_cls_lookup_write(priv, &le); | |
4096 | } | |
4097 | } | |
4098 | ||
4099 | static void mvpp2_cls_port_config(struct mvpp2_port *port) | |
4100 | { | |
4101 | struct mvpp2_cls_lookup_entry le; | |
4102 | u32 val; | |
4103 | ||
4104 | /* Set way for the port */ | |
4105 | val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); | |
4106 | val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); | |
4107 | mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); | |
4108 | ||
4109 | /* Pick the entry to be accessed in lookup ID decoding table | |
4110 | * according to the way and lkpid. | |
4111 | */ | |
4112 | le.lkpid = port->id; | |
4113 | le.way = 0; | |
4114 | le.data = 0; | |
4115 | ||
4116 | /* Set initial CPU queue for receiving packets */ | |
4117 | le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK; | |
4118 | le.data |= port->first_rxq; | |
4119 | ||
4120 | /* Disable classification engines */ | |
4121 | le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; | |
4122 | ||
4123 | /* Update lookup ID table entry */ | |
4124 | mvpp2_cls_lookup_write(port->priv, &le); | |
4125 | } | |
4126 | ||
4127 | /* Set CPU queue number for oversize packets */ | |
4128 | static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) | |
4129 | { | |
4130 | u32 val; | |
4131 | ||
4132 | mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), | |
4133 | port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); | |
4134 | ||
4135 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), | |
4136 | (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); | |
4137 | ||
4138 | val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); | |
4139 | val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); | |
4140 | mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); | |
4141 | } | |
4142 | ||
0e037281 TP |
4143 | static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) |
4144 | { | |
4145 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
4146 | return netdev_alloc_frag(pool->frag_size); | |
4147 | else | |
4148 | return kmalloc(pool->frag_size, GFP_ATOMIC); | |
4149 | } | |
4150 | ||
4151 | static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) | |
4152 | { | |
4153 | if (likely(pool->frag_size <= PAGE_SIZE)) | |
4154 | skb_free_frag(data); | |
4155 | else | |
4156 | kfree(data); | |
4157 | } | |
4158 | ||
3f518509 MW |
4159 | /* Buffer Manager configuration routines */ |
4160 | ||
4161 | /* Create pool */ | |
4162 | static int mvpp2_bm_pool_create(struct platform_device *pdev, | |
4163 | struct mvpp2 *priv, | |
4164 | struct mvpp2_bm_pool *bm_pool, int size) | |
4165 | { | |
3f518509 MW |
4166 | u32 val; |
4167 | ||
d01524d8 TP |
4168 | /* Number of buffer pointers must be a multiple of 16, as per |
4169 | * hardware constraints | |
4170 | */ | |
4171 | if (!IS_ALIGNED(size, 16)) | |
4172 | return -EINVAL; | |
4173 | ||
4174 | /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 | |
4175 | * bytes per buffer pointer | |
4176 | */ | |
4177 | if (priv->hw_version == MVPP21) | |
4178 | bm_pool->size_bytes = 2 * sizeof(u32) * size; | |
4179 | else | |
4180 | bm_pool->size_bytes = 2 * sizeof(u64) * size; | |
4181 | ||
4182 | bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, | |
20396136 | 4183 | &bm_pool->dma_addr, |
3f518509 MW |
4184 | GFP_KERNEL); |
4185 | if (!bm_pool->virt_addr) | |
4186 | return -ENOMEM; | |
4187 | ||
d3158807 TP |
4188 | if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, |
4189 | MVPP2_BM_POOL_PTR_ALIGN)) { | |
d01524d8 TP |
4190 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
4191 | bm_pool->virt_addr, bm_pool->dma_addr); | |
3f518509 MW |
4192 | dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", |
4193 | bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); | |
4194 | return -ENOMEM; | |
4195 | } | |
4196 | ||
4197 | mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), | |
d01524d8 | 4198 | lower_32_bits(bm_pool->dma_addr)); |
3f518509 MW |
4199 | mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); |
4200 | ||
4201 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
4202 | val |= MVPP2_BM_START_MASK; | |
4203 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
4204 | ||
3f518509 MW |
4205 | bm_pool->size = size; |
4206 | bm_pool->pkt_size = 0; | |
4207 | bm_pool->buf_num = 0; | |
3f518509 MW |
4208 | |
4209 | return 0; | |
4210 | } | |
4211 | ||
4212 | /* Set pool buffer size */ | |
4213 | static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, | |
4214 | struct mvpp2_bm_pool *bm_pool, | |
4215 | int buf_size) | |
4216 | { | |
4217 | u32 val; | |
4218 | ||
4219 | bm_pool->buf_size = buf_size; | |
4220 | ||
4221 | val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); | |
4222 | mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); | |
4223 | } | |
4224 | ||
d01524d8 TP |
4225 | static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, |
4226 | struct mvpp2_bm_pool *bm_pool, | |
4227 | dma_addr_t *dma_addr, | |
4228 | phys_addr_t *phys_addr) | |
4229 | { | |
a704bb5c | 4230 | int cpu = get_cpu(); |
a786841d TP |
4231 | |
4232 | *dma_addr = mvpp2_percpu_read(priv, cpu, | |
4233 | MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); | |
4234 | *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG); | |
d01524d8 TP |
4235 | |
4236 | if (priv->hw_version == MVPP22) { | |
4237 | u32 val; | |
4238 | u32 dma_addr_highbits, phys_addr_highbits; | |
4239 | ||
a786841d | 4240 | val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC); |
d01524d8 TP |
4241 | dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); |
4242 | phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> | |
4243 | MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; | |
4244 | ||
4245 | if (sizeof(dma_addr_t) == 8) | |
4246 | *dma_addr |= (u64)dma_addr_highbits << 32; | |
4247 | ||
4248 | if (sizeof(phys_addr_t) == 8) | |
4249 | *phys_addr |= (u64)phys_addr_highbits << 32; | |
4250 | } | |
a704bb5c TP |
4251 | |
4252 | put_cpu(); | |
d01524d8 TP |
4253 | } |
4254 | ||
7861f12b | 4255 | /* Free all buffers from the pool */ |
4229d502 | 4256 | static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, |
effbf5f5 | 4257 | struct mvpp2_bm_pool *bm_pool, int buf_num) |
3f518509 MW |
4258 | { |
4259 | int i; | |
4260 | ||
effbf5f5 SC |
4261 | if (buf_num > bm_pool->buf_num) { |
4262 | WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", | |
4263 | bm_pool->id, buf_num); | |
4264 | buf_num = bm_pool->buf_num; | |
4265 | } | |
4266 | ||
4267 | for (i = 0; i < buf_num; i++) { | |
20396136 | 4268 | dma_addr_t buf_dma_addr; |
4e4a105f TP |
4269 | phys_addr_t buf_phys_addr; |
4270 | void *data; | |
3f518509 | 4271 | |
d01524d8 TP |
4272 | mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, |
4273 | &buf_dma_addr, &buf_phys_addr); | |
4229d502 | 4274 | |
20396136 | 4275 | dma_unmap_single(dev, buf_dma_addr, |
4229d502 MW |
4276 | bm_pool->buf_size, DMA_FROM_DEVICE); |
4277 | ||
4e4a105f TP |
4278 | data = (void *)phys_to_virt(buf_phys_addr); |
4279 | if (!data) | |
3f518509 | 4280 | break; |
0e037281 | 4281 | |
4e4a105f | 4282 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
4283 | } |
4284 | ||
4285 | /* Update BM driver with number of buffers removed from pool */ | |
4286 | bm_pool->buf_num -= i; | |
3f518509 MW |
4287 | } |
4288 | ||
effbf5f5 | 4289 | /* Check number of buffers in BM pool */ |
6e61e10a | 4290 | static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) |
effbf5f5 SC |
4291 | { |
4292 | int buf_num = 0; | |
4293 | ||
4294 | buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & | |
4295 | MVPP22_BM_POOL_PTRS_NUM_MASK; | |
4296 | buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & | |
4297 | MVPP2_BM_BPPI_PTR_NUM_MASK; | |
4298 | ||
4299 | /* HW has one buffer ready which is not reflected in the counters */ | |
4300 | if (buf_num) | |
4301 | buf_num += 1; | |
4302 | ||
4303 | return buf_num; | |
4304 | } | |
4305 | ||
3f518509 MW |
4306 | /* Cleanup pool */ |
4307 | static int mvpp2_bm_pool_destroy(struct platform_device *pdev, | |
4308 | struct mvpp2 *priv, | |
4309 | struct mvpp2_bm_pool *bm_pool) | |
4310 | { | |
effbf5f5 | 4311 | int buf_num; |
3f518509 MW |
4312 | u32 val; |
4313 | ||
effbf5f5 SC |
4314 | buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); |
4315 | mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); | |
4316 | ||
4317 | /* Check buffer counters after free */ | |
4318 | buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); | |
4319 | if (buf_num) { | |
4320 | WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", | |
4321 | bm_pool->id, bm_pool->buf_num); | |
3f518509 MW |
4322 | return 0; |
4323 | } | |
4324 | ||
4325 | val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); | |
4326 | val |= MVPP2_BM_STOP_MASK; | |
4327 | mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); | |
4328 | ||
d01524d8 | 4329 | dma_free_coherent(&pdev->dev, bm_pool->size_bytes, |
3f518509 | 4330 | bm_pool->virt_addr, |
20396136 | 4331 | bm_pool->dma_addr); |
3f518509 MW |
4332 | return 0; |
4333 | } | |
4334 | ||
4335 | static int mvpp2_bm_pools_init(struct platform_device *pdev, | |
4336 | struct mvpp2 *priv) | |
4337 | { | |
4338 | int i, err, size; | |
4339 | struct mvpp2_bm_pool *bm_pool; | |
4340 | ||
4341 | /* Create all pools with maximum size */ | |
4342 | size = MVPP2_BM_POOL_SIZE_MAX; | |
4343 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
4344 | bm_pool = &priv->bm_pools[i]; | |
4345 | bm_pool->id = i; | |
4346 | err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); | |
4347 | if (err) | |
4348 | goto err_unroll_pools; | |
4349 | mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); | |
4350 | } | |
4351 | return 0; | |
4352 | ||
4353 | err_unroll_pools: | |
4354 | dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); | |
4355 | for (i = i - 1; i >= 0; i--) | |
4356 | mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); | |
4357 | return err; | |
4358 | } | |
4359 | ||
4360 | static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) | |
4361 | { | |
4362 | int i, err; | |
4363 | ||
4364 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
4365 | /* Mask BM all interrupts */ | |
4366 | mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); | |
4367 | /* Clear BM cause register */ | |
4368 | mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); | |
4369 | } | |
4370 | ||
4371 | /* Allocate and initialize BM pools */ | |
4372 | priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, | |
81f915eb | 4373 | sizeof(*priv->bm_pools), GFP_KERNEL); |
3f518509 MW |
4374 | if (!priv->bm_pools) |
4375 | return -ENOMEM; | |
4376 | ||
4377 | err = mvpp2_bm_pools_init(pdev, priv); | |
4378 | if (err < 0) | |
4379 | return err; | |
4380 | return 0; | |
4381 | } | |
4382 | ||
01d04936 SC |
4383 | static void mvpp2_setup_bm_pool(void) |
4384 | { | |
4385 | /* Short pool */ | |
4386 | mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; | |
4387 | mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; | |
4388 | ||
4389 | /* Long pool */ | |
4390 | mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; | |
4391 | mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; | |
576193f2 SC |
4392 | |
4393 | /* Jumbo pool */ | |
4394 | mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; | |
4395 | mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; | |
01d04936 SC |
4396 | } |
4397 | ||
3f518509 MW |
4398 | /* Attach long pool to rxq */ |
4399 | static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, | |
4400 | int lrxq, int long_pool) | |
4401 | { | |
5eac892a | 4402 | u32 val, mask; |
3f518509 MW |
4403 | int prxq; |
4404 | ||
4405 | /* Get queue physical ID */ | |
4406 | prxq = port->rxqs[lrxq]->id; | |
4407 | ||
5eac892a TP |
4408 | if (port->priv->hw_version == MVPP21) |
4409 | mask = MVPP21_RXQ_POOL_LONG_MASK; | |
4410 | else | |
4411 | mask = MVPP22_RXQ_POOL_LONG_MASK; | |
3f518509 | 4412 | |
5eac892a TP |
4413 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
4414 | val &= ~mask; | |
4415 | val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; | |
3f518509 MW |
4416 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
4417 | } | |
4418 | ||
4419 | /* Attach short pool to rxq */ | |
4420 | static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, | |
4421 | int lrxq, int short_pool) | |
4422 | { | |
5eac892a | 4423 | u32 val, mask; |
3f518509 MW |
4424 | int prxq; |
4425 | ||
4426 | /* Get queue physical ID */ | |
4427 | prxq = port->rxqs[lrxq]->id; | |
4428 | ||
5eac892a TP |
4429 | if (port->priv->hw_version == MVPP21) |
4430 | mask = MVPP21_RXQ_POOL_SHORT_MASK; | |
4431 | else | |
4432 | mask = MVPP22_RXQ_POOL_SHORT_MASK; | |
3f518509 | 4433 | |
5eac892a TP |
4434 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); |
4435 | val &= ~mask; | |
4436 | val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; | |
3f518509 MW |
4437 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); |
4438 | } | |
4439 | ||
0e037281 TP |
4440 | static void *mvpp2_buf_alloc(struct mvpp2_port *port, |
4441 | struct mvpp2_bm_pool *bm_pool, | |
20396136 | 4442 | dma_addr_t *buf_dma_addr, |
4e4a105f | 4443 | phys_addr_t *buf_phys_addr, |
0e037281 | 4444 | gfp_t gfp_mask) |
3f518509 | 4445 | { |
20396136 | 4446 | dma_addr_t dma_addr; |
0e037281 | 4447 | void *data; |
3f518509 | 4448 | |
0e037281 TP |
4449 | data = mvpp2_frag_alloc(bm_pool); |
4450 | if (!data) | |
3f518509 MW |
4451 | return NULL; |
4452 | ||
20396136 TP |
4453 | dma_addr = dma_map_single(port->dev->dev.parent, data, |
4454 | MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), | |
4455 | DMA_FROM_DEVICE); | |
4456 | if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { | |
0e037281 | 4457 | mvpp2_frag_free(bm_pool, data); |
3f518509 MW |
4458 | return NULL; |
4459 | } | |
20396136 | 4460 | *buf_dma_addr = dma_addr; |
4e4a105f | 4461 | *buf_phys_addr = virt_to_phys(data); |
3f518509 | 4462 | |
0e037281 | 4463 | return data; |
3f518509 MW |
4464 | } |
4465 | ||
3f518509 MW |
4466 | /* Release buffer to BM */ |
4467 | static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, | |
20396136 | 4468 | dma_addr_t buf_dma_addr, |
4e4a105f | 4469 | phys_addr_t buf_phys_addr) |
3f518509 | 4470 | { |
a704bb5c | 4471 | int cpu = get_cpu(); |
a786841d | 4472 | |
d01524d8 TP |
4473 | if (port->priv->hw_version == MVPP22) { |
4474 | u32 val = 0; | |
4475 | ||
4476 | if (sizeof(dma_addr_t) == 8) | |
4477 | val |= upper_32_bits(buf_dma_addr) & | |
4478 | MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; | |
4479 | ||
4480 | if (sizeof(phys_addr_t) == 8) | |
4481 | val |= (upper_32_bits(buf_phys_addr) | |
4482 | << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & | |
4483 | MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; | |
4484 | ||
cdcfeb0f YM |
4485 | mvpp2_percpu_write_relaxed(port->priv, cpu, |
4486 | MVPP22_BM_ADDR_HIGH_RLS_REG, val); | |
d01524d8 TP |
4487 | } |
4488 | ||
4e4a105f TP |
4489 | /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply |
4490 | * returned in the "cookie" field of the RX | |
4491 | * descriptor. Instead of storing the virtual address, we | |
4492 | * store the physical address | |
4493 | */ | |
cdcfeb0f YM |
4494 | mvpp2_percpu_write_relaxed(port->priv, cpu, |
4495 | MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); | |
4496 | mvpp2_percpu_write_relaxed(port->priv, cpu, | |
4497 | MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); | |
a704bb5c TP |
4498 | |
4499 | put_cpu(); | |
3f518509 MW |
4500 | } |
4501 | ||
3f518509 MW |
4502 | /* Allocate buffers for the pool */ |
4503 | static int mvpp2_bm_bufs_add(struct mvpp2_port *port, | |
4504 | struct mvpp2_bm_pool *bm_pool, int buf_num) | |
4505 | { | |
3f518509 | 4506 | int i, buf_size, total_size; |
20396136 | 4507 | dma_addr_t dma_addr; |
4e4a105f | 4508 | phys_addr_t phys_addr; |
0e037281 | 4509 | void *buf; |
3f518509 MW |
4510 | |
4511 | buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); | |
4512 | total_size = MVPP2_RX_TOTAL_SIZE(buf_size); | |
4513 | ||
4514 | if (buf_num < 0 || | |
4515 | (buf_num + bm_pool->buf_num > bm_pool->size)) { | |
4516 | netdev_err(port->dev, | |
4517 | "cannot allocate %d buffers for pool %d\n", | |
4518 | buf_num, bm_pool->id); | |
4519 | return 0; | |
4520 | } | |
4521 | ||
3f518509 | 4522 | for (i = 0; i < buf_num; i++) { |
4e4a105f TP |
4523 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, |
4524 | &phys_addr, GFP_KERNEL); | |
0e037281 | 4525 | if (!buf) |
3f518509 MW |
4526 | break; |
4527 | ||
20396136 | 4528 | mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, |
4e4a105f | 4529 | phys_addr); |
3f518509 MW |
4530 | } |
4531 | ||
4532 | /* Update BM driver with number of buffers added to pool */ | |
4533 | bm_pool->buf_num += i; | |
3f518509 MW |
4534 | |
4535 | netdev_dbg(port->dev, | |
01d04936 | 4536 | "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", |
3f518509 MW |
4537 | bm_pool->id, bm_pool->pkt_size, buf_size, total_size); |
4538 | ||
4539 | netdev_dbg(port->dev, | |
01d04936 | 4540 | "pool %d: %d of %d buffers added\n", |
3f518509 MW |
4541 | bm_pool->id, i, buf_num); |
4542 | return i; | |
4543 | } | |
4544 | ||
4545 | /* Notify the driver that BM pool is being used as specific type and return the | |
4546 | * pool pointer on success | |
4547 | */ | |
4548 | static struct mvpp2_bm_pool * | |
01d04936 | 4549 | mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) |
3f518509 | 4550 | { |
3f518509 MW |
4551 | struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; |
4552 | int num; | |
4553 | ||
01d04936 SC |
4554 | if (pool >= MVPP2_BM_POOLS_NUM) { |
4555 | netdev_err(port->dev, "Invalid pool %d\n", pool); | |
3f518509 MW |
4556 | return NULL; |
4557 | } | |
4558 | ||
3f518509 MW |
4559 | /* Allocate buffers in case BM pool is used as long pool, but packet |
4560 | * size doesn't match MTU or BM pool hasn't being used yet | |
4561 | */ | |
01d04936 | 4562 | if (new_pool->pkt_size == 0) { |
3f518509 MW |
4563 | int pkts_num; |
4564 | ||
4565 | /* Set default buffer number or free all the buffers in case | |
4566 | * the pool is not empty | |
4567 | */ | |
4568 | pkts_num = new_pool->buf_num; | |
4569 | if (pkts_num == 0) | |
01d04936 | 4570 | pkts_num = mvpp2_pools[pool].buf_num; |
3f518509 | 4571 | else |
4229d502 | 4572 | mvpp2_bm_bufs_free(port->dev->dev.parent, |
effbf5f5 | 4573 | port->priv, new_pool, pkts_num); |
3f518509 MW |
4574 | |
4575 | new_pool->pkt_size = pkt_size; | |
0e037281 TP |
4576 | new_pool->frag_size = |
4577 | SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + | |
4578 | MVPP2_SKB_SHINFO_SIZE; | |
3f518509 MW |
4579 | |
4580 | /* Allocate buffers for this pool */ | |
4581 | num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); | |
4582 | if (num != pkts_num) { | |
4583 | WARN(1, "pool %d: %d of %d allocated\n", | |
4584 | new_pool->id, num, pkts_num); | |
3f518509 MW |
4585 | return NULL; |
4586 | } | |
4587 | } | |
4588 | ||
4589 | mvpp2_bm_pool_bufsize_set(port->priv, new_pool, | |
4590 | MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); | |
4591 | ||
3f518509 MW |
4592 | return new_pool; |
4593 | } | |
4594 | ||
4595 | /* Initialize pools for swf */ | |
4596 | static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) | |
4597 | { | |
3f518509 | 4598 | int rxq; |
576193f2 SC |
4599 | enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; |
4600 | ||
4601 | /* If port pkt_size is higher than 1518B: | |
4602 | * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool | |
4603 | * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool | |
4604 | */ | |
4605 | if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { | |
4606 | long_log_pool = MVPP2_BM_JUMBO; | |
4607 | short_log_pool = MVPP2_BM_LONG; | |
4608 | } else { | |
4609 | long_log_pool = MVPP2_BM_LONG; | |
4610 | short_log_pool = MVPP2_BM_SHORT; | |
4611 | } | |
3f518509 MW |
4612 | |
4613 | if (!port->pool_long) { | |
4614 | port->pool_long = | |
576193f2 SC |
4615 | mvpp2_bm_pool_use(port, long_log_pool, |
4616 | mvpp2_pools[long_log_pool].pkt_size); | |
3f518509 MW |
4617 | if (!port->pool_long) |
4618 | return -ENOMEM; | |
4619 | ||
576193f2 | 4620 | port->pool_long->port_map |= BIT(port->id); |
3f518509 | 4621 | |
09f83975 | 4622 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4623 | mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); |
4624 | } | |
4625 | ||
4626 | if (!port->pool_short) { | |
4627 | port->pool_short = | |
576193f2 | 4628 | mvpp2_bm_pool_use(port, short_log_pool, |
e2e03164 | 4629 | mvpp2_pools[short_log_pool].pkt_size); |
3f518509 MW |
4630 | if (!port->pool_short) |
4631 | return -ENOMEM; | |
4632 | ||
576193f2 | 4633 | port->pool_short->port_map |= BIT(port->id); |
3f518509 | 4634 | |
09f83975 | 4635 | for (rxq = 0; rxq < port->nrxqs; rxq++) |
3f518509 MW |
4636 | mvpp2_rxq_short_pool_set(port, rxq, |
4637 | port->pool_short->id); | |
4638 | } | |
4639 | ||
4640 | return 0; | |
4641 | } | |
4642 | ||
4643 | static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) | |
4644 | { | |
4645 | struct mvpp2_port *port = netdev_priv(dev); | |
576193f2 SC |
4646 | enum mvpp2_bm_pool_log_num new_long_pool; |
4647 | int pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
3f518509 | 4648 | |
576193f2 SC |
4649 | /* If port MTU is higher than 1518B: |
4650 | * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool | |
4651 | * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool | |
4652 | */ | |
4653 | if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) | |
4654 | new_long_pool = MVPP2_BM_JUMBO; | |
4655 | else | |
4656 | new_long_pool = MVPP2_BM_LONG; | |
4657 | ||
4658 | if (new_long_pool != port->pool_long->id) { | |
4659 | /* Remove port from old short & long pool */ | |
4660 | port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, | |
4661 | port->pool_long->pkt_size); | |
4662 | port->pool_long->port_map &= ~BIT(port->id); | |
4663 | port->pool_long = NULL; | |
4664 | ||
4665 | port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, | |
4666 | port->pool_short->pkt_size); | |
4667 | port->pool_short->port_map &= ~BIT(port->id); | |
4668 | port->pool_short = NULL; | |
4669 | ||
4670 | port->pkt_size = pkt_size; | |
4671 | ||
4672 | /* Add port to new short & long pool */ | |
4673 | mvpp2_swf_bm_pool_init(port); | |
4674 | ||
4675 | /* Update L4 checksum when jumbo enable/disable on port */ | |
4676 | if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { | |
4677 | dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); | |
4678 | dev->hw_features &= ~(NETIF_F_IP_CSUM | | |
4679 | NETIF_F_IPV6_CSUM); | |
4680 | } else { | |
4681 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
4682 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
4683 | } | |
3f518509 MW |
4684 | } |
4685 | ||
3f518509 | 4686 | dev->mtu = mtu; |
576193f2 SC |
4687 | dev->wanted_features = dev->features; |
4688 | ||
3f518509 MW |
4689 | netdev_update_features(dev); |
4690 | return 0; | |
4691 | } | |
4692 | ||
4693 | static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) | |
4694 | { | |
591f4cfa TP |
4695 | int i, sw_thread_mask = 0; |
4696 | ||
4697 | for (i = 0; i < port->nqvecs; i++) | |
4698 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
3f518509 | 4699 | |
3f518509 | 4700 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa | 4701 | MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); |
3f518509 MW |
4702 | } |
4703 | ||
4704 | static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) | |
4705 | { | |
591f4cfa TP |
4706 | int i, sw_thread_mask = 0; |
4707 | ||
4708 | for (i = 0; i < port->nqvecs; i++) | |
4709 | sw_thread_mask |= port->qvecs[i].sw_thread_mask; | |
4710 | ||
4711 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4712 | MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); | |
4713 | } | |
4714 | ||
4715 | static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) | |
4716 | { | |
4717 | struct mvpp2_port *port = qvec->port; | |
3f518509 | 4718 | |
3f518509 | 4719 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), |
591f4cfa TP |
4720 | MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); |
4721 | } | |
4722 | ||
4723 | static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) | |
4724 | { | |
4725 | struct mvpp2_port *port = qvec->port; | |
4726 | ||
4727 | mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), | |
4728 | MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); | |
3f518509 MW |
4729 | } |
4730 | ||
e0af22d9 TP |
4731 | /* Mask the current CPU's Rx/Tx interrupts |
4732 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4733 | * using smp_processor_id() is OK. | |
4734 | */ | |
3f518509 MW |
4735 | static void mvpp2_interrupts_mask(void *arg) |
4736 | { | |
4737 | struct mvpp2_port *port = arg; | |
4738 | ||
a786841d TP |
4739 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
4740 | MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); | |
3f518509 MW |
4741 | } |
4742 | ||
e0af22d9 TP |
4743 | /* Unmask the current CPU's Rx/Tx interrupts. |
4744 | * Called by on_each_cpu(), guaranteed to run with migration disabled, | |
4745 | * using smp_processor_id() is OK. | |
4746 | */ | |
3f518509 MW |
4747 | static void mvpp2_interrupts_unmask(void *arg) |
4748 | { | |
4749 | struct mvpp2_port *port = arg; | |
213f428f TP |
4750 | u32 val; |
4751 | ||
4752 | val = MVPP2_CAUSE_MISC_SUM_MASK | | |
4753 | MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4754 | if (port->has_tx_irqs) | |
4755 | val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; | |
3f518509 | 4756 | |
a786841d | 4757 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
213f428f TP |
4758 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); |
4759 | } | |
4760 | ||
4761 | static void | |
4762 | mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) | |
4763 | { | |
4764 | u32 val; | |
4765 | int i; | |
4766 | ||
4767 | if (port->priv->hw_version != MVPP22) | |
4768 | return; | |
4769 | ||
4770 | if (mask) | |
4771 | val = 0; | |
4772 | else | |
4773 | val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; | |
4774 | ||
4775 | for (i = 0; i < port->nqvecs; i++) { | |
4776 | struct mvpp2_queue_vector *v = port->qvecs + i; | |
4777 | ||
4778 | if (v->type != MVPP2_QUEUE_VECTOR_SHARED) | |
4779 | continue; | |
4780 | ||
4781 | mvpp2_percpu_write(port->priv, v->sw_thread_id, | |
4782 | MVPP2_ISR_RX_TX_MASK_REG(port->id), val); | |
4783 | } | |
3f518509 MW |
4784 | } |
4785 | ||
4786 | /* Port configuration routines */ | |
4787 | ||
f84bf386 AT |
4788 | static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) |
4789 | { | |
4790 | struct mvpp2 *priv = port->priv; | |
4791 | u32 val; | |
4792 | ||
4793 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4794 | val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; | |
4795 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4796 | ||
4797 | regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); | |
4798 | if (port->gop_id == 2) | |
4799 | val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; | |
4800 | else if (port->gop_id == 3) | |
4801 | val |= GENCONF_CTRL0_PORT1_RGMII_MII; | |
4802 | regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); | |
4803 | } | |
4804 | ||
4805 | static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) | |
4806 | { | |
4807 | struct mvpp2 *priv = port->priv; | |
4808 | u32 val; | |
4809 | ||
4810 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4811 | val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | | |
4812 | GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; | |
4813 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4814 | ||
4815 | if (port->gop_id > 1) { | |
4816 | regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); | |
4817 | if (port->gop_id == 2) | |
4818 | val &= ~GENCONF_CTRL0_PORT0_RGMII; | |
4819 | else if (port->gop_id == 3) | |
4820 | val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; | |
4821 | regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); | |
4822 | } | |
4823 | } | |
4824 | ||
4825 | static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) | |
4826 | { | |
4827 | struct mvpp2 *priv = port->priv; | |
4828 | void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); | |
4829 | void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); | |
4830 | u32 val; | |
4831 | ||
4832 | /* XPCS */ | |
4833 | val = readl(xpcs + MVPP22_XPCS_CFG0); | |
4834 | val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | | |
4835 | MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); | |
4836 | val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); | |
4837 | writel(val, xpcs + MVPP22_XPCS_CFG0); | |
4838 | ||
4839 | /* MPCS */ | |
4840 | val = readl(mpcs + MVPP22_MPCS_CTRL); | |
4841 | val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; | |
4842 | writel(val, mpcs + MVPP22_MPCS_CTRL); | |
4843 | ||
4844 | val = readl(mpcs + MVPP22_MPCS_CLK_RESET); | |
4845 | val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | | |
4846 | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); | |
4847 | val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); | |
4848 | writel(val, mpcs + MVPP22_MPCS_CLK_RESET); | |
4849 | ||
4850 | val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; | |
4851 | val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; | |
4852 | writel(val, mpcs + MVPP22_MPCS_CLK_RESET); | |
4853 | } | |
4854 | ||
4855 | static int mvpp22_gop_init(struct mvpp2_port *port) | |
4856 | { | |
4857 | struct mvpp2 *priv = port->priv; | |
4858 | u32 val; | |
4859 | ||
4860 | if (!priv->sysctrl_base) | |
4861 | return 0; | |
4862 | ||
4863 | switch (port->phy_interface) { | |
4864 | case PHY_INTERFACE_MODE_RGMII: | |
4865 | case PHY_INTERFACE_MODE_RGMII_ID: | |
4866 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
4867 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
4868 | if (port->gop_id == 0) | |
4869 | goto invalid_conf; | |
4870 | mvpp22_gop_init_rgmii(port); | |
4871 | break; | |
4872 | case PHY_INTERFACE_MODE_SGMII: | |
4873 | mvpp22_gop_init_sgmii(port); | |
4874 | break; | |
4875 | case PHY_INTERFACE_MODE_10GKR: | |
4876 | if (port->gop_id != 0) | |
4877 | goto invalid_conf; | |
4878 | mvpp22_gop_init_10gkr(port); | |
4879 | break; | |
4880 | default: | |
4881 | goto unsupported_conf; | |
4882 | } | |
4883 | ||
4884 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); | |
4885 | val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | | |
4886 | GENCONF_PORT_CTRL1_EN(port->gop_id); | |
4887 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); | |
4888 | ||
4889 | regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); | |
4890 | val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; | |
4891 | regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); | |
4892 | ||
4893 | regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); | |
4894 | val |= GENCONF_SOFT_RESET1_GOP; | |
4895 | regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); | |
4896 | ||
4897 | unsupported_conf: | |
4898 | return 0; | |
4899 | ||
4900 | invalid_conf: | |
4901 | netdev_err(port->dev, "Invalid port configuration\n"); | |
4902 | return -EINVAL; | |
4903 | } | |
4904 | ||
fd3651b2 AT |
4905 | static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) |
4906 | { | |
4907 | u32 val; | |
4908 | ||
4909 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4910 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4911 | /* Enable the GMAC link status irq for this port */ | |
4912 | val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4913 | val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; | |
4914 | writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4915 | } | |
4916 | ||
4917 | if (port->gop_id == 0) { | |
4918 | /* Enable the XLG/GIG irqs for this port */ | |
4919 | val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); | |
4920 | if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
4921 | val |= MVPP22_XLG_EXT_INT_MASK_XLG; | |
4922 | else | |
4923 | val |= MVPP22_XLG_EXT_INT_MASK_GIG; | |
4924 | writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); | |
4925 | } | |
4926 | } | |
4927 | ||
4928 | static void mvpp22_gop_mask_irq(struct mvpp2_port *port) | |
4929 | { | |
4930 | u32 val; | |
4931 | ||
4932 | if (port->gop_id == 0) { | |
4933 | val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); | |
4934 | val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | | |
4935 | MVPP22_XLG_EXT_INT_MASK_GIG); | |
4936 | writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); | |
4937 | } | |
4938 | ||
4939 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4940 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4941 | val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4942 | val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; | |
4943 | writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); | |
4944 | } | |
4945 | } | |
4946 | ||
4947 | static void mvpp22_gop_setup_irq(struct mvpp2_port *port) | |
4948 | { | |
4949 | u32 val; | |
4950 | ||
4951 | if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
4952 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
4953 | val = readl(port->base + MVPP22_GMAC_INT_MASK); | |
4954 | val |= MVPP22_GMAC_INT_MASK_LINK_STAT; | |
4955 | writel(val, port->base + MVPP22_GMAC_INT_MASK); | |
4956 | } | |
4957 | ||
4958 | if (port->gop_id == 0) { | |
4959 | val = readl(port->base + MVPP22_XLG_INT_MASK); | |
4960 | val |= MVPP22_XLG_INT_MASK_LINK; | |
4961 | writel(val, port->base + MVPP22_XLG_INT_MASK); | |
4962 | } | |
4963 | ||
4964 | mvpp22_gop_unmask_irq(port); | |
4965 | } | |
4966 | ||
542897d9 AT |
4967 | static int mvpp22_comphy_init(struct mvpp2_port *port) |
4968 | { | |
4969 | enum phy_mode mode; | |
4970 | int ret; | |
4971 | ||
4972 | if (!port->comphy) | |
4973 | return 0; | |
4974 | ||
4975 | switch (port->phy_interface) { | |
4976 | case PHY_INTERFACE_MODE_SGMII: | |
4977 | mode = PHY_MODE_SGMII; | |
4978 | break; | |
4979 | case PHY_INTERFACE_MODE_10GKR: | |
4980 | mode = PHY_MODE_10GKR; | |
4981 | break; | |
4982 | default: | |
4983 | return -EINVAL; | |
4984 | } | |
4985 | ||
4986 | ret = phy_set_mode(port->comphy, mode); | |
4987 | if (ret) | |
4988 | return ret; | |
4989 | ||
4990 | return phy_power_on(port->comphy); | |
4991 | } | |
4992 | ||
3f518509 MW |
4993 | static void mvpp2_port_enable(struct mvpp2_port *port) |
4994 | { | |
4995 | u32 val; | |
4996 | ||
725757ae AT |
4997 | /* Only GOP port 0 has an XLG MAC */ |
4998 | if (port->gop_id == 0 && | |
4999 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
5000 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
5001 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
5002 | val |= MVPP22_XLG_CTRL0_PORT_EN | | |
5003 | MVPP22_XLG_CTRL0_MAC_RESET_DIS; | |
5004 | val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; | |
5005 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
5006 | } else { | |
5007 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5008 | val |= MVPP2_GMAC_PORT_EN_MASK; | |
5009 | val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; | |
5010 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5011 | } | |
3f518509 MW |
5012 | } |
5013 | ||
5014 | static void mvpp2_port_disable(struct mvpp2_port *port) | |
5015 | { | |
5016 | u32 val; | |
5017 | ||
725757ae AT |
5018 | /* Only GOP port 0 has an XLG MAC */ |
5019 | if (port->gop_id == 0 && | |
5020 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
5021 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { | |
5022 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
4bb04326 AT |
5023 | val &= ~MVPP22_XLG_CTRL0_PORT_EN; |
5024 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); | |
5025 | ||
5026 | /* Disable & reset should be done separately */ | |
5027 | val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; | |
725757ae AT |
5028 | writel(val, port->base + MVPP22_XLG_CTRL0_REG); |
5029 | } else { | |
5030 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5031 | val &= ~(MVPP2_GMAC_PORT_EN_MASK); | |
5032 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5033 | } | |
3f518509 MW |
5034 | } |
5035 | ||
5036 | /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ | |
5037 | static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) | |
5038 | { | |
5039 | u32 val; | |
5040 | ||
5041 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & | |
5042 | ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; | |
5043 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
5044 | } | |
5045 | ||
5046 | /* Configure loopback port */ | |
4bb04326 AT |
5047 | static void mvpp2_port_loopback_set(struct mvpp2_port *port, |
5048 | const struct phylink_link_state *state) | |
3f518509 MW |
5049 | { |
5050 | u32 val; | |
5051 | ||
5052 | val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
5053 | ||
4bb04326 | 5054 | if (state->speed == 1000) |
3f518509 MW |
5055 | val |= MVPP2_GMAC_GMII_LB_EN_MASK; |
5056 | else | |
5057 | val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; | |
5058 | ||
5059 | if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) | |
5060 | val |= MVPP2_GMAC_PCS_LB_EN_MASK; | |
5061 | else | |
5062 | val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; | |
5063 | ||
5064 | writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); | |
5065 | } | |
5066 | ||
118d6298 MR |
5067 | struct mvpp2_ethtool_counter { |
5068 | unsigned int offset; | |
5069 | const char string[ETH_GSTRING_LEN]; | |
5070 | bool reg_is_64b; | |
5071 | }; | |
5072 | ||
5073 | static u64 mvpp2_read_count(struct mvpp2_port *port, | |
5074 | const struct mvpp2_ethtool_counter *counter) | |
5075 | { | |
5076 | u64 val; | |
5077 | ||
5078 | val = readl(port->stats_base + counter->offset); | |
5079 | if (counter->reg_is_64b) | |
5080 | val += (u64)readl(port->stats_base + counter->offset + 4) << 32; | |
5081 | ||
5082 | return val; | |
5083 | } | |
5084 | ||
5085 | /* Due to the fact that software statistics and hardware statistics are, by | |
5086 | * design, incremented at different moments in the chain of packet processing, | |
5087 | * it is very likely that incoming packets could have been dropped after being | |
5088 | * counted by hardware but before reaching software statistics (most probably | |
5089 | * multicast packets), and in the oppposite way, during transmission, FCS bytes | |
5090 | * are added in between as well as TSO skb will be split and header bytes added. | |
5091 | * Hence, statistics gathered from userspace with ifconfig (software) and | |
5092 | * ethtool (hardware) cannot be compared. | |
5093 | */ | |
5094 | static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { | |
5095 | { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, | |
5096 | { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, | |
5097 | { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, | |
5098 | { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, | |
5099 | { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, | |
5100 | { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, | |
5101 | { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, | |
5102 | { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, | |
5103 | { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, | |
5104 | { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, | |
5105 | { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, | |
5106 | { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, | |
5107 | { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, | |
5108 | { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, | |
5109 | { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, | |
5110 | { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, | |
5111 | { MVPP2_MIB_FC_SENT, "fc_sent" }, | |
5112 | { MVPP2_MIB_FC_RCVD, "fc_received" }, | |
5113 | { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, | |
5114 | { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, | |
5115 | { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, | |
5116 | { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, | |
5117 | { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, | |
5118 | { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, | |
5119 | { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, | |
5120 | { MVPP2_MIB_COLLISION, "collision" }, | |
5121 | { MVPP2_MIB_LATE_COLLISION, "late_collision" }, | |
5122 | }; | |
5123 | ||
5124 | static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, | |
5125 | u8 *data) | |
5126 | { | |
5127 | if (sset == ETH_SS_STATS) { | |
5128 | int i; | |
5129 | ||
5130 | for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) | |
5131 | memcpy(data + i * ETH_GSTRING_LEN, | |
5132 | &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); | |
5133 | } | |
5134 | } | |
5135 | ||
5136 | static void mvpp2_gather_hw_statistics(struct work_struct *work) | |
5137 | { | |
5138 | struct delayed_work *del_work = to_delayed_work(work); | |
e5c500eb MR |
5139 | struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, |
5140 | stats_work); | |
118d6298 | 5141 | u64 *pstats; |
e5c500eb | 5142 | int i; |
118d6298 | 5143 | |
e5c500eb | 5144 | mutex_lock(&port->gather_stats_lock); |
118d6298 | 5145 | |
e5c500eb MR |
5146 | pstats = port->ethtool_stats; |
5147 | for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) | |
5148 | *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); | |
118d6298 MR |
5149 | |
5150 | /* No need to read again the counters right after this function if it | |
5151 | * was called asynchronously by the user (ie. use of ethtool). | |
5152 | */ | |
e5c500eb MR |
5153 | cancel_delayed_work(&port->stats_work); |
5154 | queue_delayed_work(port->priv->stats_queue, &port->stats_work, | |
118d6298 MR |
5155 | MVPP2_MIB_COUNTERS_STATS_DELAY); |
5156 | ||
e5c500eb | 5157 | mutex_unlock(&port->gather_stats_lock); |
118d6298 MR |
5158 | } |
5159 | ||
5160 | static void mvpp2_ethtool_get_stats(struct net_device *dev, | |
5161 | struct ethtool_stats *stats, u64 *data) | |
5162 | { | |
5163 | struct mvpp2_port *port = netdev_priv(dev); | |
5164 | ||
e5c500eb MR |
5165 | /* Update statistics for the given port, then take the lock to avoid |
5166 | * concurrent accesses on the ethtool_stats structure during its copy. | |
5167 | */ | |
5168 | mvpp2_gather_hw_statistics(&port->stats_work.work); | |
118d6298 | 5169 | |
e5c500eb | 5170 | mutex_lock(&port->gather_stats_lock); |
118d6298 MR |
5171 | memcpy(data, port->ethtool_stats, |
5172 | sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); | |
e5c500eb | 5173 | mutex_unlock(&port->gather_stats_lock); |
118d6298 MR |
5174 | } |
5175 | ||
5176 | static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) | |
5177 | { | |
5178 | if (sset == ETH_SS_STATS) | |
5179 | return ARRAY_SIZE(mvpp2_ethtool_regs); | |
5180 | ||
5181 | return -EOPNOTSUPP; | |
5182 | } | |
5183 | ||
3f518509 MW |
5184 | static void mvpp2_port_reset(struct mvpp2_port *port) |
5185 | { | |
5186 | u32 val; | |
118d6298 MR |
5187 | unsigned int i; |
5188 | ||
5189 | /* Read the GOP statistics to reset the hardware counters */ | |
5190 | for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) | |
5191 | mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); | |
3f518509 MW |
5192 | |
5193 | val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
5194 | ~MVPP2_GMAC_PORT_RESET_MASK; | |
5195 | writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); | |
5196 | ||
5197 | while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & | |
5198 | MVPP2_GMAC_PORT_RESET_MASK) | |
5199 | continue; | |
5200 | } | |
5201 | ||
5202 | /* Change maximum receive size of the port */ | |
5203 | static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) | |
5204 | { | |
5205 | u32 val; | |
5206 | ||
5207 | val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
5208 | val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; | |
5209 | val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
5210 | MVPP2_GMAC_MAX_RX_SIZE_OFFS); | |
5211 | writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); | |
5212 | } | |
5213 | ||
76eb1b1d SC |
5214 | /* Change maximum receive size of the port */ |
5215 | static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) | |
5216 | { | |
5217 | u32 val; | |
5218 | ||
5219 | val = readl(port->base + MVPP22_XLG_CTRL1_REG); | |
5220 | val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; | |
5221 | val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << | |
ec15ecde | 5222 | MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; |
76eb1b1d SC |
5223 | writel(val, port->base + MVPP22_XLG_CTRL1_REG); |
5224 | } | |
5225 | ||
3f518509 MW |
5226 | /* Set defaults to the MVPP2 port */ |
5227 | static void mvpp2_defaults_set(struct mvpp2_port *port) | |
5228 | { | |
5229 | int tx_port_num, val, queue, ptxq, lrxq; | |
5230 | ||
3d9017d9 | 5231 | if (port->priv->hw_version == MVPP21) { |
3d9017d9 TP |
5232 | /* Update TX FIFO MIN Threshold */ |
5233 | val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
5234 | val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; | |
5235 | /* Min. TX threshold must be less than minimal packet length */ | |
5236 | val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); | |
5237 | writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); | |
5238 | } | |
3f518509 MW |
5239 | |
5240 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
5241 | tx_port_num = mvpp2_egress_port(port); | |
5242 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, | |
5243 | tx_port_num); | |
5244 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); | |
5245 | ||
5246 | /* Close bandwidth for all queues */ | |
5247 | for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { | |
5248 | ptxq = mvpp2_txq_phys(port->id, queue); | |
5249 | mvpp2_write(port->priv, | |
5250 | MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); | |
5251 | } | |
5252 | ||
5253 | /* Set refill period to 1 usec, refill tokens | |
5254 | * and bucket size to maximum | |
5255 | */ | |
5256 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, | |
5257 | port->priv->tclk / USEC_PER_SEC); | |
5258 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); | |
5259 | val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; | |
5260 | val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); | |
5261 | val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; | |
5262 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); | |
5263 | val = MVPP2_TXP_TOKEN_SIZE_MAX; | |
5264 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
5265 | ||
5266 | /* Set MaximumLowLatencyPacketSize value to 256 */ | |
5267 | mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), | |
5268 | MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | | |
5269 | MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); | |
5270 | ||
5271 | /* Enable Rx cache snoop */ | |
09f83975 | 5272 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
5273 | queue = port->rxqs[lrxq]->id; |
5274 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
5275 | val |= MVPP2_SNOOP_PKT_SIZE_MASK | | |
5276 | MVPP2_SNOOP_BUF_HDR_MASK; | |
5277 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
5278 | } | |
5279 | ||
5280 | /* At default, mask all interrupts to all present cpus */ | |
5281 | mvpp2_interrupts_disable(port); | |
5282 | } | |
5283 | ||
5284 | /* Enable/disable receiving packets */ | |
5285 | static void mvpp2_ingress_enable(struct mvpp2_port *port) | |
5286 | { | |
5287 | u32 val; | |
5288 | int lrxq, queue; | |
5289 | ||
09f83975 | 5290 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
5291 | queue = port->rxqs[lrxq]->id; |
5292 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
5293 | val &= ~MVPP2_RXQ_DISABLE_MASK; | |
5294 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
5295 | } | |
5296 | } | |
5297 | ||
5298 | static void mvpp2_ingress_disable(struct mvpp2_port *port) | |
5299 | { | |
5300 | u32 val; | |
5301 | int lrxq, queue; | |
5302 | ||
09f83975 | 5303 | for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { |
3f518509 MW |
5304 | queue = port->rxqs[lrxq]->id; |
5305 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); | |
5306 | val |= MVPP2_RXQ_DISABLE_MASK; | |
5307 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); | |
5308 | } | |
5309 | } | |
5310 | ||
5311 | /* Enable transmit via physical egress queue | |
5312 | * - HW starts take descriptors from DRAM | |
5313 | */ | |
5314 | static void mvpp2_egress_enable(struct mvpp2_port *port) | |
5315 | { | |
5316 | u32 qmap; | |
5317 | int queue; | |
5318 | int tx_port_num = mvpp2_egress_port(port); | |
5319 | ||
5320 | /* Enable all initialized TXs. */ | |
5321 | qmap = 0; | |
09f83975 | 5322 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5323 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
5324 | ||
dbbb2f03 | 5325 | if (txq->descs) |
3f518509 MW |
5326 | qmap |= (1 << queue); |
5327 | } | |
5328 | ||
5329 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5330 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); | |
5331 | } | |
5332 | ||
5333 | /* Disable transmit via physical egress queue | |
5334 | * - HW doesn't take descriptors from DRAM | |
5335 | */ | |
5336 | static void mvpp2_egress_disable(struct mvpp2_port *port) | |
5337 | { | |
5338 | u32 reg_data; | |
5339 | int delay; | |
5340 | int tx_port_num = mvpp2_egress_port(port); | |
5341 | ||
5342 | /* Issue stop command for active channels only */ | |
5343 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5344 | reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & | |
5345 | MVPP2_TXP_SCHED_ENQ_MASK; | |
5346 | if (reg_data != 0) | |
5347 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, | |
5348 | (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); | |
5349 | ||
5350 | /* Wait for all Tx activity to terminate. */ | |
5351 | delay = 0; | |
5352 | do { | |
5353 | if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { | |
5354 | netdev_warn(port->dev, | |
5355 | "Tx stop timed out, status=0x%08x\n", | |
5356 | reg_data); | |
5357 | break; | |
5358 | } | |
5359 | mdelay(1); | |
5360 | delay++; | |
5361 | ||
5362 | /* Check port TX Command register that all | |
5363 | * Tx queues are stopped | |
5364 | */ | |
5365 | reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); | |
5366 | } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); | |
5367 | } | |
5368 | ||
5369 | /* Rx descriptors helper methods */ | |
5370 | ||
5371 | /* Get number of Rx descriptors occupied by received packets */ | |
5372 | static inline int | |
5373 | mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) | |
5374 | { | |
5375 | u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); | |
5376 | ||
5377 | return val & MVPP2_RXQ_OCCUPIED_MASK; | |
5378 | } | |
5379 | ||
5380 | /* Update Rx queue status with the number of occupied and available | |
5381 | * Rx descriptor slots. | |
5382 | */ | |
5383 | static inline void | |
5384 | mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, | |
5385 | int used_count, int free_count) | |
5386 | { | |
5387 | /* Decrement the number of used descriptors and increment count | |
5388 | * increment the number of free descriptors. | |
5389 | */ | |
5390 | u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); | |
5391 | ||
5392 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); | |
5393 | } | |
5394 | ||
5395 | /* Get pointer to next RX descriptor to be processed by SW */ | |
5396 | static inline struct mvpp2_rx_desc * | |
5397 | mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) | |
5398 | { | |
5399 | int rx_desc = rxq->next_desc_to_proc; | |
5400 | ||
5401 | rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); | |
5402 | prefetch(rxq->descs + rxq->next_desc_to_proc); | |
5403 | return rxq->descs + rx_desc; | |
5404 | } | |
5405 | ||
5406 | /* Set rx queue offset */ | |
5407 | static void mvpp2_rxq_offset_set(struct mvpp2_port *port, | |
5408 | int prxq, int offset) | |
5409 | { | |
5410 | u32 val; | |
5411 | ||
5412 | /* Convert offset from bytes to units of 32 bytes */ | |
5413 | offset = offset >> 5; | |
5414 | ||
5415 | val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); | |
5416 | val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; | |
5417 | ||
5418 | /* Offset is in */ | |
5419 | val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & | |
5420 | MVPP2_RXQ_PACKET_OFFSET_MASK); | |
5421 | ||
5422 | mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); | |
5423 | } | |
5424 | ||
3f518509 MW |
5425 | /* Tx descriptors helper methods */ |
5426 | ||
3f518509 MW |
5427 | /* Get pointer to next Tx descriptor to be processed (send) by HW */ |
5428 | static struct mvpp2_tx_desc * | |
5429 | mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) | |
5430 | { | |
5431 | int tx_desc = txq->next_desc_to_proc; | |
5432 | ||
5433 | txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); | |
5434 | return txq->descs + tx_desc; | |
5435 | } | |
5436 | ||
e0af22d9 TP |
5437 | /* Update HW with number of aggregated Tx descriptors to be sent |
5438 | * | |
5439 | * Called only from mvpp2_tx(), so migration is disabled, using | |
5440 | * smp_processor_id() is OK. | |
5441 | */ | |
3f518509 MW |
5442 | static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) |
5443 | { | |
5444 | /* aggregated access - relevant TXQ number is written in TX desc */ | |
a786841d TP |
5445 | mvpp2_percpu_write(port->priv, smp_processor_id(), |
5446 | MVPP2_AGGR_TXQ_UPDATE_REG, pending); | |
3f518509 MW |
5447 | } |
5448 | ||
5449 | ||
5450 | /* Check if there are enough free descriptors in aggregated txq. | |
5451 | * If not, update the number of occupied descriptors and repeat the check. | |
e0af22d9 TP |
5452 | * |
5453 | * Called only from mvpp2_tx(), so migration is disabled, using | |
5454 | * smp_processor_id() is OK. | |
3f518509 MW |
5455 | */ |
5456 | static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, | |
5457 | struct mvpp2_tx_queue *aggr_txq, int num) | |
5458 | { | |
02856a3b | 5459 | if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { |
3f518509 MW |
5460 | /* Update number of occupied aggregated Tx descriptors */ |
5461 | int cpu = smp_processor_id(); | |
cdcfeb0f YM |
5462 | u32 val = mvpp2_read_relaxed(priv, |
5463 | MVPP2_AGGR_TXQ_STATUS_REG(cpu)); | |
3f518509 MW |
5464 | |
5465 | aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; | |
5466 | } | |
5467 | ||
02856a3b | 5468 | if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) |
3f518509 MW |
5469 | return -ENOMEM; |
5470 | ||
5471 | return 0; | |
5472 | } | |
5473 | ||
e0af22d9 TP |
5474 | /* Reserved Tx descriptors allocation request |
5475 | * | |
5476 | * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called | |
5477 | * only by mvpp2_tx(), so migration is disabled, using | |
5478 | * smp_processor_id() is OK. | |
5479 | */ | |
3f518509 MW |
5480 | static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv, |
5481 | struct mvpp2_tx_queue *txq, int num) | |
5482 | { | |
5483 | u32 val; | |
a786841d | 5484 | int cpu = smp_processor_id(); |
3f518509 MW |
5485 | |
5486 | val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; | |
cdcfeb0f | 5487 | mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); |
3f518509 | 5488 | |
cdcfeb0f | 5489 | val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); |
3f518509 MW |
5490 | |
5491 | return val & MVPP2_TXQ_RSVD_RSLT_MASK; | |
5492 | } | |
5493 | ||
5494 | /* Check if there are enough reserved descriptors for transmission. | |
5495 | * If not, request chunk of reserved descriptors and check again. | |
5496 | */ | |
5497 | static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, | |
5498 | struct mvpp2_tx_queue *txq, | |
5499 | struct mvpp2_txq_pcpu *txq_pcpu, | |
5500 | int num) | |
5501 | { | |
5502 | int req, cpu, desc_count; | |
5503 | ||
5504 | if (txq_pcpu->reserved_num >= num) | |
5505 | return 0; | |
5506 | ||
5507 | /* Not enough descriptors reserved! Update the reserved descriptor | |
5508 | * count and check again. | |
5509 | */ | |
5510 | ||
5511 | desc_count = 0; | |
5512 | /* Compute total of used descriptors */ | |
5513 | for_each_present_cpu(cpu) { | |
5514 | struct mvpp2_txq_pcpu *txq_pcpu_aux; | |
5515 | ||
5516 | txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu); | |
5517 | desc_count += txq_pcpu_aux->count; | |
5518 | desc_count += txq_pcpu_aux->reserved_num; | |
5519 | } | |
5520 | ||
5521 | req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); | |
5522 | desc_count += req; | |
5523 | ||
5524 | if (desc_count > | |
5525 | (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) | |
5526 | return -ENOMEM; | |
5527 | ||
5528 | txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); | |
5529 | ||
5530 | /* OK, the descriptor cound has been updated: check again. */ | |
5531 | if (txq_pcpu->reserved_num < num) | |
5532 | return -ENOMEM; | |
5533 | return 0; | |
5534 | } | |
5535 | ||
5536 | /* Release the last allocated Tx descriptor. Useful to handle DMA | |
5537 | * mapping failures in the Tx path. | |
5538 | */ | |
5539 | static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) | |
5540 | { | |
5541 | if (txq->next_desc_to_proc == 0) | |
5542 | txq->next_desc_to_proc = txq->last_desc - 1; | |
5543 | else | |
5544 | txq->next_desc_to_proc--; | |
5545 | } | |
5546 | ||
5547 | /* Set Tx descriptors fields relevant for CSUM calculation */ | |
5548 | static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto, | |
5549 | int ip_hdr_len, int l4_proto) | |
5550 | { | |
5551 | u32 command; | |
5552 | ||
5553 | /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
5554 | * G_L4_chk, L4_type required only for checksum calculation | |
5555 | */ | |
5556 | command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); | |
5557 | command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); | |
5558 | command |= MVPP2_TXD_IP_CSUM_DISABLE; | |
5559 | ||
5560 | if (l3_proto == swab16(ETH_P_IP)) { | |
5561 | command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ | |
5562 | command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ | |
5563 | } else { | |
5564 | command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ | |
5565 | } | |
5566 | ||
5567 | if (l4_proto == IPPROTO_TCP) { | |
5568 | command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ | |
5569 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
5570 | } else if (l4_proto == IPPROTO_UDP) { | |
5571 | command |= MVPP2_TXD_L4_UDP; /* enable UDP */ | |
5572 | command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ | |
5573 | } else { | |
5574 | command |= MVPP2_TXD_L4_CSUM_NOT; | |
5575 | } | |
5576 | ||
5577 | return command; | |
5578 | } | |
5579 | ||
5580 | /* Get number of sent descriptors and decrement counter. | |
5581 | * The number of sent descriptors is returned. | |
5582 | * Per-CPU access | |
e0af22d9 TP |
5583 | * |
5584 | * Called only from mvpp2_txq_done(), called from mvpp2_tx() | |
5585 | * (migration disabled) and from the TX completion tasklet (migration | |
5586 | * disabled) so using smp_processor_id() is OK. | |
3f518509 MW |
5587 | */ |
5588 | static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, | |
5589 | struct mvpp2_tx_queue *txq) | |
5590 | { | |
5591 | u32 val; | |
5592 | ||
5593 | /* Reading status reg resets transmitted descriptor counter */ | |
cdcfeb0f YM |
5594 | val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(), |
5595 | MVPP2_TXQ_SENT_REG(txq->id)); | |
3f518509 MW |
5596 | |
5597 | return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> | |
5598 | MVPP2_TRANSMITTED_COUNT_OFFSET; | |
5599 | } | |
5600 | ||
e0af22d9 TP |
5601 | /* Called through on_each_cpu(), so runs on all CPUs, with migration |
5602 | * disabled, therefore using smp_processor_id() is OK. | |
5603 | */ | |
3f518509 MW |
5604 | static void mvpp2_txq_sent_counter_clear(void *arg) |
5605 | { | |
5606 | struct mvpp2_port *port = arg; | |
5607 | int queue; | |
5608 | ||
09f83975 | 5609 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
5610 | int id = port->txqs[queue]->id; |
5611 | ||
a786841d TP |
5612 | mvpp2_percpu_read(port->priv, smp_processor_id(), |
5613 | MVPP2_TXQ_SENT_REG(id)); | |
3f518509 MW |
5614 | } |
5615 | } | |
5616 | ||
5617 | /* Set max sizes for Tx queues */ | |
5618 | static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) | |
5619 | { | |
5620 | u32 val, size, mtu; | |
5621 | int txq, tx_port_num; | |
5622 | ||
5623 | mtu = port->pkt_size * 8; | |
5624 | if (mtu > MVPP2_TXP_MTU_MAX) | |
5625 | mtu = MVPP2_TXP_MTU_MAX; | |
5626 | ||
5627 | /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ | |
5628 | mtu = 3 * mtu; | |
5629 | ||
5630 | /* Indirect access to registers */ | |
5631 | tx_port_num = mvpp2_egress_port(port); | |
5632 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
5633 | ||
5634 | /* Set MTU */ | |
5635 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); | |
5636 | val &= ~MVPP2_TXP_MTU_MAX; | |
5637 | val |= mtu; | |
5638 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); | |
5639 | ||
5640 | /* TXP token size and all TXQs token size must be larger that MTU */ | |
5641 | val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); | |
5642 | size = val & MVPP2_TXP_TOKEN_SIZE_MAX; | |
5643 | if (size < mtu) { | |
5644 | size = mtu; | |
5645 | val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; | |
5646 | val |= size; | |
5647 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); | |
5648 | } | |
5649 | ||
09f83975 | 5650 | for (txq = 0; txq < port->ntxqs; txq++) { |
3f518509 MW |
5651 | val = mvpp2_read(port->priv, |
5652 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); | |
5653 | size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5654 | ||
5655 | if (size < mtu) { | |
5656 | size = mtu; | |
5657 | val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; | |
5658 | val |= size; | |
5659 | mvpp2_write(port->priv, | |
5660 | MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), | |
5661 | val); | |
5662 | } | |
5663 | } | |
5664 | } | |
5665 | ||
5666 | /* Set the number of packets that will be received before Rx interrupt | |
5667 | * will be generated by HW. | |
5668 | */ | |
5669 | static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 5670 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5671 | { |
a704bb5c | 5672 | int cpu = get_cpu(); |
a786841d | 5673 | |
f8b0d5f8 TP |
5674 | if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) |
5675 | rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; | |
3f518509 | 5676 | |
a786841d TP |
5677 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
5678 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG, | |
5679 | rxq->pkts_coal); | |
a704bb5c TP |
5680 | |
5681 | put_cpu(); | |
3f518509 MW |
5682 | } |
5683 | ||
213f428f TP |
5684 | /* For some reason in the LSP this is done on each CPU. Why ? */ |
5685 | static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, | |
5686 | struct mvpp2_tx_queue *txq) | |
5687 | { | |
5688 | int cpu = get_cpu(); | |
5689 | u32 val; | |
5690 | ||
5691 | if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) | |
5692 | txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; | |
5693 | ||
5694 | val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); | |
5695 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); | |
5696 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val); | |
5697 | ||
5698 | put_cpu(); | |
5699 | } | |
5700 | ||
ab42676a TP |
5701 | static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) |
5702 | { | |
5703 | u64 tmp = (u64)clk_hz * usec; | |
5704 | ||
5705 | do_div(tmp, USEC_PER_SEC); | |
5706 | ||
5707 | return tmp > U32_MAX ? U32_MAX : tmp; | |
5708 | } | |
5709 | ||
5710 | static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) | |
5711 | { | |
5712 | u64 tmp = (u64)cycles * USEC_PER_SEC; | |
5713 | ||
5714 | do_div(tmp, clk_hz); | |
5715 | ||
5716 | return tmp > U32_MAX ? U32_MAX : tmp; | |
5717 | } | |
5718 | ||
3f518509 MW |
5719 | /* Set the time delay in usec before Rx interrupt */ |
5720 | static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, | |
d63f9e41 | 5721 | struct mvpp2_rx_queue *rxq) |
3f518509 | 5722 | { |
ab42676a TP |
5723 | unsigned long freq = port->priv->tclk; |
5724 | u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5725 | ||
5726 | if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { | |
5727 | rxq->time_coal = | |
5728 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); | |
5729 | ||
5730 | /* re-evaluate to get actual register value */ | |
5731 | val = mvpp2_usec_to_cycles(rxq->time_coal, freq); | |
5732 | } | |
3f518509 | 5733 | |
3f518509 | 5734 | mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); |
3f518509 MW |
5735 | } |
5736 | ||
213f428f TP |
5737 | static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) |
5738 | { | |
5739 | unsigned long freq = port->priv->tclk; | |
5740 | u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5741 | ||
5742 | if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { | |
5743 | port->tx_time_coal = | |
5744 | mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); | |
5745 | ||
5746 | /* re-evaluate to get actual register value */ | |
5747 | val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); | |
5748 | } | |
5749 | ||
5750 | mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); | |
5751 | } | |
5752 | ||
3f518509 MW |
5753 | /* Free Tx queue skbuffs */ |
5754 | static void mvpp2_txq_bufs_free(struct mvpp2_port *port, | |
5755 | struct mvpp2_tx_queue *txq, | |
5756 | struct mvpp2_txq_pcpu *txq_pcpu, int num) | |
5757 | { | |
5758 | int i; | |
5759 | ||
5760 | for (i = 0; i < num; i++) { | |
8354491c TP |
5761 | struct mvpp2_txq_pcpu_buf *tx_buf = |
5762 | txq_pcpu->buffs + txq_pcpu->txq_get_index; | |
3f518509 | 5763 | |
20920267 AT |
5764 | if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) |
5765 | dma_unmap_single(port->dev->dev.parent, tx_buf->dma, | |
5766 | tx_buf->size, DMA_TO_DEVICE); | |
36fb7435 TP |
5767 | if (tx_buf->skb) |
5768 | dev_kfree_skb_any(tx_buf->skb); | |
5769 | ||
5770 | mvpp2_txq_inc_get(txq_pcpu); | |
3f518509 MW |
5771 | } |
5772 | } | |
5773 | ||
5774 | static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, | |
5775 | u32 cause) | |
5776 | { | |
5777 | int queue = fls(cause) - 1; | |
5778 | ||
5779 | return port->rxqs[queue]; | |
5780 | } | |
5781 | ||
5782 | static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, | |
5783 | u32 cause) | |
5784 | { | |
edc660fa | 5785 | int queue = fls(cause) - 1; |
3f518509 MW |
5786 | |
5787 | return port->txqs[queue]; | |
5788 | } | |
5789 | ||
5790 | /* Handle end of transmission */ | |
5791 | static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, | |
5792 | struct mvpp2_txq_pcpu *txq_pcpu) | |
5793 | { | |
5794 | struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); | |
5795 | int tx_done; | |
5796 | ||
5797 | if (txq_pcpu->cpu != smp_processor_id()) | |
5798 | netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); | |
5799 | ||
5800 | tx_done = mvpp2_txq_sent_desc_proc(port, txq); | |
5801 | if (!tx_done) | |
5802 | return; | |
5803 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); | |
5804 | ||
5805 | txq_pcpu->count -= tx_done; | |
5806 | ||
5807 | if (netif_tx_queue_stopped(nq)) | |
1d17db08 | 5808 | if (txq_pcpu->count <= txq_pcpu->wake_threshold) |
3f518509 MW |
5809 | netif_tx_wake_queue(nq); |
5810 | } | |
5811 | ||
213f428f TP |
5812 | static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, |
5813 | int cpu) | |
edc660fa MW |
5814 | { |
5815 | struct mvpp2_tx_queue *txq; | |
5816 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5817 | unsigned int tx_todo = 0; | |
5818 | ||
5819 | while (cause) { | |
5820 | txq = mvpp2_get_tx_queue(port, cause); | |
5821 | if (!txq) | |
5822 | break; | |
5823 | ||
213f428f | 5824 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); |
edc660fa MW |
5825 | |
5826 | if (txq_pcpu->count) { | |
5827 | mvpp2_txq_done(port, txq, txq_pcpu); | |
5828 | tx_todo += txq_pcpu->count; | |
5829 | } | |
5830 | ||
5831 | cause &= ~(1 << txq->log_id); | |
5832 | } | |
5833 | return tx_todo; | |
5834 | } | |
5835 | ||
3f518509 MW |
5836 | /* Rx/Tx queue initialization/cleanup methods */ |
5837 | ||
5838 | /* Allocate and initialize descriptors for aggr TXQ */ | |
5839 | static int mvpp2_aggr_txq_init(struct platform_device *pdev, | |
85affd7e | 5840 | struct mvpp2_tx_queue *aggr_txq, int cpu, |
3f518509 MW |
5841 | struct mvpp2 *priv) |
5842 | { | |
b02f31fb TP |
5843 | u32 txq_dma; |
5844 | ||
3f518509 | 5845 | /* Allocate memory for TX descriptors */ |
a154f8e3 | 5846 | aggr_txq->descs = dma_zalloc_coherent(&pdev->dev, |
85affd7e | 5847 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, |
20396136 | 5848 | &aggr_txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5849 | if (!aggr_txq->descs) |
5850 | return -ENOMEM; | |
5851 | ||
02856a3b | 5852 | aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; |
3f518509 MW |
5853 | |
5854 | /* Aggr TXQ no reset WA */ | |
5855 | aggr_txq->next_desc_to_proc = mvpp2_read(priv, | |
5856 | MVPP2_AGGR_TXQ_INDEX_REG(cpu)); | |
5857 | ||
b02f31fb TP |
5858 | /* Set Tx descriptors queue starting address indirect |
5859 | * access | |
5860 | */ | |
5861 | if (priv->hw_version == MVPP21) | |
5862 | txq_dma = aggr_txq->descs_dma; | |
5863 | else | |
5864 | txq_dma = aggr_txq->descs_dma >> | |
5865 | MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; | |
5866 | ||
5867 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); | |
85affd7e AT |
5868 | mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), |
5869 | MVPP2_AGGR_TXQ_SIZE); | |
3f518509 MW |
5870 | |
5871 | return 0; | |
5872 | } | |
5873 | ||
5874 | /* Create a specified Rx queue */ | |
5875 | static int mvpp2_rxq_init(struct mvpp2_port *port, | |
5876 | struct mvpp2_rx_queue *rxq) | |
5877 | ||
5878 | { | |
b02f31fb | 5879 | u32 rxq_dma; |
a786841d | 5880 | int cpu; |
b02f31fb | 5881 | |
3f518509 MW |
5882 | rxq->size = port->rx_ring_size; |
5883 | ||
5884 | /* Allocate memory for RX descriptors */ | |
5885 | rxq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
5886 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5887 | &rxq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5888 | if (!rxq->descs) |
5889 | return -ENOMEM; | |
5890 | ||
3f518509 MW |
5891 | rxq->last_desc = rxq->size - 1; |
5892 | ||
5893 | /* Zero occupied and non-occupied counters - direct access */ | |
5894 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
5895 | ||
5896 | /* Set Rx descriptors queue starting address - indirect access */ | |
a704bb5c | 5897 | cpu = get_cpu(); |
a786841d | 5898 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
b02f31fb TP |
5899 | if (port->priv->hw_version == MVPP21) |
5900 | rxq_dma = rxq->descs_dma; | |
5901 | else | |
5902 | rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; | |
a786841d TP |
5903 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); |
5904 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); | |
5905 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0); | |
a704bb5c | 5906 | put_cpu(); |
3f518509 MW |
5907 | |
5908 | /* Set Offset */ | |
5909 | mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); | |
5910 | ||
5911 | /* Set coalescing pkts and time */ | |
d63f9e41 TP |
5912 | mvpp2_rx_pkts_coal_set(port, rxq); |
5913 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
5914 | |
5915 | /* Add number of descriptors ready for receiving packets */ | |
5916 | mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); | |
5917 | ||
5918 | return 0; | |
5919 | } | |
5920 | ||
5921 | /* Push packets received by the RXQ to BM pool */ | |
5922 | static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, | |
5923 | struct mvpp2_rx_queue *rxq) | |
5924 | { | |
5925 | int rx_received, i; | |
5926 | ||
5927 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
5928 | if (!rx_received) | |
5929 | return; | |
5930 | ||
5931 | for (i = 0; i < rx_received; i++) { | |
5932 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); | |
56b8aae9 TP |
5933 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
5934 | int pool; | |
5935 | ||
5936 | pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> | |
5937 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 5938 | |
7d7627ba | 5939 | mvpp2_bm_pool_put(port, pool, |
ac3dd277 TP |
5940 | mvpp2_rxdesc_dma_addr_get(port, rx_desc), |
5941 | mvpp2_rxdesc_cookie_get(port, rx_desc)); | |
3f518509 MW |
5942 | } |
5943 | mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); | |
5944 | } | |
5945 | ||
5946 | /* Cleanup Rx queue */ | |
5947 | static void mvpp2_rxq_deinit(struct mvpp2_port *port, | |
5948 | struct mvpp2_rx_queue *rxq) | |
5949 | { | |
a786841d TP |
5950 | int cpu; |
5951 | ||
3f518509 MW |
5952 | mvpp2_rxq_drop_pkts(port, rxq); |
5953 | ||
5954 | if (rxq->descs) | |
5955 | dma_free_coherent(port->dev->dev.parent, | |
5956 | rxq->size * MVPP2_DESC_ALIGNED_SIZE, | |
5957 | rxq->descs, | |
20396136 | 5958 | rxq->descs_dma); |
3f518509 MW |
5959 | |
5960 | rxq->descs = NULL; | |
5961 | rxq->last_desc = 0; | |
5962 | rxq->next_desc_to_proc = 0; | |
20396136 | 5963 | rxq->descs_dma = 0; |
3f518509 MW |
5964 | |
5965 | /* Clear Rx descriptors queue starting address and size; | |
5966 | * free descriptor number | |
5967 | */ | |
5968 | mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); | |
a704bb5c | 5969 | cpu = get_cpu(); |
a786841d TP |
5970 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); |
5971 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0); | |
5972 | mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 5973 | put_cpu(); |
3f518509 MW |
5974 | } |
5975 | ||
5976 | /* Create and initialize a Tx queue */ | |
5977 | static int mvpp2_txq_init(struct mvpp2_port *port, | |
5978 | struct mvpp2_tx_queue *txq) | |
5979 | { | |
5980 | u32 val; | |
5981 | int cpu, desc, desc_per_txq, tx_port_num; | |
5982 | struct mvpp2_txq_pcpu *txq_pcpu; | |
5983 | ||
5984 | txq->size = port->tx_ring_size; | |
5985 | ||
5986 | /* Allocate memory for Tx descriptors */ | |
5987 | txq->descs = dma_alloc_coherent(port->dev->dev.parent, | |
5988 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 5989 | &txq->descs_dma, GFP_KERNEL); |
3f518509 MW |
5990 | if (!txq->descs) |
5991 | return -ENOMEM; | |
5992 | ||
3f518509 MW |
5993 | txq->last_desc = txq->size - 1; |
5994 | ||
5995 | /* Set Tx descriptors queue starting address - indirect access */ | |
a704bb5c | 5996 | cpu = get_cpu(); |
a786841d TP |
5997 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
5998 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, | |
5999 | txq->descs_dma); | |
6000 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, | |
6001 | txq->size & MVPP2_TXQ_DESC_SIZE_MASK); | |
6002 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0); | |
6003 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG, | |
6004 | txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); | |
6005 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG); | |
3f518509 | 6006 | val &= ~MVPP2_TXQ_PENDING_MASK; |
a786841d | 6007 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val); |
3f518509 MW |
6008 | |
6009 | /* Calculate base address in prefetch buffer. We reserve 16 descriptors | |
6010 | * for each existing TXQ. | |
6011 | * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT | |
6012 | * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS | |
6013 | */ | |
6014 | desc_per_txq = 16; | |
6015 | desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + | |
6016 | (txq->log_id * desc_per_txq); | |
6017 | ||
a786841d TP |
6018 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, |
6019 | MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | | |
6020 | MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); | |
a704bb5c | 6021 | put_cpu(); |
3f518509 MW |
6022 | |
6023 | /* WRR / EJP configuration - indirect access */ | |
6024 | tx_port_num = mvpp2_egress_port(port); | |
6025 | mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); | |
6026 | ||
6027 | val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); | |
6028 | val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; | |
6029 | val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); | |
6030 | val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; | |
6031 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); | |
6032 | ||
6033 | val = MVPP2_TXQ_TOKEN_SIZE_MAX; | |
6034 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), | |
6035 | val); | |
6036 | ||
6037 | for_each_present_cpu(cpu) { | |
6038 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
6039 | txq_pcpu->size = txq->size; | |
02c91ece ME |
6040 | txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, |
6041 | sizeof(*txq_pcpu->buffs), | |
6042 | GFP_KERNEL); | |
8354491c | 6043 | if (!txq_pcpu->buffs) |
ba2d8d88 | 6044 | return -ENOMEM; |
3f518509 MW |
6045 | |
6046 | txq_pcpu->count = 0; | |
6047 | txq_pcpu->reserved_num = 0; | |
6048 | txq_pcpu->txq_put_index = 0; | |
6049 | txq_pcpu->txq_get_index = 0; | |
b70d4a51 | 6050 | txq_pcpu->tso_headers = NULL; |
186cd4d4 | 6051 | |
1d17db08 AT |
6052 | txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; |
6053 | txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; | |
6054 | ||
186cd4d4 AT |
6055 | txq_pcpu->tso_headers = |
6056 | dma_alloc_coherent(port->dev->dev.parent, | |
822eaf7c | 6057 | txq_pcpu->size * TSO_HEADER_SIZE, |
186cd4d4 AT |
6058 | &txq_pcpu->tso_headers_dma, |
6059 | GFP_KERNEL); | |
6060 | if (!txq_pcpu->tso_headers) | |
ba2d8d88 | 6061 | return -ENOMEM; |
3f518509 MW |
6062 | } |
6063 | ||
6064 | return 0; | |
6065 | } | |
6066 | ||
6067 | /* Free allocated TXQ resources */ | |
6068 | static void mvpp2_txq_deinit(struct mvpp2_port *port, | |
6069 | struct mvpp2_tx_queue *txq) | |
6070 | { | |
6071 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6072 | int cpu; | |
6073 | ||
6074 | for_each_present_cpu(cpu) { | |
6075 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
8354491c | 6076 | kfree(txq_pcpu->buffs); |
186cd4d4 | 6077 | |
b70d4a51 AT |
6078 | if (txq_pcpu->tso_headers) |
6079 | dma_free_coherent(port->dev->dev.parent, | |
6080 | txq_pcpu->size * TSO_HEADER_SIZE, | |
6081 | txq_pcpu->tso_headers, | |
6082 | txq_pcpu->tso_headers_dma); | |
6083 | ||
6084 | txq_pcpu->tso_headers = NULL; | |
3f518509 MW |
6085 | } |
6086 | ||
6087 | if (txq->descs) | |
6088 | dma_free_coherent(port->dev->dev.parent, | |
6089 | txq->size * MVPP2_DESC_ALIGNED_SIZE, | |
20396136 | 6090 | txq->descs, txq->descs_dma); |
3f518509 MW |
6091 | |
6092 | txq->descs = NULL; | |
6093 | txq->last_desc = 0; | |
6094 | txq->next_desc_to_proc = 0; | |
20396136 | 6095 | txq->descs_dma = 0; |
3f518509 MW |
6096 | |
6097 | /* Set minimum bandwidth for disabled TXQs */ | |
6098 | mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); | |
6099 | ||
6100 | /* Set Tx descriptors queue starting address and size */ | |
a704bb5c | 6101 | cpu = get_cpu(); |
a786841d TP |
6102 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
6103 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0); | |
6104 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0); | |
a704bb5c | 6105 | put_cpu(); |
3f518509 MW |
6106 | } |
6107 | ||
6108 | /* Cleanup Tx ports */ | |
6109 | static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) | |
6110 | { | |
6111 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6112 | int delay, pending, cpu; | |
6113 | u32 val; | |
6114 | ||
a704bb5c | 6115 | cpu = get_cpu(); |
a786841d TP |
6116 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); |
6117 | val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG); | |
3f518509 | 6118 | val |= MVPP2_TXQ_DRAIN_EN_MASK; |
a786841d | 6119 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
3f518509 MW |
6120 | |
6121 | /* The napi queue has been stopped so wait for all packets | |
6122 | * to be transmitted. | |
6123 | */ | |
6124 | delay = 0; | |
6125 | do { | |
6126 | if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { | |
6127 | netdev_warn(port->dev, | |
6128 | "port %d: cleaning queue %d timed out\n", | |
6129 | port->id, txq->log_id); | |
6130 | break; | |
6131 | } | |
6132 | mdelay(1); | |
6133 | delay++; | |
6134 | ||
a786841d TP |
6135 | pending = mvpp2_percpu_read(port->priv, cpu, |
6136 | MVPP2_TXQ_PENDING_REG); | |
6137 | pending &= MVPP2_TXQ_PENDING_MASK; | |
3f518509 MW |
6138 | } while (pending); |
6139 | ||
6140 | val &= ~MVPP2_TXQ_DRAIN_EN_MASK; | |
a786841d | 6141 | mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); |
a704bb5c | 6142 | put_cpu(); |
3f518509 MW |
6143 | |
6144 | for_each_present_cpu(cpu) { | |
6145 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
6146 | ||
6147 | /* Release all packets */ | |
6148 | mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); | |
6149 | ||
6150 | /* Reset queue */ | |
6151 | txq_pcpu->count = 0; | |
6152 | txq_pcpu->txq_put_index = 0; | |
6153 | txq_pcpu->txq_get_index = 0; | |
6154 | } | |
6155 | } | |
6156 | ||
6157 | /* Cleanup all Tx queues */ | |
6158 | static void mvpp2_cleanup_txqs(struct mvpp2_port *port) | |
6159 | { | |
6160 | struct mvpp2_tx_queue *txq; | |
6161 | int queue; | |
6162 | u32 val; | |
6163 | ||
6164 | val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); | |
6165 | ||
6166 | /* Reset Tx ports and delete Tx queues */ | |
6167 | val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
6168 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
6169 | ||
09f83975 | 6170 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6171 | txq = port->txqs[queue]; |
6172 | mvpp2_txq_clean(port, txq); | |
6173 | mvpp2_txq_deinit(port, txq); | |
6174 | } | |
6175 | ||
6176 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); | |
6177 | ||
6178 | val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); | |
6179 | mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); | |
6180 | } | |
6181 | ||
6182 | /* Cleanup all Rx queues */ | |
6183 | static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) | |
6184 | { | |
6185 | int queue; | |
6186 | ||
09f83975 | 6187 | for (queue = 0; queue < port->nrxqs; queue++) |
3f518509 MW |
6188 | mvpp2_rxq_deinit(port, port->rxqs[queue]); |
6189 | } | |
6190 | ||
6191 | /* Init all Rx queues for port */ | |
6192 | static int mvpp2_setup_rxqs(struct mvpp2_port *port) | |
6193 | { | |
6194 | int queue, err; | |
6195 | ||
09f83975 | 6196 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
6197 | err = mvpp2_rxq_init(port, port->rxqs[queue]); |
6198 | if (err) | |
6199 | goto err_cleanup; | |
6200 | } | |
6201 | return 0; | |
6202 | ||
6203 | err_cleanup: | |
6204 | mvpp2_cleanup_rxqs(port); | |
6205 | return err; | |
6206 | } | |
6207 | ||
6208 | /* Init all tx queues for port */ | |
6209 | static int mvpp2_setup_txqs(struct mvpp2_port *port) | |
6210 | { | |
6211 | struct mvpp2_tx_queue *txq; | |
6212 | int queue, err; | |
6213 | ||
09f83975 | 6214 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
6215 | txq = port->txqs[queue]; |
6216 | err = mvpp2_txq_init(port, txq); | |
6217 | if (err) | |
6218 | goto err_cleanup; | |
6219 | } | |
6220 | ||
213f428f TP |
6221 | if (port->has_tx_irqs) { |
6222 | mvpp2_tx_time_coal_set(port); | |
6223 | for (queue = 0; queue < port->ntxqs; queue++) { | |
6224 | txq = port->txqs[queue]; | |
6225 | mvpp2_tx_pkts_coal_set(port, txq); | |
6226 | } | |
6227 | } | |
6228 | ||
3f518509 MW |
6229 | on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); |
6230 | return 0; | |
6231 | ||
6232 | err_cleanup: | |
6233 | mvpp2_cleanup_txqs(port); | |
6234 | return err; | |
6235 | } | |
6236 | ||
6237 | /* The callback for per-port interrupt */ | |
6238 | static irqreturn_t mvpp2_isr(int irq, void *dev_id) | |
6239 | { | |
591f4cfa | 6240 | struct mvpp2_queue_vector *qv = dev_id; |
3f518509 | 6241 | |
591f4cfa | 6242 | mvpp2_qvec_interrupt_disable(qv); |
3f518509 | 6243 | |
591f4cfa | 6244 | napi_schedule(&qv->napi); |
3f518509 MW |
6245 | |
6246 | return IRQ_HANDLED; | |
6247 | } | |
6248 | ||
fd3651b2 AT |
6249 | /* Per-port interrupt for link status changes */ |
6250 | static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) | |
6251 | { | |
6252 | struct mvpp2_port *port = (struct mvpp2_port *)dev_id; | |
6253 | struct net_device *dev = port->dev; | |
6254 | bool event = false, link = false; | |
6255 | u32 val; | |
6256 | ||
6257 | mvpp22_gop_mask_irq(port); | |
6258 | ||
6259 | if (port->gop_id == 0 && | |
6260 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) { | |
6261 | val = readl(port->base + MVPP22_XLG_INT_STAT); | |
6262 | if (val & MVPP22_XLG_INT_STAT_LINK) { | |
6263 | event = true; | |
6264 | val = readl(port->base + MVPP22_XLG_STATUS); | |
6265 | if (val & MVPP22_XLG_STATUS_LINK_UP) | |
6266 | link = true; | |
6267 | } | |
6268 | } else if (phy_interface_mode_is_rgmii(port->phy_interface) || | |
6269 | port->phy_interface == PHY_INTERFACE_MODE_SGMII) { | |
6270 | val = readl(port->base + MVPP22_GMAC_INT_STAT); | |
6271 | if (val & MVPP22_GMAC_INT_STAT_LINK) { | |
6272 | event = true; | |
6273 | val = readl(port->base + MVPP2_GMAC_STATUS0); | |
6274 | if (val & MVPP2_GMAC_STATUS0_LINK_UP) | |
6275 | link = true; | |
6276 | } | |
6277 | } | |
6278 | ||
4bb04326 AT |
6279 | if (port->phylink) { |
6280 | phylink_mac_change(port->phylink, link); | |
6281 | goto handled; | |
6282 | } | |
6283 | ||
fd3651b2 AT |
6284 | if (!netif_running(dev) || !event) |
6285 | goto handled; | |
6286 | ||
6287 | if (link) { | |
6288 | mvpp2_interrupts_enable(port); | |
6289 | ||
6290 | mvpp2_egress_enable(port); | |
6291 | mvpp2_ingress_enable(port); | |
6292 | netif_carrier_on(dev); | |
6293 | netif_tx_wake_all_queues(dev); | |
6294 | } else { | |
6295 | netif_tx_stop_all_queues(dev); | |
6296 | netif_carrier_off(dev); | |
6297 | mvpp2_ingress_disable(port); | |
6298 | mvpp2_egress_disable(port); | |
6299 | ||
6300 | mvpp2_interrupts_disable(port); | |
6301 | } | |
6302 | ||
6303 | handled: | |
6304 | mvpp22_gop_unmask_irq(port); | |
6305 | return IRQ_HANDLED; | |
6306 | } | |
6307 | ||
edc660fa MW |
6308 | static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) |
6309 | { | |
6310 | ktime_t interval; | |
6311 | ||
6312 | if (!port_pcpu->timer_scheduled) { | |
6313 | port_pcpu->timer_scheduled = true; | |
8b0e1953 | 6314 | interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; |
edc660fa MW |
6315 | hrtimer_start(&port_pcpu->tx_done_timer, interval, |
6316 | HRTIMER_MODE_REL_PINNED); | |
6317 | } | |
6318 | } | |
6319 | ||
6320 | static void mvpp2_tx_proc_cb(unsigned long data) | |
6321 | { | |
6322 | struct net_device *dev = (struct net_device *)data; | |
6323 | struct mvpp2_port *port = netdev_priv(dev); | |
6324 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); | |
6325 | unsigned int tx_todo, cause; | |
6326 | ||
6327 | if (!netif_running(dev)) | |
6328 | return; | |
6329 | port_pcpu->timer_scheduled = false; | |
6330 | ||
6331 | /* Process all the Tx queues */ | |
09f83975 | 6332 | cause = (1 << port->ntxqs) - 1; |
213f428f | 6333 | tx_todo = mvpp2_tx_done(port, cause, smp_processor_id()); |
edc660fa MW |
6334 | |
6335 | /* Set the timer in case not all the packets were processed */ | |
6336 | if (tx_todo) | |
6337 | mvpp2_timer_set(port_pcpu); | |
6338 | } | |
6339 | ||
6340 | static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) | |
6341 | { | |
6342 | struct mvpp2_port_pcpu *port_pcpu = container_of(timer, | |
6343 | struct mvpp2_port_pcpu, | |
6344 | tx_done_timer); | |
6345 | ||
6346 | tasklet_schedule(&port_pcpu->tx_done_tasklet); | |
6347 | ||
6348 | return HRTIMER_NORESTART; | |
6349 | } | |
6350 | ||
3f518509 MW |
6351 | /* Main RX/TX processing routines */ |
6352 | ||
6353 | /* Display more error info */ | |
6354 | static void mvpp2_rx_error(struct mvpp2_port *port, | |
6355 | struct mvpp2_rx_desc *rx_desc) | |
6356 | { | |
ac3dd277 TP |
6357 | u32 status = mvpp2_rxdesc_status_get(port, rx_desc); |
6358 | size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); | |
3f518509 MW |
6359 | |
6360 | switch (status & MVPP2_RXD_ERR_CODE_MASK) { | |
6361 | case MVPP2_RXD_ERR_CRC: | |
ac3dd277 TP |
6362 | netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n", |
6363 | status, sz); | |
3f518509 MW |
6364 | break; |
6365 | case MVPP2_RXD_ERR_OVERRUN: | |
ac3dd277 TP |
6366 | netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n", |
6367 | status, sz); | |
3f518509 MW |
6368 | break; |
6369 | case MVPP2_RXD_ERR_RESOURCE: | |
ac3dd277 TP |
6370 | netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n", |
6371 | status, sz); | |
3f518509 MW |
6372 | break; |
6373 | } | |
6374 | } | |
6375 | ||
6376 | /* Handle RX checksum offload */ | |
6377 | static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, | |
6378 | struct sk_buff *skb) | |
6379 | { | |
6380 | if (((status & MVPP2_RXD_L3_IP4) && | |
6381 | !(status & MVPP2_RXD_IP4_HEADER_ERR)) || | |
6382 | (status & MVPP2_RXD_L3_IP6)) | |
6383 | if (((status & MVPP2_RXD_L4_UDP) || | |
6384 | (status & MVPP2_RXD_L4_TCP)) && | |
6385 | (status & MVPP2_RXD_L4_CSUM_OK)) { | |
6386 | skb->csum = 0; | |
6387 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
6388 | return; | |
6389 | } | |
6390 | ||
6391 | skb->ip_summed = CHECKSUM_NONE; | |
6392 | } | |
6393 | ||
6394 | /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ | |
6395 | static int mvpp2_rx_refill(struct mvpp2_port *port, | |
56b8aae9 | 6396 | struct mvpp2_bm_pool *bm_pool, int pool) |
3f518509 | 6397 | { |
20396136 | 6398 | dma_addr_t dma_addr; |
4e4a105f | 6399 | phys_addr_t phys_addr; |
0e037281 | 6400 | void *buf; |
3f518509 | 6401 | |
3f518509 | 6402 | /* No recycle or too many buffers are in use, so allocate a new skb */ |
4e4a105f TP |
6403 | buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, |
6404 | GFP_ATOMIC); | |
0e037281 | 6405 | if (!buf) |
3f518509 MW |
6406 | return -ENOMEM; |
6407 | ||
7d7627ba | 6408 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
7ef7e1d9 | 6409 | |
3f518509 MW |
6410 | return 0; |
6411 | } | |
6412 | ||
6413 | /* Handle tx checksum */ | |
6414 | static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) | |
6415 | { | |
6416 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6417 | int ip_hdr_len = 0; | |
6418 | u8 l4_proto; | |
6419 | ||
6420 | if (skb->protocol == htons(ETH_P_IP)) { | |
6421 | struct iphdr *ip4h = ip_hdr(skb); | |
6422 | ||
6423 | /* Calculate IPv4 checksum and L4 checksum */ | |
6424 | ip_hdr_len = ip4h->ihl; | |
6425 | l4_proto = ip4h->protocol; | |
6426 | } else if (skb->protocol == htons(ETH_P_IPV6)) { | |
6427 | struct ipv6hdr *ip6h = ipv6_hdr(skb); | |
6428 | ||
6429 | /* Read l4_protocol from one of IPv6 extra headers */ | |
6430 | if (skb_network_header_len(skb) > 0) | |
6431 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
6432 | l4_proto = ip6h->nexthdr; | |
6433 | } else { | |
6434 | return MVPP2_TXD_L4_CSUM_NOT; | |
6435 | } | |
6436 | ||
6437 | return mvpp2_txq_desc_csum(skb_network_offset(skb), | |
6438 | skb->protocol, ip_hdr_len, l4_proto); | |
6439 | } | |
6440 | ||
6441 | return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; | |
6442 | } | |
6443 | ||
3f518509 | 6444 | /* Main rx processing */ |
591f4cfa TP |
6445 | static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, |
6446 | int rx_todo, struct mvpp2_rx_queue *rxq) | |
3f518509 MW |
6447 | { |
6448 | struct net_device *dev = port->dev; | |
b5015854 MW |
6449 | int rx_received; |
6450 | int rx_done = 0; | |
3f518509 MW |
6451 | u32 rcvd_pkts = 0; |
6452 | u32 rcvd_bytes = 0; | |
6453 | ||
6454 | /* Get number of received packets and clamp the to-do */ | |
6455 | rx_received = mvpp2_rxq_received(port, rxq->id); | |
6456 | if (rx_todo > rx_received) | |
6457 | rx_todo = rx_received; | |
6458 | ||
b5015854 | 6459 | while (rx_done < rx_todo) { |
3f518509 MW |
6460 | struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); |
6461 | struct mvpp2_bm_pool *bm_pool; | |
6462 | struct sk_buff *skb; | |
0e037281 | 6463 | unsigned int frag_size; |
20396136 | 6464 | dma_addr_t dma_addr; |
ac3dd277 | 6465 | phys_addr_t phys_addr; |
56b8aae9 | 6466 | u32 rx_status; |
3f518509 | 6467 | int pool, rx_bytes, err; |
0e037281 | 6468 | void *data; |
3f518509 | 6469 | |
b5015854 | 6470 | rx_done++; |
ac3dd277 TP |
6471 | rx_status = mvpp2_rxdesc_status_get(port, rx_desc); |
6472 | rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); | |
6473 | rx_bytes -= MVPP2_MH_SIZE; | |
6474 | dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); | |
6475 | phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); | |
6476 | data = (void *)phys_to_virt(phys_addr); | |
6477 | ||
56b8aae9 TP |
6478 | pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> |
6479 | MVPP2_RXD_BM_POOL_ID_OFFS; | |
3f518509 | 6480 | bm_pool = &port->priv->bm_pools[pool]; |
3f518509 MW |
6481 | |
6482 | /* In case of an error, release the requested buffer pointer | |
6483 | * to the Buffer Manager. This request process is controlled | |
6484 | * by the hardware, and the information about the buffer is | |
6485 | * comprised by the RX descriptor. | |
6486 | */ | |
6487 | if (rx_status & MVPP2_RXD_ERR_SUMMARY) { | |
8a52488b | 6488 | err_drop_frame: |
3f518509 MW |
6489 | dev->stats.rx_errors++; |
6490 | mvpp2_rx_error(port, rx_desc); | |
b5015854 | 6491 | /* Return the buffer to the pool */ |
7d7627ba | 6492 | mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); |
3f518509 MW |
6493 | continue; |
6494 | } | |
6495 | ||
0e037281 TP |
6496 | if (bm_pool->frag_size > PAGE_SIZE) |
6497 | frag_size = 0; | |
6498 | else | |
6499 | frag_size = bm_pool->frag_size; | |
6500 | ||
6501 | skb = build_skb(data, frag_size); | |
6502 | if (!skb) { | |
6503 | netdev_warn(port->dev, "skb build failed\n"); | |
6504 | goto err_drop_frame; | |
6505 | } | |
3f518509 | 6506 | |
56b8aae9 | 6507 | err = mvpp2_rx_refill(port, bm_pool, pool); |
b5015854 MW |
6508 | if (err) { |
6509 | netdev_err(port->dev, "failed to refill BM pools\n"); | |
6510 | goto err_drop_frame; | |
6511 | } | |
6512 | ||
20396136 | 6513 | dma_unmap_single(dev->dev.parent, dma_addr, |
4229d502 MW |
6514 | bm_pool->buf_size, DMA_FROM_DEVICE); |
6515 | ||
3f518509 MW |
6516 | rcvd_pkts++; |
6517 | rcvd_bytes += rx_bytes; | |
3f518509 | 6518 | |
0e037281 | 6519 | skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); |
3f518509 MW |
6520 | skb_put(skb, rx_bytes); |
6521 | skb->protocol = eth_type_trans(skb, dev); | |
6522 | mvpp2_rx_csum(port, rx_status, skb); | |
6523 | ||
591f4cfa | 6524 | napi_gro_receive(napi, skb); |
3f518509 MW |
6525 | } |
6526 | ||
6527 | if (rcvd_pkts) { | |
6528 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
6529 | ||
6530 | u64_stats_update_begin(&stats->syncp); | |
6531 | stats->rx_packets += rcvd_pkts; | |
6532 | stats->rx_bytes += rcvd_bytes; | |
6533 | u64_stats_update_end(&stats->syncp); | |
6534 | } | |
6535 | ||
6536 | /* Update Rx queue management counters */ | |
6537 | wmb(); | |
b5015854 | 6538 | mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); |
3f518509 MW |
6539 | |
6540 | return rx_todo; | |
6541 | } | |
6542 | ||
6543 | static inline void | |
ac3dd277 | 6544 | tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, |
3f518509 MW |
6545 | struct mvpp2_tx_desc *desc) |
6546 | { | |
20920267 AT |
6547 | struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); |
6548 | ||
ac3dd277 TP |
6549 | dma_addr_t buf_dma_addr = |
6550 | mvpp2_txdesc_dma_addr_get(port, desc); | |
6551 | size_t buf_sz = | |
6552 | mvpp2_txdesc_size_get(port, desc); | |
20920267 AT |
6553 | if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) |
6554 | dma_unmap_single(port->dev->dev.parent, buf_dma_addr, | |
6555 | buf_sz, DMA_TO_DEVICE); | |
3f518509 MW |
6556 | mvpp2_txq_desc_put(txq); |
6557 | } | |
6558 | ||
6559 | /* Handle tx fragmentation processing */ | |
6560 | static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, | |
6561 | struct mvpp2_tx_queue *aggr_txq, | |
6562 | struct mvpp2_tx_queue *txq) | |
6563 | { | |
6564 | struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); | |
6565 | struct mvpp2_tx_desc *tx_desc; | |
6566 | int i; | |
20396136 | 6567 | dma_addr_t buf_dma_addr; |
3f518509 MW |
6568 | |
6569 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6570 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6571 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
6572 | ||
6573 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
6574 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
6575 | mvpp2_txdesc_size_set(port, tx_desc, frag->size); | |
3f518509 | 6576 | |
20396136 | 6577 | buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, |
ac3dd277 TP |
6578 | frag->size, |
6579 | DMA_TO_DEVICE); | |
20396136 | 6580 | if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { |
3f518509 | 6581 | mvpp2_txq_desc_put(txq); |
32bae631 | 6582 | goto cleanup; |
3f518509 MW |
6583 | } |
6584 | ||
6eb5d375 | 6585 | mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); |
3f518509 MW |
6586 | |
6587 | if (i == (skb_shinfo(skb)->nr_frags - 1)) { | |
6588 | /* Last descriptor */ | |
ac3dd277 TP |
6589 | mvpp2_txdesc_cmd_set(port, tx_desc, |
6590 | MVPP2_TXD_L_DESC); | |
6591 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
6592 | } else { |
6593 | /* Descriptor in the middle: Not First, Not Last */ | |
ac3dd277 TP |
6594 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); |
6595 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
6596 | } |
6597 | } | |
6598 | ||
6599 | return 0; | |
32bae631 | 6600 | cleanup: |
3f518509 MW |
6601 | /* Release all descriptors that were used to map fragments of |
6602 | * this packet, as well as the corresponding DMA mappings | |
6603 | */ | |
6604 | for (i = i - 1; i >= 0; i--) { | |
6605 | tx_desc = txq->descs + i; | |
ac3dd277 | 6606 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 MW |
6607 | } |
6608 | ||
6609 | return -ENOMEM; | |
6610 | } | |
6611 | ||
186cd4d4 AT |
6612 | static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, |
6613 | struct net_device *dev, | |
6614 | struct mvpp2_tx_queue *txq, | |
6615 | struct mvpp2_tx_queue *aggr_txq, | |
6616 | struct mvpp2_txq_pcpu *txq_pcpu, | |
6617 | int hdr_sz) | |
6618 | { | |
6619 | struct mvpp2_port *port = netdev_priv(dev); | |
6620 | struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
6621 | dma_addr_t addr; | |
6622 | ||
6623 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); | |
6624 | mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); | |
6625 | ||
6626 | addr = txq_pcpu->tso_headers_dma + | |
6627 | txq_pcpu->txq_put_index * TSO_HEADER_SIZE; | |
6eb5d375 | 6628 | mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); |
186cd4d4 AT |
6629 | |
6630 | mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | | |
6631 | MVPP2_TXD_F_DESC | | |
6632 | MVPP2_TXD_PADDING_DISABLE); | |
6633 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
6634 | } | |
6635 | ||
6636 | static inline int mvpp2_tso_put_data(struct sk_buff *skb, | |
6637 | struct net_device *dev, struct tso_t *tso, | |
6638 | struct mvpp2_tx_queue *txq, | |
6639 | struct mvpp2_tx_queue *aggr_txq, | |
6640 | struct mvpp2_txq_pcpu *txq_pcpu, | |
6641 | int sz, bool left, bool last) | |
6642 | { | |
6643 | struct mvpp2_port *port = netdev_priv(dev); | |
6644 | struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
6645 | dma_addr_t buf_dma_addr; | |
6646 | ||
6647 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); | |
6648 | mvpp2_txdesc_size_set(port, tx_desc, sz); | |
6649 | ||
6650 | buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, | |
6651 | DMA_TO_DEVICE); | |
6652 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { | |
6653 | mvpp2_txq_desc_put(txq); | |
6654 | return -ENOMEM; | |
6655 | } | |
6656 | ||
6eb5d375 | 6657 | mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); |
186cd4d4 AT |
6658 | |
6659 | if (!left) { | |
6660 | mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); | |
6661 | if (last) { | |
6662 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
6663 | return 0; | |
6664 | } | |
6665 | } else { | |
6666 | mvpp2_txdesc_cmd_set(port, tx_desc, 0); | |
6667 | } | |
6668 | ||
6669 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
6670 | return 0; | |
6671 | } | |
6672 | ||
6673 | static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
6674 | struct mvpp2_tx_queue *txq, | |
6675 | struct mvpp2_tx_queue *aggr_txq, | |
6676 | struct mvpp2_txq_pcpu *txq_pcpu) | |
6677 | { | |
6678 | struct mvpp2_port *port = netdev_priv(dev); | |
6679 | struct tso_t tso; | |
6680 | int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
6681 | int i, len, descs = 0; | |
6682 | ||
6683 | /* Check number of available descriptors */ | |
6684 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, | |
6685 | tso_count_descs(skb)) || | |
6686 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, | |
6687 | tso_count_descs(skb))) | |
6688 | return 0; | |
6689 | ||
6690 | tso_start(skb, &tso); | |
6691 | len = skb->len - hdr_sz; | |
6692 | while (len > 0) { | |
6693 | int left = min_t(int, skb_shinfo(skb)->gso_size, len); | |
6694 | char *hdr = txq_pcpu->tso_headers + | |
6695 | txq_pcpu->txq_put_index * TSO_HEADER_SIZE; | |
6696 | ||
6697 | len -= left; | |
6698 | descs++; | |
6699 | ||
6700 | tso_build_hdr(skb, hdr, &tso, left, len == 0); | |
6701 | mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); | |
6702 | ||
6703 | while (left > 0) { | |
6704 | int sz = min_t(int, tso.size, left); | |
6705 | left -= sz; | |
6706 | descs++; | |
6707 | ||
6708 | if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, | |
6709 | txq_pcpu, sz, left, len == 0)) | |
6710 | goto release; | |
6711 | tso_build_data(skb, &tso, sz); | |
6712 | } | |
6713 | } | |
6714 | ||
6715 | return descs; | |
6716 | ||
6717 | release: | |
6718 | for (i = descs - 1; i >= 0; i--) { | |
6719 | struct mvpp2_tx_desc *tx_desc = txq->descs + i; | |
6720 | tx_desc_unmap_put(port, txq, tx_desc); | |
6721 | } | |
6722 | return 0; | |
6723 | } | |
6724 | ||
3f518509 MW |
6725 | /* Main tx processing */ |
6726 | static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev) | |
6727 | { | |
6728 | struct mvpp2_port *port = netdev_priv(dev); | |
6729 | struct mvpp2_tx_queue *txq, *aggr_txq; | |
6730 | struct mvpp2_txq_pcpu *txq_pcpu; | |
6731 | struct mvpp2_tx_desc *tx_desc; | |
20396136 | 6732 | dma_addr_t buf_dma_addr; |
3f518509 MW |
6733 | int frags = 0; |
6734 | u16 txq_id; | |
6735 | u32 tx_cmd; | |
6736 | ||
6737 | txq_id = skb_get_queue_mapping(skb); | |
6738 | txq = port->txqs[txq_id]; | |
6739 | txq_pcpu = this_cpu_ptr(txq->pcpu); | |
6740 | aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; | |
6741 | ||
186cd4d4 AT |
6742 | if (skb_is_gso(skb)) { |
6743 | frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); | |
6744 | goto out; | |
6745 | } | |
3f518509 MW |
6746 | frags = skb_shinfo(skb)->nr_frags + 1; |
6747 | ||
6748 | /* Check number of available descriptors */ | |
6749 | if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || | |
6750 | mvpp2_txq_reserved_desc_num_proc(port->priv, txq, | |
6751 | txq_pcpu, frags)) { | |
6752 | frags = 0; | |
6753 | goto out; | |
6754 | } | |
6755 | ||
6756 | /* Get a descriptor for the first part of the packet */ | |
6757 | tx_desc = mvpp2_txq_next_desc_get(aggr_txq); | |
ac3dd277 TP |
6758 | mvpp2_txdesc_txq_set(port, tx_desc, txq->id); |
6759 | mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); | |
3f518509 | 6760 | |
20396136 | 6761 | buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, |
ac3dd277 | 6762 | skb_headlen(skb), DMA_TO_DEVICE); |
20396136 | 6763 | if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { |
3f518509 MW |
6764 | mvpp2_txq_desc_put(txq); |
6765 | frags = 0; | |
6766 | goto out; | |
6767 | } | |
ac3dd277 | 6768 | |
6eb5d375 | 6769 | mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); |
3f518509 MW |
6770 | |
6771 | tx_cmd = mvpp2_skb_tx_csum(port, skb); | |
6772 | ||
6773 | if (frags == 1) { | |
6774 | /* First and Last descriptor */ | |
6775 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; | |
ac3dd277 TP |
6776 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
6777 | mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); | |
3f518509 MW |
6778 | } else { |
6779 | /* First but not Last */ | |
6780 | tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; | |
ac3dd277 TP |
6781 | mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); |
6782 | mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); | |
3f518509 MW |
6783 | |
6784 | /* Continue with other skb fragments */ | |
6785 | if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { | |
ac3dd277 | 6786 | tx_desc_unmap_put(port, txq, tx_desc); |
3f518509 | 6787 | frags = 0; |
3f518509 MW |
6788 | } |
6789 | } | |
6790 | ||
3f518509 MW |
6791 | out: |
6792 | if (frags > 0) { | |
6793 | struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); | |
186cd4d4 AT |
6794 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
6795 | ||
6796 | txq_pcpu->reserved_num -= frags; | |
6797 | txq_pcpu->count += frags; | |
6798 | aggr_txq->count += frags; | |
6799 | ||
6800 | /* Enable transmit */ | |
6801 | wmb(); | |
6802 | mvpp2_aggr_txq_pend_desc_add(port, frags); | |
6803 | ||
1d17db08 | 6804 | if (txq_pcpu->count >= txq_pcpu->stop_threshold) |
186cd4d4 | 6805 | netif_tx_stop_queue(nq); |
3f518509 MW |
6806 | |
6807 | u64_stats_update_begin(&stats->syncp); | |
6808 | stats->tx_packets++; | |
6809 | stats->tx_bytes += skb->len; | |
6810 | u64_stats_update_end(&stats->syncp); | |
6811 | } else { | |
6812 | dev->stats.tx_dropped++; | |
6813 | dev_kfree_skb_any(skb); | |
6814 | } | |
6815 | ||
edc660fa | 6816 | /* Finalize TX processing */ |
082297e6 | 6817 | if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) |
edc660fa MW |
6818 | mvpp2_txq_done(port, txq, txq_pcpu); |
6819 | ||
6820 | /* Set the timer in case not all frags were processed */ | |
213f428f TP |
6821 | if (!port->has_tx_irqs && txq_pcpu->count <= frags && |
6822 | txq_pcpu->count > 0) { | |
edc660fa MW |
6823 | struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); |
6824 | ||
6825 | mvpp2_timer_set(port_pcpu); | |
6826 | } | |
6827 | ||
3f518509 MW |
6828 | return NETDEV_TX_OK; |
6829 | } | |
6830 | ||
6831 | static inline void mvpp2_cause_error(struct net_device *dev, int cause) | |
6832 | { | |
6833 | if (cause & MVPP2_CAUSE_FCS_ERR_MASK) | |
6834 | netdev_err(dev, "FCS error\n"); | |
6835 | if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) | |
6836 | netdev_err(dev, "rx fifo overrun error\n"); | |
6837 | if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) | |
6838 | netdev_err(dev, "tx fifo underrun error\n"); | |
6839 | } | |
6840 | ||
edc660fa | 6841 | static int mvpp2_poll(struct napi_struct *napi, int budget) |
3f518509 | 6842 | { |
213f428f | 6843 | u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; |
edc660fa MW |
6844 | int rx_done = 0; |
6845 | struct mvpp2_port *port = netdev_priv(napi->dev); | |
591f4cfa | 6846 | struct mvpp2_queue_vector *qv; |
a786841d | 6847 | int cpu = smp_processor_id(); |
3f518509 | 6848 | |
591f4cfa TP |
6849 | qv = container_of(napi, struct mvpp2_queue_vector, napi); |
6850 | ||
3f518509 MW |
6851 | /* Rx/Tx cause register |
6852 | * | |
6853 | * Bits 0-15: each bit indicates received packets on the Rx queue | |
6854 | * (bit 0 is for Rx queue 0). | |
6855 | * | |
6856 | * Bits 16-23: each bit indicates transmitted packets on the Tx queue | |
6857 | * (bit 16 is for Tx queue 0). | |
6858 | * | |
6859 | * Each CPU has its own Rx/Tx cause register | |
6860 | */ | |
cdcfeb0f YM |
6861 | cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id, |
6862 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); | |
3f518509 | 6863 | |
213f428f | 6864 | cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; |
3f518509 MW |
6865 | if (cause_misc) { |
6866 | mvpp2_cause_error(port->dev, cause_misc); | |
6867 | ||
6868 | /* Clear the cause register */ | |
6869 | mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); | |
a786841d TP |
6870 | mvpp2_percpu_write(port->priv, cpu, |
6871 | MVPP2_ISR_RX_TX_CAUSE_REG(port->id), | |
6872 | cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); | |
3f518509 MW |
6873 | } |
6874 | ||
213f428f TP |
6875 | cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; |
6876 | if (cause_tx) { | |
6877 | cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; | |
6878 | mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); | |
6879 | } | |
3f518509 MW |
6880 | |
6881 | /* Process RX packets */ | |
213f428f TP |
6882 | cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; |
6883 | cause_rx <<= qv->first_rxq; | |
591f4cfa | 6884 | cause_rx |= qv->pending_cause_rx; |
3f518509 MW |
6885 | while (cause_rx && budget > 0) { |
6886 | int count; | |
6887 | struct mvpp2_rx_queue *rxq; | |
6888 | ||
6889 | rxq = mvpp2_get_rx_queue(port, cause_rx); | |
6890 | if (!rxq) | |
6891 | break; | |
6892 | ||
591f4cfa | 6893 | count = mvpp2_rx(port, napi, budget, rxq); |
3f518509 MW |
6894 | rx_done += count; |
6895 | budget -= count; | |
6896 | if (budget > 0) { | |
6897 | /* Clear the bit associated to this Rx queue | |
6898 | * so that next iteration will continue from | |
6899 | * the next Rx queue. | |
6900 | */ | |
6901 | cause_rx &= ~(1 << rxq->logic_rxq); | |
6902 | } | |
6903 | } | |
6904 | ||
6905 | if (budget > 0) { | |
6906 | cause_rx = 0; | |
6ad20165 | 6907 | napi_complete_done(napi, rx_done); |
3f518509 | 6908 | |
591f4cfa | 6909 | mvpp2_qvec_interrupt_enable(qv); |
3f518509 | 6910 | } |
591f4cfa | 6911 | qv->pending_cause_rx = cause_rx; |
3f518509 MW |
6912 | return rx_done; |
6913 | } | |
6914 | ||
4bb04326 | 6915 | static void mvpp22_mode_reconfigure(struct mvpp2_port *port) |
3f518509 | 6916 | { |
4bb04326 AT |
6917 | u32 ctrl3; |
6918 | ||
6919 | /* comphy reconfiguration */ | |
6920 | mvpp22_comphy_init(port); | |
6921 | ||
6922 | /* gop reconfiguration */ | |
6923 | mvpp22_gop_init(port); | |
6924 | ||
6925 | /* Only GOP port 0 has an XLG MAC */ | |
6926 | if (port->gop_id == 0) { | |
6927 | ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); | |
6928 | ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; | |
6929 | ||
6930 | if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
6931 | port->phy_interface == PHY_INTERFACE_MODE_10GKR) | |
6932 | ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; | |
6933 | else | |
6934 | ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; | |
6935 | ||
6936 | writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); | |
6937 | } | |
8e07269d | 6938 | |
76eb1b1d SC |
6939 | if (port->gop_id == 0 && |
6940 | (port->phy_interface == PHY_INTERFACE_MODE_XAUI || | |
6941 | port->phy_interface == PHY_INTERFACE_MODE_10GKR)) | |
6942 | mvpp2_xlg_max_rx_size_set(port); | |
6943 | else | |
6944 | mvpp2_gmac_max_rx_size_set(port); | |
4bb04326 AT |
6945 | } |
6946 | ||
6947 | /* Set hw internals when starting port */ | |
6948 | static void mvpp2_start_dev(struct mvpp2_port *port) | |
6949 | { | |
6950 | int i; | |
76eb1b1d | 6951 | |
3f518509 MW |
6952 | mvpp2_txp_max_tx_size_set(port); |
6953 | ||
591f4cfa TP |
6954 | for (i = 0; i < port->nqvecs; i++) |
6955 | napi_enable(&port->qvecs[i].napi); | |
3f518509 MW |
6956 | |
6957 | /* Enable interrupts on all CPUs */ | |
6958 | mvpp2_interrupts_enable(port); | |
6959 | ||
4bb04326 AT |
6960 | if (port->priv->hw_version == MVPP22) |
6961 | mvpp22_mode_reconfigure(port); | |
6962 | ||
6963 | if (port->phylink) { | |
6964 | phylink_start(port->phylink); | |
6965 | } else { | |
6966 | /* Phylink isn't used as of now for ACPI, so the MAC has to be | |
6967 | * configured manually when the interface is started. This will | |
6968 | * be removed as soon as the phylink ACPI support lands in. | |
6969 | */ | |
6970 | struct phylink_link_state state = { | |
6971 | .interface = port->phy_interface, | |
6972 | .link = 1, | |
6973 | }; | |
6974 | mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state); | |
542897d9 | 6975 | } |
f84bf386 | 6976 | |
3f518509 MW |
6977 | netif_tx_start_all_queues(port->dev); |
6978 | } | |
6979 | ||
6980 | /* Set hw internals when stopping port */ | |
6981 | static void mvpp2_stop_dev(struct mvpp2_port *port) | |
6982 | { | |
591f4cfa | 6983 | int i; |
8e07269d | 6984 | |
3f518509 MW |
6985 | /* Disable interrupts on all CPUs */ |
6986 | mvpp2_interrupts_disable(port); | |
6987 | ||
591f4cfa TP |
6988 | for (i = 0; i < port->nqvecs; i++) |
6989 | napi_disable(&port->qvecs[i].napi); | |
3f518509 | 6990 | |
4bb04326 AT |
6991 | if (port->phylink) |
6992 | phylink_stop(port->phylink); | |
542897d9 | 6993 | phy_power_off(port->comphy); |
3f518509 MW |
6994 | } |
6995 | ||
3f518509 MW |
6996 | static int mvpp2_check_ringparam_valid(struct net_device *dev, |
6997 | struct ethtool_ringparam *ring) | |
6998 | { | |
6999 | u16 new_rx_pending = ring->rx_pending; | |
7000 | u16 new_tx_pending = ring->tx_pending; | |
7001 | ||
7002 | if (ring->rx_pending == 0 || ring->tx_pending == 0) | |
7003 | return -EINVAL; | |
7004 | ||
7cf87e4a YM |
7005 | if (ring->rx_pending > MVPP2_MAX_RXD_MAX) |
7006 | new_rx_pending = MVPP2_MAX_RXD_MAX; | |
3f518509 MW |
7007 | else if (!IS_ALIGNED(ring->rx_pending, 16)) |
7008 | new_rx_pending = ALIGN(ring->rx_pending, 16); | |
7009 | ||
7cf87e4a YM |
7010 | if (ring->tx_pending > MVPP2_MAX_TXD_MAX) |
7011 | new_tx_pending = MVPP2_MAX_TXD_MAX; | |
3f518509 MW |
7012 | else if (!IS_ALIGNED(ring->tx_pending, 32)) |
7013 | new_tx_pending = ALIGN(ring->tx_pending, 32); | |
7014 | ||
76e583c5 AT |
7015 | /* The Tx ring size cannot be smaller than the minimum number of |
7016 | * descriptors needed for TSO. | |
7017 | */ | |
7018 | if (new_tx_pending < MVPP2_MAX_SKB_DESCS) | |
7019 | new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); | |
7020 | ||
3f518509 MW |
7021 | if (ring->rx_pending != new_rx_pending) { |
7022 | netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", | |
7023 | ring->rx_pending, new_rx_pending); | |
7024 | ring->rx_pending = new_rx_pending; | |
7025 | } | |
7026 | ||
7027 | if (ring->tx_pending != new_tx_pending) { | |
7028 | netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", | |
7029 | ring->tx_pending, new_tx_pending); | |
7030 | ring->tx_pending = new_tx_pending; | |
7031 | } | |
7032 | ||
7033 | return 0; | |
7034 | } | |
7035 | ||
26975821 | 7036 | static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) |
3f518509 MW |
7037 | { |
7038 | u32 mac_addr_l, mac_addr_m, mac_addr_h; | |
7039 | ||
7040 | mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); | |
7041 | mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); | |
7042 | mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); | |
7043 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
7044 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
7045 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
7046 | addr[3] = mac_addr_h & 0xFF; | |
7047 | addr[4] = mac_addr_m & 0xFF; | |
7048 | addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; | |
7049 | } | |
7050 | ||
591f4cfa TP |
7051 | static int mvpp2_irqs_init(struct mvpp2_port *port) |
7052 | { | |
7053 | int err, i; | |
7054 | ||
7055 | for (i = 0; i < port->nqvecs; i++) { | |
7056 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7057 | ||
13c249a9 MZ |
7058 | if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) |
7059 | irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); | |
7060 | ||
591f4cfa TP |
7061 | err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); |
7062 | if (err) | |
7063 | goto err; | |
213f428f TP |
7064 | |
7065 | if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) | |
7066 | irq_set_affinity_hint(qv->irq, | |
7067 | cpumask_of(qv->sw_thread_id)); | |
591f4cfa TP |
7068 | } |
7069 | ||
7070 | return 0; | |
7071 | err: | |
7072 | for (i = 0; i < port->nqvecs; i++) { | |
7073 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7074 | ||
213f428f | 7075 | irq_set_affinity_hint(qv->irq, NULL); |
591f4cfa TP |
7076 | free_irq(qv->irq, qv); |
7077 | } | |
7078 | ||
7079 | return err; | |
7080 | } | |
7081 | ||
7082 | static void mvpp2_irqs_deinit(struct mvpp2_port *port) | |
7083 | { | |
7084 | int i; | |
7085 | ||
7086 | for (i = 0; i < port->nqvecs; i++) { | |
7087 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7088 | ||
213f428f | 7089 | irq_set_affinity_hint(qv->irq, NULL); |
13c249a9 | 7090 | irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); |
591f4cfa TP |
7091 | free_irq(qv->irq, qv); |
7092 | } | |
7093 | } | |
7094 | ||
1d7d15d7 AT |
7095 | static void mvpp22_init_rss(struct mvpp2_port *port) |
7096 | { | |
7097 | struct mvpp2 *priv = port->priv; | |
7098 | int i; | |
7099 | ||
7100 | /* Set the table width: replace the whole classifier Rx queue number | |
7101 | * with the ones configured in RSS table entries. | |
7102 | */ | |
7103 | mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_TABLE(0)); | |
7104 | mvpp2_write(priv, MVPP22_RSS_WIDTH, 8); | |
7105 | ||
7106 | /* Loop through the classifier Rx Queues and map them to a RSS table. | |
7107 | * Map them all to the first table (0) by default. | |
7108 | */ | |
7109 | for (i = 0; i < MVPP2_CLS_RX_QUEUES; i++) { | |
7110 | mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_QUEUE(i)); | |
7111 | mvpp2_write(priv, MVPP22_RSS_TABLE, | |
7112 | MVPP22_RSS_TABLE_POINTER(0)); | |
7113 | } | |
7114 | ||
7115 | /* Configure the first table to evenly distribute the packets across | |
7116 | * real Rx Queues. The table entries map a hash to an port Rx Queue. | |
7117 | */ | |
7118 | for (i = 0; i < MVPP22_RSS_TABLE_ENTRIES; i++) { | |
7119 | u32 sel = MVPP22_RSS_INDEX_TABLE(0) | | |
7120 | MVPP22_RSS_INDEX_TABLE_ENTRY(i); | |
7121 | mvpp2_write(priv, MVPP22_RSS_INDEX, sel); | |
7122 | ||
7123 | mvpp2_write(priv, MVPP22_RSS_TABLE_ENTRY, i % port->nrxqs); | |
7124 | } | |
7125 | ||
7126 | } | |
7127 | ||
3f518509 MW |
7128 | static int mvpp2_open(struct net_device *dev) |
7129 | { | |
7130 | struct mvpp2_port *port = netdev_priv(dev); | |
fd3651b2 | 7131 | struct mvpp2 *priv = port->priv; |
3f518509 MW |
7132 | unsigned char mac_bcast[ETH_ALEN] = { |
7133 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
4bb04326 | 7134 | bool valid = false; |
3f518509 MW |
7135 | int err; |
7136 | ||
ce2a27c7 | 7137 | err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); |
3f518509 MW |
7138 | if (err) { |
7139 | netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); | |
7140 | return err; | |
7141 | } | |
ce2a27c7 | 7142 | err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); |
3f518509 | 7143 | if (err) { |
ce2a27c7 | 7144 | netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); |
3f518509 MW |
7145 | return err; |
7146 | } | |
7147 | err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); | |
7148 | if (err) { | |
7149 | netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); | |
7150 | return err; | |
7151 | } | |
7152 | err = mvpp2_prs_def_flow(port); | |
7153 | if (err) { | |
7154 | netdev_err(dev, "mvpp2_prs_def_flow failed\n"); | |
7155 | return err; | |
7156 | } | |
7157 | ||
7158 | /* Allocate the Rx/Tx queues */ | |
7159 | err = mvpp2_setup_rxqs(port); | |
7160 | if (err) { | |
7161 | netdev_err(port->dev, "cannot allocate Rx queues\n"); | |
7162 | return err; | |
7163 | } | |
7164 | ||
7165 | err = mvpp2_setup_txqs(port); | |
7166 | if (err) { | |
7167 | netdev_err(port->dev, "cannot allocate Tx queues\n"); | |
7168 | goto err_cleanup_rxqs; | |
7169 | } | |
7170 | ||
591f4cfa | 7171 | err = mvpp2_irqs_init(port); |
3f518509 | 7172 | if (err) { |
591f4cfa | 7173 | netdev_err(port->dev, "cannot init IRQs\n"); |
3f518509 MW |
7174 | goto err_cleanup_txqs; |
7175 | } | |
7176 | ||
4bb04326 AT |
7177 | /* Phylink isn't supported yet in ACPI mode */ |
7178 | if (port->of_node) { | |
7179 | err = phylink_of_phy_connect(port->phylink, port->of_node, 0); | |
7180 | if (err) { | |
7181 | netdev_err(port->dev, "could not attach PHY (%d)\n", | |
7182 | err); | |
7183 | goto err_free_irq; | |
7184 | } | |
7185 | ||
7186 | valid = true; | |
7187 | } | |
7188 | ||
7189 | if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { | |
fd3651b2 AT |
7190 | err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, |
7191 | dev->name, port); | |
7192 | if (err) { | |
7193 | netdev_err(port->dev, "cannot request link IRQ %d\n", | |
7194 | port->link_irq); | |
7195 | goto err_free_irq; | |
7196 | } | |
7197 | ||
7198 | mvpp22_gop_setup_irq(port); | |
fd3651b2 | 7199 | |
4bb04326 AT |
7200 | /* In default link is down */ |
7201 | netif_carrier_off(port->dev); | |
3f518509 | 7202 | |
4bb04326 AT |
7203 | valid = true; |
7204 | } else { | |
7205 | port->link_irq = 0; | |
7206 | } | |
7207 | ||
7208 | if (!valid) { | |
7209 | netdev_err(port->dev, | |
7210 | "invalid configuration: no dt or link IRQ"); | |
7211 | goto err_free_irq; | |
7212 | } | |
3f518509 MW |
7213 | |
7214 | /* Unmask interrupts on all CPUs */ | |
7215 | on_each_cpu(mvpp2_interrupts_unmask, port, 1); | |
213f428f | 7216 | mvpp2_shared_interrupt_mask_unmask(port, false); |
3f518509 MW |
7217 | |
7218 | mvpp2_start_dev(port); | |
7219 | ||
1d7d15d7 AT |
7220 | if (priv->hw_version == MVPP22) |
7221 | mvpp22_init_rss(port); | |
7222 | ||
118d6298 | 7223 | /* Start hardware statistics gathering */ |
e5c500eb | 7224 | queue_delayed_work(priv->stats_queue, &port->stats_work, |
118d6298 MR |
7225 | MVPP2_MIB_COUNTERS_STATS_DELAY); |
7226 | ||
3f518509 MW |
7227 | return 0; |
7228 | ||
7229 | err_free_irq: | |
591f4cfa | 7230 | mvpp2_irqs_deinit(port); |
3f518509 MW |
7231 | err_cleanup_txqs: |
7232 | mvpp2_cleanup_txqs(port); | |
7233 | err_cleanup_rxqs: | |
7234 | mvpp2_cleanup_rxqs(port); | |
7235 | return err; | |
7236 | } | |
7237 | ||
7238 | static int mvpp2_stop(struct net_device *dev) | |
7239 | { | |
7240 | struct mvpp2_port *port = netdev_priv(dev); | |
edc660fa MW |
7241 | struct mvpp2_port_pcpu *port_pcpu; |
7242 | int cpu; | |
3f518509 MW |
7243 | |
7244 | mvpp2_stop_dev(port); | |
3f518509 MW |
7245 | |
7246 | /* Mask interrupts on all CPUs */ | |
7247 | on_each_cpu(mvpp2_interrupts_mask, port, 1); | |
213f428f | 7248 | mvpp2_shared_interrupt_mask_unmask(port, true); |
3f518509 | 7249 | |
4bb04326 AT |
7250 | if (port->phylink) |
7251 | phylink_disconnect_phy(port->phylink); | |
7252 | if (port->link_irq) | |
fd3651b2 AT |
7253 | free_irq(port->link_irq, port); |
7254 | ||
591f4cfa | 7255 | mvpp2_irqs_deinit(port); |
213f428f TP |
7256 | if (!port->has_tx_irqs) { |
7257 | for_each_present_cpu(cpu) { | |
7258 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 7259 | |
213f428f TP |
7260 | hrtimer_cancel(&port_pcpu->tx_done_timer); |
7261 | port_pcpu->timer_scheduled = false; | |
7262 | tasklet_kill(&port_pcpu->tx_done_tasklet); | |
7263 | } | |
edc660fa | 7264 | } |
3f518509 MW |
7265 | mvpp2_cleanup_rxqs(port); |
7266 | mvpp2_cleanup_txqs(port); | |
7267 | ||
e5c500eb | 7268 | cancel_delayed_work_sync(&port->stats_work); |
118d6298 | 7269 | |
3f518509 MW |
7270 | return 0; |
7271 | } | |
7272 | ||
10fea26c MC |
7273 | static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, |
7274 | struct netdev_hw_addr_list *list) | |
3f518509 | 7275 | { |
3f518509 | 7276 | struct netdev_hw_addr *ha; |
10fea26c MC |
7277 | int ret; |
7278 | ||
7279 | netdev_hw_addr_list_for_each(ha, list) { | |
7280 | ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); | |
7281 | if (ret) | |
7282 | return ret; | |
3f518509 | 7283 | } |
56beda3d | 7284 | |
10fea26c MC |
7285 | return 0; |
7286 | } | |
7287 | ||
7288 | static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) | |
7289 | { | |
7290 | if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) | |
56beda3d | 7291 | mvpp2_prs_vid_enable_filtering(port); |
10fea26c MC |
7292 | else |
7293 | mvpp2_prs_vid_disable_filtering(port); | |
7294 | ||
7295 | mvpp2_prs_mac_promisc_set(port->priv, port->id, | |
7296 | MVPP2_PRS_L2_UNI_CAST, enable); | |
7297 | ||
7298 | mvpp2_prs_mac_promisc_set(port->priv, port->id, | |
7299 | MVPP2_PRS_L2_MULTI_CAST, enable); | |
7300 | } | |
7301 | ||
7302 | static void mvpp2_set_rx_mode(struct net_device *dev) | |
7303 | { | |
7304 | struct mvpp2_port *port = netdev_priv(dev); | |
7305 | ||
7306 | /* Clear the whole UC and MC list */ | |
7307 | mvpp2_prs_mac_del_all(port); | |
7308 | ||
7309 | if (dev->flags & IFF_PROMISC) { | |
7310 | mvpp2_set_rx_promisc(port, true); | |
7311 | return; | |
7312 | } | |
7313 | ||
7314 | mvpp2_set_rx_promisc(port, false); | |
7315 | ||
7316 | if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || | |
7317 | mvpp2_prs_mac_da_accept_list(port, &dev->uc)) | |
7318 | mvpp2_prs_mac_promisc_set(port->priv, port->id, | |
7319 | MVPP2_PRS_L2_UNI_CAST, true); | |
7320 | ||
7321 | if (dev->flags & IFF_ALLMULTI) { | |
7322 | mvpp2_prs_mac_promisc_set(port->priv, port->id, | |
7323 | MVPP2_PRS_L2_MULTI_CAST, true); | |
7324 | return; | |
7325 | } | |
7326 | ||
7327 | if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || | |
7328 | mvpp2_prs_mac_da_accept_list(port, &dev->mc)) | |
7329 | mvpp2_prs_mac_promisc_set(port->priv, port->id, | |
7330 | MVPP2_PRS_L2_MULTI_CAST, true); | |
3f518509 MW |
7331 | } |
7332 | ||
7333 | static int mvpp2_set_mac_address(struct net_device *dev, void *p) | |
7334 | { | |
7335 | struct mvpp2_port *port = netdev_priv(dev); | |
7336 | const struct sockaddr *addr = p; | |
7337 | int err; | |
7338 | ||
7339 | if (!is_valid_ether_addr(addr->sa_data)) { | |
7340 | err = -EADDRNOTAVAIL; | |
c1175547 | 7341 | goto log_error; |
3f518509 MW |
7342 | } |
7343 | ||
7344 | if (!netif_running(dev)) { | |
7345 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
7346 | if (!err) | |
7347 | return 0; | |
7348 | /* Reconfigure parser to accept the original MAC address */ | |
7349 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
7350 | if (err) | |
c1175547 | 7351 | goto log_error; |
3f518509 MW |
7352 | } |
7353 | ||
7354 | mvpp2_stop_dev(port); | |
7355 | ||
7356 | err = mvpp2_prs_update_mac_da(dev, addr->sa_data); | |
7357 | if (!err) | |
7358 | goto out_start; | |
7359 | ||
7360 | /* Reconfigure parser accept the original MAC address */ | |
7361 | err = mvpp2_prs_update_mac_da(dev, dev->dev_addr); | |
7362 | if (err) | |
c1175547 | 7363 | goto log_error; |
3f518509 MW |
7364 | out_start: |
7365 | mvpp2_start_dev(port); | |
7366 | mvpp2_egress_enable(port); | |
7367 | mvpp2_ingress_enable(port); | |
7368 | return 0; | |
c1175547 | 7369 | log_error: |
dfd4240a | 7370 | netdev_err(dev, "failed to change MAC address\n"); |
3f518509 MW |
7371 | return err; |
7372 | } | |
7373 | ||
7374 | static int mvpp2_change_mtu(struct net_device *dev, int mtu) | |
7375 | { | |
7376 | struct mvpp2_port *port = netdev_priv(dev); | |
7377 | int err; | |
7378 | ||
5777987e JW |
7379 | if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { |
7380 | netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, | |
7381 | ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); | |
7382 | mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); | |
3f518509 MW |
7383 | } |
7384 | ||
7385 | if (!netif_running(dev)) { | |
7386 | err = mvpp2_bm_update_mtu(dev, mtu); | |
7387 | if (!err) { | |
7388 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
7389 | return 0; | |
7390 | } | |
7391 | ||
7392 | /* Reconfigure BM to the original MTU */ | |
7393 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
7394 | if (err) | |
c1175547 | 7395 | goto log_error; |
3f518509 MW |
7396 | } |
7397 | ||
7398 | mvpp2_stop_dev(port); | |
7399 | ||
7400 | err = mvpp2_bm_update_mtu(dev, mtu); | |
7401 | if (!err) { | |
7402 | port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); | |
7403 | goto out_start; | |
7404 | } | |
7405 | ||
7406 | /* Reconfigure BM to the original MTU */ | |
7407 | err = mvpp2_bm_update_mtu(dev, dev->mtu); | |
7408 | if (err) | |
c1175547 | 7409 | goto log_error; |
3f518509 MW |
7410 | |
7411 | out_start: | |
7412 | mvpp2_start_dev(port); | |
7413 | mvpp2_egress_enable(port); | |
7414 | mvpp2_ingress_enable(port); | |
7415 | ||
7416 | return 0; | |
c1175547 | 7417 | log_error: |
dfd4240a | 7418 | netdev_err(dev, "failed to change MTU\n"); |
3f518509 MW |
7419 | return err; |
7420 | } | |
7421 | ||
bc1f4470 | 7422 | static void |
3f518509 MW |
7423 | mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
7424 | { | |
7425 | struct mvpp2_port *port = netdev_priv(dev); | |
7426 | unsigned int start; | |
7427 | int cpu; | |
7428 | ||
7429 | for_each_possible_cpu(cpu) { | |
7430 | struct mvpp2_pcpu_stats *cpu_stats; | |
7431 | u64 rx_packets; | |
7432 | u64 rx_bytes; | |
7433 | u64 tx_packets; | |
7434 | u64 tx_bytes; | |
7435 | ||
7436 | cpu_stats = per_cpu_ptr(port->stats, cpu); | |
7437 | do { | |
7438 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); | |
7439 | rx_packets = cpu_stats->rx_packets; | |
7440 | rx_bytes = cpu_stats->rx_bytes; | |
7441 | tx_packets = cpu_stats->tx_packets; | |
7442 | tx_bytes = cpu_stats->tx_bytes; | |
7443 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); | |
7444 | ||
7445 | stats->rx_packets += rx_packets; | |
7446 | stats->rx_bytes += rx_bytes; | |
7447 | stats->tx_packets += tx_packets; | |
7448 | stats->tx_bytes += tx_bytes; | |
7449 | } | |
7450 | ||
7451 | stats->rx_errors = dev->stats.rx_errors; | |
7452 | stats->rx_dropped = dev->stats.rx_dropped; | |
7453 | stats->tx_dropped = dev->stats.tx_dropped; | |
3f518509 MW |
7454 | } |
7455 | ||
bd695a5f TP |
7456 | static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
7457 | { | |
4bb04326 | 7458 | struct mvpp2_port *port = netdev_priv(dev); |
bd695a5f | 7459 | |
4bb04326 | 7460 | if (!port->phylink) |
bd695a5f TP |
7461 | return -ENOTSUPP; |
7462 | ||
4bb04326 | 7463 | return phylink_mii_ioctl(port->phylink, ifr, cmd); |
bd695a5f TP |
7464 | } |
7465 | ||
56beda3d MC |
7466 | static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) |
7467 | { | |
7468 | struct mvpp2_port *port = netdev_priv(dev); | |
7469 | int ret; | |
7470 | ||
7471 | ret = mvpp2_prs_vid_entry_add(port, vid); | |
7472 | if (ret) | |
7473 | netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", | |
7474 | MVPP2_PRS_VLAN_FILT_MAX - 1); | |
7475 | return ret; | |
7476 | } | |
7477 | ||
7478 | static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) | |
7479 | { | |
7480 | struct mvpp2_port *port = netdev_priv(dev); | |
7481 | ||
7482 | mvpp2_prs_vid_entry_remove(port, vid); | |
7483 | return 0; | |
7484 | } | |
7485 | ||
7486 | static int mvpp2_set_features(struct net_device *dev, | |
7487 | netdev_features_t features) | |
7488 | { | |
7489 | netdev_features_t changed = dev->features ^ features; | |
7490 | struct mvpp2_port *port = netdev_priv(dev); | |
7491 | ||
7492 | if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { | |
7493 | if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { | |
7494 | mvpp2_prs_vid_enable_filtering(port); | |
7495 | } else { | |
7496 | /* Invalidate all registered VID filters for this | |
7497 | * port | |
7498 | */ | |
7499 | mvpp2_prs_vid_remove_all(port); | |
7500 | ||
7501 | mvpp2_prs_vid_disable_filtering(port); | |
7502 | } | |
7503 | } | |
7504 | ||
7505 | return 0; | |
7506 | } | |
7507 | ||
3f518509 MW |
7508 | /* Ethtool methods */ |
7509 | ||
4bb04326 AT |
7510 | static int mvpp2_ethtool_nway_reset(struct net_device *dev) |
7511 | { | |
7512 | struct mvpp2_port *port = netdev_priv(dev); | |
7513 | ||
7514 | if (!port->phylink) | |
7515 | return -ENOTSUPP; | |
7516 | ||
7517 | return phylink_ethtool_nway_reset(port->phylink); | |
7518 | } | |
7519 | ||
3f518509 MW |
7520 | /* Set interrupt coalescing for ethtools */ |
7521 | static int mvpp2_ethtool_set_coalesce(struct net_device *dev, | |
7522 | struct ethtool_coalesce *c) | |
7523 | { | |
7524 | struct mvpp2_port *port = netdev_priv(dev); | |
7525 | int queue; | |
7526 | ||
09f83975 | 7527 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7528 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
7529 | ||
7530 | rxq->time_coal = c->rx_coalesce_usecs; | |
7531 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
d63f9e41 TP |
7532 | mvpp2_rx_pkts_coal_set(port, rxq); |
7533 | mvpp2_rx_time_coal_set(port, rxq); | |
3f518509 MW |
7534 | } |
7535 | ||
213f428f TP |
7536 | if (port->has_tx_irqs) { |
7537 | port->tx_time_coal = c->tx_coalesce_usecs; | |
7538 | mvpp2_tx_time_coal_set(port); | |
7539 | } | |
7540 | ||
09f83975 | 7541 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7542 | struct mvpp2_tx_queue *txq = port->txqs[queue]; |
7543 | ||
7544 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
213f428f TP |
7545 | |
7546 | if (port->has_tx_irqs) | |
7547 | mvpp2_tx_pkts_coal_set(port, txq); | |
3f518509 MW |
7548 | } |
7549 | ||
3f518509 MW |
7550 | return 0; |
7551 | } | |
7552 | ||
7553 | /* get coalescing for ethtools */ | |
7554 | static int mvpp2_ethtool_get_coalesce(struct net_device *dev, | |
7555 | struct ethtool_coalesce *c) | |
7556 | { | |
7557 | struct mvpp2_port *port = netdev_priv(dev); | |
7558 | ||
385c284f AT |
7559 | c->rx_coalesce_usecs = port->rxqs[0]->time_coal; |
7560 | c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; | |
7561 | c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; | |
24b28ccb | 7562 | c->tx_coalesce_usecs = port->tx_time_coal; |
3f518509 MW |
7563 | return 0; |
7564 | } | |
7565 | ||
7566 | static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, | |
7567 | struct ethtool_drvinfo *drvinfo) | |
7568 | { | |
7569 | strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, | |
7570 | sizeof(drvinfo->driver)); | |
7571 | strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, | |
7572 | sizeof(drvinfo->version)); | |
7573 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
7574 | sizeof(drvinfo->bus_info)); | |
7575 | } | |
7576 | ||
7577 | static void mvpp2_ethtool_get_ringparam(struct net_device *dev, | |
7578 | struct ethtool_ringparam *ring) | |
7579 | { | |
7580 | struct mvpp2_port *port = netdev_priv(dev); | |
7581 | ||
7cf87e4a YM |
7582 | ring->rx_max_pending = MVPP2_MAX_RXD_MAX; |
7583 | ring->tx_max_pending = MVPP2_MAX_TXD_MAX; | |
3f518509 MW |
7584 | ring->rx_pending = port->rx_ring_size; |
7585 | ring->tx_pending = port->tx_ring_size; | |
7586 | } | |
7587 | ||
7588 | static int mvpp2_ethtool_set_ringparam(struct net_device *dev, | |
7589 | struct ethtool_ringparam *ring) | |
7590 | { | |
7591 | struct mvpp2_port *port = netdev_priv(dev); | |
7592 | u16 prev_rx_ring_size = port->rx_ring_size; | |
7593 | u16 prev_tx_ring_size = port->tx_ring_size; | |
7594 | int err; | |
7595 | ||
7596 | err = mvpp2_check_ringparam_valid(dev, ring); | |
7597 | if (err) | |
7598 | return err; | |
7599 | ||
7600 | if (!netif_running(dev)) { | |
7601 | port->rx_ring_size = ring->rx_pending; | |
7602 | port->tx_ring_size = ring->tx_pending; | |
7603 | return 0; | |
7604 | } | |
7605 | ||
7606 | /* The interface is running, so we have to force a | |
7607 | * reallocation of the queues | |
7608 | */ | |
7609 | mvpp2_stop_dev(port); | |
7610 | mvpp2_cleanup_rxqs(port); | |
7611 | mvpp2_cleanup_txqs(port); | |
7612 | ||
7613 | port->rx_ring_size = ring->rx_pending; | |
7614 | port->tx_ring_size = ring->tx_pending; | |
7615 | ||
7616 | err = mvpp2_setup_rxqs(port); | |
7617 | if (err) { | |
7618 | /* Reallocate Rx queues with the original ring size */ | |
7619 | port->rx_ring_size = prev_rx_ring_size; | |
7620 | ring->rx_pending = prev_rx_ring_size; | |
7621 | err = mvpp2_setup_rxqs(port); | |
7622 | if (err) | |
7623 | goto err_out; | |
7624 | } | |
7625 | err = mvpp2_setup_txqs(port); | |
7626 | if (err) { | |
7627 | /* Reallocate Tx queues with the original ring size */ | |
7628 | port->tx_ring_size = prev_tx_ring_size; | |
7629 | ring->tx_pending = prev_tx_ring_size; | |
7630 | err = mvpp2_setup_txqs(port); | |
7631 | if (err) | |
7632 | goto err_clean_rxqs; | |
7633 | } | |
7634 | ||
7635 | mvpp2_start_dev(port); | |
7636 | mvpp2_egress_enable(port); | |
7637 | mvpp2_ingress_enable(port); | |
7638 | ||
7639 | return 0; | |
7640 | ||
7641 | err_clean_rxqs: | |
7642 | mvpp2_cleanup_rxqs(port); | |
7643 | err_out: | |
dfd4240a | 7644 | netdev_err(dev, "failed to change ring parameters"); |
3f518509 MW |
7645 | return err; |
7646 | } | |
7647 | ||
4bb04326 AT |
7648 | static void mvpp2_ethtool_get_pause_param(struct net_device *dev, |
7649 | struct ethtool_pauseparam *pause) | |
7650 | { | |
7651 | struct mvpp2_port *port = netdev_priv(dev); | |
7652 | ||
7653 | if (!port->phylink) | |
7654 | return; | |
7655 | ||
7656 | phylink_ethtool_get_pauseparam(port->phylink, pause); | |
7657 | } | |
7658 | ||
7659 | static int mvpp2_ethtool_set_pause_param(struct net_device *dev, | |
7660 | struct ethtool_pauseparam *pause) | |
7661 | { | |
7662 | struct mvpp2_port *port = netdev_priv(dev); | |
7663 | ||
7664 | if (!port->phylink) | |
7665 | return -ENOTSUPP; | |
7666 | ||
7667 | return phylink_ethtool_set_pauseparam(port->phylink, pause); | |
7668 | } | |
7669 | ||
7670 | static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, | |
7671 | struct ethtool_link_ksettings *cmd) | |
7672 | { | |
7673 | struct mvpp2_port *port = netdev_priv(dev); | |
7674 | ||
7675 | if (!port->phylink) | |
7676 | return -ENOTSUPP; | |
7677 | ||
7678 | return phylink_ethtool_ksettings_get(port->phylink, cmd); | |
7679 | } | |
7680 | ||
7681 | static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, | |
7682 | const struct ethtool_link_ksettings *cmd) | |
7683 | { | |
7684 | struct mvpp2_port *port = netdev_priv(dev); | |
7685 | ||
7686 | if (!port->phylink) | |
7687 | return -ENOTSUPP; | |
7688 | ||
7689 | return phylink_ethtool_ksettings_set(port->phylink, cmd); | |
7690 | } | |
7691 | ||
3f518509 MW |
7692 | /* Device ops */ |
7693 | ||
7694 | static const struct net_device_ops mvpp2_netdev_ops = { | |
7695 | .ndo_open = mvpp2_open, | |
7696 | .ndo_stop = mvpp2_stop, | |
7697 | .ndo_start_xmit = mvpp2_tx, | |
7698 | .ndo_set_rx_mode = mvpp2_set_rx_mode, | |
7699 | .ndo_set_mac_address = mvpp2_set_mac_address, | |
7700 | .ndo_change_mtu = mvpp2_change_mtu, | |
7701 | .ndo_get_stats64 = mvpp2_get_stats64, | |
bd695a5f | 7702 | .ndo_do_ioctl = mvpp2_ioctl, |
56beda3d MC |
7703 | .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, |
7704 | .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, | |
7705 | .ndo_set_features = mvpp2_set_features, | |
3f518509 MW |
7706 | }; |
7707 | ||
7708 | static const struct ethtool_ops mvpp2_eth_tool_ops = { | |
4bb04326 | 7709 | .nway_reset = mvpp2_ethtool_nway_reset, |
dcd3e73a AT |
7710 | .get_link = ethtool_op_get_link, |
7711 | .set_coalesce = mvpp2_ethtool_set_coalesce, | |
7712 | .get_coalesce = mvpp2_ethtool_get_coalesce, | |
7713 | .get_drvinfo = mvpp2_ethtool_get_drvinfo, | |
7714 | .get_ringparam = mvpp2_ethtool_get_ringparam, | |
7715 | .set_ringparam = mvpp2_ethtool_set_ringparam, | |
7716 | .get_strings = mvpp2_ethtool_get_strings, | |
7717 | .get_ethtool_stats = mvpp2_ethtool_get_stats, | |
7718 | .get_sset_count = mvpp2_ethtool_get_sset_count, | |
4bb04326 AT |
7719 | .get_pauseparam = mvpp2_ethtool_get_pause_param, |
7720 | .set_pauseparam = mvpp2_ethtool_set_pause_param, | |
7721 | .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, | |
7722 | .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, | |
3f518509 MW |
7723 | }; |
7724 | ||
213f428f TP |
7725 | /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that |
7726 | * had a single IRQ defined per-port. | |
7727 | */ | |
7728 | static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, | |
7729 | struct device_node *port_node) | |
591f4cfa TP |
7730 | { |
7731 | struct mvpp2_queue_vector *v = &port->qvecs[0]; | |
7732 | ||
7733 | v->first_rxq = 0; | |
7734 | v->nrxqs = port->nrxqs; | |
7735 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
7736 | v->sw_thread_id = 0; | |
7737 | v->sw_thread_mask = *cpumask_bits(cpu_online_mask); | |
7738 | v->port = port; | |
7739 | v->irq = irq_of_parse_and_map(port_node, 0); | |
7740 | if (v->irq <= 0) | |
7741 | return -EINVAL; | |
7742 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
7743 | NAPI_POLL_WEIGHT); | |
7744 | ||
7745 | port->nqvecs = 1; | |
7746 | ||
7747 | return 0; | |
7748 | } | |
7749 | ||
213f428f TP |
7750 | static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, |
7751 | struct device_node *port_node) | |
7752 | { | |
7753 | struct mvpp2_queue_vector *v; | |
7754 | int i, ret; | |
7755 | ||
7756 | port->nqvecs = num_possible_cpus(); | |
7757 | if (queue_mode == MVPP2_QDIST_SINGLE_MODE) | |
7758 | port->nqvecs += 1; | |
7759 | ||
7760 | for (i = 0; i < port->nqvecs; i++) { | |
7761 | char irqname[16]; | |
7762 | ||
7763 | v = port->qvecs + i; | |
7764 | ||
7765 | v->port = port; | |
7766 | v->type = MVPP2_QUEUE_VECTOR_PRIVATE; | |
7767 | v->sw_thread_id = i; | |
7768 | v->sw_thread_mask = BIT(i); | |
7769 | ||
7770 | snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); | |
7771 | ||
7772 | if (queue_mode == MVPP2_QDIST_MULTI_MODE) { | |
7773 | v->first_rxq = i * MVPP2_DEFAULT_RXQ; | |
7774 | v->nrxqs = MVPP2_DEFAULT_RXQ; | |
7775 | } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && | |
7776 | i == (port->nqvecs - 1)) { | |
7777 | v->first_rxq = 0; | |
7778 | v->nrxqs = port->nrxqs; | |
7779 | v->type = MVPP2_QUEUE_VECTOR_SHARED; | |
7780 | strncpy(irqname, "rx-shared", sizeof(irqname)); | |
7781 | } | |
7782 | ||
a75edc7c MW |
7783 | if (port_node) |
7784 | v->irq = of_irq_get_byname(port_node, irqname); | |
7785 | else | |
7786 | v->irq = fwnode_irq_get(port->fwnode, i); | |
213f428f TP |
7787 | if (v->irq <= 0) { |
7788 | ret = -EINVAL; | |
7789 | goto err; | |
7790 | } | |
7791 | ||
7792 | netif_napi_add(port->dev, &v->napi, mvpp2_poll, | |
7793 | NAPI_POLL_WEIGHT); | |
7794 | } | |
7795 | ||
7796 | return 0; | |
7797 | ||
7798 | err: | |
7799 | for (i = 0; i < port->nqvecs; i++) | |
7800 | irq_dispose_mapping(port->qvecs[i].irq); | |
7801 | return ret; | |
7802 | } | |
7803 | ||
7804 | static int mvpp2_queue_vectors_init(struct mvpp2_port *port, | |
7805 | struct device_node *port_node) | |
7806 | { | |
7807 | if (port->has_tx_irqs) | |
7808 | return mvpp2_multi_queue_vectors_init(port, port_node); | |
7809 | else | |
7810 | return mvpp2_simple_queue_vectors_init(port, port_node); | |
7811 | } | |
7812 | ||
591f4cfa TP |
7813 | static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) |
7814 | { | |
7815 | int i; | |
7816 | ||
7817 | for (i = 0; i < port->nqvecs; i++) | |
7818 | irq_dispose_mapping(port->qvecs[i].irq); | |
7819 | } | |
7820 | ||
7821 | /* Configure Rx queue group interrupt for this port */ | |
7822 | static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) | |
7823 | { | |
7824 | struct mvpp2 *priv = port->priv; | |
7825 | u32 val; | |
7826 | int i; | |
7827 | ||
7828 | if (priv->hw_version == MVPP21) { | |
7829 | mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), | |
7830 | port->nrxqs); | |
7831 | return; | |
7832 | } | |
7833 | ||
7834 | /* Handle the more complicated PPv2.2 case */ | |
7835 | for (i = 0; i < port->nqvecs; i++) { | |
7836 | struct mvpp2_queue_vector *qv = port->qvecs + i; | |
7837 | ||
7838 | if (!qv->nrxqs) | |
7839 | continue; | |
7840 | ||
7841 | val = qv->sw_thread_id; | |
7842 | val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; | |
7843 | mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); | |
7844 | ||
7845 | val = qv->first_rxq; | |
7846 | val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; | |
7847 | mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); | |
7848 | } | |
7849 | } | |
7850 | ||
3f518509 MW |
7851 | /* Initialize port HW */ |
7852 | static int mvpp2_port_init(struct mvpp2_port *port) | |
7853 | { | |
7854 | struct device *dev = port->dev->dev.parent; | |
7855 | struct mvpp2 *priv = port->priv; | |
7856 | struct mvpp2_txq_pcpu *txq_pcpu; | |
7857 | int queue, cpu, err; | |
7858 | ||
09f83975 TP |
7859 | /* Checks for hardware constraints */ |
7860 | if (port->first_rxq + port->nrxqs > | |
59b9a31e | 7861 | MVPP2_MAX_PORTS * priv->max_port_rxqs) |
3f518509 MW |
7862 | return -EINVAL; |
7863 | ||
09f83975 TP |
7864 | if (port->nrxqs % 4 || (port->nrxqs > priv->max_port_rxqs) || |
7865 | (port->ntxqs > MVPP2_MAX_TXQ)) | |
7866 | return -EINVAL; | |
7867 | ||
3f518509 MW |
7868 | /* Disable port */ |
7869 | mvpp2_egress_disable(port); | |
7870 | mvpp2_port_disable(port); | |
7871 | ||
213f428f TP |
7872 | port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; |
7873 | ||
09f83975 | 7874 | port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), |
3f518509 MW |
7875 | GFP_KERNEL); |
7876 | if (!port->txqs) | |
7877 | return -ENOMEM; | |
7878 | ||
7879 | /* Associate physical Tx queues to this port and initialize. | |
7880 | * The mapping is predefined. | |
7881 | */ | |
09f83975 | 7882 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7883 | int queue_phy_id = mvpp2_txq_phys(port->id, queue); |
7884 | struct mvpp2_tx_queue *txq; | |
7885 | ||
7886 | txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); | |
177c8d1c CJ |
7887 | if (!txq) { |
7888 | err = -ENOMEM; | |
7889 | goto err_free_percpu; | |
7890 | } | |
3f518509 MW |
7891 | |
7892 | txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); | |
7893 | if (!txq->pcpu) { | |
7894 | err = -ENOMEM; | |
7895 | goto err_free_percpu; | |
7896 | } | |
7897 | ||
7898 | txq->id = queue_phy_id; | |
7899 | txq->log_id = queue; | |
7900 | txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; | |
7901 | for_each_present_cpu(cpu) { | |
7902 | txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); | |
7903 | txq_pcpu->cpu = cpu; | |
7904 | } | |
7905 | ||
7906 | port->txqs[queue] = txq; | |
7907 | } | |
7908 | ||
09f83975 | 7909 | port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), |
3f518509 MW |
7910 | GFP_KERNEL); |
7911 | if (!port->rxqs) { | |
7912 | err = -ENOMEM; | |
7913 | goto err_free_percpu; | |
7914 | } | |
7915 | ||
7916 | /* Allocate and initialize Rx queue for this port */ | |
09f83975 | 7917 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7918 | struct mvpp2_rx_queue *rxq; |
7919 | ||
7920 | /* Map physical Rx queue to port's logical Rx queue */ | |
7921 | rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); | |
d82b0c21 JZ |
7922 | if (!rxq) { |
7923 | err = -ENOMEM; | |
3f518509 | 7924 | goto err_free_percpu; |
d82b0c21 | 7925 | } |
3f518509 MW |
7926 | /* Map this Rx queue to a physical queue */ |
7927 | rxq->id = port->first_rxq + queue; | |
7928 | rxq->port = port->id; | |
7929 | rxq->logic_rxq = queue; | |
7930 | ||
7931 | port->rxqs[queue] = rxq; | |
7932 | } | |
7933 | ||
591f4cfa | 7934 | mvpp2_rx_irqs_setup(port); |
3f518509 MW |
7935 | |
7936 | /* Create Rx descriptor rings */ | |
09f83975 | 7937 | for (queue = 0; queue < port->nrxqs; queue++) { |
3f518509 MW |
7938 | struct mvpp2_rx_queue *rxq = port->rxqs[queue]; |
7939 | ||
7940 | rxq->size = port->rx_ring_size; | |
7941 | rxq->pkts_coal = MVPP2_RX_COAL_PKTS; | |
7942 | rxq->time_coal = MVPP2_RX_COAL_USEC; | |
7943 | } | |
7944 | ||
7945 | mvpp2_ingress_disable(port); | |
7946 | ||
7947 | /* Port default configuration */ | |
7948 | mvpp2_defaults_set(port); | |
7949 | ||
7950 | /* Port's classifier configuration */ | |
7951 | mvpp2_cls_oversize_rxq_set(port); | |
7952 | mvpp2_cls_port_config(port); | |
7953 | ||
7954 | /* Provide an initial Rx packet size */ | |
7955 | port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); | |
7956 | ||
7957 | /* Initialize pools for swf */ | |
7958 | err = mvpp2_swf_bm_pool_init(port); | |
7959 | if (err) | |
7960 | goto err_free_percpu; | |
7961 | ||
7962 | return 0; | |
7963 | ||
7964 | err_free_percpu: | |
09f83975 | 7965 | for (queue = 0; queue < port->ntxqs; queue++) { |
3f518509 MW |
7966 | if (!port->txqs[queue]) |
7967 | continue; | |
7968 | free_percpu(port->txqs[queue]->pcpu); | |
7969 | } | |
7970 | return err; | |
7971 | } | |
7972 | ||
213f428f TP |
7973 | /* Checks if the port DT description has the TX interrupts |
7974 | * described. On PPv2.1, there are no such interrupts. On PPv2.2, | |
7975 | * there are available, but we need to keep support for old DTs. | |
7976 | */ | |
7977 | static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv, | |
7978 | struct device_node *port_node) | |
7979 | { | |
7980 | char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", | |
7981 | "tx-cpu2", "tx-cpu3" }; | |
7982 | int ret, i; | |
7983 | ||
7984 | if (priv->hw_version == MVPP21) | |
7985 | return false; | |
7986 | ||
7987 | for (i = 0; i < 5; i++) { | |
7988 | ret = of_property_match_string(port_node, "interrupt-names", | |
7989 | irqs[i]); | |
7990 | if (ret < 0) | |
7991 | return false; | |
7992 | } | |
7993 | ||
7994 | return true; | |
7995 | } | |
7996 | ||
3ba8c81e | 7997 | static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, |
24812221 | 7998 | struct fwnode_handle *fwnode, |
3ba8c81e AT |
7999 | char **mac_from) |
8000 | { | |
8001 | struct mvpp2_port *port = netdev_priv(dev); | |
8002 | char hw_mac_addr[ETH_ALEN] = {0}; | |
24812221 | 8003 | char fw_mac_addr[ETH_ALEN]; |
3ba8c81e | 8004 | |
24812221 MW |
8005 | if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { |
8006 | *mac_from = "firmware node"; | |
8007 | ether_addr_copy(dev->dev_addr, fw_mac_addr); | |
688cbaf2 AT |
8008 | return; |
8009 | } | |
d2a6e48e | 8010 | |
688cbaf2 AT |
8011 | if (priv->hw_version == MVPP21) { |
8012 | mvpp21_get_mac_address(port, hw_mac_addr); | |
8013 | if (is_valid_ether_addr(hw_mac_addr)) { | |
8014 | *mac_from = "hardware"; | |
8015 | ether_addr_copy(dev->dev_addr, hw_mac_addr); | |
8016 | return; | |
8017 | } | |
3ba8c81e | 8018 | } |
688cbaf2 AT |
8019 | |
8020 | *mac_from = "random"; | |
8021 | eth_hw_addr_random(dev); | |
3ba8c81e AT |
8022 | } |
8023 | ||
4bb04326 AT |
8024 | static void mvpp2_phylink_validate(struct net_device *dev, |
8025 | unsigned long *supported, | |
8026 | struct phylink_link_state *state) | |
8027 | { | |
8028 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; | |
8029 | ||
8030 | phylink_set(mask, Autoneg); | |
8031 | phylink_set_port_modes(mask); | |
8032 | phylink_set(mask, Pause); | |
8033 | phylink_set(mask, Asym_Pause); | |
8034 | ||
8035 | phylink_set(mask, 10baseT_Half); | |
8036 | phylink_set(mask, 10baseT_Full); | |
8037 | phylink_set(mask, 100baseT_Half); | |
8038 | phylink_set(mask, 100baseT_Full); | |
8039 | phylink_set(mask, 1000baseT_Full); | |
8040 | phylink_set(mask, 10000baseT_Full); | |
8041 | ||
8042 | if (state->interface == PHY_INTERFACE_MODE_10GKR) { | |
8043 | phylink_set(mask, 10000baseCR_Full); | |
8044 | phylink_set(mask, 10000baseSR_Full); | |
8045 | phylink_set(mask, 10000baseLR_Full); | |
8046 | phylink_set(mask, 10000baseLRM_Full); | |
8047 | phylink_set(mask, 10000baseER_Full); | |
8048 | phylink_set(mask, 10000baseKR_Full); | |
8049 | } | |
8050 | ||
8051 | bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
8052 | bitmap_and(state->advertising, state->advertising, mask, | |
8053 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
8054 | } | |
8055 | ||
8056 | static void mvpp22_xlg_link_state(struct mvpp2_port *port, | |
8057 | struct phylink_link_state *state) | |
8058 | { | |
8059 | u32 val; | |
8060 | ||
8061 | state->speed = SPEED_10000; | |
8062 | state->duplex = 1; | |
8063 | state->an_complete = 1; | |
8064 | ||
8065 | val = readl(port->base + MVPP22_XLG_STATUS); | |
8066 | state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); | |
8067 | ||
8068 | state->pause = 0; | |
8069 | val = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
8070 | if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) | |
8071 | state->pause |= MLO_PAUSE_TX; | |
8072 | if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) | |
8073 | state->pause |= MLO_PAUSE_RX; | |
8074 | } | |
8075 | ||
8076 | static void mvpp2_gmac_link_state(struct mvpp2_port *port, | |
8077 | struct phylink_link_state *state) | |
8078 | { | |
8079 | u32 val; | |
8080 | ||
8081 | val = readl(port->base + MVPP2_GMAC_STATUS0); | |
8082 | ||
8083 | state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); | |
8084 | state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); | |
8085 | state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); | |
8086 | ||
8087 | if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) | |
8088 | state->speed = SPEED_1000; | |
8089 | else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) | |
8090 | state->speed = SPEED_100; | |
8091 | else | |
8092 | state->speed = SPEED_10; | |
8093 | ||
8094 | state->pause = 0; | |
8095 | if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) | |
8096 | state->pause |= MLO_PAUSE_RX; | |
8097 | if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) | |
8098 | state->pause |= MLO_PAUSE_TX; | |
8099 | } | |
8100 | ||
8101 | static int mvpp2_phylink_mac_link_state(struct net_device *dev, | |
8102 | struct phylink_link_state *state) | |
8103 | { | |
8104 | struct mvpp2_port *port = netdev_priv(dev); | |
8105 | ||
8106 | if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { | |
8107 | u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); | |
8108 | mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; | |
8109 | ||
8110 | if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { | |
8111 | mvpp22_xlg_link_state(port, state); | |
8112 | return 1; | |
8113 | } | |
8114 | } | |
8115 | ||
8116 | mvpp2_gmac_link_state(port, state); | |
8117 | return 1; | |
8118 | } | |
8119 | ||
8120 | static void mvpp2_mac_an_restart(struct net_device *dev) | |
8121 | { | |
8122 | struct mvpp2_port *port = netdev_priv(dev); | |
8123 | u32 val; | |
8124 | ||
8125 | if (port->phy_interface != PHY_INTERFACE_MODE_SGMII) | |
8126 | return; | |
8127 | ||
8128 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8129 | /* The RESTART_AN bit is cleared by the h/w after restarting the AN | |
8130 | * process. | |
8131 | */ | |
8132 | val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG; | |
8133 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8134 | } | |
8135 | ||
8136 | static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, | |
8137 | const struct phylink_link_state *state) | |
8138 | { | |
8139 | u32 ctrl0, ctrl4; | |
8140 | ||
8141 | ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); | |
8142 | ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); | |
8143 | ||
8144 | if (state->pause & MLO_PAUSE_TX) | |
8145 | ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; | |
8146 | if (state->pause & MLO_PAUSE_RX) | |
8147 | ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; | |
8148 | ||
8149 | ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; | |
8150 | ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | | |
8151 | MVPP22_XLG_CTRL4_EN_IDLE_CHECK; | |
8152 | ||
8153 | writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); | |
8154 | writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); | |
8155 | } | |
8156 | ||
8157 | static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, | |
8158 | const struct phylink_link_state *state) | |
8159 | { | |
8160 | u32 an, ctrl0, ctrl2, ctrl4; | |
8161 | ||
8162 | an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8163 | ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); | |
8164 | ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); | |
8165 | ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); | |
8166 | ||
8167 | /* Force link down */ | |
8168 | an &= ~MVPP2_GMAC_FORCE_LINK_PASS; | |
8169 | an |= MVPP2_GMAC_FORCE_LINK_DOWN; | |
8170 | writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8171 | ||
8172 | /* Set the GMAC in a reset state */ | |
8173 | ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; | |
8174 | writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); | |
8175 | ||
8176 | an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | | |
8177 | MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | | |
8178 | MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | | |
8179 | MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | | |
8180 | MVPP2_GMAC_FORCE_LINK_DOWN); | |
8181 | ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; | |
8182 | ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK); | |
8183 | ||
8184 | if (!phy_interface_mode_is_rgmii(state->interface)) | |
8185 | an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG; | |
8186 | ||
8187 | if (state->duplex) | |
8188 | an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; | |
8189 | if (phylink_test(state->advertising, Pause)) | |
8190 | an |= MVPP2_GMAC_FC_ADV_EN; | |
8191 | if (phylink_test(state->advertising, Asym_Pause)) | |
8192 | an |= MVPP2_GMAC_FC_ADV_ASM_EN; | |
8193 | ||
8194 | if (state->interface == PHY_INTERFACE_MODE_SGMII) { | |
8195 | an |= MVPP2_GMAC_IN_BAND_AUTONEG; | |
8196 | ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; | |
8197 | ||
8198 | ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL | | |
8199 | MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); | |
8200 | ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | | |
8201 | MVPP22_CTRL4_DP_CLK_SEL | | |
8202 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
8203 | ||
8204 | if (state->pause & MLO_PAUSE_TX) | |
8205 | ctrl4 |= MVPP22_CTRL4_TX_FC_EN; | |
8206 | if (state->pause & MLO_PAUSE_RX) | |
8207 | ctrl4 |= MVPP22_CTRL4_RX_FC_EN; | |
8208 | } else if (phy_interface_mode_is_rgmii(state->interface)) { | |
8209 | an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS; | |
8210 | ||
8211 | if (state->speed == SPEED_1000) | |
8212 | an |= MVPP2_GMAC_CONFIG_GMII_SPEED; | |
8213 | else if (state->speed == SPEED_100) | |
8214 | an |= MVPP2_GMAC_CONFIG_MII_SPEED; | |
8215 | ||
8216 | ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; | |
8217 | ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | | |
8218 | MVPP22_CTRL4_SYNC_BYPASS_DIS | | |
8219 | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; | |
8220 | } | |
8221 | ||
8222 | writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); | |
8223 | writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); | |
8224 | writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); | |
8225 | writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8226 | } | |
8227 | ||
8228 | static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, | |
8229 | const struct phylink_link_state *state) | |
8230 | { | |
8231 | struct mvpp2_port *port = netdev_priv(dev); | |
8232 | ||
8233 | /* Check for invalid configuration */ | |
8234 | if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) { | |
8235 | netdev_err(dev, "Invalid mode on %s\n", dev->name); | |
8236 | return; | |
8237 | } | |
8238 | ||
8239 | netif_tx_stop_all_queues(port->dev); | |
8240 | if (!port->has_phy) | |
8241 | netif_carrier_off(port->dev); | |
8242 | ||
8243 | /* Make sure the port is disabled when reconfiguring the mode */ | |
8244 | mvpp2_port_disable(port); | |
8245 | ||
8246 | if (port->priv->hw_version == MVPP22 && | |
8247 | port->phy_interface != state->interface) { | |
8248 | port->phy_interface = state->interface; | |
8249 | ||
8250 | /* Reconfigure the serdes lanes */ | |
8251 | phy_power_off(port->comphy); | |
8252 | mvpp22_mode_reconfigure(port); | |
8253 | } | |
8254 | ||
8255 | /* mac (re)configuration */ | |
8256 | if (state->interface == PHY_INTERFACE_MODE_10GKR) | |
8257 | mvpp2_xlg_config(port, mode, state); | |
8258 | else if (phy_interface_mode_is_rgmii(state->interface) || | |
8259 | state->interface == PHY_INTERFACE_MODE_SGMII) | |
8260 | mvpp2_gmac_config(port, mode, state); | |
8261 | ||
8262 | if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) | |
8263 | mvpp2_port_loopback_set(port, state); | |
8264 | ||
8265 | /* If the port already was up, make sure it's still in the same state */ | |
8266 | if (state->link || !port->has_phy) { | |
8267 | mvpp2_port_enable(port); | |
8268 | ||
8269 | mvpp2_egress_enable(port); | |
8270 | mvpp2_ingress_enable(port); | |
8271 | if (!port->has_phy) | |
8272 | netif_carrier_on(dev); | |
8273 | netif_tx_wake_all_queues(dev); | |
8274 | } | |
8275 | } | |
8276 | ||
8277 | static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, | |
8278 | phy_interface_t interface, struct phy_device *phy) | |
8279 | { | |
8280 | struct mvpp2_port *port = netdev_priv(dev); | |
8281 | u32 val; | |
8282 | ||
8283 | if (!phylink_autoneg_inband(mode) && | |
8284 | interface != PHY_INTERFACE_MODE_10GKR) { | |
8285 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8286 | val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; | |
8287 | if (phy_interface_mode_is_rgmii(interface)) | |
8288 | val |= MVPP2_GMAC_FORCE_LINK_PASS; | |
8289 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8290 | } | |
8291 | ||
8292 | mvpp2_port_enable(port); | |
8293 | ||
8294 | mvpp2_egress_enable(port); | |
8295 | mvpp2_ingress_enable(port); | |
8296 | netif_tx_wake_all_queues(dev); | |
8297 | } | |
8298 | ||
8299 | static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode, | |
8300 | phy_interface_t interface) | |
8301 | { | |
8302 | struct mvpp2_port *port = netdev_priv(dev); | |
8303 | u32 val; | |
8304 | ||
8305 | if (!phylink_autoneg_inband(mode) && | |
8306 | interface != PHY_INTERFACE_MODE_10GKR) { | |
8307 | val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8308 | val &= ~MVPP2_GMAC_FORCE_LINK_PASS; | |
8309 | val |= MVPP2_GMAC_FORCE_LINK_DOWN; | |
8310 | writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); | |
8311 | } | |
8312 | ||
8313 | netif_tx_stop_all_queues(dev); | |
8314 | mvpp2_egress_disable(port); | |
8315 | mvpp2_ingress_disable(port); | |
8316 | ||
8317 | /* When using link interrupts to notify phylink of a MAC state change, | |
8318 | * we do not want the port to be disabled (we want to receive further | |
8319 | * interrupts, to be notified when the port will have a link later). | |
8320 | */ | |
8321 | if (!port->has_phy) | |
8322 | return; | |
8323 | ||
8324 | mvpp2_port_disable(port); | |
8325 | } | |
8326 | ||
8327 | static const struct phylink_mac_ops mvpp2_phylink_ops = { | |
8328 | .validate = mvpp2_phylink_validate, | |
8329 | .mac_link_state = mvpp2_phylink_mac_link_state, | |
8330 | .mac_an_restart = mvpp2_mac_an_restart, | |
8331 | .mac_config = mvpp2_mac_config, | |
8332 | .mac_link_up = mvpp2_mac_link_up, | |
8333 | .mac_link_down = mvpp2_mac_link_down, | |
8334 | }; | |
8335 | ||
3f518509 MW |
8336 | /* Ports initialization */ |
8337 | static int mvpp2_port_probe(struct platform_device *pdev, | |
24812221 | 8338 | struct fwnode_handle *port_fwnode, |
bf147153 | 8339 | struct mvpp2 *priv) |
3f518509 | 8340 | { |
a75edc7c | 8341 | struct phy *comphy = NULL; |
3f518509 | 8342 | struct mvpp2_port *port; |
edc660fa | 8343 | struct mvpp2_port_pcpu *port_pcpu; |
24812221 | 8344 | struct device_node *port_node = to_of_node(port_fwnode); |
3f518509 MW |
8345 | struct net_device *dev; |
8346 | struct resource *res; | |
4bb04326 | 8347 | struct phylink *phylink; |
3ba8c81e | 8348 | char *mac_from = ""; |
09f83975 | 8349 | unsigned int ntxqs, nrxqs; |
213f428f | 8350 | bool has_tx_irqs; |
3f518509 MW |
8351 | u32 id; |
8352 | int features; | |
8353 | int phy_mode; | |
edc660fa | 8354 | int err, i, cpu; |
3f518509 | 8355 | |
a75edc7c MW |
8356 | if (port_node) { |
8357 | has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); | |
8358 | } else { | |
8359 | has_tx_irqs = true; | |
8360 | queue_mode = MVPP2_QDIST_MULTI_MODE; | |
8361 | } | |
213f428f TP |
8362 | |
8363 | if (!has_tx_irqs) | |
8364 | queue_mode = MVPP2_QDIST_SINGLE_MODE; | |
8365 | ||
09f83975 | 8366 | ntxqs = MVPP2_MAX_TXQ; |
213f428f TP |
8367 | if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) |
8368 | nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); | |
8369 | else | |
8370 | nrxqs = MVPP2_DEFAULT_RXQ; | |
09f83975 TP |
8371 | |
8372 | dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); | |
3f518509 MW |
8373 | if (!dev) |
8374 | return -ENOMEM; | |
8375 | ||
24812221 | 8376 | phy_mode = fwnode_get_phy_mode(port_fwnode); |
3f518509 MW |
8377 | if (phy_mode < 0) { |
8378 | dev_err(&pdev->dev, "incorrect phy mode\n"); | |
8379 | err = phy_mode; | |
8380 | goto err_free_netdev; | |
8381 | } | |
8382 | ||
a75edc7c MW |
8383 | if (port_node) { |
8384 | comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); | |
8385 | if (IS_ERR(comphy)) { | |
8386 | if (PTR_ERR(comphy) == -EPROBE_DEFER) { | |
8387 | err = -EPROBE_DEFER; | |
8388 | goto err_free_netdev; | |
8389 | } | |
8390 | comphy = NULL; | |
542897d9 | 8391 | } |
542897d9 AT |
8392 | } |
8393 | ||
24812221 | 8394 | if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { |
3f518509 MW |
8395 | err = -EINVAL; |
8396 | dev_err(&pdev->dev, "missing port-id value\n"); | |
8397 | goto err_free_netdev; | |
8398 | } | |
8399 | ||
7cf87e4a | 8400 | dev->tx_queue_len = MVPP2_MAX_TXD_MAX; |
3f518509 MW |
8401 | dev->watchdog_timeo = 5 * HZ; |
8402 | dev->netdev_ops = &mvpp2_netdev_ops; | |
8403 | dev->ethtool_ops = &mvpp2_eth_tool_ops; | |
8404 | ||
8405 | port = netdev_priv(dev); | |
591f4cfa | 8406 | port->dev = dev; |
a75edc7c | 8407 | port->fwnode = port_fwnode; |
4bb04326 | 8408 | port->has_phy = !!of_find_property(port_node, "phy", NULL); |
09f83975 TP |
8409 | port->ntxqs = ntxqs; |
8410 | port->nrxqs = nrxqs; | |
213f428f TP |
8411 | port->priv = priv; |
8412 | port->has_tx_irqs = has_tx_irqs; | |
3f518509 | 8413 | |
591f4cfa TP |
8414 | err = mvpp2_queue_vectors_init(port, port_node); |
8415 | if (err) | |
3f518509 | 8416 | goto err_free_netdev; |
3f518509 | 8417 | |
a75edc7c MW |
8418 | if (port_node) |
8419 | port->link_irq = of_irq_get_byname(port_node, "link"); | |
8420 | else | |
8421 | port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); | |
fd3651b2 AT |
8422 | if (port->link_irq == -EPROBE_DEFER) { |
8423 | err = -EPROBE_DEFER; | |
8424 | goto err_deinit_qvecs; | |
8425 | } | |
8426 | if (port->link_irq <= 0) | |
8427 | /* the link irq is optional */ | |
8428 | port->link_irq = 0; | |
8429 | ||
24812221 | 8430 | if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) |
3f518509 MW |
8431 | port->flags |= MVPP2_F_LOOPBACK; |
8432 | ||
3f518509 | 8433 | port->id = id; |
59b9a31e | 8434 | if (priv->hw_version == MVPP21) |
09f83975 | 8435 | port->first_rxq = port->id * port->nrxqs; |
59b9a31e TP |
8436 | else |
8437 | port->first_rxq = port->id * priv->max_port_rxqs; | |
8438 | ||
4bb04326 | 8439 | port->of_node = port_node; |
3f518509 | 8440 | port->phy_interface = phy_mode; |
542897d9 | 8441 | port->comphy = comphy; |
3f518509 | 8442 | |
a786841d TP |
8443 | if (priv->hw_version == MVPP21) { |
8444 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); | |
8445 | port->base = devm_ioremap_resource(&pdev->dev, res); | |
8446 | if (IS_ERR(port->base)) { | |
8447 | err = PTR_ERR(port->base); | |
fd3651b2 | 8448 | goto err_free_irq; |
a786841d | 8449 | } |
118d6298 MR |
8450 | |
8451 | port->stats_base = port->priv->lms_base + | |
8452 | MVPP21_MIB_COUNTERS_OFFSET + | |
8453 | port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; | |
a786841d | 8454 | } else { |
24812221 MW |
8455 | if (fwnode_property_read_u32(port_fwnode, "gop-port-id", |
8456 | &port->gop_id)) { | |
a786841d TP |
8457 | err = -EINVAL; |
8458 | dev_err(&pdev->dev, "missing gop-port-id value\n"); | |
591f4cfa | 8459 | goto err_deinit_qvecs; |
a786841d TP |
8460 | } |
8461 | ||
8462 | port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); | |
118d6298 MR |
8463 | port->stats_base = port->priv->iface_base + |
8464 | MVPP22_MIB_COUNTERS_OFFSET + | |
8465 | port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; | |
3f518509 MW |
8466 | } |
8467 | ||
118d6298 | 8468 | /* Alloc per-cpu and ethtool stats */ |
3f518509 MW |
8469 | port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); |
8470 | if (!port->stats) { | |
8471 | err = -ENOMEM; | |
fd3651b2 | 8472 | goto err_free_irq; |
3f518509 MW |
8473 | } |
8474 | ||
118d6298 MR |
8475 | port->ethtool_stats = devm_kcalloc(&pdev->dev, |
8476 | ARRAY_SIZE(mvpp2_ethtool_regs), | |
8477 | sizeof(u64), GFP_KERNEL); | |
8478 | if (!port->ethtool_stats) { | |
8479 | err = -ENOMEM; | |
8480 | goto err_free_stats; | |
8481 | } | |
8482 | ||
e5c500eb MR |
8483 | mutex_init(&port->gather_stats_lock); |
8484 | INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); | |
8485 | ||
24812221 | 8486 | mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); |
3f518509 | 8487 | |
7cf87e4a YM |
8488 | port->tx_ring_size = MVPP2_MAX_TXD_DFLT; |
8489 | port->rx_ring_size = MVPP2_MAX_RXD_DFLT; | |
3f518509 MW |
8490 | SET_NETDEV_DEV(dev, &pdev->dev); |
8491 | ||
8492 | err = mvpp2_port_init(port); | |
8493 | if (err < 0) { | |
8494 | dev_err(&pdev->dev, "failed to init port %d\n", id); | |
8495 | goto err_free_stats; | |
8496 | } | |
26975821 | 8497 | |
26975821 TP |
8498 | mvpp2_port_periodic_xon_disable(port); |
8499 | ||
26975821 | 8500 | mvpp2_port_reset(port); |
3f518509 | 8501 | |
edc660fa MW |
8502 | port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); |
8503 | if (!port->pcpu) { | |
8504 | err = -ENOMEM; | |
8505 | goto err_free_txq_pcpu; | |
8506 | } | |
8507 | ||
213f428f TP |
8508 | if (!port->has_tx_irqs) { |
8509 | for_each_present_cpu(cpu) { | |
8510 | port_pcpu = per_cpu_ptr(port->pcpu, cpu); | |
edc660fa | 8511 | |
213f428f TP |
8512 | hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, |
8513 | HRTIMER_MODE_REL_PINNED); | |
8514 | port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; | |
8515 | port_pcpu->timer_scheduled = false; | |
edc660fa | 8516 | |
213f428f TP |
8517 | tasklet_init(&port_pcpu->tx_done_tasklet, |
8518 | mvpp2_tx_proc_cb, | |
8519 | (unsigned long)dev); | |
8520 | } | |
edc660fa MW |
8521 | } |
8522 | ||
381c5671 AT |
8523 | features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
8524 | NETIF_F_TSO; | |
3f518509 | 8525 | dev->features = features | NETIF_F_RXCSUM; |
56beda3d MC |
8526 | dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | |
8527 | NETIF_F_HW_VLAN_CTAG_FILTER; | |
576193f2 SC |
8528 | |
8529 | if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { | |
8530 | dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); | |
8531 | dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); | |
8532 | } | |
8533 | ||
3f518509 | 8534 | dev->vlan_features |= features; |
1d17db08 | 8535 | dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; |
10fea26c | 8536 | dev->priv_flags |= IFF_UNICAST_FLT; |
3f518509 | 8537 | |
576193f2 | 8538 | /* MTU range: 68 - 9704 */ |
5777987e | 8539 | dev->min_mtu = ETH_MIN_MTU; |
576193f2 SC |
8540 | /* 9704 == 9728 - 20 and rounding to 8 */ |
8541 | dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; | |
5777987e | 8542 | |
4bb04326 AT |
8543 | /* Phylink isn't used w/ ACPI as of now */ |
8544 | if (port_node) { | |
8545 | phylink = phylink_create(dev, port_fwnode, phy_mode, | |
8546 | &mvpp2_phylink_ops); | |
8547 | if (IS_ERR(phylink)) { | |
8548 | err = PTR_ERR(phylink); | |
8549 | goto err_free_port_pcpu; | |
8550 | } | |
8551 | port->phylink = phylink; | |
8552 | } else { | |
8553 | port->phylink = NULL; | |
8554 | } | |
8555 | ||
3f518509 MW |
8556 | err = register_netdev(dev); |
8557 | if (err < 0) { | |
8558 | dev_err(&pdev->dev, "failed to register netdev\n"); | |
4bb04326 | 8559 | goto err_phylink; |
3f518509 MW |
8560 | } |
8561 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); | |
8562 | ||
bf147153 MW |
8563 | priv->port_list[priv->port_count++] = port; |
8564 | ||
3f518509 MW |
8565 | return 0; |
8566 | ||
4bb04326 AT |
8567 | err_phylink: |
8568 | if (port->phylink) | |
8569 | phylink_destroy(port->phylink); | |
edc660fa MW |
8570 | err_free_port_pcpu: |
8571 | free_percpu(port->pcpu); | |
3f518509 | 8572 | err_free_txq_pcpu: |
09f83975 | 8573 | for (i = 0; i < port->ntxqs; i++) |
3f518509 MW |
8574 | free_percpu(port->txqs[i]->pcpu); |
8575 | err_free_stats: | |
8576 | free_percpu(port->stats); | |
fd3651b2 AT |
8577 | err_free_irq: |
8578 | if (port->link_irq) | |
8579 | irq_dispose_mapping(port->link_irq); | |
591f4cfa TP |
8580 | err_deinit_qvecs: |
8581 | mvpp2_queue_vectors_deinit(port); | |
3f518509 MW |
8582 | err_free_netdev: |
8583 | free_netdev(dev); | |
8584 | return err; | |
8585 | } | |
8586 | ||
8587 | /* Ports removal routine */ | |
8588 | static void mvpp2_port_remove(struct mvpp2_port *port) | |
8589 | { | |
8590 | int i; | |
8591 | ||
8592 | unregister_netdev(port->dev); | |
4bb04326 AT |
8593 | if (port->phylink) |
8594 | phylink_destroy(port->phylink); | |
edc660fa | 8595 | free_percpu(port->pcpu); |
3f518509 | 8596 | free_percpu(port->stats); |
09f83975 | 8597 | for (i = 0; i < port->ntxqs; i++) |
3f518509 | 8598 | free_percpu(port->txqs[i]->pcpu); |
591f4cfa | 8599 | mvpp2_queue_vectors_deinit(port); |
fd3651b2 AT |
8600 | if (port->link_irq) |
8601 | irq_dispose_mapping(port->link_irq); | |
3f518509 MW |
8602 | free_netdev(port->dev); |
8603 | } | |
8604 | ||
8605 | /* Initialize decoding windows */ | |
8606 | static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, | |
8607 | struct mvpp2 *priv) | |
8608 | { | |
8609 | u32 win_enable; | |
8610 | int i; | |
8611 | ||
8612 | for (i = 0; i < 6; i++) { | |
8613 | mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); | |
8614 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); | |
8615 | ||
8616 | if (i < 4) | |
8617 | mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); | |
8618 | } | |
8619 | ||
8620 | win_enable = 0; | |
8621 | ||
8622 | for (i = 0; i < dram->num_cs; i++) { | |
8623 | const struct mbus_dram_window *cs = dram->cs + i; | |
8624 | ||
8625 | mvpp2_write(priv, MVPP2_WIN_BASE(i), | |
8626 | (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | | |
8627 | dram->mbus_dram_target_id); | |
8628 | ||
8629 | mvpp2_write(priv, MVPP2_WIN_SIZE(i), | |
8630 | (cs->size - 1) & 0xffff0000); | |
8631 | ||
8632 | win_enable |= (1 << i); | |
8633 | } | |
8634 | ||
8635 | mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); | |
8636 | } | |
8637 | ||
8638 | /* Initialize Rx FIFO's */ | |
8639 | static void mvpp2_rx_fifo_init(struct mvpp2 *priv) | |
8640 | { | |
8641 | int port; | |
8642 | ||
8643 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { | |
8644 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), | |
2d1d7df8 | 8645 | MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); |
3f518509 | 8646 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), |
2d1d7df8 AT |
8647 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); |
8648 | } | |
8649 | ||
8650 | mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, | |
8651 | MVPP2_RX_FIFO_PORT_MIN_PKT); | |
8652 | mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); | |
8653 | } | |
8654 | ||
8655 | static void mvpp22_rx_fifo_init(struct mvpp2 *priv) | |
8656 | { | |
8657 | int port; | |
8658 | ||
8659 | /* The FIFO size parameters are set depending on the maximum speed a | |
8660 | * given port can handle: | |
8661 | * - Port 0: 10Gbps | |
8662 | * - Port 1: 2.5Gbps | |
8663 | * - Ports 2 and 3: 1Gbps | |
8664 | */ | |
8665 | ||
8666 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), | |
8667 | MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); | |
8668 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), | |
8669 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); | |
8670 | ||
8671 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), | |
8672 | MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); | |
8673 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), | |
8674 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); | |
8675 | ||
8676 | for (port = 2; port < MVPP2_MAX_PORTS; port++) { | |
8677 | mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), | |
8678 | MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); | |
8679 | mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), | |
8680 | MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); | |
3f518509 MW |
8681 | } |
8682 | ||
8683 | mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, | |
8684 | MVPP2_RX_FIFO_PORT_MIN_PKT); | |
8685 | mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); | |
8686 | } | |
8687 | ||
93ff130f YM |
8688 | /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G |
8689 | * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, | |
8690 | * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. | |
8691 | */ | |
7c10f974 AT |
8692 | static void mvpp22_tx_fifo_init(struct mvpp2 *priv) |
8693 | { | |
93ff130f | 8694 | int port, size, thrs; |
7c10f974 | 8695 | |
93ff130f YM |
8696 | for (port = 0; port < MVPP2_MAX_PORTS; port++) { |
8697 | if (port == 0) { | |
8698 | size = MVPP22_TX_FIFO_DATA_SIZE_10KB; | |
8699 | thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; | |
8700 | } else { | |
8701 | size = MVPP22_TX_FIFO_DATA_SIZE_3KB; | |
8702 | thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; | |
8703 | } | |
8704 | mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); | |
8705 | mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); | |
8706 | } | |
7c10f974 AT |
8707 | } |
8708 | ||
6763ce31 TP |
8709 | static void mvpp2_axi_init(struct mvpp2 *priv) |
8710 | { | |
8711 | u32 val, rdval, wrval; | |
8712 | ||
8713 | mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); | |
8714 | ||
8715 | /* AXI Bridge Configuration */ | |
8716 | ||
8717 | rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
8718 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
8719 | rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8720 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
8721 | ||
8722 | wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
8723 | << MVPP22_AXI_ATTR_CACHE_OFFS; | |
8724 | wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8725 | << MVPP22_AXI_ATTR_DOMAIN_OFFS; | |
8726 | ||
8727 | /* BM */ | |
8728 | mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); | |
8729 | mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); | |
8730 | ||
8731 | /* Descriptors */ | |
8732 | mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); | |
8733 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); | |
8734 | mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); | |
8735 | mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); | |
8736 | ||
8737 | /* Buffer Data */ | |
8738 | mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); | |
8739 | mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); | |
8740 | ||
8741 | val = MVPP22_AXI_CODE_CACHE_NON_CACHE | |
8742 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
8743 | val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM | |
8744 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
8745 | mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); | |
8746 | mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); | |
8747 | ||
8748 | val = MVPP22_AXI_CODE_CACHE_RD_CACHE | |
8749 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
8750 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8751 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
8752 | ||
8753 | mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); | |
8754 | ||
8755 | val = MVPP22_AXI_CODE_CACHE_WR_CACHE | |
8756 | << MVPP22_AXI_CODE_CACHE_OFFS; | |
8757 | val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM | |
8758 | << MVPP22_AXI_CODE_DOMAIN_OFFS; | |
8759 | ||
8760 | mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); | |
8761 | } | |
8762 | ||
3f518509 MW |
8763 | /* Initialize network controller common part HW */ |
8764 | static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) | |
8765 | { | |
8766 | const struct mbus_dram_target_info *dram_target_info; | |
8767 | int err, i; | |
08a23755 | 8768 | u32 val; |
3f518509 | 8769 | |
3f518509 MW |
8770 | /* MBUS windows configuration */ |
8771 | dram_target_info = mv_mbus_dram_info(); | |
8772 | if (dram_target_info) | |
8773 | mvpp2_conf_mbus_windows(dram_target_info, priv); | |
8774 | ||
6763ce31 TP |
8775 | if (priv->hw_version == MVPP22) |
8776 | mvpp2_axi_init(priv); | |
8777 | ||
08a23755 | 8778 | /* Disable HW PHY polling */ |
26975821 TP |
8779 | if (priv->hw_version == MVPP21) { |
8780 | val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
8781 | val |= MVPP2_PHY_AN_STOP_SMI0_MASK; | |
8782 | writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); | |
8783 | } else { | |
8784 | val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
8785 | val &= ~MVPP22_SMI_POLLING_EN; | |
8786 | writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); | |
8787 | } | |
08a23755 | 8788 | |
3f518509 MW |
8789 | /* Allocate and initialize aggregated TXQs */ |
8790 | priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), | |
d7ce3cec | 8791 | sizeof(*priv->aggr_txqs), |
3f518509 MW |
8792 | GFP_KERNEL); |
8793 | if (!priv->aggr_txqs) | |
8794 | return -ENOMEM; | |
8795 | ||
8796 | for_each_present_cpu(i) { | |
8797 | priv->aggr_txqs[i].id = i; | |
8798 | priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; | |
85affd7e | 8799 | err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); |
3f518509 MW |
8800 | if (err < 0) |
8801 | return err; | |
8802 | } | |
8803 | ||
7c10f974 AT |
8804 | /* Fifo Init */ |
8805 | if (priv->hw_version == MVPP21) { | |
2d1d7df8 | 8806 | mvpp2_rx_fifo_init(priv); |
7c10f974 | 8807 | } else { |
2d1d7df8 | 8808 | mvpp22_rx_fifo_init(priv); |
7c10f974 AT |
8809 | mvpp22_tx_fifo_init(priv); |
8810 | } | |
3f518509 | 8811 | |
26975821 TP |
8812 | if (priv->hw_version == MVPP21) |
8813 | writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, | |
8814 | priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); | |
3f518509 MW |
8815 | |
8816 | /* Allow cache snoop when transmiting packets */ | |
8817 | mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); | |
8818 | ||
8819 | /* Buffer Manager initialization */ | |
8820 | err = mvpp2_bm_init(pdev, priv); | |
8821 | if (err < 0) | |
8822 | return err; | |
8823 | ||
8824 | /* Parser default initialization */ | |
8825 | err = mvpp2_prs_default_init(pdev, priv); | |
8826 | if (err < 0) | |
8827 | return err; | |
8828 | ||
8829 | /* Classifier default initialization */ | |
8830 | mvpp2_cls_init(priv); | |
8831 | ||
8832 | return 0; | |
8833 | } | |
8834 | ||
8835 | static int mvpp2_probe(struct platform_device *pdev) | |
8836 | { | |
a75edc7c | 8837 | const struct acpi_device_id *acpi_id; |
24812221 MW |
8838 | struct fwnode_handle *fwnode = pdev->dev.fwnode; |
8839 | struct fwnode_handle *port_fwnode; | |
3f518509 MW |
8840 | struct mvpp2 *priv; |
8841 | struct resource *res; | |
a786841d | 8842 | void __iomem *base; |
118d6298 | 8843 | int i; |
3f518509 MW |
8844 | int err; |
8845 | ||
0b92e594 | 8846 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
3f518509 MW |
8847 | if (!priv) |
8848 | return -ENOMEM; | |
8849 | ||
a75edc7c MW |
8850 | if (has_acpi_companion(&pdev->dev)) { |
8851 | acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, | |
8852 | &pdev->dev); | |
8853 | priv->hw_version = (unsigned long)acpi_id->driver_data; | |
8854 | } else { | |
8855 | priv->hw_version = | |
8856 | (unsigned long)of_device_get_match_data(&pdev->dev); | |
8857 | } | |
faca9247 | 8858 | |
3f518509 | 8859 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a786841d TP |
8860 | base = devm_ioremap_resource(&pdev->dev, res); |
8861 | if (IS_ERR(base)) | |
8862 | return PTR_ERR(base); | |
8863 | ||
8864 | if (priv->hw_version == MVPP21) { | |
8865 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
8866 | priv->lms_base = devm_ioremap_resource(&pdev->dev, res); | |
8867 | if (IS_ERR(priv->lms_base)) | |
8868 | return PTR_ERR(priv->lms_base); | |
8869 | } else { | |
8870 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
a75edc7c MW |
8871 | if (has_acpi_companion(&pdev->dev)) { |
8872 | /* In case the MDIO memory region is declared in | |
8873 | * the ACPI, it can already appear as 'in-use' | |
8874 | * in the OS. Because it is overlapped by second | |
8875 | * region of the network controller, make | |
8876 | * sure it is released, before requesting it again. | |
8877 | * The care is taken by mvpp2 driver to avoid | |
8878 | * concurrent access to this memory region. | |
8879 | */ | |
8880 | release_resource(res); | |
8881 | } | |
a786841d TP |
8882 | priv->iface_base = devm_ioremap_resource(&pdev->dev, res); |
8883 | if (IS_ERR(priv->iface_base)) | |
8884 | return PTR_ERR(priv->iface_base); | |
a75edc7c | 8885 | } |
f84bf386 | 8886 | |
a75edc7c | 8887 | if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { |
f84bf386 AT |
8888 | priv->sysctrl_base = |
8889 | syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
8890 | "marvell,system-controller"); | |
8891 | if (IS_ERR(priv->sysctrl_base)) | |
8892 | /* The system controller regmap is optional for dt | |
8893 | * compatibility reasons. When not provided, the | |
8894 | * configuration of the GoP relies on the | |
8895 | * firmware/bootloader. | |
8896 | */ | |
8897 | priv->sysctrl_base = NULL; | |
a786841d TP |
8898 | } |
8899 | ||
01d04936 SC |
8900 | mvpp2_setup_bm_pool(); |
8901 | ||
df089aa0 | 8902 | for (i = 0; i < MVPP2_MAX_THREADS; i++) { |
a786841d TP |
8903 | u32 addr_space_sz; |
8904 | ||
8905 | addr_space_sz = (priv->hw_version == MVPP21 ? | |
8906 | MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); | |
df089aa0 | 8907 | priv->swth_base[i] = base + i * addr_space_sz; |
a786841d | 8908 | } |
3f518509 | 8909 | |
59b9a31e TP |
8910 | if (priv->hw_version == MVPP21) |
8911 | priv->max_port_rxqs = 8; | |
8912 | else | |
8913 | priv->max_port_rxqs = 32; | |
8914 | ||
a75edc7c MW |
8915 | if (dev_of_node(&pdev->dev)) { |
8916 | priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); | |
8917 | if (IS_ERR(priv->pp_clk)) | |
8918 | return PTR_ERR(priv->pp_clk); | |
8919 | err = clk_prepare_enable(priv->pp_clk); | |
8920 | if (err < 0) | |
8921 | return err; | |
3f518509 | 8922 | |
a75edc7c MW |
8923 | priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); |
8924 | if (IS_ERR(priv->gop_clk)) { | |
8925 | err = PTR_ERR(priv->gop_clk); | |
8926 | goto err_pp_clk; | |
fceb55d4 | 8927 | } |
a75edc7c | 8928 | err = clk_prepare_enable(priv->gop_clk); |
fceb55d4 | 8929 | if (err < 0) |
a75edc7c MW |
8930 | goto err_pp_clk; |
8931 | ||
8932 | if (priv->hw_version == MVPP22) { | |
8933 | priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); | |
8934 | if (IS_ERR(priv->mg_clk)) { | |
8935 | err = PTR_ERR(priv->mg_clk); | |
8936 | goto err_gop_clk; | |
8937 | } | |
8938 | ||
8939 | err = clk_prepare_enable(priv->mg_clk); | |
8940 | if (err < 0) | |
8941 | goto err_gop_clk; | |
9af771ce MC |
8942 | |
8943 | priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); | |
8944 | if (IS_ERR(priv->mg_core_clk)) { | |
8945 | priv->mg_core_clk = NULL; | |
8946 | } else { | |
8947 | err = clk_prepare_enable(priv->mg_core_clk); | |
8948 | if (err < 0) | |
8949 | goto err_mg_clk; | |
8950 | } | |
a75edc7c | 8951 | } |
4792ea04 GC |
8952 | |
8953 | priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); | |
8954 | if (IS_ERR(priv->axi_clk)) { | |
8955 | err = PTR_ERR(priv->axi_clk); | |
8956 | if (err == -EPROBE_DEFER) | |
9af771ce | 8957 | goto err_mg_core_clk; |
4792ea04 GC |
8958 | priv->axi_clk = NULL; |
8959 | } else { | |
8960 | err = clk_prepare_enable(priv->axi_clk); | |
8961 | if (err < 0) | |
9af771ce | 8962 | goto err_mg_core_clk; |
4792ea04 | 8963 | } |
fceb55d4 | 8964 | |
a75edc7c MW |
8965 | /* Get system's tclk rate */ |
8966 | priv->tclk = clk_get_rate(priv->pp_clk); | |
8967 | } else if (device_property_read_u32(&pdev->dev, "clock-frequency", | |
8968 | &priv->tclk)) { | |
8969 | dev_err(&pdev->dev, "missing clock-frequency value\n"); | |
8970 | return -EINVAL; | |
8971 | } | |
3f518509 | 8972 | |
2067e0a1 | 8973 | if (priv->hw_version == MVPP22) { |
da42bb27 | 8974 | err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); |
2067e0a1 | 8975 | if (err) |
45f972ad | 8976 | goto err_axi_clk; |
2067e0a1 TP |
8977 | /* Sadly, the BM pools all share the same register to |
8978 | * store the high 32 bits of their address. So they | |
8979 | * must all have the same high 32 bits, which forces | |
8980 | * us to restrict coherent memory to DMA_BIT_MASK(32). | |
8981 | */ | |
8982 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
8983 | if (err) | |
45f972ad | 8984 | goto err_axi_clk; |
2067e0a1 TP |
8985 | } |
8986 | ||
3f518509 MW |
8987 | /* Initialize network controller */ |
8988 | err = mvpp2_init(pdev, priv); | |
8989 | if (err < 0) { | |
8990 | dev_err(&pdev->dev, "failed to initialize controller\n"); | |
45f972ad | 8991 | goto err_axi_clk; |
3f518509 MW |
8992 | } |
8993 | ||
3f518509 | 8994 | /* Initialize ports */ |
24812221 MW |
8995 | fwnode_for_each_available_child_node(fwnode, port_fwnode) { |
8996 | err = mvpp2_port_probe(pdev, port_fwnode, priv); | |
3f518509 | 8997 | if (err < 0) |
26146b0e | 8998 | goto err_port_probe; |
bf147153 MW |
8999 | } |
9000 | ||
9001 | if (priv->port_count == 0) { | |
9002 | dev_err(&pdev->dev, "no ports enabled\n"); | |
9003 | err = -ENODEV; | |
45f972ad | 9004 | goto err_axi_clk; |
3f518509 MW |
9005 | } |
9006 | ||
118d6298 MR |
9007 | /* Statistics must be gathered regularly because some of them (like |
9008 | * packets counters) are 32-bit registers and could overflow quite | |
9009 | * quickly. For instance, a 10Gb link used at full bandwidth with the | |
9010 | * smallest packets (64B) will overflow a 32-bit counter in less than | |
9011 | * 30 seconds. Then, use a workqueue to fill 64-bit counters. | |
9012 | */ | |
118d6298 MR |
9013 | snprintf(priv->queue_name, sizeof(priv->queue_name), |
9014 | "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), | |
9015 | priv->port_count > 1 ? "+" : ""); | |
9016 | priv->stats_queue = create_singlethread_workqueue(priv->queue_name); | |
9017 | if (!priv->stats_queue) { | |
9018 | err = -ENOMEM; | |
26146b0e | 9019 | goto err_port_probe; |
118d6298 MR |
9020 | } |
9021 | ||
3f518509 MW |
9022 | platform_set_drvdata(pdev, priv); |
9023 | return 0; | |
9024 | ||
26146b0e AT |
9025 | err_port_probe: |
9026 | i = 0; | |
24812221 | 9027 | fwnode_for_each_available_child_node(fwnode, port_fwnode) { |
26146b0e AT |
9028 | if (priv->port_list[i]) |
9029 | mvpp2_port_remove(priv->port_list[i]); | |
9030 | i++; | |
9031 | } | |
45f972ad | 9032 | err_axi_clk: |
4792ea04 | 9033 | clk_disable_unprepare(priv->axi_clk); |
9af771ce MC |
9034 | |
9035 | err_mg_core_clk: | |
9036 | if (priv->hw_version == MVPP22) | |
9037 | clk_disable_unprepare(priv->mg_core_clk); | |
45f972ad | 9038 | err_mg_clk: |
fceb55d4 TP |
9039 | if (priv->hw_version == MVPP22) |
9040 | clk_disable_unprepare(priv->mg_clk); | |
3f518509 MW |
9041 | err_gop_clk: |
9042 | clk_disable_unprepare(priv->gop_clk); | |
9043 | err_pp_clk: | |
9044 | clk_disable_unprepare(priv->pp_clk); | |
9045 | return err; | |
9046 | } | |
9047 | ||
9048 | static int mvpp2_remove(struct platform_device *pdev) | |
9049 | { | |
9050 | struct mvpp2 *priv = platform_get_drvdata(pdev); | |
24812221 MW |
9051 | struct fwnode_handle *fwnode = pdev->dev.fwnode; |
9052 | struct fwnode_handle *port_fwnode; | |
3f518509 MW |
9053 | int i = 0; |
9054 | ||
e5c500eb | 9055 | flush_workqueue(priv->stats_queue); |
118d6298 | 9056 | destroy_workqueue(priv->stats_queue); |
118d6298 | 9057 | |
24812221 | 9058 | fwnode_for_each_available_child_node(fwnode, port_fwnode) { |
e5c500eb MR |
9059 | if (priv->port_list[i]) { |
9060 | mutex_destroy(&priv->port_list[i]->gather_stats_lock); | |
3f518509 | 9061 | mvpp2_port_remove(priv->port_list[i]); |
e5c500eb | 9062 | } |
3f518509 MW |
9063 | i++; |
9064 | } | |
9065 | ||
9066 | for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { | |
9067 | struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; | |
9068 | ||
9069 | mvpp2_bm_pool_destroy(pdev, priv, bm_pool); | |
9070 | } | |
9071 | ||
9072 | for_each_present_cpu(i) { | |
9073 | struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; | |
9074 | ||
9075 | dma_free_coherent(&pdev->dev, | |
9076 | MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, | |
9077 | aggr_txq->descs, | |
20396136 | 9078 | aggr_txq->descs_dma); |
3f518509 MW |
9079 | } |
9080 | ||
a75edc7c MW |
9081 | if (is_acpi_node(port_fwnode)) |
9082 | return 0; | |
9083 | ||
4792ea04 | 9084 | clk_disable_unprepare(priv->axi_clk); |
9af771ce | 9085 | clk_disable_unprepare(priv->mg_core_clk); |
fceb55d4 | 9086 | clk_disable_unprepare(priv->mg_clk); |
3f518509 MW |
9087 | clk_disable_unprepare(priv->pp_clk); |
9088 | clk_disable_unprepare(priv->gop_clk); | |
9089 | ||
9090 | return 0; | |
9091 | } | |
9092 | ||
9093 | static const struct of_device_id mvpp2_match[] = { | |
faca9247 TP |
9094 | { |
9095 | .compatible = "marvell,armada-375-pp2", | |
9096 | .data = (void *)MVPP21, | |
9097 | }, | |
fc5e1550 TP |
9098 | { |
9099 | .compatible = "marvell,armada-7k-pp22", | |
9100 | .data = (void *)MVPP22, | |
9101 | }, | |
3f518509 MW |
9102 | { } |
9103 | }; | |
9104 | MODULE_DEVICE_TABLE(of, mvpp2_match); | |
9105 | ||
a75edc7c MW |
9106 | static const struct acpi_device_id mvpp2_acpi_match[] = { |
9107 | { "MRVL0110", MVPP22 }, | |
9108 | { }, | |
9109 | }; | |
9110 | MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); | |
9111 | ||
3f518509 MW |
9112 | static struct platform_driver mvpp2_driver = { |
9113 | .probe = mvpp2_probe, | |
9114 | .remove = mvpp2_remove, | |
9115 | .driver = { | |
9116 | .name = MVPP2_DRIVER_NAME, | |
9117 | .of_match_table = mvpp2_match, | |
a75edc7c | 9118 | .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), |
3f518509 MW |
9119 | }, |
9120 | }; | |
9121 | ||
9122 | module_platform_driver(mvpp2_driver); | |
9123 | ||
9124 | MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); | |
9125 | MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); | |
c634099d | 9126 | MODULE_LICENSE("GPL v2"); |