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octeontx2-af: Support to enable/disable HW timestamping
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / marvell / octeontx2 / af / mbox.h
CommitLineData
26b3f3cc
NK		 1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell OcteonTx2 RVU Admin Function driver
021e2e53
AM		 3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef MBOX_H
12#define MBOX_H
13
14#include <linux/etherdevice.h>
15#include <linux/sizes.h>
16
17#include "rvu_struct.h"
a3e7121c 18#include "common.h"
021e2e53
AM		 19
20#define MBOX_SIZE SZ_64K
21
22/* AF/PF: PF initiated, PF/VF VF initiated */
23#define MBOX_DOWN_RX_START 0
24#define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26#define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27/* AF/PF: AF initiated, PF/VF PF initiated */
28#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29#define MBOX_UP_RX_SIZE SZ_1K
30#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31#define MBOX_UP_TX_SIZE SZ_1K
32
33#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34# error "incorrect mailbox area sizes"
35#endif
36
7304ac45
SG		 37#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38
fdb90298 39#define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */
021e2e53
AM		 40
41#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
42
43/* Mailbox directions */
44#define MBOX_DIR_AFPF 0 /* AF replies to PF */
45#define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46#define MBOX_DIR_PFVF 2 /* PF replies to VF */
47#define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
52
53struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
55 spinlock_t mbox_lock;
56 u16 msg_size; /* Total msg size to be sent */
57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
58 u16 num_msgs; /* No of msgs sent or waiting for response */
59 u16 msgs_acked; /* No of msgs for which response is received */
60};
61
62struct otx2_mbox {
63 struct pci_dev *pdev;
64 void *hwbase; /* Mbox region advertised by HW */
65 void *reg_base;/* CSR base for this dev */
66 u64 trigger; /* Trigger mbox notification */
67 u16 tr_shift; /* Mbox trigger shift */
68 u64 rx_start; /* Offset of Rx region in mbox memory */
69 u64 tx_start; /* Offset of Tx region in mbox memory */
70 u16 rx_size; /* Size of Rx region */
71 u16 tx_size; /* Size of Tx region */
72 u16 ndevs; /* The number of peers */
73 struct otx2_mbox_dev *dev;
74};
75
76/* Header which preceeds all mbox messages */
77struct mbox_hdr {
fdb90298 78 u64 msg_size; /* Total msgs size embedded */
021e2e53
AM		 79 u16 num_msgs; /* No of msgs embedded */
80};
81
82/* Header which preceeds every msg and is also part of it */
83struct mbox_msghdr {
84 u16 pcifunc; /* Who's sending this msg */
85 u16 id; /* Mbox message ID */
86#define OTX2_MBOX_REQ_SIG (0xdead)
87#define OTX2_MBOX_RSP_SIG (0xbeef)
88 u16 sig; /* Signature, for validating corrupted msgs */
89#define OTX2_MBOX_VERSION (0x0001)
90 u16 ver; /* Version of msg's structure for this ID */
91 u16 next_msgoff; /* Offset of next msg within mailbox region */
92 int rc; /* Msg process'ed response code */
93};
94
95void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
96void otx2_mbox_destroy(struct otx2_mbox *mbox);
7304ac45
SG		 97int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
98 struct pci_dev *pdev, void __force *reg_base,
99 int direction, int ndevs);
021e2e53
AM		 100void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
101int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
102int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
103struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
104 int size, int size_rsp);
105struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
106 struct mbox_msghdr *msg);
a36740f6 107int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
021e2e53
AM		 108int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
109 u16 pcifunc, u16 id);
110bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
111const char *otx2_mbox_id2name(u16 id);
112static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
113 int devid, int size)
114{
115 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
116}
117
118/* Mailbox message types */
119#define MBOX_MSG_MASK 0xFFFF
120#define MBOX_MSG_INVALID 0xFFFE
121#define MBOX_MSG_MAX 0xFFFF
122
123#define MBOX_MESSAGES \
746ea742 124/* Generic mbox IDs (range 0x000 - 0x1FF) */ \
eac66686
SG		 125M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
126M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
127M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
27150bc4 128M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
c554f9c1 129M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
5d9b976d 130M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
746ea742 131/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
eac66686
SG		 132M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
133M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
134M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
135M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
96be2e0d 136 cgx_mac_addr_set_or_get) \
eac66686 137M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
96be2e0d 138 cgx_mac_addr_set_or_get) \
eac66686
SG		 139M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
140M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
141M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
142M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
143M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
144M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
145M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
42157217
ZS		 146M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
147M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
f7e086e7
G		 148M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
149 cgx_pause_frm_cfg) \
746ea742 150/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
eac66686
SG		 151M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
152 npa_lf_alloc_req, npa_lf_alloc_rsp) \
153M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
154M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
155M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
746ea742
SG		 156/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
157/* TIM mbox IDs (range 0x800 - 0x9FF) */ \
158/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
159/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
f9274958
SG		 160M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
161 npc_mcam_alloc_entry_rsp) \
162M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
163 npc_mcam_free_entry_req, msg_rsp) \
651cd265
SG		 164M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
165 npc_mcam_write_entry_req, msg_rsp) \
166M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
167 npc_mcam_ena_dis_entry_req, msg_rsp) \
168M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
169 npc_mcam_ena_dis_entry_req, msg_rsp) \
170M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
171 npc_mcam_shift_entry_rsp) \
7fbb3f23
SG		 172M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
173 npc_mcam_alloc_counter_req, \
174 npc_mcam_alloc_counter_rsp) \
175M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
176 npc_mcam_oper_counter_req, msg_rsp) \
a958dd59
SG		 177M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
178 npc_mcam_unmap_counter_req, msg_rsp) \
7fbb3f23
SG		 179M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
180 npc_mcam_oper_counter_req, msg_rsp) \
181M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
182 npc_mcam_oper_counter_req, \
183 npc_mcam_oper_counter_rsp) \
63be91c8
SG		 184M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
185 npc_mcam_alloc_and_write_entry_req, \
186 npc_mcam_alloc_and_write_entry_rsp) \
631e70bb
SS		 187M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
188 msg_req, npc_get_kex_cfg_rsp) \
746ea742 189/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
eac66686
SG		 190M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
191 nix_lf_alloc_req, nix_lf_alloc_rsp) \
192M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \
193M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
194M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
195 hwctx_disable_req, msg_rsp) \
196M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
197 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
198M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
199M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
200M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
201M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
202M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
bd522d68
JJ		 203 nix_rss_flowkey_cfg, \
204 nix_rss_flowkey_cfg_rsp) \
eac66686 205M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
9b7dd87a 206M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
40df309e
SG		 207M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
208M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
86cea61d 209M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
a27d7659
KK		 210M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
211 nix_mark_format_cfg, \
212 nix_mark_format_cfg_rsp) \
159a8a67 213M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
da5d32e1
ND		 214M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
215 nix_lso_format_cfg, \
216 nix_lso_format_cfg_rsp) \
34bfe0eb 217M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) \
42157217
ZS		 218M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
219M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
27150bc4
G		 220M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
221 nix_bp_cfg_rsp) \
222M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
34bfe0eb 223M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
021e2e53 224
61071a87
LC		 225/* Messages initiated by AF (range 0xC00 - 0xDFF) */
226#define MBOX_UP_CGX_MESSAGES \
eac66686 227M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
61071a87 228
021e2e53 229enum {
eac66686 230#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
021e2e53 231MBOX_MESSAGES
61071a87 232MBOX_UP_CGX_MESSAGES
021e2e53
AM		 233#undef M
234};
235
236/* Mailbox message formats */
237
cb30711a
SG		 238#define RVU_DEFAULT_PF_FUNC 0xFFFF
239
021e2e53
AM		 240/* Generic request msg used for those mbox messages which
241 * don't send any data in the request.
242 */
243struct msg_req {
244 struct mbox_msghdr hdr;
245};
246
247/* Generic rsponse msg used a ack or response for those mbox
248 * messages which doesn't have a specific rsp msg format.
249 */
250struct msg_rsp {
251 struct mbox_msghdr hdr;
252};
253
c554f9c1
G		 254/* RVU mailbox error codes
255 * Range 256 - 300.
256 */
257enum rvu_af_status {
258 RVU_INVALID_VF_ID = -256,
259};
260
7304ac45
SG		 261struct ready_msg_rsp {
262 struct mbox_msghdr hdr;
4f4eebf2
LC		 263 u16 sclk_freq; /* SCLK frequency (in MHz) */
264 u16 rclk_freq; /* RCLK frequency (in MHz) */
7304ac45
SG		 265};
266
746ea742
SG		 267/* Structure for requesting resource provisioning.
268 * 'modify' flag to be used when either requesting more
269 * or to detach partial of a cetain resource type.
270 * Rest of the fields specify how many of what type to
271 * be attached.
272 */
273struct rsrc_attach {
274 struct mbox_msghdr hdr;
275 u8 modify:1;
276 u8 npalf:1;
277 u8 nixlf:1;
278 u16 sso;
279 u16 ssow;
280 u16 timlfs;
281 u16 cptlfs;
282};
283
284/* Structure for relinquishing resources.
285 * 'partial' flag to be used when relinquishing all resources
286 * but only of a certain type. If not set, all resources of all
287 * types provisioned to the RVU function will be detached.
288 */
289struct rsrc_detach {
290 struct mbox_msghdr hdr;
291 u8 partial:1;
292 u8 npalf:1;
293 u8 nixlf:1;
294 u8 sso:1;
295 u8 ssow:1;
296 u8 timlfs:1;
297 u8 cptlfs:1;
298};
299
756051e2
SG		 300#define MSIX_VECTOR_INVALID 0xFFFF
301#define MAX_RVU_BLKLF_CNT 256
302
303struct msix_offset_rsp {
304 struct mbox_msghdr hdr;
305 u16 npa_msixoff;
306 u16 nix_msixoff;
307 u8 sso;
308 u8 ssow;
309 u8 timlfs;
310 u8 cptlfs;
311 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
312 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
313 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
314 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
315};
316
5d9b976d
SG		 317struct get_hw_cap_rsp {
318 struct mbox_msghdr hdr;
319 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
320 u8 nix_shaping; /* Is shaping and coloring supported */
321};
322
66208910
CJ		 323/* CGX mbox message formats */
324
325struct cgx_stats_rsp {
326 struct mbox_msghdr hdr;
327#define CGX_RX_STATS_COUNT 13
328#define CGX_TX_STATS_COUNT 18
329 u64 rx_stats[CGX_RX_STATS_COUNT];
330 u64 tx_stats[CGX_TX_STATS_COUNT];
331};
332
96be2e0d
VR		 333/* Structure for requesting the operation for
334 * setting/getting mac address in the CGX interface
335 */
336struct cgx_mac_addr_set_or_get {
337 struct mbox_msghdr hdr;
338 u8 mac_addr[ETH_ALEN];
339};
61071a87
LC		 340
341struct cgx_link_user_info {
342 uint64_t link_up:1;
343 uint64_t full_duplex:1;
344 uint64_t lmac_type_id:4;
345 uint64_t speed:20; /* speed in Mbps */
346#define LMACTYPE_STR_LEN 16
347 char lmac_type[LMACTYPE_STR_LEN];
348};
349
350struct cgx_link_info_msg {
351 struct mbox_msghdr hdr;
352 struct cgx_link_user_info link_info;
353};
3fa4c323 354
f7e086e7
G		 355struct cgx_pause_frm_cfg {
356 struct mbox_msghdr hdr;
357 u8 set;
358 /* set = 1 if the request is to config pause frames */
359 /* set = 0 if the request is to fetch pause frames config */
360 u8 rx_pause;
361 u8 tx_pause;
362};
363
3fa4c323
SG		 364/* NPA mbox message formats */
365
366/* NPA mailbox error codes
367 * Range 301 - 400.
368 */
369enum npa_af_status {
370 NPA_AF_ERR_PARAM = -301,
371 NPA_AF_ERR_AQ_FULL = -302,
372 NPA_AF_ERR_AQ_ENQUEUE = -303,
373 NPA_AF_ERR_AF_LF_INVALID = -304,
374 NPA_AF_ERR_AF_LF_ALLOC = -305,
375 NPA_AF_ERR_LF_RESET = -306,
376};
377
378/* For NPA LF context alloc and init */
379struct npa_lf_alloc_req {
380 struct mbox_msghdr hdr;
381 int node;
382 int aura_sz; /* No of auras */
383 u32 nr_pools; /* No of pools */
ee1e7591 384 u64 way_mask;
3fa4c323
SG		 385};
386
387struct npa_lf_alloc_rsp {
388 struct mbox_msghdr hdr;
389 u32 stack_pg_ptrs; /* No of ptrs per stack page */
390 u32 stack_pg_bytes; /* Size of stack page */
391 u16 qints; /* NPA_AF_CONST::QINTS */
392};
393
4a3581cd
SG		 394/* NPA AQ enqueue msg */
395struct npa_aq_enq_req {
396 struct mbox_msghdr hdr;
397 u32 aura_id;
398 u8 ctype;
399 u8 op;
400 union {
401 /* Valid when op == WRITE/INIT and ctype == AURA.
402 * LF fills the pool_id in aura.pool_addr. AF will translate
403 * the pool_id to pool context pointer.
404 */
405 struct npa_aura_s aura;
406 /* Valid when op == WRITE/INIT and ctype == POOL */
407 struct npa_pool_s pool;
408 };
409 /* Mask data when op == WRITE (1=write, 0=don't write) */
410 union {
411 /* Valid when op == WRITE and ctype == AURA */
412 struct npa_aura_s aura_mask;
413 /* Valid when op == WRITE and ctype == POOL */
414 struct npa_pool_s pool_mask;
415 };
416};
417
418struct npa_aq_enq_rsp {
419 struct mbox_msghdr hdr;
420 union {
421 /* Valid when op == READ and ctype == AURA */
422 struct npa_aura_s aura;
423 /* Valid when op == READ and ctype == POOL */
424 struct npa_pool_s pool;
425 };
426};
427
57856dde
G		 428/* Disable all contexts of type 'ctype' */
429struct hwctx_disable_req {
430 struct mbox_msghdr hdr;
431 u8 ctype;
432};
433
f9274958
SG		 434/* NIX mbox message formats */
435
cb30711a
SG		 436/* NIX mailbox error codes
437 * Range 401 - 500.
438 */
439enum nix_af_status {
440 NIX_AF_ERR_PARAM = -401,
441 NIX_AF_ERR_AQ_FULL = -402,
442 NIX_AF_ERR_AQ_ENQUEUE = -403,
443 NIX_AF_ERR_AF_LF_INVALID = -404,
444 NIX_AF_ERR_AF_LF_ALLOC = -405,
445 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
446 NIX_AF_ERR_TLX_INVALID = -407,
447 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
448 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
449 NIX_AF_ERR_FRS_INVALID = -410,
450 NIX_AF_ERR_RX_LINK_INVALID = -411,
451 NIX_AF_INVAL_TXSCHQ_CFG = -412,
452 NIX_AF_SMQ_FLUSH_FAILED = -413,
453 NIX_AF_ERR_LF_RESET = -414,
b648366c 454 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
7ee74697 455 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
a27d7659 456 NIX_AF_ERR_MARK_CFG_FAIL = -417,
da5d32e1 457 NIX_AF_ERR_LSO_CFG_FAIL = -418,
f325d3f4
SG		 458 NIX_AF_INVAL_NPA_PF_FUNC = -419,
459 NIX_AF_INVAL_SSO_PF_FUNC = -420,
cb30711a
SG		 460};
461
462/* For NIX LF context alloc and init */
463struct nix_lf_alloc_req {
464 struct mbox_msghdr hdr;
465 int node;
466 u32 rq_cnt; /* No of receive queues */
467 u32 sq_cnt; /* No of send queues */
468 u32 cq_cnt; /* No of completion queues */
469 u8 xqe_sz;
470 u16 rss_sz;
471 u8 rss_grps;
472 u16 npa_func;
473 u16 sso_func;
474 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
ee1e7591 475 u64 way_mask;
cb30711a
SG		 476};
477
478struct nix_lf_alloc_rsp {
479 struct mbox_msghdr hdr;
480 u16 sqb_size;
f5721f76
SK		 481 u16 rx_chan_base;
482 u16 tx_chan_base;
483 u8 rx_chan_cnt; /* total number of RX channels */
484 u8 tx_chan_cnt; /* total number of TX channels */
59360e98
SG		 485 u8 lso_tsov4_idx;
486 u8 lso_tsov6_idx;
cb30711a 487 u8 mac_addr[ETH_ALEN];
34425e8c
KK		 488 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
489 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
490 u16 cints; /* NIX_AF_CONST2::CINTS */
491 u16 qints; /* NIX_AF_CONST2::QINTS */
cb30711a
SG		 492};
493
ffb0abd7
SG		 494/* NIX AQ enqueue msg */
495struct nix_aq_enq_req {
496 struct mbox_msghdr hdr;
497 u32 qidx;
498 u8 ctype;
499 u8 op;
500 union {
501 struct nix_rq_ctx_s rq;
502 struct nix_sq_ctx_s sq;
503 struct nix_cq_ctx_s cq;
504 struct nix_rsse_s rss;
505 struct nix_rx_mce_s mce;
506 };
507 union {
508 struct nix_rq_ctx_s rq_mask;
509 struct nix_sq_ctx_s sq_mask;
510 struct nix_cq_ctx_s cq_mask;
511 struct nix_rsse_s rss_mask;
512 struct nix_rx_mce_s mce_mask;
513 };
514};
515
516struct nix_aq_enq_rsp {
517 struct mbox_msghdr hdr;
518 union {
519 struct nix_rq_ctx_s rq;
520 struct nix_sq_ctx_s sq;
521 struct nix_cq_ctx_s cq;
522 struct nix_rsse_s rss;
523 struct nix_rx_mce_s mce;
524 };
525};
526
a3e7121c
SG		 527/* Tx scheduler/shaper mailbox messages */
528
529#define MAX_TXSCHQ_PER_FUNC 128
530
531struct nix_txsch_alloc_req {
532 struct mbox_msghdr hdr;
533 /* Scheduler queue count request at each level */
534 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
535 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
536};
537
538struct nix_txsch_alloc_rsp {
539 struct mbox_msghdr hdr;
540 /* Scheduler queue count allocated at each level */
541 u16 schq_contig[NIX_TXSCH_LVL_CNT];
542 u16 schq[NIX_TXSCH_LVL_CNT];
543 /* Scheduler queue list allocated at each level */
544 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
545 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
5d9b976d
SG		 546 u8 aggr_level; /* Traffic aggregation scheduler level */
547 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
548 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
a3e7121c
SG		 549};
550
551struct nix_txsch_free_req {
552 struct mbox_msghdr hdr;
553#define TXSCHQ_FREE_ALL BIT_ULL(0)
554 u16 flags;
555 /* Scheduler queue level to be freed */
556 u16 schq_lvl;
557 /* List of scheduler queues to be freed */
558 u16 schq;
559};
560
b279bbb3
SG		 561struct nix_txschq_config {
562 struct mbox_msghdr hdr;
563 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
564#define TXSCHQ_IDX_SHIFT 16
565#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
566#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
567 u8 num_regs;
568#define MAX_REGS_PER_MBOX_MSG 20
569 u64 reg[MAX_REGS_PER_MBOX_MSG];
570 u64 regval[MAX_REGS_PER_MBOX_MSG];
571};
572
d02913d9
VA		 573struct nix_vtag_config {
574 struct mbox_msghdr hdr;
86cea61d 575 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
d02913d9
VA		 576 u8 vtag_size;
577 /* cfg_type is '0' for tx vlan cfg
578 * cfg_type is '1' for rx vlan cfg
579 */
580 u8 cfg_type;
581 union {
582 /* valid when cfg_type is '0' */
583 struct {
584 /* tx vlan0 tag(C-VLAN) */
585 u64 vlan0;
586 /* tx vlan1 tag(S-VLAN) */
587 u64 vlan1;
588 /* insert tx vlan tag */
589 u8 insert_vlan :1;
590 /* insert tx double vlan tag */
591 u8 double_vlan :1;
592 } tx;
593
594 /* valid when cfg_type is '1' */
595 struct {
86cea61d 596 /* rx vtag type index, valid values are in 0..7 range */
d02913d9
VA		 597 u8 vtag_type;
598 /* rx vtag strip */
599 u8 strip_vtag :1;
600 /* rx vtag capture */
601 u8 capture_vtag :1;
602 } rx;
603 };
604};
605
cc96b0e9
SG		 606struct nix_rss_flowkey_cfg {
607 struct mbox_msghdr hdr;
608 int mcam_index; /* MCAM entry index to modify */
bd522d68
JJ		 609#define NIX_FLOW_KEY_TYPE_PORT BIT(0)
610#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
611#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
612#define NIX_FLOW_KEY_TYPE_TCP BIT(3)
613#define NIX_FLOW_KEY_TYPE_UDP BIT(4)
614#define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
206ff848
KK		 615#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
616#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
617#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
618#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
619#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
620#define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
621#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
622#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
623#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
624#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
625#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
626#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
cc96b0e9
SG		 627 u32 flowkey_cfg; /* Flowkey types selected */
628 u8 group; /* RSS context or group */
629};
630
bd522d68
JJ		 631struct nix_rss_flowkey_cfg_rsp {
632 struct mbox_msghdr hdr;
633 u8 alg_idx; /* Selected algo index */
634};
635
6f03cf10
SG		 636struct nix_set_mac_addr {
637 struct mbox_msghdr hdr;
638 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
639};
640
34bfe0eb
SG		 641struct nix_get_mac_addr_rsp {
642 struct mbox_msghdr hdr;
643 u8 mac_addr[ETH_ALEN];
644};
645
a27d7659
KK		 646struct nix_mark_format_cfg {
647 struct mbox_msghdr hdr;
648 u8 offset;
649 u8 y_mask;
650 u8 y_val;
651 u8 r_mask;
652 u8 r_val;
653};
654
655struct nix_mark_format_cfg_rsp {
656 struct mbox_msghdr hdr;
657 u8 mark_format_idx;
658};
659
d6f092ca
SG		 660struct nix_rx_mode {
661 struct mbox_msghdr hdr;
662#define NIX_RX_MODE_UCAST BIT(0)
663#define NIX_RX_MODE_PROMISC BIT(1)
664#define NIX_RX_MODE_ALLMULTI BIT(2)
665 u16 mode;
666};
667
159a8a67
VR		 668struct nix_rx_cfg {
669 struct mbox_msghdr hdr;
670#define NIX_RX_OL3_VERIFY BIT(0)
671#define NIX_RX_OL4_VERIFY BIT(1)
672 u8 len_verify; /* Outer L3/L4 len check */
673#define NIX_RX_CSUM_OL4_VERIFY BIT(0)
674 u8 csum_verify; /* Outer L4 checksum verification */
675};
676
9b7dd87a
SG		 677struct nix_frs_cfg {
678 struct mbox_msghdr hdr;
679 u8 update_smq; /* Update SMQ's min/max lens */
680 u8 update_minlen; /* Set minlen also */
681 u8 sdp_link; /* Set SDP RX link */
682 u16 maxlen;
683 u16 minlen;
684};
685
da5d32e1
ND		 686struct nix_lso_format_cfg {
687 struct mbox_msghdr hdr;
688 u64 field_mask;
689#define NIX_LSO_FIELD_MAX 8
690 u64 fields[NIX_LSO_FIELD_MAX];
691};
692
693struct nix_lso_format_cfg_rsp {
694 struct mbox_msghdr hdr;
695 u8 lso_format_idx;
696};
697
27150bc4
G		 698struct nix_bp_cfg_req {
699 struct mbox_msghdr hdr;
700 u16 chan_base; /* Starting channel number */
701 u8 chan_cnt; /* Number of channels */
702 u8 bpid_per_chan;
703 /* bpid_per_chan = 0 assigns single bp id for range of channels */
704 /* bpid_per_chan = 1 assigns separate bp id for each channel */
705};
706
707/* PF can be mapped to either CGX or LBK interface,
708 * so maximum 64 channels are possible.
709 */
710#define NIX_MAX_BPID_CHAN 64
711struct nix_bp_cfg_rsp {
712 struct mbox_msghdr hdr;
713 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
714 u8 chan_cnt; /* Number of channel for which bpids are assigned */
715};
716
f9274958
SG		 717/* NPC mbox message structs */
718
719#define NPC_MCAM_ENTRY_INVALID 0xFFFF
720#define NPC_MCAM_INVALID_MAP 0xFFFF
721
722/* NPC mailbox error codes
723 * Range 701 - 800.
724 */
725enum npc_af_status {
726 NPC_MCAM_INVALID_REQ = -701,
727 NPC_MCAM_ALLOC_DENIED = -702,
728 NPC_MCAM_ALLOC_FAILED = -703,
729 NPC_MCAM_PERM_DENIED = -704,
730};
731
732struct npc_mcam_alloc_entry_req {
733 struct mbox_msghdr hdr;
734#define NPC_MAX_NONCONTIG_ENTRIES 256
735 u8 contig; /* Contiguous entries ? */
736#define NPC_MCAM_ANY_PRIO 0
737#define NPC_MCAM_LOWER_PRIO 1
738#define NPC_MCAM_HIGHER_PRIO 2
739 u8 priority; /* Lower or higher w.r.t ref_entry */
740 u16 ref_entry;
741 u16 count; /* Number of entries requested */
742};
743
744struct npc_mcam_alloc_entry_rsp {
745 struct mbox_msghdr hdr;
746 u16 entry; /* Entry allocated or start index if contiguous.
747 * Invalid incase of non-contiguous.
748 */
749 u16 count; /* Number of entries allocated */
750 u16 free_count; /* Number of entries available */
751 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
752};
753
754struct npc_mcam_free_entry_req {
755 struct mbox_msghdr hdr;
756 u16 entry; /* Entry index to be freed */
757 u8 all; /* If all entries allocated to this PFVF to be freed */
758};
759
651cd265
SG		 760struct mcam_entry {
761#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
762 u64 kw[NPC_MAX_KWS_IN_KEY];
763 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
764 u64 action;
765 u64 vtag_action;
766};
767
768struct npc_mcam_write_entry_req {
769 struct mbox_msghdr hdr;
770 struct mcam_entry entry_data;
771 u16 entry; /* MCAM entry to write this match key */
772 u16 cntr; /* Counter for this MCAM entry */
773 u8 intf; /* Rx or Tx interface */
774 u8 enable_entry;/* Enable this MCAM entry ? */
775 u8 set_cntr; /* Set counter for this entry ? */
776};
777
778/* Enable/Disable a given entry */
779struct npc_mcam_ena_dis_entry_req {
780 struct mbox_msghdr hdr;
781 u16 entry;
782};
783
784struct npc_mcam_shift_entry_req {
785 struct mbox_msghdr hdr;
786#define NPC_MCAM_MAX_SHIFTS 64
787 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
788 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
789 u16 shift_count; /* Number of entries to shift */
790};
791
792struct npc_mcam_shift_entry_rsp {
793 struct mbox_msghdr hdr;
794 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
795};
796
7fbb3f23
SG		 797struct npc_mcam_alloc_counter_req {
798 struct mbox_msghdr hdr;
799 u8 contig; /* Contiguous counters ? */
800#define NPC_MAX_NONCONTIG_COUNTERS 64
801 u16 count; /* Number of counters requested */
802};
803
804struct npc_mcam_alloc_counter_rsp {
805 struct mbox_msghdr hdr;
806 u16 cntr; /* Counter allocated or start index if contiguous.
807 * Invalid incase of non-contiguous.
808 */
809 u16 count; /* Number of counters allocated */
810 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
811};
812
813struct npc_mcam_oper_counter_req {
814 struct mbox_msghdr hdr;
815 u16 cntr; /* Free a counter or clear/fetch it's stats */
816};
817
818struct npc_mcam_oper_counter_rsp {
819 struct mbox_msghdr hdr;
820 u64 stat; /* valid only while fetching counter's stats */
821};
822
a958dd59
SG		 823struct npc_mcam_unmap_counter_req {
824 struct mbox_msghdr hdr;
825 u16 cntr;
826 u16 entry; /* Entry and counter to be unmapped */
827 u8 all; /* Unmap all entries using this counter ? */
828};
829
63be91c8
SG		 830struct npc_mcam_alloc_and_write_entry_req {
831 struct mbox_msghdr hdr;
832 struct mcam_entry entry_data;
833 u16 ref_entry;
834 u8 priority; /* Lower or higher w.r.t ref_entry */
835 u8 intf; /* Rx or Tx interface */
836 u8 enable_entry;/* Enable this MCAM entry ? */
837 u8 alloc_cntr; /* Allocate counter and map ? */
838};
839
840struct npc_mcam_alloc_and_write_entry_rsp {
841 struct mbox_msghdr hdr;
842 u16 entry;
843 u16 cntr;
844};
845
631e70bb
SS		 846struct npc_get_kex_cfg_rsp {
847 struct mbox_msghdr hdr;
848 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
849 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
850#define NPC_MAX_INTF 2
851#define NPC_MAX_LID 8
852#define NPC_MAX_LT 16
853#define NPC_MAX_LD 2
854#define NPC_MAX_LFL 16
855 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
856 u64 kex_ld_flags[NPC_MAX_LD];
857 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
858 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
859 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
860 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
23705adb
VA		 861#define MKEX_NAME_LEN 128
862 u8 mkex_pfl_name[MKEX_NAME_LEN];
631e70bb
SS		 863};
864
021e2e53 865#endif /* MBOX_H */
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