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Commit | Line | Data |
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16547577 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
cb0e3ec4 | 2 | /* Marvell RVU Ethernet driver |
16547577 | 3 | * |
cb0e3ec4 | 4 | * Copyright (C) 2020 Marvell. |
16547577 | 5 | * |
16547577 SG |
6 | */ |
7 | ||
8 | #ifndef OTX2_COMMON_H | |
9 | #define OTX2_COMMON_H | |
10 | ||
cc69837f | 11 | #include <linux/ethtool.h> |
16547577 | 12 | #include <linux/pci.h> |
caa2da34 | 13 | #include <linux/iommu.h> |
c9c12d33 AM |
14 | #include <linux/net_tstamp.h> |
15 | #include <linux/ptp_clock_kernel.h> | |
16 | #include <linux/timecounter.h> | |
956fb852 | 17 | #include <linux/soc/marvell/octeontx2/asm.h> |
1d4d9e42 | 18 | #include <net/pkt_cls.h> |
2da48943 | 19 | #include <net/devlink.h> |
16547577 | 20 | |
5a6d7c9d | 21 | #include <mbox.h> |
f0a1913f | 22 | #include <npc.h> |
16547577 | 23 | #include "otx2_reg.h" |
caa2da34 | 24 | #include "otx2_txrx.h" |
2da48943 | 25 | #include "otx2_devlink.h" |
31a97460 | 26 | #include <rvu_trace.h> |
16547577 SG |
27 | |
28 | /* PCI device IDs */ | |
29 | #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 | |
3184fb5b TD |
30 | #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 |
31 | #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 | |
16547577 | 32 | |
04a21ef3 SG |
33 | #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 |
34 | ||
16547577 SG |
35 | /* PCI BAR nos */ |
36 | #define PCI_CFG_REG_BAR_NUM 2 | |
5a6d7c9d SG |
37 | #define PCI_MBOX_BAR_NUM 4 |
38 | ||
39 | #define NAME_SIZE 32 | |
40 | ||
caa2da34 SG |
41 | enum arua_mapped_qtypes { |
42 | AURA_NIX_RQ, | |
43 | AURA_NIX_SQ, | |
05fcc9e0 SG |
44 | }; |
45 | ||
04a21ef3 SG |
46 | /* NIX LF interrupts range*/ |
47 | #define NIX_LF_QINT_VEC_START 0x00 | |
48 | #define NIX_LF_CINT_VEC_START 0x40 | |
49 | #define NIX_LF_GINT_VEC 0x80 | |
50 | #define NIX_LF_ERR_VEC 0x81 | |
51 | #define NIX_LF_POISON_VEC 0x82 | |
52 | ||
4c236d5d G |
53 | /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ |
54 | #define SEND_CQ_SKID 2000 | |
55 | ||
ef6c8da7 G |
56 | struct otx2_lmt_info { |
57 | u64 lmt_addr; | |
58 | u16 lmt_id; | |
59 | }; | |
85069e95 | 60 | /* RSS configuration */ |
81a43620 G |
61 | struct otx2_rss_ctx { |
62 | u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; | |
63 | }; | |
64 | ||
85069e95 SG |
65 | struct otx2_rss_info { |
66 | u8 enable; | |
67 | u32 flowkey_cfg; | |
68 | u16 rss_size; | |
85069e95 SG |
69 | #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ |
70 | u8 key[RSS_HASH_KEY_SIZE]; | |
81a43620 | 71 | struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; |
85069e95 SG |
72 | }; |
73 | ||
abe02543 SG |
74 | /* NIX (or NPC) RX errors */ |
75 | enum otx2_errlvl { | |
76 | NPC_ERRLVL_RE, | |
77 | NPC_ERRLVL_LID_LA, | |
78 | NPC_ERRLVL_LID_LB, | |
79 | NPC_ERRLVL_LID_LC, | |
80 | NPC_ERRLVL_LID_LD, | |
81 | NPC_ERRLVL_LID_LE, | |
82 | NPC_ERRLVL_LID_LF, | |
83 | NPC_ERRLVL_LID_LG, | |
84 | NPC_ERRLVL_LID_LH, | |
85 | NPC_ERRLVL_NIX = 0x0F, | |
86 | }; | |
87 | ||
88 | enum otx2_errcodes_re { | |
89 | /* NPC_ERRLVL_RE errcodes */ | |
90 | ERRCODE_FCS = 0x7, | |
91 | ERRCODE_FCS_RCV = 0x8, | |
92 | ERRCODE_UNDERSIZE = 0x10, | |
93 | ERRCODE_OVERSIZE = 0x11, | |
94 | ERRCODE_OL2_LEN_MISMATCH = 0x12, | |
95 | /* NPC_ERRLVL_NIX errcodes */ | |
96 | ERRCODE_OL3_LEN = 0x10, | |
97 | ERRCODE_OL4_LEN = 0x11, | |
98 | ERRCODE_OL4_CSUM = 0x12, | |
99 | ERRCODE_IL3_LEN = 0x20, | |
100 | ERRCODE_IL4_LEN = 0x21, | |
101 | ERRCODE_IL4_CSUM = 0x22, | |
102 | }; | |
103 | ||
e239d0c7 G |
104 | /* NIX TX stats */ |
105 | enum nix_stat_lf_tx { | |
106 | TX_UCAST = 0x0, | |
107 | TX_BCAST = 0x1, | |
108 | TX_MCAST = 0x2, | |
109 | TX_DROP = 0x3, | |
110 | TX_OCTS = 0x4, | |
111 | TX_STATS_ENUM_LAST, | |
112 | }; | |
113 | ||
114 | /* NIX RX stats */ | |
115 | enum nix_stat_lf_rx { | |
116 | RX_OCTS = 0x0, | |
117 | RX_UCAST = 0x1, | |
118 | RX_BCAST = 0x2, | |
119 | RX_MCAST = 0x3, | |
120 | RX_DROP = 0x4, | |
121 | RX_DROP_OCTS = 0x5, | |
122 | RX_FCS = 0x6, | |
123 | RX_ERR = 0x7, | |
124 | RX_DRP_BCAST = 0x8, | |
125 | RX_DRP_MCAST = 0x9, | |
126 | RX_DRP_L3BCAST = 0xa, | |
127 | RX_DRP_L3MCAST = 0xb, | |
128 | RX_STATS_ENUM_LAST, | |
129 | }; | |
130 | ||
131 | struct otx2_dev_stats { | |
132 | u64 rx_bytes; | |
133 | u64 rx_frames; | |
134 | u64 rx_ucast_frames; | |
135 | u64 rx_bcast_frames; | |
136 | u64 rx_mcast_frames; | |
137 | u64 rx_drops; | |
138 | ||
139 | u64 tx_bytes; | |
140 | u64 tx_frames; | |
141 | u64 tx_ucast_frames; | |
142 | u64 tx_bcast_frames; | |
143 | u64 tx_mcast_frames; | |
144 | u64 tx_drops; | |
145 | }; | |
146 | ||
abe02543 SG |
147 | /* Driver counted stats */ |
148 | struct otx2_drv_stats { | |
149 | atomic_t rx_fcs_errs; | |
150 | atomic_t rx_oversize_errs; | |
151 | atomic_t rx_undersize_errs; | |
152 | atomic_t rx_csum_errs; | |
153 | atomic_t rx_len_errs; | |
154 | atomic_t rx_other_errs; | |
155 | }; | |
156 | ||
5a6d7c9d SG |
157 | struct mbox { |
158 | struct otx2_mbox mbox; | |
159 | struct work_struct mbox_wrk; | |
160 | struct otx2_mbox mbox_up; | |
161 | struct work_struct mbox_up_wrk; | |
162 | struct otx2_nic *pfvf; | |
163 | void *bbuf_base; /* Bounce buffer for mbox memory */ | |
164 | struct mutex lock; /* serialize mailbox access */ | |
165 | int num_msgs; /* mbox number of messages */ | |
166 | int up_num_msgs; /* mbox_up number of messages */ | |
167 | }; | |
16547577 SG |
168 | |
169 | struct otx2_hw { | |
170 | struct pci_dev *pdev; | |
85069e95 | 171 | struct otx2_rss_info rss_info; |
16547577 SG |
172 | u16 rx_queues; |
173 | u16 tx_queues; | |
174 | u16 max_queues; | |
05fcc9e0 | 175 | u16 pool_cnt; |
caa2da34 SG |
176 | u16 rqpool_cnt; |
177 | u16 sqpool_cnt; | |
05fcc9e0 SG |
178 | |
179 | /* NPA */ | |
180 | u32 stack_pg_ptrs; /* No of ptrs per stack page */ | |
181 | u32 stack_pg_bytes; /* Size of stack page */ | |
182 | u16 sqb_size; | |
183 | ||
caa2da34 SG |
184 | /* NIX */ |
185 | u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; | |
2ca89a2c | 186 | u16 matchall_ipolicer; |
c39830a4 | 187 | u32 dwrr_mtu; |
caa2da34 SG |
188 | |
189 | /* HW settings, coalescing etc */ | |
05fcc9e0 SG |
190 | u16 rx_chan_base; |
191 | u16 tx_chan_base; | |
04a21ef3 SG |
192 | u16 cq_qcount_wait; |
193 | u16 cq_ecount_wait; | |
caa2da34 | 194 | u16 rq_skid; |
04a21ef3 | 195 | u8 cq_time_wait; |
5a6d7c9d | 196 | |
dc1a9bf2 | 197 | /* Segmentation */ |
86d74760 SG |
198 | u8 lso_tsov4_idx; |
199 | u8 lso_tsov6_idx; | |
dc1a9bf2 SG |
200 | u8 lso_udpv4_idx; |
201 | u8 lso_udpv6_idx; | |
86d74760 | 202 | |
e7938365 SG |
203 | /* RSS */ |
204 | u8 flowkey_alg_idx; | |
205 | ||
5a6d7c9d | 206 | /* MSI-X */ |
04a21ef3 | 207 | u8 cint_cnt; /* CQ interrupt count */ |
05fcc9e0 SG |
208 | u16 npa_msixoff; /* Offset of NPA vectors */ |
209 | u16 nix_msixoff; /* Offset of NIX vectors */ | |
5a6d7c9d SG |
210 | char *irq_name; |
211 | cpumask_var_t *affinity_mask; | |
abe02543 SG |
212 | |
213 | /* Stats */ | |
e239d0c7 | 214 | struct otx2_dev_stats dev_stats; |
abe02543 | 215 | struct otx2_drv_stats drv_stats; |
d45d8979 CJ |
216 | u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; |
217 | u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; | |
d0cf9503 CJ |
218 | u64 cgx_fec_corr_blks; |
219 | u64 cgx_fec_uncorr_blks; | |
8bcf5ced SS |
220 | u8 cgx_links; /* No. of CGX links present in HW */ |
221 | u8 lbk_links; /* No. of LBK links present in HW */ | |
039190bb | 222 | u8 tx_link; /* Transmit channel link number */ |
c7766260 DC |
223 | #define HW_TSO 0 |
224 | #define CN10K_MBOX 1 | |
225 | #define CN10K_LMTST 2 | |
facede82 | 226 | unsigned long cap_flag; |
6e8ad438 G |
227 | |
228 | #define LMT_LINE_SIZE 128 | |
5c051207 G |
229 | #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ |
230 | u64 *lmt_base; | |
ef6c8da7 | 231 | struct otx2_lmt_info __percpu *lmt_info; |
16547577 SG |
232 | }; |
233 | ||
b1dc2040 HK |
234 | enum vfperm { |
235 | OTX2_RESET_VF_PERM, | |
236 | OTX2_TRUSTED_VF, | |
237 | }; | |
238 | ||
ad513ed9 TD |
239 | struct otx2_vf_config { |
240 | struct otx2_nic *pf; | |
241 | struct delayed_work link_event_work; | |
242 | bool intf_down; /* interface was either configured or not */ | |
f0c2982a NM |
243 | u8 mac[ETH_ALEN]; |
244 | u16 vlan; | |
245 | int tx_vtag_idx; | |
b1dc2040 | 246 | bool trusted; |
ad513ed9 TD |
247 | }; |
248 | ||
547d20f1 G |
249 | struct flr_work { |
250 | struct work_struct work; | |
251 | struct otx2_nic *pf; | |
252 | }; | |
253 | ||
4ff7d148 G |
254 | struct refill_work { |
255 | struct delayed_work pool_refill_work; | |
256 | struct otx2_nic *pf; | |
257 | }; | |
258 | ||
c9c12d33 AM |
259 | struct otx2_ptp { |
260 | struct ptp_clock_info ptp_info; | |
261 | struct ptp_clock *ptp_clock; | |
262 | struct otx2_nic *nic; | |
263 | ||
264 | struct cyclecounter cycle_counter; | |
265 | struct timecounter time_counter; | |
266 | }; | |
267 | ||
268 | #define OTX2_HW_TIMESTAMP_LEN 8 | |
269 | ||
63ee5157 HK |
270 | struct otx2_mac_table { |
271 | u8 addr[ETH_ALEN]; | |
272 | u16 mcam_entry; | |
273 | bool inuse; | |
274 | }; | |
275 | ||
f0a1913f | 276 | struct otx2_flow_config { |
9917060f SG |
277 | u16 *flow_ent; |
278 | u16 *def_ent; | |
279 | u16 nr_flows; | |
280 | #define OTX2_DEFAULT_FLOWCOUNT 16 | |
281 | #define OTX2_MAX_UNICAST_FLOWS 8 | |
282 | #define OTX2_MAX_VLAN_FLOWS 1 | |
283 | #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT | |
284 | #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ | |
fd9d7859 HK |
285 | OTX2_MAX_UNICAST_FLOWS + \ |
286 | OTX2_MAX_VLAN_FLOWS) | |
9917060f SG |
287 | u16 unicast_offset; |
288 | u16 rx_vlan_offset; | |
289 | u16 vf_vlan_offset; | |
290 | #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ | |
f0c2982a NM |
291 | #define OTX2_VF_VLAN_RX_INDEX 0 |
292 | #define OTX2_VF_VLAN_TX_INDEX 1 | |
2e2a8126 | 293 | u16 max_flows; |
79d2be38 HK |
294 | u8 dmacflt_max_flows; |
295 | u8 *bmap_to_dmacindex; | |
296 | unsigned long dmacflt_bmap; | |
f0a1913f SS |
297 | struct list_head flow_list; |
298 | }; | |
299 | ||
1d4d9e42 NM |
300 | struct otx2_tc_info { |
301 | /* hash table to store TC offloaded flows */ | |
302 | struct rhashtable flow_table; | |
303 | struct rhashtable_params flow_ht_params; | |
2e2a8126 | 304 | unsigned long *tc_entries_bitmap; |
1d4d9e42 NM |
305 | }; |
306 | ||
4c236d5d G |
307 | struct dev_hw_ops { |
308 | int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); | |
309 | void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, | |
310 | int size, int qidx); | |
311 | void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); | |
312 | void (*aura_freeptr)(void *dev, int aura, u64 buf); | |
313 | }; | |
314 | ||
16547577 SG |
315 | struct otx2_nic { |
316 | void __iomem *reg_base; | |
317 | struct net_device *netdev; | |
4c236d5d | 318 | struct dev_hw_ops *hw_ops; |
caa2da34 | 319 | void *iommu_domain; |
34bfe0eb | 320 | u16 max_frs; |
caa2da34 | 321 | u16 rbsize; /* Receive buffer size */ |
16547577 | 322 | |
c9c12d33 AM |
323 | #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) |
324 | #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) | |
50fe6c02 | 325 | #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) |
f0a1913f SS |
326 | #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) |
327 | #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) | |
63ee5157 | 328 | #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) |
fd9d7859 | 329 | #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) |
f0c2982a NM |
330 | #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) |
331 | #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) | |
75f36270 G |
332 | #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) |
333 | #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) | |
1d4d9e42 | 334 | #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) |
e638a83f | 335 | #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) |
2ca89a2c | 336 | #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) |
79d2be38 | 337 | #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) |
50fe6c02 LC |
338 | u64 flags; |
339 | ||
05fcc9e0 | 340 | struct otx2_qset qset; |
16547577 SG |
341 | struct otx2_hw hw; |
342 | struct pci_dev *pdev; | |
343 | struct device *dev; | |
5a6d7c9d SG |
344 | |
345 | /* Mbox */ | |
346 | struct mbox mbox; | |
d424b6c0 | 347 | struct mbox *mbox_pfvf; |
5a6d7c9d | 348 | struct workqueue_struct *mbox_wq; |
d424b6c0 | 349 | struct workqueue_struct *mbox_pfvf_wq; |
5a6d7c9d | 350 | |
d424b6c0 | 351 | u8 total_vfs; |
5a6d7c9d | 352 | u16 pcifunc; /* RVU PF_FUNC */ |
75f36270 | 353 | u16 bpid[NIX_MAX_BPID_CHAN]; |
ad513ed9 | 354 | struct otx2_vf_config *vf_configs; |
50fe6c02 | 355 | struct cgx_link_user_info linfo; |
caa2da34 | 356 | |
2e2a8126 SG |
357 | /* NPC MCAM */ |
358 | struct otx2_flow_config *flow_cfg; | |
359 | struct otx2_mac_table *mac_table; | |
360 | struct otx2_tc_info tc_info; | |
361 | ||
4ff7d148 G |
362 | u64 reset_count; |
363 | struct work_struct reset_task; | |
547d20f1 G |
364 | struct workqueue_struct *flr_wq; |
365 | struct flr_work *flr_wrk; | |
4ff7d148 | 366 | struct refill_work *refill_wrk; |
e99b7c84 SG |
367 | struct workqueue_struct *otx2_wq; |
368 | struct work_struct rx_mode_work; | |
4ff7d148 | 369 | |
6e92d71b SG |
370 | /* Ethtool stuff */ |
371 | u32 msg_enable; | |
372 | ||
caa2da34 SG |
373 | /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ |
374 | int nix_blkaddr; | |
6e8ad438 | 375 | /* LMTST Lines info */ |
5c051207 | 376 | struct qmem *dync_lmt; |
6e8ad438 | 377 | u16 tot_lmt_lines; |
5c051207 | 378 | u16 npa_lmt_lines; |
6e8ad438 | 379 | u32 nix_lmt_size; |
c9c12d33 AM |
380 | |
381 | struct otx2_ptp *ptp; | |
382 | struct hwtstamp_config tstamp; | |
f0a1913f | 383 | |
68fbff68 | 384 | unsigned long rq_bmap; |
2da48943 SG |
385 | |
386 | /* Devlink */ | |
387 | struct otx2_devlink *dl; | |
16547577 SG |
388 | }; |
389 | ||
3184fb5b TD |
390 | static inline bool is_otx2_lbkvf(struct pci_dev *pdev) |
391 | { | |
392 | return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; | |
393 | } | |
394 | ||
04a21ef3 SG |
395 | static inline bool is_96xx_A0(struct pci_dev *pdev) |
396 | { | |
397 | return (pdev->revision == 0x00) && | |
398 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); | |
399 | } | |
400 | ||
401 | static inline bool is_96xx_B0(struct pci_dev *pdev) | |
402 | { | |
403 | return (pdev->revision == 0x01) && | |
404 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); | |
405 | } | |
406 | ||
facede82 SS |
407 | /* REVID for PCIe devices. |
408 | * Bits 0..1: minor pass, bit 3..2: major pass | |
409 | * bits 7..4: midr id | |
410 | */ | |
411 | #define PCI_REVISION_ID_96XX 0x00 | |
412 | #define PCI_REVISION_ID_95XX 0x10 | |
ef6c8da7 | 413 | #define PCI_REVISION_ID_95XXN 0x20 |
facede82 SS |
414 | #define PCI_REVISION_ID_98XX 0x30 |
415 | #define PCI_REVISION_ID_95XXMM 0x40 | |
ef6c8da7 | 416 | #define PCI_REVISION_ID_95XXO 0xE0 |
facede82 SS |
417 | |
418 | static inline bool is_dev_otx2(struct pci_dev *pdev) | |
419 | { | |
420 | u8 midr = pdev->revision & 0xF0; | |
421 | ||
422 | return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || | |
ef6c8da7 G |
423 | midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || |
424 | midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); | |
facede82 SS |
425 | } |
426 | ||
04a21ef3 SG |
427 | static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) |
428 | { | |
86d74760 SG |
429 | struct otx2_hw *hw = &pfvf->hw; |
430 | ||
04a21ef3 SG |
431 | pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; |
432 | pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; | |
433 | pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; | |
434 | ||
facede82 | 435 | __set_bit(HW_TSO, &hw->cap_flag); |
86d74760 | 436 | |
04a21ef3 | 437 | if (is_96xx_A0(pfvf->pdev)) { |
facede82 | 438 | __clear_bit(HW_TSO, &hw->cap_flag); |
86d74760 | 439 | |
04a21ef3 SG |
440 | /* Time based irq coalescing is not supported */ |
441 | pfvf->hw.cq_qcount_wait = 0x0; | |
442 | ||
443 | /* Due to HW issue previous silicons required minimum | |
444 | * 600 unused CQE to avoid CQ overflow. | |
445 | */ | |
446 | pfvf->hw.rq_skid = 600; | |
447 | pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); | |
448 | } | |
786621d2 G |
449 | if (is_96xx_B0(pfvf->pdev)) |
450 | __clear_bit(HW_TSO, &hw->cap_flag); | |
451 | ||
6e8ad438 | 452 | if (!is_dev_otx2(pfvf->pdev)) { |
facede82 | 453 | __set_bit(CN10K_MBOX, &hw->cap_flag); |
6e8ad438 G |
454 | __set_bit(CN10K_LMTST, &hw->cap_flag); |
455 | } | |
04a21ef3 SG |
456 | } |
457 | ||
16547577 SG |
458 | /* Register read/write APIs */ |
459 | static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) | |
460 | { | |
461 | u64 blkaddr; | |
462 | ||
463 | switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { | |
464 | case BLKTYPE_NIX: | |
caa2da34 | 465 | blkaddr = nic->nix_blkaddr; |
16547577 SG |
466 | break; |
467 | case BLKTYPE_NPA: | |
468 | blkaddr = BLKADDR_NPA; | |
469 | break; | |
470 | default: | |
471 | blkaddr = BLKADDR_RVUM; | |
472 | break; | |
ae23aae2 | 473 | } |
16547577 SG |
474 | |
475 | offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); | |
476 | offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); | |
477 | ||
478 | return nic->reg_base + offset; | |
479 | } | |
480 | ||
481 | static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) | |
482 | { | |
483 | void __iomem *addr = otx2_get_regaddr(nic, offset); | |
484 | ||
485 | writeq(val, addr); | |
486 | } | |
487 | ||
488 | static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) | |
489 | { | |
490 | void __iomem *addr = otx2_get_regaddr(nic, offset); | |
491 | ||
492 | return readq(addr); | |
493 | } | |
494 | ||
5a6d7c9d SG |
495 | /* Mbox bounce buffer APIs */ |
496 | static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) | |
497 | { | |
498 | struct otx2_mbox *otx2_mbox; | |
499 | struct otx2_mbox_dev *mdev; | |
500 | ||
501 | mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); | |
502 | if (!mbox->bbuf_base) | |
503 | return -ENOMEM; | |
504 | ||
505 | /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF | |
506 | * prepare all mbox messages in bounce buffer instead of directly | |
507 | * in hw mbox memory. | |
508 | */ | |
509 | otx2_mbox = &mbox->mbox; | |
510 | mdev = &otx2_mbox->dev[0]; | |
511 | mdev->mbase = mbox->bbuf_base; | |
512 | ||
513 | otx2_mbox = &mbox->mbox_up; | |
514 | mdev = &otx2_mbox->dev[0]; | |
515 | mdev->mbase = mbox->bbuf_base; | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) | |
520 | { | |
521 | u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); | |
522 | void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); | |
523 | struct otx2_mbox_dev *mdev = &mbox->dev[devid]; | |
524 | struct mbox_hdr *hdr; | |
525 | u64 msg_size; | |
526 | ||
527 | if (mdev->mbase == hw_mbase) | |
528 | return; | |
529 | ||
530 | hdr = hw_mbase + mbox->rx_start; | |
531 | msg_size = hdr->msg_size; | |
532 | ||
533 | if (msg_size > mbox->rx_size - msgs_offset) | |
534 | msg_size = mbox->rx_size - msgs_offset; | |
535 | ||
536 | /* Copy mbox messages from mbox memory to bounce buffer */ | |
537 | memcpy(mdev->mbase + mbox->rx_start, | |
538 | hw_mbase + mbox->rx_start, msg_size + msgs_offset); | |
539 | } | |
540 | ||
caa2da34 SG |
541 | /* With the absence of API for 128-bit IO memory access for arm64, |
542 | * implement required operations at place. | |
543 | */ | |
544 | #if defined(CONFIG_ARM64) | |
545 | static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) | |
546 | { | |
547 | __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" | |
548 | ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); | |
549 | } | |
550 | ||
551 | static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) | |
552 | { | |
553 | u64 result; | |
554 | ||
555 | __asm__ volatile(".cpu generic+lse\n" | |
556 | "ldadd %x[i], %x[r], [%[b]]" | |
557 | : [r]"=r"(result), "+m"(*ptr) | |
558 | : [i]"r"(incr), [b]"r"(ptr) | |
559 | : "memory"); | |
560 | return result; | |
561 | } | |
562 | ||
563 | #else | |
4c236d5d | 564 | #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) |
caa2da34 SG |
565 | #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) |
566 | #endif | |
567 | ||
4c236d5d | 568 | static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, |
ef6c8da7 | 569 | u64 *ptrs, u64 num_ptrs) |
4c236d5d | 570 | { |
ef6c8da7 | 571 | struct otx2_lmt_info *lmt_info; |
4c236d5d G |
572 | u64 size = 0, count_eot = 0; |
573 | u64 tar_addr, val = 0; | |
574 | ||
ef6c8da7 | 575 | lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); |
4c236d5d G |
576 | tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); |
577 | /* LMTID is same as AURA Id */ | |
ef6c8da7 | 578 | val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); |
4c236d5d G |
579 | /* Set if [127:64] of last 128bit word has a valid pointer */ |
580 | count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; | |
581 | /* Set AURA ID to free pointer */ | |
582 | ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); | |
583 | /* Target address for LMTST flush tells HW how many 128bit | |
584 | * words are valid from NPA_LF_AURA_BATCH_FREE0. | |
585 | * | |
586 | * tar_addr[6:4] is LMTST size-1 in units of 128b. | |
587 | */ | |
588 | if (num_ptrs > 2) { | |
589 | size = (sizeof(u64) * num_ptrs) / 16; | |
590 | if (!count_eot) | |
591 | size++; | |
592 | tar_addr |= ((size - 1) & 0x7) << 4; | |
593 | } | |
9ce72ae8 | 594 | dma_wmb(); |
ef6c8da7 | 595 | memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); |
4c236d5d G |
596 | /* Perform LMTST flush */ |
597 | cn10k_lmt_flush(val, tar_addr); | |
598 | } | |
599 | ||
600 | static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) | |
601 | { | |
602 | struct otx2_nic *pfvf = dev; | |
4c236d5d G |
603 | u64 ptrs[2]; |
604 | ||
4c236d5d | 605 | ptrs[1] = buf; |
ef6c8da7 G |
606 | /* Free only one buffer at time during init and teardown */ |
607 | __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); | |
4c236d5d G |
608 | } |
609 | ||
caa2da34 SG |
610 | /* Alloc pointer from pool/aura */ |
611 | static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) | |
612 | { | |
613 | u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, | |
614 | NPA_LF_AURA_OP_ALLOCX(0)); | |
615 | u64 incr = (u64)aura | BIT_ULL(63); | |
616 | ||
617 | return otx2_atomic64_add(incr, ptr); | |
618 | } | |
619 | ||
620 | /* Free pointer to a pool/aura */ | |
4c236d5d | 621 | static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) |
caa2da34 | 622 | { |
4c236d5d G |
623 | struct otx2_nic *pfvf = dev; |
624 | void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); | |
625 | ||
626 | otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); | |
caa2da34 SG |
627 | } |
628 | ||
caa2da34 SG |
629 | static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) |
630 | { | |
631 | if (type == AURA_NIX_SQ) | |
632 | return pfvf->hw.rqpool_cnt + idx; | |
633 | ||
634 | /* AURA_NIX_RQ */ | |
635 | return idx; | |
636 | } | |
637 | ||
5a6d7c9d SG |
638 | /* Mbox APIs */ |
639 | static inline int otx2_sync_mbox_msg(struct mbox *mbox) | |
640 | { | |
641 | int err; | |
642 | ||
643 | if (!otx2_mbox_nonempty(&mbox->mbox, 0)) | |
644 | return 0; | |
645 | otx2_mbox_msg_send(&mbox->mbox, 0); | |
646 | err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); | |
647 | if (err) | |
648 | return err; | |
649 | ||
650 | return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); | |
651 | } | |
652 | ||
653 | static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) | |
654 | { | |
655 | int err; | |
656 | ||
657 | if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) | |
658 | return 0; | |
659 | otx2_mbox_msg_send(&mbox->mbox_up, devid); | |
660 | err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); | |
661 | if (err) | |
662 | return err; | |
663 | ||
664 | return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); | |
665 | } | |
666 | ||
667 | /* Use this API to send mbox msgs in atomic context | |
668 | * where sleeping is not allowed | |
669 | */ | |
670 | static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) | |
671 | { | |
672 | int err; | |
673 | ||
674 | if (!otx2_mbox_nonempty(&mbox->mbox, 0)) | |
675 | return 0; | |
676 | otx2_mbox_msg_send(&mbox->mbox, 0); | |
677 | err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); | |
678 | if (err) | |
679 | return err; | |
680 | ||
681 | return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); | |
682 | } | |
683 | ||
684 | #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ | |
685 | static struct _req_type __maybe_unused \ | |
686 | *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ | |
687 | { \ | |
688 | struct _req_type *req; \ | |
689 | \ | |
690 | req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ | |
691 | &mbox->mbox, 0, sizeof(struct _req_type), \ | |
692 | sizeof(struct _rsp_type)); \ | |
693 | if (!req) \ | |
694 | return NULL; \ | |
695 | req->hdr.sig = OTX2_MBOX_REQ_SIG; \ | |
696 | req->hdr.id = _id; \ | |
31a97460 | 697 | trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ |
5a6d7c9d SG |
698 | return req; \ |
699 | } | |
700 | ||
701 | MBOX_MESSAGES | |
702 | #undef M | |
703 | ||
704 | #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ | |
705 | int \ | |
706 | otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ | |
707 | struct _req_type *req, \ | |
708 | struct _rsp_type *rsp); \ | |
709 | ||
710 | MBOX_UP_CGX_MESSAGES | |
711 | #undef M | |
712 | ||
4ff7d148 G |
713 | /* Time to wait before watchdog kicks off */ |
714 | #define OTX2_TX_TIMEOUT (100 * HZ) | |
715 | ||
5a6d7c9d SG |
716 | #define RVU_PFVF_PF_SHIFT 10 |
717 | #define RVU_PFVF_PF_MASK 0x3F | |
718 | #define RVU_PFVF_FUNC_SHIFT 0 | |
719 | #define RVU_PFVF_FUNC_MASK 0x3FF | |
720 | ||
3cffaed2 RB |
721 | static inline bool is_otx2_vf(u16 pcifunc) |
722 | { | |
723 | return !!(pcifunc & RVU_PFVF_FUNC_MASK); | |
724 | } | |
725 | ||
04a21ef3 SG |
726 | static inline int rvu_get_pf(u16 pcifunc) |
727 | { | |
728 | return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; | |
729 | } | |
730 | ||
caa2da34 SG |
731 | static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, |
732 | struct page *page, | |
733 | size_t offset, size_t size, | |
734 | enum dma_data_direction dir) | |
735 | { | |
736 | dma_addr_t iova; | |
737 | ||
738 | iova = dma_map_page_attrs(pfvf->dev, page, | |
739 | offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); | |
740 | if (unlikely(dma_mapping_error(pfvf->dev, iova))) | |
741 | return (dma_addr_t)NULL; | |
742 | return iova; | |
743 | } | |
744 | ||
745 | static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, | |
746 | dma_addr_t addr, size_t size, | |
747 | enum dma_data_direction dir) | |
748 | { | |
749 | dma_unmap_page_attrs(pfvf->dev, addr, size, | |
750 | dir, DMA_ATTR_SKIP_CPU_SYNC); | |
751 | } | |
752 | ||
04a21ef3 SG |
753 | /* MSI-X APIs */ |
754 | void otx2_free_cints(struct otx2_nic *pfvf, int n); | |
755 | void otx2_set_cints_affinity(struct otx2_nic *pfvf); | |
34bfe0eb SG |
756 | int otx2_set_mac_address(struct net_device *netdev, void *p); |
757 | int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); | |
4ff7d148 | 758 | void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); |
34bfe0eb | 759 | void otx2_get_mac_from_af(struct net_device *netdev); |
04a21ef3 | 760 | void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); |
75f36270 | 761 | int otx2_config_pause_frm(struct otx2_nic *pfvf); |
dc1a9bf2 | 762 | void otx2_setup_segmentation(struct otx2_nic *pfvf); |
04a21ef3 | 763 | |
05fcc9e0 SG |
764 | /* RVU block related APIs */ |
765 | int otx2_attach_npa_nix(struct otx2_nic *pfvf); | |
766 | int otx2_detach_resources(struct mbox *mbox); | |
767 | int otx2_config_npa(struct otx2_nic *pfvf); | |
caa2da34 SG |
768 | int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); |
769 | int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); | |
770 | void otx2_aura_pool_free(struct otx2_nic *pfvf); | |
771 | void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); | |
772 | void otx2_sq_free_sqbs(struct otx2_nic *pfvf); | |
05fcc9e0 | 773 | int otx2_config_nix(struct otx2_nic *pfvf); |
caa2da34 SG |
774 | int otx2_config_nix_queues(struct otx2_nic *pfvf); |
775 | int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); | |
776 | int otx2_txsch_alloc(struct otx2_nic *pfvf); | |
777 | int otx2_txschq_stop(struct otx2_nic *pfvf); | |
778 | void otx2_sqb_flush(struct otx2_nic *pfvf); | |
1fb3ca76 KH |
779 | int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, |
780 | dma_addr_t *dma); | |
50fe6c02 | 781 | int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); |
caa2da34 | 782 | void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); |
75f36270 | 783 | int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); |
abe02543 | 784 | void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); |
3ca6c4c8 | 785 | void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); |
4c236d5d G |
786 | int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); |
787 | int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); | |
788 | int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, | |
789 | dma_addr_t *dma); | |
05fcc9e0 | 790 | |
85069e95 SG |
791 | /* RSS configuration APIs*/ |
792 | int otx2_rss_init(struct otx2_nic *pfvf); | |
6e92d71b SG |
793 | int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); |
794 | void otx2_set_rss_key(struct otx2_nic *pfvf); | |
81a43620 | 795 | int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); |
85069e95 | 796 | |
05fcc9e0 SG |
797 | /* Mbox handlers */ |
798 | void mbox_handler_msix_offset(struct otx2_nic *pfvf, | |
799 | struct msix_offset_rsp *rsp); | |
800 | void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, | |
801 | struct npa_lf_alloc_rsp *rsp); | |
802 | void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, | |
803 | struct nix_lf_alloc_rsp *rsp); | |
caa2da34 SG |
804 | void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, |
805 | struct nix_txsch_alloc_rsp *rsp); | |
d45d8979 CJ |
806 | void mbox_handler_cgx_stats(struct otx2_nic *pfvf, |
807 | struct cgx_stats_rsp *rsp); | |
d0cf9503 CJ |
808 | void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, |
809 | struct cgx_fec_stats_rsp *rsp); | |
810 | void otx2_set_fec_stats_count(struct otx2_nic *pfvf); | |
75f36270 G |
811 | void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, |
812 | struct nix_bp_cfg_rsp *rsp); | |
34bfe0eb | 813 | |
e239d0c7 G |
814 | /* Device stats APIs */ |
815 | void otx2_get_dev_stats(struct otx2_nic *pfvf); | |
816 | void otx2_get_stats64(struct net_device *netdev, | |
817 | struct rtnl_link_stats64 *stats); | |
d45d8979 | 818 | void otx2_update_lmac_stats(struct otx2_nic *pfvf); |
d0cf9503 | 819 | void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); |
d45d8979 CJ |
820 | int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); |
821 | int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); | |
822 | void otx2_set_ethtool_ops(struct net_device *netdev); | |
05c22b54 | 823 | void otx2vf_set_ethtool_ops(struct net_device *netdev); |
e239d0c7 | 824 | |
34bfe0eb SG |
825 | int otx2_open(struct net_device *netdev); |
826 | int otx2_stop(struct net_device *netdev); | |
d45d8979 CJ |
827 | int otx2_set_real_num_queues(struct net_device *netdev, |
828 | int tx_queues, int rx_queues); | |
f0a1913f SS |
829 | /* MCAM filter related APIs */ |
830 | int otx2_mcam_flow_init(struct otx2_nic *pf); | |
3cffaed2 | 831 | int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); |
2da48943 | 832 | int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); |
f0a1913f SS |
833 | void otx2_mcam_flow_del(struct otx2_nic *pf); |
834 | int otx2_destroy_ntuple_flows(struct otx2_nic *pf); | |
835 | int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); | |
836 | int otx2_get_flow(struct otx2_nic *pfvf, | |
837 | struct ethtool_rxnfc *nfc, u32 location); | |
838 | int otx2_get_all_flows(struct otx2_nic *pfvf, | |
839 | struct ethtool_rxnfc *nfc, u32 *rule_locs); | |
840 | int otx2_add_flow(struct otx2_nic *pfvf, | |
81a43620 | 841 | struct ethtool_rxnfc *nfc); |
f0a1913f | 842 | int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); |
3cffaed2 | 843 | int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); |
81a43620 | 844 | void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); |
63ee5157 HK |
845 | int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); |
846 | int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); | |
fd9d7859 HK |
847 | int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); |
848 | int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); | |
ab58a416 | 849 | u16 otx2_get_max_mtu(struct otx2_nic *pfvf); |
1d4d9e42 NM |
850 | /* tc support */ |
851 | int otx2_init_tc(struct otx2_nic *nic); | |
852 | void otx2_shutdown_tc(struct otx2_nic *nic); | |
853 | int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, | |
854 | void *type_data); | |
2da48943 | 855 | int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic); |
79d2be38 HK |
856 | /* CGX/RPM DMAC filters support */ |
857 | int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); | |
858 | int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u8 bit_pos); | |
859 | int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u8 bit_pos); | |
860 | int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u8 bit_pos); | |
861 | void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); | |
862 | void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); | |
16547577 | 863 | #endif /* OTX2_COMMON_H */ |