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octeontx2-pf: Fix error return code in otx2_probe()
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / marvell / octeontx2 / nic / otx2_pf.c
CommitLineData
16547577
SG		 1// SPDX-License-Identifier: GPL-2.0
2/* Marvell OcteonTx2 RVU Physcial Function ethernet driver
3 *
4 * Copyright (C) 2020 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/pci.h>
14#include <linux/etherdevice.h>
15#include <linux/of.h>
16#include <linux/if_vlan.h>
17#include <linux/iommu.h>
18#include <net/ip.h>
19
caa2da34 20#include "otx2_reg.h"
16547577 21#include "otx2_common.h"
caa2da34
SG		 22#include "otx2_txrx.h"
23#include "otx2_struct.h"
16547577
SG		 24
25#define DRV_NAME "octeontx2-nicpf"
26#define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver"
16547577
SG		 27
28/* Supported devices */
29static const struct pci_device_id otx2_pf_id_table[] = {
30 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
31 { 0, } /* end of table */
32};
33
fc992e33 34MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
16547577
SG		 35MODULE_DESCRIPTION(DRV_STRING);
36MODULE_LICENSE("GPL v2");
16547577
SG		 37MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
38
5a6d7c9d
SG		 39enum {
40 TYPE_PFAF,
41 TYPE_PFVF,
42};
43
34bfe0eb
SG		 44static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
45{
46 bool if_up = netif_running(netdev);
47 int err = 0;
48
49 if (if_up)
50 otx2_stop(netdev);
51
52 netdev_info(netdev, "Changing MTU from %d to %d\n",
53 netdev->mtu, new_mtu);
54 netdev->mtu = new_mtu;
55
56 if (if_up)
57 err = otx2_open(netdev);
58
59 return err;
60}
61
547d20f1
G		 62static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
63{
64 int irq, vfs = pf->total_vfs;
65
66 /* Disable VFs ME interrupts */
67 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
68 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
69 free_irq(irq, pf);
70
71 /* Disable VFs FLR interrupts */
72 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
74 free_irq(irq, pf);
75
76 if (vfs <= 64)
77 return;
78
79 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
80 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
81 free_irq(irq, pf);
82
83 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
85 free_irq(irq, pf);
86}
87
88static void otx2_flr_wq_destroy(struct otx2_nic *pf)
89{
90 if (!pf->flr_wq)
91 return;
92 destroy_workqueue(pf->flr_wq);
93 pf->flr_wq = NULL;
94 devm_kfree(pf->dev, pf->flr_wrk);
95}
96
97static void otx2_flr_handler(struct work_struct *work)
98{
99 struct flr_work *flrwork = container_of(work, struct flr_work, work);
100 struct otx2_nic *pf = flrwork->pf;
4c3212f5 101 struct mbox *mbox = &pf->mbox;
547d20f1
G		 102 struct msg_req *req;
103 int vf, reg = 0;
104
105 vf = flrwork - pf->flr_wrk;
106
4c3212f5
SG		 107 mutex_lock(&mbox->lock);
108 req = otx2_mbox_alloc_msg_vf_flr(mbox);
547d20f1 109 if (!req) {
4c3212f5 110 mutex_unlock(&mbox->lock);
547d20f1
G		 111 return;
112 }
113 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
114 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
115
116 if (!otx2_sync_mbox_msg(&pf->mbox)) {
117 if (vf >= 64) {
118 reg = 1;
119 vf = vf - 64;
120 }
121 /* clear transcation pending bit */
122 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
123 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
124 }
125
4c3212f5 126 mutex_unlock(&mbox->lock);
547d20f1
G		 127}
128
129static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
130{
131 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
132 int reg, dev, vf, start_vf, num_reg = 1;
133 u64 intr;
134
135 if (pf->total_vfs > 64)
136 num_reg = 2;
137
138 for (reg = 0; reg < num_reg; reg++) {
139 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
140 if (!intr)
141 continue;
142 start_vf = 64 * reg;
143 for (vf = 0; vf < 64; vf++) {
144 if (!(intr & BIT_ULL(vf)))
145 continue;
146 dev = vf + start_vf;
147 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
148 /* Clear interrupt */
149 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
150 /* Disable the interrupt */
151 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
152 BIT_ULL(vf));
153 }
154 }
155 return IRQ_HANDLED;
156}
157
158static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
159{
160 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
161 int vf, reg, num_reg = 1;
162 u64 intr;
163
164 if (pf->total_vfs > 64)
165 num_reg = 2;
166
167 for (reg = 0; reg < num_reg; reg++) {
168 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
169 if (!intr)
170 continue;
171 for (vf = 0; vf < 64; vf++) {
172 if (!(intr & BIT_ULL(vf)))
173 continue;
174 /* clear trpend bit */
175 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
176 /* clear interrupt */
177 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
178 }
179 }
180 return IRQ_HANDLED;
181}
182
183static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
184{
185 struct otx2_hw *hw = &pf->hw;
186 char *irq_name;
187 int ret;
188
189 /* Register ME interrupt handler*/
190 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
191 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
192 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
193 otx2_pf_me_intr_handler, 0, irq_name, pf);
194 if (ret) {
195 dev_err(pf->dev,
196 "RVUPF: IRQ registration failed for ME0\n");
197 }
198
199 /* Register FLR interrupt handler */
200 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
201 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
202 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
203 otx2_pf_flr_intr_handler, 0, irq_name, pf);
204 if (ret) {
205 dev_err(pf->dev,
206 "RVUPF: IRQ registration failed for FLR0\n");
207 return ret;
208 }
209
210 if (numvfs > 64) {
211 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
212 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
213 rvu_get_pf(pf->pcifunc));
214 ret = request_irq(pci_irq_vector
215 (pf->pdev, RVU_PF_INT_VEC_VFME1),
216 otx2_pf_me_intr_handler, 0, irq_name, pf);
217 if (ret) {
218 dev_err(pf->dev,
219 "RVUPF: IRQ registration failed for ME1\n");
220 }
221 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
222 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
223 rvu_get_pf(pf->pcifunc));
224 ret = request_irq(pci_irq_vector
225 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
226 otx2_pf_flr_intr_handler, 0, irq_name, pf);
227 if (ret) {
228 dev_err(pf->dev,
229 "RVUPF: IRQ registration failed for FLR1\n");
230 return ret;
231 }
232 }
233
234 /* Enable ME interrupt for all VFs*/
235 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
236 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
237
238 /* Enable FLR interrupt for all VFs*/
239 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
240 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
241
242 if (numvfs > 64) {
243 numvfs -= 64;
244
245 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
246 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
247 INTR_MASK(numvfs));
248
249 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
250 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
251 INTR_MASK(numvfs));
252 }
253 return 0;
254}
255
256static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
257{
258 int vf;
259
260 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq",
261 WQ_UNBOUND | WQ_HIGHPRI, 1);
262 if (!pf->flr_wq)
263 return -ENOMEM;
264
265 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
266 sizeof(struct flr_work), GFP_KERNEL);
267 if (!pf->flr_wrk) {
268 destroy_workqueue(pf->flr_wq);
269 return -ENOMEM;
270 }
271
272 for (vf = 0; vf < num_vfs; vf++) {
273 pf->flr_wrk[vf].pf = pf;
274 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
275 }
276
277 return 0;
278}
279
5a6d7c9d
SG		 280static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
281 int first, int mdevs, u64 intr, int type)
282{
283 struct otx2_mbox_dev *mdev;
284 struct otx2_mbox *mbox;
285 struct mbox_hdr *hdr;
286 int i;
287
288 for (i = first; i < mdevs; i++) {
289 /* start from 0 */
290 if (!(intr & BIT_ULL(i - first)))
291 continue;
292
293 mbox = &mw->mbox;
294 mdev = &mbox->dev[i];
295 if (type == TYPE_PFAF)
296 otx2_sync_mbox_bbuf(mbox, i);
297 hdr = mdev->mbase + mbox->rx_start;
298 /* The hdr->num_msgs is set to zero immediately in the interrupt
299 * handler to ensure that it holds a correct value next time
300 * when the interrupt handler is called.
301 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
302 * pf>mbox.up_num_msgs holds the data for use in
303 * pfaf_mbox_up_handler.
304 */
305 if (hdr->num_msgs) {
306 mw[i].num_msgs = hdr->num_msgs;
307 hdr->num_msgs = 0;
308 if (type == TYPE_PFAF)
309 memset(mbox->hwbase + mbox->rx_start, 0,
310 ALIGN(sizeof(struct mbox_hdr),
311 sizeof(u64)));
312
313 queue_work(mbox_wq, &mw[i].mbox_wrk);
314 }
315
316 mbox = &mw->mbox_up;
317 mdev = &mbox->dev[i];
318 if (type == TYPE_PFAF)
319 otx2_sync_mbox_bbuf(mbox, i);
320 hdr = mdev->mbase + mbox->rx_start;
321 if (hdr->num_msgs) {
322 mw[i].up_num_msgs = hdr->num_msgs;
323 hdr->num_msgs = 0;
324 if (type == TYPE_PFAF)
325 memset(mbox->hwbase + mbox->rx_start, 0,
326 ALIGN(sizeof(struct mbox_hdr),
327 sizeof(u64)));
328
329 queue_work(mbox_wq, &mw[i].mbox_up_wrk);
330 }
331 }
332}
333
d424b6c0
SG		 334static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
335 struct otx2_mbox *pfvf_mbox, void *bbuf_base,
336 int devid)
337{
338 struct otx2_mbox_dev *src_mdev = mdev;
339 int offset;
340
341 /* Msgs are already copied, trigger VF's mbox irq */
342 smp_wmb();
343
344 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
345 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
346
347 /* Restore VF's mbox bounce buffer region address */
348 src_mdev->mbase = bbuf_base;
349}
350
351static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
352 struct otx2_mbox *src_mbox,
353 int dir, int vf, int num_msgs)
354{
355 struct otx2_mbox_dev *src_mdev, *dst_mdev;
356 struct mbox_hdr *mbox_hdr;
357 struct mbox_hdr *req_hdr;
358 struct mbox *dst_mbox;
359 int dst_size, err;
360
361 if (dir == MBOX_DIR_PFAF) {
362 /* Set VF's mailbox memory as PF's bounce buffer memory, so
363 * that explicit copying of VF's msgs to PF=>AF mbox region
364 * and AF=>PF responses to VF's mbox region can be avoided.
365 */
366 src_mdev = &src_mbox->dev[vf];
367 mbox_hdr = src_mbox->hwbase +
368 src_mbox->rx_start + (vf * MBOX_SIZE);
369
370 dst_mbox = &pf->mbox;
371 dst_size = dst_mbox->mbox.tx_size -
372 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
373 /* Check if msgs fit into destination area */
374 if (mbox_hdr->msg_size > dst_size)
375 return -EINVAL;
376
377 dst_mdev = &dst_mbox->mbox.dev[0];
378
4c3212f5 379 mutex_lock(&pf->mbox.lock);
d424b6c0
SG		 380 dst_mdev->mbase = src_mdev->mbase;
381 dst_mdev->msg_size = mbox_hdr->msg_size;
382 dst_mdev->num_msgs = num_msgs;
383 err = otx2_sync_mbox_msg(dst_mbox);
384 if (err) {
385 dev_warn(pf->dev,
386 "AF not responding to VF%d messages\n", vf);
387 /* restore PF mbase and exit */
388 dst_mdev->mbase = pf->mbox.bbuf_base;
4c3212f5 389 mutex_unlock(&pf->mbox.lock);
d424b6c0
SG		 390 return err;
391 }
392 /* At this point, all the VF messages sent to AF are acked
393 * with proper responses and responses are copied to VF
394 * mailbox hence raise interrupt to VF.
395 */
396 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
397 dst_mbox->mbox.rx_start);
398 req_hdr->num_msgs = num_msgs;
399
400 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
401 pf->mbox.bbuf_base, vf);
4c3212f5 402 mutex_unlock(&pf->mbox.lock);
d424b6c0
SG		 403 } else if (dir == MBOX_DIR_PFVF_UP) {
404 src_mdev = &src_mbox->dev[0];
405 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
406 req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
407 src_mbox->rx_start);
408 req_hdr->num_msgs = num_msgs;
409
410 dst_mbox = &pf->mbox_pfvf[0];
411 dst_size = dst_mbox->mbox_up.tx_size -
412 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
413 /* Check if msgs fit into destination area */
414 if (mbox_hdr->msg_size > dst_size)
415 return -EINVAL;
416
417 dst_mdev = &dst_mbox->mbox_up.dev[vf];
418 dst_mdev->mbase = src_mdev->mbase;
419 dst_mdev->msg_size = mbox_hdr->msg_size;
420 dst_mdev->num_msgs = mbox_hdr->num_msgs;
421 err = otx2_sync_mbox_up_msg(dst_mbox, vf);
422 if (err) {
423 dev_warn(pf->dev,
424 "VF%d is not responding to mailbox\n", vf);
425 return err;
426 }
427 } else if (dir == MBOX_DIR_VFPF_UP) {
428 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
429 src_mbox->rx_start);
430 req_hdr->num_msgs = num_msgs;
431 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
432 &pf->mbox.mbox_up,
433 pf->mbox_pfvf[vf].bbuf_base,
434 0);
435 }
436
437 return 0;
438}
439
440static void otx2_pfvf_mbox_handler(struct work_struct *work)
441{
442 struct mbox_msghdr *msg = NULL;
443 int offset, vf_idx, id, err;
444 struct otx2_mbox_dev *mdev;
445 struct mbox_hdr *req_hdr;
446 struct otx2_mbox *mbox;
447 struct mbox *vf_mbox;
448 struct otx2_nic *pf;
449
450 vf_mbox = container_of(work, struct mbox, mbox_wrk);
451 pf = vf_mbox->pfvf;
452 vf_idx = vf_mbox - pf->mbox_pfvf;
453
454 mbox = &pf->mbox_pfvf[0].mbox;
455 mdev = &mbox->dev[vf_idx];
456 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
457
458 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
459
460 for (id = 0; id < vf_mbox->num_msgs; id++) {
461 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
462 offset);
463
464 if (msg->sig != OTX2_MBOX_REQ_SIG)
465 goto inval_msg;
466
467 /* Set VF's number in each of the msg */
468 msg->pcifunc &= RVU_PFVF_FUNC_MASK;
469 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
470 offset = msg->next_msgoff;
471 }
472 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
473 vf_mbox->num_msgs);
474 if (err)
475 goto inval_msg;
476 return;
477
478inval_msg:
479 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
480 otx2_mbox_msg_send(mbox, vf_idx);
481}
482
483static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
484{
485 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
486 struct otx2_nic *pf = vf_mbox->pfvf;
487 struct otx2_mbox_dev *mdev;
488 int offset, id, vf_idx = 0;
489 struct mbox_hdr *rsp_hdr;
490 struct mbox_msghdr *msg;
491 struct otx2_mbox *mbox;
492
493 vf_idx = vf_mbox - pf->mbox_pfvf;
494 mbox = &pf->mbox_pfvf[0].mbox_up;
495 mdev = &mbox->dev[vf_idx];
496
497 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
498 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
499
500 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
501 msg = mdev->mbase + offset;
502
503 if (msg->id >= MBOX_MSG_MAX) {
504 dev_err(pf->dev,
505 "Mbox msg with unknown ID 0x%x\n", msg->id);
506 goto end;
507 }
508
509 if (msg->sig != OTX2_MBOX_RSP_SIG) {
510 dev_err(pf->dev,
511 "Mbox msg with wrong signature %x, ID 0x%x\n",
512 msg->sig, msg->id);
513 goto end;
514 }
515
516 switch (msg->id) {
517 case MBOX_MSG_CGX_LINK_EVENT:
518 break;
519 default:
520 if (msg->rc)
521 dev_err(pf->dev,
522 "Mbox msg response has err %d, ID 0x%x\n",
523 msg->rc, msg->id);
524 break;
525 }
526
527end:
528 offset = mbox->rx_start + msg->next_msgoff;
529 mdev->msgs_acked++;
530 }
531
532 otx2_mbox_reset(mbox, vf_idx);
533}
534
535static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
536{
537 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
538 int vfs = pf->total_vfs;
539 struct mbox *mbox;
540 u64 intr;
541
542 mbox = pf->mbox_pfvf;
543 /* Handle VF interrupts */
544 if (vfs > 64) {
545 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
546 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
547 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
548 TYPE_PFVF);
549 vfs -= 64;
550 }
551
552 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
553 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
554
555 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
556
557 return IRQ_HANDLED;
558}
559
560static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
561{
562 void __iomem *hwbase;
563 struct mbox *mbox;
564 int err, vf;
565 u64 base;
566
567 if (!numvfs)
568 return -EINVAL;
569
570 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
571 sizeof(struct mbox), GFP_KERNEL);
572 if (!pf->mbox_pfvf)
573 return -ENOMEM;
574
575 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
576 WQ_UNBOUND | WQ_HIGHPRI |
577 WQ_MEM_RECLAIM, 1);
578 if (!pf->mbox_pfvf_wq)
579 return -ENOMEM;
580
581 base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR));
582 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
583
584 if (!hwbase) {
585 err = -ENOMEM;
586 goto free_wq;
587 }
588
589 mbox = &pf->mbox_pfvf[0];
590 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
591 MBOX_DIR_PFVF, numvfs);
592 if (err)
593 goto free_iomem;
594
595 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
596 MBOX_DIR_PFVF_UP, numvfs);
597 if (err)
598 goto free_iomem;
599
600 for (vf = 0; vf < numvfs; vf++) {
601 mbox->pfvf = pf;
602 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
603 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
604 mbox++;
605 }
606
607 return 0;
608
609free_iomem:
610 if (hwbase)
611 iounmap(hwbase);
612free_wq:
613 destroy_workqueue(pf->mbox_pfvf_wq);
614 return err;
615}
616
617static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
618{
619 struct mbox *mbox = &pf->mbox_pfvf[0];
620
621 if (!mbox)
622 return;
623
624 if (pf->mbox_pfvf_wq) {
d424b6c0
SG		 625 destroy_workqueue(pf->mbox_pfvf_wq);
626 pf->mbox_pfvf_wq = NULL;
627 }
628
629 if (mbox->mbox.hwbase)
630 iounmap(mbox->mbox.hwbase);
631
632 otx2_mbox_destroy(&mbox->mbox);
633}
634
635static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
636{
637 /* Clear PF <=> VF mailbox IRQ */
638 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
639 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
640
641 /* Enable PF <=> VF mailbox IRQ */
642 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
643 if (numvfs > 64) {
644 numvfs -= 64;
645 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
646 INTR_MASK(numvfs));
647 }
648}
649
650static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
651{
652 int vector;
653
654 /* Disable PF <=> VF mailbox IRQ */
655 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
656 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
657
658 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
659 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
660 free_irq(vector, pf);
661
662 if (numvfs > 64) {
663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
664 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
665 free_irq(vector, pf);
666 }
667}
668
669static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
670{
671 struct otx2_hw *hw = &pf->hw;
672 char *irq_name;
673 int err;
674
675 /* Register MBOX0 interrupt handler */
676 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
677 if (pf->pcifunc)
678 snprintf(irq_name, NAME_SIZE,
679 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
680 else
681 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
682 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
683 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
684 if (err) {
685 dev_err(pf->dev,
686 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
687 return err;
688 }
689
690 if (numvfs > 64) {
691 /* Register MBOX1 interrupt handler */
692 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
693 if (pf->pcifunc)
694 snprintf(irq_name, NAME_SIZE,
695 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
696 else
697 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
698 err = request_irq(pci_irq_vector(pf->pdev,
699 RVU_PF_INT_VEC_VFPF_MBOX1),
700 otx2_pfvf_mbox_intr_handler,
701 0, irq_name, pf);
702 if (err) {
703 dev_err(pf->dev,
704 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
705 return err;
706 }
707 }
708
709 otx2_enable_pfvf_mbox_intr(pf, numvfs);
710
711 return 0;
712}
713
5a6d7c9d
SG		 714static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
715 struct mbox_msghdr *msg)
716{
ad513ed9
TD		 717 int devid;
718
5a6d7c9d
SG		 719 if (msg->id >= MBOX_MSG_MAX) {
720 dev_err(pf->dev,
721 "Mbox msg with unknown ID 0x%x\n", msg->id);
722 return;
723 }
724
725 if (msg->sig != OTX2_MBOX_RSP_SIG) {
726 dev_err(pf->dev,
727 "Mbox msg with wrong signature %x, ID 0x%x\n",
728 msg->sig, msg->id);
729 return;
730 }
731
ad513ed9
TD		 732 /* message response heading VF */
733 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
734 if (devid) {
735 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
736 struct delayed_work *dwork;
737
738 switch (msg->id) {
739 case MBOX_MSG_NIX_LF_START_RX:
740 config->intf_down = false;
741 dwork = &config->link_event_work;
742 schedule_delayed_work(dwork, msecs_to_jiffies(100));
743 break;
744 case MBOX_MSG_NIX_LF_STOP_RX:
745 config->intf_down = true;
746 break;
747 }
748
749 return;
750 }
751
5a6d7c9d
SG		 752 switch (msg->id) {
753 case MBOX_MSG_READY:
754 pf->pcifunc = msg->pcifunc;
755 break;
05fcc9e0
SG		 756 case MBOX_MSG_MSIX_OFFSET:
757 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
758 break;
759 case MBOX_MSG_NPA_LF_ALLOC:
760 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
761 break;
762 case MBOX_MSG_NIX_LF_ALLOC:
763 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
764 break;
caa2da34
SG		 765 case MBOX_MSG_NIX_TXSCH_ALLOC:
766 mbox_handler_nix_txsch_alloc(pf,
767 (struct nix_txsch_alloc_rsp *)msg);
768 break;
75f36270
G		 769 case MBOX_MSG_NIX_BP_ENABLE:
770 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
771 break;
d45d8979
CJ		 772 case MBOX_MSG_CGX_STATS:
773 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
774 break;
5a6d7c9d
SG		 775 default:
776 if (msg->rc)
777 dev_err(pf->dev,
778 "Mbox msg response has err %d, ID 0x%x\n",
779 msg->rc, msg->id);
780 break;
781 }
782}
783
784static void otx2_pfaf_mbox_handler(struct work_struct *work)
785{
786 struct otx2_mbox_dev *mdev;
787 struct mbox_hdr *rsp_hdr;
788 struct mbox_msghdr *msg;
789 struct otx2_mbox *mbox;
790 struct mbox *af_mbox;
791 struct otx2_nic *pf;
792 int offset, id;
793
794 af_mbox = container_of(work, struct mbox, mbox_wrk);
795 mbox = &af_mbox->mbox;
796 mdev = &mbox->dev[0];
797 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
798
799 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
800 pf = af_mbox->pfvf;
801
802 for (id = 0; id < af_mbox->num_msgs; id++) {
803 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
804 otx2_process_pfaf_mbox_msg(pf, msg);
805 offset = mbox->rx_start + msg->next_msgoff;
806 mdev->msgs_acked++;
807 }
808
809 otx2_mbox_reset(mbox, 0);
810}
811
50fe6c02
LC		 812static void otx2_handle_link_event(struct otx2_nic *pf)
813{
814 struct cgx_link_user_info *linfo = &pf->linfo;
815 struct net_device *netdev = pf->netdev;
816
817 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
818 linfo->link_up ? "UP" : "DOWN", linfo->speed,
819 linfo->full_duplex ? "Full" : "Half");
820 if (linfo->link_up) {
821 netif_carrier_on(netdev);
822 netif_tx_start_all_queues(netdev);
823 } else {
824 netif_tx_stop_all_queues(netdev);
825 netif_carrier_off(netdev);
826 }
827}
828
829int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
830 struct cgx_link_info_msg *msg,
831 struct msg_rsp *rsp)
832{
ad513ed9
TD		 833 int i;
834
50fe6c02
LC		 835 /* Copy the link info sent by AF */
836 pf->linfo = msg->link_info;
837
ad513ed9
TD		 838 /* notify VFs about link event */
839 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
840 struct otx2_vf_config *config = &pf->vf_configs[i];
841 struct delayed_work *dwork = &config->link_event_work;
842
843 if (config->intf_down)
844 continue;
845
846 schedule_delayed_work(dwork, msecs_to_jiffies(100));
847 }
848
50fe6c02
LC		 849 /* interface has not been fully configured yet */
850 if (pf->flags & OTX2_FLAG_INTF_DOWN)
851 return 0;
852
853 otx2_handle_link_event(pf);
854 return 0;
855}
856
5a6d7c9d
SG		 857static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
858 struct mbox_msghdr *req)
859{
860 /* Check if valid, if not reply with a invalid msg */
861 if (req->sig != OTX2_MBOX_REQ_SIG) {
862 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
863 return -ENODEV;
864 }
865
866 switch (req->id) {
867#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
868 case _id: { \
869 struct _rsp_type *rsp; \
870 int err; \
871 \
872 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
873 &pf->mbox.mbox_up, 0, \
874 sizeof(struct _rsp_type)); \
875 if (!rsp) \
876 return -ENOMEM; \
877 \
878 rsp->hdr.id = _id; \
879 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
880 rsp->hdr.pcifunc = 0; \
881 rsp->hdr.rc = 0; \
882 \
883 err = otx2_mbox_up_handler_ ## _fn_name( \
884 pf, (struct _req_type *)req, rsp); \
885 return err; \
886 }
887MBOX_UP_CGX_MESSAGES
888#undef M
889 break;
890 default:
891 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
892 return -ENODEV;
893 }
894 return 0;
895}
896
897static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
898{
899 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
900 struct otx2_mbox *mbox = &af_mbox->mbox_up;
901 struct otx2_mbox_dev *mdev = &mbox->dev[0];
902 struct otx2_nic *pf = af_mbox->pfvf;
903 int offset, id, devid = 0;
904 struct mbox_hdr *rsp_hdr;
905 struct mbox_msghdr *msg;
906
907 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
908
909 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
910
911 for (id = 0; id < af_mbox->up_num_msgs; id++) {
912 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
913
914 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
915 /* Skip processing VF's messages */
916 if (!devid)
917 otx2_process_mbox_msg_up(pf, msg);
918 offset = mbox->rx_start + msg->next_msgoff;
919 }
d424b6c0
SG		 920 if (devid) {
921 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
922 MBOX_DIR_PFVF_UP, devid - 1,
923 af_mbox->up_num_msgs);
924 return;
925 }
5a6d7c9d
SG		 926
927 otx2_mbox_msg_send(mbox, 0);
928}
929
930static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
931{
932 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
933 struct mbox *mbox;
934
935 /* Clear the IRQ */
936 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
937
938 mbox = &pf->mbox;
939 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
940
941 return IRQ_HANDLED;
942}
943
944static void otx2_disable_mbox_intr(struct otx2_nic *pf)
945{
946 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
947
948 /* Disable AF => PF mailbox IRQ */
949 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
950 free_irq(vector, pf);
951}
952
953static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
954{
955 struct otx2_hw *hw = &pf->hw;
956 struct msg_req *req;
957 char *irq_name;
958 int err;
959
960 /* Register mailbox interrupt handler */
961 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
962 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
963 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
964 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
965 if (err) {
966 dev_err(pf->dev,
967 "RVUPF: IRQ registration failed for PFAF mbox irq\n");
968 return err;
969 }
970
971 /* Enable mailbox interrupt for msgs coming from AF.
972 * First clear to avoid spurious interrupts, if any.
973 */
974 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
975 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
976
977 if (!probe_af)
978 return 0;
979
980 /* Check mailbox communication with AF */
981 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
982 if (!req) {
983 otx2_disable_mbox_intr(pf);
984 return -ENOMEM;
985 }
986 err = otx2_sync_mbox_msg(&pf->mbox);
987 if (err) {
988 dev_warn(pf->dev,
989 "AF not responding to mailbox, deferring probe\n");
990 otx2_disable_mbox_intr(pf);
991 return -EPROBE_DEFER;
992 }
993
994 return 0;
995}
996
997static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
998{
999 struct mbox *mbox = &pf->mbox;
1000
1001 if (pf->mbox_wq) {
5a6d7c9d
SG		 1002 destroy_workqueue(pf->mbox_wq);
1003 pf->mbox_wq = NULL;
1004 }
1005
1006 if (mbox->mbox.hwbase)
1007 iounmap((void __iomem *)mbox->mbox.hwbase);
1008
1009 otx2_mbox_destroy(&mbox->mbox);
1010 otx2_mbox_destroy(&mbox->mbox_up);
1011}
1012
1013static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1014{
1015 struct mbox *mbox = &pf->mbox;
1016 void __iomem *hwbase;
1017 int err;
1018
1019 mbox->pfvf = pf;
1020 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox",
1021 WQ_UNBOUND | WQ_HIGHPRI |
1022 WQ_MEM_RECLAIM, 1);
1023 if (!pf->mbox_wq)
1024 return -ENOMEM;
1025
1026 /* Mailbox is a reserved memory (in RAM) region shared between
1027 * admin function (i.e AF) and this PF, shouldn't be mapped as
1028 * device memory to allow unaligned accesses.
1029 */
1030 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1031 pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM));
1032 if (!hwbase) {
1033 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1034 err = -ENOMEM;
1035 goto exit;
1036 }
1037
1038 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1039 MBOX_DIR_PFAF, 1);
1040 if (err)
1041 goto exit;
1042
1043 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1044 MBOX_DIR_PFAF_UP, 1);
1045 if (err)
1046 goto exit;
1047
1048 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1049 if (err)
1050 goto exit;
1051
1052 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1053 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
4c3212f5 1054 mutex_init(&mbox->lock);
5a6d7c9d
SG		 1055
1056 return 0;
1057exit:
1058 otx2_pfaf_mbox_destroy(pf);
1059 return err;
1060}
1061
50fe6c02
LC		 1062static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1063{
1064 struct msg_req *msg;
1065 int err;
1066
4c3212f5 1067 mutex_lock(&pf->mbox.lock);
50fe6c02
LC		 1068 if (enable)
1069 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1070 else
1071 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1072
1073 if (!msg) {
4c3212f5 1074 mutex_unlock(&pf->mbox.lock);
50fe6c02
LC		 1075 return -ENOMEM;
1076 }
1077
1078 err = otx2_sync_mbox_msg(&pf->mbox);
4c3212f5 1079 mutex_unlock(&pf->mbox.lock);
50fe6c02
LC		 1080 return err;
1081}
1082
34bfe0eb
SG		 1083static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1084{
1085 struct msg_req *msg;
1086 int err;
1087
4c3212f5 1088 mutex_lock(&pf->mbox.lock);
34bfe0eb
SG		 1089 if (enable)
1090 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1091 else
1092 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1093
1094 if (!msg) {
4c3212f5 1095 mutex_unlock(&pf->mbox.lock);
34bfe0eb
SG		 1096 return -ENOMEM;
1097 }
1098
1099 err = otx2_sync_mbox_msg(&pf->mbox);
4c3212f5 1100 mutex_unlock(&pf->mbox.lock);
34bfe0eb
SG		 1101 return err;
1102}
1103
d45d8979
CJ		 1104int otx2_set_real_num_queues(struct net_device *netdev,
1105 int tx_queues, int rx_queues)
16547577
SG		 1106{
1107 int err;
1108
1109 err = netif_set_real_num_tx_queues(netdev, tx_queues);
1110 if (err) {
1111 netdev_err(netdev,
1112 "Failed to set no of Tx queues: %d\n", tx_queues);
1113 return err;
1114 }
1115
1116 err = netif_set_real_num_rx_queues(netdev, rx_queues);
1117 if (err)
1118 netdev_err(netdev,
1119 "Failed to set no of Rx queues: %d\n", rx_queues);
1120 return err;
1121}
3184fb5b 1122EXPORT_SYMBOL(otx2_set_real_num_queues);
16547577 1123
4ff7d148
G		 1124static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1125{
1126 struct otx2_nic *pf = data;
1127 u64 val, *ptr;
1128 u64 qidx = 0;
1129
1130 /* CQ */
1131 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1132 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1133 val = otx2_atomic64_add((qidx << 44), ptr);
1134
1135 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1136 (val & NIX_CQERRINT_BITS));
1137 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1138 continue;
1139
1140 if (val & BIT_ULL(42)) {
1141 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1142 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1143 } else {
1144 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1145 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1146 qidx);
1147 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1148 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1149 qidx);
1150 }
1151
1152 schedule_work(&pf->reset_task);
1153 }
1154
1155 /* SQ */
1156 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1157 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1158 val = otx2_atomic64_add((qidx << 44), ptr);
1159 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1160 (val & NIX_SQINT_BITS));
1161
1162 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42))))
1163 continue;
1164
1165 if (val & BIT_ULL(42)) {
1166 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1167 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1168 } else {
1169 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1170 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1171 qidx,
1172 otx2_read64(pf,
1173 NIX_LF_SQ_OP_ERR_DBG));
1174 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1175 BIT_ULL(44));
1176 }
1177 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1178 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1179 qidx,
1180 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1181 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1182 BIT_ULL(44));
1183 }
1184 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1185 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1186 qidx,
1187 otx2_read64(pf,
1188 NIX_LF_SEND_ERR_DBG));
1189 otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1190 BIT_ULL(44));
1191 }
1192 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1193 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1194 qidx);
1195 }
1196
1197 schedule_work(&pf->reset_task);
1198 }
1199
1200 return IRQ_HANDLED;
1201}
1202
04a21ef3
SG		 1203static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1204{
1205 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1206 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1207 int qidx = cq_poll->cint_idx;
1208
1209 /* Disable interrupts.
1210 *
1211 * Completion interrupts behave in a level-triggered interrupt
1212 * fashion, and hence have to be cleared only after it is serviced.
1213 */
1214 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1215
1216 /* Schedule NAPI */
1217 napi_schedule_irqoff(&cq_poll->napi);
1218
1219 return IRQ_HANDLED;
1220}
1221
1222static void otx2_disable_napi(struct otx2_nic *pf)
1223{
1224 struct otx2_qset *qset = &pf->qset;
1225 struct otx2_cq_poll *cq_poll;
1226 int qidx;
1227
1228 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1229 cq_poll = &qset->napi[qidx];
1230 napi_disable(&cq_poll->napi);
1231 netif_napi_del(&cq_poll->napi);
1232 }
1233}
1234
caa2da34
SG		 1235static void otx2_free_cq_res(struct otx2_nic *pf)
1236{
1237 struct otx2_qset *qset = &pf->qset;
1238 struct otx2_cq_queue *cq;
1239 int qidx;
1240
1241 /* Disable CQs */
1242 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1243 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1244 cq = &qset->cq[qidx];
1245 qmem_free(pf->dev, cq->cqe);
1246 }
1247}
1248
1249static void otx2_free_sq_res(struct otx2_nic *pf)
1250{
1251 struct otx2_qset *qset = &pf->qset;
1252 struct otx2_snd_queue *sq;
1253 int qidx;
1254
1255 /* Disable SQs */
1256 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1257 /* Free SQB pointers */
1258 otx2_sq_free_sqbs(pf);
1259 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1260 sq = &qset->sq[qidx];
1261 qmem_free(pf->dev, sq->sqe);
86d74760 1262 qmem_free(pf->dev, sq->tso_hdrs);
3ca6c4c8 1263 kfree(sq->sg);
caa2da34
SG		 1264 kfree(sq->sqb_ptrs);
1265 }
1266}
1267
1268static int otx2_init_hw_resources(struct otx2_nic *pf)
1269{
1270 struct mbox *mbox = &pf->mbox;
1271 struct otx2_hw *hw = &pf->hw;
1272 struct msg_req *req;
1273 int err = 0, lvl;
1274
1275 /* Set required NPA LF's pool counts
1276 * Auras and Pools are used in a 1:1 mapping,
1277 * so, aura count = pool count.
1278 */
1279 hw->rqpool_cnt = hw->rx_queues;
1280 hw->sqpool_cnt = hw->tx_queues;
1281 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1282
1283 /* Get the size of receive buffers to allocate */
34bfe0eb 1284 pf->rbsize = RCV_FRAG_LEN(pf->netdev->mtu + OTX2_ETH_HLEN);
caa2da34 1285
4c3212f5 1286 mutex_lock(&mbox->lock);
caa2da34
SG		 1287 /* NPA init */
1288 err = otx2_config_npa(pf);
1289 if (err)
1290 goto exit;
1291
1292 /* NIX init */
1293 err = otx2_config_nix(pf);
1294 if (err)
1295 goto err_free_npa_lf;
1296
75f36270
G		 1297 /* Enable backpressure */
1298 otx2_nix_config_bp(pf, true);
1299
caa2da34
SG		 1300 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1301 err = otx2_rq_aura_pool_init(pf);
1302 if (err) {
4c3212f5 1303 mutex_unlock(&mbox->lock);
caa2da34
SG		 1304 goto err_free_nix_lf;
1305 }
1306 /* Init Auras and pools used by NIX SQ, for queueing SQEs */
1307 err = otx2_sq_aura_pool_init(pf);
1308 if (err) {
4c3212f5 1309 mutex_unlock(&mbox->lock);
caa2da34
SG		 1310 goto err_free_rq_ptrs;
1311 }
1312
1313 err = otx2_txsch_alloc(pf);
1314 if (err) {
4c3212f5 1315 mutex_unlock(&mbox->lock);
caa2da34
SG		 1316 goto err_free_sq_ptrs;
1317 }
1318
1319 err = otx2_config_nix_queues(pf);
1320 if (err) {
4c3212f5 1321 mutex_unlock(&mbox->lock);
caa2da34
SG		 1322 goto err_free_txsch;
1323 }
1324 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1325 err = otx2_txschq_config(pf, lvl);
1326 if (err) {
4c3212f5 1327 mutex_unlock(&mbox->lock);
caa2da34
SG		 1328 goto err_free_nix_queues;
1329 }
1330 }
4c3212f5 1331 mutex_unlock(&mbox->lock);
caa2da34
SG		 1332 return err;
1333
1334err_free_nix_queues:
1335 otx2_free_sq_res(pf);
1336 otx2_free_cq_res(pf);
1337 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1338err_free_txsch:
1339 if (otx2_txschq_stop(pf))
1340 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__);
1341err_free_sq_ptrs:
1342 otx2_sq_free_sqbs(pf);
1343err_free_rq_ptrs:
1344 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1345 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1346 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1347 otx2_aura_pool_free(pf);
1348err_free_nix_lf:
4c3212f5 1349 mutex_lock(&mbox->lock);
caa2da34
SG		 1350 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1351 if (req) {
1352 if (otx2_sync_mbox_msg(mbox))
1353 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1354 }
1355err_free_npa_lf:
1356 /* Reset NPA LF */
1357 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1358 if (req) {
1359 if (otx2_sync_mbox_msg(mbox))
1360 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1361 }
1362exit:
4c3212f5 1363 mutex_unlock(&mbox->lock);
caa2da34
SG		 1364 return err;
1365}
1366
1367static void otx2_free_hw_resources(struct otx2_nic *pf)
1368{
abe02543 1369 struct otx2_qset *qset = &pf->qset;
caa2da34 1370 struct mbox *mbox = &pf->mbox;
abe02543 1371 struct otx2_cq_queue *cq;
caa2da34 1372 struct msg_req *req;
abe02543 1373 int qidx, err;
caa2da34
SG		 1374
1375 /* Ensure all SQE are processed */
1376 otx2_sqb_flush(pf);
1377
1378 /* Stop transmission */
1379 err = otx2_txschq_stop(pf);
1380 if (err)
1381 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n");
1382
4c3212f5 1383 mutex_lock(&mbox->lock);
75f36270
G		 1384 /* Disable backpressure */
1385 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1386 otx2_nix_config_bp(pf, false);
4c3212f5 1387 mutex_unlock(&mbox->lock);
75f36270 1388
caa2da34
SG		 1389 /* Disable RQs */
1390 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1391
abe02543
SG		 1392 /*Dequeue all CQEs */
1393 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1394 cq = &qset->cq[qidx];
1395 if (cq->cq_type == CQ_RX)
1396 otx2_cleanup_rx_cqes(pf, cq);
3ca6c4c8
SG		 1397 else
1398 otx2_cleanup_tx_cqes(pf, cq);
abe02543
SG		 1399 }
1400
caa2da34
SG		 1401 otx2_free_sq_res(pf);
1402
1403 /* Free RQ buffer pointers*/
1404 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1405
1406 otx2_free_cq_res(pf);
1407
4c3212f5 1408 mutex_lock(&mbox->lock);
caa2da34
SG		 1409 /* Reset NIX LF */
1410 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1411 if (req) {
1412 if (otx2_sync_mbox_msg(mbox))
1413 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1414 }
4c3212f5 1415 mutex_unlock(&mbox->lock);
caa2da34
SG		 1416
1417 /* Disable NPA Pool and Aura hw context */
1418 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1419 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1420 otx2_aura_pool_free(pf);
1421
4c3212f5 1422 mutex_lock(&mbox->lock);
caa2da34
SG		 1423 /* Reset NPA LF */
1424 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1425 if (req) {
1426 if (otx2_sync_mbox_msg(mbox))
1427 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1428 }
4c3212f5 1429 mutex_unlock(&mbox->lock);
caa2da34
SG		 1430}
1431
34bfe0eb 1432int otx2_open(struct net_device *netdev)
16547577 1433{
05fcc9e0 1434 struct otx2_nic *pf = netdev_priv(netdev);
04a21ef3 1435 struct otx2_cq_poll *cq_poll = NULL;
caa2da34 1436 struct otx2_qset *qset = &pf->qset;
04a21ef3
SG		 1437 int err = 0, qidx, vec;
1438 char *irq_name;
05fcc9e0 1439
16547577
SG		 1440 netif_carrier_off(netdev);
1441
05fcc9e0 1442 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues;
04a21ef3
SG		 1443 /* RQ and SQs are mapped to different CQs,
1444 * so find out max CQ IRQs (i.e CINTs) needed.
1445 */
1446 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues);
1447 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1448 if (!qset->napi)
1449 return -ENOMEM;
05fcc9e0 1450
caa2da34
SG		 1451 /* CQ size of RQ */
1452 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1453 /* CQ size of SQ */
1454 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1455
1456 err = -ENOMEM;
1457 qset->cq = kcalloc(pf->qset.cq_cnt,
1458 sizeof(struct otx2_cq_queue), GFP_KERNEL);
1459 if (!qset->cq)
1460 goto err_free_mem;
1461
1462 qset->sq = kcalloc(pf->hw.tx_queues,
1463 sizeof(struct otx2_snd_queue), GFP_KERNEL);
1464 if (!qset->sq)
1465 goto err_free_mem;
1466
d45d8979
CJ		 1467 qset->rq = kcalloc(pf->hw.rx_queues,
1468 sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1469 if (!qset->rq)
1470 goto err_free_mem;
1471
caa2da34 1472 err = otx2_init_hw_resources(pf);
05fcc9e0 1473 if (err)
caa2da34 1474 goto err_free_mem;
05fcc9e0 1475
04a21ef3
SG		 1476 /* Register NAPI handler */
1477 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1478 cq_poll = &qset->napi[qidx];
1479 cq_poll->cint_idx = qidx;
1480 /* RQ0 & SQ0 are mapped to CINT0 and so on..
1481 * 'cq_ids[0]' points to RQ's CQ and
1482 * 'cq_ids[1]' points to SQ's CQ and
1483 */
1484 cq_poll->cq_ids[CQ_RX] =
1485 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1486 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1487 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1488 cq_poll->dev = (void *)pf;
1489 netif_napi_add(netdev, &cq_poll->napi,
1490 otx2_napi_handler, NAPI_POLL_WEIGHT);
1491 napi_enable(&cq_poll->napi);
1492 }
1493
34bfe0eb
SG		 1494 /* Set maximum frame size allowed in HW */
1495 err = otx2_hw_set_mtu(pf, netdev->mtu);
1496 if (err)
1497 goto err_disable_napi;
1498
85069e95
SG		 1499 /* Initialize RSS */
1500 err = otx2_rss_init(pf);
1501 if (err)
1502 goto err_disable_napi;
1503
4ff7d148
G		 1504 /* Register Queue IRQ handlers */
1505 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1506 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1507
1508 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1509
1510 err = request_irq(pci_irq_vector(pf->pdev, vec),
1511 otx2_q_intr_handler, 0, irq_name, pf);
1512 if (err) {
1513 dev_err(pf->dev,
1514 "RVUPF%d: IRQ registration failed for QERR\n",
1515 rvu_get_pf(pf->pcifunc));
1516 goto err_disable_napi;
1517 }
1518
1519 /* Enable QINT IRQ */
1520 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1521
04a21ef3
SG		 1522 /* Register CQ IRQ handlers */
1523 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1524 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1525 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1526
1527 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1528 qidx);
1529
1530 err = request_irq(pci_irq_vector(pf->pdev, vec),
1531 otx2_cq_intr_handler, 0, irq_name,
1532 &qset->napi[qidx]);
1533 if (err) {
1534 dev_err(pf->dev,
1535 "RVUPF%d: IRQ registration failed for CQ%d\n",
1536 rvu_get_pf(pf->pcifunc), qidx);
1537 goto err_free_cints;
1538 }
1539 vec++;
1540
1541 otx2_config_irq_coalescing(pf, qidx);
1542
1543 /* Enable CQ IRQ */
1544 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1545 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1546 }
1547
1548 otx2_set_cints_affinity(pf);
1549
50fe6c02
LC		 1550 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1551 /* 'intf_down' may be checked on any cpu */
1552 smp_wmb();
1553
1554 /* we have already received link status notification */
1555 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1556 otx2_handle_link_event(pf);
1557
3184fb5b
TD		 1558 /* Restore pause frame settings */
1559 otx2_config_pause_frm(pf);
1560
50fe6c02
LC		 1561 err = otx2_rxtx_enable(pf, true);
1562 if (err)
1563 goto err_free_cints;
1564
caa2da34 1565 return 0;
04a21ef3
SG		 1566
1567err_free_cints:
1568 otx2_free_cints(pf, qidx);
4ff7d148
G		 1569 vec = pci_irq_vector(pf->pdev,
1570 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1571 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1572 synchronize_irq(vec);
1573 free_irq(vec, pf);
34bfe0eb 1574err_disable_napi:
04a21ef3
SG		 1575 otx2_disable_napi(pf);
1576 otx2_free_hw_resources(pf);
caa2da34
SG		 1577err_free_mem:
1578 kfree(qset->sq);
1579 kfree(qset->cq);
d45d8979 1580 kfree(qset->rq);
04a21ef3 1581 kfree(qset->napi);
caa2da34 1582 return err;
16547577 1583}
3184fb5b 1584EXPORT_SYMBOL(otx2_open);
16547577 1585
34bfe0eb 1586int otx2_stop(struct net_device *netdev)
16547577 1587{
caa2da34 1588 struct otx2_nic *pf = netdev_priv(netdev);
04a21ef3 1589 struct otx2_cq_poll *cq_poll = NULL;
caa2da34 1590 struct otx2_qset *qset = &pf->qset;
4ff7d148 1591 int qidx, vec, wrk;
04a21ef3
SG		 1592
1593 netif_carrier_off(netdev);
1594 netif_tx_stop_all_queues(netdev);
1595
50fe6c02
LC		 1596 pf->flags |= OTX2_FLAG_INTF_DOWN;
1597 /* 'intf_down' may be checked on any cpu */
1598 smp_wmb();
1599
1600 /* First stop packet Rx/Tx */
1601 otx2_rxtx_enable(pf, false);
1602
4ff7d148
G		 1603 /* Cleanup Queue IRQ */
1604 vec = pci_irq_vector(pf->pdev,
1605 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1606 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1607 synchronize_irq(vec);
1608 free_irq(vec, pf);
1609
04a21ef3
SG		 1610 /* Cleanup CQ NAPI and IRQ */
1611 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1612 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1613 /* Disable interrupt */
1614 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1615
1616 synchronize_irq(pci_irq_vector(pf->pdev, vec));
1617
1618 cq_poll = &qset->napi[qidx];
1619 napi_synchronize(&cq_poll->napi);
1620 vec++;
1621 }
1622
1623 netif_tx_disable(netdev);
caa2da34
SG		 1624
1625 otx2_free_hw_resources(pf);
04a21ef3
SG		 1626 otx2_free_cints(pf, pf->hw.cint_cnt);
1627 otx2_disable_napi(pf);
1628
1629 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1630 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
caa2da34 1631
4ff7d148
G		 1632 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1633 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1634 devm_kfree(pf->dev, pf->refill_wrk);
1635
caa2da34
SG		 1636 kfree(qset->sq);
1637 kfree(qset->cq);
d45d8979 1638 kfree(qset->rq);
04a21ef3 1639 kfree(qset->napi);
caa2da34
SG		 1640 /* Do not clear RQ/SQ ringsize settings */
1641 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0,
1642 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt));
16547577
SG		 1643 return 0;
1644}
3184fb5b 1645EXPORT_SYMBOL(otx2_stop);
16547577 1646
3ca6c4c8
SG		 1647static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1648{
1649 struct otx2_nic *pf = netdev_priv(netdev);
1650 int qidx = skb_get_queue_mapping(skb);
1651 struct otx2_snd_queue *sq;
1652 struct netdev_queue *txq;
1653
86d74760
SG		 1654 /* Check for minimum and maximum packet length */
1655 if (skb->len <= ETH_HLEN ||
1656 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) {
3ca6c4c8
SG		 1657 dev_kfree_skb(skb);
1658 return NETDEV_TX_OK;
1659 }
1660
1661 sq = &pf->qset.sq[qidx];
1662 txq = netdev_get_tx_queue(netdev, qidx);
1663
1664 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1665 netif_tx_stop_queue(txq);
1666
1667 /* Check again, incase SQBs got freed up */
1668 smp_mb();
1669 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1670 > sq->sqe_thresh)
1671 netif_tx_wake_queue(txq);
1672
1673 return NETDEV_TX_BUSY;
1674 }
1675
1676 return NETDEV_TX_OK;
1677}
1678
34bfe0eb
SG		 1679static void otx2_set_rx_mode(struct net_device *netdev)
1680{
1681 struct otx2_nic *pf = netdev_priv(netdev);
e99b7c84
SG		 1682
1683 queue_work(pf->otx2_wq, &pf->rx_mode_work);
1684}
1685
1686static void otx2_do_set_rx_mode(struct work_struct *work)
1687{
1688 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
1689 struct net_device *netdev = pf->netdev;
34bfe0eb
SG		 1690 struct nix_rx_mode *req;
1691
1692 if (!(netdev->flags & IFF_UP))
1693 return;
1694
4c3212f5 1695 mutex_lock(&pf->mbox.lock);
34bfe0eb
SG		 1696 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1697 if (!req) {
4c3212f5 1698 mutex_unlock(&pf->mbox.lock);
34bfe0eb
SG		 1699 return;
1700 }
1701
1702 req->mode = NIX_RX_MODE_UCAST;
1703
1704 /* We don't support MAC address filtering yet */
1705 if (netdev->flags & IFF_PROMISC)
1706 req->mode |= NIX_RX_MODE_PROMISC;
1707 else if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1708 req->mode |= NIX_RX_MODE_ALLMULTI;
1709
1710 otx2_sync_mbox_msg(&pf->mbox);
4c3212f5 1711 mutex_unlock(&pf->mbox.lock);
34bfe0eb
SG		 1712}
1713
1714static int otx2_set_features(struct net_device *netdev,
1715 netdev_features_t features)
1716{
1717 netdev_features_t changed = features ^ netdev->features;
1718 struct otx2_nic *pf = netdev_priv(netdev);
1719
1720 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
1721 return otx2_cgx_config_loopback(pf,
1722 features & NETIF_F_LOOPBACK);
1723 return 0;
1724}
1725
4ff7d148
G		 1726static void otx2_reset_task(struct work_struct *work)
1727{
1728 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
1729
1730 if (!netif_running(pf->netdev))
1731 return;
1732
1733 otx2_stop(pf->netdev);
1734 pf->reset_count++;
1735 otx2_open(pf->netdev);
1736 netif_trans_update(pf->netdev);
1737}
1738
16547577
SG		 1739static const struct net_device_ops otx2_netdev_ops = {
1740 .ndo_open = otx2_open,
1741 .ndo_stop = otx2_stop,
3ca6c4c8 1742 .ndo_start_xmit = otx2_xmit,
34bfe0eb
SG		 1743 .ndo_set_mac_address = otx2_set_mac_address,
1744 .ndo_change_mtu = otx2_change_mtu,
1745 .ndo_set_rx_mode = otx2_set_rx_mode,
1746 .ndo_set_features = otx2_set_features,
4ff7d148 1747 .ndo_tx_timeout = otx2_tx_timeout,
e239d0c7 1748 .ndo_get_stats64 = otx2_get_stats64,
16547577
SG		 1749};
1750
e99b7c84
SG		 1751static int otx2_wq_init(struct otx2_nic *pf)
1752{
1753 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
1754 if (!pf->otx2_wq)
1755 return -ENOMEM;
1756
1757 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode);
1758 INIT_WORK(&pf->reset_task, otx2_reset_task);
1759 return 0;
1760}
1761
16547577
SG		 1762static int otx2_check_pf_usable(struct otx2_nic *nic)
1763{
1764 u64 rev;
1765
1766 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
1767 rev = (rev >> 12) & 0xFF;
1768 /* Check if AF has setup revision for RVUM block,
1769 * otherwise this driver probe should be deferred
1770 * until AF driver comes up.
1771 */
1772 if (!rev) {
1773 dev_warn(nic->dev,
1774 "AF is not initialized, deferring probe\n");
1775 return -EPROBE_DEFER;
1776 }
1777 return 0;
1778}
1779
05fcc9e0
SG		 1780static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
1781{
1782 struct otx2_hw *hw = &pf->hw;
1783 int num_vec, err;
1784
1785 /* NPA interrupts are inot registered, so alloc only
1786 * upto NIX vector offset.
1787 */
1788 num_vec = hw->nix_msixoff;
05fcc9e0
SG		 1789 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
1790
1791 otx2_disable_mbox_intr(pf);
1792 pci_free_irq_vectors(hw->pdev);
05fcc9e0
SG		 1793 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
1794 if (err < 0) {
1795 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
1796 __func__, num_vec);
1797 return err;
1798 }
1799
1800 return otx2_register_mbox_intr(pf, false);
1801}
1802
16547577
SG		 1803static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1804{
1805 struct device *dev = &pdev->dev;
1806 struct net_device *netdev;
1807 struct otx2_nic *pf;
1808 struct otx2_hw *hw;
1809 int err, qcount;
5a6d7c9d 1810 int num_vec;
16547577
SG		 1811
1812 err = pcim_enable_device(pdev);
1813 if (err) {
1814 dev_err(dev, "Failed to enable PCI device\n");
1815 return err;
1816 }
1817
1818 err = pci_request_regions(pdev, DRV_NAME);
1819 if (err) {
1820 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1821 return err;
1822 }
1823
1824 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
1825 if (err) {
1826 dev_err(dev, "DMA mask config failed, abort\n");
1827 goto err_release_regions;
1828 }
1829
1830 pci_set_master(pdev);
1831
1832 /* Set number of queues */
05fcc9e0 1833 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
16547577
SG		 1834
1835 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
1836 if (!netdev) {
1837 err = -ENOMEM;
1838 goto err_release_regions;
1839 }
1840
1841 pci_set_drvdata(pdev, netdev);
1842 SET_NETDEV_DEV(netdev, &pdev->dev);
1843 pf = netdev_priv(netdev);
1844 pf->netdev = netdev;
1845 pf->pdev = pdev;
1846 pf->dev = dev;
d424b6c0 1847 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
50fe6c02 1848 pf->flags |= OTX2_FLAG_INTF_DOWN;
16547577
SG		 1849
1850 hw = &pf->hw;
1851 hw->pdev = pdev;
1852 hw->rx_queues = qcount;
1853 hw->tx_queues = qcount;
1854 hw->max_queues = qcount;
1855
5a6d7c9d
SG		 1856 num_vec = pci_msix_vec_count(pdev);
1857 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
1858 GFP_KERNEL);
654cad8b
WY		 1859 if (!hw->irq_name) {
1860 err = -ENOMEM;
5a6d7c9d 1861 goto err_free_netdev;
654cad8b 1862 }
5a6d7c9d
SG		 1863
1864 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
1865 sizeof(cpumask_var_t), GFP_KERNEL);
654cad8b
WY		 1866 if (!hw->affinity_mask) {
1867 err = -ENOMEM;
5a6d7c9d 1868 goto err_free_netdev;
654cad8b 1869 }
5a6d7c9d 1870
16547577
SG		 1871 /* Map CSRs */
1872 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1873 if (!pf->reg_base) {
1874 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
1875 err = -ENOMEM;
1876 goto err_free_netdev;
1877 }
1878
1879 err = otx2_check_pf_usable(pf);
1880 if (err)
1881 goto err_free_netdev;
1882
5a6d7c9d
SG		 1883 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
1884 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
1885 if (err < 0) {
1886 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
1887 __func__, num_vec);
1888 goto err_free_netdev;
1889 }
1890
1891 /* Init PF <=> AF mailbox stuff */
1892 err = otx2_pfaf_mbox_init(pf);
1893 if (err)
1894 goto err_free_irq_vectors;
1895
1896 /* Register mailbox interrupt */
1897 err = otx2_register_mbox_intr(pf, true);
1898 if (err)
1899 goto err_mbox_destroy;
1900
05fcc9e0
SG		 1901 /* Request AF to attach NPA and NIX LFs to this PF.
1902 * NIX and NPA LFs are needed for this PF to function as a NIC.
1903 */
1904 err = otx2_attach_npa_nix(pf);
16547577 1905 if (err)
5a6d7c9d 1906 goto err_disable_mbox_intr;
16547577 1907
05fcc9e0
SG		 1908 err = otx2_realloc_msix_vectors(pf);
1909 if (err)
1910 goto err_detach_rsrc;
1911
1912 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
1913 if (err)
1914 goto err_detach_rsrc;
1915
04a21ef3
SG		 1916 otx2_setup_dev_hw_settings(pf);
1917
34bfe0eb
SG		 1918 /* Assign default mac address */
1919 otx2_get_mac_from_af(netdev);
1920
caa2da34
SG		 1921 /* NPA's pool is a stack to which SW frees buffer pointers via Aura.
1922 * HW allocates buffer pointer from stack and uses it for DMA'ing
1923 * ingress packet. In some scenarios HW can free back allocated buffer
1924 * pointers to pool. This makes it impossible for SW to maintain a
1925 * parallel list where physical addresses of buffer pointers (IOVAs)
1926 * given to HW can be saved for later reference.
1927 *
1928 * So the only way to convert Rx packet's buffer address is to use
1929 * IOMMU's iova_to_phys() handler which translates the address by
1930 * walking through the translation tables.
1931 */
1932 pf->iommu_domain = iommu_get_domain_for_dev(dev);
1933
3ca6c4c8 1934 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
85069e95 1935 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
86d74760 1936 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6);
abe02543
SG		 1937 netdev->features |= netdev->hw_features;
1938
34bfe0eb 1939 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
abe02543 1940
86d74760 1941 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS;
4ff7d148
G		 1942 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
1943
16547577
SG		 1944 netdev->netdev_ops = &otx2_netdev_ops;
1945
34bfe0eb
SG		 1946 /* MTU range: 64 - 9190 */
1947 netdev->min_mtu = OTX2_MIN_MTU;
1948 netdev->max_mtu = OTX2_MAX_MTU;
1949
16547577
SG		 1950 err = register_netdev(netdev);
1951 if (err) {
1952 dev_err(dev, "Failed to register netdevice\n");
05fcc9e0 1953 goto err_detach_rsrc;
16547577
SG		 1954 }
1955
e99b7c84
SG		 1956 err = otx2_wq_init(pf);
1957 if (err)
1958 goto err_unreg_netdev;
1959
d45d8979
CJ		 1960 otx2_set_ethtool_ops(netdev);
1961
50fe6c02
LC		 1962 /* Enable link notifications */
1963 otx2_cgx_config_linkevents(pf, true);
1964
3184fb5b
TD		 1965 /* Enable pause frames by default */
1966 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
1967 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
1968
16547577
SG		 1969 return 0;
1970
e99b7c84
SG		 1971err_unreg_netdev:
1972 unregister_netdev(netdev);
05fcc9e0
SG		 1973err_detach_rsrc:
1974 otx2_detach_resources(&pf->mbox);
5a6d7c9d
SG		 1975err_disable_mbox_intr:
1976 otx2_disable_mbox_intr(pf);
1977err_mbox_destroy:
1978 otx2_pfaf_mbox_destroy(pf);
1979err_free_irq_vectors:
1980 pci_free_irq_vectors(hw->pdev);
16547577
SG		 1981err_free_netdev:
1982 pci_set_drvdata(pdev, NULL);
1983 free_netdev(netdev);
1984err_release_regions:
1985 pci_release_regions(pdev);
1986 return err;
1987}
1988
ad513ed9
TD		 1989static void otx2_vf_link_event_task(struct work_struct *work)
1990{
1991 struct otx2_vf_config *config;
1992 struct cgx_link_info_msg *req;
1993 struct mbox_msghdr *msghdr;
1994 struct otx2_nic *pf;
1995 int vf_idx;
1996
1997 config = container_of(work, struct otx2_vf_config,
1998 link_event_work.work);
1999 vf_idx = config - config->pf->vf_configs;
2000 pf = config->pf;
2001
2002 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
2003 sizeof(*req), sizeof(struct msg_rsp));
2004 if (!msghdr) {
2005 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
2006 return;
2007 }
2008
2009 req = (struct cgx_link_info_msg *)msghdr;
2010 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
2011 req->hdr.sig = OTX2_MBOX_REQ_SIG;
2012 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
2013
2014 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
2015}
2016
d424b6c0
SG		 2017static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
2018{
2019 struct net_device *netdev = pci_get_drvdata(pdev);
2020 struct otx2_nic *pf = netdev_priv(netdev);
ad513ed9 2021 int ret, i;
d424b6c0
SG		 2022
2023 /* Init PF <=> VF mailbox stuff */
2024 ret = otx2_pfvf_mbox_init(pf, numvfs);
2025 if (ret)
2026 return ret;
2027
2028 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
2029 if (ret)
2030 goto free_mbox;
2031
ad513ed9
TD		 2032 pf->vf_configs = kcalloc(numvfs, sizeof(struct otx2_vf_config),
2033 GFP_KERNEL);
2034 if (!pf->vf_configs) {
2035 ret = -ENOMEM;
2036 goto free_intr;
2037 }
2038
2039 for (i = 0; i < numvfs; i++) {
2040 pf->vf_configs[i].pf = pf;
2041 pf->vf_configs[i].intf_down = true;
2042 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2043 otx2_vf_link_event_task);
2044 }
2045
547d20f1 2046 ret = otx2_pf_flr_init(pf, numvfs);
d424b6c0 2047 if (ret)
ad513ed9 2048 goto free_configs;
d424b6c0 2049
547d20f1
G		 2050 ret = otx2_register_flr_me_intr(pf, numvfs);
2051 if (ret)
2052 goto free_flr;
2053
2054 ret = pci_enable_sriov(pdev, numvfs);
2055 if (ret)
2056 goto free_flr_intr;
2057
d424b6c0 2058 return numvfs;
547d20f1
G		 2059free_flr_intr:
2060 otx2_disable_flr_me_intr(pf);
2061free_flr:
2062 otx2_flr_wq_destroy(pf);
ad513ed9
TD		 2063free_configs:
2064 kfree(pf->vf_configs);
d424b6c0
SG		 2065free_intr:
2066 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2067free_mbox:
2068 otx2_pfvf_mbox_destroy(pf);
2069 return ret;
2070}
2071
2072static int otx2_sriov_disable(struct pci_dev *pdev)
2073{
2074 struct net_device *netdev = pci_get_drvdata(pdev);
2075 struct otx2_nic *pf = netdev_priv(netdev);
2076 int numvfs = pci_num_vf(pdev);
ad513ed9 2077 int i;
d424b6c0
SG		 2078
2079 if (!numvfs)
2080 return 0;
2081
2082 pci_disable_sriov(pdev);
2083
ad513ed9
TD		 2084 for (i = 0; i < pci_num_vf(pdev); i++)
2085 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2086 kfree(pf->vf_configs);
2087
547d20f1
G		 2088 otx2_disable_flr_me_intr(pf);
2089 otx2_flr_wq_destroy(pf);
d424b6c0
SG		 2090 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2091 otx2_pfvf_mbox_destroy(pf);
2092
2093 return 0;
2094}
2095
2096static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
2097{
2098 if (numvfs == 0)
2099 return otx2_sriov_disable(pdev);
2100 else
2101 return otx2_sriov_enable(pdev, numvfs);
2102}
2103
16547577
SG		 2104static void otx2_remove(struct pci_dev *pdev)
2105{
2106 struct net_device *netdev = pci_get_drvdata(pdev);
2107 struct otx2_nic *pf;
2108
2109 if (!netdev)
2110 return;
2111
2112 pf = netdev_priv(netdev);
2113
50fe6c02
LC		 2114 /* Disable link notifications */
2115 otx2_cgx_config_linkevents(pf, false);
2116
16547577 2117 unregister_netdev(netdev);
d424b6c0 2118 otx2_sriov_disable(pf->pdev);
e99b7c84
SG		 2119 if (pf->otx2_wq)
2120 destroy_workqueue(pf->otx2_wq);
d424b6c0 2121
05fcc9e0 2122 otx2_detach_resources(&pf->mbox);
5a6d7c9d
SG		 2123 otx2_disable_mbox_intr(pf);
2124 otx2_pfaf_mbox_destroy(pf);
16547577
SG		 2125 pci_free_irq_vectors(pf->pdev);
2126 pci_set_drvdata(pdev, NULL);
2127 free_netdev(netdev);
5a6d7c9d 2128
16547577
SG		 2129 pci_release_regions(pdev);
2130}
2131
2132static struct pci_driver otx2_pf_driver = {
2133 .name = DRV_NAME,
2134 .id_table = otx2_pf_id_table,
2135 .probe = otx2_probe,
2136 .shutdown = otx2_remove,
2137 .remove = otx2_remove,
d424b6c0 2138 .sriov_configure = otx2_sriov_configure
16547577
SG		 2139};
2140
2141static int __init otx2_rvupf_init_module(void)
2142{
2143 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
2144
2145 return pci_register_driver(&otx2_pf_driver);
2146}
2147
2148static void __exit otx2_rvupf_cleanup_module(void)
2149{
2150 pci_unregister_driver(&otx2_pf_driver);
2151}
2152
2153module_init(otx2_rvupf_init_module);
2154module_exit(otx2_rvupf_cleanup_module);
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