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octeontx2-pf: Forward error codes to VF
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / marvell / octeontx2 / nic / otx2_pf.c
CommitLineData
16547577 1// SPDX-License-Identifier: GPL-2.0
cb0e3ec4 2/* Marvell RVU Physical Function ethernet driver
16547577 3 *
cb0e3ec4 4 * Copyright (C) 2020 Marvell.
16547577 5 *
16547577
SG		 6 */
7
8#include <linux/module.h>
9#include <linux/interrupt.h>
10#include <linux/pci.h>
11#include <linux/etherdevice.h>
12#include <linux/of.h>
13#include <linux/if_vlan.h>
14#include <linux/iommu.h>
15#include <net/ip.h>
16
caa2da34 17#include "otx2_reg.h"
16547577 18#include "otx2_common.h"
caa2da34
SG		 19#include "otx2_txrx.h"
20#include "otx2_struct.h"
c9c12d33 21#include "otx2_ptp.h"
4c236d5d 22#include "cn10k.h"
31a97460 23#include <rvu_trace.h>
16547577 24
facede82
SS		 25#define DRV_NAME "rvu_nicpf"
26#define DRV_STRING "Marvell RVU NIC Physical Function Driver"
16547577
SG		 27
28/* Supported devices */
29static const struct pci_device_id otx2_pf_id_table[] = {
30 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
31 { 0, } /* end of table */
32};
33
fc992e33 34MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
16547577
SG		 35MODULE_DESCRIPTION(DRV_STRING);
36MODULE_LICENSE("GPL v2");
16547577
SG		 37MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
38
b1dc2040
HK		 39static void otx2_vf_link_event_task(struct work_struct *work);
40
5a6d7c9d
SG		 41enum {
42 TYPE_PFAF,
43 TYPE_PFVF,
44};
45
c9c12d33
AM		 46static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable);
47static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable);
48
34bfe0eb
SG		 49static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
50{
51 bool if_up = netif_running(netdev);
52 int err = 0;
53
54 if (if_up)
55 otx2_stop(netdev);
56
57 netdev_info(netdev, "Changing MTU from %d to %d\n",
58 netdev->mtu, new_mtu);
59 netdev->mtu = new_mtu;
60
61 if (if_up)
62 err = otx2_open(netdev);
63
64 return err;
65}
66
547d20f1
G		 67static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
68{
69 int irq, vfs = pf->total_vfs;
70
71 /* Disable VFs ME interrupts */
72 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
74 free_irq(irq, pf);
75
76 /* Disable VFs FLR interrupts */
77 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
79 free_irq(irq, pf);
80
81 if (vfs <= 64)
82 return;
83
84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
86 free_irq(irq, pf);
87
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
90 free_irq(irq, pf);
91}
92
93static void otx2_flr_wq_destroy(struct otx2_nic *pf)
94{
95 if (!pf->flr_wq)
96 return;
97 destroy_workqueue(pf->flr_wq);
98 pf->flr_wq = NULL;
99 devm_kfree(pf->dev, pf->flr_wrk);
100}
101
102static void otx2_flr_handler(struct work_struct *work)
103{
104 struct flr_work *flrwork = container_of(work, struct flr_work, work);
105 struct otx2_nic *pf = flrwork->pf;
4c3212f5 106 struct mbox *mbox = &pf->mbox;
547d20f1
G		 107 struct msg_req *req;
108 int vf, reg = 0;
109
110 vf = flrwork - pf->flr_wrk;
111
4c3212f5
SG		 112 mutex_lock(&mbox->lock);
113 req = otx2_mbox_alloc_msg_vf_flr(mbox);
547d20f1 114 if (!req) {
4c3212f5 115 mutex_unlock(&mbox->lock);
547d20f1
G		 116 return;
117 }
118 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
119 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
120
121 if (!otx2_sync_mbox_msg(&pf->mbox)) {
122 if (vf >= 64) {
123 reg = 1;
124 vf = vf - 64;
125 }
126 /* clear transcation pending bit */
127 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
128 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
129 }
130
4c3212f5 131 mutex_unlock(&mbox->lock);
547d20f1
G		 132}
133
134static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
135{
136 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
137 int reg, dev, vf, start_vf, num_reg = 1;
138 u64 intr;
139
140 if (pf->total_vfs > 64)
141 num_reg = 2;
142
143 for (reg = 0; reg < num_reg; reg++) {
144 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
145 if (!intr)
146 continue;
147 start_vf = 64 * reg;
148 for (vf = 0; vf < 64; vf++) {
149 if (!(intr & BIT_ULL(vf)))
150 continue;
151 dev = vf + start_vf;
152 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
153 /* Clear interrupt */
154 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
155 /* Disable the interrupt */
156 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
157 BIT_ULL(vf));
158 }
159 }
160 return IRQ_HANDLED;
161}
162
163static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
164{
165 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
166 int vf, reg, num_reg = 1;
167 u64 intr;
168
169 if (pf->total_vfs > 64)
170 num_reg = 2;
171
172 for (reg = 0; reg < num_reg; reg++) {
173 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
174 if (!intr)
175 continue;
176 for (vf = 0; vf < 64; vf++) {
177 if (!(intr & BIT_ULL(vf)))
178 continue;
179 /* clear trpend bit */
180 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
181 /* clear interrupt */
182 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
183 }
184 }
185 return IRQ_HANDLED;
186}
187
188static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
189{
190 struct otx2_hw *hw = &pf->hw;
191 char *irq_name;
192 int ret;
193
194 /* Register ME interrupt handler*/
195 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
196 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
197 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
198 otx2_pf_me_intr_handler, 0, irq_name, pf);
199 if (ret) {
200 dev_err(pf->dev,
201 "RVUPF: IRQ registration failed for ME0\n");
202 }
203
204 /* Register FLR interrupt handler */
205 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
206 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
207 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
208 otx2_pf_flr_intr_handler, 0, irq_name, pf);
209 if (ret) {
210 dev_err(pf->dev,
211 "RVUPF: IRQ registration failed for FLR0\n");
212 return ret;
213 }
214
215 if (numvfs > 64) {
216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
218 rvu_get_pf(pf->pcifunc));
219 ret = request_irq(pci_irq_vector
220 (pf->pdev, RVU_PF_INT_VEC_VFME1),
221 otx2_pf_me_intr_handler, 0, irq_name, pf);
222 if (ret) {
223 dev_err(pf->dev,
224 "RVUPF: IRQ registration failed for ME1\n");
225 }
226 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
227 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
228 rvu_get_pf(pf->pcifunc));
229 ret = request_irq(pci_irq_vector
230 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
231 otx2_pf_flr_intr_handler, 0, irq_name, pf);
232 if (ret) {
233 dev_err(pf->dev,
234 "RVUPF: IRQ registration failed for FLR1\n");
235 return ret;
236 }
237 }
238
239 /* Enable ME interrupt for all VFs*/
240 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
241 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
242
243 /* Enable FLR interrupt for all VFs*/
244 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
245 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
246
247 if (numvfs > 64) {
248 numvfs -= 64;
249
250 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
251 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
252 INTR_MASK(numvfs));
253
254 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
255 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
256 INTR_MASK(numvfs));
257 }
258 return 0;
259}
260
261static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
262{
263 int vf;
264
265 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq",
266 WQ_UNBOUND | WQ_HIGHPRI, 1);
267 if (!pf->flr_wq)
268 return -ENOMEM;
269
270 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
271 sizeof(struct flr_work), GFP_KERNEL);
272 if (!pf->flr_wrk) {
273 destroy_workqueue(pf->flr_wq);
274 return -ENOMEM;
275 }
276
277 for (vf = 0; vf < num_vfs; vf++) {
278 pf->flr_wrk[vf].pf = pf;
279 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
280 }
281
282 return 0;
283}
284
5a6d7c9d
SG		 285static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
286 int first, int mdevs, u64 intr, int type)
287{
288 struct otx2_mbox_dev *mdev;
289 struct otx2_mbox *mbox;
290 struct mbox_hdr *hdr;
291 int i;
292
293 for (i = first; i < mdevs; i++) {
294 /* start from 0 */
295 if (!(intr & BIT_ULL(i - first)))
296 continue;
297
298 mbox = &mw->mbox;
299 mdev = &mbox->dev[i];
300 if (type == TYPE_PFAF)
301 otx2_sync_mbox_bbuf(mbox, i);
302 hdr = mdev->mbase + mbox->rx_start;
303 /* The hdr->num_msgs is set to zero immediately in the interrupt
304 * handler to ensure that it holds a correct value next time
305 * when the interrupt handler is called.
306 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
307 * pf>mbox.up_num_msgs holds the data for use in
308 * pfaf_mbox_up_handler.
309 */
310 if (hdr->num_msgs) {
311 mw[i].num_msgs = hdr->num_msgs;
312 hdr->num_msgs = 0;
313 if (type == TYPE_PFAF)
314 memset(mbox->hwbase + mbox->rx_start, 0,
315 ALIGN(sizeof(struct mbox_hdr),
316 sizeof(u64)));
317
318 queue_work(mbox_wq, &mw[i].mbox_wrk);
319 }
320
321 mbox = &mw->mbox_up;
322 mdev = &mbox->dev[i];
323 if (type == TYPE_PFAF)
324 otx2_sync_mbox_bbuf(mbox, i);
325 hdr = mdev->mbase + mbox->rx_start;
326 if (hdr->num_msgs) {
327 mw[i].up_num_msgs = hdr->num_msgs;
328 hdr->num_msgs = 0;
329 if (type == TYPE_PFAF)
330 memset(mbox->hwbase + mbox->rx_start, 0,
331 ALIGN(sizeof(struct mbox_hdr),
332 sizeof(u64)));
333
334 queue_work(mbox_wq, &mw[i].mbox_up_wrk);
335 }
336 }
337}
338
d424b6c0
SG		 339static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
340 struct otx2_mbox *pfvf_mbox, void *bbuf_base,
341 int devid)
342{
343 struct otx2_mbox_dev *src_mdev = mdev;
344 int offset;
345
346 /* Msgs are already copied, trigger VF's mbox irq */
347 smp_wmb();
348
349 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
350 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
351
352 /* Restore VF's mbox bounce buffer region address */
353 src_mdev->mbase = bbuf_base;
354}
355
356static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
357 struct otx2_mbox *src_mbox,
358 int dir, int vf, int num_msgs)
359{
360 struct otx2_mbox_dev *src_mdev, *dst_mdev;
361 struct mbox_hdr *mbox_hdr;
362 struct mbox_hdr *req_hdr;
363 struct mbox *dst_mbox;
364 int dst_size, err;
365
366 if (dir == MBOX_DIR_PFAF) {
367 /* Set VF's mailbox memory as PF's bounce buffer memory, so
368 * that explicit copying of VF's msgs to PF=>AF mbox region
369 * and AF=>PF responses to VF's mbox region can be avoided.
370 */
371 src_mdev = &src_mbox->dev[vf];
372 mbox_hdr = src_mbox->hwbase +
373 src_mbox->rx_start + (vf * MBOX_SIZE);
374
375 dst_mbox = &pf->mbox;
376 dst_size = dst_mbox->mbox.tx_size -
377 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
66a5209b
HK		 378 /* Check if msgs fit into destination area and has valid size */
379 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size)
d424b6c0
SG		 380 return -EINVAL;
381
382 dst_mdev = &dst_mbox->mbox.dev[0];
383
4c3212f5 384 mutex_lock(&pf->mbox.lock);
d424b6c0
SG		 385 dst_mdev->mbase = src_mdev->mbase;
386 dst_mdev->msg_size = mbox_hdr->msg_size;
387 dst_mdev->num_msgs = num_msgs;
388 err = otx2_sync_mbox_msg(dst_mbox);
e9261c96
SS		 389 /* Error code -EIO indicate there is a communication failure
390 * to the AF. Rest of the error codes indicate that AF processed
391 * VF messages and set the error codes in response messages
392 * (if any) so simply forward responses to VF.
393 */
394 if (err == -EIO) {
d424b6c0
SG		 395 dev_warn(pf->dev,
396 "AF not responding to VF%d messages\n", vf);
397 /* restore PF mbase and exit */
398 dst_mdev->mbase = pf->mbox.bbuf_base;
4c3212f5 399 mutex_unlock(&pf->mbox.lock);
d424b6c0
SG		 400 return err;
401 }
402 /* At this point, all the VF messages sent to AF are acked
403 * with proper responses and responses are copied to VF
404 * mailbox hence raise interrupt to VF.
405 */
406 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
407 dst_mbox->mbox.rx_start);
408 req_hdr->num_msgs = num_msgs;
409
410 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
411 pf->mbox.bbuf_base, vf);
4c3212f5 412 mutex_unlock(&pf->mbox.lock);
d424b6c0
SG		 413 } else if (dir == MBOX_DIR_PFVF_UP) {
414 src_mdev = &src_mbox->dev[0];
415 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
416 req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
417 src_mbox->rx_start);
418 req_hdr->num_msgs = num_msgs;
419
420 dst_mbox = &pf->mbox_pfvf[0];
421 dst_size = dst_mbox->mbox_up.tx_size -
422 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
423 /* Check if msgs fit into destination area */
424 if (mbox_hdr->msg_size > dst_size)
425 return -EINVAL;
426
427 dst_mdev = &dst_mbox->mbox_up.dev[vf];
428 dst_mdev->mbase = src_mdev->mbase;
429 dst_mdev->msg_size = mbox_hdr->msg_size;
430 dst_mdev->num_msgs = mbox_hdr->num_msgs;
431 err = otx2_sync_mbox_up_msg(dst_mbox, vf);
432 if (err) {
433 dev_warn(pf->dev,
434 "VF%d is not responding to mailbox\n", vf);
435 return err;
436 }
437 } else if (dir == MBOX_DIR_VFPF_UP) {
438 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
439 src_mbox->rx_start);
440 req_hdr->num_msgs = num_msgs;
441 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
442 &pf->mbox.mbox_up,
443 pf->mbox_pfvf[vf].bbuf_base,
444 0);
445 }
446
447 return 0;
448}
449
450static void otx2_pfvf_mbox_handler(struct work_struct *work)
451{
452 struct mbox_msghdr *msg = NULL;
453 int offset, vf_idx, id, err;
454 struct otx2_mbox_dev *mdev;
455 struct mbox_hdr *req_hdr;
456 struct otx2_mbox *mbox;
457 struct mbox *vf_mbox;
458 struct otx2_nic *pf;
459
460 vf_mbox = container_of(work, struct mbox, mbox_wrk);
461 pf = vf_mbox->pfvf;
462 vf_idx = vf_mbox - pf->mbox_pfvf;
463
464 mbox = &pf->mbox_pfvf[0].mbox;
465 mdev = &mbox->dev[vf_idx];
466 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
467
468 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
469
470 for (id = 0; id < vf_mbox->num_msgs; id++) {
471 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
472 offset);
473
474 if (msg->sig != OTX2_MBOX_REQ_SIG)
475 goto inval_msg;
476
477 /* Set VF's number in each of the msg */
478 msg->pcifunc &= RVU_PFVF_FUNC_MASK;
479 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
480 offset = msg->next_msgoff;
481 }
482 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
483 vf_mbox->num_msgs);
484 if (err)
485 goto inval_msg;
486 return;
487
488inval_msg:
489 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
490 otx2_mbox_msg_send(mbox, vf_idx);
491}
492
493static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
494{
495 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
496 struct otx2_nic *pf = vf_mbox->pfvf;
497 struct otx2_mbox_dev *mdev;
498 int offset, id, vf_idx = 0;
499 struct mbox_hdr *rsp_hdr;
500 struct mbox_msghdr *msg;
501 struct otx2_mbox *mbox;
502
503 vf_idx = vf_mbox - pf->mbox_pfvf;
504 mbox = &pf->mbox_pfvf[0].mbox_up;
505 mdev = &mbox->dev[vf_idx];
506
507 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
508 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
509
510 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
511 msg = mdev->mbase + offset;
512
513 if (msg->id >= MBOX_MSG_MAX) {
514 dev_err(pf->dev,
515 "Mbox msg with unknown ID 0x%x\n", msg->id);
516 goto end;
517 }
518
519 if (msg->sig != OTX2_MBOX_RSP_SIG) {
520 dev_err(pf->dev,
521 "Mbox msg with wrong signature %x, ID 0x%x\n",
522 msg->sig, msg->id);
523 goto end;
524 }
525
526 switch (msg->id) {
527 case MBOX_MSG_CGX_LINK_EVENT:
528 break;
529 default:
530 if (msg->rc)
531 dev_err(pf->dev,
532 "Mbox msg response has err %d, ID 0x%x\n",
533 msg->rc, msg->id);
534 break;
535 }
536
537end:
538 offset = mbox->rx_start + msg->next_msgoff;
66a5209b
HK		 539 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1))
540 __otx2_mbox_reset(mbox, 0);
d424b6c0
SG		 541 mdev->msgs_acked++;
542 }
d424b6c0
SG		 543}
544
545static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
546{
547 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
548 int vfs = pf->total_vfs;
549 struct mbox *mbox;
550 u64 intr;
551
552 mbox = pf->mbox_pfvf;
553 /* Handle VF interrupts */
554 if (vfs > 64) {
555 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
556 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
557 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
558 TYPE_PFVF);
559 vfs -= 64;
560 }
561
562 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
563 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
564
565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
566
31a97460
SS		 567 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr);
568
d424b6c0
SG		 569 return IRQ_HANDLED;
570}
571
572static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
573{
574 void __iomem *hwbase;
575 struct mbox *mbox;
576 int err, vf;
577 u64 base;
578
579 if (!numvfs)
580 return -EINVAL;
581
582 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
583 sizeof(struct mbox), GFP_KERNEL);
584 if (!pf->mbox_pfvf)
585 return -ENOMEM;
586
587 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox",
588 WQ_UNBOUND | WQ_HIGHPRI |
589 WQ_MEM_RECLAIM, 1);
590 if (!pf->mbox_pfvf_wq)
591 return -ENOMEM;
592
facede82
SS		 593 /* On CN10K platform, PF <-> VF mailbox region follows after
594 * PF <-> AF mailbox region.
595 */
596 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag))
597 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
598 MBOX_SIZE;
599 else
600 base = readq((void __iomem *)((u64)pf->reg_base +
601 RVU_PF_VF_BAR4_ADDR));
d424b6c0 602
facede82 603 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
d424b6c0
SG		 604 if (!hwbase) {
605 err = -ENOMEM;
606 goto free_wq;
607 }
608
609 mbox = &pf->mbox_pfvf[0];
610 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
611 MBOX_DIR_PFVF, numvfs);
612 if (err)
613 goto free_iomem;
614
615 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
616 MBOX_DIR_PFVF_UP, numvfs);
617 if (err)
618 goto free_iomem;
619
620 for (vf = 0; vf < numvfs; vf++) {
621 mbox->pfvf = pf;
622 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
623 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
624 mbox++;
625 }
626
627 return 0;
628
629free_iomem:
630 if (hwbase)
631 iounmap(hwbase);
632free_wq:
633 destroy_workqueue(pf->mbox_pfvf_wq);
634 return err;
635}
636
637static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
638{
639 struct mbox *mbox = &pf->mbox_pfvf[0];
640
641 if (!mbox)
642 return;
643
644 if (pf->mbox_pfvf_wq) {
d424b6c0
SG		 645 destroy_workqueue(pf->mbox_pfvf_wq);
646 pf->mbox_pfvf_wq = NULL;
647 }
648
649 if (mbox->mbox.hwbase)
650 iounmap(mbox->mbox.hwbase);
651
652 otx2_mbox_destroy(&mbox->mbox);
653}
654
655static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
656{
657 /* Clear PF <=> VF mailbox IRQ */
658 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
659 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
660
661 /* Enable PF <=> VF mailbox IRQ */
662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
663 if (numvfs > 64) {
664 numvfs -= 64;
665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
666 INTR_MASK(numvfs));
667 }
668}
669
670static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
671{
672 int vector;
673
674 /* Disable PF <=> VF mailbox IRQ */
675 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
676 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
677
678 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
679 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
680 free_irq(vector, pf);
681
682 if (numvfs > 64) {
683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
684 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
685 free_irq(vector, pf);
686 }
687}
688
689static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
690{
691 struct otx2_hw *hw = &pf->hw;
692 char *irq_name;
693 int err;
694
695 /* Register MBOX0 interrupt handler */
696 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
697 if (pf->pcifunc)
698 snprintf(irq_name, NAME_SIZE,
699 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
700 else
701 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
702 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
703 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
704 if (err) {
705 dev_err(pf->dev,
706 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
707 return err;
708 }
709
710 if (numvfs > 64) {
711 /* Register MBOX1 interrupt handler */
712 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
713 if (pf->pcifunc)
714 snprintf(irq_name, NAME_SIZE,
715 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
716 else
717 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
718 err = request_irq(pci_irq_vector(pf->pdev,
719 RVU_PF_INT_VEC_VFPF_MBOX1),
720 otx2_pfvf_mbox_intr_handler,
721 0, irq_name, pf);
722 if (err) {
723 dev_err(pf->dev,
724 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
725 return err;
726 }
727 }
728
729 otx2_enable_pfvf_mbox_intr(pf, numvfs);
730
731 return 0;
732}
733
5a6d7c9d
SG		 734static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
735 struct mbox_msghdr *msg)
736{
ad513ed9
TD		 737 int devid;
738
5a6d7c9d
SG		 739 if (msg->id >= MBOX_MSG_MAX) {
740 dev_err(pf->dev,
741 "Mbox msg with unknown ID 0x%x\n", msg->id);
742 return;
743 }
744
745 if (msg->sig != OTX2_MBOX_RSP_SIG) {
746 dev_err(pf->dev,
747 "Mbox msg with wrong signature %x, ID 0x%x\n",
748 msg->sig, msg->id);
749 return;
750 }
751
ad513ed9
TD		 752 /* message response heading VF */
753 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
754 if (devid) {
755 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
756 struct delayed_work *dwork;
757
758 switch (msg->id) {
759 case MBOX_MSG_NIX_LF_START_RX:
760 config->intf_down = false;
761 dwork = &config->link_event_work;
762 schedule_delayed_work(dwork, msecs_to_jiffies(100));
763 break;
764 case MBOX_MSG_NIX_LF_STOP_RX:
765 config->intf_down = true;
766 break;
767 }
768
769 return;
770 }
771
5a6d7c9d
SG		 772 switch (msg->id) {
773 case MBOX_MSG_READY:
774 pf->pcifunc = msg->pcifunc;
775 break;
05fcc9e0
SG		 776 case MBOX_MSG_MSIX_OFFSET:
777 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
778 break;
779 case MBOX_MSG_NPA_LF_ALLOC:
780 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
781 break;
782 case MBOX_MSG_NIX_LF_ALLOC:
783 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
784 break;
caa2da34
SG		 785 case MBOX_MSG_NIX_TXSCH_ALLOC:
786 mbox_handler_nix_txsch_alloc(pf,
787 (struct nix_txsch_alloc_rsp *)msg);
788 break;
75f36270
G		 789 case MBOX_MSG_NIX_BP_ENABLE:
790 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
791 break;
d45d8979
CJ		 792 case MBOX_MSG_CGX_STATS:
793 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
794 break;
d0cf9503
CJ		 795 case MBOX_MSG_CGX_FEC_STATS:
796 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg);
797 break;
5a6d7c9d
SG		 798 default:
799 if (msg->rc)
800 dev_err(pf->dev,
801 "Mbox msg response has err %d, ID 0x%x\n",
802 msg->rc, msg->id);
803 break;
804 }
805}
806
807static void otx2_pfaf_mbox_handler(struct work_struct *work)
808{
809 struct otx2_mbox_dev *mdev;
810 struct mbox_hdr *rsp_hdr;
811 struct mbox_msghdr *msg;
812 struct otx2_mbox *mbox;
813 struct mbox *af_mbox;
814 struct otx2_nic *pf;
815 int offset, id;
816
817 af_mbox = container_of(work, struct mbox, mbox_wrk);
818 mbox = &af_mbox->mbox;
819 mdev = &mbox->dev[0];
820 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
821
822 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
823 pf = af_mbox->pfvf;
824
825 for (id = 0; id < af_mbox->num_msgs; id++) {
826 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
827 otx2_process_pfaf_mbox_msg(pf, msg);
828 offset = mbox->rx_start + msg->next_msgoff;
66a5209b
HK		 829 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
830 __otx2_mbox_reset(mbox, 0);
5a6d7c9d
SG		 831 mdev->msgs_acked++;
832 }
833
5a6d7c9d
SG		 834}
835
50fe6c02
LC		 836static void otx2_handle_link_event(struct otx2_nic *pf)
837{
838 struct cgx_link_user_info *linfo = &pf->linfo;
839 struct net_device *netdev = pf->netdev;
840
841 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
842 linfo->link_up ? "UP" : "DOWN", linfo->speed,
843 linfo->full_duplex ? "Full" : "Half");
844 if (linfo->link_up) {
845 netif_carrier_on(netdev);
846 netif_tx_start_all_queues(netdev);
847 } else {
848 netif_tx_stop_all_queues(netdev);
849 netif_carrier_off(netdev);
850 }
851}
852
853int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
854 struct cgx_link_info_msg *msg,
855 struct msg_rsp *rsp)
856{
ad513ed9
TD		 857 int i;
858
50fe6c02
LC		 859 /* Copy the link info sent by AF */
860 pf->linfo = msg->link_info;
861
ad513ed9
TD		 862 /* notify VFs about link event */
863 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
864 struct otx2_vf_config *config = &pf->vf_configs[i];
865 struct delayed_work *dwork = &config->link_event_work;
866
867 if (config->intf_down)
868 continue;
869
870 schedule_delayed_work(dwork, msecs_to_jiffies(100));
871 }
872
50fe6c02
LC		 873 /* interface has not been fully configured yet */
874 if (pf->flags & OTX2_FLAG_INTF_DOWN)
875 return 0;
876
877 otx2_handle_link_event(pf);
878 return 0;
879}
880
5a6d7c9d
SG		 881static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
882 struct mbox_msghdr *req)
883{
884 /* Check if valid, if not reply with a invalid msg */
885 if (req->sig != OTX2_MBOX_REQ_SIG) {
886 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
887 return -ENODEV;
888 }
889
890 switch (req->id) {
891#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
892 case _id: { \
893 struct _rsp_type *rsp; \
894 int err; \
895 \
896 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
897 &pf->mbox.mbox_up, 0, \
898 sizeof(struct _rsp_type)); \
899 if (!rsp) \
900 return -ENOMEM; \
901 \
902 rsp->hdr.id = _id; \
903 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
904 rsp->hdr.pcifunc = 0; \
905 rsp->hdr.rc = 0; \
906 \
907 err = otx2_mbox_up_handler_ ## _fn_name( \
908 pf, (struct _req_type *)req, rsp); \
909 return err; \
910 }
911MBOX_UP_CGX_MESSAGES
912#undef M
913 break;
914 default:
915 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
916 return -ENODEV;
917 }
918 return 0;
919}
920
921static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
922{
923 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
924 struct otx2_mbox *mbox = &af_mbox->mbox_up;
925 struct otx2_mbox_dev *mdev = &mbox->dev[0];
926 struct otx2_nic *pf = af_mbox->pfvf;
927 int offset, id, devid = 0;
928 struct mbox_hdr *rsp_hdr;
929 struct mbox_msghdr *msg;
930
931 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
932
933 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
934
935 for (id = 0; id < af_mbox->up_num_msgs; id++) {
936 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
937
938 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
939 /* Skip processing VF's messages */
940 if (!devid)
941 otx2_process_mbox_msg_up(pf, msg);
942 offset = mbox->rx_start + msg->next_msgoff;
943 }
d424b6c0
SG		 944 if (devid) {
945 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
946 MBOX_DIR_PFVF_UP, devid - 1,
947 af_mbox->up_num_msgs);
948 return;
949 }
5a6d7c9d
SG		 950
951 otx2_mbox_msg_send(mbox, 0);
952}
953
954static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
955{
956 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
957 struct mbox *mbox;
958
959 /* Clear the IRQ */
960 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
961
962 mbox = &pf->mbox;
31a97460
SS		 963
964 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0));
965
5a6d7c9d
SG		 966 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
967
968 return IRQ_HANDLED;
969}
970
971static void otx2_disable_mbox_intr(struct otx2_nic *pf)
972{
973 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
974
975 /* Disable AF => PF mailbox IRQ */
976 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
977 free_irq(vector, pf);
978}
979
980static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
981{
982 struct otx2_hw *hw = &pf->hw;
983 struct msg_req *req;
984 char *irq_name;
985 int err;
986
987 /* Register mailbox interrupt handler */
988 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
989 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
990 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
991 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
992 if (err) {
993 dev_err(pf->dev,
994 "RVUPF: IRQ registration failed for PFAF mbox irq\n");
995 return err;
996 }
997
998 /* Enable mailbox interrupt for msgs coming from AF.
999 * First clear to avoid spurious interrupts, if any.
1000 */
1001 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
1002 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
1003
1004 if (!probe_af)
1005 return 0;
1006
1007 /* Check mailbox communication with AF */
1008 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
1009 if (!req) {
1010 otx2_disable_mbox_intr(pf);
1011 return -ENOMEM;
1012 }
1013 err = otx2_sync_mbox_msg(&pf->mbox);
1014 if (err) {
1015 dev_warn(pf->dev,
1016 "AF not responding to mailbox, deferring probe\n");
1017 otx2_disable_mbox_intr(pf);
1018 return -EPROBE_DEFER;
1019 }
1020
1021 return 0;
1022}
1023
1024static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1025{
1026 struct mbox *mbox = &pf->mbox;
1027
1028 if (pf->mbox_wq) {
5a6d7c9d
SG		 1029 destroy_workqueue(pf->mbox_wq);
1030 pf->mbox_wq = NULL;
1031 }
1032
1033 if (mbox->mbox.hwbase)
1034 iounmap((void __iomem *)mbox->mbox.hwbase);
1035
1036 otx2_mbox_destroy(&mbox->mbox);
1037 otx2_mbox_destroy(&mbox->mbox_up);
1038}
1039
1040static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1041{
1042 struct mbox *mbox = &pf->mbox;
1043 void __iomem *hwbase;
1044 int err;
1045
1046 mbox->pfvf = pf;
1047 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox",
1048 WQ_UNBOUND | WQ_HIGHPRI |
1049 WQ_MEM_RECLAIM, 1);
1050 if (!pf->mbox_wq)
1051 return -ENOMEM;
1052
1053 /* Mailbox is a reserved memory (in RAM) region shared between
1054 * admin function (i.e AF) and this PF, shouldn't be mapped as
1055 * device memory to allow unaligned accesses.
1056 */
1057 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
facede82 1058 MBOX_SIZE);
5a6d7c9d
SG		 1059 if (!hwbase) {
1060 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1061 err = -ENOMEM;
1062 goto exit;
1063 }
1064
1065 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1066 MBOX_DIR_PFAF, 1);
1067 if (err)
1068 goto exit;
1069
1070 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1071 MBOX_DIR_PFAF_UP, 1);
1072 if (err)
1073 goto exit;
1074
1075 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1076 if (err)
1077 goto exit;
1078
1079 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1080 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
4c3212f5 1081 mutex_init(&mbox->lock);
5a6d7c9d
SG		 1082
1083 return 0;
1084exit:
1085 otx2_pfaf_mbox_destroy(pf);
1086 return err;
1087}
1088
50fe6c02
LC		 1089static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1090{
1091 struct msg_req *msg;
1092 int err;
1093
4c3212f5 1094 mutex_lock(&pf->mbox.lock);
50fe6c02
LC		 1095 if (enable)
1096 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1097 else
1098 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1099
1100 if (!msg) {
4c3212f5 1101 mutex_unlock(&pf->mbox.lock);
50fe6c02
LC		 1102 return -ENOMEM;
1103 }
1104
1105 err = otx2_sync_mbox_msg(&pf->mbox);
4c3212f5 1106 mutex_unlock(&pf->mbox.lock);
50fe6c02
LC		 1107 return err;
1108}
1109
34bfe0eb
SG		 1110static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1111{
1112 struct msg_req *msg;
1113 int err;
1114
79d2be38
HK		 1115 if (enable && bitmap_weight(&pf->flow_cfg->dmacflt_bmap,
1116 pf->flow_cfg->dmacflt_max_flows))
1117 netdev_warn(pf->netdev,
1118 "CGX/RPM internal loopback might not work as DMAC filters are active\n");
1119
4c3212f5 1120 mutex_lock(&pf->mbox.lock);
34bfe0eb
SG		 1121 if (enable)
1122 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1123 else
1124 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1125
1126 if (!msg) {
4c3212f5 1127 mutex_unlock(&pf->mbox.lock);
34bfe0eb
SG		 1128 return -ENOMEM;
1129 }
1130
1131 err = otx2_sync_mbox_msg(&pf->mbox);
4c3212f5 1132 mutex_unlock(&pf->mbox.lock);
34bfe0eb
SG		 1133 return err;
1134}
1135
d45d8979
CJ		 1136int otx2_set_real_num_queues(struct net_device *netdev,
1137 int tx_queues, int rx_queues)
16547577
SG		 1138{
1139 int err;
1140
1141 err = netif_set_real_num_tx_queues(netdev, tx_queues);
1142 if (err) {
1143 netdev_err(netdev,
1144 "Failed to set no of Tx queues: %d\n", tx_queues);
1145 return err;
1146 }
1147
1148 err = netif_set_real_num_rx_queues(netdev, rx_queues);
1149 if (err)
1150 netdev_err(netdev,
1151 "Failed to set no of Rx queues: %d\n", rx_queues);
1152 return err;
1153}
3184fb5b 1154EXPORT_SYMBOL(otx2_set_real_num_queues);
16547577 1155
4ff7d148
G		 1156static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1157{
1158 struct otx2_nic *pf = data;
1159 u64 val, *ptr;
1160 u64 qidx = 0;
1161
1162 /* CQ */
1163 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1164 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1165 val = otx2_atomic64_add((qidx << 44), ptr);
1166
1167 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1168 (val & NIX_CQERRINT_BITS));
1169 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1170 continue;
1171
1172 if (val & BIT_ULL(42)) {
1173 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1174 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1175 } else {
1176 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1177 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1178 qidx);
1179 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1180 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1181 qidx);
1182 }
1183
1184 schedule_work(&pf->reset_task);
1185 }
1186
1187 /* SQ */
1188 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1189 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1190 val = otx2_atomic64_add((qidx << 44), ptr);
1191 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1192 (val & NIX_SQINT_BITS));
1193
1194 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42))))
1195 continue;
1196
1197 if (val & BIT_ULL(42)) {
1198 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1199 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1200 } else {
1201 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) {
1202 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx",
1203 qidx,
1204 otx2_read64(pf,
1205 NIX_LF_SQ_OP_ERR_DBG));
1206 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG,
1207 BIT_ULL(44));
1208 }
1209 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
1210 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n",
1211 qidx,
1212 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG));
1213 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG,
1214 BIT_ULL(44));
1215 }
1216 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) {
1217 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx",
1218 qidx,
1219 otx2_read64(pf,
1220 NIX_LF_SEND_ERR_DBG));
1221 otx2_write64(pf, NIX_LF_SEND_ERR_DBG,
1222 BIT_ULL(44));
1223 }
1224 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1225 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1226 qidx);
1227 }
1228
1229 schedule_work(&pf->reset_task);
1230 }
1231
1232 return IRQ_HANDLED;
1233}
1234
04a21ef3
SG		 1235static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1236{
1237 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1238 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1239 int qidx = cq_poll->cint_idx;
1240
1241 /* Disable interrupts.
1242 *
1243 * Completion interrupts behave in a level-triggered interrupt
1244 * fashion, and hence have to be cleared only after it is serviced.
1245 */
1246 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1247
1248 /* Schedule NAPI */
1249 napi_schedule_irqoff(&cq_poll->napi);
1250
1251 return IRQ_HANDLED;
1252}
1253
1254static void otx2_disable_napi(struct otx2_nic *pf)
1255{
1256 struct otx2_qset *qset = &pf->qset;
1257 struct otx2_cq_poll *cq_poll;
1258 int qidx;
1259
1260 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1261 cq_poll = &qset->napi[qidx];
1262 napi_disable(&cq_poll->napi);
1263 netif_napi_del(&cq_poll->napi);
1264 }
1265}
1266
caa2da34
SG		 1267static void otx2_free_cq_res(struct otx2_nic *pf)
1268{
1269 struct otx2_qset *qset = &pf->qset;
1270 struct otx2_cq_queue *cq;
1271 int qidx;
1272
1273 /* Disable CQs */
1274 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1275 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1276 cq = &qset->cq[qidx];
1277 qmem_free(pf->dev, cq->cqe);
1278 }
1279}
1280
1281static void otx2_free_sq_res(struct otx2_nic *pf)
1282{
1283 struct otx2_qset *qset = &pf->qset;
1284 struct otx2_snd_queue *sq;
1285 int qidx;
1286
1287 /* Disable SQs */
1288 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1289 /* Free SQB pointers */
1290 otx2_sq_free_sqbs(pf);
1291 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) {
1292 sq = &qset->sq[qidx];
1293 qmem_free(pf->dev, sq->sqe);
86d74760 1294 qmem_free(pf->dev, sq->tso_hdrs);
3ca6c4c8 1295 kfree(sq->sg);
caa2da34
SG		 1296 kfree(sq->sqb_ptrs);
1297 }
1298}
1299
ab58a416
HK		 1300static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu)
1301{
1302 int frame_size;
1303 int total_size;
1304 int rbuf_size;
1305
1306 /* The data transferred by NIX to memory consists of actual packet
1307 * plus additional data which has timestamp and/or EDSA/HIGIG2
1308 * headers if interface is configured in corresponding modes.
1309 * NIX transfers entire data using 6 segments/buffers and writes
1310 * a CQE_RX descriptor with those segment addresses. First segment
1311 * has additional data prepended to packet. Also software omits a
1312 * headroom of 128 bytes and sizeof(struct skb_shared_info) in
1313 * each segment. Hence the total size of memory needed
1314 * to receive a packet with 'mtu' is:
1315 * frame size = mtu + additional data;
1316 * memory = frame_size + (headroom + struct skb_shared_info size) * 6;
1317 * each receive buffer size = memory / 6;
1318 */
1319 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
1320 total_size = frame_size + (OTX2_HEAD_ROOM +
1321 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) * 6;
1322 rbuf_size = total_size / 6;
1323
1324 return ALIGN(rbuf_size, 2048);
1325}
1326
caa2da34
SG		 1327static int otx2_init_hw_resources(struct otx2_nic *pf)
1328{
55307fcb 1329 struct nix_lf_free_req *free_req;
caa2da34
SG		 1330 struct mbox *mbox = &pf->mbox;
1331 struct otx2_hw *hw = &pf->hw;
1332 struct msg_req *req;
1333 int err = 0, lvl;
1334
1335 /* Set required NPA LF's pool counts
1336 * Auras and Pools are used in a 1:1 mapping,
1337 * so, aura count = pool count.
1338 */
1339 hw->rqpool_cnt = hw->rx_queues;
1340 hw->sqpool_cnt = hw->tx_queues;
1341 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1342
ab58a416
HK		 1343 pf->max_frs = pf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
1344
1345 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu);
caa2da34 1346
4c3212f5 1347 mutex_lock(&mbox->lock);
caa2da34
SG		 1348 /* NPA init */
1349 err = otx2_config_npa(pf);
1350 if (err)
1351 goto exit;
1352
1353 /* NIX init */
1354 err = otx2_config_nix(pf);
1355 if (err)
1356 goto err_free_npa_lf;
1357
75f36270
G		 1358 /* Enable backpressure */
1359 otx2_nix_config_bp(pf, true);
1360
caa2da34
SG		 1361 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1362 err = otx2_rq_aura_pool_init(pf);
1363 if (err) {
4c3212f5 1364 mutex_unlock(&mbox->lock);
caa2da34
SG		 1365 goto err_free_nix_lf;
1366 }
1367 /* Init Auras and pools used by NIX SQ, for queueing SQEs */
1368 err = otx2_sq_aura_pool_init(pf);
1369 if (err) {
4c3212f5 1370 mutex_unlock(&mbox->lock);
caa2da34
SG		 1371 goto err_free_rq_ptrs;
1372 }
1373
1374 err = otx2_txsch_alloc(pf);
1375 if (err) {
4c3212f5 1376 mutex_unlock(&mbox->lock);
caa2da34
SG		 1377 goto err_free_sq_ptrs;
1378 }
1379
1380 err = otx2_config_nix_queues(pf);
1381 if (err) {
4c3212f5 1382 mutex_unlock(&mbox->lock);
caa2da34
SG		 1383 goto err_free_txsch;
1384 }
1385 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1386 err = otx2_txschq_config(pf, lvl);
1387 if (err) {
4c3212f5 1388 mutex_unlock(&mbox->lock);
caa2da34
SG		 1389 goto err_free_nix_queues;
1390 }
1391 }
4c3212f5 1392 mutex_unlock(&mbox->lock);
caa2da34
SG		 1393 return err;
1394
1395err_free_nix_queues:
1396 otx2_free_sq_res(pf);
1397 otx2_free_cq_res(pf);
1398 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1399err_free_txsch:
1400 if (otx2_txschq_stop(pf))
1401 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__);
1402err_free_sq_ptrs:
1403 otx2_sq_free_sqbs(pf);
1404err_free_rq_ptrs:
1405 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1406 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1407 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1408 otx2_aura_pool_free(pf);
1409err_free_nix_lf:
4c3212f5 1410 mutex_lock(&mbox->lock);
55307fcb
SS		 1411 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1412 if (free_req) {
1413 free_req->flags = NIX_LF_DISABLE_FLOWS;
caa2da34
SG		 1414 if (otx2_sync_mbox_msg(mbox))
1415 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1416 }
1417err_free_npa_lf:
1418 /* Reset NPA LF */
1419 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1420 if (req) {
1421 if (otx2_sync_mbox_msg(mbox))
1422 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1423 }
1424exit:
4c3212f5 1425 mutex_unlock(&mbox->lock);
caa2da34
SG		 1426 return err;
1427}
1428
1429static void otx2_free_hw_resources(struct otx2_nic *pf)
1430{
abe02543 1431 struct otx2_qset *qset = &pf->qset;
55307fcb 1432 struct nix_lf_free_req *free_req;
caa2da34 1433 struct mbox *mbox = &pf->mbox;
abe02543 1434 struct otx2_cq_queue *cq;
caa2da34 1435 struct msg_req *req;
abe02543 1436 int qidx, err;
caa2da34
SG		 1437
1438 /* Ensure all SQE are processed */
1439 otx2_sqb_flush(pf);
1440
1441 /* Stop transmission */
1442 err = otx2_txschq_stop(pf);
1443 if (err)
1444 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n");
1445
4c3212f5 1446 mutex_lock(&mbox->lock);
75f36270
G		 1447 /* Disable backpressure */
1448 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1449 otx2_nix_config_bp(pf, false);
4c3212f5 1450 mutex_unlock(&mbox->lock);
75f36270 1451
caa2da34
SG		 1452 /* Disable RQs */
1453 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1454
abe02543
SG		 1455 /*Dequeue all CQEs */
1456 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1457 cq = &qset->cq[qidx];
1458 if (cq->cq_type == CQ_RX)
1459 otx2_cleanup_rx_cqes(pf, cq);
3ca6c4c8
SG		 1460 else
1461 otx2_cleanup_tx_cqes(pf, cq);
abe02543
SG		 1462 }
1463
caa2da34
SG		 1464 otx2_free_sq_res(pf);
1465
1466 /* Free RQ buffer pointers*/
1467 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1468
1469 otx2_free_cq_res(pf);
1470
2ca89a2c
SG		 1471 /* Free all ingress bandwidth profiles allocated */
1472 cn10k_free_all_ipolicers(pf);
1473
4c3212f5 1474 mutex_lock(&mbox->lock);
caa2da34 1475 /* Reset NIX LF */
55307fcb
SS		 1476 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1477 if (free_req) {
1478 free_req->flags = NIX_LF_DISABLE_FLOWS;
f0c2982a
NM		 1479 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN))
1480 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG;
caa2da34
SG		 1481 if (otx2_sync_mbox_msg(mbox))
1482 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1483 }
4c3212f5 1484 mutex_unlock(&mbox->lock);
caa2da34
SG		 1485
1486 /* Disable NPA Pool and Aura hw context */
1487 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1488 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1489 otx2_aura_pool_free(pf);
1490
4c3212f5 1491 mutex_lock(&mbox->lock);
caa2da34
SG		 1492 /* Reset NPA LF */
1493 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1494 if (req) {
1495 if (otx2_sync_mbox_msg(mbox))
1496 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1497 }
4c3212f5 1498 mutex_unlock(&mbox->lock);
caa2da34
SG		 1499}
1500
7ea8e6ee
RB		 1501static void otx2_do_set_rx_mode(struct otx2_nic *pf)
1502{
1503 struct net_device *netdev = pf->netdev;
1504 struct nix_rx_mode *req;
1505 bool promisc = false;
1506
1507 if (!(netdev->flags & IFF_UP))
1508 return;
1509
1510 if ((netdev->flags & IFF_PROMISC) ||
1511 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) {
1512 promisc = true;
1513 }
1514
1515 /* Write unicast address to mcam entries or del from mcam */
1516 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT)
1517 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter);
1518
1519 mutex_lock(&pf->mbox.lock);
1520 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1521 if (!req) {
1522 mutex_unlock(&pf->mbox.lock);
1523 return;
1524 }
1525
1526 req->mode = NIX_RX_MODE_UCAST;
1527
1528 if (promisc)
1529 req->mode |= NIX_RX_MODE_PROMISC;
1530 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1531 req->mode |= NIX_RX_MODE_ALLMULTI;
1532
1533 req->mode |= NIX_RX_MODE_USE_MCE;
1534
1535 otx2_sync_mbox_msg(&pf->mbox);
1536 mutex_unlock(&pf->mbox.lock);
1537}
1538
34bfe0eb 1539int otx2_open(struct net_device *netdev)
16547577 1540{
05fcc9e0 1541 struct otx2_nic *pf = netdev_priv(netdev);
04a21ef3 1542 struct otx2_cq_poll *cq_poll = NULL;
caa2da34 1543 struct otx2_qset *qset = &pf->qset;
04a21ef3
SG		 1544 int err = 0, qidx, vec;
1545 char *irq_name;
05fcc9e0 1546
16547577
SG		 1547 netif_carrier_off(netdev);
1548
05fcc9e0 1549 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues;
04a21ef3
SG		 1550 /* RQ and SQs are mapped to different CQs,
1551 * so find out max CQ IRQs (i.e CINTs) needed.
1552 */
1553 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues);
1554 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1555 if (!qset->napi)
1556 return -ENOMEM;
05fcc9e0 1557
caa2da34
SG		 1558 /* CQ size of RQ */
1559 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1560 /* CQ size of SQ */
1561 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1562
1563 err = -ENOMEM;
1564 qset->cq = kcalloc(pf->qset.cq_cnt,
1565 sizeof(struct otx2_cq_queue), GFP_KERNEL);
1566 if (!qset->cq)
1567 goto err_free_mem;
1568
1569 qset->sq = kcalloc(pf->hw.tx_queues,
1570 sizeof(struct otx2_snd_queue), GFP_KERNEL);
1571 if (!qset->sq)
1572 goto err_free_mem;
1573
d45d8979
CJ		 1574 qset->rq = kcalloc(pf->hw.rx_queues,
1575 sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1576 if (!qset->rq)
1577 goto err_free_mem;
1578
caa2da34 1579 err = otx2_init_hw_resources(pf);
05fcc9e0 1580 if (err)
caa2da34 1581 goto err_free_mem;
05fcc9e0 1582
04a21ef3
SG		 1583 /* Register NAPI handler */
1584 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1585 cq_poll = &qset->napi[qidx];
1586 cq_poll->cint_idx = qidx;
1587 /* RQ0 & SQ0 are mapped to CINT0 and so on..
1588 * 'cq_ids[0]' points to RQ's CQ and
1589 * 'cq_ids[1]' points to SQ's CQ and
1590 */
1591 cq_poll->cq_ids[CQ_RX] =
1592 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1593 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1594 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1595 cq_poll->dev = (void *)pf;
1596 netif_napi_add(netdev, &cq_poll->napi,
1597 otx2_napi_handler, NAPI_POLL_WEIGHT);
1598 napi_enable(&cq_poll->napi);
1599 }
1600
34bfe0eb
SG		 1601 /* Set maximum frame size allowed in HW */
1602 err = otx2_hw_set_mtu(pf, netdev->mtu);
1603 if (err)
1604 goto err_disable_napi;
1605
dc1a9bf2
SG		 1606 /* Setup segmentation algorithms, if failed, clear offload capability */
1607 otx2_setup_segmentation(pf);
1608
85069e95
SG		 1609 /* Initialize RSS */
1610 err = otx2_rss_init(pf);
1611 if (err)
1612 goto err_disable_napi;
1613
4ff7d148
G		 1614 /* Register Queue IRQ handlers */
1615 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1616 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1617
1618 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1619
1620 err = request_irq(pci_irq_vector(pf->pdev, vec),
1621 otx2_q_intr_handler, 0, irq_name, pf);
1622 if (err) {
1623 dev_err(pf->dev,
1624 "RVUPF%d: IRQ registration failed for QERR\n",
1625 rvu_get_pf(pf->pcifunc));
1626 goto err_disable_napi;
1627 }
1628
1629 /* Enable QINT IRQ */
1630 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1631
04a21ef3
SG		 1632 /* Register CQ IRQ handlers */
1633 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1634 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1635 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1636
1637 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1638 qidx);
1639
1640 err = request_irq(pci_irq_vector(pf->pdev, vec),
1641 otx2_cq_intr_handler, 0, irq_name,
1642 &qset->napi[qidx]);
1643 if (err) {
1644 dev_err(pf->dev,
1645 "RVUPF%d: IRQ registration failed for CQ%d\n",
1646 rvu_get_pf(pf->pcifunc), qidx);
1647 goto err_free_cints;
1648 }
1649 vec++;
1650
1651 otx2_config_irq_coalescing(pf, qidx);
1652
1653 /* Enable CQ IRQ */
1654 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1655 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1656 }
1657
1658 otx2_set_cints_affinity(pf);
1659
fd9d7859
HK		 1660 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
1661 otx2_enable_rxvlan(pf, true);
1662
c9c12d33
AM		 1663 /* When reinitializing enable time stamping if it is enabled before */
1664 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1665 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1666 otx2_config_hw_tx_tstamp(pf, true);
1667 }
1668 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1669 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1670 otx2_config_hw_rx_tstamp(pf, true);
1671 }
1672
50fe6c02
LC		 1673 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1674 /* 'intf_down' may be checked on any cpu */
1675 smp_wmb();
1676
1677 /* we have already received link status notification */
1678 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1679 otx2_handle_link_event(pf);
1680
3184fb5b
TD		 1681 /* Restore pause frame settings */
1682 otx2_config_pause_frm(pf);
1683
79d2be38
HK		 1684 /* Install DMAC Filters */
1685 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
1686 otx2_dmacflt_reinstall_flows(pf);
1687
50fe6c02
LC		 1688 err = otx2_rxtx_enable(pf, true);
1689 if (err)
1ea0166d 1690 goto err_tx_stop_queues;
50fe6c02 1691
7ea8e6ee
RB		 1692 otx2_do_set_rx_mode(pf);
1693
caa2da34 1694 return 0;
04a21ef3 1695
1ea0166d
HK		 1696err_tx_stop_queues:
1697 netif_tx_stop_all_queues(netdev);
1698 netif_carrier_off(netdev);
69f0aeb1 1699 pf->flags |= OTX2_FLAG_INTF_DOWN;
04a21ef3
SG		 1700err_free_cints:
1701 otx2_free_cints(pf, qidx);
4ff7d148
G		 1702 vec = pci_irq_vector(pf->pdev,
1703 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1704 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1705 synchronize_irq(vec);
1706 free_irq(vec, pf);
34bfe0eb 1707err_disable_napi:
04a21ef3
SG		 1708 otx2_disable_napi(pf);
1709 otx2_free_hw_resources(pf);
caa2da34
SG		 1710err_free_mem:
1711 kfree(qset->sq);
1712 kfree(qset->cq);
d45d8979 1713 kfree(qset->rq);
04a21ef3 1714 kfree(qset->napi);
caa2da34 1715 return err;
16547577 1716}
3184fb5b 1717EXPORT_SYMBOL(otx2_open);
16547577 1718
34bfe0eb 1719int otx2_stop(struct net_device *netdev)
16547577 1720{
caa2da34 1721 struct otx2_nic *pf = netdev_priv(netdev);
04a21ef3 1722 struct otx2_cq_poll *cq_poll = NULL;
caa2da34 1723 struct otx2_qset *qset = &pf->qset;
f12098ce 1724 struct otx2_rss_info *rss;
4ff7d148 1725 int qidx, vec, wrk;
04a21ef3 1726
69f0aeb1
G		 1727 /* If the DOWN flag is set resources are already freed */
1728 if (pf->flags & OTX2_FLAG_INTF_DOWN)
1729 return 0;
1730
04a21ef3
SG		 1731 netif_carrier_off(netdev);
1732 netif_tx_stop_all_queues(netdev);
1733
50fe6c02
LC		 1734 pf->flags |= OTX2_FLAG_INTF_DOWN;
1735 /* 'intf_down' may be checked on any cpu */
1736 smp_wmb();
1737
1738 /* First stop packet Rx/Tx */
1739 otx2_rxtx_enable(pf, false);
1740
f12098ce
G		 1741 /* Clear RSS enable flag */
1742 rss = &pf->hw.rss_info;
1743 rss->enable = false;
1744
4ff7d148
G		 1745 /* Cleanup Queue IRQ */
1746 vec = pci_irq_vector(pf->pdev,
1747 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1748 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1749 synchronize_irq(vec);
1750 free_irq(vec, pf);
1751
04a21ef3
SG		 1752 /* Cleanup CQ NAPI and IRQ */
1753 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1754 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1755 /* Disable interrupt */
1756 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1757
1758 synchronize_irq(pci_irq_vector(pf->pdev, vec));
1759
1760 cq_poll = &qset->napi[qidx];
1761 napi_synchronize(&cq_poll->napi);
1762 vec++;
1763 }
1764
1765 netif_tx_disable(netdev);
caa2da34
SG		 1766
1767 otx2_free_hw_resources(pf);
04a21ef3
SG		 1768 otx2_free_cints(pf, pf->hw.cint_cnt);
1769 otx2_disable_napi(pf);
1770
1771 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1772 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
caa2da34 1773
4ff7d148
G		 1774 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1775 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1776 devm_kfree(pf->dev, pf->refill_wrk);
1777
caa2da34
SG		 1778 kfree(qset->sq);
1779 kfree(qset->cq);
d45d8979 1780 kfree(qset->rq);
04a21ef3 1781 kfree(qset->napi);
caa2da34
SG		 1782 /* Do not clear RQ/SQ ringsize settings */
1783 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0,
1784 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt));
16547577
SG		 1785 return 0;
1786}
3184fb5b 1787EXPORT_SYMBOL(otx2_stop);
16547577 1788
3ca6c4c8
SG		 1789static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1790{
1791 struct otx2_nic *pf = netdev_priv(netdev);
1792 int qidx = skb_get_queue_mapping(skb);
1793 struct otx2_snd_queue *sq;
1794 struct netdev_queue *txq;
1795
86d74760
SG		 1796 /* Check for minimum and maximum packet length */
1797 if (skb->len <= ETH_HLEN ||
1798 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) {
3ca6c4c8
SG		 1799 dev_kfree_skb(skb);
1800 return NETDEV_TX_OK;
1801 }
1802
1803 sq = &pf->qset.sq[qidx];
1804 txq = netdev_get_tx_queue(netdev, qidx);
1805
1806 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1807 netif_tx_stop_queue(txq);
1808
1809 /* Check again, incase SQBs got freed up */
1810 smp_mb();
1811 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1812 > sq->sqe_thresh)
1813 netif_tx_wake_queue(txq);
1814
1815 return NETDEV_TX_BUSY;
1816 }
1817
1818 return NETDEV_TX_OK;
1819}
1820
1d4d9e42
NM		 1821static netdev_features_t otx2_fix_features(struct net_device *dev,
1822 netdev_features_t features)
1823{
2e2a8126
SG		 1824 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1825 features |= NETIF_F_HW_VLAN_STAG_RX;
1826 else
1827 features &= ~NETIF_F_HW_VLAN_STAG_RX;
1d4d9e42
NM		 1828
1829 return features;
1830}
1831
34bfe0eb
SG		 1832static void otx2_set_rx_mode(struct net_device *netdev)
1833{
1834 struct otx2_nic *pf = netdev_priv(netdev);
e99b7c84
SG		 1835
1836 queue_work(pf->otx2_wq, &pf->rx_mode_work);
1837}
1838
7ea8e6ee 1839static void otx2_rx_mode_wrk_handler(struct work_struct *work)
e99b7c84
SG		 1840{
1841 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
63ee5157 1842
7ea8e6ee 1843 otx2_do_set_rx_mode(pf);
34bfe0eb
SG		 1844}
1845
1846static int otx2_set_features(struct net_device *netdev,
1847 netdev_features_t features)
1848{
1849 netdev_features_t changed = features ^ netdev->features;
f0a1913f 1850 bool ntuple = !!(features & NETIF_F_NTUPLE);
34bfe0eb 1851 struct otx2_nic *pf = netdev_priv(netdev);
2e2a8126 1852 bool tc = !!(features & NETIF_F_HW_TC);
34bfe0eb
SG		 1853
1854 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
1855 return otx2_cgx_config_loopback(pf,
1856 features & NETIF_F_LOOPBACK);
f0a1913f 1857
fd9d7859
HK		 1858 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev))
1859 return otx2_enable_rxvlan(pf,
1860 features & NETIF_F_HW_VLAN_CTAG_RX);
1861
f0a1913f
SS		 1862 if ((changed & NETIF_F_NTUPLE) && !ntuple)
1863 otx2_destroy_ntuple_flows(pf);
1864
a515e5b5
SG		 1865 if ((changed & NETIF_F_NTUPLE) && ntuple) {
1866 if (!pf->flow_cfg->max_flows) {
1867 netdev_err(netdev,
1868 "Can't enable NTUPLE, MCAM entries not allocated\n");
1869 return -EINVAL;
1870 }
1871 }
1872
1873 if ((changed & NETIF_F_HW_TC) && tc) {
1874 if (!pf->flow_cfg->max_flows) {
1875 netdev_err(netdev,
1876 "Can't enable TC, MCAM entries not allocated\n");
1877 return -EINVAL;
1878 }
1879 }
1880
2e2a8126
SG		 1881 if ((changed & NETIF_F_HW_TC) && !tc &&
1882 pf->flow_cfg && pf->flow_cfg->nr_flows) {
1d4d9e42
NM		 1883 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
1884 return -EBUSY;
1885 }
1886
2e2a8126
SG		 1887 if ((changed & NETIF_F_NTUPLE) && ntuple &&
1888 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) {
1889 netdev_err(netdev,
1890 "Can't enable NTUPLE when TC is active, disable TC and retry\n");
1891 return -EINVAL;
1892 }
1893
1894 if ((changed & NETIF_F_HW_TC) && tc &&
1895 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) {
1896 netdev_err(netdev,
1897 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n");
1898 return -EINVAL;
1899 }
1900
34bfe0eb
SG		 1901 return 0;
1902}
1903
4ff7d148
G		 1904static void otx2_reset_task(struct work_struct *work)
1905{
1906 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
1907
1908 if (!netif_running(pf->netdev))
1909 return;
1910
948a6633 1911 rtnl_lock();
4ff7d148
G		 1912 otx2_stop(pf->netdev);
1913 pf->reset_count++;
1914 otx2_open(pf->netdev);
1915 netif_trans_update(pf->netdev);
948a6633 1916 rtnl_unlock();
4ff7d148
G		 1917}
1918
c9c12d33
AM		 1919static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable)
1920{
1921 struct msg_req *req;
1922 int err;
1923
1924 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable)
1925 return 0;
1926
1927 mutex_lock(&pfvf->mbox.lock);
1928 if (enable)
1929 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox);
1930 else
1931 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox);
1932 if (!req) {
1933 mutex_unlock(&pfvf->mbox.lock);
1934 return -ENOMEM;
1935 }
1936
1937 err = otx2_sync_mbox_msg(&pfvf->mbox);
1938 if (err) {
1939 mutex_unlock(&pfvf->mbox.lock);
1940 return err;
1941 }
1942
1943 mutex_unlock(&pfvf->mbox.lock);
1944 if (enable)
1945 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED;
1946 else
1947 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1948 return 0;
1949}
1950
1951static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable)
1952{
1953 struct msg_req *req;
1954 int err;
1955
1956 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable)
1957 return 0;
1958
1959 mutex_lock(&pfvf->mbox.lock);
1960 if (enable)
1961 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox);
1962 else
1963 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox);
1964 if (!req) {
1965 mutex_unlock(&pfvf->mbox.lock);
1966 return -ENOMEM;
1967 }
1968
1969 err = otx2_sync_mbox_msg(&pfvf->mbox);
1970 if (err) {
1971 mutex_unlock(&pfvf->mbox.lock);
1972 return err;
1973 }
1974
1975 mutex_unlock(&pfvf->mbox.lock);
1976 if (enable)
1977 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED;
1978 else
1979 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1980 return 0;
1981}
1982
1983static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
1984{
1985 struct otx2_nic *pfvf = netdev_priv(netdev);
1986 struct hwtstamp_config config;
1987
1988 if (!pfvf->ptp)
1989 return -ENODEV;
1990
1991 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1992 return -EFAULT;
1993
1994 /* reserved for future extensions */
1995 if (config.flags)
1996 return -EINVAL;
1997
1998 switch (config.tx_type) {
1999 case HWTSTAMP_TX_OFF:
2000 otx2_config_hw_tx_tstamp(pfvf, false);
2001 break;
2002 case HWTSTAMP_TX_ON:
2003 otx2_config_hw_tx_tstamp(pfvf, true);
2004 break;
2005 default:
2006 return -ERANGE;
2007 }
2008
2009 switch (config.rx_filter) {
2010 case HWTSTAMP_FILTER_NONE:
2011 otx2_config_hw_rx_tstamp(pfvf, false);
2012 break;
2013 case HWTSTAMP_FILTER_ALL:
2014 case HWTSTAMP_FILTER_SOME:
2015 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2016 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2017 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2018 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2019 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2020 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2021 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2022 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2023 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2024 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2025 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2026 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2027 otx2_config_hw_rx_tstamp(pfvf, true);
2028 config.rx_filter = HWTSTAMP_FILTER_ALL;
2029 break;
2030 default:
2031 return -ERANGE;
2032 }
2033
2034 memcpy(&pfvf->tstamp, &config, sizeof(config));
2035
2036 return copy_to_user(ifr->ifr_data, &config,
2037 sizeof(config)) ? -EFAULT : 0;
2038}
2039
2040static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
2041{
2042 struct otx2_nic *pfvf = netdev_priv(netdev);
2043 struct hwtstamp_config *cfg = &pfvf->tstamp;
2044
2045 switch (cmd) {
2046 case SIOCSHWTSTAMP:
2047 return otx2_config_hwtstamp(netdev, req);
2048 case SIOCGHWTSTAMP:
2049 return copy_to_user(req->ifr_data, cfg,
2050 sizeof(*cfg)) ? -EFAULT : 0;
2051 default:
2052 return -EOPNOTSUPP;
2053 }
2054}
2055
f0c2982a
NM		 2056static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac)
2057{
2058 struct npc_install_flow_req *req;
2059 int err;
2060
2061 mutex_lock(&pf->mbox.lock);
2062 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2063 if (!req) {
2064 err = -ENOMEM;
2065 goto out;
2066 }
2067
2068 ether_addr_copy(req->packet.dmac, mac);
2069 eth_broadcast_addr((u8 *)&req->mask.dmac);
2070 req->features = BIT_ULL(NPC_DMAC);
2071 req->channel = pf->hw.rx_chan_base;
2072 req->intf = NIX_INTF_RX;
2073 req->default_rule = 1;
2074 req->append = 1;
2075 req->vf = vf + 1;
2076 req->op = NIX_RX_ACTION_DEFAULT;
2077
2078 err = otx2_sync_mbox_msg(&pf->mbox);
2079out:
2080 mutex_unlock(&pf->mbox.lock);
2081 return err;
2082}
2083
2084static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2085{
2086 struct otx2_nic *pf = netdev_priv(netdev);
2087 struct pci_dev *pdev = pf->pdev;
2088 struct otx2_vf_config *config;
2089 int ret;
2090
2091 if (!netif_running(netdev))
2092 return -EAGAIN;
2093
b1dc2040 2094 if (vf >= pf->total_vfs)
f0c2982a
NM		 2095 return -EINVAL;
2096
2097 if (!is_valid_ether_addr(mac))
2098 return -EINVAL;
2099
2100 config = &pf->vf_configs[vf];
2101 ether_addr_copy(config->mac, mac);
2102
2103 ret = otx2_do_set_vf_mac(pf, vf, mac);
2104 if (ret == 0)
b1dc2040
HK		 2105 dev_info(&pdev->dev,
2106 "Load/Reload VF driver\n");
f0c2982a
NM		 2107
2108 return ret;
2109}
2110
2111static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos,
2112 __be16 proto)
2113{
2114 struct otx2_flow_config *flow_cfg = pf->flow_cfg;
2115 struct nix_vtag_config_rsp *vtag_rsp;
2116 struct npc_delete_flow_req *del_req;
2117 struct nix_vtag_config *vtag_req;
2118 struct npc_install_flow_req *req;
2119 struct otx2_vf_config *config;
2120 int err = 0;
2121 u32 idx;
2122
2123 config = &pf->vf_configs[vf];
2124
2125 if (!vlan && !config->vlan)
2126 goto out;
2127
2128 mutex_lock(&pf->mbox.lock);
2129
2130 /* free old tx vtag entry */
2131 if (config->vlan) {
2132 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2133 if (!vtag_req) {
2134 err = -ENOMEM;
2135 goto out;
2136 }
2137 vtag_req->cfg_type = 0;
2138 vtag_req->tx.free_vtag0 = 1;
2139 vtag_req->tx.vtag0_idx = config->tx_vtag_idx;
2140
2141 err = otx2_sync_mbox_msg(&pf->mbox);
2142 if (err)
2143 goto out;
2144 }
2145
2146 if (!vlan && config->vlan) {
2147 /* rx */
2148 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2149 if (!del_req) {
2150 err = -ENOMEM;
2151 goto out;
2152 }
2153 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2154 del_req->entry =
9917060f 2155 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
f0c2982a
NM		 2156 err = otx2_sync_mbox_msg(&pf->mbox);
2157 if (err)
2158 goto out;
2159
2160 /* tx */
2161 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2162 if (!del_req) {
2163 err = -ENOMEM;
2164 goto out;
2165 }
2166 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2167 del_req->entry =
9917060f 2168 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
f0c2982a
NM		 2169 err = otx2_sync_mbox_msg(&pf->mbox);
2170
2171 goto out;
2172 }
2173
2174 /* rx */
2175 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2176 if (!req) {
2177 err = -ENOMEM;
2178 goto out;
2179 }
2180
2181 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
9917060f 2182 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
f0c2982a
NM		 2183 req->packet.vlan_tci = htons(vlan);
2184 req->mask.vlan_tci = htons(VLAN_VID_MASK);
2185 /* af fills the destination mac addr */
2186 eth_broadcast_addr((u8 *)&req->mask.dmac);
2187 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC);
2188 req->channel = pf->hw.rx_chan_base;
2189 req->intf = NIX_INTF_RX;
2190 req->vf = vf + 1;
2191 req->op = NIX_RX_ACTION_DEFAULT;
2192 req->vtag0_valid = true;
2193 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7;
2194 req->set_cntr = 1;
2195
2196 err = otx2_sync_mbox_msg(&pf->mbox);
2197 if (err)
2198 goto out;
2199
2200 /* tx */
2201 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2202 if (!vtag_req) {
2203 err = -ENOMEM;
2204 goto out;
2205 }
2206
2207 /* configure tx vtag params */
2208 vtag_req->vtag_size = VTAGSIZE_T4;
2209 vtag_req->cfg_type = 0; /* tx vlan cfg */
2210 vtag_req->tx.cfg_vtag0 = 1;
583b273d 2211 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan;
f0c2982a
NM		 2212
2213 err = otx2_sync_mbox_msg(&pf->mbox);
2214 if (err)
2215 goto out;
2216
2217 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp
2218 (&pf->mbox.mbox, 0, &vtag_req->hdr);
2219 if (IS_ERR(vtag_rsp)) {
2220 err = PTR_ERR(vtag_rsp);
2221 goto out;
2222 }
2223 config->tx_vtag_idx = vtag_rsp->vtag0_idx;
2224
2225 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2226 if (!req) {
2227 err = -ENOMEM;
2228 goto out;
2229 }
2230
2231 eth_zero_addr((u8 *)&req->mask.dmac);
2232 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
9917060f 2233 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
f0c2982a
NM		 2234 req->features = BIT_ULL(NPC_DMAC);
2235 req->channel = pf->hw.tx_chan_base;
2236 req->intf = NIX_INTF_TX;
2237 req->vf = vf + 1;
2238 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT;
2239 req->vtag0_def = vtag_rsp->vtag0_idx;
2240 req->vtag0_op = VTAG_INSERT;
2241 req->set_cntr = 1;
2242
2243 err = otx2_sync_mbox_msg(&pf->mbox);
2244out:
2245 config->vlan = vlan;
2246 mutex_unlock(&pf->mbox.lock);
2247 return err;
2248}
2249
2250static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos,
2251 __be16 proto)
2252{
2253 struct otx2_nic *pf = netdev_priv(netdev);
2254 struct pci_dev *pdev = pf->pdev;
2255
2256 if (!netif_running(netdev))
2257 return -EAGAIN;
2258
2259 if (vf >= pci_num_vf(pdev))
2260 return -EINVAL;
2261
2262 /* qos is currently unsupported */
2263 if (vlan >= VLAN_N_VID || qos)
2264 return -EINVAL;
2265
2266 if (proto != htons(ETH_P_8021Q))
2267 return -EPROTONOSUPPORT;
2268
2269 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT))
2270 return -EOPNOTSUPP;
2271
2272 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto);
2273}
2274
2275static int otx2_get_vf_config(struct net_device *netdev, int vf,
2276 struct ifla_vf_info *ivi)
2277{
2278 struct otx2_nic *pf = netdev_priv(netdev);
2279 struct pci_dev *pdev = pf->pdev;
2280 struct otx2_vf_config *config;
2281
2282 if (!netif_running(netdev))
2283 return -EAGAIN;
2284
2285 if (vf >= pci_num_vf(pdev))
2286 return -EINVAL;
2287
2288 config = &pf->vf_configs[vf];
2289 ivi->vf = vf;
2290 ether_addr_copy(ivi->mac, config->mac);
2291 ivi->vlan = config->vlan;
b1dc2040 2292 ivi->trusted = config->trusted;
f0c2982a
NM		 2293
2294 return 0;
2295}
2296
b1dc2040
HK		 2297static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf,
2298 int req_perm)
2299{
2300 struct set_vf_perm *req;
2301 int rc;
2302
2303 mutex_lock(&pf->mbox.lock);
2304 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox);
2305 if (!req) {
2306 rc = -ENOMEM;
2307 goto out;
2308 }
2309
2310 /* Let AF reset VF permissions as sriov is disabled */
2311 if (req_perm == OTX2_RESET_VF_PERM) {
2312 req->flags |= RESET_VF_PERM;
2313 } else if (req_perm == OTX2_TRUSTED_VF) {
2314 if (pf->vf_configs[vf].trusted)
2315 req->flags |= VF_TRUSTED;
2316 }
2317
2318 req->vf = vf;
2319 rc = otx2_sync_mbox_msg(&pf->mbox);
2320out:
2321 mutex_unlock(&pf->mbox.lock);
2322 return rc;
2323}
2324
2325static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf,
2326 bool enable)
2327{
2328 struct otx2_nic *pf = netdev_priv(netdev);
2329 struct pci_dev *pdev = pf->pdev;
2330 int rc;
2331
2332 if (vf >= pci_num_vf(pdev))
2333 return -EINVAL;
2334
2335 if (pf->vf_configs[vf].trusted == enable)
2336 return 0;
2337
2338 pf->vf_configs[vf].trusted = enable;
2339 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF);
2340
2341 if (rc)
2342 pf->vf_configs[vf].trusted = !enable;
2343 else
2344 netdev_info(pf->netdev, "VF %d is %strusted\n",
2345 vf, enable ? "" : "not ");
2346 return rc;
2347}
2348
16547577
SG		 2349static const struct net_device_ops otx2_netdev_ops = {
2350 .ndo_open = otx2_open,
2351 .ndo_stop = otx2_stop,
3ca6c4c8 2352 .ndo_start_xmit = otx2_xmit,
1d4d9e42 2353 .ndo_fix_features = otx2_fix_features,
34bfe0eb
SG		 2354 .ndo_set_mac_address = otx2_set_mac_address,
2355 .ndo_change_mtu = otx2_change_mtu,
2356 .ndo_set_rx_mode = otx2_set_rx_mode,
2357 .ndo_set_features = otx2_set_features,
4ff7d148 2358 .ndo_tx_timeout = otx2_tx_timeout,
e239d0c7 2359 .ndo_get_stats64 = otx2_get_stats64,
a7605370 2360 .ndo_eth_ioctl = otx2_ioctl,
f0c2982a
NM		 2361 .ndo_set_vf_mac = otx2_set_vf_mac,
2362 .ndo_set_vf_vlan = otx2_set_vf_vlan,
2363 .ndo_get_vf_config = otx2_get_vf_config,
1d4d9e42 2364 .ndo_setup_tc = otx2_setup_tc,
b1dc2040 2365 .ndo_set_vf_trust = otx2_ndo_set_vf_trust,
16547577
SG		 2366};
2367
e99b7c84
SG		 2368static int otx2_wq_init(struct otx2_nic *pf)
2369{
2370 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
2371 if (!pf->otx2_wq)
2372 return -ENOMEM;
2373
7ea8e6ee 2374 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler);
e99b7c84
SG		 2375 INIT_WORK(&pf->reset_task, otx2_reset_task);
2376 return 0;
2377}
2378
16547577
SG		 2379static int otx2_check_pf_usable(struct otx2_nic *nic)
2380{
2381 u64 rev;
2382
2383 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
2384 rev = (rev >> 12) & 0xFF;
2385 /* Check if AF has setup revision for RVUM block,
2386 * otherwise this driver probe should be deferred
2387 * until AF driver comes up.
2388 */
2389 if (!rev) {
2390 dev_warn(nic->dev,
2391 "AF is not initialized, deferring probe\n");
2392 return -EPROBE_DEFER;
2393 }
2394 return 0;
2395}
2396
05fcc9e0
SG		 2397static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
2398{
2399 struct otx2_hw *hw = &pf->hw;
2400 int num_vec, err;
2401
2402 /* NPA interrupts are inot registered, so alloc only
2403 * upto NIX vector offset.
2404 */
2405 num_vec = hw->nix_msixoff;
05fcc9e0
SG		 2406 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
2407
2408 otx2_disable_mbox_intr(pf);
2409 pci_free_irq_vectors(hw->pdev);
05fcc9e0
SG		 2410 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
2411 if (err < 0) {
2412 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
2413 __func__, num_vec);
2414 return err;
2415 }
2416
2417 return otx2_register_mbox_intr(pf, false);
2418}
2419
b1dc2040
HK		 2420static int otx2_sriov_vfcfg_init(struct otx2_nic *pf)
2421{
2422 int i;
2423
2424 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs,
2425 sizeof(struct otx2_vf_config),
2426 GFP_KERNEL);
2427 if (!pf->vf_configs)
2428 return -ENOMEM;
2429
2430 for (i = 0; i < pf->total_vfs; i++) {
2431 pf->vf_configs[i].pf = pf;
2432 pf->vf_configs[i].intf_down = true;
2433 pf->vf_configs[i].trusted = false;
2434 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2435 otx2_vf_link_event_task);
2436 }
2437
2438 return 0;
2439}
2440
2441static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf)
2442{
2443 int i;
2444
2445 if (!pf->vf_configs)
2446 return;
2447
2448 for (i = 0; i < pf->total_vfs; i++) {
2449 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2450 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM);
2451 }
2452}
2453
16547577
SG		 2454static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2455{
2456 struct device *dev = &pdev->dev;
2457 struct net_device *netdev;
2458 struct otx2_nic *pf;
2459 struct otx2_hw *hw;
2460 int err, qcount;
5a6d7c9d 2461 int num_vec;
16547577
SG		 2462
2463 err = pcim_enable_device(pdev);
2464 if (err) {
2465 dev_err(dev, "Failed to enable PCI device\n");
2466 return err;
2467 }
2468
2469 err = pci_request_regions(pdev, DRV_NAME);
2470 if (err) {
2471 dev_err(dev, "PCI request regions failed 0x%x\n", err);
2472 return err;
2473 }
2474
2475 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2476 if (err) {
2477 dev_err(dev, "DMA mask config failed, abort\n");
2478 goto err_release_regions;
2479 }
2480
2481 pci_set_master(pdev);
2482
2483 /* Set number of queues */
05fcc9e0 2484 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
16547577
SG		 2485
2486 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
2487 if (!netdev) {
2488 err = -ENOMEM;
2489 goto err_release_regions;
2490 }
2491
2492 pci_set_drvdata(pdev, netdev);
2493 SET_NETDEV_DEV(netdev, &pdev->dev);
2494 pf = netdev_priv(netdev);
2495 pf->netdev = netdev;
2496 pf->pdev = pdev;
2497 pf->dev = dev;
d424b6c0 2498 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
50fe6c02 2499 pf->flags |= OTX2_FLAG_INTF_DOWN;
16547577
SG		 2500
2501 hw = &pf->hw;
2502 hw->pdev = pdev;
2503 hw->rx_queues = qcount;
2504 hw->tx_queues = qcount;
2505 hw->max_queues = qcount;
2506
5a6d7c9d
SG		 2507 num_vec = pci_msix_vec_count(pdev);
2508 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
2509 GFP_KERNEL);
654cad8b
WY		 2510 if (!hw->irq_name) {
2511 err = -ENOMEM;
5a6d7c9d 2512 goto err_free_netdev;
654cad8b 2513 }
5a6d7c9d
SG		 2514
2515 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
2516 sizeof(cpumask_var_t), GFP_KERNEL);
654cad8b
WY		 2517 if (!hw->affinity_mask) {
2518 err = -ENOMEM;
5a6d7c9d 2519 goto err_free_netdev;
654cad8b 2520 }
5a6d7c9d 2521
16547577
SG		 2522 /* Map CSRs */
2523 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2524 if (!pf->reg_base) {
2525 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
2526 err = -ENOMEM;
2527 goto err_free_netdev;
2528 }
2529
2530 err = otx2_check_pf_usable(pf);
2531 if (err)
2532 goto err_free_netdev;
2533
5a6d7c9d
SG		 2534 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
2535 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
2536 if (err < 0) {
2537 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
2538 __func__, num_vec);
2539 goto err_free_netdev;
2540 }
2541
6e8ad438
G		 2542 otx2_setup_dev_hw_settings(pf);
2543
5a6d7c9d
SG		 2544 /* Init PF <=> AF mailbox stuff */
2545 err = otx2_pfaf_mbox_init(pf);
2546 if (err)
2547 goto err_free_irq_vectors;
2548
2549 /* Register mailbox interrupt */
2550 err = otx2_register_mbox_intr(pf, true);
2551 if (err)
2552 goto err_mbox_destroy;
2553
05fcc9e0
SG		 2554 /* Request AF to attach NPA and NIX LFs to this PF.
2555 * NIX and NPA LFs are needed for this PF to function as a NIC.
2556 */
2557 err = otx2_attach_npa_nix(pf);
16547577 2558 if (err)
5a6d7c9d 2559 goto err_disable_mbox_intr;
16547577 2560
05fcc9e0
SG		 2561 err = otx2_realloc_msix_vectors(pf);
2562 if (err)
2563 goto err_detach_rsrc;
2564
2565 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
2566 if (err)
2567 goto err_detach_rsrc;
2568
5c051207 2569 err = cn10k_lmtst_init(pf);
6e8ad438
G		 2570 if (err)
2571 goto err_detach_rsrc;
04a21ef3 2572
34bfe0eb
SG		 2573 /* Assign default mac address */
2574 otx2_get_mac_from_af(netdev);
2575
c9c12d33
AM		 2576 /* Don't check for error. Proceed without ptp */
2577 otx2_ptp_init(pf);
2578
caa2da34
SG		 2579 /* NPA's pool is a stack to which SW frees buffer pointers via Aura.
2580 * HW allocates buffer pointer from stack and uses it for DMA'ing
2581 * ingress packet. In some scenarios HW can free back allocated buffer
2582 * pointers to pool. This makes it impossible for SW to maintain a
2583 * parallel list where physical addresses of buffer pointers (IOVAs)
2584 * given to HW can be saved for later reference.
2585 *
2586 * So the only way to convert Rx packet's buffer address is to use
2587 * IOMMU's iova_to_phys() handler which translates the address by
2588 * walking through the translation tables.
2589 */
2590 pf->iommu_domain = iommu_get_domain_for_dev(dev);
2591
3ca6c4c8 2592 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
85069e95 2593 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
dc1a9bf2
SG		 2594 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
2595 NETIF_F_GSO_UDP_L4);
abe02543
SG		 2596 netdev->features |= netdev->hw_features;
2597
f0a1913f
SS		 2598 err = otx2_mcam_flow_init(pf);
2599 if (err)
2600 goto err_ptp_destroy;
2601
2602 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT)
2603 netdev->hw_features |= NETIF_F_NTUPLE;
2604
63ee5157
HK		 2605 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT)
2606 netdev->priv_flags |= IFF_UNICAST_FLT;
2607
fd9d7859
HK		 2608 /* Support TSO on tag interface */
2609 netdev->vlan_features |= netdev->features;
2610 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
2611 NETIF_F_HW_VLAN_STAG_TX;
2612 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
2613 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
2614 NETIF_F_HW_VLAN_STAG_RX;
2615 netdev->features |= netdev->hw_features;
2616
1d4d9e42
NM		 2617 /* HW supports tc offload but mutually exclusive with n-tuple filters */
2618 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT)
2619 netdev->hw_features |= NETIF_F_HW_TC;
2620
0b3834ae
SG		 2621 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
2622
86d74760 2623 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS;
4ff7d148
G		 2624 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
2625
16547577
SG		 2626 netdev->netdev_ops = &otx2_netdev_ops;
2627
34bfe0eb 2628 netdev->min_mtu = OTX2_MIN_MTU;
ab58a416 2629 netdev->max_mtu = otx2_get_max_mtu(pf);
34bfe0eb 2630
16547577
SG		 2631 err = register_netdev(netdev);
2632 if (err) {
2633 dev_err(dev, "Failed to register netdevice\n");
f0a1913f 2634 goto err_del_mcam_entries;
16547577
SG		 2635 }
2636
e99b7c84
SG		 2637 err = otx2_wq_init(pf);
2638 if (err)
2639 goto err_unreg_netdev;
2640
d45d8979
CJ		 2641 otx2_set_ethtool_ops(netdev);
2642
1d4d9e42
NM		 2643 err = otx2_init_tc(pf);
2644 if (err)
2645 goto err_mcam_flow_del;
2646
2da48943
SG		 2647 err = otx2_register_dl(pf);
2648 if (err)
2649 goto err_mcam_flow_del;
2650
b1dc2040
HK		 2651 /* Initialize SR-IOV resources */
2652 err = otx2_sriov_vfcfg_init(pf);
2653 if (err)
2654 goto err_pf_sriov_init;
2655
50fe6c02
LC		 2656 /* Enable link notifications */
2657 otx2_cgx_config_linkevents(pf, true);
2658
3184fb5b
TD		 2659 /* Enable pause frames by default */
2660 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED;
2661 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED;
2662
16547577
SG		 2663 return 0;
2664
b1dc2040
HK		 2665err_pf_sriov_init:
2666 otx2_shutdown_tc(pf);
1d4d9e42
NM		 2667err_mcam_flow_del:
2668 otx2_mcam_flow_del(pf);
e99b7c84
SG		 2669err_unreg_netdev:
2670 unregister_netdev(netdev);
f0a1913f
SS		 2671err_del_mcam_entries:
2672 otx2_mcam_flow_del(pf);
c9c12d33
AM		 2673err_ptp_destroy:
2674 otx2_ptp_destroy(pf);
05fcc9e0 2675err_detach_rsrc:
ef6c8da7
G		 2676 if (pf->hw.lmt_info)
2677 free_percpu(pf->hw.lmt_info);
5c051207
G		 2678 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2679 qmem_free(pf->dev, pf->dync_lmt);
05fcc9e0 2680 otx2_detach_resources(&pf->mbox);
5a6d7c9d
SG		 2681err_disable_mbox_intr:
2682 otx2_disable_mbox_intr(pf);
2683err_mbox_destroy:
2684 otx2_pfaf_mbox_destroy(pf);
2685err_free_irq_vectors:
2686 pci_free_irq_vectors(hw->pdev);
16547577
SG		 2687err_free_netdev:
2688 pci_set_drvdata(pdev, NULL);
2689 free_netdev(netdev);
2690err_release_regions:
2691 pci_release_regions(pdev);
2692 return err;
2693}
2694
ad513ed9
TD		 2695static void otx2_vf_link_event_task(struct work_struct *work)
2696{
2697 struct otx2_vf_config *config;
2698 struct cgx_link_info_msg *req;
2699 struct mbox_msghdr *msghdr;
2700 struct otx2_nic *pf;
2701 int vf_idx;
2702
2703 config = container_of(work, struct otx2_vf_config,
2704 link_event_work.work);
2705 vf_idx = config - config->pf->vf_configs;
2706 pf = config->pf;
2707
2708 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
2709 sizeof(*req), sizeof(struct msg_rsp));
2710 if (!msghdr) {
2711 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
2712 return;
2713 }
2714
2715 req = (struct cgx_link_info_msg *)msghdr;
2716 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
2717 req->hdr.sig = OTX2_MBOX_REQ_SIG;
2718 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
2719
2720 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
2721}
2722
d424b6c0
SG		 2723static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
2724{
2725 struct net_device *netdev = pci_get_drvdata(pdev);
2726 struct otx2_nic *pf = netdev_priv(netdev);
b1dc2040 2727 int ret;
d424b6c0
SG		 2728
2729 /* Init PF <=> VF mailbox stuff */
2730 ret = otx2_pfvf_mbox_init(pf, numvfs);
2731 if (ret)
2732 return ret;
2733
2734 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
2735 if (ret)
2736 goto free_mbox;
2737
547d20f1 2738 ret = otx2_pf_flr_init(pf, numvfs);
d424b6c0 2739 if (ret)
b1dc2040 2740 goto free_intr;
d424b6c0 2741
547d20f1
G		 2742 ret = otx2_register_flr_me_intr(pf, numvfs);
2743 if (ret)
2744 goto free_flr;
2745
2746 ret = pci_enable_sriov(pdev, numvfs);
2747 if (ret)
2748 goto free_flr_intr;
2749
d424b6c0 2750 return numvfs;
547d20f1
G		 2751free_flr_intr:
2752 otx2_disable_flr_me_intr(pf);
2753free_flr:
2754 otx2_flr_wq_destroy(pf);
d424b6c0
SG		 2755free_intr:
2756 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2757free_mbox:
2758 otx2_pfvf_mbox_destroy(pf);
2759 return ret;
2760}
2761
2762static int otx2_sriov_disable(struct pci_dev *pdev)
2763{
2764 struct net_device *netdev = pci_get_drvdata(pdev);
2765 struct otx2_nic *pf = netdev_priv(netdev);
2766 int numvfs = pci_num_vf(pdev);
2767
2768 if (!numvfs)
2769 return 0;
2770
2771 pci_disable_sriov(pdev);
2772
547d20f1
G		 2773 otx2_disable_flr_me_intr(pf);
2774 otx2_flr_wq_destroy(pf);
d424b6c0
SG		 2775 otx2_disable_pfvf_mbox_intr(pf, numvfs);
2776 otx2_pfvf_mbox_destroy(pf);
2777
2778 return 0;
2779}
2780
2781static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
2782{
2783 if (numvfs == 0)
2784 return otx2_sriov_disable(pdev);
2785 else
2786 return otx2_sriov_enable(pdev, numvfs);
2787}
2788
16547577
SG		 2789static void otx2_remove(struct pci_dev *pdev)
2790{
2791 struct net_device *netdev = pci_get_drvdata(pdev);
2792 struct otx2_nic *pf;
2793
2794 if (!netdev)
2795 return;
2796
2797 pf = netdev_priv(netdev);
2798
f0c2982a
NM		 2799 pf->flags |= OTX2_FLAG_PF_SHUTDOWN;
2800
c9c12d33
AM		 2801 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
2802 otx2_config_hw_tx_tstamp(pf, false);
2803 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
2804 otx2_config_hw_rx_tstamp(pf, false);
2805
948a6633 2806 cancel_work_sync(&pf->reset_task);
50fe6c02
LC		 2807 /* Disable link notifications */
2808 otx2_cgx_config_linkevents(pf, false);
2809
2da48943 2810 otx2_unregister_dl(pf);
16547577 2811 unregister_netdev(netdev);
d424b6c0 2812 otx2_sriov_disable(pf->pdev);
b1dc2040 2813 otx2_sriov_vfcfg_cleanup(pf);
e99b7c84
SG		 2814 if (pf->otx2_wq)
2815 destroy_workqueue(pf->otx2_wq);
d424b6c0 2816
c9c12d33 2817 otx2_ptp_destroy(pf);
f0a1913f 2818 otx2_mcam_flow_del(pf);
1d4d9e42 2819 otx2_shutdown_tc(pf);
05fcc9e0 2820 otx2_detach_resources(&pf->mbox);
ef6c8da7
G		 2821 if (pf->hw.lmt_info)
2822 free_percpu(pf->hw.lmt_info);
5c051207
G		 2823 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2824 qmem_free(pf->dev, pf->dync_lmt);
5a6d7c9d
SG		 2825 otx2_disable_mbox_intr(pf);
2826 otx2_pfaf_mbox_destroy(pf);
16547577
SG		 2827 pci_free_irq_vectors(pf->pdev);
2828 pci_set_drvdata(pdev, NULL);
2829 free_netdev(netdev);
5a6d7c9d 2830
16547577
SG		 2831 pci_release_regions(pdev);
2832}
2833
2834static struct pci_driver otx2_pf_driver = {
2835 .name = DRV_NAME,
2836 .id_table = otx2_pf_id_table,
2837 .probe = otx2_probe,
2838 .shutdown = otx2_remove,
2839 .remove = otx2_remove,
d424b6c0 2840 .sriov_configure = otx2_sriov_configure
16547577
SG		 2841};
2842
2843static int __init otx2_rvupf_init_module(void)
2844{
2845 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
2846
2847 return pci_register_driver(&otx2_pf_driver);
2848}
2849
2850static void __exit otx2_rvupf_cleanup_module(void)
2851{
2852 pci_unregister_driver(&otx2_pf_driver);
2853}
2854
2855module_init(otx2_rvupf_init_module);
2856module_exit(otx2_rvupf_cleanup_module);
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