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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 13 | * the Free Software Foundation; either version 2 of the License. |
cd28ab6a SH |
14 | * |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
18 | * GNU General Public License for more details. |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
ada1db5c JP |
25 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
26 | ||
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a | 28 | #include <linux/kernel.h> |
cd28ab6a SH |
29 | #include <linux/module.h> |
30 | #include <linux/netdevice.h> | |
d0bbccfa | 31 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
32 | #include <linux/etherdevice.h> |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/pci.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
cd28ab6a | 36 | #include <linux/ip.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c9bdd4b5 | 38 | #include <net/ip.h> |
cd28ab6a SH |
39 | #include <linux/tcp.h> |
40 | #include <linux/in.h> | |
41 | #include <linux/delay.h> | |
91c86df5 | 42 | #include <linux/workqueue.h> |
d1f13708 | 43 | #include <linux/if_vlan.h> |
d70cd51a | 44 | #include <linux/prefetch.h> |
3cf26753 | 45 | #include <linux/debugfs.h> |
ef743d33 | 46 | #include <linux/mii.h> |
cd28ab6a SH |
47 | |
48 | #include <asm/irq.h> | |
49 | ||
50 | #include "sky2.h" | |
51 | ||
52 | #define DRV_NAME "sky2" | |
d9fa7c86 | 53 | #define DRV_VERSION "1.30" |
cd28ab6a SH |
54 | |
55 | /* | |
56 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
57 | * that are organized into three (receive, transmit, status) different rings | |
14d0263f | 58 | * similar to Tigon3. |
cd28ab6a SH |
59 | */ |
60 | ||
14d0263f | 61 | #define RX_LE_SIZE 1024 |
cd28ab6a | 62 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
14d0263f | 63 | #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) |
13210ce5 | 64 | #define RX_DEF_PENDING RX_MAX_PENDING |
793b883e | 65 | |
ee5f68fe | 66 | /* This is the worst case number of transmit list elements for a single skb: |
07e31637 SH |
67 | VLAN:GSO + CKSUM + Data + skb_frags * DMA */ |
68 | #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) | |
e9c1be80 | 69 | #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) |
efe91932 | 70 | #define TX_MAX_PENDING 1024 |
b1cb8256 | 71 | #define TX_DEF_PENDING 63 |
cd28ab6a | 72 | |
cd28ab6a SH |
73 | #define TX_WATCHDOG (5 * HZ) |
74 | #define NAPI_WEIGHT 64 | |
75 | #define PHY_RETRIES 1000 | |
76 | ||
f4331a6d SH |
77 | #define SKY2_EEPROM_MAGIC 0x9955aabb |
78 | ||
060b946c | 79 | #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) |
cb5d9547 | 80 | |
cd28ab6a | 81 | static const u32 default_msg = |
793b883e SH |
82 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
83 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 84 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 85 | |
793b883e | 86 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
87 | module_param(debug, int, 0); |
88 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
89 | ||
14d0263f | 90 | static int copybreak __read_mostly = 128; |
bdb5c58e SH |
91 | module_param(copybreak, int, 0); |
92 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
93 | ||
fb2690a9 SH |
94 | static int disable_msi = 0; |
95 | module_param(disable_msi, int, 0); | |
96 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
97 | ||
5676cc7b | 98 | static int legacy_pme = 0; |
99 | module_param(legacy_pme, int, 0); | |
100 | MODULE_PARM_DESC(legacy_pme, "Legacy power management"); | |
101 | ||
e6cac9ba | 102 | static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { |
e5b74c7d SH |
103 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ |
104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ | |
e30a4ac2 | 105 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ |
2d2a3871 | 106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
2f4a66ad | 107 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ |
508f89e7 | 108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ |
f1a0b6f5 | 109 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ |
e5b74c7d SH |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ | |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ | |
05745c4a | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ |
a3b4fced | 123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ |
e5b74c7d | 124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ |
5a37a68d | 125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ |
05745c4a | 126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ |
e5b74c7d SH |
127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ |
128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ | |
129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ | |
130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ | |
131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ | |
05745c4a | 132 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ |
e5b74c7d SH |
133 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ |
134 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ | |
135 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ | |
f1a0b6f5 SH |
136 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ |
137 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ | |
69161611 | 138 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ |
5a37a68d | 139 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ |
ed4d4161 SH |
140 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ |
141 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ | |
0ce8b98d | 142 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ |
0f5aac70 | 143 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ |
0e767324 | 144 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */ |
cd28ab6a SH |
145 | { 0 } |
146 | }; | |
793b883e | 147 | |
cd28ab6a SH |
148 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
149 | ||
150 | /* Avoid conditionals by using array */ | |
151 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
152 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
f4ea431b | 153 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
cd28ab6a | 154 | |
d1b139c0 | 155 | static void sky2_set_multicast(struct net_device *dev); |
0bdb0bd0 | 156 | static irqreturn_t sky2_intr(int irq, void *dev_id); |
d1b139c0 | 157 | |
af043aa5 | 158 | /* Access to PHY via serial interconnect */ |
ef743d33 | 159 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
160 | { |
161 | int i; | |
162 | ||
163 | gma_write16(hw, port, GM_SMI_DATA, val); | |
164 | gma_write16(hw, port, GM_SMI_CTRL, | |
165 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
166 | ||
167 | for (i = 0; i < PHY_RETRIES; i++) { | |
af043aa5 SH |
168 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
169 | if (ctrl == 0xffff) | |
170 | goto io_error; | |
171 | ||
172 | if (!(ctrl & GM_SMI_CT_BUSY)) | |
ef743d33 | 173 | return 0; |
af043aa5 SH |
174 | |
175 | udelay(10); | |
cd28ab6a | 176 | } |
ef743d33 | 177 | |
060b946c | 178 | dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 179 | return -ETIMEDOUT; |
af043aa5 SH |
180 | |
181 | io_error: | |
182 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); | |
183 | return -EIO; | |
cd28ab6a SH |
184 | } |
185 | ||
ef743d33 | 186 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
187 | { |
188 | int i; | |
189 | ||
793b883e | 190 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
191 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
192 | ||
193 | for (i = 0; i < PHY_RETRIES; i++) { | |
af043aa5 SH |
194 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
195 | if (ctrl == 0xffff) | |
196 | goto io_error; | |
197 | ||
198 | if (ctrl & GM_SMI_CT_RD_VAL) { | |
ef743d33 SH |
199 | *val = gma_read16(hw, port, GM_SMI_DATA); |
200 | return 0; | |
201 | } | |
202 | ||
af043aa5 | 203 | udelay(10); |
cd28ab6a SH |
204 | } |
205 | ||
af043aa5 | 206 | dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); |
ef743d33 | 207 | return -ETIMEDOUT; |
af043aa5 SH |
208 | io_error: |
209 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); | |
210 | return -EIO; | |
ef743d33 SH |
211 | } |
212 | ||
af043aa5 | 213 | static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) |
ef743d33 SH |
214 | { |
215 | u16 v; | |
af043aa5 | 216 | __gm_phy_read(hw, port, reg, &v); |
ef743d33 | 217 | return v; |
cd28ab6a SH |
218 | } |
219 | ||
5afa0a9c | 220 | |
ae306cca SH |
221 | static void sky2_power_on(struct sky2_hw *hw) |
222 | { | |
223 | /* switch power to VCC (WA for VAUX problem) */ | |
224 | sky2_write8(hw, B0_POWER_CTRL, | |
225 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
5afa0a9c | 226 | |
ae306cca SH |
227 | /* disable Core Clock Division, */ |
228 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
d3bcfbeb | 229 | |
4b7c47aa | 230 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ae306cca SH |
231 | /* enable bits are inverted */ |
232 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
233 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
234 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
235 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
236 | else | |
237 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
977bdf06 | 238 | |
ea76e635 | 239 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
fc99fe06 | 240 | u32 reg; |
5afa0a9c | 241 | |
b32f40c4 | 242 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
b2345773 | 243 | |
b32f40c4 | 244 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); |
fc99fe06 SH |
245 | /* set all bits to 0 except bits 15..12 and 8 */ |
246 | reg &= P_ASPM_CONTROL_MSK; | |
b32f40c4 | 247 | sky2_pci_write32(hw, PCI_DEV_REG4, reg); |
fc99fe06 | 248 | |
b32f40c4 | 249 | reg = sky2_pci_read32(hw, PCI_DEV_REG5); |
fc99fe06 SH |
250 | /* set all bits to 0 except bits 28 & 27 */ |
251 | reg &= P_CTL_TIM_VMAIN_AV_MSK; | |
b32f40c4 | 252 | sky2_pci_write32(hw, PCI_DEV_REG5, reg); |
fc99fe06 | 253 | |
b32f40c4 | 254 | sky2_pci_write32(hw, PCI_CFG_REG_1, 0); |
8f70920f | 255 | |
5f8ae5c5 | 256 | sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); |
257 | ||
8f70920f SH |
258 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ |
259 | reg = sky2_read32(hw, B2_GP_IO); | |
260 | reg |= GLB_GPIO_STAT_RACE_DIS; | |
261 | sky2_write32(hw, B2_GP_IO, reg); | |
b2345773 SH |
262 | |
263 | sky2_read32(hw, B2_GP_IO); | |
5afa0a9c | 264 | } |
10547ae2 SH |
265 | |
266 | /* Turn on "driver loaded" LED */ | |
267 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); | |
ae306cca | 268 | } |
5afa0a9c | 269 | |
ae306cca SH |
270 | static void sky2_power_aux(struct sky2_hw *hw) |
271 | { | |
4b7c47aa | 272 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ae306cca SH |
273 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
274 | else | |
275 | /* enable bits are inverted */ | |
276 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
277 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
278 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
279 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
280 | ||
c23ddf8f SH |
281 | /* switch power to VAUX if supported and PME from D3cold */ |
282 | if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && | |
283 | pci_pme_capable(hw->pdev, PCI_D3cold)) | |
ae306cca SH |
284 | sky2_write8(hw, B0_POWER_CTRL, |
285 | (PC_VAUX_ENA | PC_VCC_ENA | | |
286 | PC_VAUX_ON | PC_VCC_OFF)); | |
10547ae2 SH |
287 | |
288 | /* turn off "driver loaded LED" */ | |
289 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); | |
5afa0a9c SH |
290 | } |
291 | ||
d3bcfbeb | 292 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
cd28ab6a SH |
293 | { |
294 | u16 reg; | |
295 | ||
296 | /* disable all GMAC IRQ's */ | |
297 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
793b883e | 298 | |
cd28ab6a SH |
299 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
300 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
301 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
302 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
303 | ||
304 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
305 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
306 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
307 | } | |
308 | ||
16ad91e1 SH |
309 | /* flow control to advertise bits */ |
310 | static const u16 copper_fc_adv[] = { | |
311 | [FC_NONE] = 0, | |
312 | [FC_TX] = PHY_M_AN_ASP, | |
313 | [FC_RX] = PHY_M_AN_PC, | |
314 | [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, | |
315 | }; | |
316 | ||
317 | /* flow control to advertise bits when using 1000BaseX */ | |
318 | static const u16 fiber_fc_adv[] = { | |
df3fe1f3 | 319 | [FC_NONE] = PHY_M_P_NO_PAUSE_X, |
16ad91e1 SH |
320 | [FC_TX] = PHY_M_P_ASYM_MD_X, |
321 | [FC_RX] = PHY_M_P_SYM_MD_X, | |
df3fe1f3 | 322 | [FC_BOTH] = PHY_M_P_BOTH_MD_X, |
16ad91e1 SH |
323 | }; |
324 | ||
325 | /* flow control to GMA disable bits */ | |
326 | static const u16 gm_fc_disable[] = { | |
327 | [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, | |
328 | [FC_TX] = GM_GPCR_FC_RX_DIS, | |
329 | [FC_RX] = GM_GPCR_FC_TX_DIS, | |
330 | [FC_BOTH] = 0, | |
331 | }; | |
332 | ||
333 | ||
cd28ab6a SH |
334 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) |
335 | { | |
336 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
2eaba1a2 | 337 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; |
cd28ab6a | 338 | |
0ea065e5 | 339 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
ea76e635 | 340 | !(hw->flags & SKY2_HW_NEWER_PHY)) { |
cd28ab6a SH |
341 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
342 | ||
343 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 344 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
345 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
346 | ||
53419c68 | 347 | /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ |
cd28ab6a | 348 | if (hw->chip_id == CHIP_ID_YUKON_EC) |
53419c68 | 349 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
350 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; |
351 | else | |
53419c68 SH |
352 | /* set master & slave downshift counter to 1x */ |
353 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); | |
cd28ab6a SH |
354 | |
355 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
356 | } | |
357 | ||
358 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
b89165f2 | 359 | if (sky2_is_copper(hw)) { |
05745c4a | 360 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
cd28ab6a SH |
361 | /* enable automatic crossover */ |
362 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
6d3105d5 SH |
363 | |
364 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
365 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
366 | u16 spec; | |
367 | ||
368 | /* Enable Class A driver for FE+ A0 */ | |
369 | spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); | |
370 | spec |= PHY_M_FESC_SEL_CL_A; | |
371 | gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); | |
372 | } | |
cd28ab6a SH |
373 | } else { |
374 | /* disable energy detect */ | |
375 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
376 | ||
377 | /* enable automatic crossover */ | |
378 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
379 | ||
53419c68 | 380 | /* downshift on PHY 88E1112 and 88E1149 is changed */ |
8e95a202 JP |
381 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
382 | (hw->flags & SKY2_HW_NEWER_PHY)) { | |
53419c68 | 383 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
384 | ctrl &= ~PHY_M_PC_DSC_MSK; |
385 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
386 | } | |
387 | } | |
cd28ab6a SH |
388 | } else { |
389 | /* workaround for deviation #4.88 (CRC errors) */ | |
390 | /* disable Automatic Crossover */ | |
391 | ||
392 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
b89165f2 | 393 | } |
cd28ab6a | 394 | |
b89165f2 SH |
395 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
396 | ||
397 | /* special setup for PHY 88E1112 Fiber */ | |
ea76e635 | 398 | if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { |
b89165f2 | 399 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a | 400 | |
b89165f2 SH |
401 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ |
402 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
403 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
404 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
405 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
406 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
407 | ||
408 | if (hw->pmd_type == 'P') { | |
cd28ab6a SH |
409 | /* select page 1 to access Fiber registers */ |
410 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
b89165f2 SH |
411 | |
412 | /* for SFP-module set SIGDET polarity to low */ | |
413 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
414 | ctrl |= PHY_M_FIB_SIGD_POL; | |
34dd962b | 415 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
cd28ab6a | 416 | } |
b89165f2 SH |
417 | |
418 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
cd28ab6a SH |
419 | } |
420 | ||
7800fddc | 421 | ctrl = PHY_CT_RESET; |
cd28ab6a SH |
422 | ct1000 = 0; |
423 | adv = PHY_AN_CSMA; | |
2eaba1a2 | 424 | reg = 0; |
cd28ab6a | 425 | |
0ea065e5 | 426 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { |
b89165f2 | 427 | if (sky2_is_copper(hw)) { |
cd28ab6a SH |
428 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
429 | ct1000 |= PHY_M_1000C_AFD; | |
430 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
431 | ct1000 |= PHY_M_1000C_AHD; | |
432 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
433 | adv |= PHY_M_AN_100_FD; | |
434 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
435 | adv |= PHY_M_AN_100_HD; | |
436 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
437 | adv |= PHY_M_AN_10_FD; | |
438 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
439 | adv |= PHY_M_AN_10_HD; | |
709c6e7b | 440 | |
b89165f2 SH |
441 | } else { /* special defines for FIBER (88E1040S only) */ |
442 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
443 | adv |= PHY_M_AN_1000X_AFD; | |
444 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
445 | adv |= PHY_M_AN_1000X_AHD; | |
709c6e7b | 446 | } |
cd28ab6a SH |
447 | |
448 | /* Restart Auto-negotiation */ | |
449 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
450 | } else { | |
451 | /* forced speed/duplex settings */ | |
452 | ct1000 = PHY_M_1000C_MSE; | |
453 | ||
0ea065e5 SH |
454 | /* Disable auto update for duplex flow control and duplex */ |
455 | reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; | |
cd28ab6a SH |
456 | |
457 | switch (sky2->speed) { | |
458 | case SPEED_1000: | |
459 | ctrl |= PHY_CT_SP1000; | |
2eaba1a2 | 460 | reg |= GM_GPCR_SPEED_1000; |
cd28ab6a SH |
461 | break; |
462 | case SPEED_100: | |
463 | ctrl |= PHY_CT_SP100; | |
2eaba1a2 | 464 | reg |= GM_GPCR_SPEED_100; |
cd28ab6a SH |
465 | break; |
466 | } | |
467 | ||
2eaba1a2 SH |
468 | if (sky2->duplex == DUPLEX_FULL) { |
469 | reg |= GM_GPCR_DUP_FULL; | |
470 | ctrl |= PHY_CT_DUP_MD; | |
16ad91e1 SH |
471 | } else if (sky2->speed < SPEED_1000) |
472 | sky2->flow_mode = FC_NONE; | |
0ea065e5 | 473 | } |
2eaba1a2 | 474 | |
0ea065e5 SH |
475 | if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { |
476 | if (sky2_is_copper(hw)) | |
477 | adv |= copper_fc_adv[sky2->flow_mode]; | |
478 | else | |
479 | adv |= fiber_fc_adv[sky2->flow_mode]; | |
480 | } else { | |
481 | reg |= GM_GPCR_AU_FCT_DIS; | |
16ad91e1 | 482 | reg |= gm_fc_disable[sky2->flow_mode]; |
2eaba1a2 SH |
483 | |
484 | /* Forward pause packets to GMAC? */ | |
16ad91e1 | 485 | if (sky2->flow_mode & FC_RX) |
2eaba1a2 SH |
486 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
487 | else | |
488 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
cd28ab6a SH |
489 | } |
490 | ||
2eaba1a2 SH |
491 | gma_write16(hw, port, GM_GP_CTRL, reg); |
492 | ||
05745c4a | 493 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a SH |
494 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
495 | ||
496 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
497 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
498 | ||
499 | /* Setup Phy LED's */ | |
500 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
501 | ledover = 0; | |
502 | ||
503 | switch (hw->chip_id) { | |
504 | case CHIP_ID_YUKON_FE: | |
505 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
506 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
507 | ||
508 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
509 | ||
510 | /* delete ACT LED control bits */ | |
511 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
512 | /* change ACT LED control to blink mode */ | |
513 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
514 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
515 | break; | |
516 | ||
05745c4a SH |
517 | case CHIP_ID_YUKON_FE_P: |
518 | /* Enable Link Partner Next Page */ | |
519 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
520 | ctrl |= PHY_M_PC_ENA_LIP_NP; | |
521 | ||
522 | /* disable Energy Detect and enable scrambler */ | |
523 | ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); | |
524 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
525 | ||
526 | /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ | |
527 | ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | | |
528 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | | |
529 | PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); | |
530 | ||
531 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
532 | break; | |
533 | ||
cd28ab6a | 534 | case CHIP_ID_YUKON_XL: |
793b883e | 535 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
536 | |
537 | /* select page 3 to access LED control register */ | |
538 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
539 | ||
540 | /* set LED Function Control register */ | |
ed6d32c7 SH |
541 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
542 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
543 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
544 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
545 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
546 | |
547 | /* set Polarity Control register */ | |
548 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
549 | (PHY_M_POLC_LS1_P_MIX(4) | |
550 | PHY_M_POLC_IS0_P_MIX(4) | | |
551 | PHY_M_POLC_LOS_CTRL(2) | | |
552 | PHY_M_POLC_INIT_CTRL(2) | | |
553 | PHY_M_POLC_STA1_CTRL(2) | | |
554 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
555 | |
556 | /* restore page register */ | |
793b883e | 557 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a | 558 | break; |
93745494 | 559 | |
ed6d32c7 | 560 | case CHIP_ID_YUKON_EC_U: |
93745494 | 561 | case CHIP_ID_YUKON_EX: |
ed4d4161 | 562 | case CHIP_ID_YUKON_SUPR: |
ed6d32c7 SH |
563 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
564 | ||
565 | /* select page 3 to access LED control register */ | |
566 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
567 | ||
568 | /* set LED Function Control register */ | |
569 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
570 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
571 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ | |
572 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
573 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ | |
574 | ||
575 | /* set Blink Rate in LED Timer Control Register */ | |
576 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, | |
577 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); | |
578 | /* restore page register */ | |
579 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
580 | break; | |
cd28ab6a SH |
581 | |
582 | default: | |
583 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
584 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
a84d0a3d | 585 | |
cd28ab6a | 586 | /* turn off the Rx LED (LED_RX) */ |
a84d0a3d | 587 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); |
cd28ab6a SH |
588 | } |
589 | ||
0ce8b98d | 590 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { |
977bdf06 | 591 | /* apply fixes in PHY AFE */ |
ed6d32c7 SH |
592 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); |
593 | ||
977bdf06 | 594 | /* increase differential signal amplitude in 10BASE-T */ |
ed6d32c7 SH |
595 | gm_phy_write(hw, port, 0x18, 0xaa99); |
596 | gm_phy_write(hw, port, 0x17, 0x2011); | |
cd28ab6a | 597 | |
0ce8b98d SH |
598 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
599 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ | |
600 | gm_phy_write(hw, port, 0x18, 0xa204); | |
601 | gm_phy_write(hw, port, 0x17, 0x2002); | |
602 | } | |
977bdf06 SH |
603 | |
604 | /* set page register to 0 */ | |
9467a8fc | 605 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
05745c4a SH |
606 | } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
607 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
608 | /* apply workaround for integrated resistors calibration */ | |
609 | gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); | |
610 | gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); | |
0f5aac70 SH |
611 | } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { |
612 | /* apply fixes in PHY AFE */ | |
613 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); | |
614 | ||
615 | /* apply RDAC termination workaround */ | |
616 | gm_phy_write(hw, port, 24, 0x2800); | |
617 | gm_phy_write(hw, port, 23, 0x2001); | |
618 | ||
619 | /* set page register back to 0 */ | |
620 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
e1a74b37 SH |
621 | } else if (hw->chip_id != CHIP_ID_YUKON_EX && |
622 | hw->chip_id < CHIP_ID_YUKON_SUPR) { | |
05745c4a | 623 | /* no effect on Yukon-XL */ |
977bdf06 | 624 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); |
cd28ab6a | 625 | |
8e95a202 JP |
626 | if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || |
627 | sky2->speed == SPEED_100) { | |
977bdf06 | 628 | /* turn on 100 Mbps LED (LED_LINK100) */ |
a84d0a3d | 629 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); |
977bdf06 | 630 | } |
cd28ab6a | 631 | |
977bdf06 SH |
632 | if (ledover) |
633 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
634 | ||
4fb99cd6 | 635 | } else if (hw->chip_id == CHIP_ID_YUKON_PRM && |
636 | (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { | |
637 | int i; | |
638 | /* This a phy register setup workaround copied from vendor driver. */ | |
639 | static const struct { | |
640 | u16 reg, val; | |
641 | } eee_afe[] = { | |
642 | { 0x156, 0x58ce }, | |
643 | { 0x153, 0x99eb }, | |
644 | { 0x141, 0x8064 }, | |
645 | /* { 0x155, 0x130b },*/ | |
646 | { 0x000, 0x0000 }, | |
647 | { 0x151, 0x8433 }, | |
648 | { 0x14b, 0x8c44 }, | |
649 | { 0x14c, 0x0f90 }, | |
650 | { 0x14f, 0x39aa }, | |
651 | /* { 0x154, 0x2f39 },*/ | |
652 | { 0x14d, 0xba33 }, | |
653 | { 0x144, 0x0048 }, | |
654 | { 0x152, 0x2010 }, | |
655 | /* { 0x158, 0x1223 },*/ | |
656 | { 0x140, 0x4444 }, | |
657 | { 0x154, 0x2f3b }, | |
658 | { 0x158, 0xb203 }, | |
659 | { 0x157, 0x2029 }, | |
660 | }; | |
661 | ||
662 | /* Start Workaround for OptimaEEE Rev.Z0 */ | |
663 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); | |
664 | ||
665 | gm_phy_write(hw, port, 1, 0x4099); | |
666 | gm_phy_write(hw, port, 3, 0x1120); | |
667 | gm_phy_write(hw, port, 11, 0x113c); | |
668 | gm_phy_write(hw, port, 14, 0x8100); | |
669 | gm_phy_write(hw, port, 15, 0x112a); | |
670 | gm_phy_write(hw, port, 17, 0x1008); | |
671 | ||
672 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); | |
673 | gm_phy_write(hw, port, 1, 0x20b0); | |
674 | ||
675 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); | |
676 | ||
677 | for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { | |
678 | /* apply AFE settings */ | |
679 | gm_phy_write(hw, port, 17, eee_afe[i].val); | |
680 | gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); | |
681 | } | |
682 | ||
683 | /* End Workaround for OptimaEEE */ | |
684 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
685 | ||
686 | /* Enable 10Base-Te (EEE) */ | |
687 | if (hw->chip_id >= CHIP_ID_YUKON_PRM) { | |
688 | reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); | |
689 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, | |
690 | reg | PHY_M_10B_TE_ENABLE); | |
691 | } | |
977bdf06 | 692 | } |
2eaba1a2 | 693 | |
d571b694 | 694 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
0ea065e5 | 695 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
cd28ab6a SH |
696 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); |
697 | else | |
698 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
699 | } | |
700 | ||
b96936da SH |
701 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
702 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; | |
703 | ||
704 | static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) | |
d3bcfbeb SH |
705 | { |
706 | u32 reg1; | |
d3bcfbeb | 707 | |
a40ccc68 | 708 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b32f40c4 | 709 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
b96936da | 710 | reg1 &= ~phy_power[port]; |
d3bcfbeb | 711 | |
4b7c47aa | 712 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ff35164e SH |
713 | reg1 |= coma_mode[port]; |
714 | ||
b32f40c4 | 715 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
a40ccc68 | 716 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
82637e80 | 717 | sky2_pci_read32(hw, PCI_DEV_REG1); |
f71eb1a2 SH |
718 | |
719 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
720 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); | |
721 | else if (hw->flags & SKY2_HW_ADV_POWER_CTL) | |
722 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
b96936da | 723 | } |
167f53d0 | 724 | |
b96936da SH |
725 | static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) |
726 | { | |
727 | u32 reg1; | |
db99b988 SH |
728 | u16 ctrl; |
729 | ||
730 | /* release GPHY Control reset */ | |
731 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
732 | ||
733 | /* release GMAC reset */ | |
734 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
735 | ||
736 | if (hw->flags & SKY2_HW_NEWER_PHY) { | |
737 | /* select page 2 to access MAC control register */ | |
738 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
739 | ||
740 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
741 | /* allow GMII Power Down */ | |
742 | ctrl &= ~PHY_M_MAC_GMIF_PUP; | |
743 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
744 | ||
745 | /* set page register back to 0 */ | |
746 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
747 | } | |
748 | ||
749 | /* setup General Purpose Control Register */ | |
750 | gma_write16(hw, port, GM_GP_CTRL, | |
0ea065e5 SH |
751 | GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | |
752 | GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | | |
753 | GM_GPCR_AU_SPD_DIS); | |
db99b988 SH |
754 | |
755 | if (hw->chip_id != CHIP_ID_YUKON_EC) { | |
756 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
e484d5f5 RW |
757 | /* select page 2 to access MAC control register */ |
758 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
db99b988 | 759 | |
e484d5f5 | 760 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
db99b988 SH |
761 | /* enable Power Down */ |
762 | ctrl |= PHY_M_PC_POW_D_ENA; | |
763 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
e484d5f5 RW |
764 | |
765 | /* set page register back to 0 */ | |
766 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
db99b988 SH |
767 | } |
768 | ||
769 | /* set IEEE compatible Power Down Mode (dev. #4.99) */ | |
770 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); | |
771 | } | |
b96936da | 772 | |
a40ccc68 | 773 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b96936da | 774 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
db99b988 | 775 | reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ |
b96936da | 776 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
a40ccc68 | 777 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
d3bcfbeb SH |
778 | } |
779 | ||
8e11680f | 780 | /* configure IPG according to used link speed */ |
781 | static void sky2_set_ipg(struct sky2_port *sky2) | |
782 | { | |
783 | u16 reg; | |
784 | ||
785 | reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); | |
786 | reg &= ~GM_SMOD_IPG_MSK; | |
787 | if (sky2->speed > SPEED_100) | |
788 | reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); | |
789 | else | |
790 | reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); | |
791 | gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); | |
792 | } | |
793 | ||
38000a94 BP |
794 | /* Enable Rx/Tx */ |
795 | static void sky2_enable_rx_tx(struct sky2_port *sky2) | |
796 | { | |
797 | struct sky2_hw *hw = sky2->hw; | |
798 | unsigned port = sky2->port; | |
799 | u16 reg; | |
800 | ||
801 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
802 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
803 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
804 | } | |
805 | ||
1b537565 SH |
806 | /* Force a renegotiation */ |
807 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
808 | { | |
e07b1aa8 | 809 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 810 | sky2_phy_init(sky2->hw, sky2->port); |
38000a94 | 811 | sky2_enable_rx_tx(sky2); |
e07b1aa8 | 812 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
813 | } |
814 | ||
e3173832 SH |
815 | /* Put device in state to listen for Wake On Lan */ |
816 | static void sky2_wol_init(struct sky2_port *sky2) | |
817 | { | |
818 | struct sky2_hw *hw = sky2->hw; | |
819 | unsigned port = sky2->port; | |
820 | enum flow_control save_mode; | |
821 | u16 ctrl; | |
e3173832 SH |
822 | |
823 | /* Bring hardware out of reset */ | |
824 | sky2_write16(hw, B0_CTST, CS_RST_CLR); | |
825 | sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
826 | ||
827 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
828 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
829 | ||
830 | /* Force to 10/100 | |
831 | * sky2_reset will re-enable on resume | |
832 | */ | |
833 | save_mode = sky2->flow_mode; | |
834 | ctrl = sky2->advertising; | |
835 | ||
836 | sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); | |
837 | sky2->flow_mode = FC_NONE; | |
b96936da SH |
838 | |
839 | spin_lock_bh(&sky2->phy_lock); | |
840 | sky2_phy_power_up(hw, port); | |
841 | sky2_phy_init(hw, port); | |
842 | spin_unlock_bh(&sky2->phy_lock); | |
e3173832 SH |
843 | |
844 | sky2->flow_mode = save_mode; | |
845 | sky2->advertising = ctrl; | |
846 | ||
847 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
848 | gma_write16(hw, port, GM_GP_CTRL, | |
849 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
850 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
851 | ||
852 | /* Set WOL address */ | |
853 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
854 | sky2->netdev->dev_addr, ETH_ALEN); | |
855 | ||
856 | /* Turn on appropriate WOL control bits */ | |
857 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
858 | ctrl = 0; | |
859 | if (sky2->wol & WAKE_PHY) | |
860 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
861 | else | |
862 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
863 | ||
864 | if (sky2->wol & WAKE_MAGIC) | |
865 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
866 | else | |
a419aef8 | 867 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; |
e3173832 SH |
868 | |
869 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
870 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
871 | ||
5f8ae5c5 | 872 | /* Disable PiG firmware */ |
873 | sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); | |
874 | ||
5676cc7b | 875 | /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */ |
876 | if (legacy_pme) { | |
877 | u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); | |
878 | reg1 |= PCI_Y2_PME_LEGACY; | |
879 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | |
880 | } | |
881 | ||
e3173832 SH |
882 | /* block receiver */ |
883 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
f9687c44 | 884 | sky2_read32(hw, B0_CTST); |
e3173832 SH |
885 | } |
886 | ||
69161611 SH |
887 | static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) |
888 | { | |
05745c4a SH |
889 | struct net_device *dev = hw->dev[port]; |
890 | ||
ed4d4161 SH |
891 | if ( (hw->chip_id == CHIP_ID_YUKON_EX && |
892 | hw->chip_rev != CHIP_REV_YU_EX_A0) || | |
877c8570 | 893 | hw->chip_id >= CHIP_ID_YUKON_FE_P) { |
ed4d4161 | 894 | /* Yukon-Extreme B0 and further Extreme devices */ |
44dde56d | 895 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); |
896 | } else if (dev->mtu > ETH_DATA_LEN) { | |
897 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
898 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), | |
899 | (ECU_JUMBO_WM << 16) | ECU_AE_THR); | |
05745c4a | 900 | |
44dde56d | 901 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); |
902 | } else | |
903 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); | |
69161611 SH |
904 | } |
905 | ||
cd28ab6a SH |
906 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
907 | { | |
908 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
909 | u16 reg; | |
25cccecc | 910 | u32 rx_reg; |
cd28ab6a SH |
911 | int i; |
912 | const u8 *addr = hw->dev[port]->dev_addr; | |
913 | ||
f350339c SH |
914 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
915 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
cd28ab6a SH |
916 | |
917 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
918 | ||
4b7c47aa | 919 | if (hw->chip_id == CHIP_ID_YUKON_XL && |
920 | hw->chip_rev == CHIP_REV_YU_XL_A0 && | |
921 | port == 1) { | |
cd28ab6a SH |
922 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
923 | /* clear GMAC 1 Control reset */ | |
924 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
925 | do { | |
926 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
927 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
928 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
929 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
930 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
931 | } | |
932 | ||
793b883e | 933 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 934 | |
2eaba1a2 SH |
935 | /* Enable Transmit FIFO Underrun */ |
936 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); | |
937 | ||
e07b1aa8 | 938 | spin_lock_bh(&sky2->phy_lock); |
b96936da | 939 | sky2_phy_power_up(hw, port); |
cd28ab6a | 940 | sky2_phy_init(hw, port); |
e07b1aa8 | 941 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
942 | |
943 | /* MIB clear */ | |
944 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
945 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
946 | ||
43f2f104 SH |
947 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
948 | gma_read16(hw, port, i); | |
cd28ab6a SH |
949 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
950 | ||
951 | /* transmit control */ | |
952 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
953 | ||
954 | /* receive control reg: unicast + multicast + no FCS */ | |
955 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 956 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
957 | |
958 | /* transmit flow control */ | |
959 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
960 | ||
961 | /* transmit parameter */ | |
962 | gma_write16(hw, port, GM_TX_PARAM, | |
963 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
964 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
965 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
966 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
967 | ||
968 | /* serial mode register */ | |
969 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
8e11680f | 970 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); |
cd28ab6a | 971 | |
6b1a3aef | 972 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
973 | reg |= GM_SMOD_JUMBO_ENA; |
974 | ||
c1cd0a85 | 975 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
976 | hw->chip_rev == CHIP_REV_YU_EC_U_B1) | |
977 | reg |= GM_NEW_FLOW_CTRL; | |
978 | ||
cd28ab6a SH |
979 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
980 | ||
cd28ab6a SH |
981 | /* virtual address for data */ |
982 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
983 | ||
793b883e SH |
984 | /* physical address: used for pause frames */ |
985 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
986 | ||
987 | /* ignore counter overflows */ | |
cd28ab6a SH |
988 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
989 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
990 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
991 | ||
992 | /* Configure Rx MAC FIFO */ | |
993 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
25cccecc | 994 | rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
05745c4a SH |
995 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
996 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
25cccecc | 997 | rx_reg |= GMF_RX_OVER_ON; |
69161611 | 998 | |
25cccecc | 999 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); |
cd28ab6a | 1000 | |
798fdd07 SH |
1001 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1002 | /* Hardware errata - clear flush mask */ | |
1003 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); | |
1004 | } else { | |
1005 | /* Flush Rx MAC FIFO on any flow control or error */ | |
1006 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); | |
1007 | } | |
cd28ab6a | 1008 | |
8df9a876 | 1009 | /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ |
05745c4a SH |
1010 | reg = RX_GMF_FL_THR_DEF + 1; |
1011 | /* Another magic mystery workaround from sk98lin */ | |
1012 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
1013 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
1014 | reg = 0x178; | |
1015 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); | |
cd28ab6a SH |
1016 | |
1017 | /* Configure Tx MAC FIFO */ | |
1018 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
1019 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 1020 | |
25985edc | 1021 | /* On chips without ram buffer, pause is controlled by MAC level */ |
39dbd958 | 1022 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { |
d6b54d24 | 1023 | /* Pause threshold is scaled by 8 in bytes */ |
8e95a202 JP |
1024 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
1025 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
d6b54d24 SH |
1026 | reg = 1568 / 8; |
1027 | else | |
1028 | reg = 1024 / 8; | |
1029 | sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); | |
1030 | sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); | |
b628ed98 | 1031 | |
69161611 | 1032 | sky2_set_tx_stfwd(hw, port); |
5a5b1ea0 SH |
1033 | } |
1034 | ||
e970d1f8 SH |
1035 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
1036 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
1037 | /* disable dynamic watermark */ | |
1038 | reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); | |
1039 | reg &= ~TX_DYN_WM_ENA; | |
1040 | sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); | |
1041 | } | |
cd28ab6a SH |
1042 | } |
1043 | ||
67712901 SH |
1044 | /* Assign Ram Buffer allocation to queue */ |
1045 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) | |
cd28ab6a | 1046 | { |
67712901 SH |
1047 | u32 end; |
1048 | ||
1049 | /* convert from K bytes to qwords used for hw register */ | |
1050 | start *= 1024/8; | |
1051 | space *= 1024/8; | |
1052 | end = start + space - 1; | |
793b883e | 1053 | |
cd28ab6a SH |
1054 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
1055 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
1056 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
1057 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
1058 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
1059 | ||
1060 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba | 1061 | u32 tp = space - space/4; |
793b883e | 1062 | |
1c28f6ba SH |
1063 | /* On receive queue's set the thresholds |
1064 | * give receiver priority when > 3/4 full | |
1065 | * send pause when down to 2K | |
1066 | */ | |
1067 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
1068 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 1069 | |
74f9f42c | 1070 | tp = space - 8192/8; |
1c28f6ba SH |
1071 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); |
1072 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
1073 | } else { |
1074 | /* Enable store & forward on Tx queue's because | |
1075 | * Tx FIFO is only 1K on Yukon | |
1076 | */ | |
1077 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
1078 | } | |
1079 | ||
1080 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 1081 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
1082 | } |
1083 | ||
cd28ab6a | 1084 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 1085 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
1086 | { |
1087 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
1088 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
1089 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 1090 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
1091 | } |
1092 | ||
cd28ab6a SH |
1093 | /* Setup prefetch unit registers. This is the interface between |
1094 | * hardware and driver list elements | |
1095 | */ | |
8cc048e3 | 1096 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
d6e74b6b | 1097 | dma_addr_t addr, u32 last) |
cd28ab6a | 1098 | { |
cd28ab6a SH |
1099 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
1100 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
d6e74b6b SH |
1101 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); |
1102 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); | |
cd28ab6a SH |
1103 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); |
1104 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
1105 | |
1106 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
1107 | } |
1108 | ||
9b289c33 | 1109 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) |
793b883e | 1110 | { |
9b289c33 | 1111 | struct sky2_tx_le *le = sky2->tx_le + *slot; |
793b883e | 1112 | |
ee5f68fe | 1113 | *slot = RING_NEXT(*slot, sky2->tx_ring_size); |
291ea614 | 1114 | le->ctrl = 0; |
793b883e SH |
1115 | return le; |
1116 | } | |
cd28ab6a | 1117 | |
88f5f0ca SH |
1118 | static void tx_init(struct sky2_port *sky2) |
1119 | { | |
1120 | struct sky2_tx_le *le; | |
1121 | ||
1122 | sky2->tx_prod = sky2->tx_cons = 0; | |
1123 | sky2->tx_tcpsum = 0; | |
1124 | sky2->tx_last_mss = 0; | |
ec2a5466 | 1125 | netdev_reset_queue(sky2->netdev); |
88f5f0ca | 1126 | |
9b289c33 | 1127 | le = get_tx_le(sky2, &sky2->tx_prod); |
88f5f0ca SH |
1128 | le->addr = 0; |
1129 | le->opcode = OP_ADDR64 | HW_OWNER; | |
5dce95e5 | 1130 | sky2->tx_last_upper = 0; |
88f5f0ca SH |
1131 | } |
1132 | ||
290d4de5 SH |
1133 | /* Update chip's next pointer */ |
1134 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 1135 | { |
50432cb5 | 1136 | /* Make sure write' to descriptors are complete before we tell hardware */ |
762c2de2 | 1137 | wmb(); |
50432cb5 SH |
1138 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
1139 | ||
1140 | /* Synchronize I/O on since next processor may write to tail */ | |
1141 | mmiowb(); | |
cd28ab6a SH |
1142 | } |
1143 | ||
793b883e | 1144 | |
cd28ab6a SH |
1145 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
1146 | { | |
1147 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
cb5d9547 | 1148 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
291ea614 | 1149 | le->ctrl = 0; |
cd28ab6a SH |
1150 | return le; |
1151 | } | |
1152 | ||
060b946c | 1153 | static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) |
39ef110b MM |
1154 | { |
1155 | unsigned size; | |
1156 | ||
1157 | /* Space needed for frame data + headers rounded up */ | |
1158 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); | |
1159 | ||
1160 | /* Stopping point for hardware truncation */ | |
1161 | return (size - 8) / sizeof(u32); | |
1162 | } | |
1163 | ||
060b946c | 1164 | static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) |
39ef110b MM |
1165 | { |
1166 | struct rx_ring_info *re; | |
1167 | unsigned size; | |
1168 | ||
1169 | /* Space needed for frame data + headers rounded up */ | |
1170 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); | |
1171 | ||
1172 | sky2->rx_nfrags = size >> PAGE_SHIFT; | |
1173 | BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); | |
1174 | ||
1175 | /* Compute residue after pages */ | |
1176 | size -= sky2->rx_nfrags << PAGE_SHIFT; | |
1177 | ||
1178 | /* Optimize to handle small packets and headers */ | |
1179 | if (size < copybreak) | |
1180 | size = copybreak; | |
1181 | if (size < ETH_HLEN) | |
1182 | size = ETH_HLEN; | |
1183 | ||
1184 | return size; | |
1185 | } | |
1186 | ||
14d0263f | 1187 | /* Build description to hardware for one receive segment */ |
060b946c | 1188 | static void sky2_rx_add(struct sky2_port *sky2, u8 op, |
14d0263f | 1189 | dma_addr_t map, unsigned len) |
cd28ab6a SH |
1190 | { |
1191 | struct sky2_rx_le *le; | |
1192 | ||
86c6887e | 1193 | if (sizeof(dma_addr_t) > sizeof(u32)) { |
cd28ab6a | 1194 | le = sky2_next_rx(sky2); |
86c6887e | 1195 | le->addr = cpu_to_le32(upper_32_bits(map)); |
cd28ab6a SH |
1196 | le->opcode = OP_ADDR64 | HW_OWNER; |
1197 | } | |
793b883e | 1198 | |
cd28ab6a | 1199 | le = sky2_next_rx(sky2); |
d6e74b6b | 1200 | le->addr = cpu_to_le32(lower_32_bits(map)); |
734d1868 | 1201 | le->length = cpu_to_le16(len); |
14d0263f | 1202 | le->opcode = op | HW_OWNER; |
cd28ab6a SH |
1203 | } |
1204 | ||
14d0263f SH |
1205 | /* Build description to hardware for one possibly fragmented skb */ |
1206 | static void sky2_rx_submit(struct sky2_port *sky2, | |
1207 | const struct rx_ring_info *re) | |
1208 | { | |
1209 | int i; | |
1210 | ||
1211 | sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); | |
1212 | ||
1213 | for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) | |
1214 | sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); | |
1215 | } | |
1216 | ||
1217 | ||
454e6cb6 | 1218 | static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, |
14d0263f SH |
1219 | unsigned size) |
1220 | { | |
1221 | struct sk_buff *skb = re->skb; | |
1222 | int i; | |
1223 | ||
1224 | re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); | |
3fbd9187 | 1225 | if (pci_dma_mapping_error(pdev, re->data_addr)) |
1226 | goto mapping_error; | |
454e6cb6 | 1227 | |
7cd26ce5 | 1228 | dma_unmap_len_set(re, data_size, size); |
14d0263f | 1229 | |
3fbd9187 | 1230 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
9e903e08 | 1231 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
3fbd9187 | 1232 | |
950a5a4f | 1233 | re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, |
9e903e08 | 1234 | skb_frag_size(frag), |
5d6bcdfe | 1235 | DMA_FROM_DEVICE); |
3fbd9187 | 1236 | |
5d6bcdfe | 1237 | if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) |
3fbd9187 | 1238 | goto map_page_error; |
1239 | } | |
454e6cb6 | 1240 | return 0; |
3fbd9187 | 1241 | |
1242 | map_page_error: | |
1243 | while (--i >= 0) { | |
1244 | pci_unmap_page(pdev, re->frag_addr[i], | |
9e903e08 | 1245 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
3fbd9187 | 1246 | PCI_DMA_FROMDEVICE); |
1247 | } | |
1248 | ||
7cd26ce5 | 1249 | pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), |
3fbd9187 | 1250 | PCI_DMA_FROMDEVICE); |
1251 | ||
1252 | mapping_error: | |
1253 | if (net_ratelimit()) | |
1254 | dev_warn(&pdev->dev, "%s: rx mapping error\n", | |
1255 | skb->dev->name); | |
1256 | return -EIO; | |
14d0263f SH |
1257 | } |
1258 | ||
1259 | static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) | |
1260 | { | |
1261 | struct sk_buff *skb = re->skb; | |
1262 | int i; | |
1263 | ||
7cd26ce5 | 1264 | pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), |
14d0263f SH |
1265 | PCI_DMA_FROMDEVICE); |
1266 | ||
1267 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) | |
1268 | pci_unmap_page(pdev, re->frag_addr[i], | |
9e903e08 | 1269 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
14d0263f SH |
1270 | PCI_DMA_FROMDEVICE); |
1271 | } | |
793b883e | 1272 | |
cd28ab6a SH |
1273 | /* Tell chip where to start receive checksum. |
1274 | * Actually has two checksums, but set both same to avoid possible byte | |
1275 | * order problems. | |
1276 | */ | |
793b883e | 1277 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a | 1278 | { |
ea76e635 | 1279 | struct sky2_rx_le *le = sky2_next_rx(sky2); |
793b883e | 1280 | |
ea76e635 SH |
1281 | le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); |
1282 | le->ctrl = 0; | |
1283 | le->opcode = OP_TCPSTART | HW_OWNER; | |
cd28ab6a | 1284 | |
ea76e635 SH |
1285 | sky2_write32(sky2->hw, |
1286 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
f5d64037 | 1287 | (sky2->netdev->features & NETIF_F_RXCSUM) |
0ea065e5 | 1288 | ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); |
cd28ab6a SH |
1289 | } |
1290 | ||
00427a73 | 1291 | /* |
1292 | * Fixed initial key as seed to RSS. | |
1293 | */ | |
1294 | static const uint32_t rss_init_key[10] = { | |
1295 | 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43, | |
1296 | 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30 | |
1297 | }; | |
1298 | ||
bf73130d | 1299 | /* Enable/disable receive hash calculation (RSS) */ |
c8f44aff | 1300 | static void rx_set_rss(struct net_device *dev, netdev_features_t features) |
bf73130d SH |
1301 | { |
1302 | struct sky2_port *sky2 = netdev_priv(dev); | |
1303 | struct sky2_hw *hw = sky2->hw; | |
1304 | int i, nkeys = 4; | |
1305 | ||
1306 | /* Supports IPv6 and other modes */ | |
1307 | if (hw->flags & SKY2_HW_NEW_LE) { | |
1308 | nkeys = 10; | |
1309 | sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); | |
1310 | } | |
1311 | ||
1312 | /* Program RSS initial values */ | |
f5d64037 | 1313 | if (features & NETIF_F_RXHASH) { |
bf73130d SH |
1314 | for (i = 0; i < nkeys; i++) |
1315 | sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), | |
00427a73 | 1316 | rss_init_key[i]); |
bf73130d SH |
1317 | |
1318 | /* Need to turn on (undocumented) flag to make hashing work */ | |
1319 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), | |
1320 | RX_STFW_ENA); | |
1321 | ||
1322 | sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1323 | BMU_ENA_RX_RSS_HASH); | |
1324 | } else | |
1325 | sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1326 | BMU_DIS_RX_RSS_HASH); | |
1327 | } | |
1328 | ||
6b1a3aef SH |
1329 | /* |
1330 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
1331 | * reach the end of packet and since we can't make sure that we have | |
1332 | * incoming data, we must reset the BMU while it is not doing a DMA | |
1333 | * transfer. Since it is possible that the RX path is still active, | |
1334 | * the RX RAM buffer will be stopped first, so any possible incoming | |
1335 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
1336 | * BMU is polled until any DMA in progress is ended and only then it | |
1337 | * will be reset. | |
1338 | */ | |
1339 | static void sky2_rx_stop(struct sky2_port *sky2) | |
1340 | { | |
1341 | struct sky2_hw *hw = sky2->hw; | |
1342 | unsigned rxq = rxqaddr[sky2->port]; | |
1343 | int i; | |
1344 | ||
1345 | /* disable the RAM Buffer receive queue */ | |
1346 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
1347 | ||
1348 | for (i = 0; i < 0xffff; i++) | |
1349 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
1350 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
1351 | goto stopped; | |
1352 | ||
ada1db5c | 1353 | netdev_warn(sky2->netdev, "receiver stop failed\n"); |
6b1a3aef SH |
1354 | stopped: |
1355 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
1356 | ||
1357 | /* reset the Rx prefetch unit */ | |
1358 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
3d1454dd | 1359 | mmiowb(); |
6b1a3aef | 1360 | } |
793b883e | 1361 | |
d571b694 | 1362 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
1363 | static void sky2_rx_clean(struct sky2_port *sky2) |
1364 | { | |
1365 | unsigned i; | |
1366 | ||
1367 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 1368 | for (i = 0; i < sky2->rx_pending; i++) { |
291ea614 | 1369 | struct rx_ring_info *re = sky2->rx_ring + i; |
cd28ab6a SH |
1370 | |
1371 | if (re->skb) { | |
14d0263f | 1372 | sky2_rx_unmap_skb(sky2->hw->pdev, re); |
cd28ab6a SH |
1373 | kfree_skb(re->skb); |
1374 | re->skb = NULL; | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | ||
ef743d33 SH |
1379 | /* Basic MII support */ |
1380 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1381 | { | |
1382 | struct mii_ioctl_data *data = if_mii(ifr); | |
1383 | struct sky2_port *sky2 = netdev_priv(dev); | |
1384 | struct sky2_hw *hw = sky2->hw; | |
1385 | int err = -EOPNOTSUPP; | |
1386 | ||
1387 | if (!netif_running(dev)) | |
1388 | return -ENODEV; /* Phy still in reset */ | |
1389 | ||
d89e1343 | 1390 | switch (cmd) { |
ef743d33 SH |
1391 | case SIOCGMIIPHY: |
1392 | data->phy_id = PHY_ADDR_MARV; | |
1393 | ||
1394 | /* fallthru */ | |
1395 | case SIOCGMIIREG: { | |
1396 | u16 val = 0; | |
91c86df5 | 1397 | |
e07b1aa8 | 1398 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 1399 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 1400 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 1401 | |
ef743d33 SH |
1402 | data->val_out = val; |
1403 | break; | |
1404 | } | |
1405 | ||
1406 | case SIOCSMIIREG: | |
e07b1aa8 | 1407 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 SH |
1408 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
1409 | data->val_in); | |
e07b1aa8 | 1410 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 SH |
1411 | break; |
1412 | } | |
1413 | return err; | |
1414 | } | |
1415 | ||
f5d64037 | 1416 | #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) |
d494eacd | 1417 | |
c8f44aff | 1418 | static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) |
d494eacd SH |
1419 | { |
1420 | struct sky2_port *sky2 = netdev_priv(dev); | |
1421 | struct sky2_hw *hw = sky2->hw; | |
1422 | u16 port = sky2->port; | |
1423 | ||
f5d64037 | 1424 | if (features & NETIF_F_HW_VLAN_RX) |
86aa7785 SH |
1425 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
1426 | RX_VLAN_STRIP_ON); | |
1427 | else | |
1428 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), | |
1429 | RX_VLAN_STRIP_OFF); | |
d494eacd | 1430 | |
f5d64037 | 1431 | if (features & NETIF_F_HW_VLAN_TX) { |
86aa7785 SH |
1432 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1433 | TX_VLAN_TAG_ON); | |
f5d64037 MM |
1434 | |
1435 | dev->vlan_features |= SKY2_VLAN_OFFLOADS; | |
1436 | } else { | |
86aa7785 SH |
1437 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1438 | TX_VLAN_TAG_OFF); | |
d1f13708 | 1439 | |
86aa7785 | 1440 | /* Can't do transmit offload of vlan without hw vlan */ |
f5d64037 | 1441 | dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; |
86aa7785 | 1442 | } |
d1f13708 | 1443 | } |
d1f13708 | 1444 | |
bd1c6869 SH |
1445 | /* Amount of required worst case padding in rx buffer */ |
1446 | static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) | |
1447 | { | |
1448 | return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; | |
1449 | } | |
1450 | ||
82788c7a | 1451 | /* |
14d0263f SH |
1452 | * Allocate an skb for receiving. If the MTU is large enough |
1453 | * make the skb non-linear with a fragment list of pages. | |
82788c7a | 1454 | */ |
68ac3191 | 1455 | static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) |
82788c7a SH |
1456 | { |
1457 | struct sk_buff *skb; | |
14d0263f | 1458 | int i; |
82788c7a | 1459 | |
68ac3191 ED |
1460 | skb = __netdev_alloc_skb(sky2->netdev, |
1461 | sky2->rx_data_size + sky2_rx_pad(sky2->hw), | |
1462 | gfp); | |
bd1c6869 SH |
1463 | if (!skb) |
1464 | goto nomem; | |
1465 | ||
39dbd958 | 1466 | if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { |
f03b8654 SH |
1467 | unsigned char *start; |
1468 | /* | |
1469 | * Workaround for a bug in FIFO that cause hang | |
1470 | * if the FIFO if the receive buffer is not 64 byte aligned. | |
1471 | * The buffer returned from netdev_alloc_skb is | |
1472 | * aligned except if slab debugging is enabled. | |
1473 | */ | |
f03b8654 SH |
1474 | start = PTR_ALIGN(skb->data, 8); |
1475 | skb_reserve(skb, start - skb->data); | |
bd1c6869 | 1476 | } else |
f03b8654 | 1477 | skb_reserve(skb, NET_IP_ALIGN); |
14d0263f SH |
1478 | |
1479 | for (i = 0; i < sky2->rx_nfrags; i++) { | |
68ac3191 | 1480 | struct page *page = alloc_page(gfp); |
14d0263f SH |
1481 | |
1482 | if (!page) | |
1483 | goto free_partial; | |
1484 | skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); | |
82788c7a SH |
1485 | } |
1486 | ||
1487 | return skb; | |
14d0263f SH |
1488 | free_partial: |
1489 | kfree_skb(skb); | |
1490 | nomem: | |
1491 | return NULL; | |
82788c7a SH |
1492 | } |
1493 | ||
55c9dd35 SH |
1494 | static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) |
1495 | { | |
1496 | sky2_put_idx(sky2->hw, rxq, sky2->rx_put); | |
1497 | } | |
1498 | ||
200ac492 MM |
1499 | static int sky2_alloc_rx_skbs(struct sky2_port *sky2) |
1500 | { | |
1501 | struct sky2_hw *hw = sky2->hw; | |
1502 | unsigned i; | |
1503 | ||
1504 | sky2->rx_data_size = sky2_get_rx_data_size(sky2); | |
1505 | ||
1506 | /* Fill Rx ring */ | |
1507 | for (i = 0; i < sky2->rx_pending; i++) { | |
1508 | struct rx_ring_info *re = sky2->rx_ring + i; | |
1509 | ||
68ac3191 | 1510 | re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); |
200ac492 MM |
1511 | if (!re->skb) |
1512 | return -ENOMEM; | |
1513 | ||
1514 | if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { | |
1515 | dev_kfree_skb(re->skb); | |
1516 | re->skb = NULL; | |
1517 | return -ENOMEM; | |
1518 | } | |
1519 | } | |
1520 | return 0; | |
1521 | } | |
1522 | ||
cd28ab6a | 1523 | /* |
200ac492 | 1524 | * Setup receiver buffer pool. |
14d0263f SH |
1525 | * Normal case this ends up creating one list element for skb |
1526 | * in the receive ring. Worst case if using large MTU and each | |
1527 | * allocation falls on a different 64 bit region, that results | |
1528 | * in 6 list elements per ring entry. | |
1529 | * One element is used for checksum enable/disable, and one | |
1530 | * extra to avoid wrap. | |
cd28ab6a | 1531 | */ |
200ac492 | 1532 | static void sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 1533 | { |
6b1a3aef | 1534 | struct sky2_hw *hw = sky2->hw; |
14d0263f | 1535 | struct rx_ring_info *re; |
6b1a3aef | 1536 | unsigned rxq = rxqaddr[sky2->port]; |
39ef110b | 1537 | unsigned i, thresh; |
cd28ab6a | 1538 | |
6b1a3aef | 1539 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 1540 | sky2_qset(hw, rxq); |
977bdf06 | 1541 | |
c3905bc4 | 1542 | /* On PCI express lowering the watermark gives better performance */ |
1a10ccae | 1543 | if (pci_is_pcie(hw->pdev)) |
c3905bc4 SH |
1544 | sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); |
1545 | ||
1546 | /* These chips have no ram buffer? | |
1547 | * MAC Rx RAM Read is controlled by hardware */ | |
8df9a876 | 1548 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
c1cd0a85 | 1549 | hw->chip_rev > CHIP_REV_YU_EC_U_A0) |
f449c7c1 | 1550 | sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); |
977bdf06 | 1551 | |
6b1a3aef SH |
1552 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
1553 | ||
ea76e635 SH |
1554 | if (!(hw->flags & SKY2_HW_NEW_LE)) |
1555 | rx_set_checksum(sky2); | |
14d0263f | 1556 | |
bf73130d | 1557 | if (!(hw->flags & SKY2_HW_RSS_BROKEN)) |
f5d64037 | 1558 | rx_set_rss(sky2->netdev, sky2->netdev->features); |
bf73130d | 1559 | |
200ac492 | 1560 | /* submit Rx ring */ |
793b883e | 1561 | for (i = 0; i < sky2->rx_pending; i++) { |
14d0263f | 1562 | re = sky2->rx_ring + i; |
14d0263f | 1563 | sky2_rx_submit(sky2, re); |
cd28ab6a SH |
1564 | } |
1565 | ||
a1433ac4 SH |
1566 | /* |
1567 | * The receiver hangs if it receives frames larger than the | |
1568 | * packet buffer. As a workaround, truncate oversize frames, but | |
1569 | * the register is limited to 9 bits, so if you do frames > 2052 | |
1570 | * you better get the MTU right! | |
1571 | */ | |
39ef110b | 1572 | thresh = sky2_get_rx_threshold(sky2); |
a1433ac4 SH |
1573 | if (thresh > 0x1ff) |
1574 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); | |
1575 | else { | |
1576 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); | |
1577 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
1578 | } | |
1579 | ||
6b1a3aef | 1580 | /* Tell chip about available buffers */ |
55c9dd35 | 1581 | sky2_rx_update(sky2, rxq); |
877c8570 SH |
1582 | |
1583 | if (hw->chip_id == CHIP_ID_YUKON_EX || | |
1584 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
1585 | /* | |
1586 | * Disable flushing of non ASF packets; | |
1587 | * must be done after initializing the BMUs; | |
1588 | * drivers without ASF support should do this too, otherwise | |
1589 | * it may happen that they cannot run on ASF devices; | |
1590 | * remember that the MAC FIFO isn't reset during initialization. | |
1591 | */ | |
1592 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); | |
1593 | } | |
1594 | ||
1595 | if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { | |
1596 | /* Enable RX Home Address & Routing Header checksum fix */ | |
1597 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), | |
1598 | RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); | |
1599 | ||
1600 | /* Enable TX Home Address & Routing Header checksum fix */ | |
1601 | sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), | |
1602 | TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); | |
1603 | } | |
cd28ab6a SH |
1604 | } |
1605 | ||
90bbebb4 MM |
1606 | static int sky2_alloc_buffers(struct sky2_port *sky2) |
1607 | { | |
1608 | struct sky2_hw *hw = sky2->hw; | |
1609 | ||
1610 | /* must be power of 2 */ | |
1611 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
1612 | sky2->tx_ring_size * | |
1613 | sizeof(struct sky2_tx_le), | |
1614 | &sky2->tx_le_map); | |
1615 | if (!sky2->tx_le) | |
1616 | goto nomem; | |
1617 | ||
1618 | sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), | |
1619 | GFP_KERNEL); | |
1620 | if (!sky2->tx_ring) | |
1621 | goto nomem; | |
1622 | ||
1623 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1624 | &sky2->rx_le_map); | |
1625 | if (!sky2->rx_le) | |
1626 | goto nomem; | |
1627 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1628 | ||
1629 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), | |
1630 | GFP_KERNEL); | |
1631 | if (!sky2->rx_ring) | |
1632 | goto nomem; | |
1633 | ||
200ac492 | 1634 | return sky2_alloc_rx_skbs(sky2); |
90bbebb4 MM |
1635 | nomem: |
1636 | return -ENOMEM; | |
1637 | } | |
1638 | ||
1639 | static void sky2_free_buffers(struct sky2_port *sky2) | |
1640 | { | |
1641 | struct sky2_hw *hw = sky2->hw; | |
1642 | ||
200ac492 MM |
1643 | sky2_rx_clean(sky2); |
1644 | ||
90bbebb4 MM |
1645 | if (sky2->rx_le) { |
1646 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1647 | sky2->rx_le, sky2->rx_le_map); | |
1648 | sky2->rx_le = NULL; | |
1649 | } | |
1650 | if (sky2->tx_le) { | |
1651 | pci_free_consistent(hw->pdev, | |
1652 | sky2->tx_ring_size * sizeof(struct sky2_tx_le), | |
1653 | sky2->tx_le, sky2->tx_le_map); | |
1654 | sky2->tx_le = NULL; | |
1655 | } | |
1656 | kfree(sky2->tx_ring); | |
1657 | kfree(sky2->rx_ring); | |
1658 | ||
1659 | sky2->tx_ring = NULL; | |
1660 | sky2->rx_ring = NULL; | |
1661 | } | |
1662 | ||
ea0f71e5 | 1663 | static void sky2_hw_up(struct sky2_port *sky2) |
cd28ab6a | 1664 | { |
cd28ab6a SH |
1665 | struct sky2_hw *hw = sky2->hw; |
1666 | unsigned port = sky2->port; | |
ea0f71e5 MM |
1667 | u32 ramsize; |
1668 | int cap; | |
843a46f4 | 1669 | struct net_device *otherdev = hw->dev[sky2->port^1]; |
cd28ab6a | 1670 | |
ea0f71e5 MM |
1671 | tx_init(sky2); |
1672 | ||
ee7abb04 SH |
1673 | /* |
1674 | * On dual port PCI-X card, there is an problem where status | |
1675 | * can be received out of order due to split transactions | |
843a46f4 | 1676 | */ |
ee7abb04 SH |
1677 | if (otherdev && netif_running(otherdev) && |
1678 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | |
ee7abb04 SH |
1679 | u16 cmd; |
1680 | ||
b32f40c4 | 1681 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); |
ee7abb04 | 1682 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
b32f40c4 | 1683 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); |
ea0f71e5 | 1684 | } |
cd28ab6a | 1685 | |
cd28ab6a SH |
1686 | sky2_mac_init(hw, port); |
1687 | ||
e0c28116 SH |
1688 | /* Register is number of 4K blocks on internal RAM buffer. */ |
1689 | ramsize = sky2_read8(hw, B2_E_0) * 4; | |
1690 | if (ramsize > 0) { | |
67712901 | 1691 | u32 rxspace; |
cd28ab6a | 1692 | |
ada1db5c | 1693 | netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); |
67712901 SH |
1694 | if (ramsize < 16) |
1695 | rxspace = ramsize / 2; | |
1696 | else | |
1697 | rxspace = 8 + (2*(ramsize - 16))/3; | |
cd28ab6a | 1698 | |
67712901 SH |
1699 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1700 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
1701 | ||
1702 | /* Make sure SyncQ is disabled */ | |
1703 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1704 | RB_RST_SET); | |
1705 | } | |
793b883e | 1706 | |
af4ed7e6 | 1707 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1708 | |
69161611 SH |
1709 | /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ |
1710 | if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) | |
1711 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); | |
1712 | ||
977bdf06 | 1713 | /* Set almost empty threshold */ |
8e95a202 JP |
1714 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
1715 | hw->chip_rev == CHIP_REV_YU_EC_U_A0) | |
b628ed98 | 1716 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); |
5a5b1ea0 | 1717 | |
6b1a3aef | 1718 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
ee5f68fe | 1719 | sky2->tx_ring_size - 1); |
cd28ab6a | 1720 | |
f5d64037 MM |
1721 | sky2_vlan_mode(sky2->netdev, sky2->netdev->features); |
1722 | netdev_update_features(sky2->netdev); | |
d494eacd | 1723 | |
200ac492 | 1724 | sky2_rx_start(sky2); |
ea0f71e5 MM |
1725 | } |
1726 | ||
0bdb0bd0 | 1727 | /* Setup device IRQ and enable napi to process */ |
1728 | static int sky2_setup_irq(struct sky2_hw *hw, const char *name) | |
1729 | { | |
1730 | struct pci_dev *pdev = hw->pdev; | |
1731 | int err; | |
1732 | ||
1733 | err = request_irq(pdev->irq, sky2_intr, | |
1734 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, | |
1735 | name, hw); | |
1736 | if (err) | |
1737 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); | |
1738 | else { | |
282edcec | 1739 | hw->flags |= SKY2_HW_IRQ_SETUP; |
1740 | ||
0bdb0bd0 | 1741 | napi_enable(&hw->napi); |
1742 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | |
1743 | sky2_read32(hw, B0_IMSK); | |
1744 | } | |
1745 | ||
1746 | return err; | |
1747 | } | |
1748 | ||
1749 | ||
ea0f71e5 | 1750 | /* Bring up network interface. */ |
926d0977 | 1751 | static int sky2_open(struct net_device *dev) |
ea0f71e5 MM |
1752 | { |
1753 | struct sky2_port *sky2 = netdev_priv(dev); | |
1754 | struct sky2_hw *hw = sky2->hw; | |
1755 | unsigned port = sky2->port; | |
1756 | u32 imask; | |
1757 | int err; | |
1758 | ||
1759 | netif_carrier_off(dev); | |
1760 | ||
1761 | err = sky2_alloc_buffers(sky2); | |
1762 | if (err) | |
1763 | goto err_out; | |
1764 | ||
0bdb0bd0 | 1765 | /* With single port, IRQ is setup when device is brought up */ |
1766 | if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) | |
1767 | goto err_out; | |
1768 | ||
ea0f71e5 | 1769 | sky2_hw_up(sky2); |
cd28ab6a | 1770 | |
2240eb4a LS |
1771 | /* Enable interrupts from phy/mac for port */ |
1772 | imask = sky2_read32(hw, B0_IMSK); | |
1773 | ||
1401a800 | 1774 | if (hw->chip_id == CHIP_ID_YUKON_OPT || |
1775 | hw->chip_id == CHIP_ID_YUKON_PRM || | |
1776 | hw->chip_id == CHIP_ID_YUKON_OP_2) | |
1777 | imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ | |
1778 | ||
f4ea431b | 1779 | imask |= portirq_msk[port]; |
e07b1aa8 | 1780 | sky2_write32(hw, B0_IMSK, imask); |
1fd82f3c | 1781 | sky2_read32(hw, B0_IMSK); |
e07b1aa8 | 1782 | |
6c35abae | 1783 | netif_info(sky2, ifup, dev, "enabling interface\n"); |
af18d8b8 | 1784 | |
cd28ab6a SH |
1785 | return 0; |
1786 | ||
1787 | err_out: | |
90bbebb4 | 1788 | sky2_free_buffers(sky2); |
cd28ab6a SH |
1789 | return err; |
1790 | } | |
1791 | ||
793b883e | 1792 | /* Modular subtraction in ring */ |
ee5f68fe | 1793 | static inline int tx_inuse(const struct sky2_port *sky2) |
793b883e | 1794 | { |
ee5f68fe | 1795 | return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); |
793b883e | 1796 | } |
cd28ab6a | 1797 | |
793b883e SH |
1798 | /* Number of list elements available for next tx */ |
1799 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1800 | { |
ee5f68fe | 1801 | return sky2->tx_pending - tx_inuse(sky2); |
cd28ab6a SH |
1802 | } |
1803 | ||
793b883e | 1804 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1805 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1806 | { |
793b883e SH |
1807 | unsigned count; |
1808 | ||
07e31637 SH |
1809 | count = (skb_shinfo(skb)->nr_frags + 1) |
1810 | * (sizeof(dma_addr_t) / sizeof(u32)); | |
793b883e | 1811 | |
89114afd | 1812 | if (skb_is_gso(skb)) |
793b883e | 1813 | ++count; |
07e31637 SH |
1814 | else if (sizeof(dma_addr_t) == sizeof(u32)) |
1815 | ++count; /* possible vlan */ | |
793b883e | 1816 | |
84fa7933 | 1817 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
793b883e SH |
1818 | ++count; |
1819 | ||
1820 | return count; | |
cd28ab6a SH |
1821 | } |
1822 | ||
f6815077 | 1823 | static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) |
6b84daca SH |
1824 | { |
1825 | if (re->flags & TX_MAP_SINGLE) | |
7cd26ce5 FT |
1826 | pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), |
1827 | dma_unmap_len(re, maplen), | |
6b84daca SH |
1828 | PCI_DMA_TODEVICE); |
1829 | else if (re->flags & TX_MAP_PAGE) | |
7cd26ce5 FT |
1830 | pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), |
1831 | dma_unmap_len(re, maplen), | |
6b84daca | 1832 | PCI_DMA_TODEVICE); |
f6815077 | 1833 | re->flags = 0; |
6b84daca SH |
1834 | } |
1835 | ||
793b883e SH |
1836 | /* |
1837 | * Put one packet in ring for transmit. | |
1838 | * A single packet can generate multiple list elements, and | |
1839 | * the number of ring elements will probably be less than the number | |
1840 | * of list elements used. | |
1841 | */ | |
61357325 SH |
1842 | static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, |
1843 | struct net_device *dev) | |
cd28ab6a SH |
1844 | { |
1845 | struct sky2_port *sky2 = netdev_priv(dev); | |
1846 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1847 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1848 | struct tx_ring_info *re; |
9b289c33 | 1849 | unsigned i, len; |
cd28ab6a | 1850 | dma_addr_t mapping; |
5dce95e5 SH |
1851 | u32 upper; |
1852 | u16 slot; | |
cd28ab6a SH |
1853 | u16 mss; |
1854 | u8 ctrl; | |
1855 | ||
2bb8c262 SH |
1856 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) |
1857 | return NETDEV_TX_BUSY; | |
cd28ab6a | 1858 | |
cd28ab6a SH |
1859 | len = skb_headlen(skb); |
1860 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
793b883e | 1861 | |
454e6cb6 SH |
1862 | if (pci_dma_mapping_error(hw->pdev, mapping)) |
1863 | goto mapping_error; | |
1864 | ||
9b289c33 | 1865 | slot = sky2->tx_prod; |
6c35abae JP |
1866 | netif_printk(sky2, tx_queued, KERN_DEBUG, dev, |
1867 | "tx queued, slot %u, len %d\n", slot, skb->len); | |
454e6cb6 | 1868 | |
86c6887e | 1869 | /* Send high bits if needed */ |
5dce95e5 SH |
1870 | upper = upper_32_bits(mapping); |
1871 | if (upper != sky2->tx_last_upper) { | |
9b289c33 | 1872 | le = get_tx_le(sky2, &slot); |
5dce95e5 SH |
1873 | le->addr = cpu_to_le32(upper); |
1874 | sky2->tx_last_upper = upper; | |
793b883e | 1875 | le->opcode = OP_ADDR64 | HW_OWNER; |
793b883e | 1876 | } |
cd28ab6a SH |
1877 | |
1878 | /* Check for TCP Segmentation Offload */ | |
7967168c | 1879 | mss = skb_shinfo(skb)->gso_size; |
793b883e | 1880 | if (mss != 0) { |
ea76e635 SH |
1881 | |
1882 | if (!(hw->flags & SKY2_HW_NEW_LE)) | |
69161611 SH |
1883 | mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); |
1884 | ||
1885 | if (mss != sky2->tx_last_mss) { | |
9b289c33 | 1886 | le = get_tx_le(sky2, &slot); |
69161611 | 1887 | le->addr = cpu_to_le32(mss); |
ea76e635 SH |
1888 | |
1889 | if (hw->flags & SKY2_HW_NEW_LE) | |
69161611 SH |
1890 | le->opcode = OP_MSS | HW_OWNER; |
1891 | else | |
1892 | le->opcode = OP_LRGLEN | HW_OWNER; | |
e07560cd SH |
1893 | sky2->tx_last_mss = mss; |
1894 | } | |
cd28ab6a SH |
1895 | } |
1896 | ||
cd28ab6a | 1897 | ctrl = 0; |
86aa7785 | 1898 | |
d1f13708 | 1899 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ |
eab6d18d | 1900 | if (vlan_tx_tag_present(skb)) { |
d1f13708 | 1901 | if (!le) { |
9b289c33 | 1902 | le = get_tx_le(sky2, &slot); |
f65b138c | 1903 | le->addr = 0; |
d1f13708 | 1904 | le->opcode = OP_VLAN|HW_OWNER; |
d1f13708 SH |
1905 | } else |
1906 | le->opcode |= OP_VLAN; | |
1907 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1908 | ctrl |= INS_VLAN; | |
1909 | } | |
d1f13708 SH |
1910 | |
1911 | /* Handle TCP checksum offload */ | |
84fa7933 | 1912 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
69161611 | 1913 | /* On Yukon EX (some versions) encoding change. */ |
ea76e635 | 1914 | if (hw->flags & SKY2_HW_AUTO_TX_SUM) |
69161611 SH |
1915 | ctrl |= CALSUM; /* auto checksum */ |
1916 | else { | |
1917 | const unsigned offset = skb_transport_offset(skb); | |
1918 | u32 tcpsum; | |
1919 | ||
1920 | tcpsum = offset << 16; /* sum start */ | |
1921 | tcpsum |= offset + skb->csum_offset; /* sum write */ | |
1922 | ||
1923 | ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1924 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) | |
1925 | ctrl |= UDPTCP; | |
1926 | ||
1927 | if (tcpsum != sky2->tx_tcpsum) { | |
1928 | sky2->tx_tcpsum = tcpsum; | |
1929 | ||
9b289c33 | 1930 | le = get_tx_le(sky2, &slot); |
69161611 SH |
1931 | le->addr = cpu_to_le32(tcpsum); |
1932 | le->length = 0; /* initial checksum value */ | |
1933 | le->ctrl = 1; /* one packet */ | |
1934 | le->opcode = OP_TCPLISW | HW_OWNER; | |
1935 | } | |
1d179332 | 1936 | } |
cd28ab6a SH |
1937 | } |
1938 | ||
6b84daca SH |
1939 | re = sky2->tx_ring + slot; |
1940 | re->flags = TX_MAP_SINGLE; | |
7cd26ce5 FT |
1941 | dma_unmap_addr_set(re, mapaddr, mapping); |
1942 | dma_unmap_len_set(re, maplen, len); | |
6b84daca | 1943 | |
9b289c33 | 1944 | le = get_tx_le(sky2, &slot); |
d6e74b6b | 1945 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
cd28ab6a SH |
1946 | le->length = cpu_to_le16(len); |
1947 | le->ctrl = ctrl; | |
793b883e | 1948 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1949 | |
cd28ab6a SH |
1950 | |
1951 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
291ea614 | 1952 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
cd28ab6a | 1953 | |
950a5a4f | 1954 | mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, |
9e903e08 | 1955 | skb_frag_size(frag), DMA_TO_DEVICE); |
86c6887e | 1956 | |
5d6bcdfe | 1957 | if (dma_mapping_error(&hw->pdev->dev, mapping)) |
454e6cb6 SH |
1958 | goto mapping_unwind; |
1959 | ||
5dce95e5 SH |
1960 | upper = upper_32_bits(mapping); |
1961 | if (upper != sky2->tx_last_upper) { | |
9b289c33 | 1962 | le = get_tx_le(sky2, &slot); |
5dce95e5 SH |
1963 | le->addr = cpu_to_le32(upper); |
1964 | sky2->tx_last_upper = upper; | |
793b883e | 1965 | le->opcode = OP_ADDR64 | HW_OWNER; |
cd28ab6a SH |
1966 | } |
1967 | ||
6b84daca SH |
1968 | re = sky2->tx_ring + slot; |
1969 | re->flags = TX_MAP_PAGE; | |
7cd26ce5 | 1970 | dma_unmap_addr_set(re, mapaddr, mapping); |
9e903e08 | 1971 | dma_unmap_len_set(re, maplen, skb_frag_size(frag)); |
6b84daca | 1972 | |
9b289c33 | 1973 | le = get_tx_le(sky2, &slot); |
d6e74b6b | 1974 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
9e903e08 | 1975 | le->length = cpu_to_le16(skb_frag_size(frag)); |
cd28ab6a | 1976 | le->ctrl = ctrl; |
793b883e | 1977 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1978 | } |
6cdbbdf3 | 1979 | |
6b84daca | 1980 | re->skb = skb; |
cd28ab6a SH |
1981 | le->ctrl |= EOP; |
1982 | ||
9b289c33 MM |
1983 | sky2->tx_prod = slot; |
1984 | ||
97bda706 SH |
1985 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
1986 | netif_stop_queue(dev); | |
b19666d9 | 1987 | |
ec2a5466 | 1988 | netdev_sent_queue(dev, skb->len); |
290d4de5 | 1989 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1990 | |
cd28ab6a | 1991 | return NETDEV_TX_OK; |
454e6cb6 SH |
1992 | |
1993 | mapping_unwind: | |
ee5f68fe | 1994 | for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { |
454e6cb6 SH |
1995 | re = sky2->tx_ring + i; |
1996 | ||
6b84daca | 1997 | sky2_tx_unmap(hw->pdev, re); |
454e6cb6 SH |
1998 | } |
1999 | ||
454e6cb6 SH |
2000 | mapping_error: |
2001 | if (net_ratelimit()) | |
2002 | dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); | |
2003 | dev_kfree_skb(skb); | |
2004 | return NETDEV_TX_OK; | |
cd28ab6a SH |
2005 | } |
2006 | ||
cd28ab6a | 2007 | /* |
793b883e SH |
2008 | * Free ring elements from starting at tx_cons until "done" |
2009 | * | |
481cea4a SH |
2010 | * NB: |
2011 | * 1. The hardware will tell us about partial completion of multi-part | |
291ea614 | 2012 | * buffers so make sure not to free skb to early. |
481cea4a SH |
2013 | * 2. This may run in parallel start_xmit because the it only |
2014 | * looks at the tail of the queue of FIFO (tx_cons), not | |
2015 | * the head (tx_prod) | |
cd28ab6a | 2016 | */ |
d11c13e7 | 2017 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 2018 | { |
d11c13e7 | 2019 | struct net_device *dev = sky2->netdev; |
ec2a5466 | 2020 | u16 idx; |
2021 | unsigned int bytes_compl = 0, pkts_compl = 0; | |
cd28ab6a | 2022 | |
ee5f68fe | 2023 | BUG_ON(done >= sky2->tx_ring_size); |
2224795d | 2024 | |
291ea614 | 2025 | for (idx = sky2->tx_cons; idx != done; |
ee5f68fe | 2026 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { |
291ea614 | 2027 | struct tx_ring_info *re = sky2->tx_ring + idx; |
6b84daca | 2028 | struct sk_buff *skb = re->skb; |
291ea614 | 2029 | |
6b84daca | 2030 | sky2_tx_unmap(sky2->hw->pdev, re); |
bd1c6869 | 2031 | |
6b84daca | 2032 | if (skb) { |
6c35abae JP |
2033 | netif_printk(sky2, tx_done, KERN_DEBUG, dev, |
2034 | "tx done %u\n", idx); | |
3cf26753 | 2035 | |
ec2a5466 | 2036 | pkts_compl++; |
2037 | bytes_compl += skb->len; | |
bd1c6869 | 2038 | |
f6815077 | 2039 | re->skb = NULL; |
724b6942 | 2040 | dev_kfree_skb_any(skb); |
2bf56fe2 | 2041 | |
ee5f68fe | 2042 | sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); |
cd28ab6a | 2043 | } |
793b883e | 2044 | } |
793b883e | 2045 | |
291ea614 | 2046 | sky2->tx_cons = idx; |
50432cb5 | 2047 | smp_mb(); |
ec2a5466 | 2048 | |
2049 | netdev_completed_queue(dev, pkts_compl, bytes_compl); | |
2050 | ||
2051 | u64_stats_update_begin(&sky2->tx_stats.syncp); | |
2052 | sky2->tx_stats.packets += pkts_compl; | |
2053 | sky2->tx_stats.bytes += bytes_compl; | |
2054 | u64_stats_update_end(&sky2->tx_stats.syncp); | |
cd28ab6a SH |
2055 | } |
2056 | ||
264bb4fa | 2057 | static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) |
a510996b | 2058 | { |
a510996b MM |
2059 | /* Disable Force Sync bit and Enable Alloc bit */ |
2060 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
2061 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
2062 | ||
2063 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
2064 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
2065 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
2066 | ||
2067 | /* Reset the PCI FIFO of the async Tx queue */ | |
2068 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), | |
2069 | BMU_RST_SET | BMU_FIFO_RST); | |
2070 | ||
2071 | /* Reset the Tx prefetch units */ | |
2072 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
2073 | PREF_UNIT_RST_SET); | |
2074 | ||
2075 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2076 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
f9687c44 | 2077 | |
2078 | sky2_read32(hw, B0_CTST); | |
a510996b MM |
2079 | } |
2080 | ||
f2b31cb3 | 2081 | static void sky2_hw_down(struct sky2_port *sky2) |
cd28ab6a | 2082 | { |
cd28ab6a SH |
2083 | struct sky2_hw *hw = sky2->hw; |
2084 | unsigned port = sky2->port; | |
f2b31cb3 | 2085 | u16 ctrl; |
cd28ab6a | 2086 | |
d104acaf SH |
2087 | /* Force flow control off */ |
2088 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e | 2089 | |
cd28ab6a SH |
2090 | /* Stop transmitter */ |
2091 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
2092 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
2093 | ||
2094 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 2095 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
2096 | |
2097 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 2098 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
2099 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
2100 | ||
2101 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
2102 | ||
2103 | /* Workaround shared GMAC reset */ | |
8e95a202 JP |
2104 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && |
2105 | port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
2106 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
2107 | ||
cd28ab6a | 2108 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
cd28ab6a | 2109 | |
fb914ebf | 2110 | /* Force any delayed status interrupt and NAPI */ |
6c83504f SH |
2111 | sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); |
2112 | sky2_write32(hw, STAT_TX_TIMER_CNT, 0); | |
2113 | sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); | |
2114 | sky2_read8(hw, STAT_ISR_TIMER_CTRL); | |
2115 | ||
a947a39d MM |
2116 | sky2_rx_stop(sky2); |
2117 | ||
0da6d7b3 | 2118 | spin_lock_bh(&sky2->phy_lock); |
b96936da | 2119 | sky2_phy_power_down(hw, port); |
0da6d7b3 | 2120 | spin_unlock_bh(&sky2->phy_lock); |
d3bcfbeb | 2121 | |
264bb4fa MM |
2122 | sky2_tx_reset(hw, port); |
2123 | ||
481cea4a SH |
2124 | /* Free any pending frames stuck in HW queue */ |
2125 | sky2_tx_complete(sky2, sky2->tx_prod); | |
f2b31cb3 MM |
2126 | } |
2127 | ||
2128 | /* Network shutdown */ | |
926d0977 | 2129 | static int sky2_close(struct net_device *dev) |
f2b31cb3 MM |
2130 | { |
2131 | struct sky2_port *sky2 = netdev_priv(dev); | |
8a0c9228 | 2132 | struct sky2_hw *hw = sky2->hw; |
f2b31cb3 MM |
2133 | |
2134 | /* Never really got started! */ | |
2135 | if (!sky2->tx_le) | |
2136 | return 0; | |
2137 | ||
6c35abae | 2138 | netif_info(sky2, ifdown, dev, "disabling interface\n"); |
f2b31cb3 | 2139 | |
0bdb0bd0 | 2140 | if (hw->ports == 1) { |
1401a800 | 2141 | sky2_write32(hw, B0_IMSK, 0); |
2142 | sky2_read32(hw, B0_IMSK); | |
2143 | ||
0bdb0bd0 | 2144 | napi_disable(&hw->napi); |
2145 | free_irq(hw->pdev->irq, hw); | |
282edcec | 2146 | hw->flags &= ~SKY2_HW_IRQ_SETUP; |
0bdb0bd0 | 2147 | } else { |
1401a800 | 2148 | u32 imask; |
2149 | ||
2150 | /* Disable port IRQ */ | |
2151 | imask = sky2_read32(hw, B0_IMSK); | |
2152 | imask &= ~portirq_msk[sky2->port]; | |
2153 | sky2_write32(hw, B0_IMSK, imask); | |
2154 | sky2_read32(hw, B0_IMSK); | |
2155 | ||
0bdb0bd0 | 2156 | synchronize_irq(hw->pdev->irq); |
2157 | napi_synchronize(&hw->napi); | |
2158 | } | |
8a0c9228 | 2159 | |
f2b31cb3 | 2160 | sky2_hw_down(sky2); |
481cea4a | 2161 | |
90bbebb4 | 2162 | sky2_free_buffers(sky2); |
1b537565 | 2163 | |
cd28ab6a SH |
2164 | return 0; |
2165 | } | |
2166 | ||
2167 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
2168 | { | |
ea76e635 | 2169 | if (hw->flags & SKY2_HW_FIBRE_PHY) |
793b883e SH |
2170 | return SPEED_1000; |
2171 | ||
05745c4a SH |
2172 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
2173 | if (aux & PHY_M_PS_SPEED_100) | |
2174 | return SPEED_100; | |
2175 | else | |
2176 | return SPEED_10; | |
2177 | } | |
cd28ab6a SH |
2178 | |
2179 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
2180 | case PHY_M_PS_SPEED_1000: | |
2181 | return SPEED_1000; | |
2182 | case PHY_M_PS_SPEED_100: | |
2183 | return SPEED_100; | |
2184 | default: | |
2185 | return SPEED_10; | |
2186 | } | |
2187 | } | |
2188 | ||
2189 | static void sky2_link_up(struct sky2_port *sky2) | |
2190 | { | |
2191 | struct sky2_hw *hw = sky2->hw; | |
2192 | unsigned port = sky2->port; | |
16ad91e1 SH |
2193 | static const char *fc_name[] = { |
2194 | [FC_NONE] = "none", | |
2195 | [FC_TX] = "tx", | |
2196 | [FC_RX] = "rx", | |
2197 | [FC_BOTH] = "both", | |
2198 | }; | |
cd28ab6a | 2199 | |
8e11680f | 2200 | sky2_set_ipg(sky2); |
2201 | ||
38000a94 | 2202 | sky2_enable_rx_tx(sky2); |
cd28ab6a SH |
2203 | |
2204 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
2205 | ||
2206 | netif_carrier_on(sky2->netdev); | |
cd28ab6a | 2207 | |
75e80683 | 2208 | mod_timer(&hw->watchdog_timer, jiffies + 1); |
32c2c300 | 2209 | |
cd28ab6a | 2210 | /* Turn on link LED */ |
793b883e | 2211 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
2212 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
2213 | ||
6c35abae JP |
2214 | netif_info(sky2, link, sky2->netdev, |
2215 | "Link is up at %d Mbps, %s duplex, flow control %s\n", | |
2216 | sky2->speed, | |
2217 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
2218 | fc_name[sky2->flow_status]); | |
cd28ab6a SH |
2219 | } |
2220 | ||
2221 | static void sky2_link_down(struct sky2_port *sky2) | |
2222 | { | |
2223 | struct sky2_hw *hw = sky2->hw; | |
2224 | unsigned port = sky2->port; | |
2225 | u16 reg; | |
2226 | ||
2227 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
2228 | ||
2229 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
2230 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
2231 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
cd28ab6a | 2232 | |
cd28ab6a | 2233 | netif_carrier_off(sky2->netdev); |
cd28ab6a | 2234 | |
809aaaae | 2235 | /* Turn off link LED */ |
cd28ab6a SH |
2236 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
2237 | ||
6c35abae | 2238 | netif_info(sky2, link, sky2->netdev, "Link is down\n"); |
2eaba1a2 | 2239 | |
cd28ab6a SH |
2240 | sky2_phy_init(hw, port); |
2241 | } | |
2242 | ||
16ad91e1 SH |
2243 | static enum flow_control sky2_flow(int rx, int tx) |
2244 | { | |
2245 | if (rx) | |
2246 | return tx ? FC_BOTH : FC_RX; | |
2247 | else | |
2248 | return tx ? FC_TX : FC_NONE; | |
2249 | } | |
2250 | ||
793b883e SH |
2251 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
2252 | { | |
2253 | struct sky2_hw *hw = sky2->hw; | |
2254 | unsigned port = sky2->port; | |
da4c1ff4 | 2255 | u16 advert, lpa; |
793b883e | 2256 | |
da4c1ff4 | 2257 | advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); |
793b883e | 2258 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); |
793b883e | 2259 | if (lpa & PHY_M_AN_RF) { |
ada1db5c | 2260 | netdev_err(sky2->netdev, "remote fault\n"); |
793b883e SH |
2261 | return -1; |
2262 | } | |
2263 | ||
793b883e | 2264 | if (!(aux & PHY_M_PS_SPDUP_RES)) { |
ada1db5c | 2265 | netdev_err(sky2->netdev, "speed/duplex mismatch\n"); |
793b883e SH |
2266 | return -1; |
2267 | } | |
2268 | ||
793b883e | 2269 | sky2->speed = sky2_phy_speed(hw, aux); |
7c74ac1c | 2270 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; |
793b883e | 2271 | |
da4c1ff4 SH |
2272 | /* Since the pause result bits seem to in different positions on |
2273 | * different chips. look at registers. | |
2274 | */ | |
ea76e635 | 2275 | if (hw->flags & SKY2_HW_FIBRE_PHY) { |
da4c1ff4 SH |
2276 | /* Shift for bits in fiber PHY */ |
2277 | advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); | |
2278 | lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); | |
2279 | ||
2280 | if (advert & ADVERTISE_1000XPAUSE) | |
2281 | advert |= ADVERTISE_PAUSE_CAP; | |
2282 | if (advert & ADVERTISE_1000XPSE_ASYM) | |
2283 | advert |= ADVERTISE_PAUSE_ASYM; | |
2284 | if (lpa & LPA_1000XPAUSE) | |
2285 | lpa |= LPA_PAUSE_CAP; | |
2286 | if (lpa & LPA_1000XPAUSE_ASYM) | |
2287 | lpa |= LPA_PAUSE_ASYM; | |
2288 | } | |
793b883e | 2289 | |
da4c1ff4 SH |
2290 | sky2->flow_status = FC_NONE; |
2291 | if (advert & ADVERTISE_PAUSE_CAP) { | |
2292 | if (lpa & LPA_PAUSE_CAP) | |
2293 | sky2->flow_status = FC_BOTH; | |
2294 | else if (advert & ADVERTISE_PAUSE_ASYM) | |
2295 | sky2->flow_status = FC_RX; | |
2296 | } else if (advert & ADVERTISE_PAUSE_ASYM) { | |
2297 | if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) | |
2298 | sky2->flow_status = FC_TX; | |
2299 | } | |
793b883e | 2300 | |
8e95a202 JP |
2301 | if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && |
2302 | !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) | |
16ad91e1 | 2303 | sky2->flow_status = FC_NONE; |
2eaba1a2 | 2304 | |
da4c1ff4 | 2305 | if (sky2->flow_status & FC_TX) |
793b883e SH |
2306 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
2307 | else | |
2308 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
2309 | ||
2310 | return 0; | |
2311 | } | |
cd28ab6a | 2312 | |
e07b1aa8 SH |
2313 | /* Interrupt from PHY */ |
2314 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 2315 | { |
e07b1aa8 SH |
2316 | struct net_device *dev = hw->dev[port]; |
2317 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
2318 | u16 istatus, phystat; |
2319 | ||
ebc646f6 SH |
2320 | if (!netif_running(dev)) |
2321 | return; | |
2322 | ||
e07b1aa8 SH |
2323 | spin_lock(&sky2->phy_lock); |
2324 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
2325 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
2326 | ||
6c35abae JP |
2327 | netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", |
2328 | istatus, phystat); | |
cd28ab6a | 2329 | |
0ea065e5 | 2330 | if (istatus & PHY_M_IS_AN_COMPL) { |
9badba25 | 2331 | if (sky2_autoneg_done(sky2, phystat) == 0 && |
2332 | !netif_carrier_ok(dev)) | |
793b883e SH |
2333 | sky2_link_up(sky2); |
2334 | goto out; | |
2335 | } | |
cd28ab6a | 2336 | |
793b883e SH |
2337 | if (istatus & PHY_M_IS_LSP_CHANGE) |
2338 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 2339 | |
793b883e SH |
2340 | if (istatus & PHY_M_IS_DUP_CHANGE) |
2341 | sky2->duplex = | |
2342 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 2343 | |
793b883e SH |
2344 | if (istatus & PHY_M_IS_LST_CHANGE) { |
2345 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 2346 | sky2_link_up(sky2); |
793b883e SH |
2347 | else |
2348 | sky2_link_down(sky2); | |
cd28ab6a | 2349 | } |
793b883e | 2350 | out: |
e07b1aa8 | 2351 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
2352 | } |
2353 | ||
0f5aac70 SH |
2354 | /* Special quick link interrupt (Yukon-2 Optima only) */ |
2355 | static void sky2_qlink_intr(struct sky2_hw *hw) | |
2356 | { | |
2357 | struct sky2_port *sky2 = netdev_priv(hw->dev[0]); | |
2358 | u32 imask; | |
2359 | u16 phy; | |
2360 | ||
2361 | /* disable irq */ | |
2362 | imask = sky2_read32(hw, B0_IMSK); | |
2363 | imask &= ~Y2_IS_PHY_QLNK; | |
2364 | sky2_write32(hw, B0_IMSK, imask); | |
2365 | ||
2366 | /* reset PHY Link Detect */ | |
2367 | phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); | |
a40ccc68 | 2368 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
0f5aac70 | 2369 | sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); |
a40ccc68 | 2370 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
0f5aac70 SH |
2371 | |
2372 | sky2_link_up(sky2); | |
2373 | } | |
2374 | ||
62335ab0 | 2375 | /* Transmit timeout is only called if we are running, carrier is up |
302d1252 SH |
2376 | * and tx queue is full (stopped). |
2377 | */ | |
cd28ab6a SH |
2378 | static void sky2_tx_timeout(struct net_device *dev) |
2379 | { | |
2380 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 | 2381 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a | 2382 | |
6c35abae | 2383 | netif_err(sky2, timer, dev, "tx timeout\n"); |
cd28ab6a | 2384 | |
ada1db5c JP |
2385 | netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", |
2386 | sky2->tx_cons, sky2->tx_prod, | |
2387 | sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
2388 | sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); | |
8f24664d | 2389 | |
81906791 SH |
2390 | /* can't restart safely under softirq */ |
2391 | schedule_work(&hw->restart_work); | |
cd28ab6a SH |
2392 | } |
2393 | ||
2394 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |
2395 | { | |
6b1a3aef SH |
2396 | struct sky2_port *sky2 = netdev_priv(dev); |
2397 | struct sky2_hw *hw = sky2->hw; | |
b628ed98 | 2398 | unsigned port = sky2->port; |
6b1a3aef SH |
2399 | int err; |
2400 | u16 ctl, mode; | |
e07b1aa8 | 2401 | u32 imask; |
cd28ab6a | 2402 | |
44dde56d | 2403 | /* MTU size outside the spec */ |
cd28ab6a SH |
2404 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
2405 | return -EINVAL; | |
2406 | ||
44dde56d | 2407 | /* MTU > 1500 on yukon FE and FE+ not allowed */ |
05745c4a SH |
2408 | if (new_mtu > ETH_DATA_LEN && |
2409 | (hw->chip_id == CHIP_ID_YUKON_FE || | |
2410 | hw->chip_id == CHIP_ID_YUKON_FE_P)) | |
d2adf4f6 SH |
2411 | return -EINVAL; |
2412 | ||
6b1a3aef SH |
2413 | if (!netif_running(dev)) { |
2414 | dev->mtu = new_mtu; | |
f5d64037 | 2415 | netdev_update_features(dev); |
6b1a3aef SH |
2416 | return 0; |
2417 | } | |
2418 | ||
e07b1aa8 | 2419 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef SH |
2420 | sky2_write32(hw, B0_IMSK, 0); |
2421 | ||
018d1c66 | 2422 | dev->trans_start = jiffies; /* prevent tx timeout */ |
bea3348e | 2423 | napi_disable(&hw->napi); |
df01093b | 2424 | netif_tx_disable(dev); |
018d1c66 | 2425 | |
e07b1aa8 SH |
2426 | synchronize_irq(hw->pdev->irq); |
2427 | ||
39dbd958 | 2428 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) |
69161611 | 2429 | sky2_set_tx_stfwd(hw, port); |
b628ed98 SH |
2430 | |
2431 | ctl = gma_read16(hw, port, GM_GP_CTRL); | |
2432 | gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
6b1a3aef SH |
2433 | sky2_rx_stop(sky2); |
2434 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
2435 | |
2436 | dev->mtu = new_mtu; | |
f5d64037 | 2437 | netdev_update_features(dev); |
14d0263f | 2438 | |
8e11680f | 2439 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; |
2440 | if (sky2->speed > SPEED_100) | |
2441 | mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); | |
2442 | else | |
2443 | mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); | |
6b1a3aef SH |
2444 | |
2445 | if (dev->mtu > ETH_DATA_LEN) | |
2446 | mode |= GM_SMOD_JUMBO_ENA; | |
2447 | ||
b628ed98 | 2448 | gma_write16(hw, port, GM_SERIAL_MODE, mode); |
cd28ab6a | 2449 | |
b628ed98 | 2450 | sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 2451 | |
200ac492 MM |
2452 | err = sky2_alloc_rx_skbs(sky2); |
2453 | if (!err) | |
2454 | sky2_rx_start(sky2); | |
2455 | else | |
2456 | sky2_rx_clean(sky2); | |
e07b1aa8 | 2457 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 2458 | |
d1d08d12 | 2459 | sky2_read32(hw, B0_Y2_SP_LISR); |
bea3348e SH |
2460 | napi_enable(&hw->napi); |
2461 | ||
1b537565 SH |
2462 | if (err) |
2463 | dev_close(dev); | |
2464 | else { | |
b628ed98 | 2465 | gma_write16(hw, port, GM_GP_CTRL, ctl); |
1b537565 | 2466 | |
1b537565 SH |
2467 | netif_wake_queue(dev); |
2468 | } | |
2469 | ||
cd28ab6a SH |
2470 | return err; |
2471 | } | |
2472 | ||
857504d0 | 2473 | static inline bool needs_copy(const struct rx_ring_info *re, |
2474 | unsigned length) | |
2475 | { | |
2476 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
2477 | /* Some architectures need the IP header to be aligned */ | |
2478 | if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32))) | |
2479 | return true; | |
2480 | #endif | |
2481 | return length < copybreak; | |
2482 | } | |
2483 | ||
14d0263f SH |
2484 | /* For small just reuse existing skb for next receive */ |
2485 | static struct sk_buff *receive_copy(struct sky2_port *sky2, | |
2486 | const struct rx_ring_info *re, | |
2487 | unsigned length) | |
2488 | { | |
2489 | struct sk_buff *skb; | |
2490 | ||
89d71a66 | 2491 | skb = netdev_alloc_skb_ip_align(sky2->netdev, length); |
14d0263f | 2492 | if (likely(skb)) { |
14d0263f SH |
2493 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, |
2494 | length, PCI_DMA_FROMDEVICE); | |
d626f62b | 2495 | skb_copy_from_linear_data(re->skb, skb->data, length); |
14d0263f SH |
2496 | skb->ip_summed = re->skb->ip_summed; |
2497 | skb->csum = re->skb->csum; | |
3f42941b | 2498 | skb->rxhash = re->skb->rxhash; |
e072b3fa | 2499 | skb->vlan_tci = re->skb->vlan_tci; |
3f42941b | 2500 | |
14d0263f SH |
2501 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, |
2502 | length, PCI_DMA_FROMDEVICE); | |
e072b3fa | 2503 | re->skb->vlan_tci = 0; |
3f42941b | 2504 | re->skb->rxhash = 0; |
14d0263f | 2505 | re->skb->ip_summed = CHECKSUM_NONE; |
489b10c1 | 2506 | skb_put(skb, length); |
14d0263f SH |
2507 | } |
2508 | return skb; | |
2509 | } | |
2510 | ||
2511 | /* Adjust length of skb with fragments to match received data */ | |
2512 | static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, | |
2513 | unsigned int length) | |
2514 | { | |
2515 | int i, num_frags; | |
2516 | unsigned int size; | |
2517 | ||
2518 | /* put header into skb */ | |
2519 | size = min(length, hdr_space); | |
2520 | skb->tail += size; | |
2521 | skb->len += size; | |
2522 | length -= size; | |
2523 | ||
2524 | num_frags = skb_shinfo(skb)->nr_frags; | |
2525 | for (i = 0; i < num_frags; i++) { | |
2526 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2527 | ||
2528 | if (length == 0) { | |
2529 | /* don't need this page */ | |
950a5a4f | 2530 | __skb_frag_unref(frag); |
14d0263f SH |
2531 | --skb_shinfo(skb)->nr_frags; |
2532 | } else { | |
2533 | size = min(length, (unsigned) PAGE_SIZE); | |
2534 | ||
9e903e08 | 2535 | skb_frag_size_set(frag, size); |
14d0263f | 2536 | skb->data_len += size; |
7ae60b3f | 2537 | skb->truesize += PAGE_SIZE; |
14d0263f SH |
2538 | skb->len += size; |
2539 | length -= size; | |
2540 | } | |
2541 | } | |
2542 | } | |
2543 | ||
2544 | /* Normal packet - take skb from ring element and put in a new one */ | |
2545 | static struct sk_buff *receive_new(struct sky2_port *sky2, | |
2546 | struct rx_ring_info *re, | |
2547 | unsigned int length) | |
2548 | { | |
3fbd9187 | 2549 | struct sk_buff *skb; |
2550 | struct rx_ring_info nre; | |
14d0263f SH |
2551 | unsigned hdr_space = sky2->rx_data_size; |
2552 | ||
68ac3191 | 2553 | nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); |
3fbd9187 | 2554 | if (unlikely(!nre.skb)) |
2555 | goto nobuf; | |
2556 | ||
2557 | if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) | |
2558 | goto nomap; | |
14d0263f SH |
2559 | |
2560 | skb = re->skb; | |
2561 | sky2_rx_unmap_skb(sky2->hw->pdev, re); | |
14d0263f | 2562 | prefetch(skb->data); |
3fbd9187 | 2563 | *re = nre; |
14d0263f SH |
2564 | |
2565 | if (skb_shinfo(skb)->nr_frags) | |
2566 | skb_put_frags(skb, hdr_space, length); | |
2567 | else | |
489b10c1 | 2568 | skb_put(skb, length); |
14d0263f | 2569 | return skb; |
3fbd9187 | 2570 | |
2571 | nomap: | |
2572 | dev_kfree_skb(nre.skb); | |
2573 | nobuf: | |
2574 | return NULL; | |
14d0263f SH |
2575 | } |
2576 | ||
cd28ab6a SH |
2577 | /* |
2578 | * Receive one packet. | |
d571b694 | 2579 | * For larger packets, get new buffer. |
cd28ab6a | 2580 | */ |
497d7c86 | 2581 | static struct sk_buff *sky2_receive(struct net_device *dev, |
cd28ab6a SH |
2582 | u16 length, u32 status) |
2583 | { | |
497d7c86 | 2584 | struct sky2_port *sky2 = netdev_priv(dev); |
291ea614 | 2585 | struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 2586 | struct sk_buff *skb = NULL; |
d6532232 SH |
2587 | u16 count = (status & GMR_FS_LEN) >> 16; |
2588 | ||
6c35abae JP |
2589 | netif_printk(sky2, rx_status, KERN_DEBUG, dev, |
2590 | "rx slot %u status 0x%x len %d\n", | |
2591 | sky2->rx_next, status, length); | |
cd28ab6a | 2592 | |
793b883e | 2593 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 2594 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 2595 | |
e072b3fa | 2596 | if (vlan_tx_tag_present(re->skb)) |
2597 | count -= VLAN_HLEN; /* Account for vlan tag */ | |
2598 | ||
3b12e014 SH |
2599 | /* This chip has hardware problems that generates bogus status. |
2600 | * So do only marginal checking and expect higher level protocols | |
2601 | * to handle crap frames. | |
2602 | */ | |
2603 | if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && | |
2604 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && | |
2605 | length != count) | |
2606 | goto okay; | |
2607 | ||
42eeea01 | 2608 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
2609 | goto error; |
2610 | ||
42eeea01 SH |
2611 | if (!(status & GMR_FS_RX_OK)) |
2612 | goto resubmit; | |
2613 | ||
d6532232 SH |
2614 | /* if length reported by DMA does not match PHY, packet was truncated */ |
2615 | if (length != count) | |
0885a30b | 2616 | goto error; |
71749531 | 2617 | |
3b12e014 | 2618 | okay: |
857504d0 | 2619 | if (needs_copy(re, length)) |
14d0263f SH |
2620 | skb = receive_copy(sky2, re, length); |
2621 | else | |
2622 | skb = receive_new(sky2, re, length); | |
90c30335 SH |
2623 | |
2624 | dev->stats.rx_dropped += (skb == NULL); | |
2625 | ||
793b883e | 2626 | resubmit: |
14d0263f | 2627 | sky2_rx_submit(sky2, re); |
79e57d32 | 2628 | |
cd28ab6a SH |
2629 | return skb; |
2630 | ||
2631 | error: | |
7138a0f5 | 2632 | ++dev->stats.rx_errors; |
6e15b712 | 2633 | |
6c35abae JP |
2634 | if (net_ratelimit()) |
2635 | netif_info(sky2, rx_err, dev, | |
2636 | "rx error, status 0x%x length %d\n", status, length); | |
793b883e | 2637 | |
793b883e | 2638 | goto resubmit; |
cd28ab6a SH |
2639 | } |
2640 | ||
e07b1aa8 SH |
2641 | /* Transmit complete */ |
2642 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 2643 | { |
e07b1aa8 | 2644 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 2645 | |
8a0c9228 | 2646 | if (netif_running(dev)) { |
e07b1aa8 | 2647 | sky2_tx_complete(sky2, last); |
8a0c9228 | 2648 | |
926d0977 | 2649 | /* Wake unless it's detached, and called e.g. from sky2_close() */ |
8a0c9228 MM |
2650 | if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) |
2651 | netif_wake_queue(dev); | |
2652 | } | |
cd28ab6a SH |
2653 | } |
2654 | ||
37e5a243 | 2655 | static inline void sky2_skb_rx(const struct sky2_port *sky2, |
e072b3fa | 2656 | struct sk_buff *skb) |
37e5a243 | 2657 | { |
37e5a243 SH |
2658 | if (skb->ip_summed == CHECKSUM_NONE) |
2659 | netif_receive_skb(skb); | |
2660 | else | |
2661 | napi_gro_receive(&sky2->hw->napi, skb); | |
2662 | } | |
2663 | ||
bf15fe99 SH |
2664 | static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, |
2665 | unsigned packets, unsigned bytes) | |
2666 | { | |
0885a30b | 2667 | struct net_device *dev = hw->dev[port]; |
2668 | struct sky2_port *sky2 = netdev_priv(dev); | |
bf15fe99 | 2669 | |
0885a30b | 2670 | if (packets == 0) |
2671 | return; | |
2672 | ||
2673 | u64_stats_update_begin(&sky2->rx_stats.syncp); | |
2674 | sky2->rx_stats.packets += packets; | |
2675 | sky2->rx_stats.bytes += bytes; | |
2676 | u64_stats_update_end(&sky2->rx_stats.syncp); | |
2677 | ||
2678 | dev->last_rx = jiffies; | |
2679 | sky2_rx_update(netdev_priv(dev), rxqaddr[port]); | |
bf15fe99 SH |
2680 | } |
2681 | ||
375c5688 | 2682 | static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) |
2683 | { | |
2684 | /* If this happens then driver assuming wrong format for chip type */ | |
2685 | BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); | |
2686 | ||
2687 | /* Both checksum counters are programmed to start at | |
2688 | * the same offset, so unless there is a problem they | |
2689 | * should match. This failure is an early indication that | |
2690 | * hardware receive checksumming won't work. | |
2691 | */ | |
2692 | if (likely((u16)(status >> 16) == (u16)status)) { | |
2693 | struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; | |
2694 | skb->ip_summed = CHECKSUM_COMPLETE; | |
2695 | skb->csum = le16_to_cpu(status); | |
2696 | } else { | |
2697 | dev_notice(&sky2->hw->pdev->dev, | |
2698 | "%s: receive checksum problem (status = %#x)\n", | |
2699 | sky2->netdev->name, status); | |
2700 | ||
f5d64037 MM |
2701 | /* Disable checksum offload |
2702 | * It will be reenabled on next ndo_set_features, but if it's | |
2703 | * really broken, will get disabled again | |
2704 | */ | |
2705 | sky2->netdev->features &= ~NETIF_F_RXCSUM; | |
375c5688 | 2706 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2707 | BMU_DIS_RX_CHKSUM); | |
2708 | } | |
2709 | } | |
2710 | ||
e072b3fa | 2711 | static void sky2_rx_tag(struct sky2_port *sky2, u16 length) |
2712 | { | |
2713 | struct sk_buff *skb; | |
2714 | ||
2715 | skb = sky2->rx_ring[sky2->rx_next].skb; | |
2716 | __vlan_hwaccel_put_tag(skb, be16_to_cpu(length)); | |
2717 | } | |
2718 | ||
bf73130d SH |
2719 | static void sky2_rx_hash(struct sky2_port *sky2, u32 status) |
2720 | { | |
2721 | struct sk_buff *skb; | |
2722 | ||
2723 | skb = sky2->rx_ring[sky2->rx_next].skb; | |
2724 | skb->rxhash = le32_to_cpu(status); | |
2725 | } | |
2726 | ||
e07b1aa8 | 2727 | /* Process status response ring */ |
26691830 | 2728 | static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) |
cd28ab6a | 2729 | { |
e07b1aa8 | 2730 | int work_done = 0; |
bf15fe99 SH |
2731 | unsigned int total_bytes[2] = { 0 }; |
2732 | unsigned int total_packets[2] = { 0 }; | |
a8fd6266 | 2733 | |
af2a58ac | 2734 | rmb(); |
26691830 | 2735 | do { |
55c9dd35 | 2736 | struct sky2_port *sky2; |
13210ce5 | 2737 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
ab5adecb | 2738 | unsigned port; |
13210ce5 | 2739 | struct net_device *dev; |
cd28ab6a | 2740 | struct sk_buff *skb; |
cd28ab6a SH |
2741 | u32 status; |
2742 | u16 length; | |
ab5adecb SH |
2743 | u8 opcode = le->opcode; |
2744 | ||
2745 | if (!(opcode & HW_OWNER)) | |
2746 | break; | |
cd28ab6a | 2747 | |
efe91932 | 2748 | hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); |
bea86103 | 2749 | |
ab5adecb | 2750 | port = le->css & CSS_LINK_BIT; |
69161611 | 2751 | dev = hw->dev[port]; |
13210ce5 | 2752 | sky2 = netdev_priv(dev); |
f65b138c SH |
2753 | length = le16_to_cpu(le->length); |
2754 | status = le32_to_cpu(le->status); | |
cd28ab6a | 2755 | |
ab5adecb SH |
2756 | le->opcode = 0; |
2757 | switch (opcode & ~HW_OWNER) { | |
cd28ab6a | 2758 | case OP_RXSTAT: |
bf15fe99 SH |
2759 | total_packets[port]++; |
2760 | total_bytes[port] += length; | |
90c30335 | 2761 | |
497d7c86 | 2762 | skb = sky2_receive(dev, length, status); |
90c30335 | 2763 | if (!skb) |
55c9dd35 | 2764 | break; |
13210ce5 | 2765 | |
69161611 | 2766 | /* This chip reports checksum status differently */ |
05745c4a | 2767 | if (hw->flags & SKY2_HW_NEW_LE) { |
f5d64037 | 2768 | if ((dev->features & NETIF_F_RXCSUM) && |
69161611 SH |
2769 | (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && |
2770 | (le->css & CSS_TCPUDPCSOK)) | |
2771 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2772 | else | |
2773 | skb->ip_summed = CHECKSUM_NONE; | |
2774 | } | |
2775 | ||
13210ce5 | 2776 | skb->protocol = eth_type_trans(skb, dev); |
e072b3fa | 2777 | sky2_skb_rx(sky2, skb); |
13210ce5 | 2778 | |
22e11703 | 2779 | /* Stop after net poll weight */ |
13210ce5 SH |
2780 | if (++work_done >= to_do) |
2781 | goto exit_loop; | |
cd28ab6a SH |
2782 | break; |
2783 | ||
d1f13708 | 2784 | case OP_RXVLAN: |
e072b3fa | 2785 | sky2_rx_tag(sky2, length); |
d1f13708 SH |
2786 | break; |
2787 | ||
2788 | case OP_RXCHKSVLAN: | |
e072b3fa | 2789 | sky2_rx_tag(sky2, length); |
d1f13708 | 2790 | /* fall through */ |
cd28ab6a | 2791 | case OP_RXCHKS: |
f5d64037 | 2792 | if (likely(dev->features & NETIF_F_RXCSUM)) |
375c5688 | 2793 | sky2_rx_checksum(sky2, status); |
cd28ab6a SH |
2794 | break; |
2795 | ||
bf73130d SH |
2796 | case OP_RSS_HASH: |
2797 | sky2_rx_hash(sky2, status); | |
2798 | break; | |
2799 | ||
cd28ab6a | 2800 | case OP_TXINDEXLE: |
13b97b74 | 2801 | /* TX index reports status for both ports */ |
f55925d7 | 2802 | sky2_tx_done(hw->dev[0], status & 0xfff); |
e07b1aa8 SH |
2803 | if (hw->dev[1]) |
2804 | sky2_tx_done(hw->dev[1], | |
2805 | ((status >> 24) & 0xff) | |
2806 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
2807 | break; |
2808 | ||
cd28ab6a SH |
2809 | default: |
2810 | if (net_ratelimit()) | |
ada1db5c | 2811 | pr_warning("unknown status opcode 0x%x\n", opcode); |
cd28ab6a | 2812 | } |
26691830 | 2813 | } while (hw->st_idx != idx); |
cd28ab6a | 2814 | |
fe2a24df SH |
2815 | /* Fully processed status ring so clear irq */ |
2816 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
2817 | ||
13210ce5 | 2818 | exit_loop: |
bf15fe99 SH |
2819 | sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); |
2820 | sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); | |
22e11703 | 2821 | |
e07b1aa8 | 2822 | return work_done; |
cd28ab6a SH |
2823 | } |
2824 | ||
2825 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
2826 | { | |
2827 | struct net_device *dev = hw->dev[port]; | |
2828 | ||
3be92a70 | 2829 | if (net_ratelimit()) |
ada1db5c | 2830 | netdev_info(dev, "hw error interrupt status 0x%x\n", status); |
cd28ab6a SH |
2831 | |
2832 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 | 2833 | if (net_ratelimit()) |
ada1db5c | 2834 | netdev_err(dev, "ram data read parity error\n"); |
cd28ab6a SH |
2835 | /* Clear IRQ */ |
2836 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2837 | } | |
2838 | ||
2839 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 | 2840 | if (net_ratelimit()) |
ada1db5c | 2841 | netdev_err(dev, "ram data write parity error\n"); |
cd28ab6a SH |
2842 | |
2843 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2844 | } | |
2845 | ||
2846 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 | 2847 | if (net_ratelimit()) |
ada1db5c | 2848 | netdev_err(dev, "MAC parity error\n"); |
cd28ab6a SH |
2849 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2850 | } | |
2851 | ||
2852 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 | 2853 | if (net_ratelimit()) |
ada1db5c | 2854 | netdev_err(dev, "RX parity error\n"); |
cd28ab6a SH |
2855 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2856 | } | |
2857 | ||
2858 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 | 2859 | if (net_ratelimit()) |
ada1db5c | 2860 | netdev_err(dev, "TCP segmentation error\n"); |
cd28ab6a SH |
2861 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2862 | } | |
2863 | } | |
2864 | ||
2865 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2866 | { | |
555382cb | 2867 | struct pci_dev *pdev = hw->pdev; |
cd28ab6a | 2868 | u32 status = sky2_read32(hw, B0_HWE_ISRC); |
555382cb SH |
2869 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); |
2870 | ||
2871 | status &= hwmsk; | |
cd28ab6a | 2872 | |
793b883e | 2873 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2874 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2875 | |
2876 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2877 | u16 pci_err; |
2878 | ||
a40ccc68 | 2879 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b32f40c4 | 2880 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
3be92a70 | 2881 | if (net_ratelimit()) |
555382cb | 2882 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
b02a9258 | 2883 | pci_err); |
cd28ab6a | 2884 | |
b32f40c4 | 2885 | sky2_pci_write16(hw, PCI_STATUS, |
167f53d0 | 2886 | pci_err | PCI_STATUS_ERROR_BITS); |
a40ccc68 | 2887 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
2888 | } |
2889 | ||
2890 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2891 | /* PCI-Express uncorrectable Error occurred */ |
555382cb | 2892 | u32 err; |
cd28ab6a | 2893 | |
a40ccc68 | 2894 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
7782c8c4 SH |
2895 | err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
2896 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, | |
2897 | 0xfffffffful); | |
3be92a70 | 2898 | if (net_ratelimit()) |
555382cb | 2899 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); |
cf06ffb4 | 2900 | |
7782c8c4 | 2901 | sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
a40ccc68 | 2902 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
2903 | } |
2904 | ||
2905 | if (status & Y2_HWE_L1_MASK) | |
2906 | sky2_hw_error(hw, 0, status); | |
2907 | status >>= 8; | |
2908 | if (status & Y2_HWE_L1_MASK) | |
2909 | sky2_hw_error(hw, 1, status); | |
2910 | } | |
2911 | ||
2912 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2913 | { | |
2914 | struct net_device *dev = hw->dev[port]; | |
2915 | struct sky2_port *sky2 = netdev_priv(dev); | |
2916 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2917 | ||
6c35abae | 2918 | netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); |
cd28ab6a | 2919 | |
a3caeada SH |
2920 | if (status & GM_IS_RX_CO_OV) |
2921 | gma_read16(hw, port, GM_RX_IRQ_SRC); | |
2922 | ||
2923 | if (status & GM_IS_TX_CO_OV) | |
2924 | gma_read16(hw, port, GM_TX_IRQ_SRC); | |
2925 | ||
cd28ab6a | 2926 | if (status & GM_IS_RX_FF_OR) { |
7138a0f5 | 2927 | ++dev->stats.rx_fifo_errors; |
cd28ab6a SH |
2928 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
2929 | } | |
2930 | ||
2931 | if (status & GM_IS_TX_FF_UR) { | |
7138a0f5 | 2932 | ++dev->stats.tx_fifo_errors; |
cd28ab6a SH |
2933 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
2934 | } | |
cd28ab6a SH |
2935 | } |
2936 | ||
40b01727 | 2937 | /* This should never happen it is a bug. */ |
c119731d | 2938 | static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) |
d257924e SH |
2939 | { |
2940 | struct net_device *dev = hw->dev[port]; | |
c119731d | 2941 | u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); |
d257924e | 2942 | |
ada1db5c | 2943 | dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", |
c119731d SH |
2944 | dev->name, (unsigned) q, (unsigned) idx, |
2945 | (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); | |
d257924e | 2946 | |
40b01727 | 2947 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); |
d257924e | 2948 | } |
cd28ab6a | 2949 | |
75e80683 SH |
2950 | static int sky2_rx_hung(struct net_device *dev) |
2951 | { | |
2952 | struct sky2_port *sky2 = netdev_priv(dev); | |
2953 | struct sky2_hw *hw = sky2->hw; | |
2954 | unsigned port = sky2->port; | |
2955 | unsigned rxq = rxqaddr[port]; | |
2956 | u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); | |
2957 | u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); | |
2958 | u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); | |
2959 | u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); | |
2960 | ||
2961 | /* If idle and MAC or PCI is stuck */ | |
2962 | if (sky2->check.last == dev->last_rx && | |
2963 | ((mac_rp == sky2->check.mac_rp && | |
2964 | mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || | |
2965 | /* Check if the PCI RX hang */ | |
2966 | (fifo_rp == sky2->check.fifo_rp && | |
2967 | fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { | |
ada1db5c JP |
2968 | netdev_printk(KERN_DEBUG, dev, |
2969 | "hung mac %d:%d fifo %d (%d:%d)\n", | |
2970 | mac_lev, mac_rp, fifo_lev, | |
2971 | fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); | |
75e80683 SH |
2972 | return 1; |
2973 | } else { | |
2974 | sky2->check.last = dev->last_rx; | |
2975 | sky2->check.mac_rp = mac_rp; | |
2976 | sky2->check.mac_lev = mac_lev; | |
2977 | sky2->check.fifo_rp = fifo_rp; | |
2978 | sky2->check.fifo_lev = fifo_lev; | |
2979 | return 0; | |
2980 | } | |
2981 | } | |
2982 | ||
32c2c300 | 2983 | static void sky2_watchdog(unsigned long arg) |
d27ed387 | 2984 | { |
01bd7564 | 2985 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
d27ed387 | 2986 | |
75e80683 | 2987 | /* Check for lost IRQ once a second */ |
32c2c300 | 2988 | if (sky2_read32(hw, B0_ISRC)) { |
bea3348e | 2989 | napi_schedule(&hw->napi); |
75e80683 SH |
2990 | } else { |
2991 | int i, active = 0; | |
2992 | ||
2993 | for (i = 0; i < hw->ports; i++) { | |
bea3348e | 2994 | struct net_device *dev = hw->dev[i]; |
75e80683 SH |
2995 | if (!netif_running(dev)) |
2996 | continue; | |
2997 | ++active; | |
2998 | ||
2999 | /* For chips with Rx FIFO, check if stuck */ | |
39dbd958 | 3000 | if ((hw->flags & SKY2_HW_RAM_BUFFER) && |
75e80683 | 3001 | sky2_rx_hung(dev)) { |
ada1db5c | 3002 | netdev_info(dev, "receiver hang detected\n"); |
75e80683 SH |
3003 | schedule_work(&hw->restart_work); |
3004 | return; | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | if (active == 0) | |
3009 | return; | |
32c2c300 | 3010 | } |
01bd7564 | 3011 | |
75e80683 | 3012 | mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); |
d27ed387 SH |
3013 | } |
3014 | ||
40b01727 SH |
3015 | /* Hardware/software error handling */ |
3016 | static void sky2_err_intr(struct sky2_hw *hw, u32 status) | |
cd28ab6a | 3017 | { |
40b01727 SH |
3018 | if (net_ratelimit()) |
3019 | dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); | |
cd28ab6a | 3020 | |
1e5f1283 SH |
3021 | if (status & Y2_IS_HW_ERR) |
3022 | sky2_hw_intr(hw); | |
d257924e | 3023 | |
1e5f1283 SH |
3024 | if (status & Y2_IS_IRQ_MAC1) |
3025 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 3026 | |
1e5f1283 SH |
3027 | if (status & Y2_IS_IRQ_MAC2) |
3028 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 3029 | |
1e5f1283 | 3030 | if (status & Y2_IS_CHK_RX1) |
c119731d | 3031 | sky2_le_error(hw, 0, Q_R1); |
d257924e | 3032 | |
1e5f1283 | 3033 | if (status & Y2_IS_CHK_RX2) |
c119731d | 3034 | sky2_le_error(hw, 1, Q_R2); |
d257924e | 3035 | |
1e5f1283 | 3036 | if (status & Y2_IS_CHK_TXA1) |
c119731d | 3037 | sky2_le_error(hw, 0, Q_XA1); |
d257924e | 3038 | |
1e5f1283 | 3039 | if (status & Y2_IS_CHK_TXA2) |
c119731d | 3040 | sky2_le_error(hw, 1, Q_XA2); |
40b01727 SH |
3041 | } |
3042 | ||
bea3348e | 3043 | static int sky2_poll(struct napi_struct *napi, int work_limit) |
40b01727 | 3044 | { |
bea3348e | 3045 | struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); |
40b01727 | 3046 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
6f535763 | 3047 | int work_done = 0; |
26691830 | 3048 | u16 idx; |
40b01727 SH |
3049 | |
3050 | if (unlikely(status & Y2_IS_ERROR)) | |
3051 | sky2_err_intr(hw, status); | |
3052 | ||
3053 | if (status & Y2_IS_IRQ_PHY1) | |
3054 | sky2_phy_intr(hw, 0); | |
3055 | ||
3056 | if (status & Y2_IS_IRQ_PHY2) | |
3057 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 3058 | |
0f5aac70 SH |
3059 | if (status & Y2_IS_PHY_QLNK) |
3060 | sky2_qlink_intr(hw); | |
3061 | ||
26691830 SH |
3062 | while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { |
3063 | work_done += sky2_status_intr(hw, work_limit - work_done, idx); | |
6f535763 DM |
3064 | |
3065 | if (work_done >= work_limit) | |
26691830 SH |
3066 | goto done; |
3067 | } | |
6f535763 | 3068 | |
26691830 SH |
3069 | napi_complete(napi); |
3070 | sky2_read32(hw, B0_Y2_SP_LISR); | |
3071 | done: | |
6f535763 | 3072 | |
bea3348e | 3073 | return work_done; |
e07b1aa8 SH |
3074 | } |
3075 | ||
7d12e780 | 3076 | static irqreturn_t sky2_intr(int irq, void *dev_id) |
e07b1aa8 SH |
3077 | { |
3078 | struct sky2_hw *hw = dev_id; | |
e07b1aa8 SH |
3079 | u32 status; |
3080 | ||
3081 | /* Reading this mask interrupts as side effect */ | |
3082 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
d663d181 ML |
3083 | if (status == 0 || status == ~0) { |
3084 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
e07b1aa8 | 3085 | return IRQ_NONE; |
d663d181 | 3086 | } |
793b883e | 3087 | |
e07b1aa8 | 3088 | prefetch(&hw->st_le[hw->st_idx]); |
bea3348e SH |
3089 | |
3090 | napi_schedule(&hw->napi); | |
793b883e | 3091 | |
cd28ab6a SH |
3092 | return IRQ_HANDLED; |
3093 | } | |
3094 | ||
3095 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3096 | static void sky2_netpoll(struct net_device *dev) | |
3097 | { | |
3098 | struct sky2_port *sky2 = netdev_priv(dev); | |
3099 | ||
bea3348e | 3100 | napi_schedule(&sky2->hw->napi); |
cd28ab6a SH |
3101 | } |
3102 | #endif | |
3103 | ||
3104 | /* Chip internal frequency for clock calculations */ | |
05745c4a | 3105 | static u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 3106 | { |
793b883e | 3107 | switch (hw->chip_id) { |
cd28ab6a | 3108 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 3109 | case CHIP_ID_YUKON_EC_U: |
93745494 | 3110 | case CHIP_ID_YUKON_EX: |
ed4d4161 | 3111 | case CHIP_ID_YUKON_SUPR: |
0ce8b98d | 3112 | case CHIP_ID_YUKON_UL_2: |
0f5aac70 | 3113 | case CHIP_ID_YUKON_OPT: |
4fb99cd6 | 3114 | case CHIP_ID_YUKON_PRM: |
3115 | case CHIP_ID_YUKON_OP_2: | |
05745c4a SH |
3116 | return 125; |
3117 | ||
cd28ab6a | 3118 | case CHIP_ID_YUKON_FE: |
05745c4a SH |
3119 | return 100; |
3120 | ||
3121 | case CHIP_ID_YUKON_FE_P: | |
3122 | return 50; | |
3123 | ||
3124 | case CHIP_ID_YUKON_XL: | |
3125 | return 156; | |
3126 | ||
3127 | default: | |
3128 | BUG(); | |
cd28ab6a SH |
3129 | } |
3130 | } | |
3131 | ||
fb17358f | 3132 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 3133 | { |
fb17358f | 3134 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
3135 | } |
3136 | ||
fb17358f | 3137 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 3138 | { |
fb17358f | 3139 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
3140 | } |
3141 | ||
fb17358f | 3142 | |
853e3f4c | 3143 | static int sky2_init(struct sky2_hw *hw) |
cd28ab6a | 3144 | { |
b89165f2 | 3145 | u8 t8; |
cd28ab6a | 3146 | |
167f53d0 | 3147 | /* Enable all clocks and check for bad PCI access */ |
b32f40c4 | 3148 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
451af335 | 3149 | |
cd28ab6a | 3150 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 3151 | |
cd28ab6a | 3152 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
ea76e635 SH |
3153 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
3154 | ||
060b946c | 3155 | switch (hw->chip_id) { |
ea76e635 | 3156 | case CHIP_ID_YUKON_XL: |
39dbd958 | 3157 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; |
bf73130d SH |
3158 | if (hw->chip_rev < CHIP_REV_YU_XL_A2) |
3159 | hw->flags |= SKY2_HW_RSS_BROKEN; | |
ea76e635 SH |
3160 | break; |
3161 | ||
3162 | case CHIP_ID_YUKON_EC_U: | |
3163 | hw->flags = SKY2_HW_GIGABIT | |
3164 | | SKY2_HW_NEWER_PHY | |
3165 | | SKY2_HW_ADV_POWER_CTL; | |
3166 | break; | |
3167 | ||
3168 | case CHIP_ID_YUKON_EX: | |
3169 | hw->flags = SKY2_HW_GIGABIT | |
3170 | | SKY2_HW_NEWER_PHY | |
3171 | | SKY2_HW_NEW_LE | |
aa5ca96c | 3172 | | SKY2_HW_ADV_POWER_CTL |
3173 | | SKY2_HW_RSS_CHKSUM; | |
ea76e635 SH |
3174 | |
3175 | /* New transmit checksum */ | |
3176 | if (hw->chip_rev != CHIP_REV_YU_EX_B0) | |
3177 | hw->flags |= SKY2_HW_AUTO_TX_SUM; | |
3178 | break; | |
3179 | ||
3180 | case CHIP_ID_YUKON_EC: | |
3181 | /* This rev is really old, and requires untested workarounds */ | |
3182 | if (hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
3183 | dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); | |
3184 | return -EOPNOTSUPP; | |
3185 | } | |
bf73130d | 3186 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; |
ea76e635 SH |
3187 | break; |
3188 | ||
3189 | case CHIP_ID_YUKON_FE: | |
bf73130d | 3190 | hw->flags = SKY2_HW_RSS_BROKEN; |
ea76e635 SH |
3191 | break; |
3192 | ||
05745c4a SH |
3193 | case CHIP_ID_YUKON_FE_P: |
3194 | hw->flags = SKY2_HW_NEWER_PHY | |
3195 | | SKY2_HW_NEW_LE | |
3196 | | SKY2_HW_AUTO_TX_SUM | |
3197 | | SKY2_HW_ADV_POWER_CTL; | |
86aa7785 SH |
3198 | |
3199 | /* The workaround for status conflicts VLAN tag detection. */ | |
3200 | if (hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
aa5ca96c | 3201 | hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; |
05745c4a | 3202 | break; |
ed4d4161 SH |
3203 | |
3204 | case CHIP_ID_YUKON_SUPR: | |
3205 | hw->flags = SKY2_HW_GIGABIT | |
3206 | | SKY2_HW_NEWER_PHY | |
3207 | | SKY2_HW_NEW_LE | |
3208 | | SKY2_HW_AUTO_TX_SUM | |
3209 | | SKY2_HW_ADV_POWER_CTL; | |
aa5ca96c | 3210 | |
3211 | if (hw->chip_rev == CHIP_REV_YU_SU_A0) | |
3212 | hw->flags |= SKY2_HW_RSS_CHKSUM; | |
ed4d4161 SH |
3213 | break; |
3214 | ||
0ce8b98d | 3215 | case CHIP_ID_YUKON_UL_2: |
b338682d TI |
3216 | hw->flags = SKY2_HW_GIGABIT |
3217 | | SKY2_HW_ADV_POWER_CTL; | |
3218 | break; | |
3219 | ||
0f5aac70 | 3220 | case CHIP_ID_YUKON_OPT: |
4fb99cd6 | 3221 | case CHIP_ID_YUKON_PRM: |
3222 | case CHIP_ID_YUKON_OP_2: | |
0ce8b98d | 3223 | hw->flags = SKY2_HW_GIGABIT |
b338682d | 3224 | | SKY2_HW_NEW_LE |
0ce8b98d SH |
3225 | | SKY2_HW_ADV_POWER_CTL; |
3226 | break; | |
3227 | ||
ea76e635 | 3228 | default: |
b02a9258 SH |
3229 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
3230 | hw->chip_id); | |
cd28ab6a SH |
3231 | return -EOPNOTSUPP; |
3232 | } | |
3233 | ||
ea76e635 SH |
3234 | hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); |
3235 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') | |
3236 | hw->flags |= SKY2_HW_FIBRE_PHY; | |
290d4de5 | 3237 | |
e3173832 SH |
3238 | hw->ports = 1; |
3239 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
3240 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
3241 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
3242 | ++hw->ports; | |
3243 | } | |
3244 | ||
74a61ebf MM |
3245 | if (sky2_read8(hw, B2_E_0)) |
3246 | hw->flags |= SKY2_HW_RAM_BUFFER; | |
3247 | ||
e3173832 SH |
3248 | return 0; |
3249 | } | |
3250 | ||
3251 | static void sky2_reset(struct sky2_hw *hw) | |
3252 | { | |
555382cb | 3253 | struct pci_dev *pdev = hw->pdev; |
e3173832 | 3254 | u16 status; |
1a10ccae | 3255 | int i; |
555382cb | 3256 | u32 hwe_mask = Y2_HWE_ALL_MASK; |
e3173832 | 3257 | |
cd28ab6a | 3258 | /* disable ASF */ |
acd12dde | 3259 | if (hw->chip_id == CHIP_ID_YUKON_EX |
3260 | || hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
3261 | sky2_write32(hw, CPU_WDOG, 0); | |
4f44d8ba SH |
3262 | status = sky2_read16(hw, HCU_CCSR); |
3263 | status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | | |
3264 | HCU_CCSR_UC_STATE_MSK); | |
acd12dde | 3265 | /* |
3266 | * CPU clock divider shouldn't be used because | |
3267 | * - ASF firmware may malfunction | |
3268 | * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks | |
3269 | */ | |
3270 | status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; | |
4f44d8ba | 3271 | sky2_write16(hw, HCU_CCSR, status); |
acd12dde | 3272 | sky2_write32(hw, CPU_WDOG, 0); |
4f44d8ba SH |
3273 | } else |
3274 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
3275 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
cd28ab6a SH |
3276 | |
3277 | /* do a SW reset */ | |
3278 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
3279 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
3280 | ||
ac93a394 SH |
3281 | /* allow writes to PCI config */ |
3282 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3283 | ||
cd28ab6a | 3284 | /* clear PCI errors, if any */ |
b32f40c4 | 3285 | status = sky2_pci_read16(hw, PCI_STATUS); |
167f53d0 | 3286 | status |= PCI_STATUS_ERROR_BITS; |
b32f40c4 | 3287 | sky2_pci_write16(hw, PCI_STATUS, status); |
cd28ab6a SH |
3288 | |
3289 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
3290 | ||
1a10ccae | 3291 | if (pci_is_pcie(pdev)) { |
7782c8c4 SH |
3292 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
3293 | 0xfffffffful); | |
555382cb SH |
3294 | |
3295 | /* If error bit is stuck on ignore it */ | |
3296 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) | |
3297 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); | |
7782c8c4 | 3298 | else |
555382cb SH |
3299 | hwe_mask |= Y2_IS_PCI_EXP; |
3300 | } | |
cd28ab6a | 3301 | |
ae306cca | 3302 | sky2_power_on(hw); |
a40ccc68 | 3303 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
3304 | |
3305 | for (i = 0; i < hw->ports; i++) { | |
3306 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
3307 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
69161611 | 3308 | |
ed4d4161 SH |
3309 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
3310 | hw->chip_id == CHIP_ID_YUKON_SUPR) | |
69161611 SH |
3311 | sky2_write16(hw, SK_REG(i, GMAC_CTRL), |
3312 | GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | |
3313 | | GMC_BYP_RETR_ON); | |
877c8570 SH |
3314 | |
3315 | } | |
3316 | ||
3317 | if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { | |
3318 | /* enable MACSec clock gating */ | |
3319 | sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); | |
cd28ab6a SH |
3320 | } |
3321 | ||
4fb99cd6 | 3322 | if (hw->chip_id == CHIP_ID_YUKON_OPT || |
3323 | hw->chip_id == CHIP_ID_YUKON_PRM || | |
3324 | hw->chip_id == CHIP_ID_YUKON_OP_2) { | |
0f5aac70 | 3325 | u16 reg; |
0f5aac70 | 3326 | |
4fb99cd6 | 3327 | if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { |
0f5aac70 SH |
3328 | /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ |
3329 | sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); | |
3330 | ||
3331 | /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ | |
3332 | reg = 10; | |
4fb99cd6 | 3333 | |
3334 | /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ | |
3335 | sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); | |
0f5aac70 SH |
3336 | } else { |
3337 | /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ | |
3338 | reg = 3; | |
3339 | } | |
3340 | ||
3341 | reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; | |
4fb99cd6 | 3342 | reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; |
0f5aac70 SH |
3343 | |
3344 | /* reset PHY Link Detect */ | |
a40ccc68 | 3345 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
0f5aac70 SH |
3346 | sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); |
3347 | ||
0f5aac70 SH |
3348 | /* check if PSMv2 was running before */ |
3349 | reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); | |
1a10ccae | 3350 | if (reg & PCI_EXP_LNKCTL_ASPMC) |
0f5aac70 | 3351 | /* restore the PCIe Link Control register */ |
1a10ccae JM |
3352 | sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, |
3353 | reg); | |
3354 | ||
0e767324 ML |
3355 | if (hw->chip_id == CHIP_ID_YUKON_PRM && |
3356 | hw->chip_rev == CHIP_REV_YU_PRM_A0) { | |
3357 | /* change PHY Interrupt polarity to low active */ | |
3358 | reg = sky2_read16(hw, GPHY_CTRL); | |
3359 | sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); | |
3360 | ||
3361 | /* adapt HW for low active PHY Interrupt */ | |
3362 | reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); | |
3363 | sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); | |
3364 | } | |
3365 | ||
a40ccc68 | 3366 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
0f5aac70 SH |
3367 | |
3368 | /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ | |
3369 | sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); | |
3370 | } | |
3371 | ||
793b883e SH |
3372 | /* Clear I2C IRQ noise */ |
3373 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
3374 | |
3375 | /* turn off hardware timer (unused) */ | |
3376 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3377 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 3378 | |
69634ee7 SH |
3379 | /* Turn off descriptor polling */ |
3380 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
3381 | |
3382 | /* Turn off receive timestamp */ | |
3383 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 3384 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
3385 | |
3386 | /* enable the Tx Arbiters */ | |
3387 | for (i = 0; i < hw->ports; i++) | |
3388 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
3389 | ||
3390 | /* Initialize ram interface */ | |
3391 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 3392 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
3393 | |
3394 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
3395 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
3396 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
3397 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
3398 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
3399 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
3400 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
3401 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
3402 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
3403 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
3404 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
3405 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
3406 | } | |
3407 | ||
555382cb | 3408 | sky2_write32(hw, B0_HWE_IMSK, hwe_mask); |
cd28ab6a | 3409 | |
cd28ab6a | 3410 | for (i = 0; i < hw->ports; i++) |
d3bcfbeb | 3411 | sky2_gmac_reset(hw, i); |
cd28ab6a | 3412 | |
efe91932 | 3413 | memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); |
cd28ab6a SH |
3414 | hw->st_idx = 0; |
3415 | ||
3416 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
3417 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
3418 | ||
3419 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 3420 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
3421 | |
3422 | /* Set the list last index */ | |
efe91932 | 3423 | sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); |
cd28ab6a | 3424 | |
290d4de5 SH |
3425 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
3426 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 3427 | |
290d4de5 SH |
3428 | /* set Status-FIFO ISR watermark */ |
3429 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
3430 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
3431 | else | |
3432 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 3433 | |
290d4de5 | 3434 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
3435 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
3436 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 3437 | |
793b883e | 3438 | /* enable status unit */ |
cd28ab6a SH |
3439 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
3440 | ||
3441 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
3442 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
3443 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
e3173832 SH |
3444 | } |
3445 | ||
af18d8b8 SH |
3446 | /* Take device down (offline). |
3447 | * Equivalent to doing dev_stop() but this does not | |
25985edc | 3448 | * inform upper layers of the transition. |
af18d8b8 SH |
3449 | */ |
3450 | static void sky2_detach(struct net_device *dev) | |
3451 | { | |
3452 | if (netif_running(dev)) { | |
c36531b9 | 3453 | netif_tx_lock(dev); |
af18d8b8 | 3454 | netif_device_detach(dev); /* stop txq */ |
c36531b9 | 3455 | netif_tx_unlock(dev); |
926d0977 | 3456 | sky2_close(dev); |
af18d8b8 SH |
3457 | } |
3458 | } | |
3459 | ||
3460 | /* Bring device back after doing sky2_detach */ | |
3461 | static int sky2_reattach(struct net_device *dev) | |
3462 | { | |
3463 | int err = 0; | |
3464 | ||
3465 | if (netif_running(dev)) { | |
926d0977 | 3466 | err = sky2_open(dev); |
af18d8b8 | 3467 | if (err) { |
ada1db5c | 3468 | netdev_info(dev, "could not restart %d\n", err); |
af18d8b8 SH |
3469 | dev_close(dev); |
3470 | } else { | |
3471 | netif_device_attach(dev); | |
3472 | sky2_set_multicast(dev); | |
3473 | } | |
3474 | } | |
3475 | ||
3476 | return err; | |
3477 | } | |
3478 | ||
d72ff8fa | 3479 | static void sky2_all_down(struct sky2_hw *hw) |
81906791 | 3480 | { |
af18d8b8 | 3481 | int i; |
81906791 | 3482 | |
282edcec | 3483 | if (hw->flags & SKY2_HW_IRQ_SETUP) { |
3484 | sky2_read32(hw, B0_IMSK); | |
3485 | sky2_write32(hw, B0_IMSK, 0); | |
1401a800 | 3486 | |
1401a800 | 3487 | synchronize_irq(hw->pdev->irq); |
282edcec | 3488 | napi_disable(&hw->napi); |
3489 | } | |
8a0c9228 MM |
3490 | |
3491 | for (i = 0; i < hw->ports; i++) { | |
3492 | struct net_device *dev = hw->dev[i]; | |
3493 | struct sky2_port *sky2 = netdev_priv(dev); | |
3494 | ||
3495 | if (!netif_running(dev)) | |
3496 | continue; | |
3497 | ||
3498 | netif_carrier_off(dev); | |
3499 | netif_tx_disable(dev); | |
3500 | sky2_hw_down(sky2); | |
3501 | } | |
d72ff8fa | 3502 | } |
8a0c9228 | 3503 | |
d72ff8fa MM |
3504 | static void sky2_all_up(struct sky2_hw *hw) |
3505 | { | |
3506 | u32 imask = Y2_IS_BASE; | |
3507 | int i; | |
81906791 | 3508 | |
8a0c9228 MM |
3509 | for (i = 0; i < hw->ports; i++) { |
3510 | struct net_device *dev = hw->dev[i]; | |
3511 | struct sky2_port *sky2 = netdev_priv(dev); | |
3512 | ||
3513 | if (!netif_running(dev)) | |
3514 | continue; | |
3515 | ||
3516 | sky2_hw_up(sky2); | |
37652522 | 3517 | sky2_set_multicast(dev); |
d72ff8fa | 3518 | imask |= portirq_msk[i]; |
8a0c9228 MM |
3519 | netif_wake_queue(dev); |
3520 | } | |
3521 | ||
282edcec | 3522 | if (hw->flags & SKY2_HW_IRQ_SETUP) { |
1401a800 | 3523 | sky2_write32(hw, B0_IMSK, imask); |
3524 | sky2_read32(hw, B0_IMSK); | |
3525 | sky2_read32(hw, B0_Y2_SP_LISR); | |
3526 | napi_enable(&hw->napi); | |
3527 | } | |
d72ff8fa MM |
3528 | } |
3529 | ||
3530 | static void sky2_restart(struct work_struct *work) | |
3531 | { | |
3532 | struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); | |
3533 | ||
3534 | rtnl_lock(); | |
3535 | ||
3536 | sky2_all_down(hw); | |
3537 | sky2_reset(hw); | |
3538 | sky2_all_up(hw); | |
81906791 | 3539 | |
81906791 SH |
3540 | rtnl_unlock(); |
3541 | } | |
3542 | ||
e3173832 SH |
3543 | static inline u8 sky2_wol_supported(const struct sky2_hw *hw) |
3544 | { | |
3545 | return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; | |
3546 | } | |
3547 | ||
3548 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3549 | { | |
3550 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3551 | ||
3552 | wol->supported = sky2_wol_supported(sky2->hw); | |
3553 | wol->wolopts = sky2->wol; | |
3554 | } | |
3555 | ||
3556 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3557 | { | |
3558 | struct sky2_port *sky2 = netdev_priv(dev); | |
3559 | struct sky2_hw *hw = sky2->hw; | |
0f333d10 RW |
3560 | bool enable_wakeup = false; |
3561 | int i; | |
cd28ab6a | 3562 | |
8e95a202 JP |
3563 | if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || |
3564 | !device_can_wakeup(&hw->pdev->dev)) | |
e3173832 SH |
3565 | return -EOPNOTSUPP; |
3566 | ||
3567 | sky2->wol = wol->wolopts; | |
0f333d10 RW |
3568 | |
3569 | for (i = 0; i < hw->ports; i++) { | |
3570 | struct net_device *dev = hw->dev[i]; | |
3571 | struct sky2_port *sky2 = netdev_priv(dev); | |
3572 | ||
3573 | if (sky2->wol) | |
3574 | enable_wakeup = true; | |
3575 | } | |
3576 | device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); | |
3577 | ||
cd28ab6a SH |
3578 | return 0; |
3579 | } | |
3580 | ||
28bd181a | 3581 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a | 3582 | { |
b89165f2 SH |
3583 | if (sky2_is_copper(hw)) { |
3584 | u32 modes = SUPPORTED_10baseT_Half | |
3585 | | SUPPORTED_10baseT_Full | |
3586 | | SUPPORTED_100baseT_Half | |
2aca31e7 | 3587 | | SUPPORTED_100baseT_Full; |
cd28ab6a | 3588 | |
ea76e635 | 3589 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a | 3590 | modes |= SUPPORTED_1000baseT_Half |
b89165f2 SH |
3591 | | SUPPORTED_1000baseT_Full; |
3592 | return modes; | |
cd28ab6a | 3593 | } else |
2aca31e7 SH |
3594 | return SUPPORTED_1000baseT_Half |
3595 | | SUPPORTED_1000baseT_Full; | |
cd28ab6a SH |
3596 | } |
3597 | ||
793b883e | 3598 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
3599 | { |
3600 | struct sky2_port *sky2 = netdev_priv(dev); | |
3601 | struct sky2_hw *hw = sky2->hw; | |
3602 | ||
3603 | ecmd->transceiver = XCVR_INTERNAL; | |
3604 | ecmd->supported = sky2_supported_modes(hw); | |
3605 | ecmd->phy_address = PHY_ADDR_MARV; | |
b89165f2 | 3606 | if (sky2_is_copper(hw)) { |
cd28ab6a | 3607 | ecmd->port = PORT_TP; |
70739497 | 3608 | ethtool_cmd_speed_set(ecmd, sky2->speed); |
2aca31e7 | 3609 | ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; |
b89165f2 | 3610 | } else { |
70739497 | 3611 | ethtool_cmd_speed_set(ecmd, SPEED_1000); |
cd28ab6a | 3612 | ecmd->port = PORT_FIBRE; |
2aca31e7 | 3613 | ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
b89165f2 | 3614 | } |
cd28ab6a SH |
3615 | |
3616 | ecmd->advertising = sky2->advertising; | |
0ea065e5 SH |
3617 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
3618 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
cd28ab6a SH |
3619 | ecmd->duplex = sky2->duplex; |
3620 | return 0; | |
3621 | } | |
3622 | ||
3623 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3624 | { | |
3625 | struct sky2_port *sky2 = netdev_priv(dev); | |
3626 | const struct sky2_hw *hw = sky2->hw; | |
3627 | u32 supported = sky2_supported_modes(hw); | |
3628 | ||
3629 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2aca31e7 SH |
3630 | if (ecmd->advertising & ~supported) |
3631 | return -EINVAL; | |
3632 | ||
3633 | if (sky2_is_copper(hw)) | |
3634 | sky2->advertising = ecmd->advertising | | |
3635 | ADVERTISED_TP | | |
3636 | ADVERTISED_Autoneg; | |
3637 | else | |
3638 | sky2->advertising = ecmd->advertising | | |
3639 | ADVERTISED_FIBRE | | |
3640 | ADVERTISED_Autoneg; | |
3641 | ||
0ea065e5 | 3642 | sky2->flags |= SKY2_FLAG_AUTO_SPEED; |
cd28ab6a SH |
3643 | sky2->duplex = -1; |
3644 | sky2->speed = -1; | |
3645 | } else { | |
3646 | u32 setting; | |
25db0338 | 3647 | u32 speed = ethtool_cmd_speed(ecmd); |
cd28ab6a | 3648 | |
25db0338 | 3649 | switch (speed) { |
cd28ab6a SH |
3650 | case SPEED_1000: |
3651 | if (ecmd->duplex == DUPLEX_FULL) | |
3652 | setting = SUPPORTED_1000baseT_Full; | |
3653 | else if (ecmd->duplex == DUPLEX_HALF) | |
3654 | setting = SUPPORTED_1000baseT_Half; | |
3655 | else | |
3656 | return -EINVAL; | |
3657 | break; | |
3658 | case SPEED_100: | |
3659 | if (ecmd->duplex == DUPLEX_FULL) | |
3660 | setting = SUPPORTED_100baseT_Full; | |
3661 | else if (ecmd->duplex == DUPLEX_HALF) | |
3662 | setting = SUPPORTED_100baseT_Half; | |
3663 | else | |
3664 | return -EINVAL; | |
3665 | break; | |
3666 | ||
3667 | case SPEED_10: | |
3668 | if (ecmd->duplex == DUPLEX_FULL) | |
3669 | setting = SUPPORTED_10baseT_Full; | |
3670 | else if (ecmd->duplex == DUPLEX_HALF) | |
3671 | setting = SUPPORTED_10baseT_Half; | |
3672 | else | |
3673 | return -EINVAL; | |
3674 | break; | |
3675 | default: | |
3676 | return -EINVAL; | |
3677 | } | |
3678 | ||
3679 | if ((setting & supported) == 0) | |
3680 | return -EINVAL; | |
3681 | ||
25db0338 | 3682 | sky2->speed = speed; |
cd28ab6a | 3683 | sky2->duplex = ecmd->duplex; |
0ea065e5 | 3684 | sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; |
cd28ab6a SH |
3685 | } |
3686 | ||
d1b139c0 | 3687 | if (netif_running(dev)) { |
1b537565 | 3688 | sky2_phy_reinit(sky2); |
d1b139c0 SH |
3689 | sky2_set_multicast(dev); |
3690 | } | |
cd28ab6a SH |
3691 | |
3692 | return 0; | |
3693 | } | |
3694 | ||
3695 | static void sky2_get_drvinfo(struct net_device *dev, | |
3696 | struct ethtool_drvinfo *info) | |
3697 | { | |
3698 | struct sky2_port *sky2 = netdev_priv(dev); | |
3699 | ||
68aad78c RJ |
3700 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
3701 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
68aad78c RJ |
3702 | strlcpy(info->bus_info, pci_name(sky2->hw->pdev), |
3703 | sizeof(info->bus_info)); | |
cd28ab6a SH |
3704 | } |
3705 | ||
3706 | static const struct sky2_stat { | |
793b883e SH |
3707 | char name[ETH_GSTRING_LEN]; |
3708 | u16 offset; | |
cd28ab6a SH |
3709 | } sky2_stats[] = { |
3710 | { "tx_bytes", GM_TXO_OK_HI }, | |
3711 | { "rx_bytes", GM_RXO_OK_HI }, | |
3712 | { "tx_broadcast", GM_TXF_BC_OK }, | |
3713 | { "rx_broadcast", GM_RXF_BC_OK }, | |
3714 | { "tx_multicast", GM_TXF_MC_OK }, | |
3715 | { "rx_multicast", GM_RXF_MC_OK }, | |
3716 | { "tx_unicast", GM_TXF_UC_OK }, | |
3717 | { "rx_unicast", GM_RXF_UC_OK }, | |
3718 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
3719 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 3720 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
3721 | { "late_collision",GM_TXF_LAT_COL }, |
3722 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 3723 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 3724 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 3725 | |
d2604540 | 3726 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 3727 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
3728 | { "rx_64_byte_packets", GM_RXF_64B }, |
3729 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
3730 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
3731 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
3732 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
3733 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
3734 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 3735 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
3736 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
3737 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 3738 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
3739 | |
3740 | { "tx_64_byte_packets", GM_TXF_64B }, | |
3741 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
3742 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
3743 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
3744 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
3745 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
3746 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
3747 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
3748 | }; |
3749 | ||
cd28ab6a SH |
3750 | static u32 sky2_get_msglevel(struct net_device *netdev) |
3751 | { | |
3752 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3753 | return sky2->msg_enable; | |
3754 | } | |
3755 | ||
9a7ae0a9 SH |
3756 | static int sky2_nway_reset(struct net_device *dev) |
3757 | { | |
3758 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 | 3759 | |
0ea065e5 | 3760 | if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) |
9a7ae0a9 SH |
3761 | return -EINVAL; |
3762 | ||
1b537565 | 3763 | sky2_phy_reinit(sky2); |
d1b139c0 | 3764 | sky2_set_multicast(dev); |
9a7ae0a9 SH |
3765 | |
3766 | return 0; | |
3767 | } | |
3768 | ||
793b883e | 3769 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
3770 | { |
3771 | struct sky2_hw *hw = sky2->hw; | |
3772 | unsigned port = sky2->port; | |
3773 | int i; | |
3774 | ||
0885a30b | 3775 | data[0] = get_stats64(hw, port, GM_TXO_OK_LO); |
3776 | data[1] = get_stats64(hw, port, GM_RXO_OK_LO); | |
cd28ab6a | 3777 | |
793b883e | 3778 | for (i = 2; i < count; i++) |
0885a30b | 3779 | data[i] = get_stats32(hw, port, sky2_stats[i].offset); |
cd28ab6a SH |
3780 | } |
3781 | ||
cd28ab6a SH |
3782 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
3783 | { | |
3784 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3785 | sky2->msg_enable = value; | |
3786 | } | |
3787 | ||
b9f2c044 | 3788 | static int sky2_get_sset_count(struct net_device *dev, int sset) |
cd28ab6a | 3789 | { |
b9f2c044 JG |
3790 | switch (sset) { |
3791 | case ETH_SS_STATS: | |
3792 | return ARRAY_SIZE(sky2_stats); | |
3793 | default: | |
3794 | return -EOPNOTSUPP; | |
3795 | } | |
cd28ab6a SH |
3796 | } |
3797 | ||
3798 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 3799 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
3800 | { |
3801 | struct sky2_port *sky2 = netdev_priv(dev); | |
3802 | ||
793b883e | 3803 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
3804 | } |
3805 | ||
793b883e | 3806 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
3807 | { |
3808 | int i; | |
3809 | ||
3810 | switch (stringset) { | |
3811 | case ETH_SS_STATS: | |
3812 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
3813 | memcpy(data + i * ETH_GSTRING_LEN, | |
3814 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
3815 | break; | |
3816 | } | |
3817 | } | |
3818 | ||
cd28ab6a SH |
3819 | static int sky2_set_mac_address(struct net_device *dev, void *p) |
3820 | { | |
3821 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
3822 | struct sky2_hw *hw = sky2->hw; |
3823 | unsigned port = sky2->port; | |
3824 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
3825 | |
3826 | if (!is_valid_ether_addr(addr->sa_data)) | |
3827 | return -EADDRNOTAVAIL; | |
3828 | ||
cd28ab6a | 3829 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 3830 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 3831 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 3832 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 3833 | dev->dev_addr, ETH_ALEN); |
1b537565 | 3834 | |
a8ab1ec0 SH |
3835 | /* virtual address for data */ |
3836 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3837 | ||
3838 | /* physical address: used for pause frames */ | |
3839 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
3840 | |
3841 | return 0; | |
cd28ab6a SH |
3842 | } |
3843 | ||
060b946c | 3844 | static inline void sky2_add_filter(u8 filter[8], const u8 *addr) |
a052b52f SH |
3845 | { |
3846 | u32 bit; | |
3847 | ||
3848 | bit = ether_crc(ETH_ALEN, addr) & 63; | |
3849 | filter[bit >> 3] |= 1 << (bit & 7); | |
3850 | } | |
3851 | ||
cd28ab6a SH |
3852 | static void sky2_set_multicast(struct net_device *dev) |
3853 | { | |
3854 | struct sky2_port *sky2 = netdev_priv(dev); | |
3855 | struct sky2_hw *hw = sky2->hw; | |
3856 | unsigned port = sky2->port; | |
22bedad3 | 3857 | struct netdev_hw_addr *ha; |
cd28ab6a SH |
3858 | u16 reg; |
3859 | u8 filter[8]; | |
a052b52f SH |
3860 | int rx_pause; |
3861 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; | |
cd28ab6a | 3862 | |
a052b52f | 3863 | rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); |
cd28ab6a SH |
3864 | memset(filter, 0, sizeof(filter)); |
3865 | ||
3866 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
3867 | reg |= GM_RXCR_UCF_ENA; | |
3868 | ||
d571b694 | 3869 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 3870 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
a052b52f | 3871 | else if (dev->flags & IFF_ALLMULTI) |
cd28ab6a | 3872 | memset(filter, 0xff, sizeof(filter)); |
4cd24eaf | 3873 | else if (netdev_mc_empty(dev) && !rx_pause) |
cd28ab6a SH |
3874 | reg &= ~GM_RXCR_MCF_ENA; |
3875 | else { | |
cd28ab6a SH |
3876 | reg |= GM_RXCR_MCF_ENA; |
3877 | ||
a052b52f SH |
3878 | if (rx_pause) |
3879 | sky2_add_filter(filter, pause_mc_addr); | |
3880 | ||
22bedad3 JP |
3881 | netdev_for_each_mc_addr(ha, dev) |
3882 | sky2_add_filter(filter, ha->addr); | |
cd28ab6a SH |
3883 | } |
3884 | ||
cd28ab6a | 3885 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 3886 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 3887 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 3888 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 3889 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 3890 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 3891 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 3892 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
3893 | |
3894 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
3895 | } | |
3896 | ||
0885a30b | 3897 | static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, |
3898 | struct rtnl_link_stats64 *stats) | |
3899 | { | |
3900 | struct sky2_port *sky2 = netdev_priv(dev); | |
3901 | struct sky2_hw *hw = sky2->hw; | |
3902 | unsigned port = sky2->port; | |
3903 | unsigned int start; | |
3904 | u64 _bytes, _packets; | |
3905 | ||
3906 | do { | |
3907 | start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp); | |
3908 | _bytes = sky2->rx_stats.bytes; | |
3909 | _packets = sky2->rx_stats.packets; | |
3910 | } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start)); | |
3911 | ||
3912 | stats->rx_packets = _packets; | |
3913 | stats->rx_bytes = _bytes; | |
3914 | ||
3915 | do { | |
3916 | start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp); | |
3917 | _bytes = sky2->tx_stats.bytes; | |
3918 | _packets = sky2->tx_stats.packets; | |
3919 | } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start)); | |
3920 | ||
3921 | stats->tx_packets = _packets; | |
3922 | stats->tx_bytes = _bytes; | |
3923 | ||
3924 | stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) | |
3925 | + get_stats32(hw, port, GM_RXF_BC_OK); | |
3926 | ||
3927 | stats->collisions = get_stats32(hw, port, GM_TXF_COL); | |
3928 | ||
3929 | stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); | |
3930 | stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); | |
3931 | stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) | |
3932 | + get_stats32(hw, port, GM_RXE_FRAG); | |
3933 | stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); | |
3934 | ||
3935 | stats->rx_dropped = dev->stats.rx_dropped; | |
3936 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
3937 | stats->tx_fifo_errors = dev->stats.tx_fifo_errors; | |
3938 | ||
3939 | return stats; | |
3940 | } | |
3941 | ||
cd28ab6a SH |
3942 | /* Can have one global because blinking is controlled by |
3943 | * ethtool and that is always under RTNL mutex | |
3944 | */ | |
a84d0a3d | 3945 | static void sky2_led(struct sky2_port *sky2, enum led_mode mode) |
cd28ab6a | 3946 | { |
a84d0a3d SH |
3947 | struct sky2_hw *hw = sky2->hw; |
3948 | unsigned port = sky2->port; | |
793b883e | 3949 | |
a84d0a3d SH |
3950 | spin_lock_bh(&sky2->phy_lock); |
3951 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || | |
3952 | hw->chip_id == CHIP_ID_YUKON_EX || | |
3953 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
3954 | u16 pg; | |
793b883e SH |
3955 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
3956 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
793b883e | 3957 | |
a84d0a3d SH |
3958 | switch (mode) { |
3959 | case MO_LED_OFF: | |
3960 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3961 | PHY_M_LEDC_LOS_CTRL(8) | | |
3962 | PHY_M_LEDC_INIT_CTRL(8) | | |
3963 | PHY_M_LEDC_STA1_CTRL(8) | | |
3964 | PHY_M_LEDC_STA0_CTRL(8)); | |
3965 | break; | |
3966 | case MO_LED_ON: | |
3967 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3968 | PHY_M_LEDC_LOS_CTRL(9) | | |
3969 | PHY_M_LEDC_INIT_CTRL(9) | | |
3970 | PHY_M_LEDC_STA1_CTRL(9) | | |
3971 | PHY_M_LEDC_STA0_CTRL(9)); | |
3972 | break; | |
3973 | case MO_LED_BLINK: | |
3974 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3975 | PHY_M_LEDC_LOS_CTRL(0xa) | | |
3976 | PHY_M_LEDC_INIT_CTRL(0xa) | | |
3977 | PHY_M_LEDC_STA1_CTRL(0xa) | | |
3978 | PHY_M_LEDC_STA0_CTRL(0xa)); | |
3979 | break; | |
3980 | case MO_LED_NORM: | |
3981 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3982 | PHY_M_LEDC_LOS_CTRL(1) | | |
3983 | PHY_M_LEDC_INIT_CTRL(8) | | |
3984 | PHY_M_LEDC_STA1_CTRL(7) | | |
3985 | PHY_M_LEDC_STA0_CTRL(7)); | |
3986 | } | |
793b883e | 3987 | |
a84d0a3d SH |
3988 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
3989 | } else | |
7d2e3cb7 | 3990 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
a84d0a3d SH |
3991 | PHY_M_LED_MO_DUP(mode) | |
3992 | PHY_M_LED_MO_10(mode) | | |
3993 | PHY_M_LED_MO_100(mode) | | |
3994 | PHY_M_LED_MO_1000(mode) | | |
3995 | PHY_M_LED_MO_RX(mode) | | |
3996 | PHY_M_LED_MO_TX(mode)); | |
3997 | ||
3998 | spin_unlock_bh(&sky2->phy_lock); | |
cd28ab6a SH |
3999 | } |
4000 | ||
4001 | /* blink LED's for finding board */ | |
74e532ff | 4002 | static int sky2_set_phys_id(struct net_device *dev, |
4003 | enum ethtool_phys_id_state state) | |
cd28ab6a SH |
4004 | { |
4005 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a | 4006 | |
74e532ff | 4007 | switch (state) { |
4008 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 4009 | return 1; /* cycle on/off once per second */ |
74e532ff | 4010 | case ETHTOOL_ID_INACTIVE: |
4011 | sky2_led(sky2, MO_LED_NORM); | |
4012 | break; | |
4013 | case ETHTOOL_ID_ON: | |
a84d0a3d | 4014 | sky2_led(sky2, MO_LED_ON); |
74e532ff | 4015 | break; |
4016 | case ETHTOOL_ID_OFF: | |
a84d0a3d | 4017 | sky2_led(sky2, MO_LED_OFF); |
74e532ff | 4018 | break; |
793b883e | 4019 | } |
cd28ab6a SH |
4020 | |
4021 | return 0; | |
4022 | } | |
4023 | ||
4024 | static void sky2_get_pauseparam(struct net_device *dev, | |
4025 | struct ethtool_pauseparam *ecmd) | |
4026 | { | |
4027 | struct sky2_port *sky2 = netdev_priv(dev); | |
4028 | ||
16ad91e1 SH |
4029 | switch (sky2->flow_mode) { |
4030 | case FC_NONE: | |
4031 | ecmd->tx_pause = ecmd->rx_pause = 0; | |
4032 | break; | |
4033 | case FC_TX: | |
4034 | ecmd->tx_pause = 1, ecmd->rx_pause = 0; | |
4035 | break; | |
4036 | case FC_RX: | |
4037 | ecmd->tx_pause = 0, ecmd->rx_pause = 1; | |
4038 | break; | |
4039 | case FC_BOTH: | |
4040 | ecmd->tx_pause = ecmd->rx_pause = 1; | |
4041 | } | |
4042 | ||
0ea065e5 SH |
4043 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) |
4044 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
cd28ab6a SH |
4045 | } |
4046 | ||
4047 | static int sky2_set_pauseparam(struct net_device *dev, | |
4048 | struct ethtool_pauseparam *ecmd) | |
4049 | { | |
4050 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a | 4051 | |
0ea065e5 SH |
4052 | if (ecmd->autoneg == AUTONEG_ENABLE) |
4053 | sky2->flags |= SKY2_FLAG_AUTO_PAUSE; | |
4054 | else | |
4055 | sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; | |
4056 | ||
16ad91e1 | 4057 | sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); |
cd28ab6a | 4058 | |
16ad91e1 SH |
4059 | if (netif_running(dev)) |
4060 | sky2_phy_reinit(sky2); | |
cd28ab6a | 4061 | |
2eaba1a2 | 4062 | return 0; |
cd28ab6a SH |
4063 | } |
4064 | ||
fb17358f SH |
4065 | static int sky2_get_coalesce(struct net_device *dev, |
4066 | struct ethtool_coalesce *ecmd) | |
4067 | { | |
4068 | struct sky2_port *sky2 = netdev_priv(dev); | |
4069 | struct sky2_hw *hw = sky2->hw; | |
4070 | ||
4071 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
4072 | ecmd->tx_coalesce_usecs = 0; | |
4073 | else { | |
4074 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
4075 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
4076 | } | |
4077 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
4078 | ||
4079 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
4080 | ecmd->rx_coalesce_usecs = 0; | |
4081 | else { | |
4082 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
4083 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
4084 | } | |
4085 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
4086 | ||
4087 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
4088 | ecmd->rx_coalesce_usecs_irq = 0; | |
4089 | else { | |
4090 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
4091 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
4092 | } | |
4093 | ||
4094 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
4095 | ||
4096 | return 0; | |
4097 | } | |
4098 | ||
4099 | /* Note: this affect both ports */ | |
4100 | static int sky2_set_coalesce(struct net_device *dev, | |
4101 | struct ethtool_coalesce *ecmd) | |
4102 | { | |
4103 | struct sky2_port *sky2 = netdev_priv(dev); | |
4104 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 4105 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 4106 | |
77b3d6a2 SH |
4107 | if (ecmd->tx_coalesce_usecs > tmax || |
4108 | ecmd->rx_coalesce_usecs > tmax || | |
4109 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
4110 | return -EINVAL; |
4111 | ||
ee5f68fe | 4112 | if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) |
fb17358f | 4113 | return -EINVAL; |
ff81fbbe | 4114 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 4115 | return -EINVAL; |
060b946c | 4116 | if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) |
fb17358f SH |
4117 | return -EINVAL; |
4118 | ||
4119 | if (ecmd->tx_coalesce_usecs == 0) | |
4120 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
4121 | else { | |
4122 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
4123 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
4124 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
4125 | } | |
4126 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
4127 | ||
4128 | if (ecmd->rx_coalesce_usecs == 0) | |
4129 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
4130 | else { | |
4131 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
4132 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
4133 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
4134 | } | |
4135 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
4136 | ||
4137 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
4138 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
4139 | else { | |
d28d4870 | 4140 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
4141 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
4142 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
4143 | } | |
4144 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
4145 | return 0; | |
4146 | } | |
4147 | ||
738a849c | 4148 | /* |
4149 | * Hardware is limited to min of 128 and max of 2048 for ring size | |
4150 | * and rounded up to next power of two | |
4151 | * to avoid division in modulus calclation | |
4152 | */ | |
4153 | static unsigned long roundup_ring_size(unsigned long pending) | |
4154 | { | |
4155 | return max(128ul, roundup_pow_of_two(pending+1)); | |
4156 | } | |
4157 | ||
793b883e SH |
4158 | static void sky2_get_ringparam(struct net_device *dev, |
4159 | struct ethtool_ringparam *ering) | |
4160 | { | |
4161 | struct sky2_port *sky2 = netdev_priv(dev); | |
4162 | ||
4163 | ering->rx_max_pending = RX_MAX_PENDING; | |
ee5f68fe | 4164 | ering->tx_max_pending = TX_MAX_PENDING; |
793b883e SH |
4165 | |
4166 | ering->rx_pending = sky2->rx_pending; | |
793b883e SH |
4167 | ering->tx_pending = sky2->tx_pending; |
4168 | } | |
4169 | ||
4170 | static int sky2_set_ringparam(struct net_device *dev, | |
4171 | struct ethtool_ringparam *ering) | |
4172 | { | |
4173 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e SH |
4174 | |
4175 | if (ering->rx_pending > RX_MAX_PENDING || | |
4176 | ering->rx_pending < 8 || | |
ee5f68fe SH |
4177 | ering->tx_pending < TX_MIN_PENDING || |
4178 | ering->tx_pending > TX_MAX_PENDING) | |
793b883e SH |
4179 | return -EINVAL; |
4180 | ||
af18d8b8 | 4181 | sky2_detach(dev); |
793b883e SH |
4182 | |
4183 | sky2->rx_pending = ering->rx_pending; | |
4184 | sky2->tx_pending = ering->tx_pending; | |
738a849c | 4185 | sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); |
793b883e | 4186 | |
af18d8b8 | 4187 | return sky2_reattach(dev); |
793b883e SH |
4188 | } |
4189 | ||
793b883e SH |
4190 | static int sky2_get_regs_len(struct net_device *dev) |
4191 | { | |
6e4cbb34 | 4192 | return 0x4000; |
793b883e SH |
4193 | } |
4194 | ||
c32bbff8 MM |
4195 | static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) |
4196 | { | |
4197 | /* This complicated switch statement is to make sure and | |
4198 | * only access regions that are unreserved. | |
4199 | * Some blocks are only valid on dual port cards. | |
4200 | */ | |
4201 | switch (b) { | |
4202 | /* second port */ | |
4203 | case 5: /* Tx Arbiter 2 */ | |
4204 | case 9: /* RX2 */ | |
4205 | case 14 ... 15: /* TX2 */ | |
4206 | case 17: case 19: /* Ram Buffer 2 */ | |
4207 | case 22 ... 23: /* Tx Ram Buffer 2 */ | |
4208 | case 25: /* Rx MAC Fifo 1 */ | |
4209 | case 27: /* Tx MAC Fifo 2 */ | |
4210 | case 31: /* GPHY 2 */ | |
4211 | case 40 ... 47: /* Pattern Ram 2 */ | |
4212 | case 52: case 54: /* TCP Segmentation 2 */ | |
4213 | case 112 ... 116: /* GMAC 2 */ | |
4214 | return hw->ports > 1; | |
4215 | ||
4216 | case 0: /* Control */ | |
4217 | case 2: /* Mac address */ | |
4218 | case 4: /* Tx Arbiter 1 */ | |
4219 | case 7: /* PCI express reg */ | |
4220 | case 8: /* RX1 */ | |
4221 | case 12 ... 13: /* TX1 */ | |
4222 | case 16: case 18:/* Rx Ram Buffer 1 */ | |
4223 | case 20 ... 21: /* Tx Ram Buffer 1 */ | |
4224 | case 24: /* Rx MAC Fifo 1 */ | |
4225 | case 26: /* Tx MAC Fifo 1 */ | |
4226 | case 28 ... 29: /* Descriptor and status unit */ | |
4227 | case 30: /* GPHY 1*/ | |
4228 | case 32 ... 39: /* Pattern Ram 1 */ | |
4229 | case 48: case 50: /* TCP Segmentation 1 */ | |
4230 | case 56 ... 60: /* PCI space */ | |
4231 | case 80 ... 84: /* GMAC 1 */ | |
4232 | return 1; | |
4233 | ||
4234 | default: | |
4235 | return 0; | |
4236 | } | |
4237 | } | |
4238 | ||
793b883e SH |
4239 | /* |
4240 | * Returns copy of control register region | |
3ead5db7 | 4241 | * Note: ethtool_get_regs always provides full size (16k) buffer |
793b883e SH |
4242 | */ |
4243 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4244 | void *p) | |
4245 | { | |
4246 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 4247 | const void __iomem *io = sky2->hw->regs; |
295b54c4 | 4248 | unsigned int b; |
793b883e SH |
4249 | |
4250 | regs->version = 1; | |
793b883e | 4251 | |
295b54c4 | 4252 | for (b = 0; b < 128; b++) { |
c32bbff8 MM |
4253 | /* skip poisonous diagnostic ram region in block 3 */ |
4254 | if (b == 3) | |
295b54c4 | 4255 | memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); |
c32bbff8 | 4256 | else if (sky2_reg_access_ok(sky2->hw, b)) |
295b54c4 | 4257 | memcpy_fromio(p, io, 128); |
c32bbff8 | 4258 | else |
295b54c4 | 4259 | memset(p, 0, 128); |
3ead5db7 | 4260 | |
295b54c4 SH |
4261 | p += 128; |
4262 | io += 128; | |
4263 | } | |
793b883e | 4264 | } |
cd28ab6a | 4265 | |
f4331a6d SH |
4266 | static int sky2_get_eeprom_len(struct net_device *dev) |
4267 | { | |
4268 | struct sky2_port *sky2 = netdev_priv(dev); | |
b32f40c4 | 4269 | struct sky2_hw *hw = sky2->hw; |
f4331a6d SH |
4270 | u16 reg2; |
4271 | ||
b32f40c4 | 4272 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
f4331a6d SH |
4273 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
4274 | } | |
4275 | ||
1413235c | 4276 | static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) |
f4331a6d | 4277 | { |
1413235c | 4278 | unsigned long start = jiffies; |
f4331a6d | 4279 | |
1413235c SH |
4280 | while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { |
4281 | /* Can take up to 10.6 ms for write */ | |
4282 | if (time_after(jiffies, start + HZ/4)) { | |
ada1db5c | 4283 | dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); |
1413235c SH |
4284 | return -ETIMEDOUT; |
4285 | } | |
4286 | mdelay(1); | |
4287 | } | |
167f53d0 | 4288 | |
1413235c SH |
4289 | return 0; |
4290 | } | |
167f53d0 | 4291 | |
1413235c SH |
4292 | static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, |
4293 | u16 offset, size_t length) | |
4294 | { | |
4295 | int rc = 0; | |
4296 | ||
4297 | while (length > 0) { | |
4298 | u32 val; | |
4299 | ||
4300 | sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); | |
4301 | rc = sky2_vpd_wait(hw, cap, 0); | |
4302 | if (rc) | |
4303 | break; | |
4304 | ||
4305 | val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); | |
4306 | ||
4307 | memcpy(data, &val, min(sizeof(val), length)); | |
4308 | offset += sizeof(u32); | |
4309 | data += sizeof(u32); | |
4310 | length -= sizeof(u32); | |
4311 | } | |
4312 | ||
4313 | return rc; | |
f4331a6d SH |
4314 | } |
4315 | ||
1413235c SH |
4316 | static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, |
4317 | u16 offset, unsigned int length) | |
f4331a6d | 4318 | { |
1413235c SH |
4319 | unsigned int i; |
4320 | int rc = 0; | |
4321 | ||
4322 | for (i = 0; i < length; i += sizeof(u32)) { | |
4323 | u32 val = *(u32 *)(data + i); | |
4324 | ||
4325 | sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); | |
4326 | sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); | |
4327 | ||
4328 | rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); | |
4329 | if (rc) | |
4330 | break; | |
4331 | } | |
4332 | return rc; | |
f4331a6d SH |
4333 | } |
4334 | ||
4335 | static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4336 | u8 *data) | |
4337 | { | |
4338 | struct sky2_port *sky2 = netdev_priv(dev); | |
4339 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
f4331a6d SH |
4340 | |
4341 | if (!cap) | |
4342 | return -EINVAL; | |
4343 | ||
4344 | eeprom->magic = SKY2_EEPROM_MAGIC; | |
4345 | ||
1413235c | 4346 | return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
f4331a6d SH |
4347 | } |
4348 | ||
4349 | static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4350 | u8 *data) | |
4351 | { | |
4352 | struct sky2_port *sky2 = netdev_priv(dev); | |
4353 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
f4331a6d SH |
4354 | |
4355 | if (!cap) | |
4356 | return -EINVAL; | |
4357 | ||
4358 | if (eeprom->magic != SKY2_EEPROM_MAGIC) | |
4359 | return -EINVAL; | |
4360 | ||
1413235c SH |
4361 | /* Partial writes not supported */ |
4362 | if ((eeprom->offset & 3) || (eeprom->len & 3)) | |
4363 | return -EINVAL; | |
f4331a6d | 4364 | |
1413235c | 4365 | return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
f4331a6d SH |
4366 | } |
4367 | ||
c8f44aff MM |
4368 | static netdev_features_t sky2_fix_features(struct net_device *dev, |
4369 | netdev_features_t features) | |
bf73130d | 4370 | { |
f5d64037 MM |
4371 | const struct sky2_port *sky2 = netdev_priv(dev); |
4372 | const struct sky2_hw *hw = sky2->hw; | |
bf73130d | 4373 | |
f5d64037 MM |
4374 | /* In order to do Jumbo packets on these chips, need to turn off the |
4375 | * transmit store/forward. Therefore checksum offload won't work. | |
4376 | */ | |
aa5ca96c | 4377 | if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { |
4378 | netdev_info(dev, "checksum offload not possible with jumbo frames\n"); | |
f5d64037 | 4379 | features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); |
aa5ca96c | 4380 | } |
4381 | ||
4382 | /* Some hardware requires receive checksum for RSS to work. */ | |
4383 | if ( (features & NETIF_F_RXHASH) && | |
4384 | !(features & NETIF_F_RXCSUM) && | |
4385 | (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { | |
4386 | netdev_info(dev, "receive hashing forces receive checksum\n"); | |
4387 | features |= NETIF_F_RXCSUM; | |
4388 | } | |
86aa7785 | 4389 | |
f5d64037 MM |
4390 | return features; |
4391 | } | |
86aa7785 | 4392 | |
c8f44aff | 4393 | static int sky2_set_features(struct net_device *dev, netdev_features_t features) |
f5d64037 MM |
4394 | { |
4395 | struct sky2_port *sky2 = netdev_priv(dev); | |
c8f44aff | 4396 | netdev_features_t changed = dev->features ^ features; |
86aa7785 | 4397 | |
5ff0feac | 4398 | if ((changed & NETIF_F_RXCSUM) && |
4399 | !(sky2->hw->flags & SKY2_HW_NEW_LE)) { | |
4400 | sky2_write32(sky2->hw, | |
4401 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
4402 | (features & NETIF_F_RXCSUM) | |
4403 | ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
f5d64037 | 4404 | } |
bf73130d | 4405 | |
f5d64037 MM |
4406 | if (changed & NETIF_F_RXHASH) |
4407 | rx_set_rss(dev, features); | |
86aa7785 | 4408 | |
f5d64037 MM |
4409 | if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)) |
4410 | sky2_vlan_mode(dev, features); | |
bf73130d SH |
4411 | |
4412 | return 0; | |
4413 | } | |
f4331a6d | 4414 | |
7282d491 | 4415 | static const struct ethtool_ops sky2_ethtool_ops = { |
f4331a6d SH |
4416 | .get_settings = sky2_get_settings, |
4417 | .set_settings = sky2_set_settings, | |
4418 | .get_drvinfo = sky2_get_drvinfo, | |
4419 | .get_wol = sky2_get_wol, | |
4420 | .set_wol = sky2_set_wol, | |
4421 | .get_msglevel = sky2_get_msglevel, | |
4422 | .set_msglevel = sky2_set_msglevel, | |
4423 | .nway_reset = sky2_nway_reset, | |
4424 | .get_regs_len = sky2_get_regs_len, | |
4425 | .get_regs = sky2_get_regs, | |
4426 | .get_link = ethtool_op_get_link, | |
4427 | .get_eeprom_len = sky2_get_eeprom_len, | |
4428 | .get_eeprom = sky2_get_eeprom, | |
4429 | .set_eeprom = sky2_set_eeprom, | |
f4331a6d SH |
4430 | .get_strings = sky2_get_strings, |
4431 | .get_coalesce = sky2_get_coalesce, | |
4432 | .set_coalesce = sky2_set_coalesce, | |
4433 | .get_ringparam = sky2_get_ringparam, | |
4434 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
4435 | .get_pauseparam = sky2_get_pauseparam, |
4436 | .set_pauseparam = sky2_set_pauseparam, | |
74e532ff | 4437 | .set_phys_id = sky2_set_phys_id, |
b9f2c044 | 4438 | .get_sset_count = sky2_get_sset_count, |
cd28ab6a SH |
4439 | .get_ethtool_stats = sky2_get_ethtool_stats, |
4440 | }; | |
4441 | ||
3cf26753 SH |
4442 | #ifdef CONFIG_SKY2_DEBUG |
4443 | ||
4444 | static struct dentry *sky2_debug; | |
4445 | ||
e4c2abe2 SH |
4446 | |
4447 | /* | |
4448 | * Read and parse the first part of Vital Product Data | |
4449 | */ | |
4450 | #define VPD_SIZE 128 | |
4451 | #define VPD_MAGIC 0x82 | |
4452 | ||
4453 | static const struct vpd_tag { | |
4454 | char tag[2]; | |
4455 | char *label; | |
4456 | } vpd_tags[] = { | |
4457 | { "PN", "Part Number" }, | |
4458 | { "EC", "Engineering Level" }, | |
4459 | { "MN", "Manufacturer" }, | |
4460 | { "SN", "Serial Number" }, | |
4461 | { "YA", "Asset Tag" }, | |
4462 | { "VL", "First Error Log Message" }, | |
4463 | { "VF", "Second Error Log Message" }, | |
4464 | { "VB", "Boot Agent ROM Configuration" }, | |
4465 | { "VE", "EFI UNDI Configuration" }, | |
4466 | }; | |
4467 | ||
4468 | static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) | |
4469 | { | |
4470 | size_t vpd_size; | |
4471 | loff_t offs; | |
4472 | u8 len; | |
4473 | unsigned char *buf; | |
4474 | u16 reg2; | |
4475 | ||
4476 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); | |
4477 | vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); | |
4478 | ||
4479 | seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); | |
4480 | buf = kmalloc(vpd_size, GFP_KERNEL); | |
4481 | if (!buf) { | |
4482 | seq_puts(seq, "no memory!\n"); | |
4483 | return; | |
4484 | } | |
4485 | ||
4486 | if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { | |
4487 | seq_puts(seq, "VPD read failed\n"); | |
4488 | goto out; | |
4489 | } | |
4490 | ||
4491 | if (buf[0] != VPD_MAGIC) { | |
4492 | seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); | |
4493 | goto out; | |
4494 | } | |
4495 | len = buf[1]; | |
4496 | if (len == 0 || len > vpd_size - 4) { | |
4497 | seq_printf(seq, "Invalid id length: %d\n", len); | |
4498 | goto out; | |
4499 | } | |
4500 | ||
4501 | seq_printf(seq, "%.*s\n", len, buf + 3); | |
4502 | offs = len + 3; | |
4503 | ||
4504 | while (offs < vpd_size - 4) { | |
4505 | int i; | |
4506 | ||
4507 | if (!memcmp("RW", buf + offs, 2)) /* end marker */ | |
4508 | break; | |
4509 | len = buf[offs + 2]; | |
4510 | if (offs + len + 3 >= vpd_size) | |
4511 | break; | |
4512 | ||
4513 | for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { | |
4514 | if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { | |
4515 | seq_printf(seq, " %s: %.*s\n", | |
4516 | vpd_tags[i].label, len, buf + offs + 3); | |
4517 | break; | |
4518 | } | |
4519 | } | |
4520 | offs += len + 3; | |
4521 | } | |
4522 | out: | |
4523 | kfree(buf); | |
4524 | } | |
4525 | ||
3cf26753 SH |
4526 | static int sky2_debug_show(struct seq_file *seq, void *v) |
4527 | { | |
4528 | struct net_device *dev = seq->private; | |
4529 | const struct sky2_port *sky2 = netdev_priv(dev); | |
bea3348e | 4530 | struct sky2_hw *hw = sky2->hw; |
3cf26753 SH |
4531 | unsigned port = sky2->port; |
4532 | unsigned idx, last; | |
4533 | int sop; | |
4534 | ||
e4c2abe2 | 4535 | sky2_show_vpd(seq, hw); |
3cf26753 | 4536 | |
e4c2abe2 | 4537 | seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", |
3cf26753 SH |
4538 | sky2_read32(hw, B0_ISRC), |
4539 | sky2_read32(hw, B0_IMSK), | |
4540 | sky2_read32(hw, B0_Y2_SP_ICR)); | |
4541 | ||
e4c2abe2 SH |
4542 | if (!netif_running(dev)) { |
4543 | seq_printf(seq, "network not running\n"); | |
4544 | return 0; | |
4545 | } | |
4546 | ||
bea3348e | 4547 | napi_disable(&hw->napi); |
3cf26753 SH |
4548 | last = sky2_read16(hw, STAT_PUT_IDX); |
4549 | ||
efe91932 | 4550 | seq_printf(seq, "Status ring %u\n", hw->st_size); |
3cf26753 SH |
4551 | if (hw->st_idx == last) |
4552 | seq_puts(seq, "Status ring (empty)\n"); | |
4553 | else { | |
4554 | seq_puts(seq, "Status ring\n"); | |
efe91932 | 4555 | for (idx = hw->st_idx; idx != last && idx < hw->st_size; |
4556 | idx = RING_NEXT(idx, hw->st_size)) { | |
3cf26753 SH |
4557 | const struct sky2_status_le *le = hw->st_le + idx; |
4558 | seq_printf(seq, "[%d] %#x %d %#x\n", | |
4559 | idx, le->opcode, le->length, le->status); | |
4560 | } | |
4561 | seq_puts(seq, "\n"); | |
4562 | } | |
4563 | ||
4564 | seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", | |
4565 | sky2->tx_cons, sky2->tx_prod, | |
4566 | sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
4567 | sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); | |
4568 | ||
4569 | /* Dump contents of tx ring */ | |
4570 | sop = 1; | |
ee5f68fe SH |
4571 | for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; |
4572 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { | |
3cf26753 SH |
4573 | const struct sky2_tx_le *le = sky2->tx_le + idx; |
4574 | u32 a = le32_to_cpu(le->addr); | |
4575 | ||
4576 | if (sop) | |
4577 | seq_printf(seq, "%u:", idx); | |
4578 | sop = 0; | |
4579 | ||
060b946c | 4580 | switch (le->opcode & ~HW_OWNER) { |
3cf26753 SH |
4581 | case OP_ADDR64: |
4582 | seq_printf(seq, " %#x:", a); | |
4583 | break; | |
4584 | case OP_LRGLEN: | |
4585 | seq_printf(seq, " mtu=%d", a); | |
4586 | break; | |
4587 | case OP_VLAN: | |
4588 | seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); | |
4589 | break; | |
4590 | case OP_TCPLISW: | |
4591 | seq_printf(seq, " csum=%#x", a); | |
4592 | break; | |
4593 | case OP_LARGESEND: | |
4594 | seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); | |
4595 | break; | |
4596 | case OP_PACKET: | |
4597 | seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); | |
4598 | break; | |
4599 | case OP_BUFFER: | |
4600 | seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); | |
4601 | break; | |
4602 | default: | |
4603 | seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, | |
4604 | a, le16_to_cpu(le->length)); | |
4605 | } | |
4606 | ||
4607 | if (le->ctrl & EOP) { | |
4608 | seq_putc(seq, '\n'); | |
4609 | sop = 1; | |
4610 | } | |
4611 | } | |
4612 | ||
4613 | seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", | |
4614 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), | |
c409c34b | 4615 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), |
3cf26753 SH |
4616 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); |
4617 | ||
d1d08d12 | 4618 | sky2_read32(hw, B0_Y2_SP_LISR); |
bea3348e | 4619 | napi_enable(&hw->napi); |
3cf26753 SH |
4620 | return 0; |
4621 | } | |
4622 | ||
4623 | static int sky2_debug_open(struct inode *inode, struct file *file) | |
4624 | { | |
4625 | return single_open(file, sky2_debug_show, inode->i_private); | |
4626 | } | |
4627 | ||
4628 | static const struct file_operations sky2_debug_fops = { | |
4629 | .owner = THIS_MODULE, | |
4630 | .open = sky2_debug_open, | |
4631 | .read = seq_read, | |
4632 | .llseek = seq_lseek, | |
4633 | .release = single_release, | |
4634 | }; | |
4635 | ||
4636 | /* | |
4637 | * Use network device events to create/remove/rename | |
4638 | * debugfs file entries | |
4639 | */ | |
4640 | static int sky2_device_event(struct notifier_block *unused, | |
4641 | unsigned long event, void *ptr) | |
4642 | { | |
4643 | struct net_device *dev = ptr; | |
5b296bc9 | 4644 | struct sky2_port *sky2 = netdev_priv(dev); |
3cf26753 | 4645 | |
926d0977 | 4646 | if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) |
5b296bc9 | 4647 | return NOTIFY_DONE; |
3cf26753 | 4648 | |
060b946c | 4649 | switch (event) { |
5b296bc9 SH |
4650 | case NETDEV_CHANGENAME: |
4651 | if (sky2->debugfs) { | |
4652 | sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, | |
4653 | sky2_debug, dev->name); | |
4654 | } | |
4655 | break; | |
3cf26753 | 4656 | |
5b296bc9 SH |
4657 | case NETDEV_GOING_DOWN: |
4658 | if (sky2->debugfs) { | |
ada1db5c | 4659 | netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); |
5b296bc9 SH |
4660 | debugfs_remove(sky2->debugfs); |
4661 | sky2->debugfs = NULL; | |
3cf26753 | 4662 | } |
5b296bc9 SH |
4663 | break; |
4664 | ||
4665 | case NETDEV_UP: | |
4666 | sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, | |
4667 | sky2_debug, dev, | |
4668 | &sky2_debug_fops); | |
4669 | if (IS_ERR(sky2->debugfs)) | |
4670 | sky2->debugfs = NULL; | |
3cf26753 SH |
4671 | } |
4672 | ||
4673 | return NOTIFY_DONE; | |
4674 | } | |
4675 | ||
4676 | static struct notifier_block sky2_notifier = { | |
4677 | .notifier_call = sky2_device_event, | |
4678 | }; | |
4679 | ||
4680 | ||
4681 | static __init void sky2_debug_init(void) | |
4682 | { | |
4683 | struct dentry *ent; | |
4684 | ||
4685 | ent = debugfs_create_dir("sky2", NULL); | |
4686 | if (!ent || IS_ERR(ent)) | |
4687 | return; | |
4688 | ||
4689 | sky2_debug = ent; | |
4690 | register_netdevice_notifier(&sky2_notifier); | |
4691 | } | |
4692 | ||
4693 | static __exit void sky2_debug_cleanup(void) | |
4694 | { | |
4695 | if (sky2_debug) { | |
4696 | unregister_netdevice_notifier(&sky2_notifier); | |
4697 | debugfs_remove(sky2_debug); | |
4698 | sky2_debug = NULL; | |
4699 | } | |
4700 | } | |
4701 | ||
4702 | #else | |
4703 | #define sky2_debug_init() | |
4704 | #define sky2_debug_cleanup() | |
4705 | #endif | |
4706 | ||
1436b301 SH |
4707 | /* Two copies of network device operations to handle special case of |
4708 | not allowing netpoll on second port */ | |
4709 | static const struct net_device_ops sky2_netdev_ops[2] = { | |
4710 | { | |
926d0977 | 4711 | .ndo_open = sky2_open, |
4712 | .ndo_stop = sky2_close, | |
00829823 | 4713 | .ndo_start_xmit = sky2_xmit_frame, |
1436b301 SH |
4714 | .ndo_do_ioctl = sky2_ioctl, |
4715 | .ndo_validate_addr = eth_validate_addr, | |
4716 | .ndo_set_mac_address = sky2_set_mac_address, | |
afc4b13d | 4717 | .ndo_set_rx_mode = sky2_set_multicast, |
1436b301 | 4718 | .ndo_change_mtu = sky2_change_mtu, |
f5d64037 MM |
4719 | .ndo_fix_features = sky2_fix_features, |
4720 | .ndo_set_features = sky2_set_features, | |
1436b301 | 4721 | .ndo_tx_timeout = sky2_tx_timeout, |
0885a30b | 4722 | .ndo_get_stats64 = sky2_get_stats, |
1436b301 SH |
4723 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4724 | .ndo_poll_controller = sky2_netpoll, | |
4725 | #endif | |
4726 | }, | |
4727 | { | |
926d0977 | 4728 | .ndo_open = sky2_open, |
4729 | .ndo_stop = sky2_close, | |
00829823 | 4730 | .ndo_start_xmit = sky2_xmit_frame, |
1436b301 SH |
4731 | .ndo_do_ioctl = sky2_ioctl, |
4732 | .ndo_validate_addr = eth_validate_addr, | |
4733 | .ndo_set_mac_address = sky2_set_mac_address, | |
afc4b13d | 4734 | .ndo_set_rx_mode = sky2_set_multicast, |
1436b301 | 4735 | .ndo_change_mtu = sky2_change_mtu, |
f5d64037 MM |
4736 | .ndo_fix_features = sky2_fix_features, |
4737 | .ndo_set_features = sky2_set_features, | |
1436b301 | 4738 | .ndo_tx_timeout = sky2_tx_timeout, |
0885a30b | 4739 | .ndo_get_stats64 = sky2_get_stats, |
1436b301 SH |
4740 | }, |
4741 | }; | |
3cf26753 | 4742 | |
cd28ab6a | 4743 | /* Initialize network device */ |
1dd06ae8 GKH |
4744 | static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, |
4745 | int highmem, int wol) | |
cd28ab6a SH |
4746 | { |
4747 | struct sky2_port *sky2; | |
4748 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
4749 | ||
41de8d4c | 4750 | if (!dev) |
cd28ab6a | 4751 | return NULL; |
cd28ab6a | 4752 | |
cd28ab6a | 4753 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
ef743d33 | 4754 | dev->irq = hw->pdev->irq; |
cd28ab6a | 4755 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); |
cd28ab6a | 4756 | dev->watchdog_timeo = TX_WATCHDOG; |
1436b301 | 4757 | dev->netdev_ops = &sky2_netdev_ops[port]; |
cd28ab6a SH |
4758 | |
4759 | sky2 = netdev_priv(dev); | |
4760 | sky2->netdev = dev; | |
4761 | sky2->hw = hw; | |
4762 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
4763 | ||
cd28ab6a | 4764 | /* Auto speed and flow control */ |
0ea065e5 SH |
4765 | sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; |
4766 | if (hw->chip_id != CHIP_ID_YUKON_XL) | |
f5d64037 | 4767 | dev->hw_features |= NETIF_F_RXCSUM; |
0ea065e5 | 4768 | |
16ad91e1 SH |
4769 | sky2->flow_mode = FC_BOTH; |
4770 | ||
cd28ab6a SH |
4771 | sky2->duplex = -1; |
4772 | sky2->speed = -1; | |
4773 | sky2->advertising = sky2_supported_modes(hw); | |
be63a21c | 4774 | sky2->wol = wol; |
75d070c5 | 4775 | |
e07b1aa8 | 4776 | spin_lock_init(&sky2->phy_lock); |
ee5f68fe | 4777 | |
793b883e | 4778 | sky2->tx_pending = TX_DEF_PENDING; |
738a849c | 4779 | sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); |
290d4de5 | 4780 | sky2->rx_pending = RX_DEF_PENDING; |
cd28ab6a SH |
4781 | |
4782 | hw->dev[port] = dev; | |
4783 | ||
4784 | sky2->port = port; | |
4785 | ||
f5d64037 | 4786 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; |
86aa7785 | 4787 | |
cd28ab6a SH |
4788 | if (highmem) |
4789 | dev->features |= NETIF_F_HIGHDMA; | |
cd28ab6a | 4790 | |
bf73130d SH |
4791 | /* Enable receive hashing unless hardware is known broken */ |
4792 | if (!(hw->flags & SKY2_HW_RSS_BROKEN)) | |
f5d64037 MM |
4793 | dev->hw_features |= NETIF_F_RXHASH; |
4794 | ||
4795 | if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { | |
4796 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
4797 | dev->vlan_features |= SKY2_VLAN_OFFLOADS; | |
4798 | } | |
bf73130d | 4799 | |
f5d64037 | 4800 | dev->features |= dev->hw_features; |
d1f13708 | 4801 | |
cd28ab6a | 4802 | /* read the mac address */ |
793b883e | 4803 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
cd28ab6a | 4804 | |
cd28ab6a SH |
4805 | return dev; |
4806 | } | |
4807 | ||
853e3f4c | 4808 | static void sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
4809 | { |
4810 | const struct sky2_port *sky2 = netdev_priv(dev); | |
4811 | ||
6c35abae | 4812 | netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); |
cd28ab6a SH |
4813 | } |
4814 | ||
fb2690a9 | 4815 | /* Handle software interrupt used during MSI test */ |
853e3f4c | 4816 | static irqreturn_t sky2_test_intr(int irq, void *dev_id) |
fb2690a9 SH |
4817 | { |
4818 | struct sky2_hw *hw = dev_id; | |
4819 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
4820 | ||
4821 | if (status == 0) | |
4822 | return IRQ_NONE; | |
4823 | ||
4824 | if (status & Y2_IS_IRQ_SW) { | |
ea76e635 | 4825 | hw->flags |= SKY2_HW_USE_MSI; |
fb2690a9 SH |
4826 | wake_up(&hw->msi_wait); |
4827 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4828 | } | |
4829 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
4830 | ||
4831 | return IRQ_HANDLED; | |
4832 | } | |
4833 | ||
4834 | /* Test interrupt path by forcing a a software IRQ */ | |
853e3f4c | 4835 | static int sky2_test_msi(struct sky2_hw *hw) |
fb2690a9 SH |
4836 | { |
4837 | struct pci_dev *pdev = hw->pdev; | |
4838 | int err; | |
4839 | ||
060b946c | 4840 | init_waitqueue_head(&hw->msi_wait); |
bb507fe1 | 4841 | |
b0a20ded | 4842 | err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); |
fb2690a9 | 4843 | if (err) { |
b02a9258 | 4844 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
fb2690a9 SH |
4845 | return err; |
4846 | } | |
4847 | ||
ede7193d LS |
4848 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
4849 | ||
fb2690a9 | 4850 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
bb507fe1 | 4851 | sky2_read8(hw, B0_CTST); |
fb2690a9 | 4852 | |
ea76e635 | 4853 | wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); |
fb2690a9 | 4854 | |
ea76e635 | 4855 | if (!(hw->flags & SKY2_HW_USE_MSI)) { |
fb2690a9 | 4856 | /* MSI test failed, go back to INTx mode */ |
b02a9258 SH |
4857 | dev_info(&pdev->dev, "No interrupt generated using MSI, " |
4858 | "switching to INTx mode.\n"); | |
fb2690a9 SH |
4859 | |
4860 | err = -EOPNOTSUPP; | |
4861 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4862 | } | |
4863 | ||
4864 | sky2_write32(hw, B0_IMSK, 0); | |
2bffc23a | 4865 | sky2_read32(hw, B0_IMSK); |
fb2690a9 SH |
4866 | |
4867 | free_irq(pdev->irq, hw); | |
4868 | ||
4869 | return err; | |
4870 | } | |
4871 | ||
c7127a34 SH |
4872 | /* This driver supports yukon2 chipset only */ |
4873 | static const char *sky2_name(u8 chipid, char *buf, int sz) | |
4874 | { | |
4875 | const char *name[] = { | |
4876 | "XL", /* 0xb3 */ | |
4877 | "EC Ultra", /* 0xb4 */ | |
4878 | "Extreme", /* 0xb5 */ | |
4879 | "EC", /* 0xb6 */ | |
4880 | "FE", /* 0xb7 */ | |
4881 | "FE+", /* 0xb8 */ | |
4882 | "Supreme", /* 0xb9 */ | |
0ce8b98d | 4883 | "UL 2", /* 0xba */ |
0f5aac70 SH |
4884 | "Unknown", /* 0xbb */ |
4885 | "Optima", /* 0xbc */ | |
0e767324 | 4886 | "OptimaEEE", /* 0xbd */ |
4fb99cd6 | 4887 | "Optima 2", /* 0xbe */ |
c7127a34 SH |
4888 | }; |
4889 | ||
4fb99cd6 | 4890 | if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) |
c7127a34 SH |
4891 | strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); |
4892 | else | |
4893 | snprintf(buf, sz, "(chip %#x)", chipid); | |
4894 | return buf; | |
4895 | } | |
4896 | ||
1dd06ae8 | 4897 | static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
cd28ab6a | 4898 | { |
0bdb0bd0 | 4899 | struct net_device *dev, *dev1; |
cd28ab6a | 4900 | struct sky2_hw *hw; |
be63a21c | 4901 | int err, using_dac = 0, wol_default; |
3834507d | 4902 | u32 reg; |
c7127a34 | 4903 | char buf1[16]; |
cd28ab6a | 4904 | |
793b883e SH |
4905 | err = pci_enable_device(pdev); |
4906 | if (err) { | |
b02a9258 | 4907 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
cd28ab6a SH |
4908 | goto err_out; |
4909 | } | |
4910 | ||
6cc90a5a SH |
4911 | /* Get configuration information |
4912 | * Note: only regular PCI config access once to test for HW issues | |
4913 | * other PCI access through shared memory for speed and to | |
4914 | * avoid MMCONFIG problems. | |
4915 | */ | |
4916 | err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
4917 | if (err) { | |
4918 | dev_err(&pdev->dev, "PCI read config failed\n"); | |
1c85382e | 4919 | goto err_out_disable; |
6cc90a5a SH |
4920 | } |
4921 | ||
4922 | if (~reg == 0) { | |
4923 | dev_err(&pdev->dev, "PCI configuration read error\n"); | |
0bd8ba18 | 4924 | err = -EIO; |
1c85382e | 4925 | goto err_out_disable; |
6cc90a5a SH |
4926 | } |
4927 | ||
793b883e SH |
4928 | err = pci_request_regions(pdev, DRV_NAME); |
4929 | if (err) { | |
b02a9258 | 4930 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
44a1d2e5 | 4931 | goto err_out_disable; |
cd28ab6a SH |
4932 | } |
4933 | ||
4934 | pci_set_master(pdev); | |
4935 | ||
d1f3d4dd | 4936 | if (sizeof(dma_addr_t) > sizeof(u32) && |
6a35528a | 4937 | !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { |
d1f3d4dd | 4938 | using_dac = 1; |
6a35528a | 4939 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
d1f3d4dd | 4940 | if (err < 0) { |
b02a9258 SH |
4941 | dev_err(&pdev->dev, "unable to obtain 64 bit DMA " |
4942 | "for consistent allocations\n"); | |
d1f3d4dd SH |
4943 | goto err_out_free_regions; |
4944 | } | |
d1f3d4dd | 4945 | } else { |
284901a9 | 4946 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cd28ab6a | 4947 | if (err) { |
b02a9258 | 4948 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
cd28ab6a SH |
4949 | goto err_out_free_regions; |
4950 | } | |
4951 | } | |
d1f3d4dd | 4952 | |
3834507d SH |
4953 | |
4954 | #ifdef __BIG_ENDIAN | |
4955 | /* The sk98lin vendor driver uses hardware byte swapping but | |
4956 | * this driver uses software swapping. | |
4957 | */ | |
4958 | reg &= ~PCI_REV_DESC; | |
060b946c | 4959 | err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); |
3834507d SH |
4960 | if (err) { |
4961 | dev_err(&pdev->dev, "PCI write config failed\n"); | |
4962 | goto err_out_free_regions; | |
4963 | } | |
4964 | #endif | |
4965 | ||
9d731d77 | 4966 | wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; |
be63a21c | 4967 | |
cd28ab6a | 4968 | err = -ENOMEM; |
66466797 SH |
4969 | |
4970 | hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") | |
4971 | + strlen(pci_name(pdev)) + 1, GFP_KERNEL); | |
b2adaca9 | 4972 | if (!hw) |
cd28ab6a | 4973 | goto err_out_free_regions; |
cd28ab6a | 4974 | |
cd28ab6a | 4975 | hw->pdev = pdev; |
66466797 | 4976 | sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); |
cd28ab6a SH |
4977 | |
4978 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
4979 | if (!hw->regs) { | |
b02a9258 | 4980 | dev_err(&pdev->dev, "cannot map device registers\n"); |
cd28ab6a SH |
4981 | goto err_out_free_hw; |
4982 | } | |
4983 | ||
e3173832 | 4984 | err = sky2_init(hw); |
cd28ab6a | 4985 | if (err) |
793b883e | 4986 | goto err_out_iounmap; |
cd28ab6a | 4987 | |
efe91932 | 4988 | /* ring for status responses */ |
bf73130d | 4989 | hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); |
efe91932 | 4990 | hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
4991 | &hw->st_dma); | |
0bd8ba18 PST |
4992 | if (!hw->st_le) { |
4993 | err = -ENOMEM; | |
efe91932 | 4994 | goto err_out_reset; |
0bd8ba18 | 4995 | } |
efe91932 | 4996 | |
c844d483 SH |
4997 | dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", |
4998 | sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); | |
cd28ab6a | 4999 | |
e3173832 SH |
5000 | sky2_reset(hw); |
5001 | ||
be63a21c | 5002 | dev = sky2_init_netdev(hw, 0, using_dac, wol_default); |
7f60c64b | 5003 | if (!dev) { |
5004 | err = -ENOMEM; | |
cd28ab6a | 5005 | goto err_out_free_pci; |
7f60c64b | 5006 | } |
cd28ab6a | 5007 | |
9fa1b1f3 SH |
5008 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
5009 | err = sky2_test_msi(hw); | |
1c85382e | 5010 | if (err) { |
9fa1b1f3 | 5011 | pci_disable_msi(pdev); |
1c85382e LS |
5012 | if (err != -EOPNOTSUPP) |
5013 | goto err_out_free_netdev; | |
5014 | } | |
9fa1b1f3 SH |
5015 | } |
5016 | ||
793b883e SH |
5017 | err = register_netdev(dev); |
5018 | if (err) { | |
b02a9258 | 5019 | dev_err(&pdev->dev, "cannot register net device\n"); |
cd28ab6a SH |
5020 | goto err_out_free_netdev; |
5021 | } | |
5022 | ||
33cb7d33 BP |
5023 | netif_carrier_off(dev); |
5024 | ||
6de16237 SH |
5025 | netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); |
5026 | ||
cd28ab6a SH |
5027 | sky2_show_addr(dev); |
5028 | ||
7f60c64b | 5029 | if (hw->ports > 1) { |
be63a21c | 5030 | dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); |
0bdb0bd0 | 5031 | if (!dev1) { |
5032 | err = -ENOMEM; | |
5033 | goto err_out_unregister; | |
ca519274 | 5034 | } |
0bdb0bd0 | 5035 | |
5036 | err = register_netdev(dev1); | |
5037 | if (err) { | |
5038 | dev_err(&pdev->dev, "cannot register second net device\n"); | |
5039 | goto err_out_free_dev1; | |
5040 | } | |
5041 | ||
5042 | err = sky2_setup_irq(hw, hw->irq_name); | |
5043 | if (err) | |
5044 | goto err_out_unregister_dev1; | |
5045 | ||
5046 | sky2_show_addr(dev1); | |
cd28ab6a SH |
5047 | } |
5048 | ||
32c2c300 | 5049 | setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); |
81906791 SH |
5050 | INIT_WORK(&hw->restart_work, sky2_restart); |
5051 | ||
793b883e | 5052 | pci_set_drvdata(pdev, hw); |
1ae861e6 | 5053 | pdev->d3_delay = 150; |
793b883e | 5054 | |
cd28ab6a SH |
5055 | return 0; |
5056 | ||
0bdb0bd0 | 5057 | err_out_unregister_dev1: |
5058 | unregister_netdev(dev1); | |
5059 | err_out_free_dev1: | |
5060 | free_netdev(dev1); | |
793b883e | 5061 | err_out_unregister: |
793b883e | 5062 | unregister_netdev(dev); |
cd28ab6a | 5063 | err_out_free_netdev: |
1c85382e LS |
5064 | if (hw->flags & SKY2_HW_USE_MSI) |
5065 | pci_disable_msi(pdev); | |
cd28ab6a | 5066 | free_netdev(dev); |
cd28ab6a | 5067 | err_out_free_pci: |
efe91932 | 5068 | pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
5069 | hw->st_le, hw->st_dma); | |
5070 | err_out_reset: | |
793b883e | 5071 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
5072 | err_out_iounmap: |
5073 | iounmap(hw->regs); | |
5074 | err_out_free_hw: | |
5075 | kfree(hw); | |
5076 | err_out_free_regions: | |
5077 | pci_release_regions(pdev); | |
44a1d2e5 | 5078 | err_out_disable: |
cd28ab6a | 5079 | pci_disable_device(pdev); |
cd28ab6a | 5080 | err_out: |
549a68c3 | 5081 | pci_set_drvdata(pdev, NULL); |
cd28ab6a SH |
5082 | return err; |
5083 | } | |
5084 | ||
853e3f4c | 5085 | static void sky2_remove(struct pci_dev *pdev) |
cd28ab6a | 5086 | { |
793b883e | 5087 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
6de16237 | 5088 | int i; |
cd28ab6a | 5089 | |
793b883e | 5090 | if (!hw) |
cd28ab6a SH |
5091 | return; |
5092 | ||
32c2c300 | 5093 | del_timer_sync(&hw->watchdog_timer); |
6de16237 | 5094 | cancel_work_sync(&hw->restart_work); |
d27ed387 | 5095 | |
b877fe28 | 5096 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 | 5097 | unregister_netdev(hw->dev[i]); |
81906791 | 5098 | |
d27ed387 | 5099 | sky2_write32(hw, B0_IMSK, 0); |
0bdb0bd0 | 5100 | sky2_read32(hw, B0_IMSK); |
cd28ab6a | 5101 | |
ae306cca SH |
5102 | sky2_power_aux(hw); |
5103 | ||
793b883e | 5104 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 5105 | sky2_read8(hw, B0_CTST); |
cd28ab6a | 5106 | |
0bdb0bd0 | 5107 | if (hw->ports > 1) { |
5108 | napi_disable(&hw->napi); | |
5109 | free_irq(pdev->irq, hw); | |
5110 | } | |
5111 | ||
ea76e635 | 5112 | if (hw->flags & SKY2_HW_USE_MSI) |
b0a20ded | 5113 | pci_disable_msi(pdev); |
efe91932 | 5114 | pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
5115 | hw->st_le, hw->st_dma); | |
cd28ab6a SH |
5116 | pci_release_regions(pdev); |
5117 | pci_disable_device(pdev); | |
793b883e | 5118 | |
b877fe28 | 5119 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 SH |
5120 | free_netdev(hw->dev[i]); |
5121 | ||
cd28ab6a SH |
5122 | iounmap(hw->regs); |
5123 | kfree(hw); | |
5afa0a9c | 5124 | |
cd28ab6a SH |
5125 | pci_set_drvdata(pdev, NULL); |
5126 | } | |
5127 | ||
0f333d10 | 5128 | static int sky2_suspend(struct device *dev) |
cd28ab6a | 5129 | { |
0f333d10 | 5130 | struct pci_dev *pdev = to_pci_dev(dev); |
793b883e | 5131 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
0f333d10 | 5132 | int i; |
cd28ab6a | 5133 | |
549a68c3 SH |
5134 | if (!hw) |
5135 | return 0; | |
5136 | ||
063a0b38 SH |
5137 | del_timer_sync(&hw->watchdog_timer); |
5138 | cancel_work_sync(&hw->restart_work); | |
5139 | ||
19720737 | 5140 | rtnl_lock(); |
3403aca2 MM |
5141 | |
5142 | sky2_all_down(hw); | |
f05267e7 | 5143 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a | 5144 | struct net_device *dev = hw->dev[i]; |
e3173832 | 5145 | struct sky2_port *sky2 = netdev_priv(dev); |
cd28ab6a | 5146 | |
e3173832 SH |
5147 | if (sky2->wol) |
5148 | sky2_wol_init(sky2); | |
cd28ab6a SH |
5149 | } |
5150 | ||
ae306cca | 5151 | sky2_power_aux(hw); |
19720737 | 5152 | rtnl_unlock(); |
e3173832 | 5153 | |
2ccc99b7 | 5154 | return 0; |
cd28ab6a SH |
5155 | } |
5156 | ||
94252763 | 5157 | #ifdef CONFIG_PM_SLEEP |
0f333d10 | 5158 | static int sky2_resume(struct device *dev) |
cd28ab6a | 5159 | { |
0f333d10 | 5160 | struct pci_dev *pdev = to_pci_dev(dev); |
793b883e | 5161 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
3403aca2 | 5162 | int err; |
cd28ab6a | 5163 | |
549a68c3 SH |
5164 | if (!hw) |
5165 | return 0; | |
5166 | ||
1ad5b4a5 | 5167 | /* Re-enable all clocks */ |
a0db28b8 | 5168 | err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); |
5169 | if (err) { | |
5170 | dev_err(&pdev->dev, "PCI write config failed\n"); | |
5171 | goto out; | |
5172 | } | |
1ad5b4a5 | 5173 | |
3403aca2 | 5174 | rtnl_lock(); |
e3173832 | 5175 | sky2_reset(hw); |
3403aca2 | 5176 | sky2_all_up(hw); |
af18d8b8 | 5177 | rtnl_unlock(); |
eb35cf60 | 5178 | |
ae306cca | 5179 | return 0; |
08c06d8a | 5180 | out: |
af18d8b8 | 5181 | |
b02a9258 | 5182 | dev_err(&pdev->dev, "resume failed (%d)\n", err); |
ae306cca | 5183 | pci_disable_device(pdev); |
08c06d8a | 5184 | return err; |
cd28ab6a | 5185 | } |
0f333d10 RW |
5186 | |
5187 | static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); | |
5188 | #define SKY2_PM_OPS (&sky2_pm_ops) | |
5189 | ||
5190 | #else | |
5191 | ||
5192 | #define SKY2_PM_OPS NULL | |
cd28ab6a SH |
5193 | #endif |
5194 | ||
e3173832 SH |
5195 | static void sky2_shutdown(struct pci_dev *pdev) |
5196 | { | |
0f333d10 RW |
5197 | sky2_suspend(&pdev->dev); |
5198 | pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); | |
5199 | pci_set_power_state(pdev, PCI_D3hot); | |
e3173832 SH |
5200 | } |
5201 | ||
cd28ab6a | 5202 | static struct pci_driver sky2_driver = { |
793b883e SH |
5203 | .name = DRV_NAME, |
5204 | .id_table = sky2_id_table, | |
5205 | .probe = sky2_probe, | |
853e3f4c | 5206 | .remove = sky2_remove, |
e3173832 | 5207 | .shutdown = sky2_shutdown, |
0f333d10 | 5208 | .driver.pm = SKY2_PM_OPS, |
cd28ab6a SH |
5209 | }; |
5210 | ||
5211 | static int __init sky2_init_module(void) | |
5212 | { | |
ada1db5c | 5213 | pr_info("driver version " DRV_VERSION "\n"); |
c844d483 | 5214 | |
3cf26753 | 5215 | sky2_debug_init(); |
50241c4c | 5216 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
5217 | } |
5218 | ||
5219 | static void __exit sky2_cleanup_module(void) | |
5220 | { | |
5221 | pci_unregister_driver(&sky2_driver); | |
3cf26753 | 5222 | sky2_debug_cleanup(); |
cd28ab6a SH |
5223 | } |
5224 | ||
5225 | module_init(sky2_init_module); | |
5226 | module_exit(sky2_cleanup_module); | |
5227 | ||
5228 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
65ebe634 | 5229 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
cd28ab6a | 5230 | MODULE_LICENSE("GPL"); |
5f4f9dc1 | 5231 | MODULE_VERSION(DRV_VERSION); |