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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
798b6b19 | 13 | * the Free Software Foundation; either version 2 of the License. |
cd28ab6a SH |
14 | * |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
18 | * GNU General Public License for more details. |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
ada1db5c JP |
25 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
26 | ||
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a | 28 | #include <linux/kernel.h> |
cd28ab6a SH |
29 | #include <linux/module.h> |
30 | #include <linux/netdevice.h> | |
d0bbccfa | 31 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
32 | #include <linux/etherdevice.h> |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/pci.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
cd28ab6a | 36 | #include <linux/ip.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c9bdd4b5 | 38 | #include <net/ip.h> |
cd28ab6a SH |
39 | #include <linux/tcp.h> |
40 | #include <linux/in.h> | |
41 | #include <linux/delay.h> | |
91c86df5 | 42 | #include <linux/workqueue.h> |
d1f13708 | 43 | #include <linux/if_vlan.h> |
d70cd51a | 44 | #include <linux/prefetch.h> |
3cf26753 | 45 | #include <linux/debugfs.h> |
ef743d33 | 46 | #include <linux/mii.h> |
3ee2f8ce TH |
47 | #include <linux/of_device.h> |
48 | #include <linux/of_net.h> | |
cd28ab6a SH |
49 | |
50 | #include <asm/irq.h> | |
51 | ||
52 | #include "sky2.h" | |
53 | ||
54 | #define DRV_NAME "sky2" | |
d9fa7c86 | 55 | #define DRV_VERSION "1.30" |
cd28ab6a SH |
56 | |
57 | /* | |
58 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
59 | * that are organized into three (receive, transmit, status) different rings | |
14d0263f | 60 | * similar to Tigon3. |
cd28ab6a SH |
61 | */ |
62 | ||
14d0263f | 63 | #define RX_LE_SIZE 1024 |
cd28ab6a | 64 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
14d0263f | 65 | #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) |
13210ce5 | 66 | #define RX_DEF_PENDING RX_MAX_PENDING |
793b883e | 67 | |
ee5f68fe | 68 | /* This is the worst case number of transmit list elements for a single skb: |
07e31637 SH |
69 | VLAN:GSO + CKSUM + Data + skb_frags * DMA */ |
70 | #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) | |
e9c1be80 | 71 | #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) |
efe91932 | 72 | #define TX_MAX_PENDING 1024 |
b1cb8256 | 73 | #define TX_DEF_PENDING 63 |
cd28ab6a | 74 | |
cd28ab6a SH |
75 | #define TX_WATCHDOG (5 * HZ) |
76 | #define NAPI_WEIGHT 64 | |
77 | #define PHY_RETRIES 1000 | |
78 | ||
f4331a6d SH |
79 | #define SKY2_EEPROM_MAGIC 0x9955aabb |
80 | ||
060b946c | 81 | #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) |
cb5d9547 | 82 | |
cd28ab6a | 83 | static const u32 default_msg = |
793b883e SH |
84 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
85 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 86 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 87 | |
793b883e | 88 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
89 | module_param(debug, int, 0); |
90 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
91 | ||
14d0263f | 92 | static int copybreak __read_mostly = 128; |
bdb5c58e SH |
93 | module_param(copybreak, int, 0); |
94 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
95 | ||
fb2690a9 SH |
96 | static int disable_msi = 0; |
97 | module_param(disable_msi, int, 0); | |
98 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
99 | ||
5676cc7b | 100 | static int legacy_pme = 0; |
101 | module_param(legacy_pme, int, 0); | |
102 | MODULE_PARM_DESC(legacy_pme, "Legacy power management"); | |
103 | ||
9baa3c34 | 104 | static const struct pci_device_id sky2_id_table[] = { |
e5b74c7d SH |
105 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ |
106 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ | |
e30a4ac2 | 107 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ |
2d2a3871 | 108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
2f4a66ad | 109 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ |
508f89e7 | 110 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ |
f1a0b6f5 | 111 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ |
e5b74c7d SH |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ | |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ | |
122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ | |
123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ | |
05745c4a | 124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ |
a3b4fced | 125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ |
e5b74c7d | 126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ |
5a37a68d | 127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ |
05745c4a | 128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ |
e5b74c7d SH |
129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ |
130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ | |
131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ | |
132 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ | |
133 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ | |
05745c4a | 134 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ |
e5b74c7d SH |
135 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ |
136 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ | |
137 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ | |
f1a0b6f5 SH |
138 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ |
139 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ | |
69161611 | 140 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ |
5a37a68d | 141 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ |
ed4d4161 SH |
142 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ |
143 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ | |
0ce8b98d | 144 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ |
0f5aac70 | 145 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ |
0e767324 | 146 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */ |
cd28ab6a SH |
147 | { 0 } |
148 | }; | |
793b883e | 149 | |
cd28ab6a SH |
150 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
151 | ||
152 | /* Avoid conditionals by using array */ | |
153 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
154 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
f4ea431b | 155 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
cd28ab6a | 156 | |
d1b139c0 | 157 | static void sky2_set_multicast(struct net_device *dev); |
0bdb0bd0 | 158 | static irqreturn_t sky2_intr(int irq, void *dev_id); |
d1b139c0 | 159 | |
af043aa5 | 160 | /* Access to PHY via serial interconnect */ |
ef743d33 | 161 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
162 | { |
163 | int i; | |
164 | ||
165 | gma_write16(hw, port, GM_SMI_DATA, val); | |
166 | gma_write16(hw, port, GM_SMI_CTRL, | |
167 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
168 | ||
169 | for (i = 0; i < PHY_RETRIES; i++) { | |
af043aa5 SH |
170 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
171 | if (ctrl == 0xffff) | |
172 | goto io_error; | |
173 | ||
174 | if (!(ctrl & GM_SMI_CT_BUSY)) | |
ef743d33 | 175 | return 0; |
af043aa5 SH |
176 | |
177 | udelay(10); | |
cd28ab6a | 178 | } |
ef743d33 | 179 | |
060b946c | 180 | dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 181 | return -ETIMEDOUT; |
af043aa5 SH |
182 | |
183 | io_error: | |
184 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); | |
185 | return -EIO; | |
cd28ab6a SH |
186 | } |
187 | ||
ef743d33 | 188 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
189 | { |
190 | int i; | |
191 | ||
793b883e | 192 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
193 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
194 | ||
195 | for (i = 0; i < PHY_RETRIES; i++) { | |
af043aa5 SH |
196 | u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); |
197 | if (ctrl == 0xffff) | |
198 | goto io_error; | |
199 | ||
200 | if (ctrl & GM_SMI_CT_RD_VAL) { | |
ef743d33 SH |
201 | *val = gma_read16(hw, port, GM_SMI_DATA); |
202 | return 0; | |
203 | } | |
204 | ||
af043aa5 | 205 | udelay(10); |
cd28ab6a SH |
206 | } |
207 | ||
af043aa5 | 208 | dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); |
ef743d33 | 209 | return -ETIMEDOUT; |
af043aa5 SH |
210 | io_error: |
211 | dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); | |
212 | return -EIO; | |
ef743d33 SH |
213 | } |
214 | ||
af043aa5 | 215 | static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) |
ef743d33 SH |
216 | { |
217 | u16 v; | |
af043aa5 | 218 | __gm_phy_read(hw, port, reg, &v); |
ef743d33 | 219 | return v; |
cd28ab6a SH |
220 | } |
221 | ||
5afa0a9c | 222 | |
ae306cca SH |
223 | static void sky2_power_on(struct sky2_hw *hw) |
224 | { | |
225 | /* switch power to VCC (WA for VAUX problem) */ | |
226 | sky2_write8(hw, B0_POWER_CTRL, | |
227 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
5afa0a9c | 228 | |
ae306cca SH |
229 | /* disable Core Clock Division, */ |
230 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
d3bcfbeb | 231 | |
4b7c47aa | 232 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ae306cca SH |
233 | /* enable bits are inverted */ |
234 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
235 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
236 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
237 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
238 | else | |
239 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
977bdf06 | 240 | |
ea76e635 | 241 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
fc99fe06 | 242 | u32 reg; |
5afa0a9c | 243 | |
b32f40c4 | 244 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
b2345773 | 245 | |
b32f40c4 | 246 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); |
fc99fe06 SH |
247 | /* set all bits to 0 except bits 15..12 and 8 */ |
248 | reg &= P_ASPM_CONTROL_MSK; | |
b32f40c4 | 249 | sky2_pci_write32(hw, PCI_DEV_REG4, reg); |
fc99fe06 | 250 | |
b32f40c4 | 251 | reg = sky2_pci_read32(hw, PCI_DEV_REG5); |
fc99fe06 SH |
252 | /* set all bits to 0 except bits 28 & 27 */ |
253 | reg &= P_CTL_TIM_VMAIN_AV_MSK; | |
b32f40c4 | 254 | sky2_pci_write32(hw, PCI_DEV_REG5, reg); |
fc99fe06 | 255 | |
b32f40c4 | 256 | sky2_pci_write32(hw, PCI_CFG_REG_1, 0); |
8f70920f | 257 | |
5f8ae5c5 | 258 | sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); |
259 | ||
8f70920f SH |
260 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ |
261 | reg = sky2_read32(hw, B2_GP_IO); | |
262 | reg |= GLB_GPIO_STAT_RACE_DIS; | |
263 | sky2_write32(hw, B2_GP_IO, reg); | |
b2345773 SH |
264 | |
265 | sky2_read32(hw, B2_GP_IO); | |
5afa0a9c | 266 | } |
10547ae2 SH |
267 | |
268 | /* Turn on "driver loaded" LED */ | |
269 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); | |
ae306cca | 270 | } |
5afa0a9c | 271 | |
ae306cca SH |
272 | static void sky2_power_aux(struct sky2_hw *hw) |
273 | { | |
4b7c47aa | 274 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ae306cca SH |
275 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
276 | else | |
277 | /* enable bits are inverted */ | |
278 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
279 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
280 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
281 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
282 | ||
c23ddf8f SH |
283 | /* switch power to VAUX if supported and PME from D3cold */ |
284 | if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && | |
285 | pci_pme_capable(hw->pdev, PCI_D3cold)) | |
ae306cca SH |
286 | sky2_write8(hw, B0_POWER_CTRL, |
287 | (PC_VAUX_ENA | PC_VCC_ENA | | |
288 | PC_VAUX_ON | PC_VCC_OFF)); | |
10547ae2 SH |
289 | |
290 | /* turn off "driver loaded LED" */ | |
291 | sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); | |
5afa0a9c SH |
292 | } |
293 | ||
d3bcfbeb | 294 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
cd28ab6a SH |
295 | { |
296 | u16 reg; | |
297 | ||
298 | /* disable all GMAC IRQ's */ | |
299 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
793b883e | 300 | |
cd28ab6a SH |
301 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
302 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
303 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
304 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
305 | ||
306 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
307 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
308 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
309 | } | |
310 | ||
16ad91e1 SH |
311 | /* flow control to advertise bits */ |
312 | static const u16 copper_fc_adv[] = { | |
313 | [FC_NONE] = 0, | |
314 | [FC_TX] = PHY_M_AN_ASP, | |
315 | [FC_RX] = PHY_M_AN_PC, | |
316 | [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, | |
317 | }; | |
318 | ||
319 | /* flow control to advertise bits when using 1000BaseX */ | |
320 | static const u16 fiber_fc_adv[] = { | |
df3fe1f3 | 321 | [FC_NONE] = PHY_M_P_NO_PAUSE_X, |
16ad91e1 SH |
322 | [FC_TX] = PHY_M_P_ASYM_MD_X, |
323 | [FC_RX] = PHY_M_P_SYM_MD_X, | |
df3fe1f3 | 324 | [FC_BOTH] = PHY_M_P_BOTH_MD_X, |
16ad91e1 SH |
325 | }; |
326 | ||
327 | /* flow control to GMA disable bits */ | |
328 | static const u16 gm_fc_disable[] = { | |
329 | [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, | |
330 | [FC_TX] = GM_GPCR_FC_RX_DIS, | |
331 | [FC_RX] = GM_GPCR_FC_TX_DIS, | |
332 | [FC_BOTH] = 0, | |
333 | }; | |
334 | ||
335 | ||
cd28ab6a SH |
336 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) |
337 | { | |
338 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
2eaba1a2 | 339 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; |
cd28ab6a | 340 | |
0ea065e5 | 341 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
ea76e635 | 342 | !(hw->flags & SKY2_HW_NEWER_PHY)) { |
cd28ab6a SH |
343 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
344 | ||
345 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 346 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
347 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
348 | ||
53419c68 | 349 | /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ |
cd28ab6a | 350 | if (hw->chip_id == CHIP_ID_YUKON_EC) |
53419c68 | 351 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
352 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; |
353 | else | |
53419c68 SH |
354 | /* set master & slave downshift counter to 1x */ |
355 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); | |
cd28ab6a SH |
356 | |
357 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
358 | } | |
359 | ||
360 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
b89165f2 | 361 | if (sky2_is_copper(hw)) { |
05745c4a | 362 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
cd28ab6a SH |
363 | /* enable automatic crossover */ |
364 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
6d3105d5 SH |
365 | |
366 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
367 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
368 | u16 spec; | |
369 | ||
370 | /* Enable Class A driver for FE+ A0 */ | |
371 | spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); | |
372 | spec |= PHY_M_FESC_SEL_CL_A; | |
373 | gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); | |
374 | } | |
cd28ab6a SH |
375 | } else { |
376 | /* disable energy detect */ | |
377 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
378 | ||
379 | /* enable automatic crossover */ | |
380 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
381 | ||
53419c68 | 382 | /* downshift on PHY 88E1112 and 88E1149 is changed */ |
8e95a202 JP |
383 | if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && |
384 | (hw->flags & SKY2_HW_NEWER_PHY)) { | |
53419c68 | 385 | /* set downshift counter to 3x and enable downshift */ |
cd28ab6a SH |
386 | ctrl &= ~PHY_M_PC_DSC_MSK; |
387 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
388 | } | |
389 | } | |
cd28ab6a SH |
390 | } else { |
391 | /* workaround for deviation #4.88 (CRC errors) */ | |
392 | /* disable Automatic Crossover */ | |
393 | ||
394 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
b89165f2 | 395 | } |
cd28ab6a | 396 | |
b89165f2 SH |
397 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
398 | ||
399 | /* special setup for PHY 88E1112 Fiber */ | |
ea76e635 | 400 | if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { |
b89165f2 | 401 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a | 402 | |
b89165f2 SH |
403 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ |
404 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
405 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
406 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
407 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
408 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
409 | ||
410 | if (hw->pmd_type == 'P') { | |
cd28ab6a SH |
411 | /* select page 1 to access Fiber registers */ |
412 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
b89165f2 SH |
413 | |
414 | /* for SFP-module set SIGDET polarity to low */ | |
415 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
416 | ctrl |= PHY_M_FIB_SIGD_POL; | |
34dd962b | 417 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
cd28ab6a | 418 | } |
b89165f2 SH |
419 | |
420 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
cd28ab6a SH |
421 | } |
422 | ||
7800fddc | 423 | ctrl = PHY_CT_RESET; |
cd28ab6a SH |
424 | ct1000 = 0; |
425 | adv = PHY_AN_CSMA; | |
2eaba1a2 | 426 | reg = 0; |
cd28ab6a | 427 | |
0ea065e5 | 428 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { |
b89165f2 | 429 | if (sky2_is_copper(hw)) { |
cd28ab6a SH |
430 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
431 | ct1000 |= PHY_M_1000C_AFD; | |
432 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
433 | ct1000 |= PHY_M_1000C_AHD; | |
434 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
435 | adv |= PHY_M_AN_100_FD; | |
436 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
437 | adv |= PHY_M_AN_100_HD; | |
438 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
439 | adv |= PHY_M_AN_10_FD; | |
440 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
441 | adv |= PHY_M_AN_10_HD; | |
709c6e7b | 442 | |
b89165f2 SH |
443 | } else { /* special defines for FIBER (88E1040S only) */ |
444 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
445 | adv |= PHY_M_AN_1000X_AFD; | |
446 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
447 | adv |= PHY_M_AN_1000X_AHD; | |
709c6e7b | 448 | } |
cd28ab6a SH |
449 | |
450 | /* Restart Auto-negotiation */ | |
451 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
452 | } else { | |
453 | /* forced speed/duplex settings */ | |
454 | ct1000 = PHY_M_1000C_MSE; | |
455 | ||
0ea065e5 SH |
456 | /* Disable auto update for duplex flow control and duplex */ |
457 | reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; | |
cd28ab6a SH |
458 | |
459 | switch (sky2->speed) { | |
460 | case SPEED_1000: | |
461 | ctrl |= PHY_CT_SP1000; | |
2eaba1a2 | 462 | reg |= GM_GPCR_SPEED_1000; |
cd28ab6a SH |
463 | break; |
464 | case SPEED_100: | |
465 | ctrl |= PHY_CT_SP100; | |
2eaba1a2 | 466 | reg |= GM_GPCR_SPEED_100; |
cd28ab6a SH |
467 | break; |
468 | } | |
469 | ||
2eaba1a2 SH |
470 | if (sky2->duplex == DUPLEX_FULL) { |
471 | reg |= GM_GPCR_DUP_FULL; | |
472 | ctrl |= PHY_CT_DUP_MD; | |
16ad91e1 SH |
473 | } else if (sky2->speed < SPEED_1000) |
474 | sky2->flow_mode = FC_NONE; | |
0ea065e5 | 475 | } |
2eaba1a2 | 476 | |
0ea065e5 SH |
477 | if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { |
478 | if (sky2_is_copper(hw)) | |
479 | adv |= copper_fc_adv[sky2->flow_mode]; | |
480 | else | |
481 | adv |= fiber_fc_adv[sky2->flow_mode]; | |
482 | } else { | |
483 | reg |= GM_GPCR_AU_FCT_DIS; | |
16ad91e1 | 484 | reg |= gm_fc_disable[sky2->flow_mode]; |
2eaba1a2 SH |
485 | |
486 | /* Forward pause packets to GMAC? */ | |
16ad91e1 | 487 | if (sky2->flow_mode & FC_RX) |
2eaba1a2 SH |
488 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
489 | else | |
490 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
cd28ab6a SH |
491 | } |
492 | ||
2eaba1a2 SH |
493 | gma_write16(hw, port, GM_GP_CTRL, reg); |
494 | ||
05745c4a | 495 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a SH |
496 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
497 | ||
498 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
499 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
500 | ||
501 | /* Setup Phy LED's */ | |
502 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
503 | ledover = 0; | |
504 | ||
505 | switch (hw->chip_id) { | |
506 | case CHIP_ID_YUKON_FE: | |
507 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
508 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
509 | ||
510 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
511 | ||
512 | /* delete ACT LED control bits */ | |
513 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
514 | /* change ACT LED control to blink mode */ | |
515 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
516 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
517 | break; | |
518 | ||
05745c4a SH |
519 | case CHIP_ID_YUKON_FE_P: |
520 | /* Enable Link Partner Next Page */ | |
521 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
522 | ctrl |= PHY_M_PC_ENA_LIP_NP; | |
523 | ||
524 | /* disable Energy Detect and enable scrambler */ | |
525 | ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); | |
526 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
527 | ||
528 | /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ | |
529 | ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | | |
530 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | | |
531 | PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); | |
532 | ||
533 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
534 | break; | |
535 | ||
cd28ab6a | 536 | case CHIP_ID_YUKON_XL: |
793b883e | 537 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
538 | |
539 | /* select page 3 to access LED control register */ | |
540 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
541 | ||
542 | /* set LED Function Control register */ | |
ed6d32c7 SH |
543 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
544 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
545 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
546 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
547 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
548 | |
549 | /* set Polarity Control register */ | |
550 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
551 | (PHY_M_POLC_LS1_P_MIX(4) | |
552 | PHY_M_POLC_IS0_P_MIX(4) | | |
553 | PHY_M_POLC_LOS_CTRL(2) | | |
554 | PHY_M_POLC_INIT_CTRL(2) | | |
555 | PHY_M_POLC_STA1_CTRL(2) | | |
556 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
557 | |
558 | /* restore page register */ | |
793b883e | 559 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a | 560 | break; |
93745494 | 561 | |
ed6d32c7 | 562 | case CHIP_ID_YUKON_EC_U: |
93745494 | 563 | case CHIP_ID_YUKON_EX: |
ed4d4161 | 564 | case CHIP_ID_YUKON_SUPR: |
ed6d32c7 SH |
565 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
566 | ||
567 | /* select page 3 to access LED control register */ | |
568 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
569 | ||
570 | /* set LED Function Control register */ | |
571 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
572 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
573 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ | |
574 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
575 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ | |
576 | ||
577 | /* set Blink Rate in LED Timer Control Register */ | |
578 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, | |
579 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); | |
580 | /* restore page register */ | |
581 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
582 | break; | |
cd28ab6a SH |
583 | |
584 | default: | |
585 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
586 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
a84d0a3d | 587 | |
cd28ab6a | 588 | /* turn off the Rx LED (LED_RX) */ |
a84d0a3d | 589 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); |
cd28ab6a SH |
590 | } |
591 | ||
0ce8b98d | 592 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { |
977bdf06 | 593 | /* apply fixes in PHY AFE */ |
ed6d32c7 SH |
594 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); |
595 | ||
977bdf06 | 596 | /* increase differential signal amplitude in 10BASE-T */ |
ed6d32c7 SH |
597 | gm_phy_write(hw, port, 0x18, 0xaa99); |
598 | gm_phy_write(hw, port, 0x17, 0x2011); | |
cd28ab6a | 599 | |
0ce8b98d SH |
600 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
601 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ | |
602 | gm_phy_write(hw, port, 0x18, 0xa204); | |
603 | gm_phy_write(hw, port, 0x17, 0x2002); | |
604 | } | |
977bdf06 SH |
605 | |
606 | /* set page register to 0 */ | |
9467a8fc | 607 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); |
05745c4a SH |
608 | } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
609 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
610 | /* apply workaround for integrated resistors calibration */ | |
611 | gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); | |
612 | gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); | |
0f5aac70 SH |
613 | } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { |
614 | /* apply fixes in PHY AFE */ | |
615 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); | |
616 | ||
617 | /* apply RDAC termination workaround */ | |
618 | gm_phy_write(hw, port, 24, 0x2800); | |
619 | gm_phy_write(hw, port, 23, 0x2001); | |
620 | ||
621 | /* set page register back to 0 */ | |
622 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
e1a74b37 SH |
623 | } else if (hw->chip_id != CHIP_ID_YUKON_EX && |
624 | hw->chip_id < CHIP_ID_YUKON_SUPR) { | |
05745c4a | 625 | /* no effect on Yukon-XL */ |
977bdf06 | 626 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); |
cd28ab6a | 627 | |
8e95a202 JP |
628 | if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || |
629 | sky2->speed == SPEED_100) { | |
977bdf06 | 630 | /* turn on 100 Mbps LED (LED_LINK100) */ |
a84d0a3d | 631 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); |
977bdf06 | 632 | } |
cd28ab6a | 633 | |
977bdf06 SH |
634 | if (ledover) |
635 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
636 | ||
4fb99cd6 | 637 | } else if (hw->chip_id == CHIP_ID_YUKON_PRM && |
638 | (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { | |
639 | int i; | |
640 | /* This a phy register setup workaround copied from vendor driver. */ | |
641 | static const struct { | |
642 | u16 reg, val; | |
643 | } eee_afe[] = { | |
644 | { 0x156, 0x58ce }, | |
645 | { 0x153, 0x99eb }, | |
646 | { 0x141, 0x8064 }, | |
647 | /* { 0x155, 0x130b },*/ | |
648 | { 0x000, 0x0000 }, | |
649 | { 0x151, 0x8433 }, | |
650 | { 0x14b, 0x8c44 }, | |
651 | { 0x14c, 0x0f90 }, | |
652 | { 0x14f, 0x39aa }, | |
653 | /* { 0x154, 0x2f39 },*/ | |
654 | { 0x14d, 0xba33 }, | |
655 | { 0x144, 0x0048 }, | |
656 | { 0x152, 0x2010 }, | |
657 | /* { 0x158, 0x1223 },*/ | |
658 | { 0x140, 0x4444 }, | |
659 | { 0x154, 0x2f3b }, | |
660 | { 0x158, 0xb203 }, | |
661 | { 0x157, 0x2029 }, | |
662 | }; | |
663 | ||
664 | /* Start Workaround for OptimaEEE Rev.Z0 */ | |
665 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); | |
666 | ||
667 | gm_phy_write(hw, port, 1, 0x4099); | |
668 | gm_phy_write(hw, port, 3, 0x1120); | |
669 | gm_phy_write(hw, port, 11, 0x113c); | |
670 | gm_phy_write(hw, port, 14, 0x8100); | |
671 | gm_phy_write(hw, port, 15, 0x112a); | |
672 | gm_phy_write(hw, port, 17, 0x1008); | |
673 | ||
674 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); | |
675 | gm_phy_write(hw, port, 1, 0x20b0); | |
676 | ||
677 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); | |
678 | ||
679 | for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { | |
680 | /* apply AFE settings */ | |
681 | gm_phy_write(hw, port, 17, eee_afe[i].val); | |
682 | gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); | |
683 | } | |
684 | ||
685 | /* End Workaround for OptimaEEE */ | |
686 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
687 | ||
688 | /* Enable 10Base-Te (EEE) */ | |
689 | if (hw->chip_id >= CHIP_ID_YUKON_PRM) { | |
690 | reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); | |
691 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, | |
692 | reg | PHY_M_10B_TE_ENABLE); | |
693 | } | |
977bdf06 | 694 | } |
2eaba1a2 | 695 | |
d571b694 | 696 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
0ea065e5 | 697 | if (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
cd28ab6a SH |
698 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); |
699 | else | |
700 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
701 | } | |
702 | ||
b96936da SH |
703 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
704 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; | |
705 | ||
706 | static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) | |
d3bcfbeb SH |
707 | { |
708 | u32 reg1; | |
d3bcfbeb | 709 | |
a40ccc68 | 710 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b32f40c4 | 711 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
b96936da | 712 | reg1 &= ~phy_power[port]; |
d3bcfbeb | 713 | |
4b7c47aa | 714 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) |
ff35164e SH |
715 | reg1 |= coma_mode[port]; |
716 | ||
b32f40c4 | 717 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
a40ccc68 | 718 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
82637e80 | 719 | sky2_pci_read32(hw, PCI_DEV_REG1); |
f71eb1a2 SH |
720 | |
721 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
722 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); | |
723 | else if (hw->flags & SKY2_HW_ADV_POWER_CTL) | |
724 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
b96936da | 725 | } |
167f53d0 | 726 | |
b96936da SH |
727 | static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) |
728 | { | |
729 | u32 reg1; | |
db99b988 SH |
730 | u16 ctrl; |
731 | ||
732 | /* release GPHY Control reset */ | |
733 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
734 | ||
735 | /* release GMAC reset */ | |
736 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
737 | ||
738 | if (hw->flags & SKY2_HW_NEWER_PHY) { | |
739 | /* select page 2 to access MAC control register */ | |
740 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
741 | ||
742 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
743 | /* allow GMII Power Down */ | |
744 | ctrl &= ~PHY_M_MAC_GMIF_PUP; | |
745 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
746 | ||
747 | /* set page register back to 0 */ | |
748 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
749 | } | |
750 | ||
751 | /* setup General Purpose Control Register */ | |
752 | gma_write16(hw, port, GM_GP_CTRL, | |
0ea065e5 SH |
753 | GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | |
754 | GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | | |
755 | GM_GPCR_AU_SPD_DIS); | |
db99b988 SH |
756 | |
757 | if (hw->chip_id != CHIP_ID_YUKON_EC) { | |
758 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
e484d5f5 RW |
759 | /* select page 2 to access MAC control register */ |
760 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
db99b988 | 761 | |
e484d5f5 | 762 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
db99b988 SH |
763 | /* enable Power Down */ |
764 | ctrl |= PHY_M_PC_POW_D_ENA; | |
765 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
e484d5f5 RW |
766 | |
767 | /* set page register back to 0 */ | |
768 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); | |
db99b988 SH |
769 | } |
770 | ||
771 | /* set IEEE compatible Power Down Mode (dev. #4.99) */ | |
772 | gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); | |
773 | } | |
b96936da | 774 | |
a40ccc68 | 775 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b96936da | 776 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
db99b988 | 777 | reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ |
b96936da | 778 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
a40ccc68 | 779 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
d3bcfbeb SH |
780 | } |
781 | ||
8e11680f | 782 | /* configure IPG according to used link speed */ |
783 | static void sky2_set_ipg(struct sky2_port *sky2) | |
784 | { | |
785 | u16 reg; | |
786 | ||
787 | reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); | |
788 | reg &= ~GM_SMOD_IPG_MSK; | |
789 | if (sky2->speed > SPEED_100) | |
790 | reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); | |
791 | else | |
792 | reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); | |
793 | gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); | |
794 | } | |
795 | ||
38000a94 BP |
796 | /* Enable Rx/Tx */ |
797 | static void sky2_enable_rx_tx(struct sky2_port *sky2) | |
798 | { | |
799 | struct sky2_hw *hw = sky2->hw; | |
800 | unsigned port = sky2->port; | |
801 | u16 reg; | |
802 | ||
803 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
804 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
805 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
806 | } | |
807 | ||
1b537565 SH |
808 | /* Force a renegotiation */ |
809 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
810 | { | |
e07b1aa8 | 811 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 812 | sky2_phy_init(sky2->hw, sky2->port); |
38000a94 | 813 | sky2_enable_rx_tx(sky2); |
e07b1aa8 | 814 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
815 | } |
816 | ||
e3173832 SH |
817 | /* Put device in state to listen for Wake On Lan */ |
818 | static void sky2_wol_init(struct sky2_port *sky2) | |
819 | { | |
820 | struct sky2_hw *hw = sky2->hw; | |
821 | unsigned port = sky2->port; | |
822 | enum flow_control save_mode; | |
823 | u16 ctrl; | |
e3173832 SH |
824 | |
825 | /* Bring hardware out of reset */ | |
826 | sky2_write16(hw, B0_CTST, CS_RST_CLR); | |
827 | sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
828 | ||
829 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
830 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
831 | ||
832 | /* Force to 10/100 | |
833 | * sky2_reset will re-enable on resume | |
834 | */ | |
835 | save_mode = sky2->flow_mode; | |
836 | ctrl = sky2->advertising; | |
837 | ||
838 | sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); | |
839 | sky2->flow_mode = FC_NONE; | |
b96936da SH |
840 | |
841 | spin_lock_bh(&sky2->phy_lock); | |
842 | sky2_phy_power_up(hw, port); | |
843 | sky2_phy_init(hw, port); | |
844 | spin_unlock_bh(&sky2->phy_lock); | |
e3173832 SH |
845 | |
846 | sky2->flow_mode = save_mode; | |
847 | sky2->advertising = ctrl; | |
848 | ||
849 | /* Set GMAC to no flow control and auto update for speed/duplex */ | |
850 | gma_write16(hw, port, GM_GP_CTRL, | |
851 | GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| | |
852 | GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); | |
853 | ||
854 | /* Set WOL address */ | |
855 | memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), | |
856 | sky2->netdev->dev_addr, ETH_ALEN); | |
857 | ||
858 | /* Turn on appropriate WOL control bits */ | |
859 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); | |
860 | ctrl = 0; | |
861 | if (sky2->wol & WAKE_PHY) | |
862 | ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; | |
863 | else | |
864 | ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; | |
865 | ||
866 | if (sky2->wol & WAKE_MAGIC) | |
867 | ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; | |
868 | else | |
a419aef8 | 869 | ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; |
e3173832 SH |
870 | |
871 | ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; | |
872 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | |
873 | ||
5f8ae5c5 | 874 | /* Disable PiG firmware */ |
875 | sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); | |
876 | ||
5676cc7b | 877 | /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */ |
878 | if (legacy_pme) { | |
879 | u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); | |
880 | reg1 |= PCI_Y2_PME_LEGACY; | |
881 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | |
882 | } | |
883 | ||
e3173832 SH |
884 | /* block receiver */ |
885 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
f9687c44 | 886 | sky2_read32(hw, B0_CTST); |
e3173832 SH |
887 | } |
888 | ||
69161611 SH |
889 | static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) |
890 | { | |
05745c4a SH |
891 | struct net_device *dev = hw->dev[port]; |
892 | ||
ed4d4161 SH |
893 | if ( (hw->chip_id == CHIP_ID_YUKON_EX && |
894 | hw->chip_rev != CHIP_REV_YU_EX_A0) || | |
877c8570 | 895 | hw->chip_id >= CHIP_ID_YUKON_FE_P) { |
ed4d4161 | 896 | /* Yukon-Extreme B0 and further Extreme devices */ |
44dde56d | 897 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); |
898 | } else if (dev->mtu > ETH_DATA_LEN) { | |
899 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
900 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), | |
901 | (ECU_JUMBO_WM << 16) | ECU_AE_THR); | |
05745c4a | 902 | |
44dde56d | 903 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); |
904 | } else | |
905 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); | |
69161611 SH |
906 | } |
907 | ||
cd28ab6a SH |
908 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
909 | { | |
910 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
911 | u16 reg; | |
25cccecc | 912 | u32 rx_reg; |
cd28ab6a SH |
913 | int i; |
914 | const u8 *addr = hw->dev[port]->dev_addr; | |
915 | ||
f350339c SH |
916 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
917 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); | |
cd28ab6a SH |
918 | |
919 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
920 | ||
4b7c47aa | 921 | if (hw->chip_id == CHIP_ID_YUKON_XL && |
922 | hw->chip_rev == CHIP_REV_YU_XL_A0 && | |
923 | port == 1) { | |
cd28ab6a SH |
924 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
925 | /* clear GMAC 1 Control reset */ | |
926 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
927 | do { | |
928 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
929 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
930 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
931 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
932 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
933 | } | |
934 | ||
793b883e | 935 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 936 | |
2eaba1a2 SH |
937 | /* Enable Transmit FIFO Underrun */ |
938 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); | |
939 | ||
e07b1aa8 | 940 | spin_lock_bh(&sky2->phy_lock); |
b96936da | 941 | sky2_phy_power_up(hw, port); |
cd28ab6a | 942 | sky2_phy_init(hw, port); |
e07b1aa8 | 943 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
944 | |
945 | /* MIB clear */ | |
946 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
947 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
948 | ||
43f2f104 SH |
949 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
950 | gma_read16(hw, port, i); | |
cd28ab6a SH |
951 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
952 | ||
953 | /* transmit control */ | |
954 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
955 | ||
956 | /* receive control reg: unicast + multicast + no FCS */ | |
957 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 958 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
959 | |
960 | /* transmit flow control */ | |
961 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
962 | ||
963 | /* transmit parameter */ | |
964 | gma_write16(hw, port, GM_TX_PARAM, | |
965 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
966 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
967 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
968 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
969 | ||
970 | /* serial mode register */ | |
971 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
8e11680f | 972 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); |
cd28ab6a | 973 | |
6b1a3aef | 974 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
975 | reg |= GM_SMOD_JUMBO_ENA; |
976 | ||
c1cd0a85 | 977 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
978 | hw->chip_rev == CHIP_REV_YU_EC_U_B1) | |
979 | reg |= GM_NEW_FLOW_CTRL; | |
980 | ||
cd28ab6a SH |
981 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
982 | ||
cd28ab6a SH |
983 | /* virtual address for data */ |
984 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
985 | ||
793b883e SH |
986 | /* physical address: used for pause frames */ |
987 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
988 | ||
989 | /* ignore counter overflows */ | |
cd28ab6a SH |
990 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
991 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
992 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
993 | ||
994 | /* Configure Rx MAC FIFO */ | |
995 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
25cccecc | 996 | rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
05745c4a SH |
997 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
998 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
25cccecc | 999 | rx_reg |= GMF_RX_OVER_ON; |
69161611 | 1000 | |
25cccecc | 1001 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); |
cd28ab6a | 1002 | |
798fdd07 SH |
1003 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1004 | /* Hardware errata - clear flush mask */ | |
1005 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); | |
1006 | } else { | |
1007 | /* Flush Rx MAC FIFO on any flow control or error */ | |
1008 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); | |
1009 | } | |
cd28ab6a | 1010 | |
8df9a876 | 1011 | /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ |
05745c4a SH |
1012 | reg = RX_GMF_FL_THR_DEF + 1; |
1013 | /* Another magic mystery workaround from sk98lin */ | |
1014 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && | |
1015 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
1016 | reg = 0x178; | |
1017 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); | |
cd28ab6a SH |
1018 | |
1019 | /* Configure Tx MAC FIFO */ | |
1020 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
1021 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 1022 | |
25985edc | 1023 | /* On chips without ram buffer, pause is controlled by MAC level */ |
39dbd958 | 1024 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { |
d6b54d24 | 1025 | /* Pause threshold is scaled by 8 in bytes */ |
8e95a202 JP |
1026 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
1027 | hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
d6b54d24 SH |
1028 | reg = 1568 / 8; |
1029 | else | |
1030 | reg = 1024 / 8; | |
1031 | sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); | |
1032 | sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); | |
b628ed98 | 1033 | |
69161611 | 1034 | sky2_set_tx_stfwd(hw, port); |
5a5b1ea0 SH |
1035 | } |
1036 | ||
e970d1f8 SH |
1037 | if (hw->chip_id == CHIP_ID_YUKON_FE_P && |
1038 | hw->chip_rev == CHIP_REV_YU_FE2_A0) { | |
1039 | /* disable dynamic watermark */ | |
1040 | reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); | |
1041 | reg &= ~TX_DYN_WM_ENA; | |
1042 | sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); | |
1043 | } | |
cd28ab6a SH |
1044 | } |
1045 | ||
67712901 SH |
1046 | /* Assign Ram Buffer allocation to queue */ |
1047 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) | |
cd28ab6a | 1048 | { |
67712901 SH |
1049 | u32 end; |
1050 | ||
1051 | /* convert from K bytes to qwords used for hw register */ | |
1052 | start *= 1024/8; | |
1053 | space *= 1024/8; | |
1054 | end = start + space - 1; | |
793b883e | 1055 | |
cd28ab6a SH |
1056 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
1057 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
1058 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
1059 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
1060 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
1061 | ||
1062 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba | 1063 | u32 tp = space - space/4; |
793b883e | 1064 | |
1c28f6ba SH |
1065 | /* On receive queue's set the thresholds |
1066 | * give receiver priority when > 3/4 full | |
1067 | * send pause when down to 2K | |
1068 | */ | |
1069 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
1070 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 1071 | |
74f9f42c | 1072 | tp = space - 8192/8; |
1c28f6ba SH |
1073 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); |
1074 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
1075 | } else { |
1076 | /* Enable store & forward on Tx queue's because | |
1077 | * Tx FIFO is only 1K on Yukon | |
1078 | */ | |
1079 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
1080 | } | |
1081 | ||
1082 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 1083 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
1084 | } |
1085 | ||
cd28ab6a | 1086 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 1087 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
1088 | { |
1089 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
1090 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
1091 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 1092 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
1093 | } |
1094 | ||
cd28ab6a SH |
1095 | /* Setup prefetch unit registers. This is the interface between |
1096 | * hardware and driver list elements | |
1097 | */ | |
8cc048e3 | 1098 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
d6e74b6b | 1099 | dma_addr_t addr, u32 last) |
cd28ab6a | 1100 | { |
cd28ab6a SH |
1101 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
1102 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
d6e74b6b SH |
1103 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); |
1104 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); | |
cd28ab6a SH |
1105 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); |
1106 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
1107 | |
1108 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
1109 | } |
1110 | ||
9b289c33 | 1111 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) |
793b883e | 1112 | { |
9b289c33 | 1113 | struct sky2_tx_le *le = sky2->tx_le + *slot; |
793b883e | 1114 | |
ee5f68fe | 1115 | *slot = RING_NEXT(*slot, sky2->tx_ring_size); |
291ea614 | 1116 | le->ctrl = 0; |
793b883e SH |
1117 | return le; |
1118 | } | |
cd28ab6a | 1119 | |
88f5f0ca SH |
1120 | static void tx_init(struct sky2_port *sky2) |
1121 | { | |
1122 | struct sky2_tx_le *le; | |
1123 | ||
1124 | sky2->tx_prod = sky2->tx_cons = 0; | |
1125 | sky2->tx_tcpsum = 0; | |
1126 | sky2->tx_last_mss = 0; | |
ec2a5466 | 1127 | netdev_reset_queue(sky2->netdev); |
88f5f0ca | 1128 | |
9b289c33 | 1129 | le = get_tx_le(sky2, &sky2->tx_prod); |
88f5f0ca SH |
1130 | le->addr = 0; |
1131 | le->opcode = OP_ADDR64 | HW_OWNER; | |
5dce95e5 | 1132 | sky2->tx_last_upper = 0; |
88f5f0ca SH |
1133 | } |
1134 | ||
290d4de5 SH |
1135 | /* Update chip's next pointer */ |
1136 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 1137 | { |
50432cb5 | 1138 | /* Make sure write' to descriptors are complete before we tell hardware */ |
762c2de2 | 1139 | wmb(); |
50432cb5 SH |
1140 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
1141 | ||
1142 | /* Synchronize I/O on since next processor may write to tail */ | |
1143 | mmiowb(); | |
cd28ab6a SH |
1144 | } |
1145 | ||
793b883e | 1146 | |
cd28ab6a SH |
1147 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
1148 | { | |
1149 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
cb5d9547 | 1150 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
291ea614 | 1151 | le->ctrl = 0; |
cd28ab6a SH |
1152 | return le; |
1153 | } | |
1154 | ||
060b946c | 1155 | static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) |
39ef110b MM |
1156 | { |
1157 | unsigned size; | |
1158 | ||
1159 | /* Space needed for frame data + headers rounded up */ | |
1160 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); | |
1161 | ||
1162 | /* Stopping point for hardware truncation */ | |
1163 | return (size - 8) / sizeof(u32); | |
1164 | } | |
1165 | ||
060b946c | 1166 | static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) |
39ef110b MM |
1167 | { |
1168 | struct rx_ring_info *re; | |
1169 | unsigned size; | |
1170 | ||
1171 | /* Space needed for frame data + headers rounded up */ | |
1172 | size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); | |
1173 | ||
1174 | sky2->rx_nfrags = size >> PAGE_SHIFT; | |
1175 | BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); | |
1176 | ||
1177 | /* Compute residue after pages */ | |
1178 | size -= sky2->rx_nfrags << PAGE_SHIFT; | |
1179 | ||
1180 | /* Optimize to handle small packets and headers */ | |
1181 | if (size < copybreak) | |
1182 | size = copybreak; | |
1183 | if (size < ETH_HLEN) | |
1184 | size = ETH_HLEN; | |
1185 | ||
1186 | return size; | |
1187 | } | |
1188 | ||
14d0263f | 1189 | /* Build description to hardware for one receive segment */ |
060b946c | 1190 | static void sky2_rx_add(struct sky2_port *sky2, u8 op, |
14d0263f | 1191 | dma_addr_t map, unsigned len) |
cd28ab6a SH |
1192 | { |
1193 | struct sky2_rx_le *le; | |
1194 | ||
86c6887e | 1195 | if (sizeof(dma_addr_t) > sizeof(u32)) { |
cd28ab6a | 1196 | le = sky2_next_rx(sky2); |
86c6887e | 1197 | le->addr = cpu_to_le32(upper_32_bits(map)); |
cd28ab6a SH |
1198 | le->opcode = OP_ADDR64 | HW_OWNER; |
1199 | } | |
793b883e | 1200 | |
cd28ab6a | 1201 | le = sky2_next_rx(sky2); |
d6e74b6b | 1202 | le->addr = cpu_to_le32(lower_32_bits(map)); |
734d1868 | 1203 | le->length = cpu_to_le16(len); |
14d0263f | 1204 | le->opcode = op | HW_OWNER; |
cd28ab6a SH |
1205 | } |
1206 | ||
14d0263f SH |
1207 | /* Build description to hardware for one possibly fragmented skb */ |
1208 | static void sky2_rx_submit(struct sky2_port *sky2, | |
1209 | const struct rx_ring_info *re) | |
1210 | { | |
1211 | int i; | |
1212 | ||
1213 | sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); | |
1214 | ||
1215 | for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) | |
1216 | sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); | |
1217 | } | |
1218 | ||
1219 | ||
454e6cb6 | 1220 | static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, |
14d0263f SH |
1221 | unsigned size) |
1222 | { | |
1223 | struct sk_buff *skb = re->skb; | |
1224 | int i; | |
1225 | ||
1226 | re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); | |
3fbd9187 | 1227 | if (pci_dma_mapping_error(pdev, re->data_addr)) |
1228 | goto mapping_error; | |
454e6cb6 | 1229 | |
7cd26ce5 | 1230 | dma_unmap_len_set(re, data_size, size); |
14d0263f | 1231 | |
3fbd9187 | 1232 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
9e903e08 | 1233 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
3fbd9187 | 1234 | |
950a5a4f | 1235 | re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, |
9e903e08 | 1236 | skb_frag_size(frag), |
5d6bcdfe | 1237 | DMA_FROM_DEVICE); |
3fbd9187 | 1238 | |
5d6bcdfe | 1239 | if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) |
3fbd9187 | 1240 | goto map_page_error; |
1241 | } | |
454e6cb6 | 1242 | return 0; |
3fbd9187 | 1243 | |
1244 | map_page_error: | |
1245 | while (--i >= 0) { | |
1246 | pci_unmap_page(pdev, re->frag_addr[i], | |
9e903e08 | 1247 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
3fbd9187 | 1248 | PCI_DMA_FROMDEVICE); |
1249 | } | |
1250 | ||
7cd26ce5 | 1251 | pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), |
3fbd9187 | 1252 | PCI_DMA_FROMDEVICE); |
1253 | ||
1254 | mapping_error: | |
1255 | if (net_ratelimit()) | |
1256 | dev_warn(&pdev->dev, "%s: rx mapping error\n", | |
1257 | skb->dev->name); | |
1258 | return -EIO; | |
14d0263f SH |
1259 | } |
1260 | ||
1261 | static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) | |
1262 | { | |
1263 | struct sk_buff *skb = re->skb; | |
1264 | int i; | |
1265 | ||
7cd26ce5 | 1266 | pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), |
14d0263f SH |
1267 | PCI_DMA_FROMDEVICE); |
1268 | ||
1269 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) | |
1270 | pci_unmap_page(pdev, re->frag_addr[i], | |
9e903e08 | 1271 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
14d0263f SH |
1272 | PCI_DMA_FROMDEVICE); |
1273 | } | |
793b883e | 1274 | |
cd28ab6a SH |
1275 | /* Tell chip where to start receive checksum. |
1276 | * Actually has two checksums, but set both same to avoid possible byte | |
1277 | * order problems. | |
1278 | */ | |
793b883e | 1279 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a | 1280 | { |
ea76e635 | 1281 | struct sky2_rx_le *le = sky2_next_rx(sky2); |
793b883e | 1282 | |
ea76e635 SH |
1283 | le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); |
1284 | le->ctrl = 0; | |
1285 | le->opcode = OP_TCPSTART | HW_OWNER; | |
cd28ab6a | 1286 | |
ea76e635 SH |
1287 | sky2_write32(sky2->hw, |
1288 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
f5d64037 | 1289 | (sky2->netdev->features & NETIF_F_RXCSUM) |
0ea065e5 | 1290 | ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); |
cd28ab6a SH |
1291 | } |
1292 | ||
bf73130d | 1293 | /* Enable/disable receive hash calculation (RSS) */ |
c8f44aff | 1294 | static void rx_set_rss(struct net_device *dev, netdev_features_t features) |
bf73130d SH |
1295 | { |
1296 | struct sky2_port *sky2 = netdev_priv(dev); | |
1297 | struct sky2_hw *hw = sky2->hw; | |
1298 | int i, nkeys = 4; | |
1299 | ||
1300 | /* Supports IPv6 and other modes */ | |
1301 | if (hw->flags & SKY2_HW_NEW_LE) { | |
1302 | nkeys = 10; | |
1303 | sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); | |
1304 | } | |
1305 | ||
1306 | /* Program RSS initial values */ | |
f5d64037 | 1307 | if (features & NETIF_F_RXHASH) { |
2e95b2a8 IM |
1308 | u32 rss_key[10]; |
1309 | ||
1310 | netdev_rss_key_fill(rss_key, sizeof(rss_key)); | |
bf73130d SH |
1311 | for (i = 0; i < nkeys; i++) |
1312 | sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), | |
2e95b2a8 | 1313 | rss_key[i]); |
bf73130d SH |
1314 | |
1315 | /* Need to turn on (undocumented) flag to make hashing work */ | |
1316 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), | |
1317 | RX_STFW_ENA); | |
1318 | ||
1319 | sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1320 | BMU_ENA_RX_RSS_HASH); | |
1321 | } else | |
1322 | sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
1323 | BMU_DIS_RX_RSS_HASH); | |
1324 | } | |
1325 | ||
6b1a3aef SH |
1326 | /* |
1327 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
1328 | * reach the end of packet and since we can't make sure that we have | |
1329 | * incoming data, we must reset the BMU while it is not doing a DMA | |
1330 | * transfer. Since it is possible that the RX path is still active, | |
1331 | * the RX RAM buffer will be stopped first, so any possible incoming | |
1332 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
1333 | * BMU is polled until any DMA in progress is ended and only then it | |
1334 | * will be reset. | |
1335 | */ | |
1336 | static void sky2_rx_stop(struct sky2_port *sky2) | |
1337 | { | |
1338 | struct sky2_hw *hw = sky2->hw; | |
1339 | unsigned rxq = rxqaddr[sky2->port]; | |
1340 | int i; | |
1341 | ||
1342 | /* disable the RAM Buffer receive queue */ | |
1343 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
1344 | ||
1345 | for (i = 0; i < 0xffff; i++) | |
1346 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
1347 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
1348 | goto stopped; | |
1349 | ||
ada1db5c | 1350 | netdev_warn(sky2->netdev, "receiver stop failed\n"); |
6b1a3aef SH |
1351 | stopped: |
1352 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
1353 | ||
1354 | /* reset the Rx prefetch unit */ | |
1355 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
3d1454dd | 1356 | mmiowb(); |
6b1a3aef | 1357 | } |
793b883e | 1358 | |
d571b694 | 1359 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
1360 | static void sky2_rx_clean(struct sky2_port *sky2) |
1361 | { | |
1362 | unsigned i; | |
1363 | ||
799d2fff ML |
1364 | if (sky2->rx_le) |
1365 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1366 | ||
793b883e | 1367 | for (i = 0; i < sky2->rx_pending; i++) { |
291ea614 | 1368 | struct rx_ring_info *re = sky2->rx_ring + i; |
cd28ab6a SH |
1369 | |
1370 | if (re->skb) { | |
14d0263f | 1371 | sky2_rx_unmap_skb(sky2->hw->pdev, re); |
cd28ab6a SH |
1372 | kfree_skb(re->skb); |
1373 | re->skb = NULL; | |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | ||
ef743d33 SH |
1378 | /* Basic MII support */ |
1379 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1380 | { | |
1381 | struct mii_ioctl_data *data = if_mii(ifr); | |
1382 | struct sky2_port *sky2 = netdev_priv(dev); | |
1383 | struct sky2_hw *hw = sky2->hw; | |
1384 | int err = -EOPNOTSUPP; | |
1385 | ||
1386 | if (!netif_running(dev)) | |
1387 | return -ENODEV; /* Phy still in reset */ | |
1388 | ||
d89e1343 | 1389 | switch (cmd) { |
ef743d33 SH |
1390 | case SIOCGMIIPHY: |
1391 | data->phy_id = PHY_ADDR_MARV; | |
1392 | ||
1393 | /* fallthru */ | |
1394 | case SIOCGMIIREG: { | |
1395 | u16 val = 0; | |
91c86df5 | 1396 | |
e07b1aa8 | 1397 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 1398 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 1399 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 1400 | |
ef743d33 SH |
1401 | data->val_out = val; |
1402 | break; | |
1403 | } | |
1404 | ||
1405 | case SIOCSMIIREG: | |
e07b1aa8 | 1406 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 SH |
1407 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
1408 | data->val_in); | |
e07b1aa8 | 1409 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 SH |
1410 | break; |
1411 | } | |
1412 | return err; | |
1413 | } | |
1414 | ||
f5d64037 | 1415 | #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) |
d494eacd | 1416 | |
c8f44aff | 1417 | static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) |
d494eacd SH |
1418 | { |
1419 | struct sky2_port *sky2 = netdev_priv(dev); | |
1420 | struct sky2_hw *hw = sky2->hw; | |
1421 | u16 port = sky2->port; | |
1422 | ||
f646968f | 1423 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
86aa7785 SH |
1424 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
1425 | RX_VLAN_STRIP_ON); | |
1426 | else | |
1427 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), | |
1428 | RX_VLAN_STRIP_OFF); | |
d494eacd | 1429 | |
f646968f | 1430 | if (features & NETIF_F_HW_VLAN_CTAG_TX) { |
86aa7785 SH |
1431 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1432 | TX_VLAN_TAG_ON); | |
f5d64037 MM |
1433 | |
1434 | dev->vlan_features |= SKY2_VLAN_OFFLOADS; | |
1435 | } else { | |
86aa7785 SH |
1436 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), |
1437 | TX_VLAN_TAG_OFF); | |
d1f13708 | 1438 | |
86aa7785 | 1439 | /* Can't do transmit offload of vlan without hw vlan */ |
f5d64037 | 1440 | dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; |
86aa7785 | 1441 | } |
d1f13708 | 1442 | } |
d1f13708 | 1443 | |
bd1c6869 SH |
1444 | /* Amount of required worst case padding in rx buffer */ |
1445 | static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) | |
1446 | { | |
1447 | return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; | |
1448 | } | |
1449 | ||
82788c7a | 1450 | /* |
14d0263f SH |
1451 | * Allocate an skb for receiving. If the MTU is large enough |
1452 | * make the skb non-linear with a fragment list of pages. | |
82788c7a | 1453 | */ |
68ac3191 | 1454 | static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) |
82788c7a SH |
1455 | { |
1456 | struct sk_buff *skb; | |
14d0263f | 1457 | int i; |
82788c7a | 1458 | |
68ac3191 ED |
1459 | skb = __netdev_alloc_skb(sky2->netdev, |
1460 | sky2->rx_data_size + sky2_rx_pad(sky2->hw), | |
1461 | gfp); | |
bd1c6869 SH |
1462 | if (!skb) |
1463 | goto nomem; | |
1464 | ||
39dbd958 | 1465 | if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { |
f03b8654 SH |
1466 | unsigned char *start; |
1467 | /* | |
1468 | * Workaround for a bug in FIFO that cause hang | |
1469 | * if the FIFO if the receive buffer is not 64 byte aligned. | |
1470 | * The buffer returned from netdev_alloc_skb is | |
1471 | * aligned except if slab debugging is enabled. | |
1472 | */ | |
f03b8654 SH |
1473 | start = PTR_ALIGN(skb->data, 8); |
1474 | skb_reserve(skb, start - skb->data); | |
bd1c6869 | 1475 | } else |
f03b8654 | 1476 | skb_reserve(skb, NET_IP_ALIGN); |
14d0263f SH |
1477 | |
1478 | for (i = 0; i < sky2->rx_nfrags; i++) { | |
68ac3191 | 1479 | struct page *page = alloc_page(gfp); |
14d0263f SH |
1480 | |
1481 | if (!page) | |
1482 | goto free_partial; | |
1483 | skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); | |
82788c7a SH |
1484 | } |
1485 | ||
1486 | return skb; | |
14d0263f SH |
1487 | free_partial: |
1488 | kfree_skb(skb); | |
1489 | nomem: | |
1490 | return NULL; | |
82788c7a SH |
1491 | } |
1492 | ||
55c9dd35 SH |
1493 | static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) |
1494 | { | |
1495 | sky2_put_idx(sky2->hw, rxq, sky2->rx_put); | |
1496 | } | |
1497 | ||
200ac492 MM |
1498 | static int sky2_alloc_rx_skbs(struct sky2_port *sky2) |
1499 | { | |
1500 | struct sky2_hw *hw = sky2->hw; | |
1501 | unsigned i; | |
1502 | ||
1503 | sky2->rx_data_size = sky2_get_rx_data_size(sky2); | |
1504 | ||
1505 | /* Fill Rx ring */ | |
1506 | for (i = 0; i < sky2->rx_pending; i++) { | |
1507 | struct rx_ring_info *re = sky2->rx_ring + i; | |
1508 | ||
68ac3191 | 1509 | re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); |
200ac492 MM |
1510 | if (!re->skb) |
1511 | return -ENOMEM; | |
1512 | ||
1513 | if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { | |
1514 | dev_kfree_skb(re->skb); | |
1515 | re->skb = NULL; | |
1516 | return -ENOMEM; | |
1517 | } | |
1518 | } | |
1519 | return 0; | |
1520 | } | |
1521 | ||
cd28ab6a | 1522 | /* |
200ac492 | 1523 | * Setup receiver buffer pool. |
14d0263f SH |
1524 | * Normal case this ends up creating one list element for skb |
1525 | * in the receive ring. Worst case if using large MTU and each | |
1526 | * allocation falls on a different 64 bit region, that results | |
1527 | * in 6 list elements per ring entry. | |
1528 | * One element is used for checksum enable/disable, and one | |
1529 | * extra to avoid wrap. | |
cd28ab6a | 1530 | */ |
200ac492 | 1531 | static void sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 1532 | { |
6b1a3aef | 1533 | struct sky2_hw *hw = sky2->hw; |
14d0263f | 1534 | struct rx_ring_info *re; |
6b1a3aef | 1535 | unsigned rxq = rxqaddr[sky2->port]; |
39ef110b | 1536 | unsigned i, thresh; |
cd28ab6a | 1537 | |
6b1a3aef | 1538 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 1539 | sky2_qset(hw, rxq); |
977bdf06 | 1540 | |
c3905bc4 | 1541 | /* On PCI express lowering the watermark gives better performance */ |
1a10ccae | 1542 | if (pci_is_pcie(hw->pdev)) |
c3905bc4 SH |
1543 | sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); |
1544 | ||
1545 | /* These chips have no ram buffer? | |
1546 | * MAC Rx RAM Read is controlled by hardware */ | |
8df9a876 | 1547 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
c1cd0a85 | 1548 | hw->chip_rev > CHIP_REV_YU_EC_U_A0) |
f449c7c1 | 1549 | sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); |
977bdf06 | 1550 | |
6b1a3aef SH |
1551 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
1552 | ||
ea76e635 SH |
1553 | if (!(hw->flags & SKY2_HW_NEW_LE)) |
1554 | rx_set_checksum(sky2); | |
14d0263f | 1555 | |
bf73130d | 1556 | if (!(hw->flags & SKY2_HW_RSS_BROKEN)) |
f5d64037 | 1557 | rx_set_rss(sky2->netdev, sky2->netdev->features); |
bf73130d | 1558 | |
200ac492 | 1559 | /* submit Rx ring */ |
793b883e | 1560 | for (i = 0; i < sky2->rx_pending; i++) { |
14d0263f | 1561 | re = sky2->rx_ring + i; |
14d0263f | 1562 | sky2_rx_submit(sky2, re); |
cd28ab6a SH |
1563 | } |
1564 | ||
a1433ac4 SH |
1565 | /* |
1566 | * The receiver hangs if it receives frames larger than the | |
1567 | * packet buffer. As a workaround, truncate oversize frames, but | |
1568 | * the register is limited to 9 bits, so if you do frames > 2052 | |
1569 | * you better get the MTU right! | |
1570 | */ | |
39ef110b | 1571 | thresh = sky2_get_rx_threshold(sky2); |
a1433ac4 SH |
1572 | if (thresh > 0x1ff) |
1573 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); | |
1574 | else { | |
1575 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); | |
1576 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
1577 | } | |
1578 | ||
6b1a3aef | 1579 | /* Tell chip about available buffers */ |
55c9dd35 | 1580 | sky2_rx_update(sky2, rxq); |
877c8570 SH |
1581 | |
1582 | if (hw->chip_id == CHIP_ID_YUKON_EX || | |
1583 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
1584 | /* | |
1585 | * Disable flushing of non ASF packets; | |
1586 | * must be done after initializing the BMUs; | |
1587 | * drivers without ASF support should do this too, otherwise | |
1588 | * it may happen that they cannot run on ASF devices; | |
1589 | * remember that the MAC FIFO isn't reset during initialization. | |
1590 | */ | |
1591 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); | |
1592 | } | |
1593 | ||
1594 | if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { | |
1595 | /* Enable RX Home Address & Routing Header checksum fix */ | |
1596 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), | |
1597 | RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); | |
1598 | ||
1599 | /* Enable TX Home Address & Routing Header checksum fix */ | |
1600 | sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), | |
1601 | TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); | |
1602 | } | |
cd28ab6a SH |
1603 | } |
1604 | ||
90bbebb4 MM |
1605 | static int sky2_alloc_buffers(struct sky2_port *sky2) |
1606 | { | |
1607 | struct sky2_hw *hw = sky2->hw; | |
1608 | ||
1609 | /* must be power of 2 */ | |
1610 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
1611 | sky2->tx_ring_size * | |
1612 | sizeof(struct sky2_tx_le), | |
1613 | &sky2->tx_le_map); | |
1614 | if (!sky2->tx_le) | |
1615 | goto nomem; | |
1616 | ||
1617 | sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), | |
1618 | GFP_KERNEL); | |
1619 | if (!sky2->tx_ring) | |
1620 | goto nomem; | |
1621 | ||
12fe08b2 JP |
1622 | sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES, |
1623 | &sky2->rx_le_map); | |
90bbebb4 MM |
1624 | if (!sky2->rx_le) |
1625 | goto nomem; | |
90bbebb4 MM |
1626 | |
1627 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), | |
1628 | GFP_KERNEL); | |
1629 | if (!sky2->rx_ring) | |
1630 | goto nomem; | |
1631 | ||
200ac492 | 1632 | return sky2_alloc_rx_skbs(sky2); |
90bbebb4 MM |
1633 | nomem: |
1634 | return -ENOMEM; | |
1635 | } | |
1636 | ||
1637 | static void sky2_free_buffers(struct sky2_port *sky2) | |
1638 | { | |
1639 | struct sky2_hw *hw = sky2->hw; | |
1640 | ||
200ac492 MM |
1641 | sky2_rx_clean(sky2); |
1642 | ||
90bbebb4 MM |
1643 | if (sky2->rx_le) { |
1644 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1645 | sky2->rx_le, sky2->rx_le_map); | |
1646 | sky2->rx_le = NULL; | |
1647 | } | |
1648 | if (sky2->tx_le) { | |
1649 | pci_free_consistent(hw->pdev, | |
1650 | sky2->tx_ring_size * sizeof(struct sky2_tx_le), | |
1651 | sky2->tx_le, sky2->tx_le_map); | |
1652 | sky2->tx_le = NULL; | |
1653 | } | |
1654 | kfree(sky2->tx_ring); | |
1655 | kfree(sky2->rx_ring); | |
1656 | ||
1657 | sky2->tx_ring = NULL; | |
1658 | sky2->rx_ring = NULL; | |
1659 | } | |
1660 | ||
ea0f71e5 | 1661 | static void sky2_hw_up(struct sky2_port *sky2) |
cd28ab6a | 1662 | { |
cd28ab6a SH |
1663 | struct sky2_hw *hw = sky2->hw; |
1664 | unsigned port = sky2->port; | |
ea0f71e5 MM |
1665 | u32 ramsize; |
1666 | int cap; | |
843a46f4 | 1667 | struct net_device *otherdev = hw->dev[sky2->port^1]; |
cd28ab6a | 1668 | |
ea0f71e5 MM |
1669 | tx_init(sky2); |
1670 | ||
ee7abb04 SH |
1671 | /* |
1672 | * On dual port PCI-X card, there is an problem where status | |
1673 | * can be received out of order due to split transactions | |
843a46f4 | 1674 | */ |
ee7abb04 SH |
1675 | if (otherdev && netif_running(otherdev) && |
1676 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | |
ee7abb04 SH |
1677 | u16 cmd; |
1678 | ||
b32f40c4 | 1679 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); |
ee7abb04 | 1680 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
b32f40c4 | 1681 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); |
ea0f71e5 | 1682 | } |
cd28ab6a | 1683 | |
cd28ab6a SH |
1684 | sky2_mac_init(hw, port); |
1685 | ||
e0c28116 SH |
1686 | /* Register is number of 4K blocks on internal RAM buffer. */ |
1687 | ramsize = sky2_read8(hw, B2_E_0) * 4; | |
1688 | if (ramsize > 0) { | |
67712901 | 1689 | u32 rxspace; |
cd28ab6a | 1690 | |
ada1db5c | 1691 | netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); |
67712901 SH |
1692 | if (ramsize < 16) |
1693 | rxspace = ramsize / 2; | |
1694 | else | |
1695 | rxspace = 8 + (2*(ramsize - 16))/3; | |
cd28ab6a | 1696 | |
67712901 SH |
1697 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1698 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
1699 | ||
1700 | /* Make sure SyncQ is disabled */ | |
1701 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1702 | RB_RST_SET); | |
1703 | } | |
793b883e | 1704 | |
af4ed7e6 | 1705 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1706 | |
69161611 SH |
1707 | /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ |
1708 | if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) | |
1709 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); | |
1710 | ||
977bdf06 | 1711 | /* Set almost empty threshold */ |
8e95a202 JP |
1712 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
1713 | hw->chip_rev == CHIP_REV_YU_EC_U_A0) | |
b628ed98 | 1714 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); |
5a5b1ea0 | 1715 | |
6b1a3aef | 1716 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
ee5f68fe | 1717 | sky2->tx_ring_size - 1); |
cd28ab6a | 1718 | |
f5d64037 MM |
1719 | sky2_vlan_mode(sky2->netdev, sky2->netdev->features); |
1720 | netdev_update_features(sky2->netdev); | |
d494eacd | 1721 | |
200ac492 | 1722 | sky2_rx_start(sky2); |
ea0f71e5 MM |
1723 | } |
1724 | ||
0bdb0bd0 | 1725 | /* Setup device IRQ and enable napi to process */ |
1726 | static int sky2_setup_irq(struct sky2_hw *hw, const char *name) | |
1727 | { | |
1728 | struct pci_dev *pdev = hw->pdev; | |
1729 | int err; | |
1730 | ||
1731 | err = request_irq(pdev->irq, sky2_intr, | |
1732 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, | |
1733 | name, hw); | |
1734 | if (err) | |
1735 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); | |
1736 | else { | |
282edcec | 1737 | hw->flags |= SKY2_HW_IRQ_SETUP; |
1738 | ||
0bdb0bd0 | 1739 | napi_enable(&hw->napi); |
1740 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | |
1741 | sky2_read32(hw, B0_IMSK); | |
1742 | } | |
1743 | ||
1744 | return err; | |
1745 | } | |
1746 | ||
1747 | ||
ea0f71e5 | 1748 | /* Bring up network interface. */ |
926d0977 | 1749 | static int sky2_open(struct net_device *dev) |
ea0f71e5 MM |
1750 | { |
1751 | struct sky2_port *sky2 = netdev_priv(dev); | |
1752 | struct sky2_hw *hw = sky2->hw; | |
1753 | unsigned port = sky2->port; | |
1754 | u32 imask; | |
1755 | int err; | |
1756 | ||
1757 | netif_carrier_off(dev); | |
1758 | ||
1759 | err = sky2_alloc_buffers(sky2); | |
1760 | if (err) | |
1761 | goto err_out; | |
1762 | ||
0bdb0bd0 | 1763 | /* With single port, IRQ is setup when device is brought up */ |
1764 | if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) | |
1765 | goto err_out; | |
1766 | ||
ea0f71e5 | 1767 | sky2_hw_up(sky2); |
cd28ab6a | 1768 | |
2240eb4a LS |
1769 | /* Enable interrupts from phy/mac for port */ |
1770 | imask = sky2_read32(hw, B0_IMSK); | |
1771 | ||
1401a800 | 1772 | if (hw->chip_id == CHIP_ID_YUKON_OPT || |
1773 | hw->chip_id == CHIP_ID_YUKON_PRM || | |
1774 | hw->chip_id == CHIP_ID_YUKON_OP_2) | |
1775 | imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ | |
1776 | ||
f4ea431b | 1777 | imask |= portirq_msk[port]; |
e07b1aa8 | 1778 | sky2_write32(hw, B0_IMSK, imask); |
1fd82f3c | 1779 | sky2_read32(hw, B0_IMSK); |
e07b1aa8 | 1780 | |
6c35abae | 1781 | netif_info(sky2, ifup, dev, "enabling interface\n"); |
af18d8b8 | 1782 | |
cd28ab6a SH |
1783 | return 0; |
1784 | ||
1785 | err_out: | |
90bbebb4 | 1786 | sky2_free_buffers(sky2); |
cd28ab6a SH |
1787 | return err; |
1788 | } | |
1789 | ||
793b883e | 1790 | /* Modular subtraction in ring */ |
ee5f68fe | 1791 | static inline int tx_inuse(const struct sky2_port *sky2) |
793b883e | 1792 | { |
ee5f68fe | 1793 | return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); |
793b883e | 1794 | } |
cd28ab6a | 1795 | |
793b883e SH |
1796 | /* Number of list elements available for next tx */ |
1797 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1798 | { |
ee5f68fe | 1799 | return sky2->tx_pending - tx_inuse(sky2); |
cd28ab6a SH |
1800 | } |
1801 | ||
793b883e | 1802 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1803 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1804 | { |
793b883e SH |
1805 | unsigned count; |
1806 | ||
07e31637 SH |
1807 | count = (skb_shinfo(skb)->nr_frags + 1) |
1808 | * (sizeof(dma_addr_t) / sizeof(u32)); | |
793b883e | 1809 | |
89114afd | 1810 | if (skb_is_gso(skb)) |
793b883e | 1811 | ++count; |
07e31637 SH |
1812 | else if (sizeof(dma_addr_t) == sizeof(u32)) |
1813 | ++count; /* possible vlan */ | |
793b883e | 1814 | |
84fa7933 | 1815 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
793b883e SH |
1816 | ++count; |
1817 | ||
1818 | return count; | |
cd28ab6a SH |
1819 | } |
1820 | ||
f6815077 | 1821 | static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) |
6b84daca SH |
1822 | { |
1823 | if (re->flags & TX_MAP_SINGLE) | |
7cd26ce5 FT |
1824 | pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), |
1825 | dma_unmap_len(re, maplen), | |
6b84daca SH |
1826 | PCI_DMA_TODEVICE); |
1827 | else if (re->flags & TX_MAP_PAGE) | |
7cd26ce5 FT |
1828 | pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), |
1829 | dma_unmap_len(re, maplen), | |
6b84daca | 1830 | PCI_DMA_TODEVICE); |
f6815077 | 1831 | re->flags = 0; |
6b84daca SH |
1832 | } |
1833 | ||
793b883e SH |
1834 | /* |
1835 | * Put one packet in ring for transmit. | |
1836 | * A single packet can generate multiple list elements, and | |
1837 | * the number of ring elements will probably be less than the number | |
1838 | * of list elements used. | |
1839 | */ | |
61357325 SH |
1840 | static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, |
1841 | struct net_device *dev) | |
cd28ab6a SH |
1842 | { |
1843 | struct sky2_port *sky2 = netdev_priv(dev); | |
1844 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1845 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1846 | struct tx_ring_info *re; |
9b289c33 | 1847 | unsigned i, len; |
cd28ab6a | 1848 | dma_addr_t mapping; |
5dce95e5 SH |
1849 | u32 upper; |
1850 | u16 slot; | |
cd28ab6a SH |
1851 | u16 mss; |
1852 | u8 ctrl; | |
1853 | ||
2bb8c262 SH |
1854 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) |
1855 | return NETDEV_TX_BUSY; | |
cd28ab6a | 1856 | |
cd28ab6a SH |
1857 | len = skb_headlen(skb); |
1858 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
793b883e | 1859 | |
454e6cb6 SH |
1860 | if (pci_dma_mapping_error(hw->pdev, mapping)) |
1861 | goto mapping_error; | |
1862 | ||
9b289c33 | 1863 | slot = sky2->tx_prod; |
6c35abae JP |
1864 | netif_printk(sky2, tx_queued, KERN_DEBUG, dev, |
1865 | "tx queued, slot %u, len %d\n", slot, skb->len); | |
454e6cb6 | 1866 | |
86c6887e | 1867 | /* Send high bits if needed */ |
5dce95e5 SH |
1868 | upper = upper_32_bits(mapping); |
1869 | if (upper != sky2->tx_last_upper) { | |
9b289c33 | 1870 | le = get_tx_le(sky2, &slot); |
5dce95e5 SH |
1871 | le->addr = cpu_to_le32(upper); |
1872 | sky2->tx_last_upper = upper; | |
793b883e | 1873 | le->opcode = OP_ADDR64 | HW_OWNER; |
793b883e | 1874 | } |
cd28ab6a SH |
1875 | |
1876 | /* Check for TCP Segmentation Offload */ | |
7967168c | 1877 | mss = skb_shinfo(skb)->gso_size; |
793b883e | 1878 | if (mss != 0) { |
ea76e635 SH |
1879 | |
1880 | if (!(hw->flags & SKY2_HW_NEW_LE)) | |
69161611 SH |
1881 | mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); |
1882 | ||
1883 | if (mss != sky2->tx_last_mss) { | |
9b289c33 | 1884 | le = get_tx_le(sky2, &slot); |
69161611 | 1885 | le->addr = cpu_to_le32(mss); |
ea76e635 SH |
1886 | |
1887 | if (hw->flags & SKY2_HW_NEW_LE) | |
69161611 SH |
1888 | le->opcode = OP_MSS | HW_OWNER; |
1889 | else | |
1890 | le->opcode = OP_LRGLEN | HW_OWNER; | |
e07560cd SH |
1891 | sky2->tx_last_mss = mss; |
1892 | } | |
cd28ab6a SH |
1893 | } |
1894 | ||
cd28ab6a | 1895 | ctrl = 0; |
86aa7785 | 1896 | |
d1f13708 | 1897 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ |
df8a39de | 1898 | if (skb_vlan_tag_present(skb)) { |
d1f13708 | 1899 | if (!le) { |
9b289c33 | 1900 | le = get_tx_le(sky2, &slot); |
f65b138c | 1901 | le->addr = 0; |
d1f13708 | 1902 | le->opcode = OP_VLAN|HW_OWNER; |
d1f13708 SH |
1903 | } else |
1904 | le->opcode |= OP_VLAN; | |
df8a39de | 1905 | le->length = cpu_to_be16(skb_vlan_tag_get(skb)); |
d1f13708 SH |
1906 | ctrl |= INS_VLAN; |
1907 | } | |
d1f13708 SH |
1908 | |
1909 | /* Handle TCP checksum offload */ | |
84fa7933 | 1910 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
69161611 | 1911 | /* On Yukon EX (some versions) encoding change. */ |
ea76e635 | 1912 | if (hw->flags & SKY2_HW_AUTO_TX_SUM) |
69161611 SH |
1913 | ctrl |= CALSUM; /* auto checksum */ |
1914 | else { | |
1915 | const unsigned offset = skb_transport_offset(skb); | |
1916 | u32 tcpsum; | |
1917 | ||
1918 | tcpsum = offset << 16; /* sum start */ | |
1919 | tcpsum |= offset + skb->csum_offset; /* sum write */ | |
1920 | ||
1921 | ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1922 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) | |
1923 | ctrl |= UDPTCP; | |
1924 | ||
1925 | if (tcpsum != sky2->tx_tcpsum) { | |
1926 | sky2->tx_tcpsum = tcpsum; | |
1927 | ||
9b289c33 | 1928 | le = get_tx_le(sky2, &slot); |
69161611 SH |
1929 | le->addr = cpu_to_le32(tcpsum); |
1930 | le->length = 0; /* initial checksum value */ | |
1931 | le->ctrl = 1; /* one packet */ | |
1932 | le->opcode = OP_TCPLISW | HW_OWNER; | |
1933 | } | |
1d179332 | 1934 | } |
cd28ab6a SH |
1935 | } |
1936 | ||
6b84daca SH |
1937 | re = sky2->tx_ring + slot; |
1938 | re->flags = TX_MAP_SINGLE; | |
7cd26ce5 FT |
1939 | dma_unmap_addr_set(re, mapaddr, mapping); |
1940 | dma_unmap_len_set(re, maplen, len); | |
6b84daca | 1941 | |
9b289c33 | 1942 | le = get_tx_le(sky2, &slot); |
d6e74b6b | 1943 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
cd28ab6a SH |
1944 | le->length = cpu_to_le16(len); |
1945 | le->ctrl = ctrl; | |
793b883e | 1946 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1947 | |
cd28ab6a SH |
1948 | |
1949 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
291ea614 | 1950 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
cd28ab6a | 1951 | |
950a5a4f | 1952 | mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, |
9e903e08 | 1953 | skb_frag_size(frag), DMA_TO_DEVICE); |
86c6887e | 1954 | |
5d6bcdfe | 1955 | if (dma_mapping_error(&hw->pdev->dev, mapping)) |
454e6cb6 SH |
1956 | goto mapping_unwind; |
1957 | ||
5dce95e5 SH |
1958 | upper = upper_32_bits(mapping); |
1959 | if (upper != sky2->tx_last_upper) { | |
9b289c33 | 1960 | le = get_tx_le(sky2, &slot); |
5dce95e5 SH |
1961 | le->addr = cpu_to_le32(upper); |
1962 | sky2->tx_last_upper = upper; | |
793b883e | 1963 | le->opcode = OP_ADDR64 | HW_OWNER; |
cd28ab6a SH |
1964 | } |
1965 | ||
6b84daca SH |
1966 | re = sky2->tx_ring + slot; |
1967 | re->flags = TX_MAP_PAGE; | |
7cd26ce5 | 1968 | dma_unmap_addr_set(re, mapaddr, mapping); |
9e903e08 | 1969 | dma_unmap_len_set(re, maplen, skb_frag_size(frag)); |
6b84daca | 1970 | |
9b289c33 | 1971 | le = get_tx_le(sky2, &slot); |
d6e74b6b | 1972 | le->addr = cpu_to_le32(lower_32_bits(mapping)); |
9e903e08 | 1973 | le->length = cpu_to_le16(skb_frag_size(frag)); |
cd28ab6a | 1974 | le->ctrl = ctrl; |
793b883e | 1975 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1976 | } |
6cdbbdf3 | 1977 | |
6b84daca | 1978 | re->skb = skb; |
cd28ab6a SH |
1979 | le->ctrl |= EOP; |
1980 | ||
9b289c33 MM |
1981 | sky2->tx_prod = slot; |
1982 | ||
97bda706 SH |
1983 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
1984 | netif_stop_queue(dev); | |
b19666d9 | 1985 | |
ec2a5466 | 1986 | netdev_sent_queue(dev, skb->len); |
290d4de5 | 1987 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1988 | |
cd28ab6a | 1989 | return NETDEV_TX_OK; |
454e6cb6 SH |
1990 | |
1991 | mapping_unwind: | |
ee5f68fe | 1992 | for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { |
454e6cb6 SH |
1993 | re = sky2->tx_ring + i; |
1994 | ||
6b84daca | 1995 | sky2_tx_unmap(hw->pdev, re); |
454e6cb6 SH |
1996 | } |
1997 | ||
454e6cb6 SH |
1998 | mapping_error: |
1999 | if (net_ratelimit()) | |
2000 | dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); | |
2d4186ce | 2001 | dev_kfree_skb_any(skb); |
454e6cb6 | 2002 | return NETDEV_TX_OK; |
cd28ab6a SH |
2003 | } |
2004 | ||
cd28ab6a | 2005 | /* |
793b883e SH |
2006 | * Free ring elements from starting at tx_cons until "done" |
2007 | * | |
481cea4a SH |
2008 | * NB: |
2009 | * 1. The hardware will tell us about partial completion of multi-part | |
291ea614 | 2010 | * buffers so make sure not to free skb to early. |
481cea4a SH |
2011 | * 2. This may run in parallel start_xmit because the it only |
2012 | * looks at the tail of the queue of FIFO (tx_cons), not | |
2013 | * the head (tx_prod) | |
cd28ab6a | 2014 | */ |
d11c13e7 | 2015 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 2016 | { |
d11c13e7 | 2017 | struct net_device *dev = sky2->netdev; |
ec2a5466 | 2018 | u16 idx; |
2019 | unsigned int bytes_compl = 0, pkts_compl = 0; | |
cd28ab6a | 2020 | |
ee5f68fe | 2021 | BUG_ON(done >= sky2->tx_ring_size); |
2224795d | 2022 | |
291ea614 | 2023 | for (idx = sky2->tx_cons; idx != done; |
ee5f68fe | 2024 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { |
291ea614 | 2025 | struct tx_ring_info *re = sky2->tx_ring + idx; |
6b84daca | 2026 | struct sk_buff *skb = re->skb; |
291ea614 | 2027 | |
6b84daca | 2028 | sky2_tx_unmap(sky2->hw->pdev, re); |
bd1c6869 | 2029 | |
6b84daca | 2030 | if (skb) { |
6c35abae JP |
2031 | netif_printk(sky2, tx_done, KERN_DEBUG, dev, |
2032 | "tx done %u\n", idx); | |
3cf26753 | 2033 | |
ec2a5466 | 2034 | pkts_compl++; |
2035 | bytes_compl += skb->len; | |
bd1c6869 | 2036 | |
f6815077 | 2037 | re->skb = NULL; |
724b6942 | 2038 | dev_kfree_skb_any(skb); |
2bf56fe2 | 2039 | |
ee5f68fe | 2040 | sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); |
cd28ab6a | 2041 | } |
793b883e | 2042 | } |
793b883e | 2043 | |
291ea614 | 2044 | sky2->tx_cons = idx; |
50432cb5 | 2045 | smp_mb(); |
ec2a5466 | 2046 | |
2047 | netdev_completed_queue(dev, pkts_compl, bytes_compl); | |
2048 | ||
2049 | u64_stats_update_begin(&sky2->tx_stats.syncp); | |
2050 | sky2->tx_stats.packets += pkts_compl; | |
2051 | sky2->tx_stats.bytes += bytes_compl; | |
2052 | u64_stats_update_end(&sky2->tx_stats.syncp); | |
cd28ab6a SH |
2053 | } |
2054 | ||
264bb4fa | 2055 | static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) |
a510996b | 2056 | { |
a510996b MM |
2057 | /* Disable Force Sync bit and Enable Alloc bit */ |
2058 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
2059 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
2060 | ||
2061 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
2062 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
2063 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
2064 | ||
2065 | /* Reset the PCI FIFO of the async Tx queue */ | |
2066 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), | |
2067 | BMU_RST_SET | BMU_FIFO_RST); | |
2068 | ||
2069 | /* Reset the Tx prefetch units */ | |
2070 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
2071 | PREF_UNIT_RST_SET); | |
2072 | ||
2073 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2074 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
f9687c44 | 2075 | |
2076 | sky2_read32(hw, B0_CTST); | |
a510996b MM |
2077 | } |
2078 | ||
f2b31cb3 | 2079 | static void sky2_hw_down(struct sky2_port *sky2) |
cd28ab6a | 2080 | { |
cd28ab6a SH |
2081 | struct sky2_hw *hw = sky2->hw; |
2082 | unsigned port = sky2->port; | |
f2b31cb3 | 2083 | u16 ctrl; |
cd28ab6a | 2084 | |
d104acaf SH |
2085 | /* Force flow control off */ |
2086 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e | 2087 | |
cd28ab6a SH |
2088 | /* Stop transmitter */ |
2089 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
2090 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
2091 | ||
2092 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 2093 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
2094 | |
2095 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 2096 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
2097 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
2098 | ||
2099 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
2100 | ||
2101 | /* Workaround shared GMAC reset */ | |
8e95a202 JP |
2102 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && |
2103 | port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
2104 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
2105 | ||
cd28ab6a | 2106 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
cd28ab6a | 2107 | |
fb914ebf | 2108 | /* Force any delayed status interrupt and NAPI */ |
6c83504f SH |
2109 | sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); |
2110 | sky2_write32(hw, STAT_TX_TIMER_CNT, 0); | |
2111 | sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); | |
2112 | sky2_read8(hw, STAT_ISR_TIMER_CTRL); | |
2113 | ||
a947a39d MM |
2114 | sky2_rx_stop(sky2); |
2115 | ||
0da6d7b3 | 2116 | spin_lock_bh(&sky2->phy_lock); |
b96936da | 2117 | sky2_phy_power_down(hw, port); |
0da6d7b3 | 2118 | spin_unlock_bh(&sky2->phy_lock); |
d3bcfbeb | 2119 | |
264bb4fa MM |
2120 | sky2_tx_reset(hw, port); |
2121 | ||
481cea4a SH |
2122 | /* Free any pending frames stuck in HW queue */ |
2123 | sky2_tx_complete(sky2, sky2->tx_prod); | |
f2b31cb3 MM |
2124 | } |
2125 | ||
2126 | /* Network shutdown */ | |
926d0977 | 2127 | static int sky2_close(struct net_device *dev) |
f2b31cb3 MM |
2128 | { |
2129 | struct sky2_port *sky2 = netdev_priv(dev); | |
8a0c9228 | 2130 | struct sky2_hw *hw = sky2->hw; |
f2b31cb3 MM |
2131 | |
2132 | /* Never really got started! */ | |
2133 | if (!sky2->tx_le) | |
2134 | return 0; | |
2135 | ||
6c35abae | 2136 | netif_info(sky2, ifdown, dev, "disabling interface\n"); |
f2b31cb3 | 2137 | |
0bdb0bd0 | 2138 | if (hw->ports == 1) { |
1401a800 | 2139 | sky2_write32(hw, B0_IMSK, 0); |
2140 | sky2_read32(hw, B0_IMSK); | |
2141 | ||
0bdb0bd0 | 2142 | napi_disable(&hw->napi); |
2143 | free_irq(hw->pdev->irq, hw); | |
282edcec | 2144 | hw->flags &= ~SKY2_HW_IRQ_SETUP; |
0bdb0bd0 | 2145 | } else { |
1401a800 | 2146 | u32 imask; |
2147 | ||
2148 | /* Disable port IRQ */ | |
2149 | imask = sky2_read32(hw, B0_IMSK); | |
2150 | imask &= ~portirq_msk[sky2->port]; | |
2151 | sky2_write32(hw, B0_IMSK, imask); | |
2152 | sky2_read32(hw, B0_IMSK); | |
2153 | ||
0bdb0bd0 | 2154 | synchronize_irq(hw->pdev->irq); |
2155 | napi_synchronize(&hw->napi); | |
2156 | } | |
8a0c9228 | 2157 | |
f2b31cb3 | 2158 | sky2_hw_down(sky2); |
481cea4a | 2159 | |
90bbebb4 | 2160 | sky2_free_buffers(sky2); |
1b537565 | 2161 | |
cd28ab6a SH |
2162 | return 0; |
2163 | } | |
2164 | ||
2165 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
2166 | { | |
ea76e635 | 2167 | if (hw->flags & SKY2_HW_FIBRE_PHY) |
793b883e SH |
2168 | return SPEED_1000; |
2169 | ||
05745c4a SH |
2170 | if (!(hw->flags & SKY2_HW_GIGABIT)) { |
2171 | if (aux & PHY_M_PS_SPEED_100) | |
2172 | return SPEED_100; | |
2173 | else | |
2174 | return SPEED_10; | |
2175 | } | |
cd28ab6a SH |
2176 | |
2177 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
2178 | case PHY_M_PS_SPEED_1000: | |
2179 | return SPEED_1000; | |
2180 | case PHY_M_PS_SPEED_100: | |
2181 | return SPEED_100; | |
2182 | default: | |
2183 | return SPEED_10; | |
2184 | } | |
2185 | } | |
2186 | ||
2187 | static void sky2_link_up(struct sky2_port *sky2) | |
2188 | { | |
2189 | struct sky2_hw *hw = sky2->hw; | |
2190 | unsigned port = sky2->port; | |
16ad91e1 SH |
2191 | static const char *fc_name[] = { |
2192 | [FC_NONE] = "none", | |
2193 | [FC_TX] = "tx", | |
2194 | [FC_RX] = "rx", | |
2195 | [FC_BOTH] = "both", | |
2196 | }; | |
cd28ab6a | 2197 | |
8e11680f | 2198 | sky2_set_ipg(sky2); |
2199 | ||
38000a94 | 2200 | sky2_enable_rx_tx(sky2); |
cd28ab6a SH |
2201 | |
2202 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
2203 | ||
2204 | netif_carrier_on(sky2->netdev); | |
cd28ab6a | 2205 | |
75e80683 | 2206 | mod_timer(&hw->watchdog_timer, jiffies + 1); |
32c2c300 | 2207 | |
cd28ab6a | 2208 | /* Turn on link LED */ |
793b883e | 2209 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
2210 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
2211 | ||
6c35abae JP |
2212 | netif_info(sky2, link, sky2->netdev, |
2213 | "Link is up at %d Mbps, %s duplex, flow control %s\n", | |
2214 | sky2->speed, | |
2215 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
2216 | fc_name[sky2->flow_status]); | |
cd28ab6a SH |
2217 | } |
2218 | ||
2219 | static void sky2_link_down(struct sky2_port *sky2) | |
2220 | { | |
2221 | struct sky2_hw *hw = sky2->hw; | |
2222 | unsigned port = sky2->port; | |
2223 | u16 reg; | |
2224 | ||
2225 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
2226 | ||
2227 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
2228 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
2229 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
cd28ab6a | 2230 | |
cd28ab6a | 2231 | netif_carrier_off(sky2->netdev); |
cd28ab6a | 2232 | |
809aaaae | 2233 | /* Turn off link LED */ |
cd28ab6a SH |
2234 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); |
2235 | ||
6c35abae | 2236 | netif_info(sky2, link, sky2->netdev, "Link is down\n"); |
2eaba1a2 | 2237 | |
cd28ab6a SH |
2238 | sky2_phy_init(hw, port); |
2239 | } | |
2240 | ||
16ad91e1 SH |
2241 | static enum flow_control sky2_flow(int rx, int tx) |
2242 | { | |
2243 | if (rx) | |
2244 | return tx ? FC_BOTH : FC_RX; | |
2245 | else | |
2246 | return tx ? FC_TX : FC_NONE; | |
2247 | } | |
2248 | ||
793b883e SH |
2249 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
2250 | { | |
2251 | struct sky2_hw *hw = sky2->hw; | |
2252 | unsigned port = sky2->port; | |
da4c1ff4 | 2253 | u16 advert, lpa; |
793b883e | 2254 | |
da4c1ff4 | 2255 | advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); |
793b883e | 2256 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); |
793b883e | 2257 | if (lpa & PHY_M_AN_RF) { |
ada1db5c | 2258 | netdev_err(sky2->netdev, "remote fault\n"); |
793b883e SH |
2259 | return -1; |
2260 | } | |
2261 | ||
793b883e | 2262 | if (!(aux & PHY_M_PS_SPDUP_RES)) { |
ada1db5c | 2263 | netdev_err(sky2->netdev, "speed/duplex mismatch\n"); |
793b883e SH |
2264 | return -1; |
2265 | } | |
2266 | ||
793b883e | 2267 | sky2->speed = sky2_phy_speed(hw, aux); |
7c74ac1c | 2268 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; |
793b883e | 2269 | |
da4c1ff4 SH |
2270 | /* Since the pause result bits seem to in different positions on |
2271 | * different chips. look at registers. | |
2272 | */ | |
ea76e635 | 2273 | if (hw->flags & SKY2_HW_FIBRE_PHY) { |
da4c1ff4 SH |
2274 | /* Shift for bits in fiber PHY */ |
2275 | advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); | |
2276 | lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); | |
2277 | ||
2278 | if (advert & ADVERTISE_1000XPAUSE) | |
2279 | advert |= ADVERTISE_PAUSE_CAP; | |
2280 | if (advert & ADVERTISE_1000XPSE_ASYM) | |
2281 | advert |= ADVERTISE_PAUSE_ASYM; | |
2282 | if (lpa & LPA_1000XPAUSE) | |
2283 | lpa |= LPA_PAUSE_CAP; | |
2284 | if (lpa & LPA_1000XPAUSE_ASYM) | |
2285 | lpa |= LPA_PAUSE_ASYM; | |
2286 | } | |
793b883e | 2287 | |
da4c1ff4 SH |
2288 | sky2->flow_status = FC_NONE; |
2289 | if (advert & ADVERTISE_PAUSE_CAP) { | |
2290 | if (lpa & LPA_PAUSE_CAP) | |
2291 | sky2->flow_status = FC_BOTH; | |
2292 | else if (advert & ADVERTISE_PAUSE_ASYM) | |
2293 | sky2->flow_status = FC_RX; | |
2294 | } else if (advert & ADVERTISE_PAUSE_ASYM) { | |
2295 | if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) | |
2296 | sky2->flow_status = FC_TX; | |
2297 | } | |
793b883e | 2298 | |
8e95a202 JP |
2299 | if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && |
2300 | !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) | |
16ad91e1 | 2301 | sky2->flow_status = FC_NONE; |
2eaba1a2 | 2302 | |
da4c1ff4 | 2303 | if (sky2->flow_status & FC_TX) |
793b883e SH |
2304 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
2305 | else | |
2306 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
2307 | ||
2308 | return 0; | |
2309 | } | |
cd28ab6a | 2310 | |
e07b1aa8 SH |
2311 | /* Interrupt from PHY */ |
2312 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 2313 | { |
e07b1aa8 SH |
2314 | struct net_device *dev = hw->dev[port]; |
2315 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
2316 | u16 istatus, phystat; |
2317 | ||
ebc646f6 SH |
2318 | if (!netif_running(dev)) |
2319 | return; | |
2320 | ||
e07b1aa8 SH |
2321 | spin_lock(&sky2->phy_lock); |
2322 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
2323 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
2324 | ||
6c35abae JP |
2325 | netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", |
2326 | istatus, phystat); | |
cd28ab6a | 2327 | |
0ea065e5 | 2328 | if (istatus & PHY_M_IS_AN_COMPL) { |
9badba25 | 2329 | if (sky2_autoneg_done(sky2, phystat) == 0 && |
2330 | !netif_carrier_ok(dev)) | |
793b883e SH |
2331 | sky2_link_up(sky2); |
2332 | goto out; | |
2333 | } | |
cd28ab6a | 2334 | |
793b883e SH |
2335 | if (istatus & PHY_M_IS_LSP_CHANGE) |
2336 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 2337 | |
793b883e SH |
2338 | if (istatus & PHY_M_IS_DUP_CHANGE) |
2339 | sky2->duplex = | |
2340 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 2341 | |
793b883e SH |
2342 | if (istatus & PHY_M_IS_LST_CHANGE) { |
2343 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 2344 | sky2_link_up(sky2); |
793b883e SH |
2345 | else |
2346 | sky2_link_down(sky2); | |
cd28ab6a | 2347 | } |
793b883e | 2348 | out: |
e07b1aa8 | 2349 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
2350 | } |
2351 | ||
0f5aac70 SH |
2352 | /* Special quick link interrupt (Yukon-2 Optima only) */ |
2353 | static void sky2_qlink_intr(struct sky2_hw *hw) | |
2354 | { | |
2355 | struct sky2_port *sky2 = netdev_priv(hw->dev[0]); | |
2356 | u32 imask; | |
2357 | u16 phy; | |
2358 | ||
2359 | /* disable irq */ | |
2360 | imask = sky2_read32(hw, B0_IMSK); | |
2361 | imask &= ~Y2_IS_PHY_QLNK; | |
2362 | sky2_write32(hw, B0_IMSK, imask); | |
2363 | ||
2364 | /* reset PHY Link Detect */ | |
2365 | phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); | |
a40ccc68 | 2366 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
0f5aac70 | 2367 | sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); |
a40ccc68 | 2368 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
0f5aac70 SH |
2369 | |
2370 | sky2_link_up(sky2); | |
2371 | } | |
2372 | ||
62335ab0 | 2373 | /* Transmit timeout is only called if we are running, carrier is up |
302d1252 SH |
2374 | * and tx queue is full (stopped). |
2375 | */ | |
cd28ab6a SH |
2376 | static void sky2_tx_timeout(struct net_device *dev) |
2377 | { | |
2378 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 | 2379 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a | 2380 | |
6c35abae | 2381 | netif_err(sky2, timer, dev, "tx timeout\n"); |
cd28ab6a | 2382 | |
ada1db5c JP |
2383 | netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", |
2384 | sky2->tx_cons, sky2->tx_prod, | |
2385 | sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
2386 | sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); | |
8f24664d | 2387 | |
81906791 SH |
2388 | /* can't restart safely under softirq */ |
2389 | schedule_work(&hw->restart_work); | |
cd28ab6a SH |
2390 | } |
2391 | ||
2392 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |
2393 | { | |
6b1a3aef SH |
2394 | struct sky2_port *sky2 = netdev_priv(dev); |
2395 | struct sky2_hw *hw = sky2->hw; | |
b628ed98 | 2396 | unsigned port = sky2->port; |
6b1a3aef SH |
2397 | int err; |
2398 | u16 ctl, mode; | |
e07b1aa8 | 2399 | u32 imask; |
cd28ab6a | 2400 | |
6b1a3aef SH |
2401 | if (!netif_running(dev)) { |
2402 | dev->mtu = new_mtu; | |
f5d64037 | 2403 | netdev_update_features(dev); |
6b1a3aef SH |
2404 | return 0; |
2405 | } | |
2406 | ||
e07b1aa8 | 2407 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef | 2408 | sky2_write32(hw, B0_IMSK, 0); |
ea589e9b | 2409 | sky2_read32(hw, B0_IMSK); |
6b1a3aef | 2410 | |
860e9538 | 2411 | netif_trans_update(dev); /* prevent tx timeout */ |
bea3348e | 2412 | napi_disable(&hw->napi); |
df01093b | 2413 | netif_tx_disable(dev); |
018d1c66 | 2414 | |
e07b1aa8 SH |
2415 | synchronize_irq(hw->pdev->irq); |
2416 | ||
39dbd958 | 2417 | if (!(hw->flags & SKY2_HW_RAM_BUFFER)) |
69161611 | 2418 | sky2_set_tx_stfwd(hw, port); |
b628ed98 SH |
2419 | |
2420 | ctl = gma_read16(hw, port, GM_GP_CTRL); | |
2421 | gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
6b1a3aef SH |
2422 | sky2_rx_stop(sky2); |
2423 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
2424 | |
2425 | dev->mtu = new_mtu; | |
f5d64037 | 2426 | netdev_update_features(dev); |
14d0263f | 2427 | |
8e11680f | 2428 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; |
2429 | if (sky2->speed > SPEED_100) | |
2430 | mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); | |
2431 | else | |
2432 | mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); | |
6b1a3aef SH |
2433 | |
2434 | if (dev->mtu > ETH_DATA_LEN) | |
2435 | mode |= GM_SMOD_JUMBO_ENA; | |
2436 | ||
b628ed98 | 2437 | gma_write16(hw, port, GM_SERIAL_MODE, mode); |
cd28ab6a | 2438 | |
b628ed98 | 2439 | sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 2440 | |
200ac492 MM |
2441 | err = sky2_alloc_rx_skbs(sky2); |
2442 | if (!err) | |
2443 | sky2_rx_start(sky2); | |
2444 | else | |
2445 | sky2_rx_clean(sky2); | |
e07b1aa8 | 2446 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 2447 | |
d1d08d12 | 2448 | sky2_read32(hw, B0_Y2_SP_LISR); |
bea3348e SH |
2449 | napi_enable(&hw->napi); |
2450 | ||
1b537565 SH |
2451 | if (err) |
2452 | dev_close(dev); | |
2453 | else { | |
b628ed98 | 2454 | gma_write16(hw, port, GM_GP_CTRL, ctl); |
1b537565 | 2455 | |
1b537565 SH |
2456 | netif_wake_queue(dev); |
2457 | } | |
2458 | ||
cd28ab6a SH |
2459 | return err; |
2460 | } | |
2461 | ||
857504d0 | 2462 | static inline bool needs_copy(const struct rx_ring_info *re, |
2463 | unsigned length) | |
2464 | { | |
2465 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
2466 | /* Some architectures need the IP header to be aligned */ | |
2467 | if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32))) | |
2468 | return true; | |
2469 | #endif | |
2470 | return length < copybreak; | |
2471 | } | |
2472 | ||
14d0263f SH |
2473 | /* For small just reuse existing skb for next receive */ |
2474 | static struct sk_buff *receive_copy(struct sky2_port *sky2, | |
2475 | const struct rx_ring_info *re, | |
2476 | unsigned length) | |
2477 | { | |
2478 | struct sk_buff *skb; | |
2479 | ||
89d71a66 | 2480 | skb = netdev_alloc_skb_ip_align(sky2->netdev, length); |
14d0263f | 2481 | if (likely(skb)) { |
14d0263f SH |
2482 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, |
2483 | length, PCI_DMA_FROMDEVICE); | |
d626f62b | 2484 | skb_copy_from_linear_data(re->skb, skb->data, length); |
14d0263f SH |
2485 | skb->ip_summed = re->skb->ip_summed; |
2486 | skb->csum = re->skb->csum; | |
b408f94d | 2487 | skb_copy_hash(skb, re->skb); |
88dccf5b | 2488 | skb->vlan_proto = re->skb->vlan_proto; |
e072b3fa | 2489 | skb->vlan_tci = re->skb->vlan_tci; |
3f42941b | 2490 | |
14d0263f SH |
2491 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, |
2492 | length, PCI_DMA_FROMDEVICE); | |
88dccf5b | 2493 | re->skb->vlan_proto = 0; |
e072b3fa | 2494 | re->skb->vlan_tci = 0; |
b408f94d | 2495 | skb_clear_hash(re->skb); |
14d0263f | 2496 | re->skb->ip_summed = CHECKSUM_NONE; |
489b10c1 | 2497 | skb_put(skb, length); |
14d0263f SH |
2498 | } |
2499 | return skb; | |
2500 | } | |
2501 | ||
2502 | /* Adjust length of skb with fragments to match received data */ | |
2503 | static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, | |
2504 | unsigned int length) | |
2505 | { | |
2506 | int i, num_frags; | |
2507 | unsigned int size; | |
2508 | ||
2509 | /* put header into skb */ | |
2510 | size = min(length, hdr_space); | |
2511 | skb->tail += size; | |
2512 | skb->len += size; | |
2513 | length -= size; | |
2514 | ||
2515 | num_frags = skb_shinfo(skb)->nr_frags; | |
2516 | for (i = 0; i < num_frags; i++) { | |
2517 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2518 | ||
2519 | if (length == 0) { | |
2520 | /* don't need this page */ | |
950a5a4f | 2521 | __skb_frag_unref(frag); |
14d0263f SH |
2522 | --skb_shinfo(skb)->nr_frags; |
2523 | } else { | |
2524 | size = min(length, (unsigned) PAGE_SIZE); | |
2525 | ||
9e903e08 | 2526 | skb_frag_size_set(frag, size); |
14d0263f | 2527 | skb->data_len += size; |
7ae60b3f | 2528 | skb->truesize += PAGE_SIZE; |
14d0263f SH |
2529 | skb->len += size; |
2530 | length -= size; | |
2531 | } | |
2532 | } | |
2533 | } | |
2534 | ||
2535 | /* Normal packet - take skb from ring element and put in a new one */ | |
2536 | static struct sk_buff *receive_new(struct sky2_port *sky2, | |
2537 | struct rx_ring_info *re, | |
2538 | unsigned int length) | |
2539 | { | |
3fbd9187 | 2540 | struct sk_buff *skb; |
2541 | struct rx_ring_info nre; | |
14d0263f SH |
2542 | unsigned hdr_space = sky2->rx_data_size; |
2543 | ||
68ac3191 | 2544 | nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); |
3fbd9187 | 2545 | if (unlikely(!nre.skb)) |
2546 | goto nobuf; | |
2547 | ||
2548 | if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) | |
2549 | goto nomap; | |
14d0263f SH |
2550 | |
2551 | skb = re->skb; | |
2552 | sky2_rx_unmap_skb(sky2->hw->pdev, re); | |
14d0263f | 2553 | prefetch(skb->data); |
3fbd9187 | 2554 | *re = nre; |
14d0263f SH |
2555 | |
2556 | if (skb_shinfo(skb)->nr_frags) | |
2557 | skb_put_frags(skb, hdr_space, length); | |
2558 | else | |
489b10c1 | 2559 | skb_put(skb, length); |
14d0263f | 2560 | return skb; |
3fbd9187 | 2561 | |
2562 | nomap: | |
2563 | dev_kfree_skb(nre.skb); | |
2564 | nobuf: | |
2565 | return NULL; | |
14d0263f SH |
2566 | } |
2567 | ||
cd28ab6a SH |
2568 | /* |
2569 | * Receive one packet. | |
d571b694 | 2570 | * For larger packets, get new buffer. |
cd28ab6a | 2571 | */ |
497d7c86 | 2572 | static struct sk_buff *sky2_receive(struct net_device *dev, |
cd28ab6a SH |
2573 | u16 length, u32 status) |
2574 | { | |
497d7c86 | 2575 | struct sky2_port *sky2 = netdev_priv(dev); |
291ea614 | 2576 | struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 2577 | struct sk_buff *skb = NULL; |
d6532232 SH |
2578 | u16 count = (status & GMR_FS_LEN) >> 16; |
2579 | ||
6c35abae JP |
2580 | netif_printk(sky2, rx_status, KERN_DEBUG, dev, |
2581 | "rx slot %u status 0x%x len %d\n", | |
2582 | sky2->rx_next, status, length); | |
cd28ab6a | 2583 | |
793b883e | 2584 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 2585 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 2586 | |
df8a39de | 2587 | if (skb_vlan_tag_present(re->skb)) |
e072b3fa | 2588 | count -= VLAN_HLEN; /* Account for vlan tag */ |
2589 | ||
3b12e014 SH |
2590 | /* This chip has hardware problems that generates bogus status. |
2591 | * So do only marginal checking and expect higher level protocols | |
2592 | * to handle crap frames. | |
2593 | */ | |
2594 | if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && | |
2595 | sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && | |
2596 | length != count) | |
2597 | goto okay; | |
2598 | ||
42eeea01 | 2599 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
2600 | goto error; |
2601 | ||
42eeea01 SH |
2602 | if (!(status & GMR_FS_RX_OK)) |
2603 | goto resubmit; | |
2604 | ||
d6532232 SH |
2605 | /* if length reported by DMA does not match PHY, packet was truncated */ |
2606 | if (length != count) | |
0885a30b | 2607 | goto error; |
71749531 | 2608 | |
3b12e014 | 2609 | okay: |
857504d0 | 2610 | if (needs_copy(re, length)) |
14d0263f SH |
2611 | skb = receive_copy(sky2, re, length); |
2612 | else | |
2613 | skb = receive_new(sky2, re, length); | |
90c30335 SH |
2614 | |
2615 | dev->stats.rx_dropped += (skb == NULL); | |
2616 | ||
793b883e | 2617 | resubmit: |
14d0263f | 2618 | sky2_rx_submit(sky2, re); |
79e57d32 | 2619 | |
cd28ab6a SH |
2620 | return skb; |
2621 | ||
2622 | error: | |
7138a0f5 | 2623 | ++dev->stats.rx_errors; |
6e15b712 | 2624 | |
6c35abae JP |
2625 | if (net_ratelimit()) |
2626 | netif_info(sky2, rx_err, dev, | |
2627 | "rx error, status 0x%x length %d\n", status, length); | |
793b883e | 2628 | |
793b883e | 2629 | goto resubmit; |
cd28ab6a SH |
2630 | } |
2631 | ||
e07b1aa8 SH |
2632 | /* Transmit complete */ |
2633 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 2634 | { |
e07b1aa8 | 2635 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 2636 | |
8a0c9228 | 2637 | if (netif_running(dev)) { |
e07b1aa8 | 2638 | sky2_tx_complete(sky2, last); |
8a0c9228 | 2639 | |
926d0977 | 2640 | /* Wake unless it's detached, and called e.g. from sky2_close() */ |
8a0c9228 MM |
2641 | if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) |
2642 | netif_wake_queue(dev); | |
2643 | } | |
cd28ab6a SH |
2644 | } |
2645 | ||
37e5a243 | 2646 | static inline void sky2_skb_rx(const struct sky2_port *sky2, |
e072b3fa | 2647 | struct sk_buff *skb) |
37e5a243 | 2648 | { |
37e5a243 SH |
2649 | if (skb->ip_summed == CHECKSUM_NONE) |
2650 | netif_receive_skb(skb); | |
2651 | else | |
2652 | napi_gro_receive(&sky2->hw->napi, skb); | |
2653 | } | |
2654 | ||
bf15fe99 SH |
2655 | static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, |
2656 | unsigned packets, unsigned bytes) | |
2657 | { | |
0885a30b | 2658 | struct net_device *dev = hw->dev[port]; |
2659 | struct sky2_port *sky2 = netdev_priv(dev); | |
bf15fe99 | 2660 | |
0885a30b | 2661 | if (packets == 0) |
2662 | return; | |
2663 | ||
2664 | u64_stats_update_begin(&sky2->rx_stats.syncp); | |
2665 | sky2->rx_stats.packets += packets; | |
2666 | sky2->rx_stats.bytes += bytes; | |
2667 | u64_stats_update_end(&sky2->rx_stats.syncp); | |
2668 | ||
2669 | dev->last_rx = jiffies; | |
2670 | sky2_rx_update(netdev_priv(dev), rxqaddr[port]); | |
bf15fe99 SH |
2671 | } |
2672 | ||
375c5688 | 2673 | static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) |
2674 | { | |
2675 | /* If this happens then driver assuming wrong format for chip type */ | |
2676 | BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); | |
2677 | ||
2678 | /* Both checksum counters are programmed to start at | |
2679 | * the same offset, so unless there is a problem they | |
2680 | * should match. This failure is an early indication that | |
2681 | * hardware receive checksumming won't work. | |
2682 | */ | |
2683 | if (likely((u16)(status >> 16) == (u16)status)) { | |
2684 | struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; | |
2685 | skb->ip_summed = CHECKSUM_COMPLETE; | |
2686 | skb->csum = le16_to_cpu(status); | |
2687 | } else { | |
2688 | dev_notice(&sky2->hw->pdev->dev, | |
2689 | "%s: receive checksum problem (status = %#x)\n", | |
2690 | sky2->netdev->name, status); | |
2691 | ||
f5d64037 MM |
2692 | /* Disable checksum offload |
2693 | * It will be reenabled on next ndo_set_features, but if it's | |
2694 | * really broken, will get disabled again | |
2695 | */ | |
2696 | sky2->netdev->features &= ~NETIF_F_RXCSUM; | |
375c5688 | 2697 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2698 | BMU_DIS_RX_CHKSUM); | |
2699 | } | |
2700 | } | |
2701 | ||
e072b3fa | 2702 | static void sky2_rx_tag(struct sky2_port *sky2, u16 length) |
2703 | { | |
2704 | struct sk_buff *skb; | |
2705 | ||
2706 | skb = sky2->rx_ring[sky2->rx_next].skb; | |
86a9bad3 | 2707 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length)); |
e072b3fa | 2708 | } |
2709 | ||
bf73130d SH |
2710 | static void sky2_rx_hash(struct sky2_port *sky2, u32 status) |
2711 | { | |
2712 | struct sk_buff *skb; | |
2713 | ||
2714 | skb = sky2->rx_ring[sky2->rx_next].skb; | |
b408f94d | 2715 | skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3); |
bf73130d SH |
2716 | } |
2717 | ||
e07b1aa8 | 2718 | /* Process status response ring */ |
26691830 | 2719 | static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) |
cd28ab6a | 2720 | { |
e07b1aa8 | 2721 | int work_done = 0; |
bf15fe99 SH |
2722 | unsigned int total_bytes[2] = { 0 }; |
2723 | unsigned int total_packets[2] = { 0 }; | |
a8fd6266 | 2724 | |
21ceda26 EB |
2725 | if (to_do <= 0) |
2726 | return work_done; | |
2727 | ||
af2a58ac | 2728 | rmb(); |
26691830 | 2729 | do { |
55c9dd35 | 2730 | struct sky2_port *sky2; |
13210ce5 | 2731 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
ab5adecb | 2732 | unsigned port; |
13210ce5 | 2733 | struct net_device *dev; |
cd28ab6a | 2734 | struct sk_buff *skb; |
cd28ab6a SH |
2735 | u32 status; |
2736 | u16 length; | |
ab5adecb SH |
2737 | u8 opcode = le->opcode; |
2738 | ||
2739 | if (!(opcode & HW_OWNER)) | |
2740 | break; | |
cd28ab6a | 2741 | |
efe91932 | 2742 | hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); |
bea86103 | 2743 | |
ab5adecb | 2744 | port = le->css & CSS_LINK_BIT; |
69161611 | 2745 | dev = hw->dev[port]; |
13210ce5 | 2746 | sky2 = netdev_priv(dev); |
f65b138c SH |
2747 | length = le16_to_cpu(le->length); |
2748 | status = le32_to_cpu(le->status); | |
cd28ab6a | 2749 | |
ab5adecb SH |
2750 | le->opcode = 0; |
2751 | switch (opcode & ~HW_OWNER) { | |
cd28ab6a | 2752 | case OP_RXSTAT: |
bf15fe99 SH |
2753 | total_packets[port]++; |
2754 | total_bytes[port] += length; | |
90c30335 | 2755 | |
497d7c86 | 2756 | skb = sky2_receive(dev, length, status); |
90c30335 | 2757 | if (!skb) |
55c9dd35 | 2758 | break; |
13210ce5 | 2759 | |
69161611 | 2760 | /* This chip reports checksum status differently */ |
05745c4a | 2761 | if (hw->flags & SKY2_HW_NEW_LE) { |
f5d64037 | 2762 | if ((dev->features & NETIF_F_RXCSUM) && |
69161611 SH |
2763 | (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && |
2764 | (le->css & CSS_TCPUDPCSOK)) | |
2765 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2766 | else | |
2767 | skb->ip_summed = CHECKSUM_NONE; | |
2768 | } | |
2769 | ||
13210ce5 | 2770 | skb->protocol = eth_type_trans(skb, dev); |
e072b3fa | 2771 | sky2_skb_rx(sky2, skb); |
13210ce5 | 2772 | |
22e11703 | 2773 | /* Stop after net poll weight */ |
13210ce5 SH |
2774 | if (++work_done >= to_do) |
2775 | goto exit_loop; | |
cd28ab6a SH |
2776 | break; |
2777 | ||
d1f13708 | 2778 | case OP_RXVLAN: |
e072b3fa | 2779 | sky2_rx_tag(sky2, length); |
d1f13708 SH |
2780 | break; |
2781 | ||
2782 | case OP_RXCHKSVLAN: | |
e072b3fa | 2783 | sky2_rx_tag(sky2, length); |
d1f13708 | 2784 | /* fall through */ |
cd28ab6a | 2785 | case OP_RXCHKS: |
f5d64037 | 2786 | if (likely(dev->features & NETIF_F_RXCSUM)) |
375c5688 | 2787 | sky2_rx_checksum(sky2, status); |
cd28ab6a SH |
2788 | break; |
2789 | ||
bf73130d SH |
2790 | case OP_RSS_HASH: |
2791 | sky2_rx_hash(sky2, status); | |
2792 | break; | |
2793 | ||
cd28ab6a | 2794 | case OP_TXINDEXLE: |
13b97b74 | 2795 | /* TX index reports status for both ports */ |
f55925d7 | 2796 | sky2_tx_done(hw->dev[0], status & 0xfff); |
e07b1aa8 SH |
2797 | if (hw->dev[1]) |
2798 | sky2_tx_done(hw->dev[1], | |
2799 | ((status >> 24) & 0xff) | |
2800 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
2801 | break; |
2802 | ||
cd28ab6a SH |
2803 | default: |
2804 | if (net_ratelimit()) | |
fe3881cf | 2805 | pr_warn("unknown status opcode 0x%x\n", opcode); |
cd28ab6a | 2806 | } |
26691830 | 2807 | } while (hw->st_idx != idx); |
cd28ab6a | 2808 | |
fe2a24df SH |
2809 | /* Fully processed status ring so clear irq */ |
2810 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
2811 | ||
13210ce5 | 2812 | exit_loop: |
bf15fe99 SH |
2813 | sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); |
2814 | sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); | |
22e11703 | 2815 | |
e07b1aa8 | 2816 | return work_done; |
cd28ab6a SH |
2817 | } |
2818 | ||
2819 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
2820 | { | |
2821 | struct net_device *dev = hw->dev[port]; | |
2822 | ||
3be92a70 | 2823 | if (net_ratelimit()) |
ada1db5c | 2824 | netdev_info(dev, "hw error interrupt status 0x%x\n", status); |
cd28ab6a SH |
2825 | |
2826 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 | 2827 | if (net_ratelimit()) |
ada1db5c | 2828 | netdev_err(dev, "ram data read parity error\n"); |
cd28ab6a SH |
2829 | /* Clear IRQ */ |
2830 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2831 | } | |
2832 | ||
2833 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 | 2834 | if (net_ratelimit()) |
ada1db5c | 2835 | netdev_err(dev, "ram data write parity error\n"); |
cd28ab6a SH |
2836 | |
2837 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2838 | } | |
2839 | ||
2840 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 | 2841 | if (net_ratelimit()) |
ada1db5c | 2842 | netdev_err(dev, "MAC parity error\n"); |
cd28ab6a SH |
2843 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2844 | } | |
2845 | ||
2846 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 | 2847 | if (net_ratelimit()) |
ada1db5c | 2848 | netdev_err(dev, "RX parity error\n"); |
cd28ab6a SH |
2849 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2850 | } | |
2851 | ||
2852 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 | 2853 | if (net_ratelimit()) |
ada1db5c | 2854 | netdev_err(dev, "TCP segmentation error\n"); |
cd28ab6a SH |
2855 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2856 | } | |
2857 | } | |
2858 | ||
2859 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2860 | { | |
555382cb | 2861 | struct pci_dev *pdev = hw->pdev; |
cd28ab6a | 2862 | u32 status = sky2_read32(hw, B0_HWE_ISRC); |
555382cb SH |
2863 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); |
2864 | ||
2865 | status &= hwmsk; | |
cd28ab6a | 2866 | |
793b883e | 2867 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2868 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2869 | |
2870 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2871 | u16 pci_err; |
2872 | ||
a40ccc68 | 2873 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
b32f40c4 | 2874 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
3be92a70 | 2875 | if (net_ratelimit()) |
555382cb | 2876 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
b02a9258 | 2877 | pci_err); |
cd28ab6a | 2878 | |
b32f40c4 | 2879 | sky2_pci_write16(hw, PCI_STATUS, |
167f53d0 | 2880 | pci_err | PCI_STATUS_ERROR_BITS); |
a40ccc68 | 2881 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
2882 | } |
2883 | ||
2884 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2885 | /* PCI-Express uncorrectable Error occurred */ |
555382cb | 2886 | u32 err; |
cd28ab6a | 2887 | |
a40ccc68 | 2888 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
7782c8c4 SH |
2889 | err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
2890 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, | |
2891 | 0xfffffffful); | |
3be92a70 | 2892 | if (net_ratelimit()) |
555382cb | 2893 | dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); |
cf06ffb4 | 2894 | |
7782c8c4 | 2895 | sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); |
a40ccc68 | 2896 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
2897 | } |
2898 | ||
2899 | if (status & Y2_HWE_L1_MASK) | |
2900 | sky2_hw_error(hw, 0, status); | |
2901 | status >>= 8; | |
2902 | if (status & Y2_HWE_L1_MASK) | |
2903 | sky2_hw_error(hw, 1, status); | |
2904 | } | |
2905 | ||
2906 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2907 | { | |
2908 | struct net_device *dev = hw->dev[port]; | |
2909 | struct sky2_port *sky2 = netdev_priv(dev); | |
2910 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2911 | ||
6c35abae | 2912 | netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); |
cd28ab6a | 2913 | |
a3caeada SH |
2914 | if (status & GM_IS_RX_CO_OV) |
2915 | gma_read16(hw, port, GM_RX_IRQ_SRC); | |
2916 | ||
2917 | if (status & GM_IS_TX_CO_OV) | |
2918 | gma_read16(hw, port, GM_TX_IRQ_SRC); | |
2919 | ||
cd28ab6a | 2920 | if (status & GM_IS_RX_FF_OR) { |
7138a0f5 | 2921 | ++dev->stats.rx_fifo_errors; |
cd28ab6a SH |
2922 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
2923 | } | |
2924 | ||
2925 | if (status & GM_IS_TX_FF_UR) { | |
7138a0f5 | 2926 | ++dev->stats.tx_fifo_errors; |
cd28ab6a SH |
2927 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
2928 | } | |
cd28ab6a SH |
2929 | } |
2930 | ||
40b01727 | 2931 | /* This should never happen it is a bug. */ |
c119731d | 2932 | static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) |
d257924e SH |
2933 | { |
2934 | struct net_device *dev = hw->dev[port]; | |
c119731d | 2935 | u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); |
d257924e | 2936 | |
ada1db5c | 2937 | dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", |
c119731d SH |
2938 | dev->name, (unsigned) q, (unsigned) idx, |
2939 | (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); | |
d257924e | 2940 | |
40b01727 | 2941 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); |
d257924e | 2942 | } |
cd28ab6a | 2943 | |
75e80683 SH |
2944 | static int sky2_rx_hung(struct net_device *dev) |
2945 | { | |
2946 | struct sky2_port *sky2 = netdev_priv(dev); | |
2947 | struct sky2_hw *hw = sky2->hw; | |
2948 | unsigned port = sky2->port; | |
2949 | unsigned rxq = rxqaddr[port]; | |
2950 | u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); | |
2951 | u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); | |
2952 | u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); | |
2953 | u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); | |
2954 | ||
2955 | /* If idle and MAC or PCI is stuck */ | |
2956 | if (sky2->check.last == dev->last_rx && | |
2957 | ((mac_rp == sky2->check.mac_rp && | |
2958 | mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || | |
2959 | /* Check if the PCI RX hang */ | |
2960 | (fifo_rp == sky2->check.fifo_rp && | |
2961 | fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { | |
ada1db5c JP |
2962 | netdev_printk(KERN_DEBUG, dev, |
2963 | "hung mac %d:%d fifo %d (%d:%d)\n", | |
2964 | mac_lev, mac_rp, fifo_lev, | |
2965 | fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); | |
75e80683 SH |
2966 | return 1; |
2967 | } else { | |
2968 | sky2->check.last = dev->last_rx; | |
2969 | sky2->check.mac_rp = mac_rp; | |
2970 | sky2->check.mac_lev = mac_lev; | |
2971 | sky2->check.fifo_rp = fifo_rp; | |
2972 | sky2->check.fifo_lev = fifo_lev; | |
2973 | return 0; | |
2974 | } | |
2975 | } | |
2976 | ||
32c2c300 | 2977 | static void sky2_watchdog(unsigned long arg) |
d27ed387 | 2978 | { |
01bd7564 | 2979 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
d27ed387 | 2980 | |
75e80683 | 2981 | /* Check for lost IRQ once a second */ |
32c2c300 | 2982 | if (sky2_read32(hw, B0_ISRC)) { |
bea3348e | 2983 | napi_schedule(&hw->napi); |
75e80683 SH |
2984 | } else { |
2985 | int i, active = 0; | |
2986 | ||
2987 | for (i = 0; i < hw->ports; i++) { | |
bea3348e | 2988 | struct net_device *dev = hw->dev[i]; |
75e80683 SH |
2989 | if (!netif_running(dev)) |
2990 | continue; | |
2991 | ++active; | |
2992 | ||
2993 | /* For chips with Rx FIFO, check if stuck */ | |
39dbd958 | 2994 | if ((hw->flags & SKY2_HW_RAM_BUFFER) && |
75e80683 | 2995 | sky2_rx_hung(dev)) { |
ada1db5c | 2996 | netdev_info(dev, "receiver hang detected\n"); |
75e80683 SH |
2997 | schedule_work(&hw->restart_work); |
2998 | return; | |
2999 | } | |
3000 | } | |
3001 | ||
3002 | if (active == 0) | |
3003 | return; | |
32c2c300 | 3004 | } |
01bd7564 | 3005 | |
75e80683 | 3006 | mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); |
d27ed387 SH |
3007 | } |
3008 | ||
40b01727 SH |
3009 | /* Hardware/software error handling */ |
3010 | static void sky2_err_intr(struct sky2_hw *hw, u32 status) | |
cd28ab6a | 3011 | { |
40b01727 SH |
3012 | if (net_ratelimit()) |
3013 | dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); | |
cd28ab6a | 3014 | |
1e5f1283 SH |
3015 | if (status & Y2_IS_HW_ERR) |
3016 | sky2_hw_intr(hw); | |
d257924e | 3017 | |
1e5f1283 SH |
3018 | if (status & Y2_IS_IRQ_MAC1) |
3019 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 3020 | |
1e5f1283 SH |
3021 | if (status & Y2_IS_IRQ_MAC2) |
3022 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 3023 | |
1e5f1283 | 3024 | if (status & Y2_IS_CHK_RX1) |
c119731d | 3025 | sky2_le_error(hw, 0, Q_R1); |
d257924e | 3026 | |
1e5f1283 | 3027 | if (status & Y2_IS_CHK_RX2) |
c119731d | 3028 | sky2_le_error(hw, 1, Q_R2); |
d257924e | 3029 | |
1e5f1283 | 3030 | if (status & Y2_IS_CHK_TXA1) |
c119731d | 3031 | sky2_le_error(hw, 0, Q_XA1); |
d257924e | 3032 | |
1e5f1283 | 3033 | if (status & Y2_IS_CHK_TXA2) |
c119731d | 3034 | sky2_le_error(hw, 1, Q_XA2); |
40b01727 SH |
3035 | } |
3036 | ||
bea3348e | 3037 | static int sky2_poll(struct napi_struct *napi, int work_limit) |
40b01727 | 3038 | { |
bea3348e | 3039 | struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); |
40b01727 | 3040 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
6f535763 | 3041 | int work_done = 0; |
26691830 | 3042 | u16 idx; |
40b01727 SH |
3043 | |
3044 | if (unlikely(status & Y2_IS_ERROR)) | |
3045 | sky2_err_intr(hw, status); | |
3046 | ||
3047 | if (status & Y2_IS_IRQ_PHY1) | |
3048 | sky2_phy_intr(hw, 0); | |
3049 | ||
3050 | if (status & Y2_IS_IRQ_PHY2) | |
3051 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 3052 | |
0f5aac70 SH |
3053 | if (status & Y2_IS_PHY_QLNK) |
3054 | sky2_qlink_intr(hw); | |
3055 | ||
26691830 SH |
3056 | while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { |
3057 | work_done += sky2_status_intr(hw, work_limit - work_done, idx); | |
6f535763 DM |
3058 | |
3059 | if (work_done >= work_limit) | |
26691830 SH |
3060 | goto done; |
3061 | } | |
6f535763 | 3062 | |
f4b63ea0 | 3063 | napi_complete_done(napi, work_done); |
26691830 SH |
3064 | sky2_read32(hw, B0_Y2_SP_LISR); |
3065 | done: | |
6f535763 | 3066 | |
bea3348e | 3067 | return work_done; |
e07b1aa8 SH |
3068 | } |
3069 | ||
7d12e780 | 3070 | static irqreturn_t sky2_intr(int irq, void *dev_id) |
e07b1aa8 SH |
3071 | { |
3072 | struct sky2_hw *hw = dev_id; | |
e07b1aa8 SH |
3073 | u32 status; |
3074 | ||
3075 | /* Reading this mask interrupts as side effect */ | |
3076 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
d663d181 ML |
3077 | if (status == 0 || status == ~0) { |
3078 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
e07b1aa8 | 3079 | return IRQ_NONE; |
d663d181 | 3080 | } |
793b883e | 3081 | |
e07b1aa8 | 3082 | prefetch(&hw->st_le[hw->st_idx]); |
bea3348e SH |
3083 | |
3084 | napi_schedule(&hw->napi); | |
793b883e | 3085 | |
cd28ab6a SH |
3086 | return IRQ_HANDLED; |
3087 | } | |
3088 | ||
3089 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3090 | static void sky2_netpoll(struct net_device *dev) | |
3091 | { | |
3092 | struct sky2_port *sky2 = netdev_priv(dev); | |
3093 | ||
bea3348e | 3094 | napi_schedule(&sky2->hw->napi); |
cd28ab6a SH |
3095 | } |
3096 | #endif | |
3097 | ||
3098 | /* Chip internal frequency for clock calculations */ | |
05745c4a | 3099 | static u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 3100 | { |
793b883e | 3101 | switch (hw->chip_id) { |
cd28ab6a | 3102 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 3103 | case CHIP_ID_YUKON_EC_U: |
93745494 | 3104 | case CHIP_ID_YUKON_EX: |
ed4d4161 | 3105 | case CHIP_ID_YUKON_SUPR: |
0ce8b98d | 3106 | case CHIP_ID_YUKON_UL_2: |
0f5aac70 | 3107 | case CHIP_ID_YUKON_OPT: |
4fb99cd6 | 3108 | case CHIP_ID_YUKON_PRM: |
3109 | case CHIP_ID_YUKON_OP_2: | |
05745c4a SH |
3110 | return 125; |
3111 | ||
cd28ab6a | 3112 | case CHIP_ID_YUKON_FE: |
05745c4a SH |
3113 | return 100; |
3114 | ||
3115 | case CHIP_ID_YUKON_FE_P: | |
3116 | return 50; | |
3117 | ||
3118 | case CHIP_ID_YUKON_XL: | |
3119 | return 156; | |
3120 | ||
3121 | default: | |
3122 | BUG(); | |
cd28ab6a SH |
3123 | } |
3124 | } | |
3125 | ||
fb17358f | 3126 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 3127 | { |
fb17358f | 3128 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
3129 | } |
3130 | ||
fb17358f | 3131 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 3132 | { |
fb17358f | 3133 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
3134 | } |
3135 | ||
fb17358f | 3136 | |
853e3f4c | 3137 | static int sky2_init(struct sky2_hw *hw) |
cd28ab6a | 3138 | { |
b89165f2 | 3139 | u8 t8; |
cd28ab6a | 3140 | |
167f53d0 | 3141 | /* Enable all clocks and check for bad PCI access */ |
b32f40c4 | 3142 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
451af335 | 3143 | |
cd28ab6a | 3144 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 3145 | |
cd28ab6a | 3146 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
ea76e635 SH |
3147 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
3148 | ||
060b946c | 3149 | switch (hw->chip_id) { |
ea76e635 | 3150 | case CHIP_ID_YUKON_XL: |
39dbd958 | 3151 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; |
bf73130d SH |
3152 | if (hw->chip_rev < CHIP_REV_YU_XL_A2) |
3153 | hw->flags |= SKY2_HW_RSS_BROKEN; | |
ea76e635 SH |
3154 | break; |
3155 | ||
3156 | case CHIP_ID_YUKON_EC_U: | |
3157 | hw->flags = SKY2_HW_GIGABIT | |
3158 | | SKY2_HW_NEWER_PHY | |
3159 | | SKY2_HW_ADV_POWER_CTL; | |
3160 | break; | |
3161 | ||
3162 | case CHIP_ID_YUKON_EX: | |
3163 | hw->flags = SKY2_HW_GIGABIT | |
3164 | | SKY2_HW_NEWER_PHY | |
3165 | | SKY2_HW_NEW_LE | |
aa5ca96c | 3166 | | SKY2_HW_ADV_POWER_CTL |
3167 | | SKY2_HW_RSS_CHKSUM; | |
ea76e635 SH |
3168 | |
3169 | /* New transmit checksum */ | |
3170 | if (hw->chip_rev != CHIP_REV_YU_EX_B0) | |
3171 | hw->flags |= SKY2_HW_AUTO_TX_SUM; | |
3172 | break; | |
3173 | ||
3174 | case CHIP_ID_YUKON_EC: | |
3175 | /* This rev is really old, and requires untested workarounds */ | |
3176 | if (hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
3177 | dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); | |
3178 | return -EOPNOTSUPP; | |
3179 | } | |
bf73130d | 3180 | hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; |
ea76e635 SH |
3181 | break; |
3182 | ||
3183 | case CHIP_ID_YUKON_FE: | |
bf73130d | 3184 | hw->flags = SKY2_HW_RSS_BROKEN; |
ea76e635 SH |
3185 | break; |
3186 | ||
05745c4a SH |
3187 | case CHIP_ID_YUKON_FE_P: |
3188 | hw->flags = SKY2_HW_NEWER_PHY | |
3189 | | SKY2_HW_NEW_LE | |
3190 | | SKY2_HW_AUTO_TX_SUM | |
3191 | | SKY2_HW_ADV_POWER_CTL; | |
86aa7785 SH |
3192 | |
3193 | /* The workaround for status conflicts VLAN tag detection. */ | |
3194 | if (hw->chip_rev == CHIP_REV_YU_FE2_A0) | |
aa5ca96c | 3195 | hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; |
05745c4a | 3196 | break; |
ed4d4161 SH |
3197 | |
3198 | case CHIP_ID_YUKON_SUPR: | |
3199 | hw->flags = SKY2_HW_GIGABIT | |
3200 | | SKY2_HW_NEWER_PHY | |
3201 | | SKY2_HW_NEW_LE | |
3202 | | SKY2_HW_AUTO_TX_SUM | |
3203 | | SKY2_HW_ADV_POWER_CTL; | |
aa5ca96c | 3204 | |
3205 | if (hw->chip_rev == CHIP_REV_YU_SU_A0) | |
3206 | hw->flags |= SKY2_HW_RSS_CHKSUM; | |
ed4d4161 SH |
3207 | break; |
3208 | ||
0ce8b98d | 3209 | case CHIP_ID_YUKON_UL_2: |
b338682d TI |
3210 | hw->flags = SKY2_HW_GIGABIT |
3211 | | SKY2_HW_ADV_POWER_CTL; | |
3212 | break; | |
3213 | ||
0f5aac70 | 3214 | case CHIP_ID_YUKON_OPT: |
4fb99cd6 | 3215 | case CHIP_ID_YUKON_PRM: |
3216 | case CHIP_ID_YUKON_OP_2: | |
0ce8b98d | 3217 | hw->flags = SKY2_HW_GIGABIT |
b338682d | 3218 | | SKY2_HW_NEW_LE |
0ce8b98d SH |
3219 | | SKY2_HW_ADV_POWER_CTL; |
3220 | break; | |
3221 | ||
ea76e635 | 3222 | default: |
b02a9258 SH |
3223 | dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", |
3224 | hw->chip_id); | |
cd28ab6a SH |
3225 | return -EOPNOTSUPP; |
3226 | } | |
3227 | ||
ea76e635 SH |
3228 | hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); |
3229 | if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') | |
3230 | hw->flags |= SKY2_HW_FIBRE_PHY; | |
290d4de5 | 3231 | |
e3173832 SH |
3232 | hw->ports = 1; |
3233 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
3234 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
3235 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
3236 | ++hw->ports; | |
3237 | } | |
3238 | ||
74a61ebf MM |
3239 | if (sky2_read8(hw, B2_E_0)) |
3240 | hw->flags |= SKY2_HW_RAM_BUFFER; | |
3241 | ||
e3173832 SH |
3242 | return 0; |
3243 | } | |
3244 | ||
3245 | static void sky2_reset(struct sky2_hw *hw) | |
3246 | { | |
555382cb | 3247 | struct pci_dev *pdev = hw->pdev; |
e3173832 | 3248 | u16 status; |
1a10ccae | 3249 | int i; |
555382cb | 3250 | u32 hwe_mask = Y2_HWE_ALL_MASK; |
e3173832 | 3251 | |
cd28ab6a | 3252 | /* disable ASF */ |
acd12dde | 3253 | if (hw->chip_id == CHIP_ID_YUKON_EX |
3254 | || hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
3255 | sky2_write32(hw, CPU_WDOG, 0); | |
4f44d8ba SH |
3256 | status = sky2_read16(hw, HCU_CCSR); |
3257 | status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | | |
3258 | HCU_CCSR_UC_STATE_MSK); | |
acd12dde | 3259 | /* |
3260 | * CPU clock divider shouldn't be used because | |
3261 | * - ASF firmware may malfunction | |
3262 | * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks | |
3263 | */ | |
3264 | status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; | |
4f44d8ba | 3265 | sky2_write16(hw, HCU_CCSR, status); |
acd12dde | 3266 | sky2_write32(hw, CPU_WDOG, 0); |
4f44d8ba SH |
3267 | } else |
3268 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
3269 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
cd28ab6a SH |
3270 | |
3271 | /* do a SW reset */ | |
3272 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
3273 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
3274 | ||
ac93a394 SH |
3275 | /* allow writes to PCI config */ |
3276 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3277 | ||
cd28ab6a | 3278 | /* clear PCI errors, if any */ |
b32f40c4 | 3279 | status = sky2_pci_read16(hw, PCI_STATUS); |
167f53d0 | 3280 | status |= PCI_STATUS_ERROR_BITS; |
b32f40c4 | 3281 | sky2_pci_write16(hw, PCI_STATUS, status); |
cd28ab6a SH |
3282 | |
3283 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
3284 | ||
1a10ccae | 3285 | if (pci_is_pcie(pdev)) { |
7782c8c4 SH |
3286 | sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, |
3287 | 0xfffffffful); | |
555382cb SH |
3288 | |
3289 | /* If error bit is stuck on ignore it */ | |
3290 | if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) | |
3291 | dev_info(&pdev->dev, "ignoring stuck error report bit\n"); | |
7782c8c4 | 3292 | else |
555382cb SH |
3293 | hwe_mask |= Y2_IS_PCI_EXP; |
3294 | } | |
cd28ab6a | 3295 | |
ae306cca | 3296 | sky2_power_on(hw); |
a40ccc68 | 3297 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
cd28ab6a SH |
3298 | |
3299 | for (i = 0; i < hw->ports; i++) { | |
3300 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
3301 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
69161611 | 3302 | |
ed4d4161 SH |
3303 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
3304 | hw->chip_id == CHIP_ID_YUKON_SUPR) | |
69161611 SH |
3305 | sky2_write16(hw, SK_REG(i, GMAC_CTRL), |
3306 | GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | |
3307 | | GMC_BYP_RETR_ON); | |
877c8570 SH |
3308 | |
3309 | } | |
3310 | ||
3311 | if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { | |
3312 | /* enable MACSec clock gating */ | |
3313 | sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); | |
cd28ab6a SH |
3314 | } |
3315 | ||
4fb99cd6 | 3316 | if (hw->chip_id == CHIP_ID_YUKON_OPT || |
3317 | hw->chip_id == CHIP_ID_YUKON_PRM || | |
3318 | hw->chip_id == CHIP_ID_YUKON_OP_2) { | |
0f5aac70 | 3319 | u16 reg; |
0f5aac70 | 3320 | |
4fb99cd6 | 3321 | if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { |
0f5aac70 SH |
3322 | /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ |
3323 | sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); | |
3324 | ||
3325 | /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ | |
3326 | reg = 10; | |
4fb99cd6 | 3327 | |
3328 | /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ | |
3329 | sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); | |
0f5aac70 SH |
3330 | } else { |
3331 | /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ | |
3332 | reg = 3; | |
3333 | } | |
3334 | ||
3335 | reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; | |
4fb99cd6 | 3336 | reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; |
0f5aac70 SH |
3337 | |
3338 | /* reset PHY Link Detect */ | |
a40ccc68 | 3339 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
0f5aac70 SH |
3340 | sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); |
3341 | ||
0f5aac70 SH |
3342 | /* check if PSMv2 was running before */ |
3343 | reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); | |
1a10ccae | 3344 | if (reg & PCI_EXP_LNKCTL_ASPMC) |
0f5aac70 | 3345 | /* restore the PCIe Link Control register */ |
1a10ccae JM |
3346 | sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, |
3347 | reg); | |
3348 | ||
0e767324 ML |
3349 | if (hw->chip_id == CHIP_ID_YUKON_PRM && |
3350 | hw->chip_rev == CHIP_REV_YU_PRM_A0) { | |
3351 | /* change PHY Interrupt polarity to low active */ | |
3352 | reg = sky2_read16(hw, GPHY_CTRL); | |
3353 | sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); | |
3354 | ||
3355 | /* adapt HW for low active PHY Interrupt */ | |
3356 | reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); | |
3357 | sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); | |
3358 | } | |
3359 | ||
a40ccc68 | 3360 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
0f5aac70 SH |
3361 | |
3362 | /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ | |
3363 | sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); | |
3364 | } | |
3365 | ||
793b883e SH |
3366 | /* Clear I2C IRQ noise */ |
3367 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
3368 | |
3369 | /* turn off hardware timer (unused) */ | |
3370 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3371 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 3372 | |
69634ee7 SH |
3373 | /* Turn off descriptor polling */ |
3374 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
3375 | |
3376 | /* Turn off receive timestamp */ | |
3377 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 3378 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
3379 | |
3380 | /* enable the Tx Arbiters */ | |
3381 | for (i = 0; i < hw->ports; i++) | |
3382 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
3383 | ||
3384 | /* Initialize ram interface */ | |
3385 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 3386 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
3387 | |
3388 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
3389 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
3390 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
3391 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
3392 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
3393 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
3394 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
3395 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
3396 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
3397 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
3398 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
3399 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
3400 | } | |
3401 | ||
555382cb | 3402 | sky2_write32(hw, B0_HWE_IMSK, hwe_mask); |
cd28ab6a | 3403 | |
cd28ab6a | 3404 | for (i = 0; i < hw->ports; i++) |
d3bcfbeb | 3405 | sky2_gmac_reset(hw, i); |
cd28ab6a | 3406 | |
efe91932 | 3407 | memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); |
cd28ab6a SH |
3408 | hw->st_idx = 0; |
3409 | ||
3410 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
3411 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
3412 | ||
3413 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 3414 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
3415 | |
3416 | /* Set the list last index */ | |
efe91932 | 3417 | sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); |
cd28ab6a | 3418 | |
290d4de5 SH |
3419 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
3420 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 3421 | |
290d4de5 SH |
3422 | /* set Status-FIFO ISR watermark */ |
3423 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
3424 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
3425 | else | |
3426 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 3427 | |
290d4de5 | 3428 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
3429 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
3430 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 3431 | |
793b883e | 3432 | /* enable status unit */ |
cd28ab6a SH |
3433 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
3434 | ||
3435 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
3436 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
3437 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
e3173832 SH |
3438 | } |
3439 | ||
af18d8b8 SH |
3440 | /* Take device down (offline). |
3441 | * Equivalent to doing dev_stop() but this does not | |
25985edc | 3442 | * inform upper layers of the transition. |
af18d8b8 SH |
3443 | */ |
3444 | static void sky2_detach(struct net_device *dev) | |
3445 | { | |
3446 | if (netif_running(dev)) { | |
c36531b9 | 3447 | netif_tx_lock(dev); |
af18d8b8 | 3448 | netif_device_detach(dev); /* stop txq */ |
c36531b9 | 3449 | netif_tx_unlock(dev); |
926d0977 | 3450 | sky2_close(dev); |
af18d8b8 SH |
3451 | } |
3452 | } | |
3453 | ||
3454 | /* Bring device back after doing sky2_detach */ | |
3455 | static int sky2_reattach(struct net_device *dev) | |
3456 | { | |
3457 | int err = 0; | |
3458 | ||
3459 | if (netif_running(dev)) { | |
926d0977 | 3460 | err = sky2_open(dev); |
af18d8b8 | 3461 | if (err) { |
ada1db5c | 3462 | netdev_info(dev, "could not restart %d\n", err); |
af18d8b8 SH |
3463 | dev_close(dev); |
3464 | } else { | |
3465 | netif_device_attach(dev); | |
3466 | sky2_set_multicast(dev); | |
3467 | } | |
3468 | } | |
3469 | ||
3470 | return err; | |
3471 | } | |
3472 | ||
d72ff8fa | 3473 | static void sky2_all_down(struct sky2_hw *hw) |
81906791 | 3474 | { |
af18d8b8 | 3475 | int i; |
81906791 | 3476 | |
282edcec | 3477 | if (hw->flags & SKY2_HW_IRQ_SETUP) { |
282edcec | 3478 | sky2_write32(hw, B0_IMSK, 0); |
ea589e9b | 3479 | sky2_read32(hw, B0_IMSK); |
1401a800 | 3480 | |
1401a800 | 3481 | synchronize_irq(hw->pdev->irq); |
282edcec | 3482 | napi_disable(&hw->napi); |
3483 | } | |
8a0c9228 MM |
3484 | |
3485 | for (i = 0; i < hw->ports; i++) { | |
3486 | struct net_device *dev = hw->dev[i]; | |
3487 | struct sky2_port *sky2 = netdev_priv(dev); | |
3488 | ||
3489 | if (!netif_running(dev)) | |
3490 | continue; | |
3491 | ||
3492 | netif_carrier_off(dev); | |
3493 | netif_tx_disable(dev); | |
3494 | sky2_hw_down(sky2); | |
3495 | } | |
d72ff8fa | 3496 | } |
8a0c9228 | 3497 | |
d72ff8fa MM |
3498 | static void sky2_all_up(struct sky2_hw *hw) |
3499 | { | |
3500 | u32 imask = Y2_IS_BASE; | |
3501 | int i; | |
81906791 | 3502 | |
8a0c9228 MM |
3503 | for (i = 0; i < hw->ports; i++) { |
3504 | struct net_device *dev = hw->dev[i]; | |
3505 | struct sky2_port *sky2 = netdev_priv(dev); | |
3506 | ||
3507 | if (!netif_running(dev)) | |
3508 | continue; | |
3509 | ||
3510 | sky2_hw_up(sky2); | |
37652522 | 3511 | sky2_set_multicast(dev); |
d72ff8fa | 3512 | imask |= portirq_msk[i]; |
8a0c9228 MM |
3513 | netif_wake_queue(dev); |
3514 | } | |
3515 | ||
282edcec | 3516 | if (hw->flags & SKY2_HW_IRQ_SETUP) { |
1401a800 | 3517 | sky2_write32(hw, B0_IMSK, imask); |
3518 | sky2_read32(hw, B0_IMSK); | |
3519 | sky2_read32(hw, B0_Y2_SP_LISR); | |
3520 | napi_enable(&hw->napi); | |
3521 | } | |
d72ff8fa MM |
3522 | } |
3523 | ||
3524 | static void sky2_restart(struct work_struct *work) | |
3525 | { | |
3526 | struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); | |
3527 | ||
3528 | rtnl_lock(); | |
3529 | ||
3530 | sky2_all_down(hw); | |
3531 | sky2_reset(hw); | |
3532 | sky2_all_up(hw); | |
81906791 | 3533 | |
81906791 SH |
3534 | rtnl_unlock(); |
3535 | } | |
3536 | ||
e3173832 SH |
3537 | static inline u8 sky2_wol_supported(const struct sky2_hw *hw) |
3538 | { | |
3539 | return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; | |
3540 | } | |
3541 | ||
3542 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3543 | { | |
3544 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3545 | ||
3546 | wol->supported = sky2_wol_supported(sky2->hw); | |
3547 | wol->wolopts = sky2->wol; | |
3548 | } | |
3549 | ||
3550 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3551 | { | |
3552 | struct sky2_port *sky2 = netdev_priv(dev); | |
3553 | struct sky2_hw *hw = sky2->hw; | |
0f333d10 RW |
3554 | bool enable_wakeup = false; |
3555 | int i; | |
cd28ab6a | 3556 | |
8e95a202 JP |
3557 | if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || |
3558 | !device_can_wakeup(&hw->pdev->dev)) | |
e3173832 SH |
3559 | return -EOPNOTSUPP; |
3560 | ||
3561 | sky2->wol = wol->wolopts; | |
0f333d10 RW |
3562 | |
3563 | for (i = 0; i < hw->ports; i++) { | |
3564 | struct net_device *dev = hw->dev[i]; | |
3565 | struct sky2_port *sky2 = netdev_priv(dev); | |
3566 | ||
3567 | if (sky2->wol) | |
3568 | enable_wakeup = true; | |
3569 | } | |
3570 | device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); | |
3571 | ||
cd28ab6a SH |
3572 | return 0; |
3573 | } | |
3574 | ||
28bd181a | 3575 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a | 3576 | { |
b89165f2 SH |
3577 | if (sky2_is_copper(hw)) { |
3578 | u32 modes = SUPPORTED_10baseT_Half | |
3579 | | SUPPORTED_10baseT_Full | |
3580 | | SUPPORTED_100baseT_Half | |
2aca31e7 | 3581 | | SUPPORTED_100baseT_Full; |
cd28ab6a | 3582 | |
ea76e635 | 3583 | if (hw->flags & SKY2_HW_GIGABIT) |
cd28ab6a | 3584 | modes |= SUPPORTED_1000baseT_Half |
b89165f2 SH |
3585 | | SUPPORTED_1000baseT_Full; |
3586 | return modes; | |
cd28ab6a | 3587 | } else |
2aca31e7 SH |
3588 | return SUPPORTED_1000baseT_Half |
3589 | | SUPPORTED_1000baseT_Full; | |
cd28ab6a SH |
3590 | } |
3591 | ||
793b883e | 3592 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
3593 | { |
3594 | struct sky2_port *sky2 = netdev_priv(dev); | |
3595 | struct sky2_hw *hw = sky2->hw; | |
3596 | ||
3597 | ecmd->transceiver = XCVR_INTERNAL; | |
3598 | ecmd->supported = sky2_supported_modes(hw); | |
3599 | ecmd->phy_address = PHY_ADDR_MARV; | |
b89165f2 | 3600 | if (sky2_is_copper(hw)) { |
cd28ab6a | 3601 | ecmd->port = PORT_TP; |
70739497 | 3602 | ethtool_cmd_speed_set(ecmd, sky2->speed); |
2aca31e7 | 3603 | ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; |
b89165f2 | 3604 | } else { |
70739497 | 3605 | ethtool_cmd_speed_set(ecmd, SPEED_1000); |
cd28ab6a | 3606 | ecmd->port = PORT_FIBRE; |
2aca31e7 | 3607 | ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
b89165f2 | 3608 | } |
cd28ab6a SH |
3609 | |
3610 | ecmd->advertising = sky2->advertising; | |
0ea065e5 SH |
3611 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) |
3612 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
cd28ab6a SH |
3613 | ecmd->duplex = sky2->duplex; |
3614 | return 0; | |
3615 | } | |
3616 | ||
3617 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3618 | { | |
3619 | struct sky2_port *sky2 = netdev_priv(dev); | |
3620 | const struct sky2_hw *hw = sky2->hw; | |
3621 | u32 supported = sky2_supported_modes(hw); | |
3622 | ||
3623 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2aca31e7 SH |
3624 | if (ecmd->advertising & ~supported) |
3625 | return -EINVAL; | |
3626 | ||
3627 | if (sky2_is_copper(hw)) | |
3628 | sky2->advertising = ecmd->advertising | | |
3629 | ADVERTISED_TP | | |
3630 | ADVERTISED_Autoneg; | |
3631 | else | |
3632 | sky2->advertising = ecmd->advertising | | |
3633 | ADVERTISED_FIBRE | | |
3634 | ADVERTISED_Autoneg; | |
3635 | ||
0ea065e5 | 3636 | sky2->flags |= SKY2_FLAG_AUTO_SPEED; |
cd28ab6a SH |
3637 | sky2->duplex = -1; |
3638 | sky2->speed = -1; | |
3639 | } else { | |
3640 | u32 setting; | |
25db0338 | 3641 | u32 speed = ethtool_cmd_speed(ecmd); |
cd28ab6a | 3642 | |
25db0338 | 3643 | switch (speed) { |
cd28ab6a SH |
3644 | case SPEED_1000: |
3645 | if (ecmd->duplex == DUPLEX_FULL) | |
3646 | setting = SUPPORTED_1000baseT_Full; | |
3647 | else if (ecmd->duplex == DUPLEX_HALF) | |
3648 | setting = SUPPORTED_1000baseT_Half; | |
3649 | else | |
3650 | return -EINVAL; | |
3651 | break; | |
3652 | case SPEED_100: | |
3653 | if (ecmd->duplex == DUPLEX_FULL) | |
3654 | setting = SUPPORTED_100baseT_Full; | |
3655 | else if (ecmd->duplex == DUPLEX_HALF) | |
3656 | setting = SUPPORTED_100baseT_Half; | |
3657 | else | |
3658 | return -EINVAL; | |
3659 | break; | |
3660 | ||
3661 | case SPEED_10: | |
3662 | if (ecmd->duplex == DUPLEX_FULL) | |
3663 | setting = SUPPORTED_10baseT_Full; | |
3664 | else if (ecmd->duplex == DUPLEX_HALF) | |
3665 | setting = SUPPORTED_10baseT_Half; | |
3666 | else | |
3667 | return -EINVAL; | |
3668 | break; | |
3669 | default: | |
3670 | return -EINVAL; | |
3671 | } | |
3672 | ||
3673 | if ((setting & supported) == 0) | |
3674 | return -EINVAL; | |
3675 | ||
25db0338 | 3676 | sky2->speed = speed; |
cd28ab6a | 3677 | sky2->duplex = ecmd->duplex; |
0ea065e5 | 3678 | sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; |
cd28ab6a SH |
3679 | } |
3680 | ||
d1b139c0 | 3681 | if (netif_running(dev)) { |
1b537565 | 3682 | sky2_phy_reinit(sky2); |
d1b139c0 SH |
3683 | sky2_set_multicast(dev); |
3684 | } | |
cd28ab6a SH |
3685 | |
3686 | return 0; | |
3687 | } | |
3688 | ||
3689 | static void sky2_get_drvinfo(struct net_device *dev, | |
3690 | struct ethtool_drvinfo *info) | |
3691 | { | |
3692 | struct sky2_port *sky2 = netdev_priv(dev); | |
3693 | ||
68aad78c RJ |
3694 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
3695 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
68aad78c RJ |
3696 | strlcpy(info->bus_info, pci_name(sky2->hw->pdev), |
3697 | sizeof(info->bus_info)); | |
cd28ab6a SH |
3698 | } |
3699 | ||
3700 | static const struct sky2_stat { | |
793b883e SH |
3701 | char name[ETH_GSTRING_LEN]; |
3702 | u16 offset; | |
cd28ab6a SH |
3703 | } sky2_stats[] = { |
3704 | { "tx_bytes", GM_TXO_OK_HI }, | |
3705 | { "rx_bytes", GM_RXO_OK_HI }, | |
3706 | { "tx_broadcast", GM_TXF_BC_OK }, | |
3707 | { "rx_broadcast", GM_RXF_BC_OK }, | |
3708 | { "tx_multicast", GM_TXF_MC_OK }, | |
3709 | { "rx_multicast", GM_RXF_MC_OK }, | |
3710 | { "tx_unicast", GM_TXF_UC_OK }, | |
3711 | { "rx_unicast", GM_RXF_UC_OK }, | |
3712 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
3713 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 3714 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
3715 | { "late_collision",GM_TXF_LAT_COL }, |
3716 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 3717 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 3718 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 3719 | |
d2604540 | 3720 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 3721 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
3722 | { "rx_64_byte_packets", GM_RXF_64B }, |
3723 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
3724 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
3725 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
3726 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
3727 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
3728 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 3729 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
3730 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
3731 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 3732 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
3733 | |
3734 | { "tx_64_byte_packets", GM_TXF_64B }, | |
3735 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
3736 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
3737 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
3738 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
3739 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
3740 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
3741 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
3742 | }; |
3743 | ||
cd28ab6a SH |
3744 | static u32 sky2_get_msglevel(struct net_device *netdev) |
3745 | { | |
3746 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3747 | return sky2->msg_enable; | |
3748 | } | |
3749 | ||
9a7ae0a9 SH |
3750 | static int sky2_nway_reset(struct net_device *dev) |
3751 | { | |
3752 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 | 3753 | |
0ea065e5 | 3754 | if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) |
9a7ae0a9 SH |
3755 | return -EINVAL; |
3756 | ||
1b537565 | 3757 | sky2_phy_reinit(sky2); |
d1b139c0 | 3758 | sky2_set_multicast(dev); |
9a7ae0a9 SH |
3759 | |
3760 | return 0; | |
3761 | } | |
3762 | ||
793b883e | 3763 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
3764 | { |
3765 | struct sky2_hw *hw = sky2->hw; | |
3766 | unsigned port = sky2->port; | |
3767 | int i; | |
3768 | ||
0885a30b | 3769 | data[0] = get_stats64(hw, port, GM_TXO_OK_LO); |
3770 | data[1] = get_stats64(hw, port, GM_RXO_OK_LO); | |
cd28ab6a | 3771 | |
793b883e | 3772 | for (i = 2; i < count; i++) |
0885a30b | 3773 | data[i] = get_stats32(hw, port, sky2_stats[i].offset); |
cd28ab6a SH |
3774 | } |
3775 | ||
cd28ab6a SH |
3776 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
3777 | { | |
3778 | struct sky2_port *sky2 = netdev_priv(netdev); | |
3779 | sky2->msg_enable = value; | |
3780 | } | |
3781 | ||
b9f2c044 | 3782 | static int sky2_get_sset_count(struct net_device *dev, int sset) |
cd28ab6a | 3783 | { |
b9f2c044 JG |
3784 | switch (sset) { |
3785 | case ETH_SS_STATS: | |
3786 | return ARRAY_SIZE(sky2_stats); | |
3787 | default: | |
3788 | return -EOPNOTSUPP; | |
3789 | } | |
cd28ab6a SH |
3790 | } |
3791 | ||
3792 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 3793 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
3794 | { |
3795 | struct sky2_port *sky2 = netdev_priv(dev); | |
3796 | ||
793b883e | 3797 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
3798 | } |
3799 | ||
793b883e | 3800 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
3801 | { |
3802 | int i; | |
3803 | ||
3804 | switch (stringset) { | |
3805 | case ETH_SS_STATS: | |
3806 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
3807 | memcpy(data + i * ETH_GSTRING_LEN, | |
3808 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
3809 | break; | |
3810 | } | |
3811 | } | |
3812 | ||
cd28ab6a SH |
3813 | static int sky2_set_mac_address(struct net_device *dev, void *p) |
3814 | { | |
3815 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
3816 | struct sky2_hw *hw = sky2->hw; |
3817 | unsigned port = sky2->port; | |
3818 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
3819 | |
3820 | if (!is_valid_ether_addr(addr->sa_data)) | |
3821 | return -EADDRNOTAVAIL; | |
3822 | ||
cd28ab6a | 3823 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 3824 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 3825 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 3826 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 3827 | dev->dev_addr, ETH_ALEN); |
1b537565 | 3828 | |
a8ab1ec0 SH |
3829 | /* virtual address for data */ |
3830 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
3831 | ||
3832 | /* physical address: used for pause frames */ | |
3833 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
3834 | |
3835 | return 0; | |
cd28ab6a SH |
3836 | } |
3837 | ||
060b946c | 3838 | static inline void sky2_add_filter(u8 filter[8], const u8 *addr) |
a052b52f SH |
3839 | { |
3840 | u32 bit; | |
3841 | ||
3842 | bit = ether_crc(ETH_ALEN, addr) & 63; | |
3843 | filter[bit >> 3] |= 1 << (bit & 7); | |
3844 | } | |
3845 | ||
cd28ab6a SH |
3846 | static void sky2_set_multicast(struct net_device *dev) |
3847 | { | |
3848 | struct sky2_port *sky2 = netdev_priv(dev); | |
3849 | struct sky2_hw *hw = sky2->hw; | |
3850 | unsigned port = sky2->port; | |
22bedad3 | 3851 | struct netdev_hw_addr *ha; |
cd28ab6a SH |
3852 | u16 reg; |
3853 | u8 filter[8]; | |
a052b52f SH |
3854 | int rx_pause; |
3855 | static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; | |
cd28ab6a | 3856 | |
a052b52f | 3857 | rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); |
cd28ab6a SH |
3858 | memset(filter, 0, sizeof(filter)); |
3859 | ||
3860 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
3861 | reg |= GM_RXCR_UCF_ENA; | |
3862 | ||
d571b694 | 3863 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 3864 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
a052b52f | 3865 | else if (dev->flags & IFF_ALLMULTI) |
cd28ab6a | 3866 | memset(filter, 0xff, sizeof(filter)); |
4cd24eaf | 3867 | else if (netdev_mc_empty(dev) && !rx_pause) |
cd28ab6a SH |
3868 | reg &= ~GM_RXCR_MCF_ENA; |
3869 | else { | |
cd28ab6a SH |
3870 | reg |= GM_RXCR_MCF_ENA; |
3871 | ||
a052b52f SH |
3872 | if (rx_pause) |
3873 | sky2_add_filter(filter, pause_mc_addr); | |
3874 | ||
22bedad3 JP |
3875 | netdev_for_each_mc_addr(ha, dev) |
3876 | sky2_add_filter(filter, ha->addr); | |
cd28ab6a SH |
3877 | } |
3878 | ||
cd28ab6a | 3879 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 3880 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 3881 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 3882 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 3883 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 3884 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 3885 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 3886 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
3887 | |
3888 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
3889 | } | |
3890 | ||
0885a30b | 3891 | static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, |
3892 | struct rtnl_link_stats64 *stats) | |
3893 | { | |
3894 | struct sky2_port *sky2 = netdev_priv(dev); | |
3895 | struct sky2_hw *hw = sky2->hw; | |
3896 | unsigned port = sky2->port; | |
3897 | unsigned int start; | |
3898 | u64 _bytes, _packets; | |
3899 | ||
3900 | do { | |
57a7744e | 3901 | start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp); |
0885a30b | 3902 | _bytes = sky2->rx_stats.bytes; |
3903 | _packets = sky2->rx_stats.packets; | |
57a7744e | 3904 | } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start)); |
0885a30b | 3905 | |
3906 | stats->rx_packets = _packets; | |
3907 | stats->rx_bytes = _bytes; | |
3908 | ||
3909 | do { | |
57a7744e | 3910 | start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp); |
0885a30b | 3911 | _bytes = sky2->tx_stats.bytes; |
3912 | _packets = sky2->tx_stats.packets; | |
57a7744e | 3913 | } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start)); |
0885a30b | 3914 | |
3915 | stats->tx_packets = _packets; | |
3916 | stats->tx_bytes = _bytes; | |
3917 | ||
3918 | stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) | |
3919 | + get_stats32(hw, port, GM_RXF_BC_OK); | |
3920 | ||
3921 | stats->collisions = get_stats32(hw, port, GM_TXF_COL); | |
3922 | ||
3923 | stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); | |
3924 | stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); | |
3925 | stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) | |
3926 | + get_stats32(hw, port, GM_RXE_FRAG); | |
3927 | stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); | |
3928 | ||
3929 | stats->rx_dropped = dev->stats.rx_dropped; | |
3930 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
3931 | stats->tx_fifo_errors = dev->stats.tx_fifo_errors; | |
3932 | ||
3933 | return stats; | |
3934 | } | |
3935 | ||
cd28ab6a SH |
3936 | /* Can have one global because blinking is controlled by |
3937 | * ethtool and that is always under RTNL mutex | |
3938 | */ | |
a84d0a3d | 3939 | static void sky2_led(struct sky2_port *sky2, enum led_mode mode) |
cd28ab6a | 3940 | { |
a84d0a3d SH |
3941 | struct sky2_hw *hw = sky2->hw; |
3942 | unsigned port = sky2->port; | |
793b883e | 3943 | |
a84d0a3d SH |
3944 | spin_lock_bh(&sky2->phy_lock); |
3945 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || | |
3946 | hw->chip_id == CHIP_ID_YUKON_EX || | |
3947 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | |
3948 | u16 pg; | |
793b883e SH |
3949 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
3950 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
793b883e | 3951 | |
a84d0a3d SH |
3952 | switch (mode) { |
3953 | case MO_LED_OFF: | |
3954 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3955 | PHY_M_LEDC_LOS_CTRL(8) | | |
3956 | PHY_M_LEDC_INIT_CTRL(8) | | |
3957 | PHY_M_LEDC_STA1_CTRL(8) | | |
3958 | PHY_M_LEDC_STA0_CTRL(8)); | |
3959 | break; | |
3960 | case MO_LED_ON: | |
3961 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3962 | PHY_M_LEDC_LOS_CTRL(9) | | |
3963 | PHY_M_LEDC_INIT_CTRL(9) | | |
3964 | PHY_M_LEDC_STA1_CTRL(9) | | |
3965 | PHY_M_LEDC_STA0_CTRL(9)); | |
3966 | break; | |
3967 | case MO_LED_BLINK: | |
3968 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3969 | PHY_M_LEDC_LOS_CTRL(0xa) | | |
3970 | PHY_M_LEDC_INIT_CTRL(0xa) | | |
3971 | PHY_M_LEDC_STA1_CTRL(0xa) | | |
3972 | PHY_M_LEDC_STA0_CTRL(0xa)); | |
3973 | break; | |
3974 | case MO_LED_NORM: | |
3975 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
3976 | PHY_M_LEDC_LOS_CTRL(1) | | |
3977 | PHY_M_LEDC_INIT_CTRL(8) | | |
3978 | PHY_M_LEDC_STA1_CTRL(7) | | |
3979 | PHY_M_LEDC_STA0_CTRL(7)); | |
3980 | } | |
793b883e | 3981 | |
a84d0a3d SH |
3982 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
3983 | } else | |
7d2e3cb7 | 3984 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
a84d0a3d SH |
3985 | PHY_M_LED_MO_DUP(mode) | |
3986 | PHY_M_LED_MO_10(mode) | | |
3987 | PHY_M_LED_MO_100(mode) | | |
3988 | PHY_M_LED_MO_1000(mode) | | |
3989 | PHY_M_LED_MO_RX(mode) | | |
3990 | PHY_M_LED_MO_TX(mode)); | |
3991 | ||
3992 | spin_unlock_bh(&sky2->phy_lock); | |
cd28ab6a SH |
3993 | } |
3994 | ||
3995 | /* blink LED's for finding board */ | |
74e532ff | 3996 | static int sky2_set_phys_id(struct net_device *dev, |
3997 | enum ethtool_phys_id_state state) | |
cd28ab6a SH |
3998 | { |
3999 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a | 4000 | |
74e532ff | 4001 | switch (state) { |
4002 | case ETHTOOL_ID_ACTIVE: | |
fce55922 | 4003 | return 1; /* cycle on/off once per second */ |
74e532ff | 4004 | case ETHTOOL_ID_INACTIVE: |
4005 | sky2_led(sky2, MO_LED_NORM); | |
4006 | break; | |
4007 | case ETHTOOL_ID_ON: | |
a84d0a3d | 4008 | sky2_led(sky2, MO_LED_ON); |
74e532ff | 4009 | break; |
4010 | case ETHTOOL_ID_OFF: | |
a84d0a3d | 4011 | sky2_led(sky2, MO_LED_OFF); |
74e532ff | 4012 | break; |
793b883e | 4013 | } |
cd28ab6a SH |
4014 | |
4015 | return 0; | |
4016 | } | |
4017 | ||
4018 | static void sky2_get_pauseparam(struct net_device *dev, | |
4019 | struct ethtool_pauseparam *ecmd) | |
4020 | { | |
4021 | struct sky2_port *sky2 = netdev_priv(dev); | |
4022 | ||
16ad91e1 SH |
4023 | switch (sky2->flow_mode) { |
4024 | case FC_NONE: | |
4025 | ecmd->tx_pause = ecmd->rx_pause = 0; | |
4026 | break; | |
4027 | case FC_TX: | |
4028 | ecmd->tx_pause = 1, ecmd->rx_pause = 0; | |
4029 | break; | |
4030 | case FC_RX: | |
4031 | ecmd->tx_pause = 0, ecmd->rx_pause = 1; | |
4032 | break; | |
4033 | case FC_BOTH: | |
4034 | ecmd->tx_pause = ecmd->rx_pause = 1; | |
4035 | } | |
4036 | ||
0ea065e5 SH |
4037 | ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) |
4038 | ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
cd28ab6a SH |
4039 | } |
4040 | ||
4041 | static int sky2_set_pauseparam(struct net_device *dev, | |
4042 | struct ethtool_pauseparam *ecmd) | |
4043 | { | |
4044 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a | 4045 | |
0ea065e5 SH |
4046 | if (ecmd->autoneg == AUTONEG_ENABLE) |
4047 | sky2->flags |= SKY2_FLAG_AUTO_PAUSE; | |
4048 | else | |
4049 | sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; | |
4050 | ||
16ad91e1 | 4051 | sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); |
cd28ab6a | 4052 | |
16ad91e1 SH |
4053 | if (netif_running(dev)) |
4054 | sky2_phy_reinit(sky2); | |
cd28ab6a | 4055 | |
2eaba1a2 | 4056 | return 0; |
cd28ab6a SH |
4057 | } |
4058 | ||
fb17358f SH |
4059 | static int sky2_get_coalesce(struct net_device *dev, |
4060 | struct ethtool_coalesce *ecmd) | |
4061 | { | |
4062 | struct sky2_port *sky2 = netdev_priv(dev); | |
4063 | struct sky2_hw *hw = sky2->hw; | |
4064 | ||
4065 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
4066 | ecmd->tx_coalesce_usecs = 0; | |
4067 | else { | |
4068 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
4069 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
4070 | } | |
4071 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
4072 | ||
4073 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
4074 | ecmd->rx_coalesce_usecs = 0; | |
4075 | else { | |
4076 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
4077 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
4078 | } | |
4079 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
4080 | ||
4081 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
4082 | ecmd->rx_coalesce_usecs_irq = 0; | |
4083 | else { | |
4084 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
4085 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
4086 | } | |
4087 | ||
4088 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
4089 | ||
4090 | return 0; | |
4091 | } | |
4092 | ||
4093 | /* Note: this affect both ports */ | |
4094 | static int sky2_set_coalesce(struct net_device *dev, | |
4095 | struct ethtool_coalesce *ecmd) | |
4096 | { | |
4097 | struct sky2_port *sky2 = netdev_priv(dev); | |
4098 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 4099 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 4100 | |
77b3d6a2 SH |
4101 | if (ecmd->tx_coalesce_usecs > tmax || |
4102 | ecmd->rx_coalesce_usecs > tmax || | |
4103 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
4104 | return -EINVAL; |
4105 | ||
ee5f68fe | 4106 | if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) |
fb17358f | 4107 | return -EINVAL; |
ff81fbbe | 4108 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 4109 | return -EINVAL; |
060b946c | 4110 | if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) |
fb17358f SH |
4111 | return -EINVAL; |
4112 | ||
4113 | if (ecmd->tx_coalesce_usecs == 0) | |
4114 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
4115 | else { | |
4116 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
4117 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
4118 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
4119 | } | |
4120 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
4121 | ||
4122 | if (ecmd->rx_coalesce_usecs == 0) | |
4123 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
4124 | else { | |
4125 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
4126 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
4127 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
4128 | } | |
4129 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
4130 | ||
4131 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
4132 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
4133 | else { | |
d28d4870 | 4134 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
4135 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
4136 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
4137 | } | |
4138 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
4139 | return 0; | |
4140 | } | |
4141 | ||
738a849c | 4142 | /* |
4143 | * Hardware is limited to min of 128 and max of 2048 for ring size | |
4144 | * and rounded up to next power of two | |
4145 | * to avoid division in modulus calclation | |
4146 | */ | |
4147 | static unsigned long roundup_ring_size(unsigned long pending) | |
4148 | { | |
4149 | return max(128ul, roundup_pow_of_two(pending+1)); | |
4150 | } | |
4151 | ||
793b883e SH |
4152 | static void sky2_get_ringparam(struct net_device *dev, |
4153 | struct ethtool_ringparam *ering) | |
4154 | { | |
4155 | struct sky2_port *sky2 = netdev_priv(dev); | |
4156 | ||
4157 | ering->rx_max_pending = RX_MAX_PENDING; | |
ee5f68fe | 4158 | ering->tx_max_pending = TX_MAX_PENDING; |
793b883e SH |
4159 | |
4160 | ering->rx_pending = sky2->rx_pending; | |
793b883e SH |
4161 | ering->tx_pending = sky2->tx_pending; |
4162 | } | |
4163 | ||
4164 | static int sky2_set_ringparam(struct net_device *dev, | |
4165 | struct ethtool_ringparam *ering) | |
4166 | { | |
4167 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e SH |
4168 | |
4169 | if (ering->rx_pending > RX_MAX_PENDING || | |
4170 | ering->rx_pending < 8 || | |
ee5f68fe SH |
4171 | ering->tx_pending < TX_MIN_PENDING || |
4172 | ering->tx_pending > TX_MAX_PENDING) | |
793b883e SH |
4173 | return -EINVAL; |
4174 | ||
af18d8b8 | 4175 | sky2_detach(dev); |
793b883e SH |
4176 | |
4177 | sky2->rx_pending = ering->rx_pending; | |
4178 | sky2->tx_pending = ering->tx_pending; | |
738a849c | 4179 | sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); |
793b883e | 4180 | |
af18d8b8 | 4181 | return sky2_reattach(dev); |
793b883e SH |
4182 | } |
4183 | ||
793b883e SH |
4184 | static int sky2_get_regs_len(struct net_device *dev) |
4185 | { | |
6e4cbb34 | 4186 | return 0x4000; |
793b883e SH |
4187 | } |
4188 | ||
c32bbff8 MM |
4189 | static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) |
4190 | { | |
4191 | /* This complicated switch statement is to make sure and | |
4192 | * only access regions that are unreserved. | |
4193 | * Some blocks are only valid on dual port cards. | |
4194 | */ | |
4195 | switch (b) { | |
4196 | /* second port */ | |
4197 | case 5: /* Tx Arbiter 2 */ | |
4198 | case 9: /* RX2 */ | |
4199 | case 14 ... 15: /* TX2 */ | |
4200 | case 17: case 19: /* Ram Buffer 2 */ | |
4201 | case 22 ... 23: /* Tx Ram Buffer 2 */ | |
4202 | case 25: /* Rx MAC Fifo 1 */ | |
4203 | case 27: /* Tx MAC Fifo 2 */ | |
4204 | case 31: /* GPHY 2 */ | |
4205 | case 40 ... 47: /* Pattern Ram 2 */ | |
4206 | case 52: case 54: /* TCP Segmentation 2 */ | |
4207 | case 112 ... 116: /* GMAC 2 */ | |
4208 | return hw->ports > 1; | |
4209 | ||
4210 | case 0: /* Control */ | |
4211 | case 2: /* Mac address */ | |
4212 | case 4: /* Tx Arbiter 1 */ | |
4213 | case 7: /* PCI express reg */ | |
4214 | case 8: /* RX1 */ | |
4215 | case 12 ... 13: /* TX1 */ | |
4216 | case 16: case 18:/* Rx Ram Buffer 1 */ | |
4217 | case 20 ... 21: /* Tx Ram Buffer 1 */ | |
4218 | case 24: /* Rx MAC Fifo 1 */ | |
4219 | case 26: /* Tx MAC Fifo 1 */ | |
4220 | case 28 ... 29: /* Descriptor and status unit */ | |
4221 | case 30: /* GPHY 1*/ | |
4222 | case 32 ... 39: /* Pattern Ram 1 */ | |
4223 | case 48: case 50: /* TCP Segmentation 1 */ | |
4224 | case 56 ... 60: /* PCI space */ | |
4225 | case 80 ... 84: /* GMAC 1 */ | |
4226 | return 1; | |
4227 | ||
4228 | default: | |
4229 | return 0; | |
4230 | } | |
4231 | } | |
4232 | ||
793b883e SH |
4233 | /* |
4234 | * Returns copy of control register region | |
3ead5db7 | 4235 | * Note: ethtool_get_regs always provides full size (16k) buffer |
793b883e SH |
4236 | */ |
4237 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4238 | void *p) | |
4239 | { | |
4240 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 4241 | const void __iomem *io = sky2->hw->regs; |
295b54c4 | 4242 | unsigned int b; |
793b883e SH |
4243 | |
4244 | regs->version = 1; | |
793b883e | 4245 | |
295b54c4 | 4246 | for (b = 0; b < 128; b++) { |
c32bbff8 MM |
4247 | /* skip poisonous diagnostic ram region in block 3 */ |
4248 | if (b == 3) | |
295b54c4 | 4249 | memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); |
c32bbff8 | 4250 | else if (sky2_reg_access_ok(sky2->hw, b)) |
295b54c4 | 4251 | memcpy_fromio(p, io, 128); |
c32bbff8 | 4252 | else |
295b54c4 | 4253 | memset(p, 0, 128); |
3ead5db7 | 4254 | |
295b54c4 SH |
4255 | p += 128; |
4256 | io += 128; | |
4257 | } | |
793b883e | 4258 | } |
cd28ab6a | 4259 | |
f4331a6d SH |
4260 | static int sky2_get_eeprom_len(struct net_device *dev) |
4261 | { | |
4262 | struct sky2_port *sky2 = netdev_priv(dev); | |
b32f40c4 | 4263 | struct sky2_hw *hw = sky2->hw; |
f4331a6d SH |
4264 | u16 reg2; |
4265 | ||
b32f40c4 | 4266 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
f4331a6d SH |
4267 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
4268 | } | |
4269 | ||
1413235c | 4270 | static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) |
f4331a6d | 4271 | { |
1413235c | 4272 | unsigned long start = jiffies; |
f4331a6d | 4273 | |
1413235c SH |
4274 | while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { |
4275 | /* Can take up to 10.6 ms for write */ | |
4276 | if (time_after(jiffies, start + HZ/4)) { | |
ada1db5c | 4277 | dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); |
1413235c SH |
4278 | return -ETIMEDOUT; |
4279 | } | |
4280 | mdelay(1); | |
4281 | } | |
167f53d0 | 4282 | |
1413235c SH |
4283 | return 0; |
4284 | } | |
167f53d0 | 4285 | |
1413235c SH |
4286 | static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, |
4287 | u16 offset, size_t length) | |
4288 | { | |
4289 | int rc = 0; | |
4290 | ||
4291 | while (length > 0) { | |
4292 | u32 val; | |
4293 | ||
4294 | sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); | |
4295 | rc = sky2_vpd_wait(hw, cap, 0); | |
4296 | if (rc) | |
4297 | break; | |
4298 | ||
4299 | val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); | |
4300 | ||
4301 | memcpy(data, &val, min(sizeof(val), length)); | |
4302 | offset += sizeof(u32); | |
4303 | data += sizeof(u32); | |
4304 | length -= sizeof(u32); | |
4305 | } | |
4306 | ||
4307 | return rc; | |
f4331a6d SH |
4308 | } |
4309 | ||
1413235c SH |
4310 | static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, |
4311 | u16 offset, unsigned int length) | |
f4331a6d | 4312 | { |
1413235c SH |
4313 | unsigned int i; |
4314 | int rc = 0; | |
4315 | ||
4316 | for (i = 0; i < length; i += sizeof(u32)) { | |
4317 | u32 val = *(u32 *)(data + i); | |
4318 | ||
4319 | sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); | |
4320 | sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); | |
4321 | ||
4322 | rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); | |
4323 | if (rc) | |
4324 | break; | |
4325 | } | |
4326 | return rc; | |
f4331a6d SH |
4327 | } |
4328 | ||
4329 | static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4330 | u8 *data) | |
4331 | { | |
4332 | struct sky2_port *sky2 = netdev_priv(dev); | |
4333 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
f4331a6d SH |
4334 | |
4335 | if (!cap) | |
4336 | return -EINVAL; | |
4337 | ||
4338 | eeprom->magic = SKY2_EEPROM_MAGIC; | |
4339 | ||
1413235c | 4340 | return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
f4331a6d SH |
4341 | } |
4342 | ||
4343 | static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |
4344 | u8 *data) | |
4345 | { | |
4346 | struct sky2_port *sky2 = netdev_priv(dev); | |
4347 | int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); | |
f4331a6d SH |
4348 | |
4349 | if (!cap) | |
4350 | return -EINVAL; | |
4351 | ||
4352 | if (eeprom->magic != SKY2_EEPROM_MAGIC) | |
4353 | return -EINVAL; | |
4354 | ||
1413235c SH |
4355 | /* Partial writes not supported */ |
4356 | if ((eeprom->offset & 3) || (eeprom->len & 3)) | |
4357 | return -EINVAL; | |
f4331a6d | 4358 | |
1413235c | 4359 | return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); |
f4331a6d SH |
4360 | } |
4361 | ||
c8f44aff MM |
4362 | static netdev_features_t sky2_fix_features(struct net_device *dev, |
4363 | netdev_features_t features) | |
bf73130d | 4364 | { |
f5d64037 MM |
4365 | const struct sky2_port *sky2 = netdev_priv(dev); |
4366 | const struct sky2_hw *hw = sky2->hw; | |
bf73130d | 4367 | |
f5d64037 MM |
4368 | /* In order to do Jumbo packets on these chips, need to turn off the |
4369 | * transmit store/forward. Therefore checksum offload won't work. | |
4370 | */ | |
aa5ca96c | 4371 | if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { |
4372 | netdev_info(dev, "checksum offload not possible with jumbo frames\n"); | |
a188222b | 4373 | features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK); |
aa5ca96c | 4374 | } |
4375 | ||
4376 | /* Some hardware requires receive checksum for RSS to work. */ | |
4377 | if ( (features & NETIF_F_RXHASH) && | |
4378 | !(features & NETIF_F_RXCSUM) && | |
4379 | (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { | |
4380 | netdev_info(dev, "receive hashing forces receive checksum\n"); | |
4381 | features |= NETIF_F_RXCSUM; | |
4382 | } | |
86aa7785 | 4383 | |
f5d64037 MM |
4384 | return features; |
4385 | } | |
86aa7785 | 4386 | |
c8f44aff | 4387 | static int sky2_set_features(struct net_device *dev, netdev_features_t features) |
f5d64037 MM |
4388 | { |
4389 | struct sky2_port *sky2 = netdev_priv(dev); | |
c8f44aff | 4390 | netdev_features_t changed = dev->features ^ features; |
86aa7785 | 4391 | |
5ff0feac | 4392 | if ((changed & NETIF_F_RXCSUM) && |
4393 | !(sky2->hw->flags & SKY2_HW_NEW_LE)) { | |
4394 | sky2_write32(sky2->hw, | |
4395 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
4396 | (features & NETIF_F_RXCSUM) | |
4397 | ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
f5d64037 | 4398 | } |
bf73130d | 4399 | |
f5d64037 MM |
4400 | if (changed & NETIF_F_RXHASH) |
4401 | rx_set_rss(dev, features); | |
86aa7785 | 4402 | |
f646968f | 4403 | if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) |
f5d64037 | 4404 | sky2_vlan_mode(dev, features); |
bf73130d SH |
4405 | |
4406 | return 0; | |
4407 | } | |
f4331a6d | 4408 | |
7282d491 | 4409 | static const struct ethtool_ops sky2_ethtool_ops = { |
f4331a6d SH |
4410 | .get_settings = sky2_get_settings, |
4411 | .set_settings = sky2_set_settings, | |
4412 | .get_drvinfo = sky2_get_drvinfo, | |
4413 | .get_wol = sky2_get_wol, | |
4414 | .set_wol = sky2_set_wol, | |
4415 | .get_msglevel = sky2_get_msglevel, | |
4416 | .set_msglevel = sky2_set_msglevel, | |
4417 | .nway_reset = sky2_nway_reset, | |
4418 | .get_regs_len = sky2_get_regs_len, | |
4419 | .get_regs = sky2_get_regs, | |
4420 | .get_link = ethtool_op_get_link, | |
4421 | .get_eeprom_len = sky2_get_eeprom_len, | |
4422 | .get_eeprom = sky2_get_eeprom, | |
4423 | .set_eeprom = sky2_set_eeprom, | |
f4331a6d SH |
4424 | .get_strings = sky2_get_strings, |
4425 | .get_coalesce = sky2_get_coalesce, | |
4426 | .set_coalesce = sky2_set_coalesce, | |
4427 | .get_ringparam = sky2_get_ringparam, | |
4428 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
4429 | .get_pauseparam = sky2_get_pauseparam, |
4430 | .set_pauseparam = sky2_set_pauseparam, | |
74e532ff | 4431 | .set_phys_id = sky2_set_phys_id, |
b9f2c044 | 4432 | .get_sset_count = sky2_get_sset_count, |
cd28ab6a SH |
4433 | .get_ethtool_stats = sky2_get_ethtool_stats, |
4434 | }; | |
4435 | ||
3cf26753 SH |
4436 | #ifdef CONFIG_SKY2_DEBUG |
4437 | ||
4438 | static struct dentry *sky2_debug; | |
4439 | ||
e4c2abe2 SH |
4440 | |
4441 | /* | |
4442 | * Read and parse the first part of Vital Product Data | |
4443 | */ | |
4444 | #define VPD_SIZE 128 | |
4445 | #define VPD_MAGIC 0x82 | |
4446 | ||
4447 | static const struct vpd_tag { | |
4448 | char tag[2]; | |
4449 | char *label; | |
4450 | } vpd_tags[] = { | |
4451 | { "PN", "Part Number" }, | |
4452 | { "EC", "Engineering Level" }, | |
4453 | { "MN", "Manufacturer" }, | |
4454 | { "SN", "Serial Number" }, | |
4455 | { "YA", "Asset Tag" }, | |
4456 | { "VL", "First Error Log Message" }, | |
4457 | { "VF", "Second Error Log Message" }, | |
4458 | { "VB", "Boot Agent ROM Configuration" }, | |
4459 | { "VE", "EFI UNDI Configuration" }, | |
4460 | }; | |
4461 | ||
4462 | static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) | |
4463 | { | |
4464 | size_t vpd_size; | |
4465 | loff_t offs; | |
4466 | u8 len; | |
4467 | unsigned char *buf; | |
4468 | u16 reg2; | |
4469 | ||
4470 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); | |
4471 | vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); | |
4472 | ||
4473 | seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); | |
4474 | buf = kmalloc(vpd_size, GFP_KERNEL); | |
4475 | if (!buf) { | |
4476 | seq_puts(seq, "no memory!\n"); | |
4477 | return; | |
4478 | } | |
4479 | ||
4480 | if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { | |
4481 | seq_puts(seq, "VPD read failed\n"); | |
4482 | goto out; | |
4483 | } | |
4484 | ||
4485 | if (buf[0] != VPD_MAGIC) { | |
4486 | seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); | |
4487 | goto out; | |
4488 | } | |
4489 | len = buf[1]; | |
4490 | if (len == 0 || len > vpd_size - 4) { | |
4491 | seq_printf(seq, "Invalid id length: %d\n", len); | |
4492 | goto out; | |
4493 | } | |
4494 | ||
4495 | seq_printf(seq, "%.*s\n", len, buf + 3); | |
4496 | offs = len + 3; | |
4497 | ||
4498 | while (offs < vpd_size - 4) { | |
4499 | int i; | |
4500 | ||
4501 | if (!memcmp("RW", buf + offs, 2)) /* end marker */ | |
4502 | break; | |
4503 | len = buf[offs + 2]; | |
4504 | if (offs + len + 3 >= vpd_size) | |
4505 | break; | |
4506 | ||
4507 | for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { | |
4508 | if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { | |
4509 | seq_printf(seq, " %s: %.*s\n", | |
4510 | vpd_tags[i].label, len, buf + offs + 3); | |
4511 | break; | |
4512 | } | |
4513 | } | |
4514 | offs += len + 3; | |
4515 | } | |
4516 | out: | |
4517 | kfree(buf); | |
4518 | } | |
4519 | ||
3cf26753 SH |
4520 | static int sky2_debug_show(struct seq_file *seq, void *v) |
4521 | { | |
4522 | struct net_device *dev = seq->private; | |
4523 | const struct sky2_port *sky2 = netdev_priv(dev); | |
bea3348e | 4524 | struct sky2_hw *hw = sky2->hw; |
3cf26753 SH |
4525 | unsigned port = sky2->port; |
4526 | unsigned idx, last; | |
4527 | int sop; | |
4528 | ||
e4c2abe2 | 4529 | sky2_show_vpd(seq, hw); |
3cf26753 | 4530 | |
e4c2abe2 | 4531 | seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", |
3cf26753 SH |
4532 | sky2_read32(hw, B0_ISRC), |
4533 | sky2_read32(hw, B0_IMSK), | |
4534 | sky2_read32(hw, B0_Y2_SP_ICR)); | |
4535 | ||
e4c2abe2 SH |
4536 | if (!netif_running(dev)) { |
4537 | seq_printf(seq, "network not running\n"); | |
4538 | return 0; | |
4539 | } | |
4540 | ||
bea3348e | 4541 | napi_disable(&hw->napi); |
3cf26753 SH |
4542 | last = sky2_read16(hw, STAT_PUT_IDX); |
4543 | ||
efe91932 | 4544 | seq_printf(seq, "Status ring %u\n", hw->st_size); |
3cf26753 SH |
4545 | if (hw->st_idx == last) |
4546 | seq_puts(seq, "Status ring (empty)\n"); | |
4547 | else { | |
4548 | seq_puts(seq, "Status ring\n"); | |
efe91932 | 4549 | for (idx = hw->st_idx; idx != last && idx < hw->st_size; |
4550 | idx = RING_NEXT(idx, hw->st_size)) { | |
3cf26753 SH |
4551 | const struct sky2_status_le *le = hw->st_le + idx; |
4552 | seq_printf(seq, "[%d] %#x %d %#x\n", | |
4553 | idx, le->opcode, le->length, le->status); | |
4554 | } | |
4555 | seq_puts(seq, "\n"); | |
4556 | } | |
4557 | ||
4558 | seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", | |
4559 | sky2->tx_cons, sky2->tx_prod, | |
4560 | sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), | |
4561 | sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); | |
4562 | ||
4563 | /* Dump contents of tx ring */ | |
4564 | sop = 1; | |
ee5f68fe SH |
4565 | for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; |
4566 | idx = RING_NEXT(idx, sky2->tx_ring_size)) { | |
3cf26753 SH |
4567 | const struct sky2_tx_le *le = sky2->tx_le + idx; |
4568 | u32 a = le32_to_cpu(le->addr); | |
4569 | ||
4570 | if (sop) | |
4571 | seq_printf(seq, "%u:", idx); | |
4572 | sop = 0; | |
4573 | ||
060b946c | 4574 | switch (le->opcode & ~HW_OWNER) { |
3cf26753 SH |
4575 | case OP_ADDR64: |
4576 | seq_printf(seq, " %#x:", a); | |
4577 | break; | |
4578 | case OP_LRGLEN: | |
4579 | seq_printf(seq, " mtu=%d", a); | |
4580 | break; | |
4581 | case OP_VLAN: | |
4582 | seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); | |
4583 | break; | |
4584 | case OP_TCPLISW: | |
4585 | seq_printf(seq, " csum=%#x", a); | |
4586 | break; | |
4587 | case OP_LARGESEND: | |
4588 | seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); | |
4589 | break; | |
4590 | case OP_PACKET: | |
4591 | seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); | |
4592 | break; | |
4593 | case OP_BUFFER: | |
4594 | seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); | |
4595 | break; | |
4596 | default: | |
4597 | seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, | |
4598 | a, le16_to_cpu(le->length)); | |
4599 | } | |
4600 | ||
4601 | if (le->ctrl & EOP) { | |
4602 | seq_putc(seq, '\n'); | |
4603 | sop = 1; | |
4604 | } | |
4605 | } | |
4606 | ||
4607 | seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", | |
4608 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), | |
c409c34b | 4609 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), |
3cf26753 SH |
4610 | sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); |
4611 | ||
d1d08d12 | 4612 | sky2_read32(hw, B0_Y2_SP_LISR); |
bea3348e | 4613 | napi_enable(&hw->napi); |
3cf26753 SH |
4614 | return 0; |
4615 | } | |
4616 | ||
4617 | static int sky2_debug_open(struct inode *inode, struct file *file) | |
4618 | { | |
4619 | return single_open(file, sky2_debug_show, inode->i_private); | |
4620 | } | |
4621 | ||
4622 | static const struct file_operations sky2_debug_fops = { | |
4623 | .owner = THIS_MODULE, | |
4624 | .open = sky2_debug_open, | |
4625 | .read = seq_read, | |
4626 | .llseek = seq_lseek, | |
4627 | .release = single_release, | |
4628 | }; | |
4629 | ||
4630 | /* | |
4631 | * Use network device events to create/remove/rename | |
4632 | * debugfs file entries | |
4633 | */ | |
4634 | static int sky2_device_event(struct notifier_block *unused, | |
4635 | unsigned long event, void *ptr) | |
4636 | { | |
351638e7 | 4637 | struct net_device *dev = netdev_notifier_info_to_dev(ptr); |
5b296bc9 | 4638 | struct sky2_port *sky2 = netdev_priv(dev); |
3cf26753 | 4639 | |
926d0977 | 4640 | if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) |
5b296bc9 | 4641 | return NOTIFY_DONE; |
3cf26753 | 4642 | |
060b946c | 4643 | switch (event) { |
5b296bc9 SH |
4644 | case NETDEV_CHANGENAME: |
4645 | if (sky2->debugfs) { | |
4646 | sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, | |
4647 | sky2_debug, dev->name); | |
4648 | } | |
4649 | break; | |
3cf26753 | 4650 | |
5b296bc9 SH |
4651 | case NETDEV_GOING_DOWN: |
4652 | if (sky2->debugfs) { | |
ada1db5c | 4653 | netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); |
5b296bc9 SH |
4654 | debugfs_remove(sky2->debugfs); |
4655 | sky2->debugfs = NULL; | |
3cf26753 | 4656 | } |
5b296bc9 SH |
4657 | break; |
4658 | ||
4659 | case NETDEV_UP: | |
4660 | sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, | |
4661 | sky2_debug, dev, | |
4662 | &sky2_debug_fops); | |
4663 | if (IS_ERR(sky2->debugfs)) | |
4664 | sky2->debugfs = NULL; | |
3cf26753 SH |
4665 | } |
4666 | ||
4667 | return NOTIFY_DONE; | |
4668 | } | |
4669 | ||
4670 | static struct notifier_block sky2_notifier = { | |
4671 | .notifier_call = sky2_device_event, | |
4672 | }; | |
4673 | ||
4674 | ||
4675 | static __init void sky2_debug_init(void) | |
4676 | { | |
4677 | struct dentry *ent; | |
4678 | ||
4679 | ent = debugfs_create_dir("sky2", NULL); | |
4680 | if (!ent || IS_ERR(ent)) | |
4681 | return; | |
4682 | ||
4683 | sky2_debug = ent; | |
4684 | register_netdevice_notifier(&sky2_notifier); | |
4685 | } | |
4686 | ||
4687 | static __exit void sky2_debug_cleanup(void) | |
4688 | { | |
4689 | if (sky2_debug) { | |
4690 | unregister_netdevice_notifier(&sky2_notifier); | |
4691 | debugfs_remove(sky2_debug); | |
4692 | sky2_debug = NULL; | |
4693 | } | |
4694 | } | |
4695 | ||
4696 | #else | |
4697 | #define sky2_debug_init() | |
4698 | #define sky2_debug_cleanup() | |
4699 | #endif | |
4700 | ||
1436b301 SH |
4701 | /* Two copies of network device operations to handle special case of |
4702 | not allowing netpoll on second port */ | |
4703 | static const struct net_device_ops sky2_netdev_ops[2] = { | |
4704 | { | |
926d0977 | 4705 | .ndo_open = sky2_open, |
4706 | .ndo_stop = sky2_close, | |
00829823 | 4707 | .ndo_start_xmit = sky2_xmit_frame, |
1436b301 SH |
4708 | .ndo_do_ioctl = sky2_ioctl, |
4709 | .ndo_validate_addr = eth_validate_addr, | |
4710 | .ndo_set_mac_address = sky2_set_mac_address, | |
afc4b13d | 4711 | .ndo_set_rx_mode = sky2_set_multicast, |
1436b301 | 4712 | .ndo_change_mtu = sky2_change_mtu, |
f5d64037 MM |
4713 | .ndo_fix_features = sky2_fix_features, |
4714 | .ndo_set_features = sky2_set_features, | |
1436b301 | 4715 | .ndo_tx_timeout = sky2_tx_timeout, |
0885a30b | 4716 | .ndo_get_stats64 = sky2_get_stats, |
1436b301 SH |
4717 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4718 | .ndo_poll_controller = sky2_netpoll, | |
4719 | #endif | |
4720 | }, | |
4721 | { | |
926d0977 | 4722 | .ndo_open = sky2_open, |
4723 | .ndo_stop = sky2_close, | |
00829823 | 4724 | .ndo_start_xmit = sky2_xmit_frame, |
1436b301 SH |
4725 | .ndo_do_ioctl = sky2_ioctl, |
4726 | .ndo_validate_addr = eth_validate_addr, | |
4727 | .ndo_set_mac_address = sky2_set_mac_address, | |
afc4b13d | 4728 | .ndo_set_rx_mode = sky2_set_multicast, |
1436b301 | 4729 | .ndo_change_mtu = sky2_change_mtu, |
f5d64037 MM |
4730 | .ndo_fix_features = sky2_fix_features, |
4731 | .ndo_set_features = sky2_set_features, | |
1436b301 | 4732 | .ndo_tx_timeout = sky2_tx_timeout, |
0885a30b | 4733 | .ndo_get_stats64 = sky2_get_stats, |
1436b301 SH |
4734 | }, |
4735 | }; | |
3cf26753 | 4736 | |
cd28ab6a | 4737 | /* Initialize network device */ |
1dd06ae8 GKH |
4738 | static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, |
4739 | int highmem, int wol) | |
cd28ab6a SH |
4740 | { |
4741 | struct sky2_port *sky2; | |
4742 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3ee2f8ce | 4743 | const void *iap; |
cd28ab6a | 4744 | |
41de8d4c | 4745 | if (!dev) |
cd28ab6a | 4746 | return NULL; |
cd28ab6a | 4747 | |
cd28ab6a | 4748 | SET_NETDEV_DEV(dev, &hw->pdev->dev); |
ef743d33 | 4749 | dev->irq = hw->pdev->irq; |
7ad24ea4 | 4750 | dev->ethtool_ops = &sky2_ethtool_ops; |
cd28ab6a | 4751 | dev->watchdog_timeo = TX_WATCHDOG; |
1436b301 | 4752 | dev->netdev_ops = &sky2_netdev_ops[port]; |
cd28ab6a SH |
4753 | |
4754 | sky2 = netdev_priv(dev); | |
4755 | sky2->netdev = dev; | |
4756 | sky2->hw = hw; | |
4757 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
4758 | ||
827da44c JS |
4759 | u64_stats_init(&sky2->tx_stats.syncp); |
4760 | u64_stats_init(&sky2->rx_stats.syncp); | |
4761 | ||
cd28ab6a | 4762 | /* Auto speed and flow control */ |
0ea065e5 SH |
4763 | sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; |
4764 | if (hw->chip_id != CHIP_ID_YUKON_XL) | |
f5d64037 | 4765 | dev->hw_features |= NETIF_F_RXCSUM; |
0ea065e5 | 4766 | |
16ad91e1 SH |
4767 | sky2->flow_mode = FC_BOTH; |
4768 | ||
cd28ab6a SH |
4769 | sky2->duplex = -1; |
4770 | sky2->speed = -1; | |
4771 | sky2->advertising = sky2_supported_modes(hw); | |
be63a21c | 4772 | sky2->wol = wol; |
75d070c5 | 4773 | |
e07b1aa8 | 4774 | spin_lock_init(&sky2->phy_lock); |
ee5f68fe | 4775 | |
793b883e | 4776 | sky2->tx_pending = TX_DEF_PENDING; |
738a849c | 4777 | sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); |
290d4de5 | 4778 | sky2->rx_pending = RX_DEF_PENDING; |
cd28ab6a SH |
4779 | |
4780 | hw->dev[port] = dev; | |
4781 | ||
4782 | sky2->port = port; | |
4783 | ||
f5d64037 | 4784 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; |
86aa7785 | 4785 | |
cd28ab6a SH |
4786 | if (highmem) |
4787 | dev->features |= NETIF_F_HIGHDMA; | |
cd28ab6a | 4788 | |
bf73130d SH |
4789 | /* Enable receive hashing unless hardware is known broken */ |
4790 | if (!(hw->flags & SKY2_HW_RSS_BROKEN)) | |
f5d64037 MM |
4791 | dev->hw_features |= NETIF_F_RXHASH; |
4792 | ||
4793 | if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { | |
f646968f PM |
4794 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | |
4795 | NETIF_F_HW_VLAN_CTAG_RX; | |
f5d64037 MM |
4796 | dev->vlan_features |= SKY2_VLAN_OFFLOADS; |
4797 | } | |
bf73130d | 4798 | |
f5d64037 | 4799 | dev->features |= dev->hw_features; |
d1f13708 | 4800 | |
5777987e JW |
4801 | /* MTU range: 60 - 1500 or 9000 */ |
4802 | dev->min_mtu = ETH_ZLEN; | |
4803 | if (hw->chip_id == CHIP_ID_YUKON_FE || | |
4804 | hw->chip_id == CHIP_ID_YUKON_FE_P) | |
4805 | dev->max_mtu = ETH_DATA_LEN; | |
4806 | else | |
4807 | dev->max_mtu = ETH_JUMBO_MTU; | |
4808 | ||
3ee2f8ce TH |
4809 | /* try to get mac address in the following order: |
4810 | * 1) from device tree data | |
4811 | * 2) from internal registers set by bootloader | |
4812 | */ | |
4813 | iap = of_get_mac_address(hw->pdev->dev.of_node); | |
4814 | if (iap) | |
4815 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
4816 | else | |
4817 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, | |
4818 | ETH_ALEN); | |
cd28ab6a | 4819 | |
0f50c10d LD |
4820 | /* if the address is invalid, use a random value */ |
4821 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
4822 | struct sockaddr sa = { AF_UNSPEC }; | |
4823 | ||
4824 | netdev_warn(dev, | |
4825 | "Invalid MAC address, defaulting to random\n"); | |
4826 | eth_hw_addr_random(dev); | |
4827 | memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); | |
4828 | if (sky2_set_mac_address(dev, &sa)) | |
4829 | netdev_warn(dev, "Failed to set MAC address.\n"); | |
4830 | } | |
4831 | ||
cd28ab6a SH |
4832 | return dev; |
4833 | } | |
4834 | ||
853e3f4c | 4835 | static void sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
4836 | { |
4837 | const struct sky2_port *sky2 = netdev_priv(dev); | |
4838 | ||
6c35abae | 4839 | netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); |
cd28ab6a SH |
4840 | } |
4841 | ||
fb2690a9 | 4842 | /* Handle software interrupt used during MSI test */ |
853e3f4c | 4843 | static irqreturn_t sky2_test_intr(int irq, void *dev_id) |
fb2690a9 SH |
4844 | { |
4845 | struct sky2_hw *hw = dev_id; | |
4846 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
4847 | ||
4848 | if (status == 0) | |
4849 | return IRQ_NONE; | |
4850 | ||
4851 | if (status & Y2_IS_IRQ_SW) { | |
ea76e635 | 4852 | hw->flags |= SKY2_HW_USE_MSI; |
fb2690a9 SH |
4853 | wake_up(&hw->msi_wait); |
4854 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4855 | } | |
4856 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
4857 | ||
4858 | return IRQ_HANDLED; | |
4859 | } | |
4860 | ||
4861 | /* Test interrupt path by forcing a a software IRQ */ | |
853e3f4c | 4862 | static int sky2_test_msi(struct sky2_hw *hw) |
fb2690a9 SH |
4863 | { |
4864 | struct pci_dev *pdev = hw->pdev; | |
4865 | int err; | |
4866 | ||
060b946c | 4867 | init_waitqueue_head(&hw->msi_wait); |
bb507fe1 | 4868 | |
b0a20ded | 4869 | err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); |
fb2690a9 | 4870 | if (err) { |
b02a9258 | 4871 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
fb2690a9 SH |
4872 | return err; |
4873 | } | |
4874 | ||
ede7193d LS |
4875 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
4876 | ||
fb2690a9 | 4877 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
bb507fe1 | 4878 | sky2_read8(hw, B0_CTST); |
fb2690a9 | 4879 | |
ea76e635 | 4880 | wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); |
fb2690a9 | 4881 | |
ea76e635 | 4882 | if (!(hw->flags & SKY2_HW_USE_MSI)) { |
fb2690a9 | 4883 | /* MSI test failed, go back to INTx mode */ |
b02a9258 SH |
4884 | dev_info(&pdev->dev, "No interrupt generated using MSI, " |
4885 | "switching to INTx mode.\n"); | |
fb2690a9 SH |
4886 | |
4887 | err = -EOPNOTSUPP; | |
4888 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
4889 | } | |
4890 | ||
4891 | sky2_write32(hw, B0_IMSK, 0); | |
2bffc23a | 4892 | sky2_read32(hw, B0_IMSK); |
fb2690a9 SH |
4893 | |
4894 | free_irq(pdev->irq, hw); | |
4895 | ||
4896 | return err; | |
4897 | } | |
4898 | ||
c7127a34 SH |
4899 | /* This driver supports yukon2 chipset only */ |
4900 | static const char *sky2_name(u8 chipid, char *buf, int sz) | |
4901 | { | |
4902 | const char *name[] = { | |
4903 | "XL", /* 0xb3 */ | |
4904 | "EC Ultra", /* 0xb4 */ | |
4905 | "Extreme", /* 0xb5 */ | |
4906 | "EC", /* 0xb6 */ | |
4907 | "FE", /* 0xb7 */ | |
4908 | "FE+", /* 0xb8 */ | |
4909 | "Supreme", /* 0xb9 */ | |
0ce8b98d | 4910 | "UL 2", /* 0xba */ |
0f5aac70 SH |
4911 | "Unknown", /* 0xbb */ |
4912 | "Optima", /* 0xbc */ | |
0e767324 | 4913 | "OptimaEEE", /* 0xbd */ |
4fb99cd6 | 4914 | "Optima 2", /* 0xbe */ |
c7127a34 SH |
4915 | }; |
4916 | ||
4fb99cd6 | 4917 | if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) |
c7127a34 SH |
4918 | strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); |
4919 | else | |
4920 | snprintf(buf, sz, "(chip %#x)", chipid); | |
4921 | return buf; | |
4922 | } | |
4923 | ||
1dd06ae8 | 4924 | static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
cd28ab6a | 4925 | { |
0bdb0bd0 | 4926 | struct net_device *dev, *dev1; |
cd28ab6a | 4927 | struct sky2_hw *hw; |
be63a21c | 4928 | int err, using_dac = 0, wol_default; |
3834507d | 4929 | u32 reg; |
c7127a34 | 4930 | char buf1[16]; |
cd28ab6a | 4931 | |
793b883e SH |
4932 | err = pci_enable_device(pdev); |
4933 | if (err) { | |
b02a9258 | 4934 | dev_err(&pdev->dev, "cannot enable PCI device\n"); |
cd28ab6a SH |
4935 | goto err_out; |
4936 | } | |
4937 | ||
6cc90a5a SH |
4938 | /* Get configuration information |
4939 | * Note: only regular PCI config access once to test for HW issues | |
4940 | * other PCI access through shared memory for speed and to | |
4941 | * avoid MMCONFIG problems. | |
4942 | */ | |
4943 | err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
4944 | if (err) { | |
4945 | dev_err(&pdev->dev, "PCI read config failed\n"); | |
1c85382e | 4946 | goto err_out_disable; |
6cc90a5a SH |
4947 | } |
4948 | ||
4949 | if (~reg == 0) { | |
4950 | dev_err(&pdev->dev, "PCI configuration read error\n"); | |
0bd8ba18 | 4951 | err = -EIO; |
1c85382e | 4952 | goto err_out_disable; |
6cc90a5a SH |
4953 | } |
4954 | ||
793b883e SH |
4955 | err = pci_request_regions(pdev, DRV_NAME); |
4956 | if (err) { | |
b02a9258 | 4957 | dev_err(&pdev->dev, "cannot obtain PCI resources\n"); |
44a1d2e5 | 4958 | goto err_out_disable; |
cd28ab6a SH |
4959 | } |
4960 | ||
4961 | pci_set_master(pdev); | |
4962 | ||
d1f3d4dd | 4963 | if (sizeof(dma_addr_t) > sizeof(u32) && |
6a35528a | 4964 | !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { |
d1f3d4dd | 4965 | using_dac = 1; |
6a35528a | 4966 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
d1f3d4dd | 4967 | if (err < 0) { |
b02a9258 SH |
4968 | dev_err(&pdev->dev, "unable to obtain 64 bit DMA " |
4969 | "for consistent allocations\n"); | |
d1f3d4dd SH |
4970 | goto err_out_free_regions; |
4971 | } | |
d1f3d4dd | 4972 | } else { |
284901a9 | 4973 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cd28ab6a | 4974 | if (err) { |
b02a9258 | 4975 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
cd28ab6a SH |
4976 | goto err_out_free_regions; |
4977 | } | |
4978 | } | |
d1f3d4dd | 4979 | |
3834507d SH |
4980 | |
4981 | #ifdef __BIG_ENDIAN | |
4982 | /* The sk98lin vendor driver uses hardware byte swapping but | |
4983 | * this driver uses software swapping. | |
4984 | */ | |
4985 | reg &= ~PCI_REV_DESC; | |
060b946c | 4986 | err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); |
3834507d SH |
4987 | if (err) { |
4988 | dev_err(&pdev->dev, "PCI write config failed\n"); | |
4989 | goto err_out_free_regions; | |
4990 | } | |
4991 | #endif | |
4992 | ||
9d731d77 | 4993 | wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; |
be63a21c | 4994 | |
cd28ab6a | 4995 | err = -ENOMEM; |
66466797 SH |
4996 | |
4997 | hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") | |
4998 | + strlen(pci_name(pdev)) + 1, GFP_KERNEL); | |
b2adaca9 | 4999 | if (!hw) |
cd28ab6a | 5000 | goto err_out_free_regions; |
cd28ab6a | 5001 | |
cd28ab6a | 5002 | hw->pdev = pdev; |
66466797 | 5003 | sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); |
cd28ab6a SH |
5004 | |
5005 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
5006 | if (!hw->regs) { | |
b02a9258 | 5007 | dev_err(&pdev->dev, "cannot map device registers\n"); |
cd28ab6a SH |
5008 | goto err_out_free_hw; |
5009 | } | |
5010 | ||
e3173832 | 5011 | err = sky2_init(hw); |
cd28ab6a | 5012 | if (err) |
793b883e | 5013 | goto err_out_iounmap; |
cd28ab6a | 5014 | |
efe91932 | 5015 | /* ring for status responses */ |
bf73130d | 5016 | hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); |
efe91932 | 5017 | hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
5018 | &hw->st_dma); | |
0bd8ba18 PST |
5019 | if (!hw->st_le) { |
5020 | err = -ENOMEM; | |
efe91932 | 5021 | goto err_out_reset; |
0bd8ba18 | 5022 | } |
efe91932 | 5023 | |
c844d483 SH |
5024 | dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", |
5025 | sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); | |
cd28ab6a | 5026 | |
e3173832 SH |
5027 | sky2_reset(hw); |
5028 | ||
be63a21c | 5029 | dev = sky2_init_netdev(hw, 0, using_dac, wol_default); |
7f60c64b | 5030 | if (!dev) { |
5031 | err = -ENOMEM; | |
cd28ab6a | 5032 | goto err_out_free_pci; |
7f60c64b | 5033 | } |
cd28ab6a | 5034 | |
9fa1b1f3 SH |
5035 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
5036 | err = sky2_test_msi(hw); | |
1c85382e | 5037 | if (err) { |
9fa1b1f3 | 5038 | pci_disable_msi(pdev); |
1c85382e LS |
5039 | if (err != -EOPNOTSUPP) |
5040 | goto err_out_free_netdev; | |
5041 | } | |
9fa1b1f3 SH |
5042 | } |
5043 | ||
731073b9 SG |
5044 | netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); |
5045 | ||
793b883e SH |
5046 | err = register_netdev(dev); |
5047 | if (err) { | |
b02a9258 | 5048 | dev_err(&pdev->dev, "cannot register net device\n"); |
cd28ab6a SH |
5049 | goto err_out_free_netdev; |
5050 | } | |
5051 | ||
33cb7d33 BP |
5052 | netif_carrier_off(dev); |
5053 | ||
cd28ab6a SH |
5054 | sky2_show_addr(dev); |
5055 | ||
7f60c64b | 5056 | if (hw->ports > 1) { |
be63a21c | 5057 | dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); |
0bdb0bd0 | 5058 | if (!dev1) { |
5059 | err = -ENOMEM; | |
5060 | goto err_out_unregister; | |
ca519274 | 5061 | } |
0bdb0bd0 | 5062 | |
5063 | err = register_netdev(dev1); | |
5064 | if (err) { | |
5065 | dev_err(&pdev->dev, "cannot register second net device\n"); | |
5066 | goto err_out_free_dev1; | |
5067 | } | |
5068 | ||
5069 | err = sky2_setup_irq(hw, hw->irq_name); | |
5070 | if (err) | |
5071 | goto err_out_unregister_dev1; | |
5072 | ||
5073 | sky2_show_addr(dev1); | |
cd28ab6a SH |
5074 | } |
5075 | ||
32c2c300 | 5076 | setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); |
81906791 SH |
5077 | INIT_WORK(&hw->restart_work, sky2_restart); |
5078 | ||
793b883e | 5079 | pci_set_drvdata(pdev, hw); |
1ae861e6 | 5080 | pdev->d3_delay = 150; |
793b883e | 5081 | |
cd28ab6a SH |
5082 | return 0; |
5083 | ||
0bdb0bd0 | 5084 | err_out_unregister_dev1: |
5085 | unregister_netdev(dev1); | |
5086 | err_out_free_dev1: | |
5087 | free_netdev(dev1); | |
793b883e | 5088 | err_out_unregister: |
793b883e | 5089 | unregister_netdev(dev); |
cd28ab6a | 5090 | err_out_free_netdev: |
1c85382e LS |
5091 | if (hw->flags & SKY2_HW_USE_MSI) |
5092 | pci_disable_msi(pdev); | |
cd28ab6a | 5093 | free_netdev(dev); |
cd28ab6a | 5094 | err_out_free_pci: |
efe91932 | 5095 | pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
5096 | hw->st_le, hw->st_dma); | |
5097 | err_out_reset: | |
793b883e | 5098 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
5099 | err_out_iounmap: |
5100 | iounmap(hw->regs); | |
5101 | err_out_free_hw: | |
5102 | kfree(hw); | |
5103 | err_out_free_regions: | |
5104 | pci_release_regions(pdev); | |
44a1d2e5 | 5105 | err_out_disable: |
cd28ab6a | 5106 | pci_disable_device(pdev); |
cd28ab6a SH |
5107 | err_out: |
5108 | return err; | |
5109 | } | |
5110 | ||
853e3f4c | 5111 | static void sky2_remove(struct pci_dev *pdev) |
cd28ab6a | 5112 | { |
793b883e | 5113 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
6de16237 | 5114 | int i; |
cd28ab6a | 5115 | |
793b883e | 5116 | if (!hw) |
cd28ab6a SH |
5117 | return; |
5118 | ||
32c2c300 | 5119 | del_timer_sync(&hw->watchdog_timer); |
6de16237 | 5120 | cancel_work_sync(&hw->restart_work); |
d27ed387 | 5121 | |
b877fe28 | 5122 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 | 5123 | unregister_netdev(hw->dev[i]); |
81906791 | 5124 | |
d27ed387 | 5125 | sky2_write32(hw, B0_IMSK, 0); |
0bdb0bd0 | 5126 | sky2_read32(hw, B0_IMSK); |
cd28ab6a | 5127 | |
ae306cca SH |
5128 | sky2_power_aux(hw); |
5129 | ||
793b883e | 5130 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 5131 | sky2_read8(hw, B0_CTST); |
cd28ab6a | 5132 | |
0bdb0bd0 | 5133 | if (hw->ports > 1) { |
5134 | napi_disable(&hw->napi); | |
5135 | free_irq(pdev->irq, hw); | |
5136 | } | |
5137 | ||
ea76e635 | 5138 | if (hw->flags & SKY2_HW_USE_MSI) |
b0a20ded | 5139 | pci_disable_msi(pdev); |
efe91932 | 5140 | pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), |
5141 | hw->st_le, hw->st_dma); | |
cd28ab6a SH |
5142 | pci_release_regions(pdev); |
5143 | pci_disable_device(pdev); | |
793b883e | 5144 | |
b877fe28 | 5145 | for (i = hw->ports-1; i >= 0; --i) |
6de16237 SH |
5146 | free_netdev(hw->dev[i]); |
5147 | ||
cd28ab6a SH |
5148 | iounmap(hw->regs); |
5149 | kfree(hw); | |
cd28ab6a SH |
5150 | } |
5151 | ||
0f333d10 | 5152 | static int sky2_suspend(struct device *dev) |
cd28ab6a | 5153 | { |
0f333d10 | 5154 | struct pci_dev *pdev = to_pci_dev(dev); |
793b883e | 5155 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
0f333d10 | 5156 | int i; |
cd28ab6a | 5157 | |
549a68c3 SH |
5158 | if (!hw) |
5159 | return 0; | |
5160 | ||
063a0b38 SH |
5161 | del_timer_sync(&hw->watchdog_timer); |
5162 | cancel_work_sync(&hw->restart_work); | |
5163 | ||
19720737 | 5164 | rtnl_lock(); |
3403aca2 MM |
5165 | |
5166 | sky2_all_down(hw); | |
f05267e7 | 5167 | for (i = 0; i < hw->ports; i++) { |
cd28ab6a | 5168 | struct net_device *dev = hw->dev[i]; |
e3173832 | 5169 | struct sky2_port *sky2 = netdev_priv(dev); |
cd28ab6a | 5170 | |
e3173832 SH |
5171 | if (sky2->wol) |
5172 | sky2_wol_init(sky2); | |
cd28ab6a SH |
5173 | } |
5174 | ||
ae306cca | 5175 | sky2_power_aux(hw); |
19720737 | 5176 | rtnl_unlock(); |
e3173832 | 5177 | |
2ccc99b7 | 5178 | return 0; |
cd28ab6a SH |
5179 | } |
5180 | ||
94252763 | 5181 | #ifdef CONFIG_PM_SLEEP |
0f333d10 | 5182 | static int sky2_resume(struct device *dev) |
cd28ab6a | 5183 | { |
0f333d10 | 5184 | struct pci_dev *pdev = to_pci_dev(dev); |
793b883e | 5185 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
3403aca2 | 5186 | int err; |
cd28ab6a | 5187 | |
549a68c3 SH |
5188 | if (!hw) |
5189 | return 0; | |
5190 | ||
1ad5b4a5 | 5191 | /* Re-enable all clocks */ |
a0db28b8 | 5192 | err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); |
5193 | if (err) { | |
5194 | dev_err(&pdev->dev, "PCI write config failed\n"); | |
5195 | goto out; | |
5196 | } | |
1ad5b4a5 | 5197 | |
3403aca2 | 5198 | rtnl_lock(); |
e3173832 | 5199 | sky2_reset(hw); |
3403aca2 | 5200 | sky2_all_up(hw); |
af18d8b8 | 5201 | rtnl_unlock(); |
eb35cf60 | 5202 | |
ae306cca | 5203 | return 0; |
08c06d8a | 5204 | out: |
af18d8b8 | 5205 | |
b02a9258 | 5206 | dev_err(&pdev->dev, "resume failed (%d)\n", err); |
ae306cca | 5207 | pci_disable_device(pdev); |
08c06d8a | 5208 | return err; |
cd28ab6a | 5209 | } |
0f333d10 RW |
5210 | |
5211 | static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); | |
5212 | #define SKY2_PM_OPS (&sky2_pm_ops) | |
5213 | ||
5214 | #else | |
5215 | ||
5216 | #define SKY2_PM_OPS NULL | |
cd28ab6a SH |
5217 | #endif |
5218 | ||
e3173832 SH |
5219 | static void sky2_shutdown(struct pci_dev *pdev) |
5220 | { | |
06ba3b21 JL |
5221 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5222 | int port; | |
5223 | ||
5224 | for (port = 0; port < hw->ports; port++) { | |
5225 | struct net_device *ndev = hw->dev[port]; | |
5226 | ||
5227 | rtnl_lock(); | |
5228 | if (netif_running(ndev)) { | |
5229 | dev_close(ndev); | |
5230 | netif_device_detach(ndev); | |
5231 | } | |
5232 | rtnl_unlock(); | |
5233 | } | |
0f333d10 RW |
5234 | sky2_suspend(&pdev->dev); |
5235 | pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); | |
5236 | pci_set_power_state(pdev, PCI_D3hot); | |
e3173832 SH |
5237 | } |
5238 | ||
cd28ab6a | 5239 | static struct pci_driver sky2_driver = { |
793b883e SH |
5240 | .name = DRV_NAME, |
5241 | .id_table = sky2_id_table, | |
5242 | .probe = sky2_probe, | |
853e3f4c | 5243 | .remove = sky2_remove, |
e3173832 | 5244 | .shutdown = sky2_shutdown, |
0f333d10 | 5245 | .driver.pm = SKY2_PM_OPS, |
cd28ab6a SH |
5246 | }; |
5247 | ||
5248 | static int __init sky2_init_module(void) | |
5249 | { | |
ada1db5c | 5250 | pr_info("driver version " DRV_VERSION "\n"); |
c844d483 | 5251 | |
3cf26753 | 5252 | sky2_debug_init(); |
50241c4c | 5253 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
5254 | } |
5255 | ||
5256 | static void __exit sky2_cleanup_module(void) | |
5257 | { | |
5258 | pci_unregister_driver(&sky2_driver); | |
3cf26753 | 5259 | sky2_debug_cleanup(); |
cd28ab6a SH |
5260 | } |
5261 | ||
5262 | module_init(sky2_init_module); | |
5263 | module_exit(sky2_cleanup_module); | |
5264 | ||
5265 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
65ebe634 | 5266 | MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); |
cd28ab6a | 5267 | MODULE_LICENSE("GPL"); |
5f4f9dc1 | 5268 | MODULE_VERSION(DRV_VERSION); |