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net: mediatek: remove unnecessary platform_set_drvdata()
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
53void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54{
55 __raw_writel(val, eth->base + reg);
56}
57
58u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59{
60 return __raw_readl(eth->base + reg);
61}
62
63static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64{
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77}
78
379672de
WY		 79static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
656e7052
JC		 81{
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96}
97
379672de 98static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 99{
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116}
117
118static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120{
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124}
125
126static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127{
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131}
132
133static void mtk_phy_link_adjust(struct net_device *dev)
134{
135 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
656e7052
JC		 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
08ef55c6 155 if (mac->phy_dev->duplex) {
656e7052
JC		 156 mcr |= MAC_MCR_FORCE_DPX;
157
08ef55c6
JC		 158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
656e7052
JC		 179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186}
187
188static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190{
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 210 if (!phydev) {
656e7052 211 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 212 return -ENODEV;
656e7052
JC		 213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223}
224
225static int mtk_phy_connect(struct mtk_mac *mac)
226{
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
656e7052
JC		 235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
37920fce
JC		 239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052
JC		 242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
248 case PHY_INTERFACE_MODE_RMII:
249 ge_mode = 2;
250 break;
251 default:
252 dev_err(eth->dev, "invalid phy_mode\n");
253 return -1;
254 }
255
256 /* put the gmac into the right mode */
257 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
258 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
259 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
260 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
261
262 mtk_phy_connect_node(eth, mac, np);
263 mac->phy_dev->autoneg = AUTONEG_ENABLE;
264 mac->phy_dev->speed = 0;
265 mac->phy_dev->duplex = 0;
08ef55c6
JC		 266 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
267 SUPPORTED_Asym_Pause;
656e7052
JC		 268 mac->phy_dev->advertising = mac->phy_dev->supported |
269 ADVERTISED_Autoneg;
270 phy_start_aneg(mac->phy_dev);
271
272 return 0;
273}
274
275static int mtk_mdio_init(struct mtk_eth *eth)
276{
277 struct device_node *mii_np;
278 int err;
279
280 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
281 if (!mii_np) {
282 dev_err(eth->dev, "no %s child node found", "mdio-bus");
283 return -ENODEV;
284 }
285
286 if (!of_device_is_available(mii_np)) {
287 err = 0;
288 goto err_put_node;
289 }
290
291 eth->mii_bus = mdiobus_alloc();
292 if (!eth->mii_bus) {
293 err = -ENOMEM;
294 goto err_put_node;
295 }
296
297 eth->mii_bus->name = "mdio";
298 eth->mii_bus->read = mtk_mdio_read;
299 eth->mii_bus->write = mtk_mdio_write;
300 eth->mii_bus->priv = eth;
301 eth->mii_bus->parent = eth->dev;
302
303 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
304 err = of_mdiobus_register(eth->mii_bus, mii_np);
305 if (err)
306 goto err_free_bus;
307
308 return 0;
309
310err_free_bus:
207bdf18 311 mdiobus_free(eth->mii_bus);
656e7052
JC		 312
313err_put_node:
314 of_node_put(mii_np);
315 eth->mii_bus = NULL;
316 return err;
317}
318
319static void mtk_mdio_cleanup(struct mtk_eth *eth)
320{
321 if (!eth->mii_bus)
322 return;
323
324 mdiobus_unregister(eth->mii_bus);
325 of_node_put(eth->mii_bus->dev.of_node);
207bdf18 326 mdiobus_free(eth->mii_bus);
656e7052
JC		 327}
328
329static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
330{
7bc9ccec 331 unsigned long flags;
656e7052
JC		 332 u32 val;
333
7bc9ccec 334 spin_lock_irqsave(&eth->irq_lock, flags);
656e7052
JC		 335 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
336 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
7bc9ccec 337 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 338}
339
340static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
341{
7bc9ccec 342 unsigned long flags;
656e7052
JC		 343 u32 val;
344
7bc9ccec 345 spin_lock_irqsave(&eth->irq_lock, flags);
656e7052
JC		 346 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
347 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
7bc9ccec 348 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 349}
350
351static int mtk_set_mac_address(struct net_device *dev, void *p)
352{
353 int ret = eth_mac_addr(dev, p);
354 struct mtk_mac *mac = netdev_priv(dev);
355 const char *macaddr = dev->dev_addr;
656e7052
JC		 356
357 if (ret)
358 return ret;
359
e3e9652a 360 spin_lock_bh(&mac->hw->page_lock);
656e7052
JC		 361 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
362 MTK_GDMA_MAC_ADRH(mac->id));
363 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
364 (macaddr[4] << 8) | macaddr[5],
365 MTK_GDMA_MAC_ADRL(mac->id));
e3e9652a 366 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 367
368 return 0;
369}
370
371void mtk_stats_update_mac(struct mtk_mac *mac)
372{
373 struct mtk_hw_stats *hw_stats = mac->hw_stats;
374 unsigned int base = MTK_GDM1_TX_GBCNT;
375 u64 stats;
376
377 base += hw_stats->reg_offset;
378
379 u64_stats_update_begin(&hw_stats->syncp);
380
381 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
382 stats = mtk_r32(mac->hw, base + 0x04);
383 if (stats)
384 hw_stats->rx_bytes += (stats << 32);
385 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
386 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
387 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
388 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
389 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
390 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
391 hw_stats->rx_flow_control_packets +=
392 mtk_r32(mac->hw, base + 0x24);
393 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
394 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
395 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
396 stats = mtk_r32(mac->hw, base + 0x34);
397 if (stats)
398 hw_stats->tx_bytes += (stats << 32);
399 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
400 u64_stats_update_end(&hw_stats->syncp);
401}
402
403static void mtk_stats_update(struct mtk_eth *eth)
404{
405 int i;
406
407 for (i = 0; i < MTK_MAC_COUNT; i++) {
408 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
409 continue;
410 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
411 mtk_stats_update_mac(eth->mac[i]);
412 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
413 }
414 }
415}
416
417static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
418 struct rtnl_link_stats64 *storage)
419{
420 struct mtk_mac *mac = netdev_priv(dev);
421 struct mtk_hw_stats *hw_stats = mac->hw_stats;
422 unsigned int start;
423
424 if (netif_running(dev) && netif_device_present(dev)) {
425 if (spin_trylock(&hw_stats->stats_lock)) {
426 mtk_stats_update_mac(mac);
427 spin_unlock(&hw_stats->stats_lock);
428 }
429 }
430
431 do {
432 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
433 storage->rx_packets = hw_stats->rx_packets;
434 storage->tx_packets = hw_stats->tx_packets;
435 storage->rx_bytes = hw_stats->rx_bytes;
436 storage->tx_bytes = hw_stats->tx_bytes;
437 storage->collisions = hw_stats->tx_collisions;
438 storage->rx_length_errors = hw_stats->rx_short_errors +
439 hw_stats->rx_long_errors;
440 storage->rx_over_errors = hw_stats->rx_overflow;
441 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
442 storage->rx_errors = hw_stats->rx_checksum_errors;
443 storage->tx_aborted_errors = hw_stats->tx_skip;
444 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
445
446 storage->tx_errors = dev->stats.tx_errors;
447 storage->rx_dropped = dev->stats.rx_dropped;
448 storage->tx_dropped = dev->stats.tx_dropped;
449
450 return storage;
451}
452
453static inline int mtk_max_frag_size(int mtu)
454{
455 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
456 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
457 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
458
459 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
460 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
461}
462
463static inline int mtk_max_buf_size(int frag_size)
464{
465 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
466 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
467
468 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
469
470 return buf_size;
471}
472
473static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
474 struct mtk_rx_dma *dma_rxd)
475{
476 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
477 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
478 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
479 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
480}
481
482/* the qdma core needs scratch memory to be setup */
483static int mtk_init_fq_dma(struct mtk_eth *eth)
484{
605e4fe4 485 dma_addr_t phy_ring_tail;
656e7052
JC		 486 int cnt = MTK_DMA_SIZE;
487 dma_addr_t dma_addr;
488 int i;
489
490 eth->scratch_ring = dma_alloc_coherent(eth->dev,
491 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 492 &eth->phy_scratch_ring,
656e7052
JC		 493 GFP_ATOMIC | __GFP_ZERO);
494 if (unlikely(!eth->scratch_ring))
495 return -ENOMEM;
496
497 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
498 GFP_KERNEL);
562c5a70
JC		 499 if (unlikely(!eth->scratch_head))
500 return -ENOMEM;
501
656e7052
JC		 502 dma_addr = dma_map_single(eth->dev,
503 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
504 DMA_FROM_DEVICE);
505 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
506 return -ENOMEM;
507
508 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 509 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 510 (sizeof(struct mtk_tx_dma) * (cnt - 1));
511
512 for (i = 0; i < cnt; i++) {
513 eth->scratch_ring[i].txd1 =
514 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
515 if (i < cnt - 1)
605e4fe4 516 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 517 ((i + 1) * sizeof(struct mtk_tx_dma)));
518 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
519 }
520
605e4fe4 521 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 522 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
523 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
524 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
525
526 return 0;
527}
528
529static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
530{
531 void *ret = ring->dma;
532
533 return ret + (desc - ring->phys);
534}
535
536static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
537 struct mtk_tx_dma *txd)
538{
539 int idx = txd - ring->dma;
540
541 return &ring->buf[idx];
542}
543
544static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
545{
546 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
547 dma_unmap_single(dev,
548 dma_unmap_addr(tx_buf, dma_addr0),
549 dma_unmap_len(tx_buf, dma_len0),
550 DMA_TO_DEVICE);
551 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
552 dma_unmap_page(dev,
553 dma_unmap_addr(tx_buf, dma_addr0),
554 dma_unmap_len(tx_buf, dma_len0),
555 DMA_TO_DEVICE);
556 }
557 tx_buf->flags = 0;
558 if (tx_buf->skb &&
559 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
560 dev_kfree_skb_any(tx_buf->skb);
561 tx_buf->skb = NULL;
562}
563
564static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
565 int tx_num, struct mtk_tx_ring *ring, bool gso)
566{
567 struct mtk_mac *mac = netdev_priv(dev);
568 struct mtk_eth *eth = mac->hw;
569 struct mtk_tx_dma *itxd, *txd;
570 struct mtk_tx_buf *tx_buf;
656e7052
JC		 571 dma_addr_t mapped_addr;
572 unsigned int nr_frags;
573 int i, n_desc = 1;
574 u32 txd4 = 0;
575
576 itxd = ring->next_free;
577 if (itxd == ring->last_free)
578 return -ENOMEM;
579
580 /* set the forward port */
581 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
582
583 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
584 memset(tx_buf, 0, sizeof(*tx_buf));
585
586 if (gso)
587 txd4 |= TX_DMA_TSO;
588
589 /* TX Checksum offload */
590 if (skb->ip_summed == CHECKSUM_PARTIAL)
591 txd4 |= TX_DMA_CHKSUM;
592
593 /* VLAN header offload */
594 if (skb_vlan_tag_present(skb))
595 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
596
597 mapped_addr = dma_map_single(&dev->dev, skb->data,
598 skb_headlen(skb), DMA_TO_DEVICE);
599 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
600 return -ENOMEM;
601
656e7052
JC		 602 WRITE_ONCE(itxd->txd1, mapped_addr);
603 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
604 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
605 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
606
607 /* TX SG offload */
608 txd = itxd;
609 nr_frags = skb_shinfo(skb)->nr_frags;
610 for (i = 0; i < nr_frags; i++) {
611 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
612 unsigned int offset = 0;
613 int frag_size = skb_frag_size(frag);
614
615 while (frag_size) {
616 bool last_frag = false;
617 unsigned int frag_map_size;
618
619 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
620 if (txd == ring->last_free)
621 goto err_dma;
622
623 n_desc++;
624 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
625 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
626 frag_map_size,
627 DMA_TO_DEVICE);
628 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
629 goto err_dma;
630
631 if (i == nr_frags - 1 &&
632 (frag_size - frag_map_size) == 0)
633 last_frag = true;
634
635 WRITE_ONCE(txd->txd1, mapped_addr);
636 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
637 TX_DMA_PLEN0(frag_map_size) |
369f0453 638 last_frag * TX_DMA_LS0));
656e7052
JC		 639 WRITE_ONCE(txd->txd4, 0);
640
641 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
642 tx_buf = mtk_desc_to_tx_buf(ring, txd);
643 memset(tx_buf, 0, sizeof(*tx_buf));
644
645 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
646 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
647 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
648 frag_size -= frag_map_size;
649 offset += frag_map_size;
650 }
651 }
652
653 /* store skb to cleanup */
654 tx_buf->skb = skb;
655
656 WRITE_ONCE(itxd->txd4, txd4);
657 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
658 (!nr_frags * TX_DMA_LS0)));
659
656e7052
JC		 660 netdev_sent_queue(dev, skb->len);
661 skb_tx_timestamp(skb);
662
663 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
664 atomic_sub(n_desc, &ring->free_count);
665
666 /* make sure that all changes to the dma ring are flushed before we
667 * continue
668 */
669 wmb();
670
671 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
672 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
673
674 return 0;
675
676err_dma:
677 do {
2fae723c 678 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 679
680 /* unmap dma */
681 mtk_tx_unmap(&dev->dev, tx_buf);
682
683 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
684 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
685 } while (itxd != txd);
686
687 return -ENOMEM;
688}
689
690static inline int mtk_cal_txd_req(struct sk_buff *skb)
691{
692 int i, nfrags;
693 struct skb_frag_struct *frag;
694
695 nfrags = 1;
696 if (skb_is_gso(skb)) {
697 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
698 frag = &skb_shinfo(skb)->frags[i];
699 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
700 }
701 } else {
702 nfrags += skb_shinfo(skb)->nr_frags;
703 }
704
beeb4ca4 705 return nfrags;
656e7052
JC		 706}
707
ad3cba98
JC		 708static int mtk_queue_stopped(struct mtk_eth *eth)
709{
710 int i;
711
712 for (i = 0; i < MTK_MAC_COUNT; i++) {
713 if (!eth->netdev[i])
714 continue;
715 if (netif_queue_stopped(eth->netdev[i]))
716 return 1;
717 }
718
719 return 0;
720}
721
13c822f6
JC		 722static void mtk_wake_queue(struct mtk_eth *eth)
723{
724 int i;
725
726 for (i = 0; i < MTK_MAC_COUNT; i++) {
727 if (!eth->netdev[i])
728 continue;
729 netif_wake_queue(eth->netdev[i]);
730 }
731}
732
733static void mtk_stop_queue(struct mtk_eth *eth)
734{
735 int i;
736
737 for (i = 0; i < MTK_MAC_COUNT; i++) {
738 if (!eth->netdev[i])
739 continue;
740 netif_stop_queue(eth->netdev[i]);
741 }
742}
743
656e7052
JC		 744static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
745{
746 struct mtk_mac *mac = netdev_priv(dev);
747 struct mtk_eth *eth = mac->hw;
748 struct mtk_tx_ring *ring = &eth->tx_ring;
749 struct net_device_stats *stats = &dev->stats;
750 bool gso = false;
751 int tx_num;
752
34c2e4c9
JC		 753 /* normally we can rely on the stack not calling this more than once,
754 * however we have 2 queues running on the same ring so we need to lock
755 * the ring access
756 */
e3e9652a 757 spin_lock(&eth->page_lock);
34c2e4c9 758
656e7052
JC		 759 tx_num = mtk_cal_txd_req(skb);
760 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 761 mtk_stop_queue(eth);
656e7052
JC		 762 netif_err(eth, tx_queued, dev,
763 "Tx Ring full when queue awake!\n");
e3e9652a 764 spin_unlock(&eth->page_lock);
656e7052
JC		 765 return NETDEV_TX_BUSY;
766 }
767
768 /* TSO: fill MSS info in tcp checksum field */
769 if (skb_is_gso(skb)) {
770 if (skb_cow_head(skb, 0)) {
771 netif_warn(eth, tx_err, dev,
772 "GSO expand head fail.\n");
773 goto drop;
774 }
775
776 if (skb_shinfo(skb)->gso_type &
777 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
778 gso = true;
779 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
780 }
781 }
782
783 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
784 goto drop;
785
82c6544d 786 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 787 mtk_stop_queue(eth);
82c6544d 788
e3e9652a 789 spin_unlock(&eth->page_lock);
656e7052
JC		 790
791 return NETDEV_TX_OK;
792
793drop:
e3e9652a 794 spin_unlock(&eth->page_lock);
656e7052
JC		 795 stats->tx_dropped++;
796 dev_kfree_skb(skb);
797 return NETDEV_TX_OK;
798}
799
800static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 801 struct mtk_eth *eth)
656e7052
JC		 802{
803 struct mtk_rx_ring *ring = &eth->rx_ring;
804 int idx = ring->calc_idx;
805 struct sk_buff *skb;
806 u8 *data, *new_data;
807 struct mtk_rx_dma *rxd, trxd;
808 int done = 0;
809
810 while (done < budget) {
811 struct net_device *netdev;
812 unsigned int pktlen;
813 dma_addr_t dma_addr;
814 int mac = 0;
815
816 idx = NEXT_RX_DESP_IDX(idx);
817 rxd = &ring->dma[idx];
818 data = ring->data[idx];
819
820 mtk_rx_get_desc(&trxd, rxd);
821 if (!(trxd.rxd2 & RX_DMA_DONE))
822 break;
823
824 /* find out which mac the packet come from. values start at 1 */
825 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
826 RX_DMA_FPORT_MASK;
827 mac--;
828
829 netdev = eth->netdev[mac];
830
831 /* alloc new buffer */
832 new_data = napi_alloc_frag(ring->frag_size);
833 if (unlikely(!new_data)) {
834 netdev->stats.rx_dropped++;
835 goto release_desc;
836 }
837 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
838 new_data + NET_SKB_PAD,
839 ring->buf_size,
840 DMA_FROM_DEVICE);
841 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
842 skb_free_frag(new_data);
94321a9f 843 netdev->stats.rx_dropped++;
656e7052
JC		 844 goto release_desc;
845 }
846
847 /* receive data */
848 skb = build_skb(data, ring->frag_size);
849 if (unlikely(!skb)) {
850 put_page(virt_to_head_page(new_data));
94321a9f 851 netdev->stats.rx_dropped++;
656e7052
JC		 852 goto release_desc;
853 }
854 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
855
856 dma_unmap_single(&netdev->dev, trxd.rxd1,
857 ring->buf_size, DMA_FROM_DEVICE);
858 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
859 skb->dev = netdev;
860 skb_put(skb, pktlen);
861 if (trxd.rxd4 & RX_DMA_L4_VALID)
862 skb->ip_summed = CHECKSUM_UNNECESSARY;
863 else
864 skb_checksum_none_assert(skb);
865 skb->protocol = eth_type_trans(skb, netdev);
866
867 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
868 RX_DMA_VID(trxd.rxd3))
869 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
870 RX_DMA_VID(trxd.rxd3));
871 napi_gro_receive(napi, skb);
872
873 ring->data[idx] = new_data;
874 rxd->rxd1 = (unsigned int)dma_addr;
875
876release_desc:
877 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
878
879 ring->calc_idx = idx;
880 /* make sure that all changes to the dma ring are flushed before
881 * we continue
882 */
883 wmb();
884 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
885 done++;
886 }
887
888 if (done < budget)
eece71e8 889 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
656e7052
JC		 890
891 return done;
892}
893
80673029 894static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 895{
896 struct mtk_tx_ring *ring = &eth->tx_ring;
897 struct mtk_tx_dma *desc;
898 struct sk_buff *skb;
899 struct mtk_tx_buf *tx_buf;
80673029 900 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 901 unsigned int bytes[MTK_MAX_DEVS];
902 u32 cpu, dma;
903 static int condition;
80673029 904 int total = 0, i;
656e7052
JC		 905
906 memset(done, 0, sizeof(done));
907 memset(bytes, 0, sizeof(bytes));
908
909 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
910 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
911
912 desc = mtk_qdma_phys_to_virt(ring, cpu);
913
914 while ((cpu != dma) && budget) {
915 u32 next_cpu = desc->txd2;
916 int mac;
917
918 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
919 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
920 break;
921
922 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
923 TX_DMA_FPORT_MASK;
924 mac--;
925
926 tx_buf = mtk_desc_to_tx_buf(ring, desc);
927 skb = tx_buf->skb;
928 if (!skb) {
929 condition = 1;
930 break;
931 }
932
933 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
934 bytes[mac] += skb->len;
935 done[mac]++;
936 budget--;
937 }
938 mtk_tx_unmap(eth->dev, tx_buf);
939
656e7052
JC		 940 ring->last_free = desc;
941 atomic_inc(&ring->free_count);
942
943 cpu = next_cpu;
944 }
945
946 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
947
948 for (i = 0; i < MTK_MAC_COUNT; i++) {
949 if (!eth->netdev[i] || !done[i])
950 continue;
951 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
952 total += done[i];
953 }
954
ad3cba98
JC		 955 if (mtk_queue_stopped(eth) &&
956 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 957 mtk_wake_queue(eth);
656e7052
JC		 958
959 return total;
960}
961
80673029 962static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 963{
80673029 964 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 965
eece71e8 966 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 967 mtk_stats_update(eth);
eece71e8
JC		 968 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
969 MTK_INT_STATUS2);
656e7052 970 }
80673029
JC		 971}
972
973static int mtk_napi_tx(struct napi_struct *napi, int budget)
974{
975 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
976 u32 status, mask;
977 int tx_done = 0;
978
979 mtk_handle_status_irq(eth);
980 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
981 tx_done = mtk_poll_tx(eth, budget);
982
983 if (unlikely(netif_msg_intr(eth))) {
984 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
985 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
986 dev_info(eth->dev,
987 "done tx %d, intr 0x%08x/0x%x\n",
988 tx_done, status, mask);
989 }
990
991 if (tx_done == budget)
992 return budget;
993
994 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
995 if (status & MTK_TX_DONE_INT)
996 return budget;
997
998 napi_complete(napi);
999 mtk_irq_enable(eth, MTK_TX_DONE_INT);
1000
1001 return tx_done;
1002}
1003
1004static int mtk_napi_rx(struct napi_struct *napi, int budget)
1005{
1006 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1007 u32 status, mask;
1008 int rx_done = 0;
1009
1010 mtk_handle_status_irq(eth);
1011 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
1012 rx_done = mtk_poll_rx(napi, budget, eth);
656e7052
JC		 1013
1014 if (unlikely(netif_msg_intr(eth))) {
80673029 1015 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
656e7052 1016 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
80673029
JC		 1017 dev_info(eth->dev,
1018 "done rx %d, intr 0x%08x/0x%x\n",
1019 rx_done, status, mask);
656e7052
JC		 1020 }
1021
80673029 1022 if (rx_done == budget)
656e7052
JC		 1023 return budget;
1024
1025 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
80673029 1026 if (status & MTK_RX_DONE_INT)
656e7052
JC		 1027 return budget;
1028
1029 napi_complete(napi);
80673029 1030 mtk_irq_enable(eth, MTK_RX_DONE_INT);
656e7052
JC		 1031
1032 return rx_done;
1033}
1034
1035static int mtk_tx_alloc(struct mtk_eth *eth)
1036{
1037 struct mtk_tx_ring *ring = &eth->tx_ring;
1038 int i, sz = sizeof(*ring->dma);
1039
1040 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1041 GFP_KERNEL);
1042 if (!ring->buf)
1043 goto no_tx_mem;
1044
1045 ring->dma = dma_alloc_coherent(eth->dev,
1046 MTK_DMA_SIZE * sz,
1047 &ring->phys,
1048 GFP_ATOMIC | __GFP_ZERO);
1049 if (!ring->dma)
1050 goto no_tx_mem;
1051
1052 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1053 for (i = 0; i < MTK_DMA_SIZE; i++) {
1054 int next = (i + 1) % MTK_DMA_SIZE;
1055 u32 next_ptr = ring->phys + next * sz;
1056
1057 ring->dma[i].txd2 = next_ptr;
1058 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1059 }
1060
1061 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1062 ring->next_free = &ring->dma[0];
12c97c13 1063 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1064 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1065
1066 /* make sure that all changes to the dma ring are flushed before we
1067 * continue
1068 */
1069 wmb();
1070
1071 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1072 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1073 mtk_w32(eth,
1074 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1075 MTK_QTX_CRX_PTR);
1076 mtk_w32(eth,
1077 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1078 MTK_QTX_DRX_PTR);
1079
1080 return 0;
1081
1082no_tx_mem:
1083 return -ENOMEM;
1084}
1085
1086static void mtk_tx_clean(struct mtk_eth *eth)
1087{
1088 struct mtk_tx_ring *ring = &eth->tx_ring;
1089 int i;
1090
1091 if (ring->buf) {
1092 for (i = 0; i < MTK_DMA_SIZE; i++)
1093 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1094 kfree(ring->buf);
1095 ring->buf = NULL;
1096 }
1097
1098 if (ring->dma) {
1099 dma_free_coherent(eth->dev,
1100 MTK_DMA_SIZE * sizeof(*ring->dma),
1101 ring->dma,
1102 ring->phys);
1103 ring->dma = NULL;
1104 }
1105}
1106
1107static int mtk_rx_alloc(struct mtk_eth *eth)
1108{
1109 struct mtk_rx_ring *ring = &eth->rx_ring;
1110 int i;
1111
1112 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1113 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1114 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1115 GFP_KERNEL);
1116 if (!ring->data)
1117 return -ENOMEM;
1118
1119 for (i = 0; i < MTK_DMA_SIZE; i++) {
1120 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1121 if (!ring->data[i])
1122 return -ENOMEM;
1123 }
1124
1125 ring->dma = dma_alloc_coherent(eth->dev,
1126 MTK_DMA_SIZE * sizeof(*ring->dma),
1127 &ring->phys,
1128 GFP_ATOMIC | __GFP_ZERO);
1129 if (!ring->dma)
1130 return -ENOMEM;
1131
1132 for (i = 0; i < MTK_DMA_SIZE; i++) {
1133 dma_addr_t dma_addr = dma_map_single(eth->dev,
1134 ring->data[i] + NET_SKB_PAD,
1135 ring->buf_size,
1136 DMA_FROM_DEVICE);
1137 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1138 return -ENOMEM;
1139 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1140
1141 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1142 }
1143 ring->calc_idx = MTK_DMA_SIZE - 1;
1144 /* make sure that all changes to the dma ring are flushed before we
1145 * continue
1146 */
1147 wmb();
1148
1149 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1150 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1151 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1152 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1153 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1154
1155 return 0;
1156}
1157
1158static void mtk_rx_clean(struct mtk_eth *eth)
1159{
1160 struct mtk_rx_ring *ring = &eth->rx_ring;
1161 int i;
1162
1163 if (ring->data && ring->dma) {
1164 for (i = 0; i < MTK_DMA_SIZE; i++) {
1165 if (!ring->data[i])
1166 continue;
1167 if (!ring->dma[i].rxd1)
1168 continue;
1169 dma_unmap_single(eth->dev,
1170 ring->dma[i].rxd1,
1171 ring->buf_size,
1172 DMA_FROM_DEVICE);
1173 skb_free_frag(ring->data[i]);
1174 }
1175 kfree(ring->data);
1176 ring->data = NULL;
1177 }
1178
1179 if (ring->dma) {
1180 dma_free_coherent(eth->dev,
1181 MTK_DMA_SIZE * sizeof(*ring->dma),
1182 ring->dma,
1183 ring->phys);
1184 ring->dma = NULL;
1185 }
1186}
1187
1188/* wait for DMA to finish whatever it is doing before we start using it again */
1189static int mtk_dma_busy_wait(struct mtk_eth *eth)
1190{
1191 unsigned long t_start = jiffies;
1192
1193 while (1) {
1194 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1195 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1196 return 0;
1197 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1198 break;
1199 }
1200
1201 dev_err(eth->dev, "DMA init timeout\n");
1202 return -1;
1203}
1204
1205static int mtk_dma_init(struct mtk_eth *eth)
1206{
1207 int err;
1208
1209 if (mtk_dma_busy_wait(eth))
1210 return -EBUSY;
1211
1212 /* QDMA needs scratch memory for internal reordering of the
1213 * descriptors
1214 */
1215 err = mtk_init_fq_dma(eth);
1216 if (err)
1217 return err;
1218
1219 err = mtk_tx_alloc(eth);
1220 if (err)
1221 return err;
1222
1223 err = mtk_rx_alloc(eth);
1224 if (err)
1225 return err;
1226
1227 /* Enable random early drop and set drop threshold automatically */
1228 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1229 MTK_QDMA_FC_THRES);
1230 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1231
1232 return 0;
1233}
1234
1235static void mtk_dma_free(struct mtk_eth *eth)
1236{
1237 int i;
1238
1239 for (i = 0; i < MTK_MAC_COUNT; i++)
1240 if (eth->netdev[i])
1241 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1242 if (eth->scratch_ring) {
1243 dma_free_coherent(eth->dev,
1244 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1245 eth->scratch_ring,
1246 eth->phy_scratch_ring);
1247 eth->scratch_ring = NULL;
1248 eth->phy_scratch_ring = 0;
1249 }
656e7052
JC		 1250 mtk_tx_clean(eth);
1251 mtk_rx_clean(eth);
1252 kfree(eth->scratch_head);
1253}
1254
1255static void mtk_tx_timeout(struct net_device *dev)
1256{
1257 struct mtk_mac *mac = netdev_priv(dev);
1258 struct mtk_eth *eth = mac->hw;
1259
1260 eth->netdev[mac->id]->stats.tx_errors++;
1261 netif_err(eth, tx_err, dev,
1262 "transmit timed out\n");
7c78b4ad 1263 schedule_work(&eth->pending_work);
656e7052
JC		 1264}
1265
80673029 1266static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1267{
1268 struct mtk_eth *eth = _eth;
656e7052 1269
80673029
JC		 1270 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1271 __napi_schedule(&eth->rx_napi);
1272 mtk_irq_disable(eth, MTK_RX_DONE_INT);
1273 }
656e7052 1274
80673029
JC		 1275 return IRQ_HANDLED;
1276}
1277
1278static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1279{
1280 struct mtk_eth *eth = _eth;
1281
1282 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1283 __napi_schedule(&eth->tx_napi);
1284 mtk_irq_disable(eth, MTK_TX_DONE_INT);
656e7052 1285 }
656e7052
JC		 1286
1287 return IRQ_HANDLED;
1288}
1289
1290#ifdef CONFIG_NET_POLL_CONTROLLER
1291static void mtk_poll_controller(struct net_device *dev)
1292{
1293 struct mtk_mac *mac = netdev_priv(dev);
1294 struct mtk_eth *eth = mac->hw;
1295 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1296
1297 mtk_irq_disable(eth, int_mask);
8186f6e3 1298 mtk_handle_irq_rx(eth->irq[2], dev);
656e7052
JC		 1299 mtk_irq_enable(eth, int_mask);
1300}
1301#endif
1302
1303static int mtk_start_dma(struct mtk_eth *eth)
1304{
1305 int err;
1306
1307 err = mtk_dma_init(eth);
1308 if (err) {
1309 mtk_dma_free(eth);
1310 return err;
1311 }
1312
1313 mtk_w32(eth,
1314 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1315 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
6675086d 1316 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1317 MTK_QDMA_GLO_CFG);
1318
1319 return 0;
1320}
1321
1322static int mtk_open(struct net_device *dev)
1323{
1324 struct mtk_mac *mac = netdev_priv(dev);
1325 struct mtk_eth *eth = mac->hw;
1326
1327 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1328 if (!atomic_read(&eth->dma_refcnt)) {
1329 int err = mtk_start_dma(eth);
1330
1331 if (err)
1332 return err;
1333
80673029 1334 napi_enable(&eth->tx_napi);
656e7052
JC		 1335 napi_enable(&eth->rx_napi);
1336 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1337 }
1338 atomic_inc(&eth->dma_refcnt);
1339
1340 phy_start(mac->phy_dev);
1341 netif_start_queue(dev);
1342
1343 return 0;
1344}
1345
1346static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1347{
656e7052
JC		 1348 u32 val;
1349 int i;
1350
1351 /* stop the dma engine */
e3e9652a 1352 spin_lock_bh(&eth->page_lock);
656e7052
JC		 1353 val = mtk_r32(eth, glo_cfg);
1354 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1355 glo_cfg);
e3e9652a 1356 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 1357
1358 /* wait for dma stop */
1359 for (i = 0; i < 10; i++) {
1360 val = mtk_r32(eth, glo_cfg);
1361 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1362 msleep(20);
1363 continue;
1364 }
1365 break;
1366 }
1367}
1368
1369static int mtk_stop(struct net_device *dev)
1370{
1371 struct mtk_mac *mac = netdev_priv(dev);
1372 struct mtk_eth *eth = mac->hw;
1373
1374 netif_tx_disable(dev);
1375 phy_stop(mac->phy_dev);
1376
1377 /* only shutdown DMA if this is the last user */
1378 if (!atomic_dec_and_test(&eth->dma_refcnt))
1379 return 0;
1380
1381 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
80673029 1382 napi_disable(&eth->tx_napi);
656e7052
JC		 1383 napi_disable(&eth->rx_napi);
1384
1385 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1386
1387 mtk_dma_free(eth);
1388
1389 return 0;
1390}
1391
1392static int __init mtk_hw_init(struct mtk_eth *eth)
1393{
1394 int err, i;
1395
1396 /* reset the frame engine */
1397 reset_control_assert(eth->rstc);
1398 usleep_range(10, 20);
1399 reset_control_deassert(eth->rstc);
1400 usleep_range(10, 20);
1401
1402 /* Set GE2 driving and slew rate */
1403 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1404
1405 /* set GE2 TDSEL */
1406 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1407
1408 /* set GE2 TUNE */
1409 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1410
1411 /* GE1, Force 1000M/FD, FC ON */
1412 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1413
1414 /* GE2, Force 1000M/FD, FC ON */
1415 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1416
1417 /* Enable RX VLan Offloading */
1418 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1419
80673029
JC		 1420 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1421 dev_name(eth->dev), eth);
1422 if (err)
1423 return err;
1424 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
656e7052
JC		 1425 dev_name(eth->dev), eth);
1426 if (err)
1427 return err;
1428
1429 err = mtk_mdio_init(eth);
1430 if (err)
1431 return err;
1432
1433 /* disable delay and normal interrupt */
1434 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2ff0bb61 1435 mtk_irq_disable(eth, ~0);
656e7052
JC		 1436 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1437 mtk_w32(eth, 0, MTK_RST_GL);
1438
1439 /* FE int grouping */
80673029
JC		 1440 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1441 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1442 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1443 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1444 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1445
1446 for (i = 0; i < 2; i++) {
1447 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1448
1449 /* setup the forward port to send frame to QDMA */
1450 val &= ~0xffff;
1451 val |= 0x5555;
1452
1453 /* Enable RX checksum */
1454 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1455
1456 /* setup the mac dma */
1457 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1458 }
1459
1460 return 0;
1461}
1462
1463static int __init mtk_init(struct net_device *dev)
1464{
1465 struct mtk_mac *mac = netdev_priv(dev);
1466 struct mtk_eth *eth = mac->hw;
1467 const char *mac_addr;
1468
1469 mac_addr = of_get_mac_address(mac->of_node);
1470 if (mac_addr)
1471 ether_addr_copy(dev->dev_addr, mac_addr);
1472
1473 /* If the mac address is invalid, use random mac address */
1474 if (!is_valid_ether_addr(dev->dev_addr)) {
1475 random_ether_addr(dev->dev_addr);
1476 dev_err(eth->dev, "generated random MAC address %pM\n",
1477 dev->dev_addr);
1478 dev->addr_assign_type = NET_ADDR_RANDOM;
1479 }
1480
1481 return mtk_phy_connect(mac);
1482}
1483
1484static void mtk_uninit(struct net_device *dev)
1485{
1486 struct mtk_mac *mac = netdev_priv(dev);
1487 struct mtk_eth *eth = mac->hw;
1488
1489 phy_disconnect(mac->phy_dev);
1490 mtk_mdio_cleanup(eth);
1491 mtk_irq_disable(eth, ~0);
80673029
JC		 1492 free_irq(eth->irq[1], dev);
1493 free_irq(eth->irq[2], dev);
656e7052
JC		 1494}
1495
1496static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1497{
1498 struct mtk_mac *mac = netdev_priv(dev);
1499
1500 switch (cmd) {
1501 case SIOCGMIIPHY:
1502 case SIOCGMIIREG:
1503 case SIOCSMIIREG:
1504 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1505 default:
1506 break;
1507 }
1508
1509 return -EOPNOTSUPP;
1510}
1511
1512static void mtk_pending_work(struct work_struct *work)
1513{
7c78b4ad 1514 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1515 int err, i;
1516 unsigned long restart = 0;
656e7052
JC		 1517
1518 rtnl_lock();
656e7052 1519
e7d425dc
JC		 1520 /* stop all devices to make sure that dma is properly shut down */
1521 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1522 if (!eth->netdev[i])
e7d425dc
JC		 1523 continue;
1524 mtk_stop(eth->netdev[i]);
1525 __set_bit(i, &restart);
1526 }
1527
1528 /* restart DMA and enable IRQs */
1529 for (i = 0; i < MTK_MAC_COUNT; i++) {
1530 if (!test_bit(i, &restart))
1531 continue;
1532 err = mtk_open(eth->netdev[i]);
1533 if (err) {
1534 netif_alert(eth, ifup, eth->netdev[i],
1535 "Driver up/down cycle failed, closing device.\n");
1536 dev_close(eth->netdev[i]);
1537 }
656e7052
JC		 1538 }
1539 rtnl_unlock();
1540}
1541
1542static int mtk_cleanup(struct mtk_eth *eth)
1543{
1544 int i;
1545
1546 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1547 if (!eth->netdev[i])
1548 continue;
1549
1550 unregister_netdev(eth->netdev[i]);
1551 free_netdev(eth->netdev[i]);
656e7052 1552 }
7c78b4ad 1553 cancel_work_sync(&eth->pending_work);
656e7052
JC		 1554
1555 return 0;
1556}
1557
1558static int mtk_get_settings(struct net_device *dev,
1559 struct ethtool_cmd *cmd)
1560{
1561 struct mtk_mac *mac = netdev_priv(dev);
1562 int err;
1563
1564 err = phy_read_status(mac->phy_dev);
1565 if (err)
1566 return -ENODEV;
1567
1568 return phy_ethtool_gset(mac->phy_dev, cmd);
1569}
1570
1571static int mtk_set_settings(struct net_device *dev,
1572 struct ethtool_cmd *cmd)
1573{
1574 struct mtk_mac *mac = netdev_priv(dev);
1575
1576 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1577 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1578 cmd->phy_address);
1579 if (!mac->phy_dev)
1580 return -ENODEV;
1581 }
1582
1583 return phy_ethtool_sset(mac->phy_dev, cmd);
1584}
1585
1586static void mtk_get_drvinfo(struct net_device *dev,
1587 struct ethtool_drvinfo *info)
1588{
1589 struct mtk_mac *mac = netdev_priv(dev);
1590
1591 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1592 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1593 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1594}
1595
1596static u32 mtk_get_msglevel(struct net_device *dev)
1597{
1598 struct mtk_mac *mac = netdev_priv(dev);
1599
1600 return mac->hw->msg_enable;
1601}
1602
1603static void mtk_set_msglevel(struct net_device *dev, u32 value)
1604{
1605 struct mtk_mac *mac = netdev_priv(dev);
1606
1607 mac->hw->msg_enable = value;
1608}
1609
1610static int mtk_nway_reset(struct net_device *dev)
1611{
1612 struct mtk_mac *mac = netdev_priv(dev);
1613
1614 return genphy_restart_aneg(mac->phy_dev);
1615}
1616
1617static u32 mtk_get_link(struct net_device *dev)
1618{
1619 struct mtk_mac *mac = netdev_priv(dev);
1620 int err;
1621
1622 err = genphy_update_link(mac->phy_dev);
1623 if (err)
1624 return ethtool_op_get_link(dev);
1625
1626 return mac->phy_dev->link;
1627}
1628
1629static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1630{
1631 int i;
1632
1633 switch (stringset) {
1634 case ETH_SS_STATS:
1635 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1636 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1637 data += ETH_GSTRING_LEN;
1638 }
1639 break;
1640 }
1641}
1642
1643static int mtk_get_sset_count(struct net_device *dev, int sset)
1644{
1645 switch (sset) {
1646 case ETH_SS_STATS:
1647 return ARRAY_SIZE(mtk_ethtool_stats);
1648 default:
1649 return -EOPNOTSUPP;
1650 }
1651}
1652
1653static void mtk_get_ethtool_stats(struct net_device *dev,
1654 struct ethtool_stats *stats, u64 *data)
1655{
1656 struct mtk_mac *mac = netdev_priv(dev);
1657 struct mtk_hw_stats *hwstats = mac->hw_stats;
1658 u64 *data_src, *data_dst;
1659 unsigned int start;
1660 int i;
1661
1662 if (netif_running(dev) && netif_device_present(dev)) {
1663 if (spin_trylock(&hwstats->stats_lock)) {
1664 mtk_stats_update_mac(mac);
1665 spin_unlock(&hwstats->stats_lock);
1666 }
1667 }
1668
1669 do {
1670 data_src = (u64*)hwstats;
1671 data_dst = data;
1672 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1673
1674 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1675 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1676 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1677}
1678
1679static struct ethtool_ops mtk_ethtool_ops = {
1680 .get_settings = mtk_get_settings,
1681 .set_settings = mtk_set_settings,
1682 .get_drvinfo = mtk_get_drvinfo,
1683 .get_msglevel = mtk_get_msglevel,
1684 .set_msglevel = mtk_set_msglevel,
1685 .nway_reset = mtk_nway_reset,
1686 .get_link = mtk_get_link,
1687 .get_strings = mtk_get_strings,
1688 .get_sset_count = mtk_get_sset_count,
1689 .get_ethtool_stats = mtk_get_ethtool_stats,
1690};
1691
1692static const struct net_device_ops mtk_netdev_ops = {
1693 .ndo_init = mtk_init,
1694 .ndo_uninit = mtk_uninit,
1695 .ndo_open = mtk_open,
1696 .ndo_stop = mtk_stop,
1697 .ndo_start_xmit = mtk_start_xmit,
1698 .ndo_set_mac_address = mtk_set_mac_address,
1699 .ndo_validate_addr = eth_validate_addr,
1700 .ndo_do_ioctl = mtk_do_ioctl,
1701 .ndo_change_mtu = eth_change_mtu,
1702 .ndo_tx_timeout = mtk_tx_timeout,
1703 .ndo_get_stats64 = mtk_get_stats64,
1704#ifdef CONFIG_NET_POLL_CONTROLLER
1705 .ndo_poll_controller = mtk_poll_controller,
1706#endif
1707};
1708
1709static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1710{
1711 struct mtk_mac *mac;
1712 const __be32 *_id = of_get_property(np, "reg", NULL);
1713 int id, err;
1714
1715 if (!_id) {
1716 dev_err(eth->dev, "missing mac id\n");
1717 return -EINVAL;
1718 }
1719
1720 id = be32_to_cpup(_id);
1721 if (id >= MTK_MAC_COUNT) {
1722 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1723 return -EINVAL;
1724 }
1725
1726 if (eth->netdev[id]) {
1727 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1728 return -EINVAL;
1729 }
1730
1731 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1732 if (!eth->netdev[id]) {
1733 dev_err(eth->dev, "alloc_etherdev failed\n");
1734 return -ENOMEM;
1735 }
1736 mac = netdev_priv(eth->netdev[id]);
1737 eth->mac[id] = mac;
1738 mac->id = id;
1739 mac->hw = eth;
1740 mac->of_node = np;
656e7052
JC		 1741
1742 mac->hw_stats = devm_kzalloc(eth->dev,
1743 sizeof(*mac->hw_stats),
1744 GFP_KERNEL);
1745 if (!mac->hw_stats) {
1746 dev_err(eth->dev, "failed to allocate counter memory\n");
1747 err = -ENOMEM;
1748 goto free_netdev;
1749 }
1750 spin_lock_init(&mac->hw_stats->stats_lock);
1751 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1752
1753 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 1754 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 1755 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1756 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1757 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1758 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1759 eth->netdev[id]->features |= MTK_HW_FEATURES;
1760 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1761
1762 err = register_netdev(eth->netdev[id]);
1763 if (err) {
1764 dev_err(eth->dev, "error bringing up device\n");
1765 goto free_netdev;
1766 }
80673029 1767 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 1768 netif_info(eth, probe, eth->netdev[id],
1769 "mediatek frame engine at 0x%08lx, irq %d\n",
80673029 1770 eth->netdev[id]->base_addr, eth->irq[0]);
656e7052
JC		 1771
1772 return 0;
1773
1774free_netdev:
1775 free_netdev(eth->netdev[id]);
1776 return err;
1777}
1778
1779static int mtk_probe(struct platform_device *pdev)
1780{
1781 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1782 struct device_node *mac_np;
1783 const struct of_device_id *match;
1784 struct mtk_soc_data *soc;
1785 struct mtk_eth *eth;
1786 int err;
80673029 1787 int i;
656e7052 1788
656e7052
JC		 1789 match = of_match_device(of_mtk_match, &pdev->dev);
1790 soc = (struct mtk_soc_data *)match->data;
1791
1792 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1793 if (!eth)
1794 return -ENOMEM;
1795
1796 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1797 if (IS_ERR(eth->base))
1798 return PTR_ERR(eth->base);
656e7052
JC		 1799
1800 spin_lock_init(&eth->page_lock);
7bc9ccec 1801 spin_lock_init(&eth->irq_lock);
656e7052
JC		 1802
1803 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1804 "mediatek,ethsys");
1805 if (IS_ERR(eth->ethsys)) {
1806 dev_err(&pdev->dev, "no ethsys regmap found\n");
1807 return PTR_ERR(eth->ethsys);
1808 }
1809
1810 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1811 "mediatek,pctl");
1812 if (IS_ERR(eth->pctl)) {
1813 dev_err(&pdev->dev, "no pctl regmap found\n");
1814 return PTR_ERR(eth->pctl);
1815 }
1816
1817 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1818 if (IS_ERR(eth->rstc)) {
1819 dev_err(&pdev->dev, "no eth reset found\n");
1820 return PTR_ERR(eth->rstc);
1821 }
1822
80673029
JC		 1823 for (i = 0; i < 3; i++) {
1824 eth->irq[i] = platform_get_irq(pdev, i);
1825 if (eth->irq[i] < 0) {
1826 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1827 return -ENXIO;
1828 }
656e7052
JC		 1829 }
1830
1831 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1832 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1833 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1834 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1835 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1836 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1837 return -ENODEV;
1838
1839 clk_prepare_enable(eth->clk_ethif);
1840 clk_prepare_enable(eth->clk_esw);
1841 clk_prepare_enable(eth->clk_gp1);
1842 clk_prepare_enable(eth->clk_gp2);
1843
1844 eth->dev = &pdev->dev;
1845 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 1846 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 1847
1848 err = mtk_hw_init(eth);
1849 if (err)
1850 return err;
1851
1852 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1853 if (!of_device_is_compatible(mac_np,
1854 "mediatek,eth-mac"))
1855 continue;
1856
1857 if (!of_device_is_available(mac_np))
1858 continue;
1859
1860 err = mtk_add_mac(eth, mac_np);
1861 if (err)
1862 goto err_free_dev;
1863 }
1864
1865 /* we run 2 devices on the same DMA ring so we need a dummy device
1866 * for NAPI to work
1867 */
1868 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 1869 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1870 MTK_NAPI_WEIGHT);
1871 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 1872 MTK_NAPI_WEIGHT);
1873
1874 platform_set_drvdata(pdev, eth);
1875
1876 return 0;
1877
1878err_free_dev:
1879 mtk_cleanup(eth);
1880 return err;
1881}
1882
1883static int mtk_remove(struct platform_device *pdev)
1884{
1885 struct mtk_eth *eth = platform_get_drvdata(pdev);
1886
1887 clk_disable_unprepare(eth->clk_ethif);
1888 clk_disable_unprepare(eth->clk_esw);
1889 clk_disable_unprepare(eth->clk_gp1);
1890 clk_disable_unprepare(eth->clk_gp2);
1891
80673029 1892 netif_napi_del(&eth->tx_napi);
656e7052
JC		 1893 netif_napi_del(&eth->rx_napi);
1894 mtk_cleanup(eth);
656e7052
JC		 1895
1896 return 0;
1897}
1898
1899const struct of_device_id of_mtk_match[] = {
1900 { .compatible = "mediatek,mt7623-eth" },
1901 {},
1902};
1903
1904static struct platform_driver mtk_driver = {
1905 .probe = mtk_probe,
1906 .remove = mtk_remove,
1907 .driver = {
1908 .name = "mtk_soc_eth",
656e7052
JC		 1909 .of_match_table = of_mtk_match,
1910 },
1911};
1912
1913module_platform_driver(mtk_driver);
1914
1915MODULE_LICENSE("GPL");
1916MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1917MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
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