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Merge branch 'mediatek-trgmii'
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
26a2ad8a 21#include <linux/pm_runtime.h>
656e7052
JC		 22#include <linux/if_vlan.h>
23#include <linux/reset.h>
24#include <linux/tcp.h>
25
26#include "mtk_eth_soc.h"
27
28static int mtk_msg_level = -1;
29module_param_named(msg_level, mtk_msg_level, int, 0);
30MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32#define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
34
35/* strings used by ethtool */
36static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
38 u32 offset;
39} mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
52};
53
549e5495 54static const char * const mtk_clks_source_name[] = {
f430dea7 55 "ethif", "esw", "gp1", "gp2", "trgpll"
549e5495
SW		 56};
57
656e7052
JC		 58void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59{
60 __raw_writel(val, eth->base + reg);
61}
62
63u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64{
65 return __raw_readl(eth->base + reg);
66}
67
68static int mtk_mdio_busy_wait(struct mtk_eth *eth)
69{
70 unsigned long t_start = jiffies;
71
72 while (1) {
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
74 return 0;
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
76 break;
77 usleep_range(10, 20);
78 }
79
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
81 return -1;
82}
83
379672de
WY		 84static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
656e7052
JC		 86{
87 if (mtk_mdio_busy_wait(eth))
88 return -1;
89
90 write_data &= 0xffff;
91
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
95 MTK_PHY_IAC);
96
97 if (mtk_mdio_busy_wait(eth))
98 return -1;
99
100 return 0;
101}
102
379672de 103static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 104{
105 u32 d;
106
107 if (mtk_mdio_busy_wait(eth))
108 return 0xffff;
109
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
113 MTK_PHY_IAC);
114
115 if (mtk_mdio_busy_wait(eth))
116 return 0xffff;
117
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
119
120 return d;
121}
122
123static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
125{
126 struct mtk_eth *eth = bus->priv;
127
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
129}
130
131static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
132{
133 struct mtk_eth *eth = bus->priv;
134
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
136}
137
f430dea7
SW		 138static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
139{
140 u32 val;
141 int ret;
142
143 val = (speed == SPEED_1000) ?
144 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
145 mtk_w32(eth, val, INTF_MODE);
146
147 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
148 ETHSYS_TRGMII_CLK_SEL362_5,
149 ETHSYS_TRGMII_CLK_SEL362_5);
150
151 val = (speed == SPEED_1000) ? 250000000 : 500000000;
152 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
153 if (ret)
154 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
155
156 val = (speed == SPEED_1000) ?
157 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
158 mtk_w32(eth, val, TRGMII_RCK_CTRL);
159
160 val = (speed == SPEED_1000) ?
161 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
162 mtk_w32(eth, val, TRGMII_TCK_CTRL);
163}
164
656e7052
JC		 165static void mtk_phy_link_adjust(struct net_device *dev)
166{
167 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 168 u16 lcl_adv = 0, rmt_adv = 0;
169 u8 flowctrl;
656e7052
JC		 170 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
171 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
172 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
173 MAC_MCR_BACKPR_EN;
174
dce6fa42
SW		 175 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
176 return;
177
656e7052
JC		 178 switch (mac->phy_dev->speed) {
179 case SPEED_1000:
180 mcr |= MAC_MCR_SPEED_1000;
181 break;
182 case SPEED_100:
183 mcr |= MAC_MCR_SPEED_100;
184 break;
185 };
186
f430dea7
SW		 187 if (mac->id == 0 && !mac->trgmii)
188 mtk_gmac0_rgmii_adjust(mac->hw, mac->phy_dev->speed);
189
656e7052
JC		 190 if (mac->phy_dev->link)
191 mcr |= MAC_MCR_FORCE_LINK;
192
08ef55c6 193 if (mac->phy_dev->duplex) {
656e7052
JC		 194 mcr |= MAC_MCR_FORCE_DPX;
195
08ef55c6
JC		 196 if (mac->phy_dev->pause)
197 rmt_adv = LPA_PAUSE_CAP;
198 if (mac->phy_dev->asym_pause)
199 rmt_adv |= LPA_PAUSE_ASYM;
200
201 if (mac->phy_dev->advertising & ADVERTISED_Pause)
202 lcl_adv |= ADVERTISE_PAUSE_CAP;
203 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
204 lcl_adv |= ADVERTISE_PAUSE_ASYM;
205
206 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
207
208 if (flowctrl & FLOW_CTRL_TX)
209 mcr |= MAC_MCR_FORCE_TX_FC;
210 if (flowctrl & FLOW_CTRL_RX)
211 mcr |= MAC_MCR_FORCE_RX_FC;
212
213 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
214 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
215 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
216 }
656e7052
JC		 217
218 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
219
220 if (mac->phy_dev->link)
221 netif_carrier_on(dev);
222 else
223 netif_carrier_off(dev);
224}
225
226static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
227 struct device_node *phy_node)
228{
229 const __be32 *_addr = NULL;
230 struct phy_device *phydev;
231 int phy_mode, addr;
232
233 _addr = of_get_property(phy_node, "reg", NULL);
234
235 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
236 pr_err("%s: invalid phy address\n", phy_node->name);
237 return -EINVAL;
238 }
239 addr = be32_to_cpu(*_addr);
240 phy_mode = of_get_phy_mode(phy_node);
241 if (phy_mode < 0) {
242 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
243 return -EINVAL;
244 }
245
246 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
247 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 248 if (!phydev) {
656e7052 249 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 250 return -ENODEV;
656e7052
JC		 251 }
252
253 dev_info(eth->dev,
254 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
255 mac->id, phydev_name(phydev), phydev->phy_id,
256 phydev->drv->name);
257
258 mac->phy_dev = phydev;
259
260 return 0;
261}
262
263static int mtk_phy_connect(struct mtk_mac *mac)
264{
265 struct mtk_eth *eth = mac->hw;
266 struct device_node *np;
9ea4d311 267 u32 val;
656e7052
JC		 268
269 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 270 if (!np && of_phy_is_fixed_link(mac->of_node))
271 if (!of_phy_register_fixed_link(mac->of_node))
272 np = of_node_get(mac->of_node);
656e7052
JC		 273 if (!np)
274 return -ENODEV;
275
276 switch (of_get_phy_mode(np)) {
572de608
SW		 277 case PHY_INTERFACE_MODE_TRGMII:
278 mac->trgmii = true;
37920fce
JC		 279 case PHY_INTERFACE_MODE_RGMII_TXID:
280 case PHY_INTERFACE_MODE_RGMII_RXID:
281 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052 282 case PHY_INTERFACE_MODE_RGMII:
9ea4d311 283 mac->ge_mode = 0;
656e7052
JC		 284 break;
285 case PHY_INTERFACE_MODE_MII:
9ea4d311 286 mac->ge_mode = 1;
656e7052 287 break;
8ca7f4fe 288 case PHY_INTERFACE_MODE_REVMII:
9ea4d311 289 mac->ge_mode = 2;
656e7052 290 break;
8ca7f4fe 291 case PHY_INTERFACE_MODE_RMII:
292 if (!mac->id)
293 goto err_phy;
9ea4d311 294 mac->ge_mode = 3;
8ca7f4fe 295 break;
656e7052 296 default:
8ca7f4fe 297 goto err_phy;
656e7052
JC		 298 }
299
300 /* put the gmac into the right mode */
301 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
302 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
9ea4d311 303 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
656e7052
JC		 304 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
305
306 mtk_phy_connect_node(eth, mac, np);
307 mac->phy_dev->autoneg = AUTONEG_ENABLE;
308 mac->phy_dev->speed = 0;
309 mac->phy_dev->duplex = 0;
b2025c7c 310
311 if (of_phy_is_fixed_link(mac->of_node))
312 mac->phy_dev->supported |=
313 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
314
08ef55c6
JC		 315 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
316 SUPPORTED_Asym_Pause;
656e7052
JC		 317 mac->phy_dev->advertising = mac->phy_dev->supported |
318 ADVERTISED_Autoneg;
319 phy_start_aneg(mac->phy_dev);
320
e8c2993a 321 of_node_put(np);
322
656e7052 323 return 0;
8ca7f4fe 324
325err_phy:
326 of_node_put(np);
327 dev_err(eth->dev, "invalid phy_mode\n");
328 return -EINVAL;
656e7052
JC		 329}
330
331static int mtk_mdio_init(struct mtk_eth *eth)
332{
333 struct device_node *mii_np;
1e515b7f 334 int ret;
656e7052
JC		 335
336 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
337 if (!mii_np) {
338 dev_err(eth->dev, "no %s child node found", "mdio-bus");
339 return -ENODEV;
340 }
341
342 if (!of_device_is_available(mii_np)) {
aa6e8a54 343 ret = -ENODEV;
656e7052
JC		 344 goto err_put_node;
345 }
346
1e515b7f 347 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
656e7052 348 if (!eth->mii_bus) {
1e515b7f 349 ret = -ENOMEM;
656e7052
JC		 350 goto err_put_node;
351 }
352
353 eth->mii_bus->name = "mdio";
354 eth->mii_bus->read = mtk_mdio_read;
355 eth->mii_bus->write = mtk_mdio_write;
356 eth->mii_bus->priv = eth;
357 eth->mii_bus->parent = eth->dev;
358
359 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
1e515b7f 360 ret = of_mdiobus_register(eth->mii_bus, mii_np);
656e7052
JC		 361
362err_put_node:
363 of_node_put(mii_np);
1e515b7f 364 return ret;
656e7052
JC		 365}
366
367static void mtk_mdio_cleanup(struct mtk_eth *eth)
368{
369 if (!eth->mii_bus)
370 return;
371
372 mdiobus_unregister(eth->mii_bus);
656e7052
JC		 373}
374
bacfd110
NC		 375static inline void mtk_irq_disable(struct mtk_eth *eth,
376 unsigned reg, u32 mask)
656e7052 377{
7bc9ccec 378 unsigned long flags;
656e7052
JC		 379 u32 val;
380
7bc9ccec 381 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 382 val = mtk_r32(eth, reg);
383 mtk_w32(eth, val & ~mask, reg);
7bc9ccec 384 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 385}
386
bacfd110
NC		 387static inline void mtk_irq_enable(struct mtk_eth *eth,
388 unsigned reg, u32 mask)
656e7052 389{
7bc9ccec 390 unsigned long flags;
656e7052
JC		 391 u32 val;
392
7bc9ccec 393 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 394 val = mtk_r32(eth, reg);
395 mtk_w32(eth, val | mask, reg);
7bc9ccec 396 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 397}
398
399static int mtk_set_mac_address(struct net_device *dev, void *p)
400{
401 int ret = eth_mac_addr(dev, p);
402 struct mtk_mac *mac = netdev_priv(dev);
403 const char *macaddr = dev->dev_addr;
656e7052
JC		 404
405 if (ret)
406 return ret;
407
dce6fa42
SW		 408 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
409 return -EBUSY;
410
e3e9652a 411 spin_lock_bh(&mac->hw->page_lock);
656e7052
JC		 412 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
413 MTK_GDMA_MAC_ADRH(mac->id));
414 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
415 (macaddr[4] << 8) | macaddr[5],
416 MTK_GDMA_MAC_ADRL(mac->id));
e3e9652a 417 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 418
419 return 0;
420}
421
422void mtk_stats_update_mac(struct mtk_mac *mac)
423{
424 struct mtk_hw_stats *hw_stats = mac->hw_stats;
425 unsigned int base = MTK_GDM1_TX_GBCNT;
426 u64 stats;
427
428 base += hw_stats->reg_offset;
429
430 u64_stats_update_begin(&hw_stats->syncp);
431
432 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
433 stats = mtk_r32(mac->hw, base + 0x04);
434 if (stats)
435 hw_stats->rx_bytes += (stats << 32);
436 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
437 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
438 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
439 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
440 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
441 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
442 hw_stats->rx_flow_control_packets +=
443 mtk_r32(mac->hw, base + 0x24);
444 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
445 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
446 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
447 stats = mtk_r32(mac->hw, base + 0x34);
448 if (stats)
449 hw_stats->tx_bytes += (stats << 32);
450 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
451 u64_stats_update_end(&hw_stats->syncp);
452}
453
454static void mtk_stats_update(struct mtk_eth *eth)
455{
456 int i;
457
458 for (i = 0; i < MTK_MAC_COUNT; i++) {
459 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
460 continue;
461 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
462 mtk_stats_update_mac(eth->mac[i]);
463 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
464 }
465 }
466}
467
468static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
469 struct rtnl_link_stats64 *storage)
470{
471 struct mtk_mac *mac = netdev_priv(dev);
472 struct mtk_hw_stats *hw_stats = mac->hw_stats;
473 unsigned int start;
474
475 if (netif_running(dev) && netif_device_present(dev)) {
476 if (spin_trylock(&hw_stats->stats_lock)) {
477 mtk_stats_update_mac(mac);
478 spin_unlock(&hw_stats->stats_lock);
479 }
480 }
481
482 do {
483 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
484 storage->rx_packets = hw_stats->rx_packets;
485 storage->tx_packets = hw_stats->tx_packets;
486 storage->rx_bytes = hw_stats->rx_bytes;
487 storage->tx_bytes = hw_stats->tx_bytes;
488 storage->collisions = hw_stats->tx_collisions;
489 storage->rx_length_errors = hw_stats->rx_short_errors +
490 hw_stats->rx_long_errors;
491 storage->rx_over_errors = hw_stats->rx_overflow;
492 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
493 storage->rx_errors = hw_stats->rx_checksum_errors;
494 storage->tx_aborted_errors = hw_stats->tx_skip;
495 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
496
497 storage->tx_errors = dev->stats.tx_errors;
498 storage->rx_dropped = dev->stats.rx_dropped;
499 storage->tx_dropped = dev->stats.tx_dropped;
500
501 return storage;
502}
503
504static inline int mtk_max_frag_size(int mtu)
505{
506 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
507 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
508 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
509
510 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
511 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
512}
513
514static inline int mtk_max_buf_size(int frag_size)
515{
516 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
517 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
518
519 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
520
521 return buf_size;
522}
523
524static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
525 struct mtk_rx_dma *dma_rxd)
526{
527 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
528 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
529 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
530 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
531}
532
533/* the qdma core needs scratch memory to be setup */
534static int mtk_init_fq_dma(struct mtk_eth *eth)
535{
605e4fe4 536 dma_addr_t phy_ring_tail;
656e7052
JC		 537 int cnt = MTK_DMA_SIZE;
538 dma_addr_t dma_addr;
539 int i;
540
541 eth->scratch_ring = dma_alloc_coherent(eth->dev,
542 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 543 &eth->phy_scratch_ring,
656e7052
JC		 544 GFP_ATOMIC | __GFP_ZERO);
545 if (unlikely(!eth->scratch_ring))
546 return -ENOMEM;
547
548 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
549 GFP_KERNEL);
562c5a70
JC		 550 if (unlikely(!eth->scratch_head))
551 return -ENOMEM;
552
656e7052
JC		 553 dma_addr = dma_map_single(eth->dev,
554 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
555 DMA_FROM_DEVICE);
556 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
557 return -ENOMEM;
558
559 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 560 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 561 (sizeof(struct mtk_tx_dma) * (cnt - 1));
562
563 for (i = 0; i < cnt; i++) {
564 eth->scratch_ring[i].txd1 =
565 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
566 if (i < cnt - 1)
605e4fe4 567 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 568 ((i + 1) * sizeof(struct mtk_tx_dma)));
569 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
570 }
571
605e4fe4 572 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 573 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
574 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
575 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
576
577 return 0;
578}
579
580static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
581{
582 void *ret = ring->dma;
583
584 return ret + (desc - ring->phys);
585}
586
587static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
588 struct mtk_tx_dma *txd)
589{
590 int idx = txd - ring->dma;
591
592 return &ring->buf[idx];
593}
594
55a4e778 595static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 596{
597 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 598 dma_unmap_single(eth->dev,
656e7052
JC		 599 dma_unmap_addr(tx_buf, dma_addr0),
600 dma_unmap_len(tx_buf, dma_len0),
601 DMA_TO_DEVICE);
602 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 603 dma_unmap_page(eth->dev,
656e7052
JC		 604 dma_unmap_addr(tx_buf, dma_addr0),
605 dma_unmap_len(tx_buf, dma_len0),
606 DMA_TO_DEVICE);
607 }
608 tx_buf->flags = 0;
609 if (tx_buf->skb &&
610 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
611 dev_kfree_skb_any(tx_buf->skb);
612 tx_buf->skb = NULL;
613}
614
615static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
616 int tx_num, struct mtk_tx_ring *ring, bool gso)
617{
618 struct mtk_mac *mac = netdev_priv(dev);
619 struct mtk_eth *eth = mac->hw;
620 struct mtk_tx_dma *itxd, *txd;
621 struct mtk_tx_buf *tx_buf;
656e7052
JC		 622 dma_addr_t mapped_addr;
623 unsigned int nr_frags;
624 int i, n_desc = 1;
c6f1dc4d 625 u32 txd4 = 0, fport;
656e7052
JC		 626
627 itxd = ring->next_free;
628 if (itxd == ring->last_free)
629 return -ENOMEM;
630
631 /* set the forward port */
c6f1dc4d
SW		 632 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
633 txd4 |= fport;
656e7052
JC		 634
635 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
636 memset(tx_buf, 0, sizeof(*tx_buf));
637
638 if (gso)
639 txd4 |= TX_DMA_TSO;
640
641 /* TX Checksum offload */
642 if (skb->ip_summed == CHECKSUM_PARTIAL)
643 txd4 |= TX_DMA_CHKSUM;
644
645 /* VLAN header offload */
646 if (skb_vlan_tag_present(skb))
647 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
648
55a4e778 649 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 650 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 651 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 652 return -ENOMEM;
653
656e7052
JC		 654 WRITE_ONCE(itxd->txd1, mapped_addr);
655 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
656 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
657 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
658
659 /* TX SG offload */
660 txd = itxd;
661 nr_frags = skb_shinfo(skb)->nr_frags;
662 for (i = 0; i < nr_frags; i++) {
663 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
664 unsigned int offset = 0;
665 int frag_size = skb_frag_size(frag);
666
667 while (frag_size) {
668 bool last_frag = false;
669 unsigned int frag_map_size;
670
671 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
672 if (txd == ring->last_free)
673 goto err_dma;
674
675 n_desc++;
676 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 677 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 678 frag_map_size,
679 DMA_TO_DEVICE);
55a4e778 680 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 681 goto err_dma;
682
683 if (i == nr_frags - 1 &&
684 (frag_size - frag_map_size) == 0)
685 last_frag = true;
686
687 WRITE_ONCE(txd->txd1, mapped_addr);
688 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
689 TX_DMA_PLEN0(frag_map_size) |
369f0453 690 last_frag * TX_DMA_LS0));
c6f1dc4d 691 WRITE_ONCE(txd->txd4, fport);
656e7052
JC		 692
693 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
694 tx_buf = mtk_desc_to_tx_buf(ring, txd);
695 memset(tx_buf, 0, sizeof(*tx_buf));
696
697 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
698 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
699 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
700 frag_size -= frag_map_size;
701 offset += frag_map_size;
702 }
703 }
704
705 /* store skb to cleanup */
706 tx_buf->skb = skb;
707
708 WRITE_ONCE(itxd->txd4, txd4);
709 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
710 (!nr_frags * TX_DMA_LS0)));
711
656e7052
JC		 712 netdev_sent_queue(dev, skb->len);
713 skb_tx_timestamp(skb);
714
715 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
716 atomic_sub(n_desc, &ring->free_count);
717
718 /* make sure that all changes to the dma ring are flushed before we
719 * continue
720 */
721 wmb();
722
723 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
724 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
725
726 return 0;
727
728err_dma:
729 do {
2fae723c 730 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 731
732 /* unmap dma */
55a4e778 733 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 734
735 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
736 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
737 } while (itxd != txd);
738
739 return -ENOMEM;
740}
741
742static inline int mtk_cal_txd_req(struct sk_buff *skb)
743{
744 int i, nfrags;
745 struct skb_frag_struct *frag;
746
747 nfrags = 1;
748 if (skb_is_gso(skb)) {
749 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
750 frag = &skb_shinfo(skb)->frags[i];
751 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
752 }
753 } else {
754 nfrags += skb_shinfo(skb)->nr_frags;
755 }
756
beeb4ca4 757 return nfrags;
656e7052
JC		 758}
759
ad3cba98
JC		 760static int mtk_queue_stopped(struct mtk_eth *eth)
761{
762 int i;
763
764 for (i = 0; i < MTK_MAC_COUNT; i++) {
765 if (!eth->netdev[i])
766 continue;
767 if (netif_queue_stopped(eth->netdev[i]))
768 return 1;
769 }
770
771 return 0;
772}
773
13c822f6
JC		 774static void mtk_wake_queue(struct mtk_eth *eth)
775{
776 int i;
777
778 for (i = 0; i < MTK_MAC_COUNT; i++) {
779 if (!eth->netdev[i])
780 continue;
781 netif_wake_queue(eth->netdev[i]);
782 }
783}
784
785static void mtk_stop_queue(struct mtk_eth *eth)
786{
787 int i;
788
789 for (i = 0; i < MTK_MAC_COUNT; i++) {
790 if (!eth->netdev[i])
791 continue;
792 netif_stop_queue(eth->netdev[i]);
793 }
794}
795
656e7052
JC		 796static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
797{
798 struct mtk_mac *mac = netdev_priv(dev);
799 struct mtk_eth *eth = mac->hw;
800 struct mtk_tx_ring *ring = &eth->tx_ring;
801 struct net_device_stats *stats = &dev->stats;
802 bool gso = false;
803 int tx_num;
804
34c2e4c9
JC		 805 /* normally we can rely on the stack not calling this more than once,
806 * however we have 2 queues running on the same ring so we need to lock
807 * the ring access
808 */
e3e9652a 809 spin_lock(&eth->page_lock);
34c2e4c9 810
dce6fa42
SW		 811 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
812 goto drop;
813
656e7052
JC		 814 tx_num = mtk_cal_txd_req(skb);
815 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 816 mtk_stop_queue(eth);
656e7052
JC		 817 netif_err(eth, tx_queued, dev,
818 "Tx Ring full when queue awake!\n");
e3e9652a 819 spin_unlock(&eth->page_lock);
656e7052
JC		 820 return NETDEV_TX_BUSY;
821 }
822
823 /* TSO: fill MSS info in tcp checksum field */
824 if (skb_is_gso(skb)) {
825 if (skb_cow_head(skb, 0)) {
826 netif_warn(eth, tx_err, dev,
827 "GSO expand head fail.\n");
828 goto drop;
829 }
830
831 if (skb_shinfo(skb)->gso_type &
832 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
833 gso = true;
834 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
835 }
836 }
837
838 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
839 goto drop;
840
82c6544d 841 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 842 mtk_stop_queue(eth);
82c6544d 843
e3e9652a 844 spin_unlock(&eth->page_lock);
656e7052
JC		 845
846 return NETDEV_TX_OK;
847
848drop:
e3e9652a 849 spin_unlock(&eth->page_lock);
656e7052
JC		 850 stats->tx_dropped++;
851 dev_kfree_skb(skb);
852 return NETDEV_TX_OK;
853}
854
ee406810
NC		 855static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
856{
857 int i;
858 struct mtk_rx_ring *ring;
859 int idx;
860
861 if (!eth->hwlro)
862 return &eth->rx_ring[0];
863
864 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
865 ring = &eth->rx_ring[i];
866 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
867 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
868 ring->calc_idx_update = true;
869 return ring;
870 }
871 }
872
873 return NULL;
874}
875
876static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
877{
878 struct mtk_rx_ring *ring;
879 int i;
880
881 if (!eth->hwlro) {
882 ring = &eth->rx_ring[0];
883 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
884 } else {
885 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
886 ring = &eth->rx_ring[i];
887 if (ring->calc_idx_update) {
888 ring->calc_idx_update = false;
889 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
890 }
891 }
892 }
893}
894
656e7052 895static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 896 struct mtk_eth *eth)
656e7052 897{
ee406810
NC		 898 struct mtk_rx_ring *ring;
899 int idx;
656e7052
JC		 900 struct sk_buff *skb;
901 u8 *data, *new_data;
902 struct mtk_rx_dma *rxd, trxd;
903 int done = 0;
904
905 while (done < budget) {
906 struct net_device *netdev;
907 unsigned int pktlen;
908 dma_addr_t dma_addr;
909 int mac = 0;
910
ee406810
NC		 911 ring = mtk_get_rx_ring(eth);
912 if (unlikely(!ring))
913 goto rx_done;
914
915 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
656e7052
JC		 916 rxd = &ring->dma[idx];
917 data = ring->data[idx];
918
919 mtk_rx_get_desc(&trxd, rxd);
920 if (!(trxd.rxd2 & RX_DMA_DONE))
921 break;
922
923 /* find out which mac the packet come from. values start at 1 */
924 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
925 RX_DMA_FPORT_MASK;
926 mac--;
927
928 netdev = eth->netdev[mac];
929
dce6fa42
SW		 930 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
931 goto release_desc;
932
656e7052
JC		 933 /* alloc new buffer */
934 new_data = napi_alloc_frag(ring->frag_size);
935 if (unlikely(!new_data)) {
936 netdev->stats.rx_dropped++;
937 goto release_desc;
938 }
55a4e778 939 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 940 new_data + NET_SKB_PAD,
941 ring->buf_size,
942 DMA_FROM_DEVICE);
55a4e778 943 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 944 skb_free_frag(new_data);
94321a9f 945 netdev->stats.rx_dropped++;
656e7052
JC		 946 goto release_desc;
947 }
948
949 /* receive data */
950 skb = build_skb(data, ring->frag_size);
951 if (unlikely(!skb)) {
1b430799 952 skb_free_frag(new_data);
94321a9f 953 netdev->stats.rx_dropped++;
656e7052
JC		 954 goto release_desc;
955 }
956 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
957
55a4e778 958 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 959 ring->buf_size, DMA_FROM_DEVICE);
960 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
961 skb->dev = netdev;
962 skb_put(skb, pktlen);
963 if (trxd.rxd4 & RX_DMA_L4_VALID)
964 skb->ip_summed = CHECKSUM_UNNECESSARY;
965 else
966 skb_checksum_none_assert(skb);
967 skb->protocol = eth_type_trans(skb, netdev);
968
969 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
970 RX_DMA_VID(trxd.rxd3))
971 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
972 RX_DMA_VID(trxd.rxd3));
973 napi_gro_receive(napi, skb);
974
975 ring->data[idx] = new_data;
976 rxd->rxd1 = (unsigned int)dma_addr;
977
978release_desc:
979 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
980
981 ring->calc_idx = idx;
635372ad 982
656e7052
JC		 983 done++;
984 }
985
ee406810 986rx_done:
41156cea
SW		 987 if (done) {
988 /* make sure that all changes to the dma ring are flushed before
989 * we continue
990 */
991 wmb();
ee406810 992 mtk_update_rx_cpu_idx(eth);
41156cea 993 }
656e7052
JC		 994
995 return done;
996}
997
80673029 998static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 999{
1000 struct mtk_tx_ring *ring = &eth->tx_ring;
1001 struct mtk_tx_dma *desc;
1002 struct sk_buff *skb;
1003 struct mtk_tx_buf *tx_buf;
80673029 1004 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 1005 unsigned int bytes[MTK_MAX_DEVS];
1006 u32 cpu, dma;
1007 static int condition;
80673029 1008 int total = 0, i;
656e7052
JC		 1009
1010 memset(done, 0, sizeof(done));
1011 memset(bytes, 0, sizeof(bytes));
1012
1013 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1014 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1015
1016 desc = mtk_qdma_phys_to_virt(ring, cpu);
1017
1018 while ((cpu != dma) && budget) {
1019 u32 next_cpu = desc->txd2;
1020 int mac;
1021
1022 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1023 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1024 break;
1025
1026 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
1027 TX_DMA_FPORT_MASK;
1028 mac--;
1029
1030 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1031 skb = tx_buf->skb;
1032 if (!skb) {
1033 condition = 1;
1034 break;
1035 }
1036
1037 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1038 bytes[mac] += skb->len;
1039 done[mac]++;
1040 budget--;
1041 }
55a4e778 1042 mtk_tx_unmap(eth, tx_buf);
656e7052 1043
656e7052
JC		 1044 ring->last_free = desc;
1045 atomic_inc(&ring->free_count);
1046
1047 cpu = next_cpu;
1048 }
1049
1050 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1051
1052 for (i = 0; i < MTK_MAC_COUNT; i++) {
1053 if (!eth->netdev[i] || !done[i])
1054 continue;
1055 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1056 total += done[i];
1057 }
1058
ad3cba98
JC		 1059 if (mtk_queue_stopped(eth) &&
1060 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 1061 mtk_wake_queue(eth);
656e7052
JC		 1062
1063 return total;
1064}
1065
80673029 1066static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 1067{
80673029 1068 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 1069
eece71e8 1070 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 1071 mtk_stats_update(eth);
eece71e8
JC		 1072 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1073 MTK_INT_STATUS2);
656e7052 1074 }
80673029
JC		 1075}
1076
1077static int mtk_napi_tx(struct napi_struct *napi, int budget)
1078{
1079 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1080 u32 status, mask;
1081 int tx_done = 0;
1082
1083 mtk_handle_status_irq(eth);
1084 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1085 tx_done = mtk_poll_tx(eth, budget);
1086
1087 if (unlikely(netif_msg_intr(eth))) {
1088 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1089 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1090 dev_info(eth->dev,
1091 "done tx %d, intr 0x%08x/0x%x\n",
1092 tx_done, status, mask);
1093 }
1094
1095 if (tx_done == budget)
1096 return budget;
1097
1098 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1099 if (status & MTK_TX_DONE_INT)
1100 return budget;
1101
1102 napi_complete(napi);
bacfd110 1103 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
80673029
JC		 1104
1105 return tx_done;
1106}
1107
1108static int mtk_napi_rx(struct napi_struct *napi, int budget)
1109{
1110 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1111 u32 status, mask;
1112 int rx_done = 0;
41156cea 1113 int remain_budget = budget;
80673029
JC		 1114
1115 mtk_handle_status_irq(eth);
41156cea
SW		 1116
1117poll_again:
bacfd110 1118 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
41156cea 1119 rx_done = mtk_poll_rx(napi, remain_budget, eth);
656e7052
JC		 1120
1121 if (unlikely(netif_msg_intr(eth))) {
bacfd110
NC		 1122 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1123 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
80673029
JC		 1124 dev_info(eth->dev,
1125 "done rx %d, intr 0x%08x/0x%x\n",
1126 rx_done, status, mask);
656e7052 1127 }
41156cea 1128 if (rx_done == remain_budget)
656e7052
JC		 1129 return budget;
1130
bacfd110 1131 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
41156cea
SW		 1132 if (status & MTK_RX_DONE_INT) {
1133 remain_budget -= rx_done;
1134 goto poll_again;
1135 }
656e7052 1136 napi_complete(napi);
bacfd110 1137 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052 1138
41156cea 1139 return rx_done + budget - remain_budget;
656e7052
JC		 1140}
1141
1142static int mtk_tx_alloc(struct mtk_eth *eth)
1143{
1144 struct mtk_tx_ring *ring = &eth->tx_ring;
1145 int i, sz = sizeof(*ring->dma);
1146
1147 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1148 GFP_KERNEL);
1149 if (!ring->buf)
1150 goto no_tx_mem;
1151
1152 ring->dma = dma_alloc_coherent(eth->dev,
1153 MTK_DMA_SIZE * sz,
1154 &ring->phys,
1155 GFP_ATOMIC | __GFP_ZERO);
1156 if (!ring->dma)
1157 goto no_tx_mem;
1158
1159 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1160 for (i = 0; i < MTK_DMA_SIZE; i++) {
1161 int next = (i + 1) % MTK_DMA_SIZE;
1162 u32 next_ptr = ring->phys + next * sz;
1163
1164 ring->dma[i].txd2 = next_ptr;
1165 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1166 }
1167
1168 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1169 ring->next_free = &ring->dma[0];
12c97c13 1170 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1171 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1172
1173 /* make sure that all changes to the dma ring are flushed before we
1174 * continue
1175 */
1176 wmb();
1177
1178 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1179 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1180 mtk_w32(eth,
1181 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1182 MTK_QTX_CRX_PTR);
1183 mtk_w32(eth,
1184 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1185 MTK_QTX_DRX_PTR);
bacfd110 1186 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
656e7052
JC		 1187
1188 return 0;
1189
1190no_tx_mem:
1191 return -ENOMEM;
1192}
1193
1194static void mtk_tx_clean(struct mtk_eth *eth)
1195{
1196 struct mtk_tx_ring *ring = &eth->tx_ring;
1197 int i;
1198
1199 if (ring->buf) {
1200 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1201 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1202 kfree(ring->buf);
1203 ring->buf = NULL;
1204 }
1205
1206 if (ring->dma) {
1207 dma_free_coherent(eth->dev,
1208 MTK_DMA_SIZE * sizeof(*ring->dma),
1209 ring->dma,
1210 ring->phys);
1211 ring->dma = NULL;
1212 }
1213}
1214
ee406810 1215static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
656e7052 1216{
ee406810
NC		 1217 struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
1218 int rx_data_len, rx_dma_size;
656e7052
JC		 1219 int i;
1220
ee406810
NC		 1221 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1222 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1223 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1224 } else {
1225 rx_data_len = ETH_DATA_LEN;
1226 rx_dma_size = MTK_DMA_SIZE;
1227 }
1228
1229 ring->frag_size = mtk_max_frag_size(rx_data_len);
656e7052 1230 ring->buf_size = mtk_max_buf_size(ring->frag_size);
ee406810 1231 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
656e7052
JC		 1232 GFP_KERNEL);
1233 if (!ring->data)
1234 return -ENOMEM;
1235
ee406810 1236 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1237 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1238 if (!ring->data[i])
1239 return -ENOMEM;
1240 }
1241
1242 ring->dma = dma_alloc_coherent(eth->dev,
ee406810 1243 rx_dma_size * sizeof(*ring->dma),
656e7052
JC		 1244 &ring->phys,
1245 GFP_ATOMIC | __GFP_ZERO);
1246 if (!ring->dma)
1247 return -ENOMEM;
1248
ee406810 1249 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1250 dma_addr_t dma_addr = dma_map_single(eth->dev,
1251 ring->data[i] + NET_SKB_PAD,
1252 ring->buf_size,
1253 DMA_FROM_DEVICE);
1254 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1255 return -ENOMEM;
1256 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1257
1258 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1259 }
ee406810
NC		 1260 ring->dma_size = rx_dma_size;
1261 ring->calc_idx_update = false;
1262 ring->calc_idx = rx_dma_size - 1;
1263 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
656e7052
JC		 1264 /* make sure that all changes to the dma ring are flushed before we
1265 * continue
1266 */
1267 wmb();
1268
ee406810
NC		 1269 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
1270 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
1271 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1272 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
656e7052
JC		 1273
1274 return 0;
1275}
1276
ee406810 1277static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
656e7052 1278{
ee406810 1279 struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
656e7052
JC		 1280 int i;
1281
1282 if (ring->data && ring->dma) {
ee406810 1283 for (i = 0; i < ring->dma_size; i++) {
656e7052
JC		 1284 if (!ring->data[i])
1285 continue;
1286 if (!ring->dma[i].rxd1)
1287 continue;
1288 dma_unmap_single(eth->dev,
1289 ring->dma[i].rxd1,
1290 ring->buf_size,
1291 DMA_FROM_DEVICE);
1292 skb_free_frag(ring->data[i]);
1293 }
1294 kfree(ring->data);
1295 ring->data = NULL;
1296 }
1297
1298 if (ring->dma) {
1299 dma_free_coherent(eth->dev,
ee406810 1300 ring->dma_size * sizeof(*ring->dma),
656e7052
JC		 1301 ring->dma,
1302 ring->phys);
1303 ring->dma = NULL;
1304 }
1305}
1306
ee406810
NC		 1307static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1308{
1309 int i;
1310 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1311 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1312
1313 /* set LRO rings to auto-learn modes */
1314 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1315
1316 /* validate LRO ring */
1317 ring_ctrl_dw2 |= MTK_RING_VLD;
1318
1319 /* set AGE timer (unit: 20us) */
1320 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1321 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1322
1323 /* set max AGG timer (unit: 20us) */
1324 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1325
1326 /* set max LRO AGG count */
1327 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1328 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1329
1330 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1331 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1332 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1333 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1334 }
1335
1336 /* IPv4 checksum update enable */
1337 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1338
1339 /* switch priority comparison to packet count mode */
1340 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1341
1342 /* bandwidth threshold setting */
1343 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1344
1345 /* auto-learn score delta setting */
1346 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1347
1348 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1349 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1350 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1351
1352 /* set HW LRO mode & the max aggregation count for rx packets */
1353 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1354
1355 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1356 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1357
1358 /* enable HW LRO */
1359 lro_ctrl_dw0 |= MTK_LRO_EN;
1360
1361 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1362 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1363
1364 return 0;
1365}
1366
1367static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1368{
1369 int i;
1370 u32 val;
1371
1372 /* relinquish lro rings, flush aggregated packets */
1373 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1374
1375 /* wait for relinquishments done */
1376 for (i = 0; i < 10; i++) {
1377 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1378 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1379 msleep(20);
1380 continue;
1381 }
1382 }
1383
1384 /* invalidate lro rings */
1385 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1386 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1387
1388 /* disable HW LRO */
1389 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1390}
1391
7aab747e
NC		 1392static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1393{
1394 u32 reg_val;
1395
1396 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1397
1398 /* invalidate the IP setting */
1399 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1400
1401 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1402
1403 /* validate the IP setting */
1404 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1405}
1406
1407static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1408{
1409 u32 reg_val;
1410
1411 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1412
1413 /* invalidate the IP setting */
1414 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1415
1416 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1417}
1418
1419static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1420{
1421 int cnt = 0;
1422 int i;
1423
1424 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1425 if (mac->hwlro_ip[i])
1426 cnt++;
1427 }
1428
1429 return cnt;
1430}
1431
1432static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1433 struct ethtool_rxnfc *cmd)
1434{
1435 struct ethtool_rx_flow_spec *fsp =
1436 (struct ethtool_rx_flow_spec *)&cmd->fs;
1437 struct mtk_mac *mac = netdev_priv(dev);
1438 struct mtk_eth *eth = mac->hw;
1439 int hwlro_idx;
1440
1441 if ((fsp->flow_type != TCP_V4_FLOW) ||
1442 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1443 (fsp->location > 1))
1444 return -EINVAL;
1445
1446 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1447 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1448
1449 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1450
1451 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1452
1453 return 0;
1454}
1455
1456static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1457 struct ethtool_rxnfc *cmd)
1458{
1459 struct ethtool_rx_flow_spec *fsp =
1460 (struct ethtool_rx_flow_spec *)&cmd->fs;
1461 struct mtk_mac *mac = netdev_priv(dev);
1462 struct mtk_eth *eth = mac->hw;
1463 int hwlro_idx;
1464
1465 if (fsp->location > 1)
1466 return -EINVAL;
1467
1468 mac->hwlro_ip[fsp->location] = 0;
1469 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1470
1471 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1472
1473 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1474
1475 return 0;
1476}
1477
1478static void mtk_hwlro_netdev_disable(struct net_device *dev)
1479{
1480 struct mtk_mac *mac = netdev_priv(dev);
1481 struct mtk_eth *eth = mac->hw;
1482 int i, hwlro_idx;
1483
1484 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1485 mac->hwlro_ip[i] = 0;
1486 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1487
1488 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1489 }
1490
1491 mac->hwlro_ip_cnt = 0;
1492}
1493
1494static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1495 struct ethtool_rxnfc *cmd)
1496{
1497 struct mtk_mac *mac = netdev_priv(dev);
1498 struct ethtool_rx_flow_spec *fsp =
1499 (struct ethtool_rx_flow_spec *)&cmd->fs;
1500
1501 /* only tcp dst ipv4 is meaningful, others are meaningless */
1502 fsp->flow_type = TCP_V4_FLOW;
1503 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1504 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1505
1506 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1507 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1508 fsp->h_u.tcp_ip4_spec.psrc = 0;
1509 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1510 fsp->h_u.tcp_ip4_spec.pdst = 0;
1511 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1512 fsp->h_u.tcp_ip4_spec.tos = 0;
1513 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1514
1515 return 0;
1516}
1517
1518static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1519 struct ethtool_rxnfc *cmd,
1520 u32 *rule_locs)
1521{
1522 struct mtk_mac *mac = netdev_priv(dev);
1523 int cnt = 0;
1524 int i;
1525
1526 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1527 if (mac->hwlro_ip[i]) {
1528 rule_locs[cnt] = i;
1529 cnt++;
1530 }
1531 }
1532
1533 cmd->rule_cnt = cnt;
1534
1535 return 0;
1536}
1537
1538static netdev_features_t mtk_fix_features(struct net_device *dev,
1539 netdev_features_t features)
1540{
1541 if (!(features & NETIF_F_LRO)) {
1542 struct mtk_mac *mac = netdev_priv(dev);
1543 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1544
1545 if (ip_cnt) {
1546 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1547
1548 features |= NETIF_F_LRO;
1549 }
1550 }
1551
1552 return features;
1553}
1554
1555static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1556{
1557 int err = 0;
1558
1559 if (!((dev->features ^ features) & NETIF_F_LRO))
1560 return 0;
1561
1562 if (!(features & NETIF_F_LRO))
1563 mtk_hwlro_netdev_disable(dev);
1564
1565 return err;
1566}
1567
656e7052
JC		 1568/* wait for DMA to finish whatever it is doing before we start using it again */
1569static int mtk_dma_busy_wait(struct mtk_eth *eth)
1570{
1571 unsigned long t_start = jiffies;
1572
1573 while (1) {
1574 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1575 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1576 return 0;
1577 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1578 break;
1579 }
1580
1581 dev_err(eth->dev, "DMA init timeout\n");
1582 return -1;
1583}
1584
1585static int mtk_dma_init(struct mtk_eth *eth)
1586{
1587 int err;
ee406810 1588 u32 i;
656e7052
JC		 1589
1590 if (mtk_dma_busy_wait(eth))
1591 return -EBUSY;
1592
1593 /* QDMA needs scratch memory for internal reordering of the
1594 * descriptors
1595 */
1596 err = mtk_init_fq_dma(eth);
1597 if (err)
1598 return err;
1599
1600 err = mtk_tx_alloc(eth);
1601 if (err)
1602 return err;
1603
ee406810 1604 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
656e7052
JC		 1605 if (err)
1606 return err;
1607
ee406810
NC		 1608 if (eth->hwlro) {
1609 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1610 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1611 if (err)
1612 return err;
1613 }
1614 err = mtk_hwlro_rx_init(eth);
1615 if (err)
1616 return err;
1617 }
1618
656e7052
JC		 1619 /* Enable random early drop and set drop threshold automatically */
1620 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1621 MTK_QDMA_FC_THRES);
1622 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1623
1624 return 0;
1625}
1626
1627static void mtk_dma_free(struct mtk_eth *eth)
1628{
1629 int i;
1630
1631 for (i = 0; i < MTK_MAC_COUNT; i++)
1632 if (eth->netdev[i])
1633 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1634 if (eth->scratch_ring) {
1635 dma_free_coherent(eth->dev,
1636 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1637 eth->scratch_ring,
1638 eth->phy_scratch_ring);
1639 eth->scratch_ring = NULL;
1640 eth->phy_scratch_ring = 0;
1641 }
656e7052 1642 mtk_tx_clean(eth);
ee406810
NC		 1643 mtk_rx_clean(eth, 0);
1644
1645 if (eth->hwlro) {
1646 mtk_hwlro_rx_uninit(eth);
1647 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1648 mtk_rx_clean(eth, i);
1649 }
1650
656e7052
JC		 1651 kfree(eth->scratch_head);
1652}
1653
1654static void mtk_tx_timeout(struct net_device *dev)
1655{
1656 struct mtk_mac *mac = netdev_priv(dev);
1657 struct mtk_eth *eth = mac->hw;
1658
1659 eth->netdev[mac->id]->stats.tx_errors++;
1660 netif_err(eth, tx_err, dev,
1661 "transmit timed out\n");
7c78b4ad 1662 schedule_work(&eth->pending_work);
656e7052
JC		 1663}
1664
80673029 1665static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1666{
1667 struct mtk_eth *eth = _eth;
656e7052 1668
80673029
JC		 1669 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1670 __napi_schedule(&eth->rx_napi);
bacfd110 1671 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1672 }
656e7052 1673
80673029
JC		 1674 return IRQ_HANDLED;
1675}
1676
1677static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1678{
1679 struct mtk_eth *eth = _eth;
1680
1681 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1682 __napi_schedule(&eth->tx_napi);
bacfd110 1683 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
656e7052 1684 }
656e7052
JC		 1685
1686 return IRQ_HANDLED;
1687}
1688
1689#ifdef CONFIG_NET_POLL_CONTROLLER
1690static void mtk_poll_controller(struct net_device *dev)
1691{
1692 struct mtk_mac *mac = netdev_priv(dev);
1693 struct mtk_eth *eth = mac->hw;
656e7052 1694
bacfd110
NC		 1695 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1696 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
8186f6e3 1697 mtk_handle_irq_rx(eth->irq[2], dev);
bacfd110
NC		 1698 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1699 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1700}
1701#endif
1702
1703static int mtk_start_dma(struct mtk_eth *eth)
1704{
1705 int err;
1706
1707 err = mtk_dma_init(eth);
1708 if (err) {
1709 mtk_dma_free(eth);
1710 return err;
1711 }
1712
1713 mtk_w32(eth,
bacfd110
NC		 1714 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1715 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1716 MTK_QDMA_GLO_CFG);
1717
bacfd110
NC		 1718 mtk_w32(eth,
1719 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1720 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1721 MTK_PDMA_GLO_CFG);
1722
656e7052
JC		 1723 return 0;
1724}
1725
1726static int mtk_open(struct net_device *dev)
1727{
1728 struct mtk_mac *mac = netdev_priv(dev);
1729 struct mtk_eth *eth = mac->hw;
1730
1731 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1732 if (!atomic_read(&eth->dma_refcnt)) {
1733 int err = mtk_start_dma(eth);
1734
1735 if (err)
1736 return err;
1737
80673029 1738 napi_enable(&eth->tx_napi);
656e7052 1739 napi_enable(&eth->rx_napi);
bacfd110
NC		 1740 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1741 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1742 }
1743 atomic_inc(&eth->dma_refcnt);
1744
1745 phy_start(mac->phy_dev);
1746 netif_start_queue(dev);
1747
1748 return 0;
1749}
1750
1751static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1752{
656e7052
JC		 1753 u32 val;
1754 int i;
1755
1756 /* stop the dma engine */
e3e9652a 1757 spin_lock_bh(&eth->page_lock);
656e7052
JC		 1758 val = mtk_r32(eth, glo_cfg);
1759 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1760 glo_cfg);
e3e9652a 1761 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 1762
1763 /* wait for dma stop */
1764 for (i = 0; i < 10; i++) {
1765 val = mtk_r32(eth, glo_cfg);
1766 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1767 msleep(20);
1768 continue;
1769 }
1770 break;
1771 }
1772}
1773
1774static int mtk_stop(struct net_device *dev)
1775{
1776 struct mtk_mac *mac = netdev_priv(dev);
1777 struct mtk_eth *eth = mac->hw;
1778
1779 netif_tx_disable(dev);
1780 phy_stop(mac->phy_dev);
1781
1782 /* only shutdown DMA if this is the last user */
1783 if (!atomic_dec_and_test(&eth->dma_refcnt))
1784 return 0;
1785
bacfd110
NC		 1786 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1787 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1788 napi_disable(&eth->tx_napi);
656e7052
JC		 1789 napi_disable(&eth->rx_napi);
1790
1791 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1792
1793 mtk_dma_free(eth);
1794
1795 return 0;
1796}
1797
2a8307aa
SW		 1798static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1799{
1800 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1801 reset_bits,
1802 reset_bits);
1803
1804 usleep_range(1000, 1100);
1805 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1806 reset_bits,
1807 ~reset_bits);
1808 mdelay(10);
1809}
1810
9ea4d311 1811static int mtk_hw_init(struct mtk_eth *eth)
656e7052 1812{
9ea4d311
SW		 1813 int i, val;
1814
1815 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1816 return 0;
85574dbf 1817
26a2ad8a
SW		 1818 pm_runtime_enable(eth->dev);
1819 pm_runtime_get_sync(eth->dev);
1820
85574dbf
SW		 1821 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1822 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1823 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1824 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
2a8307aa
SW		 1825 ethsys_reset(eth, RSTCTRL_FE);
1826 ethsys_reset(eth, RSTCTRL_PPE);
656e7052 1827
9ea4d311
SW		 1828 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1829 for (i = 0; i < MTK_MAC_COUNT; i++) {
1830 if (!eth->mac[i])
1831 continue;
1832 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1833 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1834 }
1835 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1836
656e7052
JC		 1837 /* Set GE2 driving and slew rate */
1838 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1839
1840 /* set GE2 TDSEL */
1841 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1842
1843 /* set GE2 TUNE */
1844 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1845
1846 /* GE1, Force 1000M/FD, FC ON */
1847 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1848
1849 /* GE2, Force 1000M/FD, FC ON */
1850 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1851
1852 /* Enable RX VLan Offloading */
1853 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1854
656e7052
JC		 1855 /* disable delay and normal interrupt */
1856 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
bacfd110
NC		 1857 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1858 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1859 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
656e7052
JC		 1860 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1861 mtk_w32(eth, 0, MTK_RST_GL);
1862
1863 /* FE int grouping */
80673029
JC		 1864 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1865 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1866 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1867 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1868 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1869
1870 for (i = 0; i < 2; i++) {
1871 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1872
9c08435e 1873 /* setup the forward port to send frame to PDMA */
656e7052 1874 val &= ~0xffff;
656e7052
JC		 1875
1876 /* Enable RX checksum */
1877 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1878
1879 /* setup the mac dma */
1880 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1881 }
1882
1883 return 0;
1884}
1885
bf253fb7
SW		 1886static int mtk_hw_deinit(struct mtk_eth *eth)
1887{
9ea4d311
SW		 1888 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
1889 return 0;
1890
bf253fb7
SW		 1891 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1892 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1893 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1894 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1895
26a2ad8a
SW		 1896 pm_runtime_put_sync(eth->dev);
1897 pm_runtime_disable(eth->dev);
1898
bf253fb7
SW		 1899 return 0;
1900}
1901
656e7052
JC		 1902static int __init mtk_init(struct net_device *dev)
1903{
1904 struct mtk_mac *mac = netdev_priv(dev);
1905 struct mtk_eth *eth = mac->hw;
1906 const char *mac_addr;
1907
1908 mac_addr = of_get_mac_address(mac->of_node);
1909 if (mac_addr)
1910 ether_addr_copy(dev->dev_addr, mac_addr);
1911
1912 /* If the mac address is invalid, use random mac address */
1913 if (!is_valid_ether_addr(dev->dev_addr)) {
1914 random_ether_addr(dev->dev_addr);
1915 dev_err(eth->dev, "generated random MAC address %pM\n",
1916 dev->dev_addr);
1917 dev->addr_assign_type = NET_ADDR_RANDOM;
1918 }
1919
1920 return mtk_phy_connect(mac);
1921}
1922
1923static void mtk_uninit(struct net_device *dev)
1924{
1925 struct mtk_mac *mac = netdev_priv(dev);
1926 struct mtk_eth *eth = mac->hw;
1927
1928 phy_disconnect(mac->phy_dev);
bacfd110
NC		 1929 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1930 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
656e7052
JC		 1931}
1932
1933static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1934{
1935 struct mtk_mac *mac = netdev_priv(dev);
1936
1937 switch (cmd) {
1938 case SIOCGMIIPHY:
1939 case SIOCGMIIREG:
1940 case SIOCSMIIREG:
1941 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1942 default:
1943 break;
1944 }
1945
1946 return -EOPNOTSUPP;
1947}
1948
1949static void mtk_pending_work(struct work_struct *work)
1950{
7c78b4ad 1951 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1952 int err, i;
1953 unsigned long restart = 0;
656e7052
JC		 1954
1955 rtnl_lock();
656e7052 1956
dce6fa42
SW		 1957 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
1958
1959 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
1960 cpu_relax();
1961
1962 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
e7d425dc
JC		 1963 /* stop all devices to make sure that dma is properly shut down */
1964 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1965 if (!eth->netdev[i])
e7d425dc
JC		 1966 continue;
1967 mtk_stop(eth->netdev[i]);
1968 __set_bit(i, &restart);
1969 }
dce6fa42 1970 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
e7d425dc 1971
9ea4d311
SW		 1972 /* restart underlying hardware such as power, clock, pin mux
1973 * and the connected phy
1974 */
1975 mtk_hw_deinit(eth);
1976
1977 if (eth->dev->pins)
1978 pinctrl_select_state(eth->dev->pins->p,
1979 eth->dev->pins->default_state);
1980 mtk_hw_init(eth);
1981
1982 for (i = 0; i < MTK_MAC_COUNT; i++) {
1983 if (!eth->mac[i] ||
1984 of_phy_is_fixed_link(eth->mac[i]->of_node))
1985 continue;
1986 err = phy_init_hw(eth->mac[i]->phy_dev);
1987 if (err)
1988 dev_err(eth->dev, "%s: PHY init failed.\n",
1989 eth->netdev[i]->name);
1990 }
1991
e7d425dc
JC		 1992 /* restart DMA and enable IRQs */
1993 for (i = 0; i < MTK_MAC_COUNT; i++) {
1994 if (!test_bit(i, &restart))
1995 continue;
1996 err = mtk_open(eth->netdev[i]);
1997 if (err) {
1998 netif_alert(eth, ifup, eth->netdev[i],
1999 "Driver up/down cycle failed, closing device.\n");
2000 dev_close(eth->netdev[i]);
2001 }
656e7052 2002 }
dce6fa42
SW		 2003
2004 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2005
2006 clear_bit_unlock(MTK_RESETTING, &eth->state);
2007
656e7052
JC		 2008 rtnl_unlock();
2009}
2010
8a8a9e89 2011static int mtk_free_dev(struct mtk_eth *eth)
656e7052
JC		 2012{
2013 int i;
2014
2015 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 2016 if (!eth->netdev[i])
2017 continue;
8a8a9e89
SW		 2018 free_netdev(eth->netdev[i]);
2019 }
2020
2021 return 0;
2022}
656e7052 2023
8a8a9e89
SW		 2024static int mtk_unreg_dev(struct mtk_eth *eth)
2025{
2026 int i;
2027
2028 for (i = 0; i < MTK_MAC_COUNT; i++) {
2029 if (!eth->netdev[i])
2030 continue;
656e7052 2031 unregister_netdev(eth->netdev[i]);
656e7052 2032 }
8a8a9e89
SW		 2033
2034 return 0;
2035}
2036
2037static int mtk_cleanup(struct mtk_eth *eth)
2038{
2039 mtk_unreg_dev(eth);
2040 mtk_free_dev(eth);
7c78b4ad 2041 cancel_work_sync(&eth->pending_work);
656e7052
JC		 2042
2043 return 0;
2044}
2045
2046static int mtk_get_settings(struct net_device *dev,
2047 struct ethtool_cmd *cmd)
2048{
2049 struct mtk_mac *mac = netdev_priv(dev);
2050 int err;
2051
dce6fa42
SW		 2052 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2053 return -EBUSY;
2054
656e7052
JC		 2055 err = phy_read_status(mac->phy_dev);
2056 if (err)
2057 return -ENODEV;
2058
2059 return phy_ethtool_gset(mac->phy_dev, cmd);
2060}
2061
2062static int mtk_set_settings(struct net_device *dev,
2063 struct ethtool_cmd *cmd)
2064{
2065 struct mtk_mac *mac = netdev_priv(dev);
2066
2067 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
2068 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
2069 cmd->phy_address);
2070 if (!mac->phy_dev)
2071 return -ENODEV;
2072 }
2073
2074 return phy_ethtool_sset(mac->phy_dev, cmd);
2075}
2076
2077static void mtk_get_drvinfo(struct net_device *dev,
2078 struct ethtool_drvinfo *info)
2079{
2080 struct mtk_mac *mac = netdev_priv(dev);
2081
2082 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2083 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2084 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2085}
2086
2087static u32 mtk_get_msglevel(struct net_device *dev)
2088{
2089 struct mtk_mac *mac = netdev_priv(dev);
2090
2091 return mac->hw->msg_enable;
2092}
2093
2094static void mtk_set_msglevel(struct net_device *dev, u32 value)
2095{
2096 struct mtk_mac *mac = netdev_priv(dev);
2097
2098 mac->hw->msg_enable = value;
2099}
2100
2101static int mtk_nway_reset(struct net_device *dev)
2102{
2103 struct mtk_mac *mac = netdev_priv(dev);
2104
dce6fa42
SW		 2105 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2106 return -EBUSY;
2107
656e7052
JC		 2108 return genphy_restart_aneg(mac->phy_dev);
2109}
2110
2111static u32 mtk_get_link(struct net_device *dev)
2112{
2113 struct mtk_mac *mac = netdev_priv(dev);
2114 int err;
2115
dce6fa42
SW		 2116 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2117 return -EBUSY;
2118
656e7052
JC		 2119 err = genphy_update_link(mac->phy_dev);
2120 if (err)
2121 return ethtool_op_get_link(dev);
2122
2123 return mac->phy_dev->link;
2124}
2125
2126static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2127{
2128 int i;
2129
2130 switch (stringset) {
2131 case ETH_SS_STATS:
2132 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2133 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2134 data += ETH_GSTRING_LEN;
2135 }
2136 break;
2137 }
2138}
2139
2140static int mtk_get_sset_count(struct net_device *dev, int sset)
2141{
2142 switch (sset) {
2143 case ETH_SS_STATS:
2144 return ARRAY_SIZE(mtk_ethtool_stats);
2145 default:
2146 return -EOPNOTSUPP;
2147 }
2148}
2149
2150static void mtk_get_ethtool_stats(struct net_device *dev,
2151 struct ethtool_stats *stats, u64 *data)
2152{
2153 struct mtk_mac *mac = netdev_priv(dev);
2154 struct mtk_hw_stats *hwstats = mac->hw_stats;
2155 u64 *data_src, *data_dst;
2156 unsigned int start;
2157 int i;
2158
dce6fa42
SW		 2159 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2160 return;
2161
656e7052
JC		 2162 if (netif_running(dev) && netif_device_present(dev)) {
2163 if (spin_trylock(&hwstats->stats_lock)) {
2164 mtk_stats_update_mac(mac);
2165 spin_unlock(&hwstats->stats_lock);
2166 }
2167 }
2168
94d308d0
SW		 2169 data_src = (u64 *)hwstats;
2170
656e7052 2171 do {
656e7052
JC		 2172 data_dst = data;
2173 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2174
2175 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2176 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2177 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2178}
2179
7aab747e
NC		 2180static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2181 u32 *rule_locs)
2182{
2183 int ret = -EOPNOTSUPP;
2184
2185 switch (cmd->cmd) {
2186 case ETHTOOL_GRXRINGS:
2187 if (dev->features & NETIF_F_LRO) {
2188 cmd->data = MTK_MAX_RX_RING_NUM;
2189 ret = 0;
2190 }
2191 break;
2192 case ETHTOOL_GRXCLSRLCNT:
2193 if (dev->features & NETIF_F_LRO) {
2194 struct mtk_mac *mac = netdev_priv(dev);
2195
2196 cmd->rule_cnt = mac->hwlro_ip_cnt;
2197 ret = 0;
2198 }
2199 break;
2200 case ETHTOOL_GRXCLSRULE:
2201 if (dev->features & NETIF_F_LRO)
2202 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2203 break;
2204 case ETHTOOL_GRXCLSRLALL:
2205 if (dev->features & NETIF_F_LRO)
2206 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2207 rule_locs);
2208 break;
2209 default:
2210 break;
2211 }
2212
2213 return ret;
2214}
2215
2216static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2217{
2218 int ret = -EOPNOTSUPP;
2219
2220 switch (cmd->cmd) {
2221 case ETHTOOL_SRXCLSRLINS:
2222 if (dev->features & NETIF_F_LRO)
2223 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2224 break;
2225 case ETHTOOL_SRXCLSRLDEL:
2226 if (dev->features & NETIF_F_LRO)
2227 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2228 break;
2229 default:
2230 break;
2231 }
2232
2233 return ret;
2234}
2235
6a38cb15 2236static const struct ethtool_ops mtk_ethtool_ops = {
656e7052
JC		 2237 .get_settings = mtk_get_settings,
2238 .set_settings = mtk_set_settings,
2239 .get_drvinfo = mtk_get_drvinfo,
2240 .get_msglevel = mtk_get_msglevel,
2241 .set_msglevel = mtk_set_msglevel,
2242 .nway_reset = mtk_nway_reset,
2243 .get_link = mtk_get_link,
2244 .get_strings = mtk_get_strings,
2245 .get_sset_count = mtk_get_sset_count,
2246 .get_ethtool_stats = mtk_get_ethtool_stats,
7aab747e
NC		 2247 .get_rxnfc = mtk_get_rxnfc,
2248 .set_rxnfc = mtk_set_rxnfc,
656e7052
JC		 2249};
2250
2251static const struct net_device_ops mtk_netdev_ops = {
2252 .ndo_init = mtk_init,
2253 .ndo_uninit = mtk_uninit,
2254 .ndo_open = mtk_open,
2255 .ndo_stop = mtk_stop,
2256 .ndo_start_xmit = mtk_start_xmit,
2257 .ndo_set_mac_address = mtk_set_mac_address,
2258 .ndo_validate_addr = eth_validate_addr,
2259 .ndo_do_ioctl = mtk_do_ioctl,
2260 .ndo_change_mtu = eth_change_mtu,
2261 .ndo_tx_timeout = mtk_tx_timeout,
2262 .ndo_get_stats64 = mtk_get_stats64,
7aab747e
NC		 2263 .ndo_fix_features = mtk_fix_features,
2264 .ndo_set_features = mtk_set_features,
656e7052
JC		 2265#ifdef CONFIG_NET_POLL_CONTROLLER
2266 .ndo_poll_controller = mtk_poll_controller,
2267#endif
2268};
2269
2270static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2271{
2272 struct mtk_mac *mac;
2273 const __be32 *_id = of_get_property(np, "reg", NULL);
2274 int id, err;
2275
2276 if (!_id) {
2277 dev_err(eth->dev, "missing mac id\n");
2278 return -EINVAL;
2279 }
2280
2281 id = be32_to_cpup(_id);
2282 if (id >= MTK_MAC_COUNT) {
2283 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2284 return -EINVAL;
2285 }
2286
2287 if (eth->netdev[id]) {
2288 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2289 return -EINVAL;
2290 }
2291
2292 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2293 if (!eth->netdev[id]) {
2294 dev_err(eth->dev, "alloc_etherdev failed\n");
2295 return -ENOMEM;
2296 }
2297 mac = netdev_priv(eth->netdev[id]);
2298 eth->mac[id] = mac;
2299 mac->id = id;
2300 mac->hw = eth;
2301 mac->of_node = np;
656e7052 2302
ee406810
NC		 2303 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2304 mac->hwlro_ip_cnt = 0;
2305
656e7052
JC		 2306 mac->hw_stats = devm_kzalloc(eth->dev,
2307 sizeof(*mac->hw_stats),
2308 GFP_KERNEL);
2309 if (!mac->hw_stats) {
2310 dev_err(eth->dev, "failed to allocate counter memory\n");
2311 err = -ENOMEM;
2312 goto free_netdev;
2313 }
2314 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 2315 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 2316 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2317
2318 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 2319 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 2320 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2321 eth->netdev[id]->base_addr = (unsigned long)eth->base;
ee406810
NC		 2322
2323 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2324 if (eth->hwlro)
2325 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2326
656e7052
JC		 2327 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2328 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2329 eth->netdev[id]->features |= MTK_HW_FEATURES;
2330 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2331
80673029 2332 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 2333 return 0;
2334
2335free_netdev:
2336 free_netdev(eth->netdev[id]);
2337 return err;
2338}
2339
2340static int mtk_probe(struct platform_device *pdev)
2341{
2342 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2343 struct device_node *mac_np;
2344 const struct of_device_id *match;
2345 struct mtk_soc_data *soc;
2346 struct mtk_eth *eth;
2347 int err;
80673029 2348 int i;
656e7052 2349
656e7052
JC		 2350 match = of_match_device(of_mtk_match, &pdev->dev);
2351 soc = (struct mtk_soc_data *)match->data;
2352
2353 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2354 if (!eth)
2355 return -ENOMEM;
2356
549e5495 2357 eth->dev = &pdev->dev;
656e7052 2358 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 2359 if (IS_ERR(eth->base))
2360 return PTR_ERR(eth->base);
656e7052
JC		 2361
2362 spin_lock_init(&eth->page_lock);
7bc9ccec 2363 spin_lock_init(&eth->irq_lock);
656e7052
JC		 2364
2365 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2366 "mediatek,ethsys");
2367 if (IS_ERR(eth->ethsys)) {
2368 dev_err(&pdev->dev, "no ethsys regmap found\n");
2369 return PTR_ERR(eth->ethsys);
2370 }
2371
2372 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2373 "mediatek,pctl");
2374 if (IS_ERR(eth->pctl)) {
2375 dev_err(&pdev->dev, "no pctl regmap found\n");
2376 return PTR_ERR(eth->pctl);
2377 }
2378
ee406810
NC		 2379 eth->hwlro = of_property_read_bool(pdev->dev.of_node, "mediatek,hwlro");
2380
80673029
JC		 2381 for (i = 0; i < 3; i++) {
2382 eth->irq[i] = platform_get_irq(pdev, i);
2383 if (eth->irq[i] < 0) {
2384 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2385 return -ENXIO;
2386 }
656e7052 2387 }
549e5495
SW		 2388 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2389 eth->clks[i] = devm_clk_get(eth->dev,
2390 mtk_clks_source_name[i]);
2391 if (IS_ERR(eth->clks[i])) {
2392 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2393 return -EPROBE_DEFER;
2394 return -ENODEV;
2395 }
2396 }
656e7052 2397
656e7052 2398 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 2399 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 2400
2401 err = mtk_hw_init(eth);
2402 if (err)
2403 return err;
2404
2405 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2406 if (!of_device_is_compatible(mac_np,
2407 "mediatek,eth-mac"))
2408 continue;
2409
2410 if (!of_device_is_available(mac_np))
2411 continue;
2412
2413 err = mtk_add_mac(eth, mac_np);
2414 if (err)
8a8a9e89 2415 goto err_deinit_hw;
656e7052
JC		 2416 }
2417
85574dbf
SW		 2418 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2419 dev_name(eth->dev), eth);
2420 if (err)
2421 goto err_free_dev;
2422
2423 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2424 dev_name(eth->dev), eth);
2425 if (err)
2426 goto err_free_dev;
2427
2428 err = mtk_mdio_init(eth);
2429 if (err)
2430 goto err_free_dev;
2431
2432 for (i = 0; i < MTK_MAX_DEVS; i++) {
2433 if (!eth->netdev[i])
2434 continue;
2435
2436 err = register_netdev(eth->netdev[i]);
2437 if (err) {
2438 dev_err(eth->dev, "error bringing up device\n");
8a8a9e89 2439 goto err_deinit_mdio;
85574dbf
SW		 2440 } else
2441 netif_info(eth, probe, eth->netdev[i],
2442 "mediatek frame engine at 0x%08lx, irq %d\n",
2443 eth->netdev[i]->base_addr, eth->irq[0]);
2444 }
2445
656e7052
JC		 2446 /* we run 2 devices on the same DMA ring so we need a dummy device
2447 * for NAPI to work
2448 */
2449 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 2450 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2451 MTK_NAPI_WEIGHT);
2452 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 2453 MTK_NAPI_WEIGHT);
2454
2455 platform_set_drvdata(pdev, eth);
2456
2457 return 0;
2458
8a8a9e89
SW		 2459err_deinit_mdio:
2460 mtk_mdio_cleanup(eth);
656e7052 2461err_free_dev:
8a8a9e89
SW		 2462 mtk_free_dev(eth);
2463err_deinit_hw:
2464 mtk_hw_deinit(eth);
2465
656e7052
JC		 2466 return err;
2467}
2468
2469static int mtk_remove(struct platform_device *pdev)
2470{
2471 struct mtk_eth *eth = platform_get_drvdata(pdev);
79e9a414
SW		 2472 int i;
2473
2474 /* stop all devices to make sure that dma is properly shut down */
2475 for (i = 0; i < MTK_MAC_COUNT; i++) {
2476 if (!eth->netdev[i])
2477 continue;
2478 mtk_stop(eth->netdev[i]);
2479 }
656e7052 2480
bf253fb7 2481 mtk_hw_deinit(eth);
656e7052 2482
80673029 2483 netif_napi_del(&eth->tx_napi);
656e7052
JC		 2484 netif_napi_del(&eth->rx_napi);
2485 mtk_cleanup(eth);
e82f7148 2486 mtk_mdio_cleanup(eth);
656e7052
JC		 2487
2488 return 0;
2489}
2490
2491const struct of_device_id of_mtk_match[] = {
2492 { .compatible = "mediatek,mt7623-eth" },
2493 {},
2494};
2495
2496static struct platform_driver mtk_driver = {
2497 .probe = mtk_probe,
2498 .remove = mtk_remove,
2499 .driver = {
2500 .name = "mtk_soc_eth",
656e7052
JC		 2501 .of_match_table = of_mtk_match,
2502 },
2503};
2504
2505module_platform_driver(mtk_driver);
2506
2507MODULE_LICENSE("GPL");
2508MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2509MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
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