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net: ethernet: mediatek: add extension of phy-mode for TRGMII
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
26a2ad8a 21#include <linux/pm_runtime.h>
656e7052
JC		 22#include <linux/if_vlan.h>
23#include <linux/reset.h>
24#include <linux/tcp.h>
25
26#include "mtk_eth_soc.h"
27
28static int mtk_msg_level = -1;
29module_param_named(msg_level, mtk_msg_level, int, 0);
30MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32#define MTK_ETHTOOL_STAT(x) { #x, \
33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
34
35/* strings used by ethtool */
36static const struct mtk_ethtool_stats {
37 char str[ETH_GSTRING_LEN];
38 u32 offset;
39} mtk_ethtool_stats[] = {
40 MTK_ETHTOOL_STAT(tx_bytes),
41 MTK_ETHTOOL_STAT(tx_packets),
42 MTK_ETHTOOL_STAT(tx_skip),
43 MTK_ETHTOOL_STAT(tx_collisions),
44 MTK_ETHTOOL_STAT(rx_bytes),
45 MTK_ETHTOOL_STAT(rx_packets),
46 MTK_ETHTOOL_STAT(rx_overflow),
47 MTK_ETHTOOL_STAT(rx_fcs_errors),
48 MTK_ETHTOOL_STAT(rx_short_errors),
49 MTK_ETHTOOL_STAT(rx_long_errors),
50 MTK_ETHTOOL_STAT(rx_checksum_errors),
51 MTK_ETHTOOL_STAT(rx_flow_control_packets),
52};
53
549e5495
SW		 54static const char * const mtk_clks_source_name[] = {
55 "ethif", "esw", "gp1", "gp2"
56};
57
656e7052
JC		 58void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59{
60 __raw_writel(val, eth->base + reg);
61}
62
63u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64{
65 return __raw_readl(eth->base + reg);
66}
67
68static int mtk_mdio_busy_wait(struct mtk_eth *eth)
69{
70 unsigned long t_start = jiffies;
71
72 while (1) {
73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
74 return 0;
75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
76 break;
77 usleep_range(10, 20);
78 }
79
80 dev_err(eth->dev, "mdio: MDIO timeout\n");
81 return -1;
82}
83
379672de
WY		 84static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
85 u32 phy_register, u32 write_data)
656e7052
JC		 86{
87 if (mtk_mdio_busy_wait(eth))
88 return -1;
89
90 write_data &= 0xffff;
91
92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
93 (phy_register << PHY_IAC_REG_SHIFT) |
94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
95 MTK_PHY_IAC);
96
97 if (mtk_mdio_busy_wait(eth))
98 return -1;
99
100 return 0;
101}
102
379672de 103static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 104{
105 u32 d;
106
107 if (mtk_mdio_busy_wait(eth))
108 return 0xffff;
109
110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
111 (phy_reg << PHY_IAC_REG_SHIFT) |
112 (phy_addr << PHY_IAC_ADDR_SHIFT),
113 MTK_PHY_IAC);
114
115 if (mtk_mdio_busy_wait(eth))
116 return 0xffff;
117
118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
119
120 return d;
121}
122
123static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
124 int phy_reg, u16 val)
125{
126 struct mtk_eth *eth = bus->priv;
127
128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
129}
130
131static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
132{
133 struct mtk_eth *eth = bus->priv;
134
135 return _mtk_mdio_read(eth, phy_addr, phy_reg);
136}
137
138static void mtk_phy_link_adjust(struct net_device *dev)
139{
140 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 141 u16 lcl_adv = 0, rmt_adv = 0;
142 u8 flowctrl;
656e7052
JC		 143 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
144 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
145 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
146 MAC_MCR_BACKPR_EN;
147
dce6fa42
SW		 148 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
149 return;
150
656e7052
JC		 151 switch (mac->phy_dev->speed) {
152 case SPEED_1000:
153 mcr |= MAC_MCR_SPEED_1000;
154 break;
155 case SPEED_100:
156 mcr |= MAC_MCR_SPEED_100;
157 break;
158 };
159
160 if (mac->phy_dev->link)
161 mcr |= MAC_MCR_FORCE_LINK;
162
08ef55c6 163 if (mac->phy_dev->duplex) {
656e7052
JC		 164 mcr |= MAC_MCR_FORCE_DPX;
165
08ef55c6
JC		 166 if (mac->phy_dev->pause)
167 rmt_adv = LPA_PAUSE_CAP;
168 if (mac->phy_dev->asym_pause)
169 rmt_adv |= LPA_PAUSE_ASYM;
170
171 if (mac->phy_dev->advertising & ADVERTISED_Pause)
172 lcl_adv |= ADVERTISE_PAUSE_CAP;
173 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
174 lcl_adv |= ADVERTISE_PAUSE_ASYM;
175
176 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
177
178 if (flowctrl & FLOW_CTRL_TX)
179 mcr |= MAC_MCR_FORCE_TX_FC;
180 if (flowctrl & FLOW_CTRL_RX)
181 mcr |= MAC_MCR_FORCE_RX_FC;
182
183 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
184 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
185 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
186 }
656e7052
JC		 187
188 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
189
190 if (mac->phy_dev->link)
191 netif_carrier_on(dev);
192 else
193 netif_carrier_off(dev);
194}
195
196static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
197 struct device_node *phy_node)
198{
199 const __be32 *_addr = NULL;
200 struct phy_device *phydev;
201 int phy_mode, addr;
202
203 _addr = of_get_property(phy_node, "reg", NULL);
204
205 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
206 pr_err("%s: invalid phy address\n", phy_node->name);
207 return -EINVAL;
208 }
209 addr = be32_to_cpu(*_addr);
210 phy_mode = of_get_phy_mode(phy_node);
211 if (phy_mode < 0) {
212 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
213 return -EINVAL;
214 }
215
216 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
217 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 218 if (!phydev) {
656e7052 219 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 220 return -ENODEV;
656e7052
JC		 221 }
222
223 dev_info(eth->dev,
224 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
225 mac->id, phydev_name(phydev), phydev->phy_id,
226 phydev->drv->name);
227
228 mac->phy_dev = phydev;
229
230 return 0;
231}
232
233static int mtk_phy_connect(struct mtk_mac *mac)
234{
235 struct mtk_eth *eth = mac->hw;
236 struct device_node *np;
9ea4d311 237 u32 val;
656e7052
JC		 238
239 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 240 if (!np && of_phy_is_fixed_link(mac->of_node))
241 if (!of_phy_register_fixed_link(mac->of_node))
242 np = of_node_get(mac->of_node);
656e7052
JC		 243 if (!np)
244 return -ENODEV;
245
246 switch (of_get_phy_mode(np)) {
572de608
SW		 247 case PHY_INTERFACE_MODE_TRGMII:
248 mac->trgmii = true;
37920fce
JC		 249 case PHY_INTERFACE_MODE_RGMII_TXID:
250 case PHY_INTERFACE_MODE_RGMII_RXID:
251 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052 252 case PHY_INTERFACE_MODE_RGMII:
9ea4d311 253 mac->ge_mode = 0;
656e7052
JC		 254 break;
255 case PHY_INTERFACE_MODE_MII:
9ea4d311 256 mac->ge_mode = 1;
656e7052 257 break;
8ca7f4fe 258 case PHY_INTERFACE_MODE_REVMII:
9ea4d311 259 mac->ge_mode = 2;
656e7052 260 break;
8ca7f4fe 261 case PHY_INTERFACE_MODE_RMII:
262 if (!mac->id)
263 goto err_phy;
9ea4d311 264 mac->ge_mode = 3;
8ca7f4fe 265 break;
656e7052 266 default:
8ca7f4fe 267 goto err_phy;
656e7052
JC		 268 }
269
270 /* put the gmac into the right mode */
271 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
272 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
9ea4d311 273 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
656e7052
JC		 274 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
275
276 mtk_phy_connect_node(eth, mac, np);
277 mac->phy_dev->autoneg = AUTONEG_ENABLE;
278 mac->phy_dev->speed = 0;
279 mac->phy_dev->duplex = 0;
b2025c7c 280
281 if (of_phy_is_fixed_link(mac->of_node))
282 mac->phy_dev->supported |=
283 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
284
08ef55c6
JC		 285 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
286 SUPPORTED_Asym_Pause;
656e7052
JC		 287 mac->phy_dev->advertising = mac->phy_dev->supported |
288 ADVERTISED_Autoneg;
289 phy_start_aneg(mac->phy_dev);
290
e8c2993a 291 of_node_put(np);
292
656e7052 293 return 0;
8ca7f4fe 294
295err_phy:
296 of_node_put(np);
297 dev_err(eth->dev, "invalid phy_mode\n");
298 return -EINVAL;
656e7052
JC		 299}
300
301static int mtk_mdio_init(struct mtk_eth *eth)
302{
303 struct device_node *mii_np;
1e515b7f 304 int ret;
656e7052
JC		 305
306 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
307 if (!mii_np) {
308 dev_err(eth->dev, "no %s child node found", "mdio-bus");
309 return -ENODEV;
310 }
311
312 if (!of_device_is_available(mii_np)) {
aa6e8a54 313 ret = -ENODEV;
656e7052
JC		 314 goto err_put_node;
315 }
316
1e515b7f 317 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
656e7052 318 if (!eth->mii_bus) {
1e515b7f 319 ret = -ENOMEM;
656e7052
JC		 320 goto err_put_node;
321 }
322
323 eth->mii_bus->name = "mdio";
324 eth->mii_bus->read = mtk_mdio_read;
325 eth->mii_bus->write = mtk_mdio_write;
326 eth->mii_bus->priv = eth;
327 eth->mii_bus->parent = eth->dev;
328
329 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
1e515b7f 330 ret = of_mdiobus_register(eth->mii_bus, mii_np);
656e7052
JC		 331
332err_put_node:
333 of_node_put(mii_np);
1e515b7f 334 return ret;
656e7052
JC		 335}
336
337static void mtk_mdio_cleanup(struct mtk_eth *eth)
338{
339 if (!eth->mii_bus)
340 return;
341
342 mdiobus_unregister(eth->mii_bus);
656e7052
JC		 343}
344
bacfd110
NC		 345static inline void mtk_irq_disable(struct mtk_eth *eth,
346 unsigned reg, u32 mask)
656e7052 347{
7bc9ccec 348 unsigned long flags;
656e7052
JC		 349 u32 val;
350
7bc9ccec 351 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 352 val = mtk_r32(eth, reg);
353 mtk_w32(eth, val & ~mask, reg);
7bc9ccec 354 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 355}
356
bacfd110
NC		 357static inline void mtk_irq_enable(struct mtk_eth *eth,
358 unsigned reg, u32 mask)
656e7052 359{
7bc9ccec 360 unsigned long flags;
656e7052
JC		 361 u32 val;
362
7bc9ccec 363 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 364 val = mtk_r32(eth, reg);
365 mtk_w32(eth, val | mask, reg);
7bc9ccec 366 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 367}
368
369static int mtk_set_mac_address(struct net_device *dev, void *p)
370{
371 int ret = eth_mac_addr(dev, p);
372 struct mtk_mac *mac = netdev_priv(dev);
373 const char *macaddr = dev->dev_addr;
656e7052
JC		 374
375 if (ret)
376 return ret;
377
dce6fa42
SW		 378 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
379 return -EBUSY;
380
e3e9652a 381 spin_lock_bh(&mac->hw->page_lock);
656e7052
JC		 382 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
383 MTK_GDMA_MAC_ADRH(mac->id));
384 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
385 (macaddr[4] << 8) | macaddr[5],
386 MTK_GDMA_MAC_ADRL(mac->id));
e3e9652a 387 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 388
389 return 0;
390}
391
392void mtk_stats_update_mac(struct mtk_mac *mac)
393{
394 struct mtk_hw_stats *hw_stats = mac->hw_stats;
395 unsigned int base = MTK_GDM1_TX_GBCNT;
396 u64 stats;
397
398 base += hw_stats->reg_offset;
399
400 u64_stats_update_begin(&hw_stats->syncp);
401
402 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
403 stats = mtk_r32(mac->hw, base + 0x04);
404 if (stats)
405 hw_stats->rx_bytes += (stats << 32);
406 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
407 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
408 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
409 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
410 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
411 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
412 hw_stats->rx_flow_control_packets +=
413 mtk_r32(mac->hw, base + 0x24);
414 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
415 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
416 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
417 stats = mtk_r32(mac->hw, base + 0x34);
418 if (stats)
419 hw_stats->tx_bytes += (stats << 32);
420 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
421 u64_stats_update_end(&hw_stats->syncp);
422}
423
424static void mtk_stats_update(struct mtk_eth *eth)
425{
426 int i;
427
428 for (i = 0; i < MTK_MAC_COUNT; i++) {
429 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
430 continue;
431 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
432 mtk_stats_update_mac(eth->mac[i]);
433 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
434 }
435 }
436}
437
438static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
439 struct rtnl_link_stats64 *storage)
440{
441 struct mtk_mac *mac = netdev_priv(dev);
442 struct mtk_hw_stats *hw_stats = mac->hw_stats;
443 unsigned int start;
444
445 if (netif_running(dev) && netif_device_present(dev)) {
446 if (spin_trylock(&hw_stats->stats_lock)) {
447 mtk_stats_update_mac(mac);
448 spin_unlock(&hw_stats->stats_lock);
449 }
450 }
451
452 do {
453 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
454 storage->rx_packets = hw_stats->rx_packets;
455 storage->tx_packets = hw_stats->tx_packets;
456 storage->rx_bytes = hw_stats->rx_bytes;
457 storage->tx_bytes = hw_stats->tx_bytes;
458 storage->collisions = hw_stats->tx_collisions;
459 storage->rx_length_errors = hw_stats->rx_short_errors +
460 hw_stats->rx_long_errors;
461 storage->rx_over_errors = hw_stats->rx_overflow;
462 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
463 storage->rx_errors = hw_stats->rx_checksum_errors;
464 storage->tx_aborted_errors = hw_stats->tx_skip;
465 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
466
467 storage->tx_errors = dev->stats.tx_errors;
468 storage->rx_dropped = dev->stats.rx_dropped;
469 storage->tx_dropped = dev->stats.tx_dropped;
470
471 return storage;
472}
473
474static inline int mtk_max_frag_size(int mtu)
475{
476 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
477 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
478 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
479
480 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
481 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
482}
483
484static inline int mtk_max_buf_size(int frag_size)
485{
486 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
487 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
488
489 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
490
491 return buf_size;
492}
493
494static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
495 struct mtk_rx_dma *dma_rxd)
496{
497 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
498 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
499 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
500 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
501}
502
503/* the qdma core needs scratch memory to be setup */
504static int mtk_init_fq_dma(struct mtk_eth *eth)
505{
605e4fe4 506 dma_addr_t phy_ring_tail;
656e7052
JC		 507 int cnt = MTK_DMA_SIZE;
508 dma_addr_t dma_addr;
509 int i;
510
511 eth->scratch_ring = dma_alloc_coherent(eth->dev,
512 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 513 &eth->phy_scratch_ring,
656e7052
JC		 514 GFP_ATOMIC | __GFP_ZERO);
515 if (unlikely(!eth->scratch_ring))
516 return -ENOMEM;
517
518 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
519 GFP_KERNEL);
562c5a70
JC		 520 if (unlikely(!eth->scratch_head))
521 return -ENOMEM;
522
656e7052
JC		 523 dma_addr = dma_map_single(eth->dev,
524 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
525 DMA_FROM_DEVICE);
526 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
527 return -ENOMEM;
528
529 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 530 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 531 (sizeof(struct mtk_tx_dma) * (cnt - 1));
532
533 for (i = 0; i < cnt; i++) {
534 eth->scratch_ring[i].txd1 =
535 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
536 if (i < cnt - 1)
605e4fe4 537 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 538 ((i + 1) * sizeof(struct mtk_tx_dma)));
539 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
540 }
541
605e4fe4 542 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 543 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
544 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
545 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
546
547 return 0;
548}
549
550static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
551{
552 void *ret = ring->dma;
553
554 return ret + (desc - ring->phys);
555}
556
557static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
558 struct mtk_tx_dma *txd)
559{
560 int idx = txd - ring->dma;
561
562 return &ring->buf[idx];
563}
564
55a4e778 565static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 566{
567 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 568 dma_unmap_single(eth->dev,
656e7052
JC		 569 dma_unmap_addr(tx_buf, dma_addr0),
570 dma_unmap_len(tx_buf, dma_len0),
571 DMA_TO_DEVICE);
572 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 573 dma_unmap_page(eth->dev,
656e7052
JC		 574 dma_unmap_addr(tx_buf, dma_addr0),
575 dma_unmap_len(tx_buf, dma_len0),
576 DMA_TO_DEVICE);
577 }
578 tx_buf->flags = 0;
579 if (tx_buf->skb &&
580 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
581 dev_kfree_skb_any(tx_buf->skb);
582 tx_buf->skb = NULL;
583}
584
585static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
586 int tx_num, struct mtk_tx_ring *ring, bool gso)
587{
588 struct mtk_mac *mac = netdev_priv(dev);
589 struct mtk_eth *eth = mac->hw;
590 struct mtk_tx_dma *itxd, *txd;
591 struct mtk_tx_buf *tx_buf;
656e7052
JC		 592 dma_addr_t mapped_addr;
593 unsigned int nr_frags;
594 int i, n_desc = 1;
c6f1dc4d 595 u32 txd4 = 0, fport;
656e7052
JC		 596
597 itxd = ring->next_free;
598 if (itxd == ring->last_free)
599 return -ENOMEM;
600
601 /* set the forward port */
c6f1dc4d
SW		 602 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
603 txd4 |= fport;
656e7052
JC		 604
605 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
606 memset(tx_buf, 0, sizeof(*tx_buf));
607
608 if (gso)
609 txd4 |= TX_DMA_TSO;
610
611 /* TX Checksum offload */
612 if (skb->ip_summed == CHECKSUM_PARTIAL)
613 txd4 |= TX_DMA_CHKSUM;
614
615 /* VLAN header offload */
616 if (skb_vlan_tag_present(skb))
617 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
618
55a4e778 619 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 620 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 621 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 622 return -ENOMEM;
623
656e7052
JC		 624 WRITE_ONCE(itxd->txd1, mapped_addr);
625 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
626 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
627 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
628
629 /* TX SG offload */
630 txd = itxd;
631 nr_frags = skb_shinfo(skb)->nr_frags;
632 for (i = 0; i < nr_frags; i++) {
633 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
634 unsigned int offset = 0;
635 int frag_size = skb_frag_size(frag);
636
637 while (frag_size) {
638 bool last_frag = false;
639 unsigned int frag_map_size;
640
641 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
642 if (txd == ring->last_free)
643 goto err_dma;
644
645 n_desc++;
646 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 647 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 648 frag_map_size,
649 DMA_TO_DEVICE);
55a4e778 650 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 651 goto err_dma;
652
653 if (i == nr_frags - 1 &&
654 (frag_size - frag_map_size) == 0)
655 last_frag = true;
656
657 WRITE_ONCE(txd->txd1, mapped_addr);
658 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
659 TX_DMA_PLEN0(frag_map_size) |
369f0453 660 last_frag * TX_DMA_LS0));
c6f1dc4d 661 WRITE_ONCE(txd->txd4, fport);
656e7052
JC		 662
663 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
664 tx_buf = mtk_desc_to_tx_buf(ring, txd);
665 memset(tx_buf, 0, sizeof(*tx_buf));
666
667 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
668 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
669 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
670 frag_size -= frag_map_size;
671 offset += frag_map_size;
672 }
673 }
674
675 /* store skb to cleanup */
676 tx_buf->skb = skb;
677
678 WRITE_ONCE(itxd->txd4, txd4);
679 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
680 (!nr_frags * TX_DMA_LS0)));
681
656e7052
JC		 682 netdev_sent_queue(dev, skb->len);
683 skb_tx_timestamp(skb);
684
685 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
686 atomic_sub(n_desc, &ring->free_count);
687
688 /* make sure that all changes to the dma ring are flushed before we
689 * continue
690 */
691 wmb();
692
693 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
694 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
695
696 return 0;
697
698err_dma:
699 do {
2fae723c 700 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 701
702 /* unmap dma */
55a4e778 703 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 704
705 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
706 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
707 } while (itxd != txd);
708
709 return -ENOMEM;
710}
711
712static inline int mtk_cal_txd_req(struct sk_buff *skb)
713{
714 int i, nfrags;
715 struct skb_frag_struct *frag;
716
717 nfrags = 1;
718 if (skb_is_gso(skb)) {
719 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
720 frag = &skb_shinfo(skb)->frags[i];
721 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
722 }
723 } else {
724 nfrags += skb_shinfo(skb)->nr_frags;
725 }
726
beeb4ca4 727 return nfrags;
656e7052
JC		 728}
729
ad3cba98
JC		 730static int mtk_queue_stopped(struct mtk_eth *eth)
731{
732 int i;
733
734 for (i = 0; i < MTK_MAC_COUNT; i++) {
735 if (!eth->netdev[i])
736 continue;
737 if (netif_queue_stopped(eth->netdev[i]))
738 return 1;
739 }
740
741 return 0;
742}
743
13c822f6
JC		 744static void mtk_wake_queue(struct mtk_eth *eth)
745{
746 int i;
747
748 for (i = 0; i < MTK_MAC_COUNT; i++) {
749 if (!eth->netdev[i])
750 continue;
751 netif_wake_queue(eth->netdev[i]);
752 }
753}
754
755static void mtk_stop_queue(struct mtk_eth *eth)
756{
757 int i;
758
759 for (i = 0; i < MTK_MAC_COUNT; i++) {
760 if (!eth->netdev[i])
761 continue;
762 netif_stop_queue(eth->netdev[i]);
763 }
764}
765
656e7052
JC		 766static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
767{
768 struct mtk_mac *mac = netdev_priv(dev);
769 struct mtk_eth *eth = mac->hw;
770 struct mtk_tx_ring *ring = &eth->tx_ring;
771 struct net_device_stats *stats = &dev->stats;
772 bool gso = false;
773 int tx_num;
774
34c2e4c9
JC		 775 /* normally we can rely on the stack not calling this more than once,
776 * however we have 2 queues running on the same ring so we need to lock
777 * the ring access
778 */
e3e9652a 779 spin_lock(&eth->page_lock);
34c2e4c9 780
dce6fa42
SW		 781 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
782 goto drop;
783
656e7052
JC		 784 tx_num = mtk_cal_txd_req(skb);
785 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 786 mtk_stop_queue(eth);
656e7052
JC		 787 netif_err(eth, tx_queued, dev,
788 "Tx Ring full when queue awake!\n");
e3e9652a 789 spin_unlock(&eth->page_lock);
656e7052
JC		 790 return NETDEV_TX_BUSY;
791 }
792
793 /* TSO: fill MSS info in tcp checksum field */
794 if (skb_is_gso(skb)) {
795 if (skb_cow_head(skb, 0)) {
796 netif_warn(eth, tx_err, dev,
797 "GSO expand head fail.\n");
798 goto drop;
799 }
800
801 if (skb_shinfo(skb)->gso_type &
802 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
803 gso = true;
804 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
805 }
806 }
807
808 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
809 goto drop;
810
82c6544d 811 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 812 mtk_stop_queue(eth);
82c6544d 813
e3e9652a 814 spin_unlock(&eth->page_lock);
656e7052
JC		 815
816 return NETDEV_TX_OK;
817
818drop:
e3e9652a 819 spin_unlock(&eth->page_lock);
656e7052
JC		 820 stats->tx_dropped++;
821 dev_kfree_skb(skb);
822 return NETDEV_TX_OK;
823}
824
ee406810
NC		 825static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
826{
827 int i;
828 struct mtk_rx_ring *ring;
829 int idx;
830
831 if (!eth->hwlro)
832 return &eth->rx_ring[0];
833
834 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
835 ring = &eth->rx_ring[i];
836 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
837 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
838 ring->calc_idx_update = true;
839 return ring;
840 }
841 }
842
843 return NULL;
844}
845
846static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
847{
848 struct mtk_rx_ring *ring;
849 int i;
850
851 if (!eth->hwlro) {
852 ring = &eth->rx_ring[0];
853 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
854 } else {
855 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
856 ring = &eth->rx_ring[i];
857 if (ring->calc_idx_update) {
858 ring->calc_idx_update = false;
859 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
860 }
861 }
862 }
863}
864
656e7052 865static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 866 struct mtk_eth *eth)
656e7052 867{
ee406810
NC		 868 struct mtk_rx_ring *ring;
869 int idx;
656e7052
JC		 870 struct sk_buff *skb;
871 u8 *data, *new_data;
872 struct mtk_rx_dma *rxd, trxd;
873 int done = 0;
874
875 while (done < budget) {
876 struct net_device *netdev;
877 unsigned int pktlen;
878 dma_addr_t dma_addr;
879 int mac = 0;
880
ee406810
NC		 881 ring = mtk_get_rx_ring(eth);
882 if (unlikely(!ring))
883 goto rx_done;
884
885 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
656e7052
JC		 886 rxd = &ring->dma[idx];
887 data = ring->data[idx];
888
889 mtk_rx_get_desc(&trxd, rxd);
890 if (!(trxd.rxd2 & RX_DMA_DONE))
891 break;
892
893 /* find out which mac the packet come from. values start at 1 */
894 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
895 RX_DMA_FPORT_MASK;
896 mac--;
897
898 netdev = eth->netdev[mac];
899
dce6fa42
SW		 900 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
901 goto release_desc;
902
656e7052
JC		 903 /* alloc new buffer */
904 new_data = napi_alloc_frag(ring->frag_size);
905 if (unlikely(!new_data)) {
906 netdev->stats.rx_dropped++;
907 goto release_desc;
908 }
55a4e778 909 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 910 new_data + NET_SKB_PAD,
911 ring->buf_size,
912 DMA_FROM_DEVICE);
55a4e778 913 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 914 skb_free_frag(new_data);
94321a9f 915 netdev->stats.rx_dropped++;
656e7052
JC		 916 goto release_desc;
917 }
918
919 /* receive data */
920 skb = build_skb(data, ring->frag_size);
921 if (unlikely(!skb)) {
1b430799 922 skb_free_frag(new_data);
94321a9f 923 netdev->stats.rx_dropped++;
656e7052
JC		 924 goto release_desc;
925 }
926 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
927
55a4e778 928 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 929 ring->buf_size, DMA_FROM_DEVICE);
930 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
931 skb->dev = netdev;
932 skb_put(skb, pktlen);
933 if (trxd.rxd4 & RX_DMA_L4_VALID)
934 skb->ip_summed = CHECKSUM_UNNECESSARY;
935 else
936 skb_checksum_none_assert(skb);
937 skb->protocol = eth_type_trans(skb, netdev);
938
939 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
940 RX_DMA_VID(trxd.rxd3))
941 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
942 RX_DMA_VID(trxd.rxd3));
943 napi_gro_receive(napi, skb);
944
945 ring->data[idx] = new_data;
946 rxd->rxd1 = (unsigned int)dma_addr;
947
948release_desc:
949 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
950
951 ring->calc_idx = idx;
635372ad 952
656e7052
JC		 953 done++;
954 }
955
ee406810 956rx_done:
41156cea
SW		 957 if (done) {
958 /* make sure that all changes to the dma ring are flushed before
959 * we continue
960 */
961 wmb();
ee406810 962 mtk_update_rx_cpu_idx(eth);
41156cea 963 }
656e7052
JC		 964
965 return done;
966}
967
80673029 968static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 969{
970 struct mtk_tx_ring *ring = &eth->tx_ring;
971 struct mtk_tx_dma *desc;
972 struct sk_buff *skb;
973 struct mtk_tx_buf *tx_buf;
80673029 974 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 975 unsigned int bytes[MTK_MAX_DEVS];
976 u32 cpu, dma;
977 static int condition;
80673029 978 int total = 0, i;
656e7052
JC		 979
980 memset(done, 0, sizeof(done));
981 memset(bytes, 0, sizeof(bytes));
982
983 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
984 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
985
986 desc = mtk_qdma_phys_to_virt(ring, cpu);
987
988 while ((cpu != dma) && budget) {
989 u32 next_cpu = desc->txd2;
990 int mac;
991
992 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
993 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
994 break;
995
996 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
997 TX_DMA_FPORT_MASK;
998 mac--;
999
1000 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1001 skb = tx_buf->skb;
1002 if (!skb) {
1003 condition = 1;
1004 break;
1005 }
1006
1007 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1008 bytes[mac] += skb->len;
1009 done[mac]++;
1010 budget--;
1011 }
55a4e778 1012 mtk_tx_unmap(eth, tx_buf);
656e7052 1013
656e7052
JC		 1014 ring->last_free = desc;
1015 atomic_inc(&ring->free_count);
1016
1017 cpu = next_cpu;
1018 }
1019
1020 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1021
1022 for (i = 0; i < MTK_MAC_COUNT; i++) {
1023 if (!eth->netdev[i] || !done[i])
1024 continue;
1025 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1026 total += done[i];
1027 }
1028
ad3cba98
JC		 1029 if (mtk_queue_stopped(eth) &&
1030 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 1031 mtk_wake_queue(eth);
656e7052
JC		 1032
1033 return total;
1034}
1035
80673029 1036static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 1037{
80673029 1038 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 1039
eece71e8 1040 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 1041 mtk_stats_update(eth);
eece71e8
JC		 1042 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1043 MTK_INT_STATUS2);
656e7052 1044 }
80673029
JC		 1045}
1046
1047static int mtk_napi_tx(struct napi_struct *napi, int budget)
1048{
1049 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1050 u32 status, mask;
1051 int tx_done = 0;
1052
1053 mtk_handle_status_irq(eth);
1054 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1055 tx_done = mtk_poll_tx(eth, budget);
1056
1057 if (unlikely(netif_msg_intr(eth))) {
1058 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1059 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1060 dev_info(eth->dev,
1061 "done tx %d, intr 0x%08x/0x%x\n",
1062 tx_done, status, mask);
1063 }
1064
1065 if (tx_done == budget)
1066 return budget;
1067
1068 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1069 if (status & MTK_TX_DONE_INT)
1070 return budget;
1071
1072 napi_complete(napi);
bacfd110 1073 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
80673029
JC		 1074
1075 return tx_done;
1076}
1077
1078static int mtk_napi_rx(struct napi_struct *napi, int budget)
1079{
1080 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1081 u32 status, mask;
1082 int rx_done = 0;
41156cea 1083 int remain_budget = budget;
80673029
JC		 1084
1085 mtk_handle_status_irq(eth);
41156cea
SW		 1086
1087poll_again:
bacfd110 1088 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
41156cea 1089 rx_done = mtk_poll_rx(napi, remain_budget, eth);
656e7052
JC		 1090
1091 if (unlikely(netif_msg_intr(eth))) {
bacfd110
NC		 1092 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1093 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
80673029
JC		 1094 dev_info(eth->dev,
1095 "done rx %d, intr 0x%08x/0x%x\n",
1096 rx_done, status, mask);
656e7052 1097 }
41156cea 1098 if (rx_done == remain_budget)
656e7052
JC		 1099 return budget;
1100
bacfd110 1101 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
41156cea
SW		 1102 if (status & MTK_RX_DONE_INT) {
1103 remain_budget -= rx_done;
1104 goto poll_again;
1105 }
656e7052 1106 napi_complete(napi);
bacfd110 1107 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052 1108
41156cea 1109 return rx_done + budget - remain_budget;
656e7052
JC		 1110}
1111
1112static int mtk_tx_alloc(struct mtk_eth *eth)
1113{
1114 struct mtk_tx_ring *ring = &eth->tx_ring;
1115 int i, sz = sizeof(*ring->dma);
1116
1117 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1118 GFP_KERNEL);
1119 if (!ring->buf)
1120 goto no_tx_mem;
1121
1122 ring->dma = dma_alloc_coherent(eth->dev,
1123 MTK_DMA_SIZE * sz,
1124 &ring->phys,
1125 GFP_ATOMIC | __GFP_ZERO);
1126 if (!ring->dma)
1127 goto no_tx_mem;
1128
1129 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1130 for (i = 0; i < MTK_DMA_SIZE; i++) {
1131 int next = (i + 1) % MTK_DMA_SIZE;
1132 u32 next_ptr = ring->phys + next * sz;
1133
1134 ring->dma[i].txd2 = next_ptr;
1135 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1136 }
1137
1138 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1139 ring->next_free = &ring->dma[0];
12c97c13 1140 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1141 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1142
1143 /* make sure that all changes to the dma ring are flushed before we
1144 * continue
1145 */
1146 wmb();
1147
1148 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1149 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1150 mtk_w32(eth,
1151 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1152 MTK_QTX_CRX_PTR);
1153 mtk_w32(eth,
1154 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1155 MTK_QTX_DRX_PTR);
bacfd110 1156 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
656e7052
JC		 1157
1158 return 0;
1159
1160no_tx_mem:
1161 return -ENOMEM;
1162}
1163
1164static void mtk_tx_clean(struct mtk_eth *eth)
1165{
1166 struct mtk_tx_ring *ring = &eth->tx_ring;
1167 int i;
1168
1169 if (ring->buf) {
1170 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1171 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1172 kfree(ring->buf);
1173 ring->buf = NULL;
1174 }
1175
1176 if (ring->dma) {
1177 dma_free_coherent(eth->dev,
1178 MTK_DMA_SIZE * sizeof(*ring->dma),
1179 ring->dma,
1180 ring->phys);
1181 ring->dma = NULL;
1182 }
1183}
1184
ee406810 1185static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
656e7052 1186{
ee406810
NC		 1187 struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
1188 int rx_data_len, rx_dma_size;
656e7052
JC		 1189 int i;
1190
ee406810
NC		 1191 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1192 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1193 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1194 } else {
1195 rx_data_len = ETH_DATA_LEN;
1196 rx_dma_size = MTK_DMA_SIZE;
1197 }
1198
1199 ring->frag_size = mtk_max_frag_size(rx_data_len);
656e7052 1200 ring->buf_size = mtk_max_buf_size(ring->frag_size);
ee406810 1201 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
656e7052
JC		 1202 GFP_KERNEL);
1203 if (!ring->data)
1204 return -ENOMEM;
1205
ee406810 1206 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1207 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1208 if (!ring->data[i])
1209 return -ENOMEM;
1210 }
1211
1212 ring->dma = dma_alloc_coherent(eth->dev,
ee406810 1213 rx_dma_size * sizeof(*ring->dma),
656e7052
JC		 1214 &ring->phys,
1215 GFP_ATOMIC | __GFP_ZERO);
1216 if (!ring->dma)
1217 return -ENOMEM;
1218
ee406810 1219 for (i = 0; i < rx_dma_size; i++) {
656e7052
JC		 1220 dma_addr_t dma_addr = dma_map_single(eth->dev,
1221 ring->data[i] + NET_SKB_PAD,
1222 ring->buf_size,
1223 DMA_FROM_DEVICE);
1224 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1225 return -ENOMEM;
1226 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1227
1228 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1229 }
ee406810
NC		 1230 ring->dma_size = rx_dma_size;
1231 ring->calc_idx_update = false;
1232 ring->calc_idx = rx_dma_size - 1;
1233 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
656e7052
JC		 1234 /* make sure that all changes to the dma ring are flushed before we
1235 * continue
1236 */
1237 wmb();
1238
ee406810
NC		 1239 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
1240 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
1241 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1242 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
656e7052
JC		 1243
1244 return 0;
1245}
1246
ee406810 1247static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
656e7052 1248{
ee406810 1249 struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
656e7052
JC		 1250 int i;
1251
1252 if (ring->data && ring->dma) {
ee406810 1253 for (i = 0; i < ring->dma_size; i++) {
656e7052
JC		 1254 if (!ring->data[i])
1255 continue;
1256 if (!ring->dma[i].rxd1)
1257 continue;
1258 dma_unmap_single(eth->dev,
1259 ring->dma[i].rxd1,
1260 ring->buf_size,
1261 DMA_FROM_DEVICE);
1262 skb_free_frag(ring->data[i]);
1263 }
1264 kfree(ring->data);
1265 ring->data = NULL;
1266 }
1267
1268 if (ring->dma) {
1269 dma_free_coherent(eth->dev,
ee406810 1270 ring->dma_size * sizeof(*ring->dma),
656e7052
JC		 1271 ring->dma,
1272 ring->phys);
1273 ring->dma = NULL;
1274 }
1275}
1276
ee406810
NC		 1277static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1278{
1279 int i;
1280 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1281 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1282
1283 /* set LRO rings to auto-learn modes */
1284 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1285
1286 /* validate LRO ring */
1287 ring_ctrl_dw2 |= MTK_RING_VLD;
1288
1289 /* set AGE timer (unit: 20us) */
1290 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1291 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1292
1293 /* set max AGG timer (unit: 20us) */
1294 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1295
1296 /* set max LRO AGG count */
1297 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1298 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1299
1300 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1301 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1302 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1303 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1304 }
1305
1306 /* IPv4 checksum update enable */
1307 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1308
1309 /* switch priority comparison to packet count mode */
1310 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1311
1312 /* bandwidth threshold setting */
1313 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1314
1315 /* auto-learn score delta setting */
1316 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1317
1318 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1319 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1320 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1321
1322 /* set HW LRO mode & the max aggregation count for rx packets */
1323 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1324
1325 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1326 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1327
1328 /* enable HW LRO */
1329 lro_ctrl_dw0 |= MTK_LRO_EN;
1330
1331 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1332 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1333
1334 return 0;
1335}
1336
1337static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1338{
1339 int i;
1340 u32 val;
1341
1342 /* relinquish lro rings, flush aggregated packets */
1343 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1344
1345 /* wait for relinquishments done */
1346 for (i = 0; i < 10; i++) {
1347 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1348 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1349 msleep(20);
1350 continue;
1351 }
1352 }
1353
1354 /* invalidate lro rings */
1355 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1356 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1357
1358 /* disable HW LRO */
1359 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1360}
1361
7aab747e
NC		 1362static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1363{
1364 u32 reg_val;
1365
1366 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1367
1368 /* invalidate the IP setting */
1369 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1370
1371 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1372
1373 /* validate the IP setting */
1374 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1375}
1376
1377static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1378{
1379 u32 reg_val;
1380
1381 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1382
1383 /* invalidate the IP setting */
1384 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1385
1386 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1387}
1388
1389static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1390{
1391 int cnt = 0;
1392 int i;
1393
1394 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1395 if (mac->hwlro_ip[i])
1396 cnt++;
1397 }
1398
1399 return cnt;
1400}
1401
1402static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1403 struct ethtool_rxnfc *cmd)
1404{
1405 struct ethtool_rx_flow_spec *fsp =
1406 (struct ethtool_rx_flow_spec *)&cmd->fs;
1407 struct mtk_mac *mac = netdev_priv(dev);
1408 struct mtk_eth *eth = mac->hw;
1409 int hwlro_idx;
1410
1411 if ((fsp->flow_type != TCP_V4_FLOW) ||
1412 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1413 (fsp->location > 1))
1414 return -EINVAL;
1415
1416 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1417 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1418
1419 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1420
1421 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1422
1423 return 0;
1424}
1425
1426static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1427 struct ethtool_rxnfc *cmd)
1428{
1429 struct ethtool_rx_flow_spec *fsp =
1430 (struct ethtool_rx_flow_spec *)&cmd->fs;
1431 struct mtk_mac *mac = netdev_priv(dev);
1432 struct mtk_eth *eth = mac->hw;
1433 int hwlro_idx;
1434
1435 if (fsp->location > 1)
1436 return -EINVAL;
1437
1438 mac->hwlro_ip[fsp->location] = 0;
1439 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1440
1441 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1442
1443 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1444
1445 return 0;
1446}
1447
1448static void mtk_hwlro_netdev_disable(struct net_device *dev)
1449{
1450 struct mtk_mac *mac = netdev_priv(dev);
1451 struct mtk_eth *eth = mac->hw;
1452 int i, hwlro_idx;
1453
1454 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1455 mac->hwlro_ip[i] = 0;
1456 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1457
1458 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1459 }
1460
1461 mac->hwlro_ip_cnt = 0;
1462}
1463
1464static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1465 struct ethtool_rxnfc *cmd)
1466{
1467 struct mtk_mac *mac = netdev_priv(dev);
1468 struct ethtool_rx_flow_spec *fsp =
1469 (struct ethtool_rx_flow_spec *)&cmd->fs;
1470
1471 /* only tcp dst ipv4 is meaningful, others are meaningless */
1472 fsp->flow_type = TCP_V4_FLOW;
1473 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1474 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1475
1476 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1477 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1478 fsp->h_u.tcp_ip4_spec.psrc = 0;
1479 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1480 fsp->h_u.tcp_ip4_spec.pdst = 0;
1481 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1482 fsp->h_u.tcp_ip4_spec.tos = 0;
1483 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1484
1485 return 0;
1486}
1487
1488static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1489 struct ethtool_rxnfc *cmd,
1490 u32 *rule_locs)
1491{
1492 struct mtk_mac *mac = netdev_priv(dev);
1493 int cnt = 0;
1494 int i;
1495
1496 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1497 if (mac->hwlro_ip[i]) {
1498 rule_locs[cnt] = i;
1499 cnt++;
1500 }
1501 }
1502
1503 cmd->rule_cnt = cnt;
1504
1505 return 0;
1506}
1507
1508static netdev_features_t mtk_fix_features(struct net_device *dev,
1509 netdev_features_t features)
1510{
1511 if (!(features & NETIF_F_LRO)) {
1512 struct mtk_mac *mac = netdev_priv(dev);
1513 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1514
1515 if (ip_cnt) {
1516 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1517
1518 features |= NETIF_F_LRO;
1519 }
1520 }
1521
1522 return features;
1523}
1524
1525static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1526{
1527 int err = 0;
1528
1529 if (!((dev->features ^ features) & NETIF_F_LRO))
1530 return 0;
1531
1532 if (!(features & NETIF_F_LRO))
1533 mtk_hwlro_netdev_disable(dev);
1534
1535 return err;
1536}
1537
656e7052
JC		 1538/* wait for DMA to finish whatever it is doing before we start using it again */
1539static int mtk_dma_busy_wait(struct mtk_eth *eth)
1540{
1541 unsigned long t_start = jiffies;
1542
1543 while (1) {
1544 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1545 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1546 return 0;
1547 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1548 break;
1549 }
1550
1551 dev_err(eth->dev, "DMA init timeout\n");
1552 return -1;
1553}
1554
1555static int mtk_dma_init(struct mtk_eth *eth)
1556{
1557 int err;
ee406810 1558 u32 i;
656e7052
JC		 1559
1560 if (mtk_dma_busy_wait(eth))
1561 return -EBUSY;
1562
1563 /* QDMA needs scratch memory for internal reordering of the
1564 * descriptors
1565 */
1566 err = mtk_init_fq_dma(eth);
1567 if (err)
1568 return err;
1569
1570 err = mtk_tx_alloc(eth);
1571 if (err)
1572 return err;
1573
ee406810 1574 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
656e7052
JC		 1575 if (err)
1576 return err;
1577
ee406810
NC		 1578 if (eth->hwlro) {
1579 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1580 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1581 if (err)
1582 return err;
1583 }
1584 err = mtk_hwlro_rx_init(eth);
1585 if (err)
1586 return err;
1587 }
1588
656e7052
JC		 1589 /* Enable random early drop and set drop threshold automatically */
1590 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1591 MTK_QDMA_FC_THRES);
1592 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1593
1594 return 0;
1595}
1596
1597static void mtk_dma_free(struct mtk_eth *eth)
1598{
1599 int i;
1600
1601 for (i = 0; i < MTK_MAC_COUNT; i++)
1602 if (eth->netdev[i])
1603 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1604 if (eth->scratch_ring) {
1605 dma_free_coherent(eth->dev,
1606 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1607 eth->scratch_ring,
1608 eth->phy_scratch_ring);
1609 eth->scratch_ring = NULL;
1610 eth->phy_scratch_ring = 0;
1611 }
656e7052 1612 mtk_tx_clean(eth);
ee406810
NC		 1613 mtk_rx_clean(eth, 0);
1614
1615 if (eth->hwlro) {
1616 mtk_hwlro_rx_uninit(eth);
1617 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1618 mtk_rx_clean(eth, i);
1619 }
1620
656e7052
JC		 1621 kfree(eth->scratch_head);
1622}
1623
1624static void mtk_tx_timeout(struct net_device *dev)
1625{
1626 struct mtk_mac *mac = netdev_priv(dev);
1627 struct mtk_eth *eth = mac->hw;
1628
1629 eth->netdev[mac->id]->stats.tx_errors++;
1630 netif_err(eth, tx_err, dev,
1631 "transmit timed out\n");
7c78b4ad 1632 schedule_work(&eth->pending_work);
656e7052
JC		 1633}
1634
80673029 1635static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1636{
1637 struct mtk_eth *eth = _eth;
656e7052 1638
80673029
JC		 1639 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1640 __napi_schedule(&eth->rx_napi);
bacfd110 1641 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1642 }
656e7052 1643
80673029
JC		 1644 return IRQ_HANDLED;
1645}
1646
1647static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1648{
1649 struct mtk_eth *eth = _eth;
1650
1651 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1652 __napi_schedule(&eth->tx_napi);
bacfd110 1653 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
656e7052 1654 }
656e7052
JC		 1655
1656 return IRQ_HANDLED;
1657}
1658
1659#ifdef CONFIG_NET_POLL_CONTROLLER
1660static void mtk_poll_controller(struct net_device *dev)
1661{
1662 struct mtk_mac *mac = netdev_priv(dev);
1663 struct mtk_eth *eth = mac->hw;
656e7052 1664
bacfd110
NC		 1665 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1666 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
8186f6e3 1667 mtk_handle_irq_rx(eth->irq[2], dev);
bacfd110
NC		 1668 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1669 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1670}
1671#endif
1672
1673static int mtk_start_dma(struct mtk_eth *eth)
1674{
1675 int err;
1676
1677 err = mtk_dma_init(eth);
1678 if (err) {
1679 mtk_dma_free(eth);
1680 return err;
1681 }
1682
1683 mtk_w32(eth,
bacfd110
NC		 1684 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1685 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1686 MTK_QDMA_GLO_CFG);
1687
bacfd110
NC		 1688 mtk_w32(eth,
1689 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1690 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1691 MTK_PDMA_GLO_CFG);
1692
656e7052
JC		 1693 return 0;
1694}
1695
1696static int mtk_open(struct net_device *dev)
1697{
1698 struct mtk_mac *mac = netdev_priv(dev);
1699 struct mtk_eth *eth = mac->hw;
1700
1701 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1702 if (!atomic_read(&eth->dma_refcnt)) {
1703 int err = mtk_start_dma(eth);
1704
1705 if (err)
1706 return err;
1707
80673029 1708 napi_enable(&eth->tx_napi);
656e7052 1709 napi_enable(&eth->rx_napi);
bacfd110
NC		 1710 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1711 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1712 }
1713 atomic_inc(&eth->dma_refcnt);
1714
1715 phy_start(mac->phy_dev);
1716 netif_start_queue(dev);
1717
1718 return 0;
1719}
1720
1721static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1722{
656e7052
JC		 1723 u32 val;
1724 int i;
1725
1726 /* stop the dma engine */
e3e9652a 1727 spin_lock_bh(&eth->page_lock);
656e7052
JC		 1728 val = mtk_r32(eth, glo_cfg);
1729 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1730 glo_cfg);
e3e9652a 1731 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 1732
1733 /* wait for dma stop */
1734 for (i = 0; i < 10; i++) {
1735 val = mtk_r32(eth, glo_cfg);
1736 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1737 msleep(20);
1738 continue;
1739 }
1740 break;
1741 }
1742}
1743
1744static int mtk_stop(struct net_device *dev)
1745{
1746 struct mtk_mac *mac = netdev_priv(dev);
1747 struct mtk_eth *eth = mac->hw;
1748
1749 netif_tx_disable(dev);
1750 phy_stop(mac->phy_dev);
1751
1752 /* only shutdown DMA if this is the last user */
1753 if (!atomic_dec_and_test(&eth->dma_refcnt))
1754 return 0;
1755
bacfd110
NC		 1756 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1757 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1758 napi_disable(&eth->tx_napi);
656e7052
JC		 1759 napi_disable(&eth->rx_napi);
1760
1761 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1762
1763 mtk_dma_free(eth);
1764
1765 return 0;
1766}
1767
2a8307aa
SW		 1768static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1769{
1770 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1771 reset_bits,
1772 reset_bits);
1773
1774 usleep_range(1000, 1100);
1775 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1776 reset_bits,
1777 ~reset_bits);
1778 mdelay(10);
1779}
1780
9ea4d311 1781static int mtk_hw_init(struct mtk_eth *eth)
656e7052 1782{
9ea4d311
SW		 1783 int i, val;
1784
1785 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1786 return 0;
85574dbf 1787
26a2ad8a
SW		 1788 pm_runtime_enable(eth->dev);
1789 pm_runtime_get_sync(eth->dev);
1790
85574dbf
SW		 1791 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1792 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1793 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1794 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
2a8307aa
SW		 1795 ethsys_reset(eth, RSTCTRL_FE);
1796 ethsys_reset(eth, RSTCTRL_PPE);
656e7052 1797
9ea4d311
SW		 1798 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1799 for (i = 0; i < MTK_MAC_COUNT; i++) {
1800 if (!eth->mac[i])
1801 continue;
1802 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1803 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1804 }
1805 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1806
656e7052
JC		 1807 /* Set GE2 driving and slew rate */
1808 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1809
1810 /* set GE2 TDSEL */
1811 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1812
1813 /* set GE2 TUNE */
1814 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1815
1816 /* GE1, Force 1000M/FD, FC ON */
1817 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1818
1819 /* GE2, Force 1000M/FD, FC ON */
1820 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1821
1822 /* Enable RX VLan Offloading */
1823 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1824
656e7052
JC		 1825 /* disable delay and normal interrupt */
1826 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
bacfd110
NC		 1827 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1828 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1829 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
656e7052
JC		 1830 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1831 mtk_w32(eth, 0, MTK_RST_GL);
1832
1833 /* FE int grouping */
80673029
JC		 1834 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1835 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1836 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1837 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1838 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1839
1840 for (i = 0; i < 2; i++) {
1841 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1842
9c08435e 1843 /* setup the forward port to send frame to PDMA */
656e7052 1844 val &= ~0xffff;
656e7052
JC		 1845
1846 /* Enable RX checksum */
1847 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1848
1849 /* setup the mac dma */
1850 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1851 }
1852
1853 return 0;
1854}
1855
bf253fb7
SW		 1856static int mtk_hw_deinit(struct mtk_eth *eth)
1857{
9ea4d311
SW		 1858 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
1859 return 0;
1860
bf253fb7
SW		 1861 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1862 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1863 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1864 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1865
26a2ad8a
SW		 1866 pm_runtime_put_sync(eth->dev);
1867 pm_runtime_disable(eth->dev);
1868
bf253fb7
SW		 1869 return 0;
1870}
1871
656e7052
JC		 1872static int __init mtk_init(struct net_device *dev)
1873{
1874 struct mtk_mac *mac = netdev_priv(dev);
1875 struct mtk_eth *eth = mac->hw;
1876 const char *mac_addr;
1877
1878 mac_addr = of_get_mac_address(mac->of_node);
1879 if (mac_addr)
1880 ether_addr_copy(dev->dev_addr, mac_addr);
1881
1882 /* If the mac address is invalid, use random mac address */
1883 if (!is_valid_ether_addr(dev->dev_addr)) {
1884 random_ether_addr(dev->dev_addr);
1885 dev_err(eth->dev, "generated random MAC address %pM\n",
1886 dev->dev_addr);
1887 dev->addr_assign_type = NET_ADDR_RANDOM;
1888 }
1889
1890 return mtk_phy_connect(mac);
1891}
1892
1893static void mtk_uninit(struct net_device *dev)
1894{
1895 struct mtk_mac *mac = netdev_priv(dev);
1896 struct mtk_eth *eth = mac->hw;
1897
1898 phy_disconnect(mac->phy_dev);
bacfd110
NC		 1899 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1900 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
656e7052
JC		 1901}
1902
1903static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1904{
1905 struct mtk_mac *mac = netdev_priv(dev);
1906
1907 switch (cmd) {
1908 case SIOCGMIIPHY:
1909 case SIOCGMIIREG:
1910 case SIOCSMIIREG:
1911 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1912 default:
1913 break;
1914 }
1915
1916 return -EOPNOTSUPP;
1917}
1918
1919static void mtk_pending_work(struct work_struct *work)
1920{
7c78b4ad 1921 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1922 int err, i;
1923 unsigned long restart = 0;
656e7052
JC		 1924
1925 rtnl_lock();
656e7052 1926
dce6fa42
SW		 1927 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
1928
1929 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
1930 cpu_relax();
1931
1932 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
e7d425dc
JC		 1933 /* stop all devices to make sure that dma is properly shut down */
1934 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1935 if (!eth->netdev[i])
e7d425dc
JC		 1936 continue;
1937 mtk_stop(eth->netdev[i]);
1938 __set_bit(i, &restart);
1939 }
dce6fa42 1940 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
e7d425dc 1941
9ea4d311
SW		 1942 /* restart underlying hardware such as power, clock, pin mux
1943 * and the connected phy
1944 */
1945 mtk_hw_deinit(eth);
1946
1947 if (eth->dev->pins)
1948 pinctrl_select_state(eth->dev->pins->p,
1949 eth->dev->pins->default_state);
1950 mtk_hw_init(eth);
1951
1952 for (i = 0; i < MTK_MAC_COUNT; i++) {
1953 if (!eth->mac[i] ||
1954 of_phy_is_fixed_link(eth->mac[i]->of_node))
1955 continue;
1956 err = phy_init_hw(eth->mac[i]->phy_dev);
1957 if (err)
1958 dev_err(eth->dev, "%s: PHY init failed.\n",
1959 eth->netdev[i]->name);
1960 }
1961
e7d425dc
JC		 1962 /* restart DMA and enable IRQs */
1963 for (i = 0; i < MTK_MAC_COUNT; i++) {
1964 if (!test_bit(i, &restart))
1965 continue;
1966 err = mtk_open(eth->netdev[i]);
1967 if (err) {
1968 netif_alert(eth, ifup, eth->netdev[i],
1969 "Driver up/down cycle failed, closing device.\n");
1970 dev_close(eth->netdev[i]);
1971 }
656e7052 1972 }
dce6fa42
SW		 1973
1974 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
1975
1976 clear_bit_unlock(MTK_RESETTING, &eth->state);
1977
656e7052
JC		 1978 rtnl_unlock();
1979}
1980
8a8a9e89 1981static int mtk_free_dev(struct mtk_eth *eth)
656e7052
JC		 1982{
1983 int i;
1984
1985 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1986 if (!eth->netdev[i])
1987 continue;
8a8a9e89
SW		 1988 free_netdev(eth->netdev[i]);
1989 }
1990
1991 return 0;
1992}
656e7052 1993
8a8a9e89
SW		 1994static int mtk_unreg_dev(struct mtk_eth *eth)
1995{
1996 int i;
1997
1998 for (i = 0; i < MTK_MAC_COUNT; i++) {
1999 if (!eth->netdev[i])
2000 continue;
656e7052 2001 unregister_netdev(eth->netdev[i]);
656e7052 2002 }
8a8a9e89
SW		 2003
2004 return 0;
2005}
2006
2007static int mtk_cleanup(struct mtk_eth *eth)
2008{
2009 mtk_unreg_dev(eth);
2010 mtk_free_dev(eth);
7c78b4ad 2011 cancel_work_sync(&eth->pending_work);
656e7052
JC		 2012
2013 return 0;
2014}
2015
2016static int mtk_get_settings(struct net_device *dev,
2017 struct ethtool_cmd *cmd)
2018{
2019 struct mtk_mac *mac = netdev_priv(dev);
2020 int err;
2021
dce6fa42
SW		 2022 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2023 return -EBUSY;
2024
656e7052
JC		 2025 err = phy_read_status(mac->phy_dev);
2026 if (err)
2027 return -ENODEV;
2028
2029 return phy_ethtool_gset(mac->phy_dev, cmd);
2030}
2031
2032static int mtk_set_settings(struct net_device *dev,
2033 struct ethtool_cmd *cmd)
2034{
2035 struct mtk_mac *mac = netdev_priv(dev);
2036
2037 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
2038 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
2039 cmd->phy_address);
2040 if (!mac->phy_dev)
2041 return -ENODEV;
2042 }
2043
2044 return phy_ethtool_sset(mac->phy_dev, cmd);
2045}
2046
2047static void mtk_get_drvinfo(struct net_device *dev,
2048 struct ethtool_drvinfo *info)
2049{
2050 struct mtk_mac *mac = netdev_priv(dev);
2051
2052 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2053 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2054 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2055}
2056
2057static u32 mtk_get_msglevel(struct net_device *dev)
2058{
2059 struct mtk_mac *mac = netdev_priv(dev);
2060
2061 return mac->hw->msg_enable;
2062}
2063
2064static void mtk_set_msglevel(struct net_device *dev, u32 value)
2065{
2066 struct mtk_mac *mac = netdev_priv(dev);
2067
2068 mac->hw->msg_enable = value;
2069}
2070
2071static int mtk_nway_reset(struct net_device *dev)
2072{
2073 struct mtk_mac *mac = netdev_priv(dev);
2074
dce6fa42
SW		 2075 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2076 return -EBUSY;
2077
656e7052
JC		 2078 return genphy_restart_aneg(mac->phy_dev);
2079}
2080
2081static u32 mtk_get_link(struct net_device *dev)
2082{
2083 struct mtk_mac *mac = netdev_priv(dev);
2084 int err;
2085
dce6fa42
SW		 2086 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2087 return -EBUSY;
2088
656e7052
JC		 2089 err = genphy_update_link(mac->phy_dev);
2090 if (err)
2091 return ethtool_op_get_link(dev);
2092
2093 return mac->phy_dev->link;
2094}
2095
2096static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2097{
2098 int i;
2099
2100 switch (stringset) {
2101 case ETH_SS_STATS:
2102 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2103 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2104 data += ETH_GSTRING_LEN;
2105 }
2106 break;
2107 }
2108}
2109
2110static int mtk_get_sset_count(struct net_device *dev, int sset)
2111{
2112 switch (sset) {
2113 case ETH_SS_STATS:
2114 return ARRAY_SIZE(mtk_ethtool_stats);
2115 default:
2116 return -EOPNOTSUPP;
2117 }
2118}
2119
2120static void mtk_get_ethtool_stats(struct net_device *dev,
2121 struct ethtool_stats *stats, u64 *data)
2122{
2123 struct mtk_mac *mac = netdev_priv(dev);
2124 struct mtk_hw_stats *hwstats = mac->hw_stats;
2125 u64 *data_src, *data_dst;
2126 unsigned int start;
2127 int i;
2128
dce6fa42
SW		 2129 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2130 return;
2131
656e7052
JC		 2132 if (netif_running(dev) && netif_device_present(dev)) {
2133 if (spin_trylock(&hwstats->stats_lock)) {
2134 mtk_stats_update_mac(mac);
2135 spin_unlock(&hwstats->stats_lock);
2136 }
2137 }
2138
94d308d0
SW		 2139 data_src = (u64 *)hwstats;
2140
656e7052 2141 do {
656e7052
JC		 2142 data_dst = data;
2143 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2144
2145 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2146 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2147 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2148}
2149
7aab747e
NC		 2150static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2151 u32 *rule_locs)
2152{
2153 int ret = -EOPNOTSUPP;
2154
2155 switch (cmd->cmd) {
2156 case ETHTOOL_GRXRINGS:
2157 if (dev->features & NETIF_F_LRO) {
2158 cmd->data = MTK_MAX_RX_RING_NUM;
2159 ret = 0;
2160 }
2161 break;
2162 case ETHTOOL_GRXCLSRLCNT:
2163 if (dev->features & NETIF_F_LRO) {
2164 struct mtk_mac *mac = netdev_priv(dev);
2165
2166 cmd->rule_cnt = mac->hwlro_ip_cnt;
2167 ret = 0;
2168 }
2169 break;
2170 case ETHTOOL_GRXCLSRULE:
2171 if (dev->features & NETIF_F_LRO)
2172 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2173 break;
2174 case ETHTOOL_GRXCLSRLALL:
2175 if (dev->features & NETIF_F_LRO)
2176 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2177 rule_locs);
2178 break;
2179 default:
2180 break;
2181 }
2182
2183 return ret;
2184}
2185
2186static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2187{
2188 int ret = -EOPNOTSUPP;
2189
2190 switch (cmd->cmd) {
2191 case ETHTOOL_SRXCLSRLINS:
2192 if (dev->features & NETIF_F_LRO)
2193 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2194 break;
2195 case ETHTOOL_SRXCLSRLDEL:
2196 if (dev->features & NETIF_F_LRO)
2197 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2198 break;
2199 default:
2200 break;
2201 }
2202
2203 return ret;
2204}
2205
6a38cb15 2206static const struct ethtool_ops mtk_ethtool_ops = {
656e7052
JC		 2207 .get_settings = mtk_get_settings,
2208 .set_settings = mtk_set_settings,
2209 .get_drvinfo = mtk_get_drvinfo,
2210 .get_msglevel = mtk_get_msglevel,
2211 .set_msglevel = mtk_set_msglevel,
2212 .nway_reset = mtk_nway_reset,
2213 .get_link = mtk_get_link,
2214 .get_strings = mtk_get_strings,
2215 .get_sset_count = mtk_get_sset_count,
2216 .get_ethtool_stats = mtk_get_ethtool_stats,
7aab747e
NC		 2217 .get_rxnfc = mtk_get_rxnfc,
2218 .set_rxnfc = mtk_set_rxnfc,
656e7052
JC		 2219};
2220
2221static const struct net_device_ops mtk_netdev_ops = {
2222 .ndo_init = mtk_init,
2223 .ndo_uninit = mtk_uninit,
2224 .ndo_open = mtk_open,
2225 .ndo_stop = mtk_stop,
2226 .ndo_start_xmit = mtk_start_xmit,
2227 .ndo_set_mac_address = mtk_set_mac_address,
2228 .ndo_validate_addr = eth_validate_addr,
2229 .ndo_do_ioctl = mtk_do_ioctl,
2230 .ndo_change_mtu = eth_change_mtu,
2231 .ndo_tx_timeout = mtk_tx_timeout,
2232 .ndo_get_stats64 = mtk_get_stats64,
7aab747e
NC		 2233 .ndo_fix_features = mtk_fix_features,
2234 .ndo_set_features = mtk_set_features,
656e7052
JC		 2235#ifdef CONFIG_NET_POLL_CONTROLLER
2236 .ndo_poll_controller = mtk_poll_controller,
2237#endif
2238};
2239
2240static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2241{
2242 struct mtk_mac *mac;
2243 const __be32 *_id = of_get_property(np, "reg", NULL);
2244 int id, err;
2245
2246 if (!_id) {
2247 dev_err(eth->dev, "missing mac id\n");
2248 return -EINVAL;
2249 }
2250
2251 id = be32_to_cpup(_id);
2252 if (id >= MTK_MAC_COUNT) {
2253 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2254 return -EINVAL;
2255 }
2256
2257 if (eth->netdev[id]) {
2258 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2259 return -EINVAL;
2260 }
2261
2262 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2263 if (!eth->netdev[id]) {
2264 dev_err(eth->dev, "alloc_etherdev failed\n");
2265 return -ENOMEM;
2266 }
2267 mac = netdev_priv(eth->netdev[id]);
2268 eth->mac[id] = mac;
2269 mac->id = id;
2270 mac->hw = eth;
2271 mac->of_node = np;
656e7052 2272
ee406810
NC		 2273 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2274 mac->hwlro_ip_cnt = 0;
2275
656e7052
JC		 2276 mac->hw_stats = devm_kzalloc(eth->dev,
2277 sizeof(*mac->hw_stats),
2278 GFP_KERNEL);
2279 if (!mac->hw_stats) {
2280 dev_err(eth->dev, "failed to allocate counter memory\n");
2281 err = -ENOMEM;
2282 goto free_netdev;
2283 }
2284 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 2285 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 2286 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2287
2288 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 2289 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 2290 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2291 eth->netdev[id]->base_addr = (unsigned long)eth->base;
ee406810
NC		 2292
2293 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2294 if (eth->hwlro)
2295 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2296
656e7052
JC		 2297 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2298 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2299 eth->netdev[id]->features |= MTK_HW_FEATURES;
2300 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2301
80673029 2302 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 2303 return 0;
2304
2305free_netdev:
2306 free_netdev(eth->netdev[id]);
2307 return err;
2308}
2309
2310static int mtk_probe(struct platform_device *pdev)
2311{
2312 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2313 struct device_node *mac_np;
2314 const struct of_device_id *match;
2315 struct mtk_soc_data *soc;
2316 struct mtk_eth *eth;
2317 int err;
80673029 2318 int i;
656e7052 2319
656e7052
JC		 2320 match = of_match_device(of_mtk_match, &pdev->dev);
2321 soc = (struct mtk_soc_data *)match->data;
2322
2323 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2324 if (!eth)
2325 return -ENOMEM;
2326
549e5495 2327 eth->dev = &pdev->dev;
656e7052 2328 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 2329 if (IS_ERR(eth->base))
2330 return PTR_ERR(eth->base);
656e7052
JC		 2331
2332 spin_lock_init(&eth->page_lock);
7bc9ccec 2333 spin_lock_init(&eth->irq_lock);
656e7052
JC		 2334
2335 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2336 "mediatek,ethsys");
2337 if (IS_ERR(eth->ethsys)) {
2338 dev_err(&pdev->dev, "no ethsys regmap found\n");
2339 return PTR_ERR(eth->ethsys);
2340 }
2341
2342 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2343 "mediatek,pctl");
2344 if (IS_ERR(eth->pctl)) {
2345 dev_err(&pdev->dev, "no pctl regmap found\n");
2346 return PTR_ERR(eth->pctl);
2347 }
2348
ee406810
NC		 2349 eth->hwlro = of_property_read_bool(pdev->dev.of_node, "mediatek,hwlro");
2350
80673029
JC		 2351 for (i = 0; i < 3; i++) {
2352 eth->irq[i] = platform_get_irq(pdev, i);
2353 if (eth->irq[i] < 0) {
2354 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2355 return -ENXIO;
2356 }
656e7052 2357 }
549e5495
SW		 2358 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2359 eth->clks[i] = devm_clk_get(eth->dev,
2360 mtk_clks_source_name[i]);
2361 if (IS_ERR(eth->clks[i])) {
2362 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2363 return -EPROBE_DEFER;
2364 return -ENODEV;
2365 }
2366 }
656e7052 2367
656e7052 2368 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 2369 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 2370
2371 err = mtk_hw_init(eth);
2372 if (err)
2373 return err;
2374
2375 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2376 if (!of_device_is_compatible(mac_np,
2377 "mediatek,eth-mac"))
2378 continue;
2379
2380 if (!of_device_is_available(mac_np))
2381 continue;
2382
2383 err = mtk_add_mac(eth, mac_np);
2384 if (err)
8a8a9e89 2385 goto err_deinit_hw;
656e7052
JC		 2386 }
2387
85574dbf
SW		 2388 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2389 dev_name(eth->dev), eth);
2390 if (err)
2391 goto err_free_dev;
2392
2393 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2394 dev_name(eth->dev), eth);
2395 if (err)
2396 goto err_free_dev;
2397
2398 err = mtk_mdio_init(eth);
2399 if (err)
2400 goto err_free_dev;
2401
2402 for (i = 0; i < MTK_MAX_DEVS; i++) {
2403 if (!eth->netdev[i])
2404 continue;
2405
2406 err = register_netdev(eth->netdev[i]);
2407 if (err) {
2408 dev_err(eth->dev, "error bringing up device\n");
8a8a9e89 2409 goto err_deinit_mdio;
85574dbf
SW		 2410 } else
2411 netif_info(eth, probe, eth->netdev[i],
2412 "mediatek frame engine at 0x%08lx, irq %d\n",
2413 eth->netdev[i]->base_addr, eth->irq[0]);
2414 }
2415
656e7052
JC		 2416 /* we run 2 devices on the same DMA ring so we need a dummy device
2417 * for NAPI to work
2418 */
2419 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 2420 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2421 MTK_NAPI_WEIGHT);
2422 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 2423 MTK_NAPI_WEIGHT);
2424
2425 platform_set_drvdata(pdev, eth);
2426
2427 return 0;
2428
8a8a9e89
SW		 2429err_deinit_mdio:
2430 mtk_mdio_cleanup(eth);
656e7052 2431err_free_dev:
8a8a9e89
SW		 2432 mtk_free_dev(eth);
2433err_deinit_hw:
2434 mtk_hw_deinit(eth);
2435
656e7052
JC		 2436 return err;
2437}
2438
2439static int mtk_remove(struct platform_device *pdev)
2440{
2441 struct mtk_eth *eth = platform_get_drvdata(pdev);
79e9a414
SW		 2442 int i;
2443
2444 /* stop all devices to make sure that dma is properly shut down */
2445 for (i = 0; i < MTK_MAC_COUNT; i++) {
2446 if (!eth->netdev[i])
2447 continue;
2448 mtk_stop(eth->netdev[i]);
2449 }
656e7052 2450
bf253fb7 2451 mtk_hw_deinit(eth);
656e7052 2452
80673029 2453 netif_napi_del(&eth->tx_napi);
656e7052
JC		 2454 netif_napi_del(&eth->rx_napi);
2455 mtk_cleanup(eth);
e82f7148 2456 mtk_mdio_cleanup(eth);
656e7052
JC		 2457
2458 return 0;
2459}
2460
2461const struct of_device_id of_mtk_match[] = {
2462 { .compatible = "mediatek,mt7623-eth" },
2463 {},
2464};
2465
2466static struct platform_driver mtk_driver = {
2467 .probe = mtk_probe,
2468 .remove = mtk_remove,
2469 .driver = {
2470 .name = "mtk_soc_eth",
656e7052
JC		 2471 .of_match_table = of_mtk_match,
2472 },
2473};
2474
2475module_platform_driver(mtk_driver);
2476
2477MODULE_LICENSE("GPL");
2478MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2479MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
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