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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
53void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54{
55 __raw_writel(val, eth->base + reg);
56}
57
58u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59{
60 return __raw_readl(eth->base + reg);
61}
62
63static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64{
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77}
78
379672de
WY		 79static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
656e7052
JC		 81{
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96}
97
379672de 98static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 99{
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116}
117
118static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120{
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124}
125
126static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127{
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131}
132
133static void mtk_phy_link_adjust(struct net_device *dev)
134{
135 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
656e7052
JC		 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
08ef55c6 155 if (mac->phy_dev->duplex) {
656e7052
JC		 156 mcr |= MAC_MCR_FORCE_DPX;
157
08ef55c6
JC		 158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
656e7052
JC		 179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186}
187
188static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190{
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 210 if (!phydev) {
656e7052 211 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 212 return -ENODEV;
656e7052
JC		 213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223}
224
225static int mtk_phy_connect(struct mtk_mac *mac)
226{
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
656e7052
JC		 235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
37920fce
JC		 239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052
JC		 242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
8ca7f4fe 248 case PHY_INTERFACE_MODE_REVMII:
656e7052
JC		 249 ge_mode = 2;
250 break;
8ca7f4fe 251 case PHY_INTERFACE_MODE_RMII:
252 if (!mac->id)
253 goto err_phy;
254 ge_mode = 3;
255 break;
656e7052 256 default:
8ca7f4fe 257 goto err_phy;
656e7052
JC		 258 }
259
260 /* put the gmac into the right mode */
261 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
262 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
263 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
264 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
265
266 mtk_phy_connect_node(eth, mac, np);
267 mac->phy_dev->autoneg = AUTONEG_ENABLE;
268 mac->phy_dev->speed = 0;
269 mac->phy_dev->duplex = 0;
b2025c7c 270
271 if (of_phy_is_fixed_link(mac->of_node))
272 mac->phy_dev->supported |=
273 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
274
08ef55c6
JC		 275 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
276 SUPPORTED_Asym_Pause;
656e7052
JC		 277 mac->phy_dev->advertising = mac->phy_dev->supported |
278 ADVERTISED_Autoneg;
279 phy_start_aneg(mac->phy_dev);
280
e8c2993a 281 of_node_put(np);
282
656e7052 283 return 0;
8ca7f4fe 284
285err_phy:
286 of_node_put(np);
287 dev_err(eth->dev, "invalid phy_mode\n");
288 return -EINVAL;
656e7052
JC		 289}
290
291static int mtk_mdio_init(struct mtk_eth *eth)
292{
293 struct device_node *mii_np;
294 int err;
295
296 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
297 if (!mii_np) {
298 dev_err(eth->dev, "no %s child node found", "mdio-bus");
299 return -ENODEV;
300 }
301
302 if (!of_device_is_available(mii_np)) {
303 err = 0;
304 goto err_put_node;
305 }
306
307 eth->mii_bus = mdiobus_alloc();
308 if (!eth->mii_bus) {
309 err = -ENOMEM;
310 goto err_put_node;
311 }
312
313 eth->mii_bus->name = "mdio";
314 eth->mii_bus->read = mtk_mdio_read;
315 eth->mii_bus->write = mtk_mdio_write;
316 eth->mii_bus->priv = eth;
317 eth->mii_bus->parent = eth->dev;
318
319 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
320 err = of_mdiobus_register(eth->mii_bus, mii_np);
321 if (err)
322 goto err_free_bus;
323
324 return 0;
325
326err_free_bus:
207bdf18 327 mdiobus_free(eth->mii_bus);
656e7052
JC		 328
329err_put_node:
330 of_node_put(mii_np);
331 eth->mii_bus = NULL;
332 return err;
333}
334
335static void mtk_mdio_cleanup(struct mtk_eth *eth)
336{
337 if (!eth->mii_bus)
338 return;
339
340 mdiobus_unregister(eth->mii_bus);
341 of_node_put(eth->mii_bus->dev.of_node);
207bdf18 342 mdiobus_free(eth->mii_bus);
656e7052
JC		 343}
344
bacfd110
NC		 345static inline void mtk_irq_disable(struct mtk_eth *eth,
346 unsigned reg, u32 mask)
656e7052 347{
7bc9ccec 348 unsigned long flags;
656e7052
JC		 349 u32 val;
350
7bc9ccec 351 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 352 val = mtk_r32(eth, reg);
353 mtk_w32(eth, val & ~mask, reg);
7bc9ccec 354 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 355}
356
bacfd110
NC		 357static inline void mtk_irq_enable(struct mtk_eth *eth,
358 unsigned reg, u32 mask)
656e7052 359{
7bc9ccec 360 unsigned long flags;
656e7052
JC		 361 u32 val;
362
7bc9ccec 363 spin_lock_irqsave(&eth->irq_lock, flags);
bacfd110
NC		 364 val = mtk_r32(eth, reg);
365 mtk_w32(eth, val | mask, reg);
7bc9ccec 366 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 367}
368
369static int mtk_set_mac_address(struct net_device *dev, void *p)
370{
371 int ret = eth_mac_addr(dev, p);
372 struct mtk_mac *mac = netdev_priv(dev);
373 const char *macaddr = dev->dev_addr;
656e7052
JC		 374
375 if (ret)
376 return ret;
377
e3e9652a 378 spin_lock_bh(&mac->hw->page_lock);
656e7052
JC		 379 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
380 MTK_GDMA_MAC_ADRH(mac->id));
381 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
382 (macaddr[4] << 8) | macaddr[5],
383 MTK_GDMA_MAC_ADRL(mac->id));
e3e9652a 384 spin_unlock_bh(&mac->hw->page_lock);
656e7052
JC		 385
386 return 0;
387}
388
389void mtk_stats_update_mac(struct mtk_mac *mac)
390{
391 struct mtk_hw_stats *hw_stats = mac->hw_stats;
392 unsigned int base = MTK_GDM1_TX_GBCNT;
393 u64 stats;
394
395 base += hw_stats->reg_offset;
396
397 u64_stats_update_begin(&hw_stats->syncp);
398
399 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
400 stats = mtk_r32(mac->hw, base + 0x04);
401 if (stats)
402 hw_stats->rx_bytes += (stats << 32);
403 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
404 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
405 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
406 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
407 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
408 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
409 hw_stats->rx_flow_control_packets +=
410 mtk_r32(mac->hw, base + 0x24);
411 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
412 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
413 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
414 stats = mtk_r32(mac->hw, base + 0x34);
415 if (stats)
416 hw_stats->tx_bytes += (stats << 32);
417 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
418 u64_stats_update_end(&hw_stats->syncp);
419}
420
421static void mtk_stats_update(struct mtk_eth *eth)
422{
423 int i;
424
425 for (i = 0; i < MTK_MAC_COUNT; i++) {
426 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
427 continue;
428 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
429 mtk_stats_update_mac(eth->mac[i]);
430 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
431 }
432 }
433}
434
435static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
436 struct rtnl_link_stats64 *storage)
437{
438 struct mtk_mac *mac = netdev_priv(dev);
439 struct mtk_hw_stats *hw_stats = mac->hw_stats;
440 unsigned int start;
441
442 if (netif_running(dev) && netif_device_present(dev)) {
443 if (spin_trylock(&hw_stats->stats_lock)) {
444 mtk_stats_update_mac(mac);
445 spin_unlock(&hw_stats->stats_lock);
446 }
447 }
448
449 do {
450 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
451 storage->rx_packets = hw_stats->rx_packets;
452 storage->tx_packets = hw_stats->tx_packets;
453 storage->rx_bytes = hw_stats->rx_bytes;
454 storage->tx_bytes = hw_stats->tx_bytes;
455 storage->collisions = hw_stats->tx_collisions;
456 storage->rx_length_errors = hw_stats->rx_short_errors +
457 hw_stats->rx_long_errors;
458 storage->rx_over_errors = hw_stats->rx_overflow;
459 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
460 storage->rx_errors = hw_stats->rx_checksum_errors;
461 storage->tx_aborted_errors = hw_stats->tx_skip;
462 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
463
464 storage->tx_errors = dev->stats.tx_errors;
465 storage->rx_dropped = dev->stats.rx_dropped;
466 storage->tx_dropped = dev->stats.tx_dropped;
467
468 return storage;
469}
470
471static inline int mtk_max_frag_size(int mtu)
472{
473 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
474 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
475 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
476
477 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
478 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
479}
480
481static inline int mtk_max_buf_size(int frag_size)
482{
483 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
484 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
485
486 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
487
488 return buf_size;
489}
490
491static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
492 struct mtk_rx_dma *dma_rxd)
493{
494 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
495 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
496 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
497 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
498}
499
500/* the qdma core needs scratch memory to be setup */
501static int mtk_init_fq_dma(struct mtk_eth *eth)
502{
605e4fe4 503 dma_addr_t phy_ring_tail;
656e7052
JC		 504 int cnt = MTK_DMA_SIZE;
505 dma_addr_t dma_addr;
506 int i;
507
508 eth->scratch_ring = dma_alloc_coherent(eth->dev,
509 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 510 &eth->phy_scratch_ring,
656e7052
JC		 511 GFP_ATOMIC | __GFP_ZERO);
512 if (unlikely(!eth->scratch_ring))
513 return -ENOMEM;
514
515 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
516 GFP_KERNEL);
562c5a70
JC		 517 if (unlikely(!eth->scratch_head))
518 return -ENOMEM;
519
656e7052
JC		 520 dma_addr = dma_map_single(eth->dev,
521 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
522 DMA_FROM_DEVICE);
523 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
524 return -ENOMEM;
525
526 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 527 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 528 (sizeof(struct mtk_tx_dma) * (cnt - 1));
529
530 for (i = 0; i < cnt; i++) {
531 eth->scratch_ring[i].txd1 =
532 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
533 if (i < cnt - 1)
605e4fe4 534 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 535 ((i + 1) * sizeof(struct mtk_tx_dma)));
536 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
537 }
538
605e4fe4 539 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 540 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
541 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
542 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
543
544 return 0;
545}
546
547static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
548{
549 void *ret = ring->dma;
550
551 return ret + (desc - ring->phys);
552}
553
554static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
555 struct mtk_tx_dma *txd)
556{
557 int idx = txd - ring->dma;
558
559 return &ring->buf[idx];
560}
561
55a4e778 562static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 563{
564 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 565 dma_unmap_single(eth->dev,
656e7052
JC		 566 dma_unmap_addr(tx_buf, dma_addr0),
567 dma_unmap_len(tx_buf, dma_len0),
568 DMA_TO_DEVICE);
569 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 570 dma_unmap_page(eth->dev,
656e7052
JC		 571 dma_unmap_addr(tx_buf, dma_addr0),
572 dma_unmap_len(tx_buf, dma_len0),
573 DMA_TO_DEVICE);
574 }
575 tx_buf->flags = 0;
576 if (tx_buf->skb &&
577 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
578 dev_kfree_skb_any(tx_buf->skb);
579 tx_buf->skb = NULL;
580}
581
582static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
583 int tx_num, struct mtk_tx_ring *ring, bool gso)
584{
585 struct mtk_mac *mac = netdev_priv(dev);
586 struct mtk_eth *eth = mac->hw;
587 struct mtk_tx_dma *itxd, *txd;
588 struct mtk_tx_buf *tx_buf;
656e7052
JC		 589 dma_addr_t mapped_addr;
590 unsigned int nr_frags;
591 int i, n_desc = 1;
592 u32 txd4 = 0;
593
594 itxd = ring->next_free;
595 if (itxd == ring->last_free)
596 return -ENOMEM;
597
598 /* set the forward port */
599 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
600
601 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
602 memset(tx_buf, 0, sizeof(*tx_buf));
603
604 if (gso)
605 txd4 |= TX_DMA_TSO;
606
607 /* TX Checksum offload */
608 if (skb->ip_summed == CHECKSUM_PARTIAL)
609 txd4 |= TX_DMA_CHKSUM;
610
611 /* VLAN header offload */
612 if (skb_vlan_tag_present(skb))
613 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
614
55a4e778 615 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 616 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 617 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 618 return -ENOMEM;
619
656e7052
JC		 620 WRITE_ONCE(itxd->txd1, mapped_addr);
621 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
622 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
623 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
624
625 /* TX SG offload */
626 txd = itxd;
627 nr_frags = skb_shinfo(skb)->nr_frags;
628 for (i = 0; i < nr_frags; i++) {
629 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
630 unsigned int offset = 0;
631 int frag_size = skb_frag_size(frag);
632
633 while (frag_size) {
634 bool last_frag = false;
635 unsigned int frag_map_size;
636
637 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
638 if (txd == ring->last_free)
639 goto err_dma;
640
641 n_desc++;
642 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 643 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 644 frag_map_size,
645 DMA_TO_DEVICE);
55a4e778 646 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 647 goto err_dma;
648
649 if (i == nr_frags - 1 &&
650 (frag_size - frag_map_size) == 0)
651 last_frag = true;
652
653 WRITE_ONCE(txd->txd1, mapped_addr);
654 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
655 TX_DMA_PLEN0(frag_map_size) |
369f0453 656 last_frag * TX_DMA_LS0));
656e7052
JC		 657 WRITE_ONCE(txd->txd4, 0);
658
659 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
660 tx_buf = mtk_desc_to_tx_buf(ring, txd);
661 memset(tx_buf, 0, sizeof(*tx_buf));
662
663 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
664 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
665 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
666 frag_size -= frag_map_size;
667 offset += frag_map_size;
668 }
669 }
670
671 /* store skb to cleanup */
672 tx_buf->skb = skb;
673
674 WRITE_ONCE(itxd->txd4, txd4);
675 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
676 (!nr_frags * TX_DMA_LS0)));
677
656e7052
JC		 678 netdev_sent_queue(dev, skb->len);
679 skb_tx_timestamp(skb);
680
681 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
682 atomic_sub(n_desc, &ring->free_count);
683
684 /* make sure that all changes to the dma ring are flushed before we
685 * continue
686 */
687 wmb();
688
689 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
690 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
691
692 return 0;
693
694err_dma:
695 do {
2fae723c 696 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 697
698 /* unmap dma */
55a4e778 699 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 700
701 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
702 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
703 } while (itxd != txd);
704
705 return -ENOMEM;
706}
707
708static inline int mtk_cal_txd_req(struct sk_buff *skb)
709{
710 int i, nfrags;
711 struct skb_frag_struct *frag;
712
713 nfrags = 1;
714 if (skb_is_gso(skb)) {
715 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
716 frag = &skb_shinfo(skb)->frags[i];
717 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
718 }
719 } else {
720 nfrags += skb_shinfo(skb)->nr_frags;
721 }
722
beeb4ca4 723 return nfrags;
656e7052
JC		 724}
725
ad3cba98
JC		 726static int mtk_queue_stopped(struct mtk_eth *eth)
727{
728 int i;
729
730 for (i = 0; i < MTK_MAC_COUNT; i++) {
731 if (!eth->netdev[i])
732 continue;
733 if (netif_queue_stopped(eth->netdev[i]))
734 return 1;
735 }
736
737 return 0;
738}
739
13c822f6
JC		 740static void mtk_wake_queue(struct mtk_eth *eth)
741{
742 int i;
743
744 for (i = 0; i < MTK_MAC_COUNT; i++) {
745 if (!eth->netdev[i])
746 continue;
747 netif_wake_queue(eth->netdev[i]);
748 }
749}
750
751static void mtk_stop_queue(struct mtk_eth *eth)
752{
753 int i;
754
755 for (i = 0; i < MTK_MAC_COUNT; i++) {
756 if (!eth->netdev[i])
757 continue;
758 netif_stop_queue(eth->netdev[i]);
759 }
760}
761
656e7052
JC		 762static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
763{
764 struct mtk_mac *mac = netdev_priv(dev);
765 struct mtk_eth *eth = mac->hw;
766 struct mtk_tx_ring *ring = &eth->tx_ring;
767 struct net_device_stats *stats = &dev->stats;
768 bool gso = false;
769 int tx_num;
770
34c2e4c9
JC		 771 /* normally we can rely on the stack not calling this more than once,
772 * however we have 2 queues running on the same ring so we need to lock
773 * the ring access
774 */
e3e9652a 775 spin_lock(&eth->page_lock);
34c2e4c9 776
656e7052
JC		 777 tx_num = mtk_cal_txd_req(skb);
778 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 779 mtk_stop_queue(eth);
656e7052
JC		 780 netif_err(eth, tx_queued, dev,
781 "Tx Ring full when queue awake!\n");
e3e9652a 782 spin_unlock(&eth->page_lock);
656e7052
JC		 783 return NETDEV_TX_BUSY;
784 }
785
786 /* TSO: fill MSS info in tcp checksum field */
787 if (skb_is_gso(skb)) {
788 if (skb_cow_head(skb, 0)) {
789 netif_warn(eth, tx_err, dev,
790 "GSO expand head fail.\n");
791 goto drop;
792 }
793
794 if (skb_shinfo(skb)->gso_type &
795 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
796 gso = true;
797 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
798 }
799 }
800
801 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
802 goto drop;
803
82c6544d 804 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 805 mtk_stop_queue(eth);
82c6544d 806
e3e9652a 807 spin_unlock(&eth->page_lock);
656e7052
JC		 808
809 return NETDEV_TX_OK;
810
811drop:
e3e9652a 812 spin_unlock(&eth->page_lock);
656e7052
JC		 813 stats->tx_dropped++;
814 dev_kfree_skb(skb);
815 return NETDEV_TX_OK;
816}
817
818static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 819 struct mtk_eth *eth)
656e7052
JC		 820{
821 struct mtk_rx_ring *ring = &eth->rx_ring;
822 int idx = ring->calc_idx;
823 struct sk_buff *skb;
824 u8 *data, *new_data;
825 struct mtk_rx_dma *rxd, trxd;
826 int done = 0;
827
828 while (done < budget) {
829 struct net_device *netdev;
830 unsigned int pktlen;
831 dma_addr_t dma_addr;
832 int mac = 0;
833
834 idx = NEXT_RX_DESP_IDX(idx);
835 rxd = &ring->dma[idx];
836 data = ring->data[idx];
837
838 mtk_rx_get_desc(&trxd, rxd);
839 if (!(trxd.rxd2 & RX_DMA_DONE))
840 break;
841
842 /* find out which mac the packet come from. values start at 1 */
843 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
844 RX_DMA_FPORT_MASK;
845 mac--;
846
847 netdev = eth->netdev[mac];
848
849 /* alloc new buffer */
850 new_data = napi_alloc_frag(ring->frag_size);
851 if (unlikely(!new_data)) {
852 netdev->stats.rx_dropped++;
853 goto release_desc;
854 }
55a4e778 855 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 856 new_data + NET_SKB_PAD,
857 ring->buf_size,
858 DMA_FROM_DEVICE);
55a4e778 859 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 860 skb_free_frag(new_data);
94321a9f 861 netdev->stats.rx_dropped++;
656e7052
JC		 862 goto release_desc;
863 }
864
865 /* receive data */
866 skb = build_skb(data, ring->frag_size);
867 if (unlikely(!skb)) {
868 put_page(virt_to_head_page(new_data));
94321a9f 869 netdev->stats.rx_dropped++;
656e7052
JC		 870 goto release_desc;
871 }
872 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
873
55a4e778 874 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 875 ring->buf_size, DMA_FROM_DEVICE);
876 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
877 skb->dev = netdev;
878 skb_put(skb, pktlen);
879 if (trxd.rxd4 & RX_DMA_L4_VALID)
880 skb->ip_summed = CHECKSUM_UNNECESSARY;
881 else
882 skb_checksum_none_assert(skb);
883 skb->protocol = eth_type_trans(skb, netdev);
884
885 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
886 RX_DMA_VID(trxd.rxd3))
887 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
888 RX_DMA_VID(trxd.rxd3));
889 napi_gro_receive(napi, skb);
890
891 ring->data[idx] = new_data;
892 rxd->rxd1 = (unsigned int)dma_addr;
893
894release_desc:
895 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
896
897 ring->calc_idx = idx;
635372ad 898
656e7052
JC		 899 done++;
900 }
635372ad
SW		 901 /* make sure that all changes to the dma ring are flushed before
902 * we continue
903 */
904 wmb();
905 mtk_w32(eth, ring->calc_idx, MTK_PRX_CRX_IDX0);
656e7052
JC		 906
907 if (done < budget)
bacfd110 908 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
656e7052
JC		 909
910 return done;
911}
912
80673029 913static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 914{
915 struct mtk_tx_ring *ring = &eth->tx_ring;
916 struct mtk_tx_dma *desc;
917 struct sk_buff *skb;
918 struct mtk_tx_buf *tx_buf;
80673029 919 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 920 unsigned int bytes[MTK_MAX_DEVS];
921 u32 cpu, dma;
922 static int condition;
80673029 923 int total = 0, i;
656e7052
JC		 924
925 memset(done, 0, sizeof(done));
926 memset(bytes, 0, sizeof(bytes));
927
928 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
929 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
930
931 desc = mtk_qdma_phys_to_virt(ring, cpu);
932
933 while ((cpu != dma) && budget) {
934 u32 next_cpu = desc->txd2;
935 int mac;
936
937 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
938 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
939 break;
940
941 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
942 TX_DMA_FPORT_MASK;
943 mac--;
944
945 tx_buf = mtk_desc_to_tx_buf(ring, desc);
946 skb = tx_buf->skb;
947 if (!skb) {
948 condition = 1;
949 break;
950 }
951
952 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
953 bytes[mac] += skb->len;
954 done[mac]++;
955 budget--;
956 }
55a4e778 957 mtk_tx_unmap(eth, tx_buf);
656e7052 958
656e7052
JC		 959 ring->last_free = desc;
960 atomic_inc(&ring->free_count);
961
962 cpu = next_cpu;
963 }
964
965 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
966
967 for (i = 0; i < MTK_MAC_COUNT; i++) {
968 if (!eth->netdev[i] || !done[i])
969 continue;
970 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
971 total += done[i];
972 }
973
ad3cba98
JC		 974 if (mtk_queue_stopped(eth) &&
975 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 976 mtk_wake_queue(eth);
656e7052
JC		 977
978 return total;
979}
980
80673029 981static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 982{
80673029 983 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 984
eece71e8 985 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 986 mtk_stats_update(eth);
eece71e8
JC		 987 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
988 MTK_INT_STATUS2);
656e7052 989 }
80673029
JC		 990}
991
992static int mtk_napi_tx(struct napi_struct *napi, int budget)
993{
994 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
995 u32 status, mask;
996 int tx_done = 0;
997
998 mtk_handle_status_irq(eth);
999 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1000 tx_done = mtk_poll_tx(eth, budget);
1001
1002 if (unlikely(netif_msg_intr(eth))) {
1003 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1004 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1005 dev_info(eth->dev,
1006 "done tx %d, intr 0x%08x/0x%x\n",
1007 tx_done, status, mask);
1008 }
1009
1010 if (tx_done == budget)
1011 return budget;
1012
1013 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1014 if (status & MTK_TX_DONE_INT)
1015 return budget;
1016
1017 napi_complete(napi);
bacfd110 1018 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
80673029
JC		 1019
1020 return tx_done;
1021}
1022
1023static int mtk_napi_rx(struct napi_struct *napi, int budget)
1024{
1025 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1026 u32 status, mask;
1027 int rx_done = 0;
1028
1029 mtk_handle_status_irq(eth);
bacfd110 1030 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
80673029 1031 rx_done = mtk_poll_rx(napi, budget, eth);
656e7052
JC		 1032
1033 if (unlikely(netif_msg_intr(eth))) {
bacfd110
NC		 1034 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1035 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
80673029
JC		 1036 dev_info(eth->dev,
1037 "done rx %d, intr 0x%08x/0x%x\n",
1038 rx_done, status, mask);
656e7052
JC		 1039 }
1040
80673029 1041 if (rx_done == budget)
656e7052
JC		 1042 return budget;
1043
bacfd110 1044 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
80673029 1045 if (status & MTK_RX_DONE_INT)
656e7052
JC		 1046 return budget;
1047
1048 napi_complete(napi);
bacfd110 1049 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1050
1051 return rx_done;
1052}
1053
1054static int mtk_tx_alloc(struct mtk_eth *eth)
1055{
1056 struct mtk_tx_ring *ring = &eth->tx_ring;
1057 int i, sz = sizeof(*ring->dma);
1058
1059 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1060 GFP_KERNEL);
1061 if (!ring->buf)
1062 goto no_tx_mem;
1063
1064 ring->dma = dma_alloc_coherent(eth->dev,
1065 MTK_DMA_SIZE * sz,
1066 &ring->phys,
1067 GFP_ATOMIC | __GFP_ZERO);
1068 if (!ring->dma)
1069 goto no_tx_mem;
1070
1071 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1072 for (i = 0; i < MTK_DMA_SIZE; i++) {
1073 int next = (i + 1) % MTK_DMA_SIZE;
1074 u32 next_ptr = ring->phys + next * sz;
1075
1076 ring->dma[i].txd2 = next_ptr;
1077 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1078 }
1079
1080 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1081 ring->next_free = &ring->dma[0];
12c97c13 1082 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1083 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1084
1085 /* make sure that all changes to the dma ring are flushed before we
1086 * continue
1087 */
1088 wmb();
1089
1090 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1091 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1092 mtk_w32(eth,
1093 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1094 MTK_QTX_CRX_PTR);
1095 mtk_w32(eth,
1096 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1097 MTK_QTX_DRX_PTR);
bacfd110 1098 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
656e7052
JC		 1099
1100 return 0;
1101
1102no_tx_mem:
1103 return -ENOMEM;
1104}
1105
1106static void mtk_tx_clean(struct mtk_eth *eth)
1107{
1108 struct mtk_tx_ring *ring = &eth->tx_ring;
1109 int i;
1110
1111 if (ring->buf) {
1112 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1113 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1114 kfree(ring->buf);
1115 ring->buf = NULL;
1116 }
1117
1118 if (ring->dma) {
1119 dma_free_coherent(eth->dev,
1120 MTK_DMA_SIZE * sizeof(*ring->dma),
1121 ring->dma,
1122 ring->phys);
1123 ring->dma = NULL;
1124 }
1125}
1126
1127static int mtk_rx_alloc(struct mtk_eth *eth)
1128{
1129 struct mtk_rx_ring *ring = &eth->rx_ring;
1130 int i;
1131
1132 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1133 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1134 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1135 GFP_KERNEL);
1136 if (!ring->data)
1137 return -ENOMEM;
1138
1139 for (i = 0; i < MTK_DMA_SIZE; i++) {
1140 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1141 if (!ring->data[i])
1142 return -ENOMEM;
1143 }
1144
1145 ring->dma = dma_alloc_coherent(eth->dev,
1146 MTK_DMA_SIZE * sizeof(*ring->dma),
1147 &ring->phys,
1148 GFP_ATOMIC | __GFP_ZERO);
1149 if (!ring->dma)
1150 return -ENOMEM;
1151
1152 for (i = 0; i < MTK_DMA_SIZE; i++) {
1153 dma_addr_t dma_addr = dma_map_single(eth->dev,
1154 ring->data[i] + NET_SKB_PAD,
1155 ring->buf_size,
1156 DMA_FROM_DEVICE);
1157 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1158 return -ENOMEM;
1159 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1160
1161 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1162 }
1163 ring->calc_idx = MTK_DMA_SIZE - 1;
1164 /* make sure that all changes to the dma ring are flushed before we
1165 * continue
1166 */
1167 wmb();
1168
bacfd110
NC		 1169 mtk_w32(eth, eth->rx_ring.phys, MTK_PRX_BASE_PTR0);
1170 mtk_w32(eth, MTK_DMA_SIZE, MTK_PRX_MAX_CNT0);
1171 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_PRX_CRX_IDX0);
1172 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_PDMA_RST_IDX);
656e7052
JC		 1173
1174 return 0;
1175}
1176
1177static void mtk_rx_clean(struct mtk_eth *eth)
1178{
1179 struct mtk_rx_ring *ring = &eth->rx_ring;
1180 int i;
1181
1182 if (ring->data && ring->dma) {
1183 for (i = 0; i < MTK_DMA_SIZE; i++) {
1184 if (!ring->data[i])
1185 continue;
1186 if (!ring->dma[i].rxd1)
1187 continue;
1188 dma_unmap_single(eth->dev,
1189 ring->dma[i].rxd1,
1190 ring->buf_size,
1191 DMA_FROM_DEVICE);
1192 skb_free_frag(ring->data[i]);
1193 }
1194 kfree(ring->data);
1195 ring->data = NULL;
1196 }
1197
1198 if (ring->dma) {
1199 dma_free_coherent(eth->dev,
1200 MTK_DMA_SIZE * sizeof(*ring->dma),
1201 ring->dma,
1202 ring->phys);
1203 ring->dma = NULL;
1204 }
1205}
1206
1207/* wait for DMA to finish whatever it is doing before we start using it again */
1208static int mtk_dma_busy_wait(struct mtk_eth *eth)
1209{
1210 unsigned long t_start = jiffies;
1211
1212 while (1) {
1213 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1214 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1215 return 0;
1216 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1217 break;
1218 }
1219
1220 dev_err(eth->dev, "DMA init timeout\n");
1221 return -1;
1222}
1223
1224static int mtk_dma_init(struct mtk_eth *eth)
1225{
1226 int err;
1227
1228 if (mtk_dma_busy_wait(eth))
1229 return -EBUSY;
1230
1231 /* QDMA needs scratch memory for internal reordering of the
1232 * descriptors
1233 */
1234 err = mtk_init_fq_dma(eth);
1235 if (err)
1236 return err;
1237
1238 err = mtk_tx_alloc(eth);
1239 if (err)
1240 return err;
1241
1242 err = mtk_rx_alloc(eth);
1243 if (err)
1244 return err;
1245
1246 /* Enable random early drop and set drop threshold automatically */
1247 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1248 MTK_QDMA_FC_THRES);
1249 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1250
1251 return 0;
1252}
1253
1254static void mtk_dma_free(struct mtk_eth *eth)
1255{
1256 int i;
1257
1258 for (i = 0; i < MTK_MAC_COUNT; i++)
1259 if (eth->netdev[i])
1260 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1261 if (eth->scratch_ring) {
1262 dma_free_coherent(eth->dev,
1263 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1264 eth->scratch_ring,
1265 eth->phy_scratch_ring);
1266 eth->scratch_ring = NULL;
1267 eth->phy_scratch_ring = 0;
1268 }
656e7052
JC		 1269 mtk_tx_clean(eth);
1270 mtk_rx_clean(eth);
1271 kfree(eth->scratch_head);
1272}
1273
1274static void mtk_tx_timeout(struct net_device *dev)
1275{
1276 struct mtk_mac *mac = netdev_priv(dev);
1277 struct mtk_eth *eth = mac->hw;
1278
1279 eth->netdev[mac->id]->stats.tx_errors++;
1280 netif_err(eth, tx_err, dev,
1281 "transmit timed out\n");
7c78b4ad 1282 schedule_work(&eth->pending_work);
656e7052
JC		 1283}
1284
80673029 1285static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1286{
1287 struct mtk_eth *eth = _eth;
656e7052 1288
80673029
JC		 1289 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1290 __napi_schedule(&eth->rx_napi);
bacfd110 1291 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1292 }
656e7052 1293
80673029
JC		 1294 return IRQ_HANDLED;
1295}
1296
1297static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1298{
1299 struct mtk_eth *eth = _eth;
1300
1301 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1302 __napi_schedule(&eth->tx_napi);
bacfd110 1303 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
656e7052 1304 }
656e7052
JC		 1305
1306 return IRQ_HANDLED;
1307}
1308
1309#ifdef CONFIG_NET_POLL_CONTROLLER
1310static void mtk_poll_controller(struct net_device *dev)
1311{
1312 struct mtk_mac *mac = netdev_priv(dev);
1313 struct mtk_eth *eth = mac->hw;
656e7052 1314
bacfd110
NC		 1315 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1316 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
8186f6e3 1317 mtk_handle_irq_rx(eth->irq[2], dev);
bacfd110
NC		 1318 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1319 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1320}
1321#endif
1322
1323static int mtk_start_dma(struct mtk_eth *eth)
1324{
1325 int err;
1326
1327 err = mtk_dma_init(eth);
1328 if (err) {
1329 mtk_dma_free(eth);
1330 return err;
1331 }
1332
1333 mtk_w32(eth,
bacfd110
NC		 1334 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1335 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1336 MTK_QDMA_GLO_CFG);
1337
bacfd110
NC		 1338 mtk_w32(eth,
1339 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1340 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1341 MTK_PDMA_GLO_CFG);
1342
656e7052
JC		 1343 return 0;
1344}
1345
1346static int mtk_open(struct net_device *dev)
1347{
1348 struct mtk_mac *mac = netdev_priv(dev);
1349 struct mtk_eth *eth = mac->hw;
1350
1351 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1352 if (!atomic_read(&eth->dma_refcnt)) {
1353 int err = mtk_start_dma(eth);
1354
1355 if (err)
1356 return err;
1357
80673029 1358 napi_enable(&eth->tx_napi);
656e7052 1359 napi_enable(&eth->rx_napi);
bacfd110
NC		 1360 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1361 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
656e7052
JC		 1362 }
1363 atomic_inc(&eth->dma_refcnt);
1364
1365 phy_start(mac->phy_dev);
1366 netif_start_queue(dev);
1367
1368 return 0;
1369}
1370
1371static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1372{
656e7052
JC		 1373 u32 val;
1374 int i;
1375
1376 /* stop the dma engine */
e3e9652a 1377 spin_lock_bh(&eth->page_lock);
656e7052
JC		 1378 val = mtk_r32(eth, glo_cfg);
1379 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1380 glo_cfg);
e3e9652a 1381 spin_unlock_bh(&eth->page_lock);
656e7052
JC		 1382
1383 /* wait for dma stop */
1384 for (i = 0; i < 10; i++) {
1385 val = mtk_r32(eth, glo_cfg);
1386 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1387 msleep(20);
1388 continue;
1389 }
1390 break;
1391 }
1392}
1393
1394static int mtk_stop(struct net_device *dev)
1395{
1396 struct mtk_mac *mac = netdev_priv(dev);
1397 struct mtk_eth *eth = mac->hw;
1398
1399 netif_tx_disable(dev);
1400 phy_stop(mac->phy_dev);
1401
1402 /* only shutdown DMA if this is the last user */
1403 if (!atomic_dec_and_test(&eth->dma_refcnt))
1404 return 0;
1405
bacfd110
NC		 1406 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1407 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
80673029 1408 napi_disable(&eth->tx_napi);
656e7052
JC		 1409 napi_disable(&eth->rx_napi);
1410
1411 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1412
1413 mtk_dma_free(eth);
1414
1415 return 0;
1416}
1417
1418static int __init mtk_hw_init(struct mtk_eth *eth)
1419{
1420 int err, i;
1421
1422 /* reset the frame engine */
1423 reset_control_assert(eth->rstc);
1424 usleep_range(10, 20);
1425 reset_control_deassert(eth->rstc);
1426 usleep_range(10, 20);
1427
1428 /* Set GE2 driving and slew rate */
1429 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1430
1431 /* set GE2 TDSEL */
1432 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1433
1434 /* set GE2 TUNE */
1435 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1436
1437 /* GE1, Force 1000M/FD, FC ON */
1438 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1439
1440 /* GE2, Force 1000M/FD, FC ON */
1441 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1442
1443 /* Enable RX VLan Offloading */
1444 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1445
80673029
JC		 1446 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1447 dev_name(eth->dev), eth);
1448 if (err)
1449 return err;
1450 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
656e7052
JC		 1451 dev_name(eth->dev), eth);
1452 if (err)
1453 return err;
1454
1455 err = mtk_mdio_init(eth);
1456 if (err)
1457 return err;
1458
1459 /* disable delay and normal interrupt */
1460 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
bacfd110
NC		 1461 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1462 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1463 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
656e7052
JC		 1464 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1465 mtk_w32(eth, 0, MTK_RST_GL);
1466
1467 /* FE int grouping */
80673029
JC		 1468 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1469 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1470 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1471 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1472 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1473
1474 for (i = 0; i < 2; i++) {
1475 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1476
9c08435e 1477 /* setup the forward port to send frame to PDMA */
656e7052 1478 val &= ~0xffff;
656e7052
JC		 1479
1480 /* Enable RX checksum */
1481 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1482
1483 /* setup the mac dma */
1484 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1485 }
1486
1487 return 0;
1488}
1489
1490static int __init mtk_init(struct net_device *dev)
1491{
1492 struct mtk_mac *mac = netdev_priv(dev);
1493 struct mtk_eth *eth = mac->hw;
1494 const char *mac_addr;
1495
1496 mac_addr = of_get_mac_address(mac->of_node);
1497 if (mac_addr)
1498 ether_addr_copy(dev->dev_addr, mac_addr);
1499
1500 /* If the mac address is invalid, use random mac address */
1501 if (!is_valid_ether_addr(dev->dev_addr)) {
1502 random_ether_addr(dev->dev_addr);
1503 dev_err(eth->dev, "generated random MAC address %pM\n",
1504 dev->dev_addr);
1505 dev->addr_assign_type = NET_ADDR_RANDOM;
1506 }
1507
1508 return mtk_phy_connect(mac);
1509}
1510
1511static void mtk_uninit(struct net_device *dev)
1512{
1513 struct mtk_mac *mac = netdev_priv(dev);
1514 struct mtk_eth *eth = mac->hw;
1515
1516 phy_disconnect(mac->phy_dev);
1517 mtk_mdio_cleanup(eth);
bacfd110
NC		 1518 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1519 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
80673029
JC		 1520 free_irq(eth->irq[1], dev);
1521 free_irq(eth->irq[2], dev);
656e7052
JC		 1522}
1523
1524static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1525{
1526 struct mtk_mac *mac = netdev_priv(dev);
1527
1528 switch (cmd) {
1529 case SIOCGMIIPHY:
1530 case SIOCGMIIREG:
1531 case SIOCSMIIREG:
1532 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1533 default:
1534 break;
1535 }
1536
1537 return -EOPNOTSUPP;
1538}
1539
1540static void mtk_pending_work(struct work_struct *work)
1541{
7c78b4ad 1542 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1543 int err, i;
1544 unsigned long restart = 0;
656e7052
JC		 1545
1546 rtnl_lock();
656e7052 1547
e7d425dc
JC		 1548 /* stop all devices to make sure that dma is properly shut down */
1549 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1550 if (!eth->netdev[i])
e7d425dc
JC		 1551 continue;
1552 mtk_stop(eth->netdev[i]);
1553 __set_bit(i, &restart);
1554 }
1555
1556 /* restart DMA and enable IRQs */
1557 for (i = 0; i < MTK_MAC_COUNT; i++) {
1558 if (!test_bit(i, &restart))
1559 continue;
1560 err = mtk_open(eth->netdev[i]);
1561 if (err) {
1562 netif_alert(eth, ifup, eth->netdev[i],
1563 "Driver up/down cycle failed, closing device.\n");
1564 dev_close(eth->netdev[i]);
1565 }
656e7052
JC		 1566 }
1567 rtnl_unlock();
1568}
1569
1570static int mtk_cleanup(struct mtk_eth *eth)
1571{
1572 int i;
1573
1574 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1575 if (!eth->netdev[i])
1576 continue;
1577
1578 unregister_netdev(eth->netdev[i]);
1579 free_netdev(eth->netdev[i]);
656e7052 1580 }
7c78b4ad 1581 cancel_work_sync(&eth->pending_work);
656e7052
JC		 1582
1583 return 0;
1584}
1585
1586static int mtk_get_settings(struct net_device *dev,
1587 struct ethtool_cmd *cmd)
1588{
1589 struct mtk_mac *mac = netdev_priv(dev);
1590 int err;
1591
1592 err = phy_read_status(mac->phy_dev);
1593 if (err)
1594 return -ENODEV;
1595
1596 return phy_ethtool_gset(mac->phy_dev, cmd);
1597}
1598
1599static int mtk_set_settings(struct net_device *dev,
1600 struct ethtool_cmd *cmd)
1601{
1602 struct mtk_mac *mac = netdev_priv(dev);
1603
1604 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1605 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1606 cmd->phy_address);
1607 if (!mac->phy_dev)
1608 return -ENODEV;
1609 }
1610
1611 return phy_ethtool_sset(mac->phy_dev, cmd);
1612}
1613
1614static void mtk_get_drvinfo(struct net_device *dev,
1615 struct ethtool_drvinfo *info)
1616{
1617 struct mtk_mac *mac = netdev_priv(dev);
1618
1619 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1620 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1621 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1622}
1623
1624static u32 mtk_get_msglevel(struct net_device *dev)
1625{
1626 struct mtk_mac *mac = netdev_priv(dev);
1627
1628 return mac->hw->msg_enable;
1629}
1630
1631static void mtk_set_msglevel(struct net_device *dev, u32 value)
1632{
1633 struct mtk_mac *mac = netdev_priv(dev);
1634
1635 mac->hw->msg_enable = value;
1636}
1637
1638static int mtk_nway_reset(struct net_device *dev)
1639{
1640 struct mtk_mac *mac = netdev_priv(dev);
1641
1642 return genphy_restart_aneg(mac->phy_dev);
1643}
1644
1645static u32 mtk_get_link(struct net_device *dev)
1646{
1647 struct mtk_mac *mac = netdev_priv(dev);
1648 int err;
1649
1650 err = genphy_update_link(mac->phy_dev);
1651 if (err)
1652 return ethtool_op_get_link(dev);
1653
1654 return mac->phy_dev->link;
1655}
1656
1657static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1658{
1659 int i;
1660
1661 switch (stringset) {
1662 case ETH_SS_STATS:
1663 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1664 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1665 data += ETH_GSTRING_LEN;
1666 }
1667 break;
1668 }
1669}
1670
1671static int mtk_get_sset_count(struct net_device *dev, int sset)
1672{
1673 switch (sset) {
1674 case ETH_SS_STATS:
1675 return ARRAY_SIZE(mtk_ethtool_stats);
1676 default:
1677 return -EOPNOTSUPP;
1678 }
1679}
1680
1681static void mtk_get_ethtool_stats(struct net_device *dev,
1682 struct ethtool_stats *stats, u64 *data)
1683{
1684 struct mtk_mac *mac = netdev_priv(dev);
1685 struct mtk_hw_stats *hwstats = mac->hw_stats;
1686 u64 *data_src, *data_dst;
1687 unsigned int start;
1688 int i;
1689
1690 if (netif_running(dev) && netif_device_present(dev)) {
1691 if (spin_trylock(&hwstats->stats_lock)) {
1692 mtk_stats_update_mac(mac);
1693 spin_unlock(&hwstats->stats_lock);
1694 }
1695 }
1696
1697 do {
bacfd110 1698 data_src = (u64 *)hwstats;
656e7052
JC		 1699 data_dst = data;
1700 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1701
1702 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1703 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1704 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1705}
1706
6a38cb15 1707static const struct ethtool_ops mtk_ethtool_ops = {
656e7052
JC		 1708 .get_settings = mtk_get_settings,
1709 .set_settings = mtk_set_settings,
1710 .get_drvinfo = mtk_get_drvinfo,
1711 .get_msglevel = mtk_get_msglevel,
1712 .set_msglevel = mtk_set_msglevel,
1713 .nway_reset = mtk_nway_reset,
1714 .get_link = mtk_get_link,
1715 .get_strings = mtk_get_strings,
1716 .get_sset_count = mtk_get_sset_count,
1717 .get_ethtool_stats = mtk_get_ethtool_stats,
1718};
1719
1720static const struct net_device_ops mtk_netdev_ops = {
1721 .ndo_init = mtk_init,
1722 .ndo_uninit = mtk_uninit,
1723 .ndo_open = mtk_open,
1724 .ndo_stop = mtk_stop,
1725 .ndo_start_xmit = mtk_start_xmit,
1726 .ndo_set_mac_address = mtk_set_mac_address,
1727 .ndo_validate_addr = eth_validate_addr,
1728 .ndo_do_ioctl = mtk_do_ioctl,
1729 .ndo_change_mtu = eth_change_mtu,
1730 .ndo_tx_timeout = mtk_tx_timeout,
1731 .ndo_get_stats64 = mtk_get_stats64,
1732#ifdef CONFIG_NET_POLL_CONTROLLER
1733 .ndo_poll_controller = mtk_poll_controller,
1734#endif
1735};
1736
1737static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1738{
1739 struct mtk_mac *mac;
1740 const __be32 *_id = of_get_property(np, "reg", NULL);
1741 int id, err;
1742
1743 if (!_id) {
1744 dev_err(eth->dev, "missing mac id\n");
1745 return -EINVAL;
1746 }
1747
1748 id = be32_to_cpup(_id);
1749 if (id >= MTK_MAC_COUNT) {
1750 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1751 return -EINVAL;
1752 }
1753
1754 if (eth->netdev[id]) {
1755 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1756 return -EINVAL;
1757 }
1758
1759 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1760 if (!eth->netdev[id]) {
1761 dev_err(eth->dev, "alloc_etherdev failed\n");
1762 return -ENOMEM;
1763 }
1764 mac = netdev_priv(eth->netdev[id]);
1765 eth->mac[id] = mac;
1766 mac->id = id;
1767 mac->hw = eth;
1768 mac->of_node = np;
656e7052
JC		 1769
1770 mac->hw_stats = devm_kzalloc(eth->dev,
1771 sizeof(*mac->hw_stats),
1772 GFP_KERNEL);
1773 if (!mac->hw_stats) {
1774 dev_err(eth->dev, "failed to allocate counter memory\n");
1775 err = -ENOMEM;
1776 goto free_netdev;
1777 }
1778 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 1779 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 1780 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1781
1782 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 1783 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 1784 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1785 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1786 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1787 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1788 eth->netdev[id]->features |= MTK_HW_FEATURES;
1789 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1790
1791 err = register_netdev(eth->netdev[id]);
1792 if (err) {
1793 dev_err(eth->dev, "error bringing up device\n");
1794 goto free_netdev;
1795 }
80673029 1796 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 1797 netif_info(eth, probe, eth->netdev[id],
1798 "mediatek frame engine at 0x%08lx, irq %d\n",
80673029 1799 eth->netdev[id]->base_addr, eth->irq[0]);
656e7052
JC		 1800
1801 return 0;
1802
1803free_netdev:
1804 free_netdev(eth->netdev[id]);
1805 return err;
1806}
1807
1808static int mtk_probe(struct platform_device *pdev)
1809{
1810 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1811 struct device_node *mac_np;
1812 const struct of_device_id *match;
1813 struct mtk_soc_data *soc;
1814 struct mtk_eth *eth;
1815 int err;
80673029 1816 int i;
656e7052 1817
656e7052
JC		 1818 match = of_match_device(of_mtk_match, &pdev->dev);
1819 soc = (struct mtk_soc_data *)match->data;
1820
1821 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1822 if (!eth)
1823 return -ENOMEM;
1824
1825 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1826 if (IS_ERR(eth->base))
1827 return PTR_ERR(eth->base);
656e7052
JC		 1828
1829 spin_lock_init(&eth->page_lock);
7bc9ccec 1830 spin_lock_init(&eth->irq_lock);
656e7052
JC		 1831
1832 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1833 "mediatek,ethsys");
1834 if (IS_ERR(eth->ethsys)) {
1835 dev_err(&pdev->dev, "no ethsys regmap found\n");
1836 return PTR_ERR(eth->ethsys);
1837 }
1838
1839 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1840 "mediatek,pctl");
1841 if (IS_ERR(eth->pctl)) {
1842 dev_err(&pdev->dev, "no pctl regmap found\n");
1843 return PTR_ERR(eth->pctl);
1844 }
1845
1846 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1847 if (IS_ERR(eth->rstc)) {
1848 dev_err(&pdev->dev, "no eth reset found\n");
1849 return PTR_ERR(eth->rstc);
1850 }
1851
80673029
JC		 1852 for (i = 0; i < 3; i++) {
1853 eth->irq[i] = platform_get_irq(pdev, i);
1854 if (eth->irq[i] < 0) {
1855 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1856 return -ENXIO;
1857 }
656e7052
JC		 1858 }
1859
1860 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1861 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1862 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1863 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1864 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1865 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1866 return -ENODEV;
1867
1868 clk_prepare_enable(eth->clk_ethif);
1869 clk_prepare_enable(eth->clk_esw);
1870 clk_prepare_enable(eth->clk_gp1);
1871 clk_prepare_enable(eth->clk_gp2);
1872
1873 eth->dev = &pdev->dev;
1874 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 1875 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 1876
1877 err = mtk_hw_init(eth);
1878 if (err)
1879 return err;
1880
1881 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1882 if (!of_device_is_compatible(mac_np,
1883 "mediatek,eth-mac"))
1884 continue;
1885
1886 if (!of_device_is_available(mac_np))
1887 continue;
1888
1889 err = mtk_add_mac(eth, mac_np);
1890 if (err)
1891 goto err_free_dev;
1892 }
1893
1894 /* we run 2 devices on the same DMA ring so we need a dummy device
1895 * for NAPI to work
1896 */
1897 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 1898 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1899 MTK_NAPI_WEIGHT);
1900 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 1901 MTK_NAPI_WEIGHT);
1902
1903 platform_set_drvdata(pdev, eth);
1904
1905 return 0;
1906
1907err_free_dev:
1908 mtk_cleanup(eth);
1909 return err;
1910}
1911
1912static int mtk_remove(struct platform_device *pdev)
1913{
1914 struct mtk_eth *eth = platform_get_drvdata(pdev);
1915
1916 clk_disable_unprepare(eth->clk_ethif);
1917 clk_disable_unprepare(eth->clk_esw);
1918 clk_disable_unprepare(eth->clk_gp1);
1919 clk_disable_unprepare(eth->clk_gp2);
1920
80673029 1921 netif_napi_del(&eth->tx_napi);
656e7052
JC		 1922 netif_napi_del(&eth->rx_napi);
1923 mtk_cleanup(eth);
656e7052
JC		 1924
1925 return 0;
1926}
1927
1928const struct of_device_id of_mtk_match[] = {
1929 { .compatible = "mediatek,mt7623-eth" },
1930 {},
1931};
1932
1933static struct platform_driver mtk_driver = {
1934 .probe = mtk_probe,
1935 .remove = mtk_remove,
1936 .driver = {
1937 .name = "mtk_soc_eth",
656e7052
JC		 1938 .of_match_table = of_mtk_match,
1939 },
1940};
1941
1942module_platform_driver(mtk_driver);
1943
1944MODULE_LICENSE("GPL");
1945MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1946MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
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