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bridge: re-introduce 'fix parsing of MLDv2 reports'
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
CommitLineData
656e7052
JC		 1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/of_device.h>
16#include <linux/of_mdio.h>
17#include <linux/of_net.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20#include <linux/clk.h>
21#include <linux/if_vlan.h>
22#include <linux/reset.h>
23#include <linux/tcp.h>
24
25#include "mtk_eth_soc.h"
26
27static int mtk_msg_level = -1;
28module_param_named(msg_level, mtk_msg_level, int, 0);
29MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31#define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34/* strings used by ethtool */
35static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38} mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51};
52
53void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54{
55 __raw_writel(val, eth->base + reg);
56}
57
58u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59{
60 return __raw_readl(eth->base + reg);
61}
62
63static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64{
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77}
78
379672de
WY		 79static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
656e7052
JC		 81{
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96}
97
379672de 98static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
656e7052
JC		 99{
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116}
117
118static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120{
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124}
125
126static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127{
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131}
132
133static void mtk_phy_link_adjust(struct net_device *dev)
134{
135 struct mtk_mac *mac = netdev_priv(dev);
08ef55c6
JC		 136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
656e7052
JC		 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
08ef55c6 155 if (mac->phy_dev->duplex) {
656e7052
JC		 156 mcr |= MAC_MCR_FORCE_DPX;
157
08ef55c6
JC		 158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
656e7052
JC		 179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186}
187
188static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190{
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
977bc20c 210 if (!phydev) {
656e7052 211 dev_err(eth->dev, "could not connect to PHY\n");
977bc20c 212 return -ENODEV;
656e7052
JC		 213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223}
224
225static int mtk_phy_connect(struct mtk_mac *mac)
226{
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
0c72c50f
JC		 232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
656e7052
JC		 235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
37920fce
JC		 239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
656e7052
JC		 242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
8ca7f4fe 248 case PHY_INTERFACE_MODE_REVMII:
656e7052
JC		 249 ge_mode = 2;
250 break;
8ca7f4fe 251 case PHY_INTERFACE_MODE_RMII:
252 if (!mac->id)
253 goto err_phy;
254 ge_mode = 3;
255 break;
656e7052 256 default:
8ca7f4fe 257 goto err_phy;
656e7052
JC		 258 }
259
260 /* put the gmac into the right mode */
261 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
262 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
263 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
264 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
265
266 mtk_phy_connect_node(eth, mac, np);
267 mac->phy_dev->autoneg = AUTONEG_ENABLE;
268 mac->phy_dev->speed = 0;
269 mac->phy_dev->duplex = 0;
b2025c7c 270
271 if (of_phy_is_fixed_link(mac->of_node))
272 mac->phy_dev->supported |=
273 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
274
08ef55c6
JC		 275 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
276 SUPPORTED_Asym_Pause;
656e7052
JC		 277 mac->phy_dev->advertising = mac->phy_dev->supported |
278 ADVERTISED_Autoneg;
279 phy_start_aneg(mac->phy_dev);
280
e8c2993a 281 of_node_put(np);
282
656e7052 283 return 0;
8ca7f4fe 284
285err_phy:
286 of_node_put(np);
287 dev_err(eth->dev, "invalid phy_mode\n");
288 return -EINVAL;
656e7052
JC		 289}
290
291static int mtk_mdio_init(struct mtk_eth *eth)
292{
293 struct device_node *mii_np;
294 int err;
295
296 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
297 if (!mii_np) {
298 dev_err(eth->dev, "no %s child node found", "mdio-bus");
299 return -ENODEV;
300 }
301
302 if (!of_device_is_available(mii_np)) {
303 err = 0;
304 goto err_put_node;
305 }
306
307 eth->mii_bus = mdiobus_alloc();
308 if (!eth->mii_bus) {
309 err = -ENOMEM;
310 goto err_put_node;
311 }
312
313 eth->mii_bus->name = "mdio";
314 eth->mii_bus->read = mtk_mdio_read;
315 eth->mii_bus->write = mtk_mdio_write;
316 eth->mii_bus->priv = eth;
317 eth->mii_bus->parent = eth->dev;
318
319 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
320 err = of_mdiobus_register(eth->mii_bus, mii_np);
321 if (err)
322 goto err_free_bus;
323
324 return 0;
325
326err_free_bus:
207bdf18 327 mdiobus_free(eth->mii_bus);
656e7052
JC		 328
329err_put_node:
330 of_node_put(mii_np);
331 eth->mii_bus = NULL;
332 return err;
333}
334
335static void mtk_mdio_cleanup(struct mtk_eth *eth)
336{
337 if (!eth->mii_bus)
338 return;
339
340 mdiobus_unregister(eth->mii_bus);
341 of_node_put(eth->mii_bus->dev.of_node);
207bdf18 342 mdiobus_free(eth->mii_bus);
656e7052
JC		 343}
344
345static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
346{
7bc9ccec 347 unsigned long flags;
656e7052
JC		 348 u32 val;
349
7bc9ccec 350 spin_lock_irqsave(&eth->irq_lock, flags);
656e7052
JC		 351 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
352 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
7bc9ccec 353 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 354}
355
356static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
357{
7bc9ccec 358 unsigned long flags;
656e7052
JC		 359 u32 val;
360
7bc9ccec 361 spin_lock_irqsave(&eth->irq_lock, flags);
656e7052
JC		 362 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
363 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
7bc9ccec 364 spin_unlock_irqrestore(&eth->irq_lock, flags);
656e7052
JC		 365}
366
367static int mtk_set_mac_address(struct net_device *dev, void *p)
368{
369 int ret = eth_mac_addr(dev, p);
370 struct mtk_mac *mac = netdev_priv(dev);
371 const char *macaddr = dev->dev_addr;
372 unsigned long flags;
373
374 if (ret)
375 return ret;
376
377 spin_lock_irqsave(&mac->hw->page_lock, flags);
378 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
379 MTK_GDMA_MAC_ADRH(mac->id));
380 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
381 (macaddr[4] << 8) | macaddr[5],
382 MTK_GDMA_MAC_ADRL(mac->id));
383 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
384
385 return 0;
386}
387
388void mtk_stats_update_mac(struct mtk_mac *mac)
389{
390 struct mtk_hw_stats *hw_stats = mac->hw_stats;
391 unsigned int base = MTK_GDM1_TX_GBCNT;
392 u64 stats;
393
394 base += hw_stats->reg_offset;
395
396 u64_stats_update_begin(&hw_stats->syncp);
397
398 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
399 stats = mtk_r32(mac->hw, base + 0x04);
400 if (stats)
401 hw_stats->rx_bytes += (stats << 32);
402 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
403 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
404 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
405 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
406 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
407 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
408 hw_stats->rx_flow_control_packets +=
409 mtk_r32(mac->hw, base + 0x24);
410 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
411 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
412 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
413 stats = mtk_r32(mac->hw, base + 0x34);
414 if (stats)
415 hw_stats->tx_bytes += (stats << 32);
416 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
417 u64_stats_update_end(&hw_stats->syncp);
418}
419
420static void mtk_stats_update(struct mtk_eth *eth)
421{
422 int i;
423
424 for (i = 0; i < MTK_MAC_COUNT; i++) {
425 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
426 continue;
427 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
428 mtk_stats_update_mac(eth->mac[i]);
429 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
430 }
431 }
432}
433
434static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
435 struct rtnl_link_stats64 *storage)
436{
437 struct mtk_mac *mac = netdev_priv(dev);
438 struct mtk_hw_stats *hw_stats = mac->hw_stats;
439 unsigned int start;
440
441 if (netif_running(dev) && netif_device_present(dev)) {
442 if (spin_trylock(&hw_stats->stats_lock)) {
443 mtk_stats_update_mac(mac);
444 spin_unlock(&hw_stats->stats_lock);
445 }
446 }
447
448 do {
449 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
450 storage->rx_packets = hw_stats->rx_packets;
451 storage->tx_packets = hw_stats->tx_packets;
452 storage->rx_bytes = hw_stats->rx_bytes;
453 storage->tx_bytes = hw_stats->tx_bytes;
454 storage->collisions = hw_stats->tx_collisions;
455 storage->rx_length_errors = hw_stats->rx_short_errors +
456 hw_stats->rx_long_errors;
457 storage->rx_over_errors = hw_stats->rx_overflow;
458 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
459 storage->rx_errors = hw_stats->rx_checksum_errors;
460 storage->tx_aborted_errors = hw_stats->tx_skip;
461 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
462
463 storage->tx_errors = dev->stats.tx_errors;
464 storage->rx_dropped = dev->stats.rx_dropped;
465 storage->tx_dropped = dev->stats.tx_dropped;
466
467 return storage;
468}
469
470static inline int mtk_max_frag_size(int mtu)
471{
472 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
473 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
474 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
475
476 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
477 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
478}
479
480static inline int mtk_max_buf_size(int frag_size)
481{
482 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
483 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
484
485 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
486
487 return buf_size;
488}
489
490static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
491 struct mtk_rx_dma *dma_rxd)
492{
493 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
494 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
495 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
496 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
497}
498
499/* the qdma core needs scratch memory to be setup */
500static int mtk_init_fq_dma(struct mtk_eth *eth)
501{
605e4fe4 502 dma_addr_t phy_ring_tail;
656e7052
JC		 503 int cnt = MTK_DMA_SIZE;
504 dma_addr_t dma_addr;
505 int i;
506
507 eth->scratch_ring = dma_alloc_coherent(eth->dev,
508 cnt * sizeof(struct mtk_tx_dma),
605e4fe4 509 &eth->phy_scratch_ring,
656e7052
JC		 510 GFP_ATOMIC | __GFP_ZERO);
511 if (unlikely(!eth->scratch_ring))
512 return -ENOMEM;
513
514 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
515 GFP_KERNEL);
562c5a70
JC		 516 if (unlikely(!eth->scratch_head))
517 return -ENOMEM;
518
656e7052
JC		 519 dma_addr = dma_map_single(eth->dev,
520 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
521 DMA_FROM_DEVICE);
522 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
523 return -ENOMEM;
524
525 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
605e4fe4 526 phy_ring_tail = eth->phy_scratch_ring +
656e7052
JC		 527 (sizeof(struct mtk_tx_dma) * (cnt - 1));
528
529 for (i = 0; i < cnt; i++) {
530 eth->scratch_ring[i].txd1 =
531 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
532 if (i < cnt - 1)
605e4fe4 533 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
656e7052
JC		 534 ((i + 1) * sizeof(struct mtk_tx_dma)));
535 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
536 }
537
605e4fe4 538 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
656e7052
JC		 539 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
540 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
541 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
542
543 return 0;
544}
545
546static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
547{
548 void *ret = ring->dma;
549
550 return ret + (desc - ring->phys);
551}
552
553static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
554 struct mtk_tx_dma *txd)
555{
556 int idx = txd - ring->dma;
557
558 return &ring->buf[idx];
559}
560
55a4e778 561static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
656e7052
JC		 562{
563 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
55a4e778 564 dma_unmap_single(eth->dev,
656e7052
JC		 565 dma_unmap_addr(tx_buf, dma_addr0),
566 dma_unmap_len(tx_buf, dma_len0),
567 DMA_TO_DEVICE);
568 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
55a4e778 569 dma_unmap_page(eth->dev,
656e7052
JC		 570 dma_unmap_addr(tx_buf, dma_addr0),
571 dma_unmap_len(tx_buf, dma_len0),
572 DMA_TO_DEVICE);
573 }
574 tx_buf->flags = 0;
575 if (tx_buf->skb &&
576 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
577 dev_kfree_skb_any(tx_buf->skb);
578 tx_buf->skb = NULL;
579}
580
581static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
582 int tx_num, struct mtk_tx_ring *ring, bool gso)
583{
584 struct mtk_mac *mac = netdev_priv(dev);
585 struct mtk_eth *eth = mac->hw;
586 struct mtk_tx_dma *itxd, *txd;
587 struct mtk_tx_buf *tx_buf;
656e7052
JC		 588 dma_addr_t mapped_addr;
589 unsigned int nr_frags;
590 int i, n_desc = 1;
591 u32 txd4 = 0;
592
593 itxd = ring->next_free;
594 if (itxd == ring->last_free)
595 return -ENOMEM;
596
597 /* set the forward port */
598 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
599
600 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
601 memset(tx_buf, 0, sizeof(*tx_buf));
602
603 if (gso)
604 txd4 |= TX_DMA_TSO;
605
606 /* TX Checksum offload */
607 if (skb->ip_summed == CHECKSUM_PARTIAL)
608 txd4 |= TX_DMA_CHKSUM;
609
610 /* VLAN header offload */
611 if (skb_vlan_tag_present(skb))
612 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
613
55a4e778 614 mapped_addr = dma_map_single(eth->dev, skb->data,
656e7052 615 skb_headlen(skb), DMA_TO_DEVICE);
55a4e778 616 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 617 return -ENOMEM;
618
656e7052
JC		 619 WRITE_ONCE(itxd->txd1, mapped_addr);
620 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
621 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
622 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
623
624 /* TX SG offload */
625 txd = itxd;
626 nr_frags = skb_shinfo(skb)->nr_frags;
627 for (i = 0; i < nr_frags; i++) {
628 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
629 unsigned int offset = 0;
630 int frag_size = skb_frag_size(frag);
631
632 while (frag_size) {
633 bool last_frag = false;
634 unsigned int frag_map_size;
635
636 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
637 if (txd == ring->last_free)
638 goto err_dma;
639
640 n_desc++;
641 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
55a4e778 642 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
656e7052
JC		 643 frag_map_size,
644 DMA_TO_DEVICE);
55a4e778 645 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
656e7052
JC		 646 goto err_dma;
647
648 if (i == nr_frags - 1 &&
649 (frag_size - frag_map_size) == 0)
650 last_frag = true;
651
652 WRITE_ONCE(txd->txd1, mapped_addr);
653 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
654 TX_DMA_PLEN0(frag_map_size) |
369f0453 655 last_frag * TX_DMA_LS0));
656e7052
JC		 656 WRITE_ONCE(txd->txd4, 0);
657
658 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
659 tx_buf = mtk_desc_to_tx_buf(ring, txd);
660 memset(tx_buf, 0, sizeof(*tx_buf));
661
662 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
663 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
664 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
665 frag_size -= frag_map_size;
666 offset += frag_map_size;
667 }
668 }
669
670 /* store skb to cleanup */
671 tx_buf->skb = skb;
672
673 WRITE_ONCE(itxd->txd4, txd4);
674 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
675 (!nr_frags * TX_DMA_LS0)));
676
656e7052
JC		 677 netdev_sent_queue(dev, skb->len);
678 skb_tx_timestamp(skb);
679
680 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
681 atomic_sub(n_desc, &ring->free_count);
682
683 /* make sure that all changes to the dma ring are flushed before we
684 * continue
685 */
686 wmb();
687
688 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
689 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
690
691 return 0;
692
693err_dma:
694 do {
2fae723c 695 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
656e7052
JC		 696
697 /* unmap dma */
55a4e778 698 mtk_tx_unmap(eth, tx_buf);
656e7052
JC		 699
700 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
701 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
702 } while (itxd != txd);
703
704 return -ENOMEM;
705}
706
707static inline int mtk_cal_txd_req(struct sk_buff *skb)
708{
709 int i, nfrags;
710 struct skb_frag_struct *frag;
711
712 nfrags = 1;
713 if (skb_is_gso(skb)) {
714 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
715 frag = &skb_shinfo(skb)->frags[i];
716 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
717 }
718 } else {
719 nfrags += skb_shinfo(skb)->nr_frags;
720 }
721
beeb4ca4 722 return nfrags;
656e7052
JC		 723}
724
ad3cba98
JC		 725static int mtk_queue_stopped(struct mtk_eth *eth)
726{
727 int i;
728
729 for (i = 0; i < MTK_MAC_COUNT; i++) {
730 if (!eth->netdev[i])
731 continue;
732 if (netif_queue_stopped(eth->netdev[i]))
733 return 1;
734 }
735
736 return 0;
737}
738
13c822f6
JC		 739static void mtk_wake_queue(struct mtk_eth *eth)
740{
741 int i;
742
743 for (i = 0; i < MTK_MAC_COUNT; i++) {
744 if (!eth->netdev[i])
745 continue;
746 netif_wake_queue(eth->netdev[i]);
747 }
748}
749
750static void mtk_stop_queue(struct mtk_eth *eth)
751{
752 int i;
753
754 for (i = 0; i < MTK_MAC_COUNT; i++) {
755 if (!eth->netdev[i])
756 continue;
757 netif_stop_queue(eth->netdev[i]);
758 }
759}
760
656e7052
JC		 761static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
762{
763 struct mtk_mac *mac = netdev_priv(dev);
764 struct mtk_eth *eth = mac->hw;
765 struct mtk_tx_ring *ring = &eth->tx_ring;
766 struct net_device_stats *stats = &dev->stats;
34c2e4c9 767 unsigned long flags;
656e7052
JC		 768 bool gso = false;
769 int tx_num;
770
34c2e4c9
JC		 771 /* normally we can rely on the stack not calling this more than once,
772 * however we have 2 queues running on the same ring so we need to lock
773 * the ring access
774 */
775 spin_lock_irqsave(&eth->page_lock, flags);
776
656e7052
JC		 777 tx_num = mtk_cal_txd_req(skb);
778 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
13c822f6 779 mtk_stop_queue(eth);
656e7052
JC		 780 netif_err(eth, tx_queued, dev,
781 "Tx Ring full when queue awake!\n");
34c2e4c9 782 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 783 return NETDEV_TX_BUSY;
784 }
785
786 /* TSO: fill MSS info in tcp checksum field */
787 if (skb_is_gso(skb)) {
788 if (skb_cow_head(skb, 0)) {
789 netif_warn(eth, tx_err, dev,
790 "GSO expand head fail.\n");
791 goto drop;
792 }
793
794 if (skb_shinfo(skb)->gso_type &
795 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
796 gso = true;
797 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
798 }
799 }
800
801 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
802 goto drop;
803
82c6544d 804 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
13c822f6 805 mtk_stop_queue(eth);
82c6544d 806
34c2e4c9 807 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 808
809 return NETDEV_TX_OK;
810
811drop:
34c2e4c9 812 spin_unlock_irqrestore(&eth->page_lock, flags);
656e7052
JC		 813 stats->tx_dropped++;
814 dev_kfree_skb(skb);
815 return NETDEV_TX_OK;
816}
817
818static int mtk_poll_rx(struct napi_struct *napi, int budget,
eece71e8 819 struct mtk_eth *eth)
656e7052
JC		 820{
821 struct mtk_rx_ring *ring = &eth->rx_ring;
822 int idx = ring->calc_idx;
823 struct sk_buff *skb;
824 u8 *data, *new_data;
825 struct mtk_rx_dma *rxd, trxd;
826 int done = 0;
827
828 while (done < budget) {
829 struct net_device *netdev;
830 unsigned int pktlen;
831 dma_addr_t dma_addr;
832 int mac = 0;
833
834 idx = NEXT_RX_DESP_IDX(idx);
835 rxd = &ring->dma[idx];
836 data = ring->data[idx];
837
838 mtk_rx_get_desc(&trxd, rxd);
839 if (!(trxd.rxd2 & RX_DMA_DONE))
840 break;
841
842 /* find out which mac the packet come from. values start at 1 */
843 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
844 RX_DMA_FPORT_MASK;
845 mac--;
846
847 netdev = eth->netdev[mac];
848
849 /* alloc new buffer */
850 new_data = napi_alloc_frag(ring->frag_size);
851 if (unlikely(!new_data)) {
852 netdev->stats.rx_dropped++;
853 goto release_desc;
854 }
55a4e778 855 dma_addr = dma_map_single(eth->dev,
656e7052
JC		 856 new_data + NET_SKB_PAD,
857 ring->buf_size,
858 DMA_FROM_DEVICE);
55a4e778 859 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
656e7052 860 skb_free_frag(new_data);
94321a9f 861 netdev->stats.rx_dropped++;
656e7052
JC		 862 goto release_desc;
863 }
864
865 /* receive data */
866 skb = build_skb(data, ring->frag_size);
867 if (unlikely(!skb)) {
868 put_page(virt_to_head_page(new_data));
94321a9f 869 netdev->stats.rx_dropped++;
656e7052
JC		 870 goto release_desc;
871 }
872 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
873
55a4e778 874 dma_unmap_single(eth->dev, trxd.rxd1,
656e7052
JC		 875 ring->buf_size, DMA_FROM_DEVICE);
876 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
877 skb->dev = netdev;
878 skb_put(skb, pktlen);
879 if (trxd.rxd4 & RX_DMA_L4_VALID)
880 skb->ip_summed = CHECKSUM_UNNECESSARY;
881 else
882 skb_checksum_none_assert(skb);
883 skb->protocol = eth_type_trans(skb, netdev);
884
885 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
886 RX_DMA_VID(trxd.rxd3))
887 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
888 RX_DMA_VID(trxd.rxd3));
889 napi_gro_receive(napi, skb);
890
891 ring->data[idx] = new_data;
892 rxd->rxd1 = (unsigned int)dma_addr;
893
894release_desc:
895 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
896
897 ring->calc_idx = idx;
898 /* make sure that all changes to the dma ring are flushed before
899 * we continue
900 */
901 wmb();
902 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
903 done++;
904 }
905
906 if (done < budget)
eece71e8 907 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
656e7052
JC		 908
909 return done;
910}
911
80673029 912static int mtk_poll_tx(struct mtk_eth *eth, int budget)
656e7052
JC		 913{
914 struct mtk_tx_ring *ring = &eth->tx_ring;
915 struct mtk_tx_dma *desc;
916 struct sk_buff *skb;
917 struct mtk_tx_buf *tx_buf;
80673029 918 unsigned int done[MTK_MAX_DEVS];
656e7052
JC		 919 unsigned int bytes[MTK_MAX_DEVS];
920 u32 cpu, dma;
921 static int condition;
80673029 922 int total = 0, i;
656e7052
JC		 923
924 memset(done, 0, sizeof(done));
925 memset(bytes, 0, sizeof(bytes));
926
927 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
928 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
929
930 desc = mtk_qdma_phys_to_virt(ring, cpu);
931
932 while ((cpu != dma) && budget) {
933 u32 next_cpu = desc->txd2;
934 int mac;
935
936 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
937 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
938 break;
939
940 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
941 TX_DMA_FPORT_MASK;
942 mac--;
943
944 tx_buf = mtk_desc_to_tx_buf(ring, desc);
945 skb = tx_buf->skb;
946 if (!skb) {
947 condition = 1;
948 break;
949 }
950
951 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
952 bytes[mac] += skb->len;
953 done[mac]++;
954 budget--;
955 }
55a4e778 956 mtk_tx_unmap(eth, tx_buf);
656e7052 957
656e7052
JC		 958 ring->last_free = desc;
959 atomic_inc(&ring->free_count);
960
961 cpu = next_cpu;
962 }
963
964 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
965
966 for (i = 0; i < MTK_MAC_COUNT; i++) {
967 if (!eth->netdev[i] || !done[i])
968 continue;
969 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
970 total += done[i];
971 }
972
ad3cba98
JC		 973 if (mtk_queue_stopped(eth) &&
974 (atomic_read(&ring->free_count) > ring->thresh))
13c822f6 975 mtk_wake_queue(eth);
656e7052
JC		 976
977 return total;
978}
979
80673029 980static void mtk_handle_status_irq(struct mtk_eth *eth)
656e7052 981{
80673029 982 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
656e7052 983
eece71e8 984 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
656e7052 985 mtk_stats_update(eth);
eece71e8
JC		 986 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
987 MTK_INT_STATUS2);
656e7052 988 }
80673029
JC		 989}
990
991static int mtk_napi_tx(struct napi_struct *napi, int budget)
992{
993 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
994 u32 status, mask;
995 int tx_done = 0;
996
997 mtk_handle_status_irq(eth);
998 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
999 tx_done = mtk_poll_tx(eth, budget);
1000
1001 if (unlikely(netif_msg_intr(eth))) {
1002 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1003 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1004 dev_info(eth->dev,
1005 "done tx %d, intr 0x%08x/0x%x\n",
1006 tx_done, status, mask);
1007 }
1008
1009 if (tx_done == budget)
1010 return budget;
1011
1012 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1013 if (status & MTK_TX_DONE_INT)
1014 return budget;
1015
1016 napi_complete(napi);
1017 mtk_irq_enable(eth, MTK_TX_DONE_INT);
1018
1019 return tx_done;
1020}
1021
1022static int mtk_napi_rx(struct napi_struct *napi, int budget)
1023{
1024 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1025 u32 status, mask;
1026 int rx_done = 0;
1027
1028 mtk_handle_status_irq(eth);
1029 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
1030 rx_done = mtk_poll_rx(napi, budget, eth);
656e7052
JC		 1031
1032 if (unlikely(netif_msg_intr(eth))) {
80673029 1033 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
656e7052 1034 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
80673029
JC		 1035 dev_info(eth->dev,
1036 "done rx %d, intr 0x%08x/0x%x\n",
1037 rx_done, status, mask);
656e7052
JC		 1038 }
1039
80673029 1040 if (rx_done == budget)
656e7052
JC		 1041 return budget;
1042
1043 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
80673029 1044 if (status & MTK_RX_DONE_INT)
656e7052
JC		 1045 return budget;
1046
1047 napi_complete(napi);
80673029 1048 mtk_irq_enable(eth, MTK_RX_DONE_INT);
656e7052
JC		 1049
1050 return rx_done;
1051}
1052
1053static int mtk_tx_alloc(struct mtk_eth *eth)
1054{
1055 struct mtk_tx_ring *ring = &eth->tx_ring;
1056 int i, sz = sizeof(*ring->dma);
1057
1058 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1059 GFP_KERNEL);
1060 if (!ring->buf)
1061 goto no_tx_mem;
1062
1063 ring->dma = dma_alloc_coherent(eth->dev,
1064 MTK_DMA_SIZE * sz,
1065 &ring->phys,
1066 GFP_ATOMIC | __GFP_ZERO);
1067 if (!ring->dma)
1068 goto no_tx_mem;
1069
1070 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1071 for (i = 0; i < MTK_DMA_SIZE; i++) {
1072 int next = (i + 1) % MTK_DMA_SIZE;
1073 u32 next_ptr = ring->phys + next * sz;
1074
1075 ring->dma[i].txd2 = next_ptr;
1076 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1077 }
1078
1079 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1080 ring->next_free = &ring->dma[0];
12c97c13 1081 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
04698ccc 1082 ring->thresh = MAX_SKB_FRAGS;
656e7052
JC		 1083
1084 /* make sure that all changes to the dma ring are flushed before we
1085 * continue
1086 */
1087 wmb();
1088
1089 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1090 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1091 mtk_w32(eth,
1092 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1093 MTK_QTX_CRX_PTR);
1094 mtk_w32(eth,
1095 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1096 MTK_QTX_DRX_PTR);
1097
1098 return 0;
1099
1100no_tx_mem:
1101 return -ENOMEM;
1102}
1103
1104static void mtk_tx_clean(struct mtk_eth *eth)
1105{
1106 struct mtk_tx_ring *ring = &eth->tx_ring;
1107 int i;
1108
1109 if (ring->buf) {
1110 for (i = 0; i < MTK_DMA_SIZE; i++)
55a4e778 1111 mtk_tx_unmap(eth, &ring->buf[i]);
656e7052
JC		 1112 kfree(ring->buf);
1113 ring->buf = NULL;
1114 }
1115
1116 if (ring->dma) {
1117 dma_free_coherent(eth->dev,
1118 MTK_DMA_SIZE * sizeof(*ring->dma),
1119 ring->dma,
1120 ring->phys);
1121 ring->dma = NULL;
1122 }
1123}
1124
1125static int mtk_rx_alloc(struct mtk_eth *eth)
1126{
1127 struct mtk_rx_ring *ring = &eth->rx_ring;
1128 int i;
1129
1130 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1131 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1132 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1133 GFP_KERNEL);
1134 if (!ring->data)
1135 return -ENOMEM;
1136
1137 for (i = 0; i < MTK_DMA_SIZE; i++) {
1138 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1139 if (!ring->data[i])
1140 return -ENOMEM;
1141 }
1142
1143 ring->dma = dma_alloc_coherent(eth->dev,
1144 MTK_DMA_SIZE * sizeof(*ring->dma),
1145 &ring->phys,
1146 GFP_ATOMIC | __GFP_ZERO);
1147 if (!ring->dma)
1148 return -ENOMEM;
1149
1150 for (i = 0; i < MTK_DMA_SIZE; i++) {
1151 dma_addr_t dma_addr = dma_map_single(eth->dev,
1152 ring->data[i] + NET_SKB_PAD,
1153 ring->buf_size,
1154 DMA_FROM_DEVICE);
1155 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1156 return -ENOMEM;
1157 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1158
1159 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1160 }
1161 ring->calc_idx = MTK_DMA_SIZE - 1;
1162 /* make sure that all changes to the dma ring are flushed before we
1163 * continue
1164 */
1165 wmb();
1166
1167 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1168 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1169 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1170 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1171 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1172
1173 return 0;
1174}
1175
1176static void mtk_rx_clean(struct mtk_eth *eth)
1177{
1178 struct mtk_rx_ring *ring = &eth->rx_ring;
1179 int i;
1180
1181 if (ring->data && ring->dma) {
1182 for (i = 0; i < MTK_DMA_SIZE; i++) {
1183 if (!ring->data[i])
1184 continue;
1185 if (!ring->dma[i].rxd1)
1186 continue;
1187 dma_unmap_single(eth->dev,
1188 ring->dma[i].rxd1,
1189 ring->buf_size,
1190 DMA_FROM_DEVICE);
1191 skb_free_frag(ring->data[i]);
1192 }
1193 kfree(ring->data);
1194 ring->data = NULL;
1195 }
1196
1197 if (ring->dma) {
1198 dma_free_coherent(eth->dev,
1199 MTK_DMA_SIZE * sizeof(*ring->dma),
1200 ring->dma,
1201 ring->phys);
1202 ring->dma = NULL;
1203 }
1204}
1205
1206/* wait for DMA to finish whatever it is doing before we start using it again */
1207static int mtk_dma_busy_wait(struct mtk_eth *eth)
1208{
1209 unsigned long t_start = jiffies;
1210
1211 while (1) {
1212 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1213 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1214 return 0;
1215 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1216 break;
1217 }
1218
1219 dev_err(eth->dev, "DMA init timeout\n");
1220 return -1;
1221}
1222
1223static int mtk_dma_init(struct mtk_eth *eth)
1224{
1225 int err;
1226
1227 if (mtk_dma_busy_wait(eth))
1228 return -EBUSY;
1229
1230 /* QDMA needs scratch memory for internal reordering of the
1231 * descriptors
1232 */
1233 err = mtk_init_fq_dma(eth);
1234 if (err)
1235 return err;
1236
1237 err = mtk_tx_alloc(eth);
1238 if (err)
1239 return err;
1240
1241 err = mtk_rx_alloc(eth);
1242 if (err)
1243 return err;
1244
1245 /* Enable random early drop and set drop threshold automatically */
1246 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1247 MTK_QDMA_FC_THRES);
1248 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1249
1250 return 0;
1251}
1252
1253static void mtk_dma_free(struct mtk_eth *eth)
1254{
1255 int i;
1256
1257 for (i = 0; i < MTK_MAC_COUNT; i++)
1258 if (eth->netdev[i])
1259 netdev_reset_queue(eth->netdev[i]);
605e4fe4
JC		 1260 if (eth->scratch_ring) {
1261 dma_free_coherent(eth->dev,
1262 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1263 eth->scratch_ring,
1264 eth->phy_scratch_ring);
1265 eth->scratch_ring = NULL;
1266 eth->phy_scratch_ring = 0;
1267 }
656e7052
JC		 1268 mtk_tx_clean(eth);
1269 mtk_rx_clean(eth);
1270 kfree(eth->scratch_head);
1271}
1272
1273static void mtk_tx_timeout(struct net_device *dev)
1274{
1275 struct mtk_mac *mac = netdev_priv(dev);
1276 struct mtk_eth *eth = mac->hw;
1277
1278 eth->netdev[mac->id]->stats.tx_errors++;
1279 netif_err(eth, tx_err, dev,
1280 "transmit timed out\n");
7c78b4ad 1281 schedule_work(&eth->pending_work);
656e7052
JC		 1282}
1283
80673029 1284static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
656e7052
JC		 1285{
1286 struct mtk_eth *eth = _eth;
656e7052 1287
80673029
JC		 1288 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1289 __napi_schedule(&eth->rx_napi);
1290 mtk_irq_disable(eth, MTK_RX_DONE_INT);
1291 }
656e7052 1292
80673029
JC		 1293 return IRQ_HANDLED;
1294}
1295
1296static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1297{
1298 struct mtk_eth *eth = _eth;
1299
1300 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1301 __napi_schedule(&eth->tx_napi);
1302 mtk_irq_disable(eth, MTK_TX_DONE_INT);
656e7052 1303 }
656e7052
JC		 1304
1305 return IRQ_HANDLED;
1306}
1307
1308#ifdef CONFIG_NET_POLL_CONTROLLER
1309static void mtk_poll_controller(struct net_device *dev)
1310{
1311 struct mtk_mac *mac = netdev_priv(dev);
1312 struct mtk_eth *eth = mac->hw;
1313 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1314
1315 mtk_irq_disable(eth, int_mask);
8186f6e3 1316 mtk_handle_irq_rx(eth->irq[2], dev);
656e7052
JC		 1317 mtk_irq_enable(eth, int_mask);
1318}
1319#endif
1320
1321static int mtk_start_dma(struct mtk_eth *eth)
1322{
1323 int err;
1324
1325 err = mtk_dma_init(eth);
1326 if (err) {
1327 mtk_dma_free(eth);
1328 return err;
1329 }
1330
1331 mtk_w32(eth,
1332 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1333 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
6675086d 1334 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
656e7052
JC		 1335 MTK_QDMA_GLO_CFG);
1336
1337 return 0;
1338}
1339
1340static int mtk_open(struct net_device *dev)
1341{
1342 struct mtk_mac *mac = netdev_priv(dev);
1343 struct mtk_eth *eth = mac->hw;
1344
1345 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1346 if (!atomic_read(&eth->dma_refcnt)) {
1347 int err = mtk_start_dma(eth);
1348
1349 if (err)
1350 return err;
1351
80673029 1352 napi_enable(&eth->tx_napi);
656e7052
JC		 1353 napi_enable(&eth->rx_napi);
1354 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1355 }
1356 atomic_inc(&eth->dma_refcnt);
1357
1358 phy_start(mac->phy_dev);
1359 netif_start_queue(dev);
1360
1361 return 0;
1362}
1363
1364static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1365{
1366 unsigned long flags;
1367 u32 val;
1368 int i;
1369
1370 /* stop the dma engine */
1371 spin_lock_irqsave(&eth->page_lock, flags);
1372 val = mtk_r32(eth, glo_cfg);
1373 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1374 glo_cfg);
1375 spin_unlock_irqrestore(&eth->page_lock, flags);
1376
1377 /* wait for dma stop */
1378 for (i = 0; i < 10; i++) {
1379 val = mtk_r32(eth, glo_cfg);
1380 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1381 msleep(20);
1382 continue;
1383 }
1384 break;
1385 }
1386}
1387
1388static int mtk_stop(struct net_device *dev)
1389{
1390 struct mtk_mac *mac = netdev_priv(dev);
1391 struct mtk_eth *eth = mac->hw;
1392
1393 netif_tx_disable(dev);
1394 phy_stop(mac->phy_dev);
1395
1396 /* only shutdown DMA if this is the last user */
1397 if (!atomic_dec_and_test(&eth->dma_refcnt))
1398 return 0;
1399
1400 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
80673029 1401 napi_disable(&eth->tx_napi);
656e7052
JC		 1402 napi_disable(&eth->rx_napi);
1403
1404 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1405
1406 mtk_dma_free(eth);
1407
1408 return 0;
1409}
1410
1411static int __init mtk_hw_init(struct mtk_eth *eth)
1412{
1413 int err, i;
1414
1415 /* reset the frame engine */
1416 reset_control_assert(eth->rstc);
1417 usleep_range(10, 20);
1418 reset_control_deassert(eth->rstc);
1419 usleep_range(10, 20);
1420
1421 /* Set GE2 driving and slew rate */
1422 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1423
1424 /* set GE2 TDSEL */
1425 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1426
1427 /* set GE2 TUNE */
1428 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1429
1430 /* GE1, Force 1000M/FD, FC ON */
1431 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1432
1433 /* GE2, Force 1000M/FD, FC ON */
1434 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1435
1436 /* Enable RX VLan Offloading */
1437 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1438
80673029
JC		 1439 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1440 dev_name(eth->dev), eth);
1441 if (err)
1442 return err;
1443 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
656e7052
JC		 1444 dev_name(eth->dev), eth);
1445 if (err)
1446 return err;
1447
1448 err = mtk_mdio_init(eth);
1449 if (err)
1450 return err;
1451
1452 /* disable delay and normal interrupt */
1453 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2ff0bb61 1454 mtk_irq_disable(eth, ~0);
656e7052
JC		 1455 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1456 mtk_w32(eth, 0, MTK_RST_GL);
1457
1458 /* FE int grouping */
80673029
JC		 1459 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1460 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1461 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1462 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1463 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
656e7052
JC		 1464
1465 for (i = 0; i < 2; i++) {
1466 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1467
1468 /* setup the forward port to send frame to QDMA */
1469 val &= ~0xffff;
1470 val |= 0x5555;
1471
1472 /* Enable RX checksum */
1473 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1474
1475 /* setup the mac dma */
1476 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1477 }
1478
1479 return 0;
1480}
1481
1482static int __init mtk_init(struct net_device *dev)
1483{
1484 struct mtk_mac *mac = netdev_priv(dev);
1485 struct mtk_eth *eth = mac->hw;
1486 const char *mac_addr;
1487
1488 mac_addr = of_get_mac_address(mac->of_node);
1489 if (mac_addr)
1490 ether_addr_copy(dev->dev_addr, mac_addr);
1491
1492 /* If the mac address is invalid, use random mac address */
1493 if (!is_valid_ether_addr(dev->dev_addr)) {
1494 random_ether_addr(dev->dev_addr);
1495 dev_err(eth->dev, "generated random MAC address %pM\n",
1496 dev->dev_addr);
1497 dev->addr_assign_type = NET_ADDR_RANDOM;
1498 }
1499
1500 return mtk_phy_connect(mac);
1501}
1502
1503static void mtk_uninit(struct net_device *dev)
1504{
1505 struct mtk_mac *mac = netdev_priv(dev);
1506 struct mtk_eth *eth = mac->hw;
1507
1508 phy_disconnect(mac->phy_dev);
1509 mtk_mdio_cleanup(eth);
1510 mtk_irq_disable(eth, ~0);
80673029
JC		 1511 free_irq(eth->irq[1], dev);
1512 free_irq(eth->irq[2], dev);
656e7052
JC		 1513}
1514
1515static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1516{
1517 struct mtk_mac *mac = netdev_priv(dev);
1518
1519 switch (cmd) {
1520 case SIOCGMIIPHY:
1521 case SIOCGMIIREG:
1522 case SIOCSMIIREG:
1523 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1524 default:
1525 break;
1526 }
1527
1528 return -EOPNOTSUPP;
1529}
1530
1531static void mtk_pending_work(struct work_struct *work)
1532{
7c78b4ad 1533 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
e7d425dc
JC		 1534 int err, i;
1535 unsigned long restart = 0;
656e7052
JC		 1536
1537 rtnl_lock();
656e7052 1538
e7d425dc
JC		 1539 /* stop all devices to make sure that dma is properly shut down */
1540 for (i = 0; i < MTK_MAC_COUNT; i++) {
7c78b4ad 1541 if (!eth->netdev[i])
e7d425dc
JC		 1542 continue;
1543 mtk_stop(eth->netdev[i]);
1544 __set_bit(i, &restart);
1545 }
1546
1547 /* restart DMA and enable IRQs */
1548 for (i = 0; i < MTK_MAC_COUNT; i++) {
1549 if (!test_bit(i, &restart))
1550 continue;
1551 err = mtk_open(eth->netdev[i]);
1552 if (err) {
1553 netif_alert(eth, ifup, eth->netdev[i],
1554 "Driver up/down cycle failed, closing device.\n");
1555 dev_close(eth->netdev[i]);
1556 }
656e7052
JC		 1557 }
1558 rtnl_unlock();
1559}
1560
1561static int mtk_cleanup(struct mtk_eth *eth)
1562{
1563 int i;
1564
1565 for (i = 0; i < MTK_MAC_COUNT; i++) {
656e7052
JC		 1566 if (!eth->netdev[i])
1567 continue;
1568
1569 unregister_netdev(eth->netdev[i]);
1570 free_netdev(eth->netdev[i]);
656e7052 1571 }
7c78b4ad 1572 cancel_work_sync(&eth->pending_work);
656e7052
JC		 1573
1574 return 0;
1575}
1576
1577static int mtk_get_settings(struct net_device *dev,
1578 struct ethtool_cmd *cmd)
1579{
1580 struct mtk_mac *mac = netdev_priv(dev);
1581 int err;
1582
1583 err = phy_read_status(mac->phy_dev);
1584 if (err)
1585 return -ENODEV;
1586
1587 return phy_ethtool_gset(mac->phy_dev, cmd);
1588}
1589
1590static int mtk_set_settings(struct net_device *dev,
1591 struct ethtool_cmd *cmd)
1592{
1593 struct mtk_mac *mac = netdev_priv(dev);
1594
1595 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1596 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1597 cmd->phy_address);
1598 if (!mac->phy_dev)
1599 return -ENODEV;
1600 }
1601
1602 return phy_ethtool_sset(mac->phy_dev, cmd);
1603}
1604
1605static void mtk_get_drvinfo(struct net_device *dev,
1606 struct ethtool_drvinfo *info)
1607{
1608 struct mtk_mac *mac = netdev_priv(dev);
1609
1610 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1611 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1612 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1613}
1614
1615static u32 mtk_get_msglevel(struct net_device *dev)
1616{
1617 struct mtk_mac *mac = netdev_priv(dev);
1618
1619 return mac->hw->msg_enable;
1620}
1621
1622static void mtk_set_msglevel(struct net_device *dev, u32 value)
1623{
1624 struct mtk_mac *mac = netdev_priv(dev);
1625
1626 mac->hw->msg_enable = value;
1627}
1628
1629static int mtk_nway_reset(struct net_device *dev)
1630{
1631 struct mtk_mac *mac = netdev_priv(dev);
1632
1633 return genphy_restart_aneg(mac->phy_dev);
1634}
1635
1636static u32 mtk_get_link(struct net_device *dev)
1637{
1638 struct mtk_mac *mac = netdev_priv(dev);
1639 int err;
1640
1641 err = genphy_update_link(mac->phy_dev);
1642 if (err)
1643 return ethtool_op_get_link(dev);
1644
1645 return mac->phy_dev->link;
1646}
1647
1648static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1649{
1650 int i;
1651
1652 switch (stringset) {
1653 case ETH_SS_STATS:
1654 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1655 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1656 data += ETH_GSTRING_LEN;
1657 }
1658 break;
1659 }
1660}
1661
1662static int mtk_get_sset_count(struct net_device *dev, int sset)
1663{
1664 switch (sset) {
1665 case ETH_SS_STATS:
1666 return ARRAY_SIZE(mtk_ethtool_stats);
1667 default:
1668 return -EOPNOTSUPP;
1669 }
1670}
1671
1672static void mtk_get_ethtool_stats(struct net_device *dev,
1673 struct ethtool_stats *stats, u64 *data)
1674{
1675 struct mtk_mac *mac = netdev_priv(dev);
1676 struct mtk_hw_stats *hwstats = mac->hw_stats;
1677 u64 *data_src, *data_dst;
1678 unsigned int start;
1679 int i;
1680
1681 if (netif_running(dev) && netif_device_present(dev)) {
1682 if (spin_trylock(&hwstats->stats_lock)) {
1683 mtk_stats_update_mac(mac);
1684 spin_unlock(&hwstats->stats_lock);
1685 }
1686 }
1687
1688 do {
1689 data_src = (u64*)hwstats;
1690 data_dst = data;
1691 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1692
1693 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1694 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1695 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1696}
1697
1698static struct ethtool_ops mtk_ethtool_ops = {
1699 .get_settings = mtk_get_settings,
1700 .set_settings = mtk_set_settings,
1701 .get_drvinfo = mtk_get_drvinfo,
1702 .get_msglevel = mtk_get_msglevel,
1703 .set_msglevel = mtk_set_msglevel,
1704 .nway_reset = mtk_nway_reset,
1705 .get_link = mtk_get_link,
1706 .get_strings = mtk_get_strings,
1707 .get_sset_count = mtk_get_sset_count,
1708 .get_ethtool_stats = mtk_get_ethtool_stats,
1709};
1710
1711static const struct net_device_ops mtk_netdev_ops = {
1712 .ndo_init = mtk_init,
1713 .ndo_uninit = mtk_uninit,
1714 .ndo_open = mtk_open,
1715 .ndo_stop = mtk_stop,
1716 .ndo_start_xmit = mtk_start_xmit,
1717 .ndo_set_mac_address = mtk_set_mac_address,
1718 .ndo_validate_addr = eth_validate_addr,
1719 .ndo_do_ioctl = mtk_do_ioctl,
1720 .ndo_change_mtu = eth_change_mtu,
1721 .ndo_tx_timeout = mtk_tx_timeout,
1722 .ndo_get_stats64 = mtk_get_stats64,
1723#ifdef CONFIG_NET_POLL_CONTROLLER
1724 .ndo_poll_controller = mtk_poll_controller,
1725#endif
1726};
1727
1728static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1729{
1730 struct mtk_mac *mac;
1731 const __be32 *_id = of_get_property(np, "reg", NULL);
1732 int id, err;
1733
1734 if (!_id) {
1735 dev_err(eth->dev, "missing mac id\n");
1736 return -EINVAL;
1737 }
1738
1739 id = be32_to_cpup(_id);
1740 if (id >= MTK_MAC_COUNT) {
1741 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1742 return -EINVAL;
1743 }
1744
1745 if (eth->netdev[id]) {
1746 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1747 return -EINVAL;
1748 }
1749
1750 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1751 if (!eth->netdev[id]) {
1752 dev_err(eth->dev, "alloc_etherdev failed\n");
1753 return -ENOMEM;
1754 }
1755 mac = netdev_priv(eth->netdev[id]);
1756 eth->mac[id] = mac;
1757 mac->id = id;
1758 mac->hw = eth;
1759 mac->of_node = np;
656e7052
JC		 1760
1761 mac->hw_stats = devm_kzalloc(eth->dev,
1762 sizeof(*mac->hw_stats),
1763 GFP_KERNEL);
1764 if (!mac->hw_stats) {
1765 dev_err(eth->dev, "failed to allocate counter memory\n");
1766 err = -ENOMEM;
1767 goto free_netdev;
1768 }
1769 spin_lock_init(&mac->hw_stats->stats_lock);
d7005652 1770 u64_stats_init(&mac->hw_stats->syncp);
656e7052
JC		 1771 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1772
1773 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
eaadf9fd 1774 eth->netdev[id]->watchdog_timeo = 5 * HZ;
656e7052
JC		 1775 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1776 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1777 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1778 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1779 eth->netdev[id]->features |= MTK_HW_FEATURES;
1780 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1781
1782 err = register_netdev(eth->netdev[id]);
1783 if (err) {
1784 dev_err(eth->dev, "error bringing up device\n");
1785 goto free_netdev;
1786 }
80673029 1787 eth->netdev[id]->irq = eth->irq[0];
656e7052
JC		 1788 netif_info(eth, probe, eth->netdev[id],
1789 "mediatek frame engine at 0x%08lx, irq %d\n",
80673029 1790 eth->netdev[id]->base_addr, eth->irq[0]);
656e7052
JC		 1791
1792 return 0;
1793
1794free_netdev:
1795 free_netdev(eth->netdev[id]);
1796 return err;
1797}
1798
1799static int mtk_probe(struct platform_device *pdev)
1800{
1801 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1802 struct device_node *mac_np;
1803 const struct of_device_id *match;
1804 struct mtk_soc_data *soc;
1805 struct mtk_eth *eth;
1806 int err;
80673029 1807 int i;
656e7052 1808
656e7052
JC		 1809 match = of_match_device(of_mtk_match, &pdev->dev);
1810 soc = (struct mtk_soc_data *)match->data;
1811
1812 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1813 if (!eth)
1814 return -ENOMEM;
1815
1816 eth->base = devm_ioremap_resource(&pdev->dev, res);
621e49f6
VZ		 1817 if (IS_ERR(eth->base))
1818 return PTR_ERR(eth->base);
656e7052
JC		 1819
1820 spin_lock_init(&eth->page_lock);
7bc9ccec 1821 spin_lock_init(&eth->irq_lock);
656e7052
JC		 1822
1823 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1824 "mediatek,ethsys");
1825 if (IS_ERR(eth->ethsys)) {
1826 dev_err(&pdev->dev, "no ethsys regmap found\n");
1827 return PTR_ERR(eth->ethsys);
1828 }
1829
1830 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1831 "mediatek,pctl");
1832 if (IS_ERR(eth->pctl)) {
1833 dev_err(&pdev->dev, "no pctl regmap found\n");
1834 return PTR_ERR(eth->pctl);
1835 }
1836
1837 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1838 if (IS_ERR(eth->rstc)) {
1839 dev_err(&pdev->dev, "no eth reset found\n");
1840 return PTR_ERR(eth->rstc);
1841 }
1842
80673029
JC		 1843 for (i = 0; i < 3; i++) {
1844 eth->irq[i] = platform_get_irq(pdev, i);
1845 if (eth->irq[i] < 0) {
1846 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1847 return -ENXIO;
1848 }
656e7052
JC		 1849 }
1850
1851 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1852 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1853 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1854 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1855 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1856 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1857 return -ENODEV;
1858
1859 clk_prepare_enable(eth->clk_ethif);
1860 clk_prepare_enable(eth->clk_esw);
1861 clk_prepare_enable(eth->clk_gp1);
1862 clk_prepare_enable(eth->clk_gp2);
1863
1864 eth->dev = &pdev->dev;
1865 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
7c78b4ad 1866 INIT_WORK(&eth->pending_work, mtk_pending_work);
656e7052
JC		 1867
1868 err = mtk_hw_init(eth);
1869 if (err)
1870 return err;
1871
1872 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1873 if (!of_device_is_compatible(mac_np,
1874 "mediatek,eth-mac"))
1875 continue;
1876
1877 if (!of_device_is_available(mac_np))
1878 continue;
1879
1880 err = mtk_add_mac(eth, mac_np);
1881 if (err)
1882 goto err_free_dev;
1883 }
1884
1885 /* we run 2 devices on the same DMA ring so we need a dummy device
1886 * for NAPI to work
1887 */
1888 init_dummy_netdev(&eth->dummy_dev);
80673029
JC		 1889 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1890 MTK_NAPI_WEIGHT);
1891 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
656e7052
JC		 1892 MTK_NAPI_WEIGHT);
1893
1894 platform_set_drvdata(pdev, eth);
1895
1896 return 0;
1897
1898err_free_dev:
1899 mtk_cleanup(eth);
1900 return err;
1901}
1902
1903static int mtk_remove(struct platform_device *pdev)
1904{
1905 struct mtk_eth *eth = platform_get_drvdata(pdev);
1906
1907 clk_disable_unprepare(eth->clk_ethif);
1908 clk_disable_unprepare(eth->clk_esw);
1909 clk_disable_unprepare(eth->clk_gp1);
1910 clk_disable_unprepare(eth->clk_gp2);
1911
80673029 1912 netif_napi_del(&eth->tx_napi);
656e7052
JC		 1913 netif_napi_del(&eth->rx_napi);
1914 mtk_cleanup(eth);
1915 platform_set_drvdata(pdev, NULL);
1916
1917 return 0;
1918}
1919
1920const struct of_device_id of_mtk_match[] = {
1921 { .compatible = "mediatek,mt7623-eth" },
1922 {},
1923};
1924
1925static struct platform_driver mtk_driver = {
1926 .probe = mtk_probe,
1927 .remove = mtk_remove,
1928 .driver = {
1929 .name = "mtk_soc_eth",
656e7052
JC		 1930 .of_match_table = of_mtk_match,
1931 },
1932};
1933
1934module_platform_driver(mtk_driver);
1935
1936MODULE_LICENSE("GPL");
1937MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1938MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
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