[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.h

/*   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; version 2 of the License
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
 *   Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
 *   Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
 */

#ifndef MTK_ETH_H
#define MTK_ETH_H

#define MTK_QDMA_PAGE_SIZE	2048
#define	MTK_MAX_RX_LENGTH	1536
#define MTK_TX_DMA_BUF_LEN	0x3fff
#define MTK_DMA_SIZE		256
#define MTK_NAPI_WEIGHT		64
#define MTK_MAC_COUNT		2
#define MTK_RX_ETH_HLEN		(VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
#define MTK_RX_HLEN		(NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
#define MTK_DMA_DUMMY_DESC	0xffffffff
#define MTK_DEFAULT_MSG_ENABLE	(NETIF_MSG_DRV | \
				 NETIF_MSG_PROBE | \
				 NETIF_MSG_LINK | \
				 NETIF_MSG_TIMER | \
				 NETIF_MSG_IFDOWN | \
				 NETIF_MSG_IFUP | \
				 NETIF_MSG_RX_ERR | \
				 NETIF_MSG_TX_ERR)
#define MTK_HW_FEATURES		(NETIF_F_IP_CSUM | \
				 NETIF_F_RXCSUM | \
				 NETIF_F_HW_VLAN_CTAG_TX | \
				 NETIF_F_HW_VLAN_CTAG_RX | \
				 NETIF_F_SG | NETIF_F_TSO | \
				 NETIF_F_TSO6 | \
				 NETIF_F_IPV6_CSUM)
#define NEXT_RX_DESP_IDX(X)	(((X) + 1) & (MTK_DMA_SIZE - 1))

/* Frame Engine Global Reset Register */
#define MTK_RST_GL		0x04
#define RST_GL_PSE		BIT(0)

/* Frame Engine Interrupt Status Register */
#define MTK_INT_STATUS2		0x08
#define MTK_GDM1_AF		BIT(28)
#define MTK_GDM2_AF		BIT(29)

/* Frame Engine Interrupt Grouping Register */
#define MTK_FE_INT_GRP		0x20

/* CDMP Exgress Control Register */
#define MTK_CDMP_EG_CTRL	0x404

/* GDM Exgress Control Register */
#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
#define MTK_GDMA_ICS_EN		BIT(22)
#define MTK_GDMA_TCS_EN		BIT(21)
#define MTK_GDMA_UCS_EN		BIT(20)

/* Unicast Filter MAC Address Register - Low */
#define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))

/* Unicast Filter MAC Address Register - High */
#define MTK_GDMA_MAC_ADRH(x)	(0x50C + (x * 0x1000))

/* PDMA Interrupt grouping registers */
#define MTK_PDMA_INT_GRP1	0xa50
#define MTK_PDMA_INT_GRP2	0xa54

/* QDMA TX Queue Configuration Registers */
#define MTK_QTX_CFG(x)		(0x1800 + (x * 0x10))
#define QDMA_RES_THRES		4

/* QDMA TX Queue Scheduler Registers */
#define MTK_QTX_SCH(x)		(0x1804 + (x * 0x10))

/* QDMA RX Base Pointer Register */
#define MTK_QRX_BASE_PTR0	0x1900

/* QDMA RX Maximum Count Register */
#define MTK_QRX_MAX_CNT0	0x1904

/* QDMA RX CPU Pointer Register */
#define MTK_QRX_CRX_IDX0	0x1908

/* QDMA RX DMA Pointer Register */
#define MTK_QRX_DRX_IDX0	0x190C

/* QDMA Global Configuration Register */
#define MTK_QDMA_GLO_CFG	0x1A04
#define MTK_RX_2B_OFFSET	BIT(31)
#define MTK_RX_BT_32DWORDS	(3 << 11)
#define MTK_NDP_CO_PRO		BIT(10)
#define MTK_TX_WB_DDONE		BIT(6)
#define MTK_DMA_SIZE_16DWORDS	(2 << 4)
#define MTK_RX_DMA_BUSY		BIT(3)
#define MTK_TX_DMA_BUSY		BIT(1)
#define MTK_RX_DMA_EN		BIT(2)
#define MTK_TX_DMA_EN		BIT(0)
#define MTK_DMA_BUSY_TIMEOUT	HZ

/* QDMA Reset Index Register */
#define MTK_QDMA_RST_IDX	0x1A08
#define MTK_PST_DRX_IDX0	BIT(16)

/* QDMA Delay Interrupt Register */
#define MTK_QDMA_DELAY_INT	0x1A0C

/* QDMA Flow Control Register */
#define MTK_QDMA_FC_THRES	0x1A10
#define FC_THRES_DROP_MODE	BIT(20)
#define FC_THRES_DROP_EN	(7 << 16)
#define FC_THRES_MIN		0x4444

/* QDMA Interrupt Status Register */
#define MTK_QMTK_INT_STATUS	0x1A18
#define MTK_RX_DONE_INT1	BIT(17)
#define MTK_RX_DONE_INT0	BIT(16)
#define MTK_TX_DONE_INT3	BIT(3)
#define MTK_TX_DONE_INT2	BIT(2)
#define MTK_TX_DONE_INT1	BIT(1)
#define MTK_TX_DONE_INT0	BIT(0)
#define MTK_RX_DONE_INT		(MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1)
#define MTK_TX_DONE_INT		(MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
				 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)

/* QDMA Interrupt grouping registers */
#define MTK_QDMA_INT_GRP1	0x1a20
#define MTK_QDMA_INT_GRP2	0x1a24
#define MTK_RLS_DONE_INT	BIT(0)

/* QDMA Interrupt Status Register */
#define MTK_QDMA_INT_MASK	0x1A1C

/* QDMA Interrupt Mask Register */
#define MTK_QDMA_HRED2		0x1A44

/* QDMA TX Forward CPU Pointer Register */
#define MTK_QTX_CTX_PTR		0x1B00

/* QDMA TX Forward DMA Pointer Register */
#define MTK_QTX_DTX_PTR		0x1B04

/* QDMA TX Release CPU Pointer Register */
#define MTK_QTX_CRX_PTR		0x1B10

/* QDMA TX Release DMA Pointer Register */
#define MTK_QTX_DRX_PTR		0x1B14

/* QDMA FQ Head Pointer Register */
#define MTK_QDMA_FQ_HEAD	0x1B20

/* QDMA FQ Head Pointer Register */
#define MTK_QDMA_FQ_TAIL	0x1B24

/* QDMA FQ Free Page Counter Register */
#define MTK_QDMA_FQ_CNT		0x1B28

/* QDMA FQ Free Page Buffer Length Register */
#define MTK_QDMA_FQ_BLEN	0x1B2C

/* GMA1 Received Good Byte Count Register */
#define MTK_GDM1_TX_GBCNT	0x2400
#define MTK_STAT_OFFSET		0x40

/* QDMA descriptor txd4 */
#define TX_DMA_CHKSUM		(0x7 << 29)
#define TX_DMA_TSO		BIT(28)
#define TX_DMA_FPORT_SHIFT	25
#define TX_DMA_FPORT_MASK	0x7
#define TX_DMA_INS_VLAN		BIT(16)

/* QDMA descriptor txd3 */
#define TX_DMA_OWNER_CPU	BIT(31)
#define TX_DMA_LS0		BIT(30)
#define TX_DMA_PLEN0(_x)	(((_x) & MTK_TX_DMA_BUF_LEN) << 16)
#define TX_DMA_SWC		BIT(14)
#define TX_DMA_SDL(_x)		(((_x) & 0x3fff) << 16)

/* QDMA descriptor rxd2 */
#define RX_DMA_DONE		BIT(31)
#define RX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x)	(((_x) >> 16) & 0x3fff)

/* QDMA descriptor rxd3 */
#define RX_DMA_VID(_x)		((_x) & 0xfff)

/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID		BIT(24)
#define RX_DMA_FPORT_SHIFT	19
#define RX_DMA_FPORT_MASK	0x7

/* PHY Indirect Access Control registers */
#define MTK_PHY_IAC		0x10004
#define PHY_IAC_ACCESS		BIT(31)
#define PHY_IAC_READ		BIT(19)
#define PHY_IAC_WRITE		BIT(18)
#define PHY_IAC_START		BIT(16)
#define PHY_IAC_ADDR_SHIFT	20
#define PHY_IAC_REG_SHIFT	25
#define PHY_IAC_TIMEOUT		HZ

/* Mac control registers */
#define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
#define MAC_MCR_MAX_RX_1536	BIT(24)
#define MAC_MCR_IPG_CFG		(BIT(18) | BIT(16))
#define MAC_MCR_FORCE_MODE	BIT(15)
#define MAC_MCR_TX_EN		BIT(14)
#define MAC_MCR_RX_EN		BIT(13)
#define MAC_MCR_BACKOFF_EN	BIT(9)
#define MAC_MCR_BACKPR_EN	BIT(8)
#define MAC_MCR_FORCE_RX_FC	BIT(5)
#define MAC_MCR_FORCE_TX_FC	BIT(4)
#define MAC_MCR_SPEED_1000	BIT(3)
#define MAC_MCR_SPEED_100	BIT(2)
#define MAC_MCR_FORCE_DPX	BIT(1)
#define MAC_MCR_FORCE_LINK	BIT(0)
#define MAC_MCR_FIXED_LINK	(MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
				 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
				 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
				 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
				 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
				 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)

/* GPIO port control registers for GMAC 2*/
#define GPIO_OD33_CTRL8		0x4c0
#define GPIO_BIAS_CTRL		0xed0
#define GPIO_DRV_SEL10		0xf00

/* ethernet subsystem config register */
#define ETHSYS_SYSCFG0		0x14
#define SYSCFG0_GE_MASK		0x3
#define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))

struct mtk_rx_dma {
	unsigned int rxd1;
	unsigned int rxd2;
	unsigned int rxd3;
	unsigned int rxd4;
} __packed __aligned(4);

struct mtk_tx_dma {
	unsigned int txd1;
	unsigned int txd2;
	unsigned int txd3;
	unsigned int txd4;
} __packed __aligned(4);

struct mtk_eth;
struct mtk_mac;

/* struct mtk_hw_stats - the structure that holds the traffic statistics.
 * @stats_lock:		make sure that stats operations are atomic
 * @reg_offset:		the status register offset of the SoC
 * @syncp:		the refcount
 *
 * All of the supported SoCs have hardware counters for traffic statistics.
 * Whenever the status IRQ triggers we can read the latest stats from these
 * counters and store them in this struct.
 */
struct mtk_hw_stats {
	u64 tx_bytes;
	u64 tx_packets;
	u64 tx_skip;
	u64 tx_collisions;
	u64 rx_bytes;
	u64 rx_packets;
	u64 rx_overflow;
	u64 rx_fcs_errors;
	u64 rx_short_errors;
	u64 rx_long_errors;
	u64 rx_checksum_errors;
	u64 rx_flow_control_packets;

	spinlock_t		stats_lock;
	u32			reg_offset;
	struct u64_stats_sync	syncp;
};

/* PDMA descriptor can point at 1-2 segments. This enum allows us to track how
 * memory was allocated so that it can be freed properly
 */
enum mtk_tx_flags {
	MTK_TX_FLAGS_SINGLE0	= 0x01,
	MTK_TX_FLAGS_PAGE0	= 0x02,
};

/* This enum allows us to identify how the clock is defined on the array of the
 * clock in the order
 */
enum mtk_clks_map {
	MTK_CLK_ETHIF,
	MTK_CLK_ESW,
	MTK_CLK_GP1,
	MTK_CLK_GP2,
	MTK_CLK_MAX
};

/* struct mtk_tx_buf -	This struct holds the pointers to the memory pointed at
 *			by the TX descriptor	s
 * @skb:		The SKB pointer of the packet being sent
 * @dma_addr0:		The base addr of the first segment
 * @dma_len0:		The length of the first segment
 * @dma_addr1:		The base addr of the second segment
 * @dma_len1:		The length of the second segment
 */
struct mtk_tx_buf {
	struct sk_buff *skb;
	u32 flags;
	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
	DEFINE_DMA_UNMAP_LEN(dma_len0);
	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
	DEFINE_DMA_UNMAP_LEN(dma_len1);
};

/* struct mtk_tx_ring -	This struct holds info describing a TX ring
 * @dma:		The descriptor ring
 * @buf:		The memory pointed at by the ring
 * @phys:		The physical addr of tx_buf
 * @next_free:		Pointer to the next free descriptor
 * @last_free:		Pointer to the last free descriptor
 * @thresh:		The threshold of minimum amount of free descriptors
 * @free_count:		QDMA uses a linked list. Track how many free descriptors
 *			are present
 */
struct mtk_tx_ring {
	struct mtk_tx_dma *dma;
	struct mtk_tx_buf *buf;
	dma_addr_t phys;
	struct mtk_tx_dma *next_free;
	struct mtk_tx_dma *last_free;
	u16 thresh;
	atomic_t free_count;
};

/* struct mtk_rx_ring -	This struct holds info describing a RX ring
 * @dma:		The descriptor ring
 * @data:		The memory pointed at by the ring
 * @phys:		The physical addr of rx_buf
 * @frag_size:		How big can each fragment be
 * @buf_size:		The size of each packet buffer
 * @calc_idx:		The current head of ring
 */
struct mtk_rx_ring {
	struct mtk_rx_dma *dma;
	u8 **data;
	dma_addr_t phys;
	u16 frag_size;
	u16 buf_size;
	u16 calc_idx;
};

/* currently no SoC has more than 2 macs */
#define MTK_MAX_DEVS			2

/* struct mtk_eth -	This is the main datasructure for holding the state
 *			of the driver
 * @dev:		The device pointer
 * @base:		The mapped register i/o base
 * @page_lock:		Make sure that register operations are atomic
 * @dummy_dev:		we run 2 netdevs on 1 physical DMA ring and need a
 *			dummy for NAPI to work
 * @netdev:		The netdev instances
 * @mac:		Each netdev is linked to a physical MAC
 * @irq:		The IRQ that we are using
 * @msg_enable:		Ethtool msg level
 * @ethsys:		The register map pointing at the range used to setup
 *			MII modes
 * @pctl:		The register map pointing at the range used to setup
 *			GMAC port drive/slew values
 * @dma_refcnt:		track how many netdevs are using the DMA engine
 * @tx_ring:		Pointer to the memore holding info about the TX ring
 * @rx_ring:		Pointer to the memore holding info about the RX ring
 * @tx_napi:		The TX NAPI struct
 * @rx_napi:		The RX NAPI struct
 * @scratch_ring:	Newer SoCs need memory for a second HW managed TX ring
 * @phy_scratch_ring:	physical address of scratch_ring
 * @scratch_head:	The scratch memory that scratch_ring points to.
 * @clks:		clock array for all clocks required
 * @mii_bus:		If there is a bus we need to create an instance for it
 * @pending_work:	The workqueue used to reset the dma ring
 */

struct mtk_eth {
	struct device			*dev;
	void __iomem			*base;
	struct reset_control		*rstc;
	spinlock_t			page_lock;
	spinlock_t			irq_lock;
	struct net_device		dummy_dev;
	struct net_device		*netdev[MTK_MAX_DEVS];
	struct mtk_mac			*mac[MTK_MAX_DEVS];
	int				irq[3];
	u32				msg_enable;
	unsigned long			sysclk;
	struct regmap			*ethsys;
	struct regmap			*pctl;
	atomic_t			dma_refcnt;
	struct mtk_tx_ring		tx_ring;
	struct mtk_rx_ring		rx_ring;
	struct napi_struct		tx_napi;
	struct napi_struct		rx_napi;
	struct mtk_tx_dma		*scratch_ring;
	dma_addr_t			phy_scratch_ring;
	void				*scratch_head;
	struct clk			*clks[MTK_CLK_MAX];

	struct mii_bus			*mii_bus;
	struct work_struct		pending_work;
};

/* struct mtk_mac -	the structure that holds the info about the MACs of the
 *			SoC
 * @id:			The number of the MAC
 * @of_node:		Our devicetree node
 * @hw:			Backpointer to our main datastruture
 * @hw_stats:		Packet statistics counter
 * @phy_dev:		The attached PHY if available
 */
struct mtk_mac {
	int				id;
	struct device_node		*of_node;
	struct mtk_eth			*hw;
	struct mtk_hw_stats		*hw_stats;
	struct phy_device		*phy_dev;
};

/* the struct describing the SoC. these are declared in the soc_xyz.c files */
extern const struct of_device_id of_mtk_match[];

/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);

void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);

#endif /* MTK_ETH_H */
Commit	Line	Data
656e7052 JC	1	/* This program is free software; you can redistribute it and/or modify
	2	* it under the terms of the GNU General Public License as published by
	3	* the Free Software Foundation; version 2 of the License
	4	*
	5	* This program is distributed in the hope that it will be useful,
	6	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	7	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	8	* GNU General Public License for more details.
	9	*
	10	* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
	11	* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
	12	* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
	13	*/
	14
	15	#ifndef MTK_ETH_H
	16	#define MTK_ETH_H
	17
	18	#define MTK_QDMA_PAGE_SIZE 2048
	19	#define MTK_MAX_RX_LENGTH 1536
	20	#define MTK_TX_DMA_BUF_LEN 0x3fff
	21	#define MTK_DMA_SIZE 256
	22	#define MTK_NAPI_WEIGHT 64
	23	#define MTK_MAC_COUNT 2
	24	#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
	25	#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
	26	#define MTK_DMA_DUMMY_DESC 0xffffffff
	27	#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV \| \
	28	NETIF_MSG_PROBE \| \
	29	NETIF_MSG_LINK \| \
	30	NETIF_MSG_TIMER \| \
	31	NETIF_MSG_IFDOWN \| \
	32	NETIF_MSG_IFUP \| \
	33	NETIF_MSG_RX_ERR \| \
	34	NETIF_MSG_TX_ERR)
	35	#define MTK_HW_FEATURES (NETIF_F_IP_CSUM \| \
	36	NETIF_F_RXCSUM \| \
	37	NETIF_F_HW_VLAN_CTAG_TX \| \
	38	NETIF_F_HW_VLAN_CTAG_RX \| \
	39	NETIF_F_SG \| NETIF_F_TSO \| \
	40	NETIF_F_TSO6 \| \
	41	NETIF_F_IPV6_CSUM)
	42	#define NEXT_RX_DESP_IDX(X) (((X) + 1) & (MTK_DMA_SIZE - 1))
	43
	44	/* Frame Engine Global Reset Register */
	45	#define MTK_RST_GL 0x04
	46	#define RST_GL_PSE BIT(0)
	47
	48	/* Frame Engine Interrupt Status Register */
	49	#define MTK_INT_STATUS2 0x08
	50	#define MTK_GDM1_AF BIT(28)
	51	#define MTK_GDM2_AF BIT(29)
	52
	53	/* Frame Engine Interrupt Grouping Register */
	54	#define MTK_FE_INT_GRP 0x20
	55
	56	/* CDMP Exgress Control Register */
	57	#define MTK_CDMP_EG_CTRL 0x404
	58
	59	/* GDM Exgress Control Register */
	60	#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
	61	#define MTK_GDMA_ICS_EN BIT(22)
	62	#define MTK_GDMA_TCS_EN BIT(21)
	63	#define MTK_GDMA_UCS_EN BIT(20)
	64
65	/* Unicast Filter MAC Address Register - Low */
66	#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
67
68	/* Unicast Filter MAC Address Register - High */
69	#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
70
80673029 JC	71	/* PDMA Interrupt grouping registers */
	72	#define MTK_PDMA_INT_GRP1 0xa50
	73	#define MTK_PDMA_INT_GRP2 0xa54
	74
656e7052 JC	75	/* QDMA TX Queue Configuration Registers */
	76	#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
	77	#define QDMA_RES_THRES 4
	78
	79	/* QDMA TX Queue Scheduler Registers */
	80	#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
	81
	82	/* QDMA RX Base Pointer Register */
	83	#define MTK_QRX_BASE_PTR0 0x1900
	84
	85	/* QDMA RX Maximum Count Register */
	86	#define MTK_QRX_MAX_CNT0 0x1904
	87
	88	/* QDMA RX CPU Pointer Register */
	89	#define MTK_QRX_CRX_IDX0 0x1908
	90
	91	/* QDMA RX DMA Pointer Register */
	92	#define MTK_QRX_DRX_IDX0 0x190C
	93
	94	/* QDMA Global Configuration Register */
	95	#define MTK_QDMA_GLO_CFG 0x1A04
	96	#define MTK_RX_2B_OFFSET BIT(31)
	97	#define MTK_RX_BT_32DWORDS (3 << 11)
6675086d	98	#define MTK_NDP_CO_PRO BIT(10)
656e7052 JC	99	#define MTK_TX_WB_DDONE BIT(6)
	100	#define MTK_DMA_SIZE_16DWORDS (2 << 4)
	101	#define MTK_RX_DMA_BUSY BIT(3)
	102	#define MTK_TX_DMA_BUSY BIT(1)
	103	#define MTK_RX_DMA_EN BIT(2)
	104	#define MTK_TX_DMA_EN BIT(0)
	105	#define MTK_DMA_BUSY_TIMEOUT HZ
	106
	107	/* QDMA Reset Index Register */
	108	#define MTK_QDMA_RST_IDX 0x1A08
	109	#define MTK_PST_DRX_IDX0 BIT(16)
	110
	111	/* QDMA Delay Interrupt Register */
	112	#define MTK_QDMA_DELAY_INT 0x1A0C
	113
	114	/* QDMA Flow Control Register */
	115	#define MTK_QDMA_FC_THRES 0x1A10
	116	#define FC_THRES_DROP_MODE BIT(20)
	117	#define FC_THRES_DROP_EN (7 << 16)
	118	#define FC_THRES_MIN 0x4444
	119
	120	/* QDMA Interrupt Status Register */
	121	#define MTK_QMTK_INT_STATUS 0x1A18
	122	#define MTK_RX_DONE_INT1 BIT(17)
	123	#define MTK_RX_DONE_INT0 BIT(16)
	124	#define MTK_TX_DONE_INT3 BIT(3)
	125	#define MTK_TX_DONE_INT2 BIT(2)
	126	#define MTK_TX_DONE_INT1 BIT(1)
	127	#define MTK_TX_DONE_INT0 BIT(0)
	128	#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 \| MTK_RX_DONE_INT1)
	129	#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 \| MTK_TX_DONE_INT1 \| \
	130	MTK_TX_DONE_INT2 \| MTK_TX_DONE_INT3)
	131
80673029 JC	132	/* QDMA Interrupt grouping registers */
	133	#define MTK_QDMA_INT_GRP1 0x1a20
	134	#define MTK_QDMA_INT_GRP2 0x1a24
	135	#define MTK_RLS_DONE_INT BIT(0)
	136
656e7052 JC	137	/* QDMA Interrupt Status Register */
	138	#define MTK_QDMA_INT_MASK 0x1A1C
	139
	140	/* QDMA Interrupt Mask Register */
	141	#define MTK_QDMA_HRED2 0x1A44
	142
	143	/* QDMA TX Forward CPU Pointer Register */
	144	#define MTK_QTX_CTX_PTR 0x1B00
	145
	146	/* QDMA TX Forward DMA Pointer Register */
	147	#define MTK_QTX_DTX_PTR 0x1B04
	148
	149	/* QDMA TX Release CPU Pointer Register */
	150	#define MTK_QTX_CRX_PTR 0x1B10
	151
	152	/* QDMA TX Release DMA Pointer Register */
	153	#define MTK_QTX_DRX_PTR 0x1B14
	154
	155	/* QDMA FQ Head Pointer Register */
	156	#define MTK_QDMA_FQ_HEAD 0x1B20
	157
	158	/* QDMA FQ Head Pointer Register */
	159	#define MTK_QDMA_FQ_TAIL 0x1B24
	160
	161	/* QDMA FQ Free Page Counter Register */
	162	#define MTK_QDMA_FQ_CNT 0x1B28
	163
	164	/* QDMA FQ Free Page Buffer Length Register */
	165	#define MTK_QDMA_FQ_BLEN 0x1B2C
	166
	167	/* GMA1 Received Good Byte Count Register */
	168	#define MTK_GDM1_TX_GBCNT 0x2400
	169	#define MTK_STAT_OFFSET 0x40
	170
	171	/* QDMA descriptor txd4 */
	172	#define TX_DMA_CHKSUM (0x7 << 29)
	173	#define TX_DMA_TSO BIT(28)
	174	#define TX_DMA_FPORT_SHIFT 25
	175	#define TX_DMA_FPORT_MASK 0x7
	176	#define TX_DMA_INS_VLAN BIT(16)
	177
	178	/* QDMA descriptor txd3 */
	179	#define TX_DMA_OWNER_CPU BIT(31)
	180	#define TX_DMA_LS0 BIT(30)
	181	#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
	182	#define TX_DMA_SWC BIT(14)
	183	#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
	184
	185	/* QDMA descriptor rxd2 */
	186	#define RX_DMA_DONE BIT(31)
	187	#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
	188	#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
	189
	190	/* QDMA descriptor rxd3 */
	191	#define RX_DMA_VID(_x) ((_x) & 0xfff)
	192
	193	/* QDMA descriptor rxd4 */
	194	#define RX_DMA_L4_VALID BIT(24)
	195	#define RX_DMA_FPORT_SHIFT 19
	196	#define RX_DMA_FPORT_MASK 0x7
	197
	198	/* PHY Indirect Access Control registers */
	199	#define MTK_PHY_IAC 0x10004
	200	#define PHY_IAC_ACCESS BIT(31)
201	#define PHY_IAC_READ BIT(19)
202	#define PHY_IAC_WRITE BIT(18)
203	#define PHY_IAC_START BIT(16)
204	#define PHY_IAC_ADDR_SHIFT 20
205	#define PHY_IAC_REG_SHIFT 25
206	#define PHY_IAC_TIMEOUT HZ
207
208	/* Mac control registers */
209	#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
210	#define MAC_MCR_MAX_RX_1536 BIT(24)
211	#define MAC_MCR_IPG_CFG (BIT(18) \| BIT(16))
212	#define MAC_MCR_FORCE_MODE BIT(15)
213	#define MAC_MCR_TX_EN BIT(14)
214	#define MAC_MCR_RX_EN BIT(13)
215	#define MAC_MCR_BACKOFF_EN BIT(9)
216	#define MAC_MCR_BACKPR_EN BIT(8)
217	#define MAC_MCR_FORCE_RX_FC BIT(5)
218	#define MAC_MCR_FORCE_TX_FC BIT(4)
219	#define MAC_MCR_SPEED_1000 BIT(3)
220	#define MAC_MCR_SPEED_100 BIT(2)
221	#define MAC_MCR_FORCE_DPX BIT(1)
222	#define MAC_MCR_FORCE_LINK BIT(0)
223	#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 \| MAC_MCR_IPG_CFG \| \
224	MAC_MCR_FORCE_MODE \| MAC_MCR_TX_EN \| \
225	MAC_MCR_RX_EN \| MAC_MCR_BACKOFF_EN \| \
226	MAC_MCR_BACKPR_EN \| MAC_MCR_FORCE_RX_FC \| \
227	MAC_MCR_FORCE_TX_FC \| MAC_MCR_SPEED_1000 \| \
228	MAC_MCR_FORCE_DPX \| MAC_MCR_FORCE_LINK)
229
230	/* GPIO port control registers for GMAC 2*/
231	#define GPIO_OD33_CTRL8 0x4c0
232	#define GPIO_BIAS_CTRL 0xed0
233	#define GPIO_DRV_SEL10 0xf00
234
235	/* ethernet subsystem config register */
236	#define ETHSYS_SYSCFG0 0x14
237	#define SYSCFG0_GE_MASK 0x3
238	#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
239
240	struct mtk_rx_dma {
241	unsigned int rxd1;
242	unsigned int rxd2;
243	unsigned int rxd3;
244	unsigned int rxd4;
245	} __packed __aligned(4);
246
247	struct mtk_tx_dma {
248	unsigned int txd1;
249	unsigned int txd2;
250	unsigned int txd3;
251	unsigned int txd4;
252	} __packed __aligned(4);
253
254	struct mtk_eth;
255	struct mtk_mac;
256
257	/* struct mtk_hw_stats - the structure that holds the traffic statistics.
258	* @stats_lock: make sure that stats operations are atomic
259	* @reg_offset: the status register offset of the SoC
260	* @syncp: the refcount
261	*
262	* All of the supported SoCs have hardware counters for traffic statistics.
263	* Whenever the status IRQ triggers we can read the latest stats from these
264	* counters and store them in this struct.
265	*/
266	struct mtk_hw_stats {
267	u64 tx_bytes;
268	u64 tx_packets;
269	u64 tx_skip;
270	u64 tx_collisions;
271	u64 rx_bytes;
272	u64 rx_packets;
273	u64 rx_overflow;
274	u64 rx_fcs_errors;
275	u64 rx_short_errors;
276	u64 rx_long_errors;
277	u64 rx_checksum_errors;
278	u64 rx_flow_control_packets;
279
280	spinlock_t stats_lock;
281	u32 reg_offset;
282	struct u64_stats_sync syncp;
283	};
284
285	/* PDMA descriptor can point at 1-2 segments. This enum allows us to track how
286	* memory was allocated so that it can be freed properly
287	*/
288	enum mtk_tx_flags {
289	MTK_TX_FLAGS_SINGLE0 = 0x01,
290	MTK_TX_FLAGS_PAGE0 = 0x02,
291	};
292
549e5495 SW	293	/* This enum allows us to identify how the clock is defined on the array of the
	294	* clock in the order
	295	*/
	296	enum mtk_clks_map {
	297	MTK_CLK_ETHIF,
	298	MTK_CLK_ESW,
	299	MTK_CLK_GP1,
	300	MTK_CLK_GP2,
	301	MTK_CLK_MAX
	302	};
	303
656e7052 JC	304	/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
	305	* by the TX descriptor s
	306	* @skb: The SKB pointer of the packet being sent
	307	* @dma_addr0: The base addr of the first segment
	308	* @dma_len0: The length of the first segment
	309	* @dma_addr1: The base addr of the second segment
	310	* @dma_len1: The length of the second segment
	311	*/
	312	struct mtk_tx_buf {
	313	struct sk_buff *skb;
	314	u32 flags;
	315	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
	316	DEFINE_DMA_UNMAP_LEN(dma_len0);
	317	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
	318	DEFINE_DMA_UNMAP_LEN(dma_len1);
	319	};
	320
	321	/* struct mtk_tx_ring - This struct holds info describing a TX ring
	322	* @dma: The descriptor ring
	323	* @buf: The memory pointed at by the ring
	324	* @phys: The physical addr of tx_buf
	325	* @next_free: Pointer to the next free descriptor
	326	* @last_free: Pointer to the last free descriptor
	327	* @thresh: The threshold of minimum amount of free descriptors
	328	* @free_count: QDMA uses a linked list. Track how many free descriptors
	329	* are present
	330	*/
	331	struct mtk_tx_ring {
	332	struct mtk_tx_dma *dma;
	333	struct mtk_tx_buf *buf;
	334	dma_addr_t phys;
	335	struct mtk_tx_dma *next_free;
	336	struct mtk_tx_dma *last_free;
	337	u16 thresh;
	338	atomic_t free_count;
	339	};
	340
	341	/* struct mtk_rx_ring - This struct holds info describing a RX ring
	342	* @dma: The descriptor ring
	343	* @data: The memory pointed at by the ring
	344	* @phys: The physical addr of rx_buf
	345	* @frag_size: How big can each fragment be
	346	* @buf_size: The size of each packet buffer
	347	* @calc_idx: The current head of ring
	348	*/
	349	struct mtk_rx_ring {
	350	struct mtk_rx_dma *dma;
	351	u8 **data;
	352	dma_addr_t phys;
	353	u16 frag_size;
	354	u16 buf_size;
	355	u16 calc_idx;
	356	};
	357
	358	/* currently no SoC has more than 2 macs */
	359	#define MTK_MAX_DEVS 2
	360
	361	/* struct mtk_eth - This is the main datasructure for holding the state
	362	* of the driver
	363	* @dev: The device pointer
	364	* @base: The mapped register i/o base
	365	* @page_lock: Make sure that register operations are atomic
	366	* @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
	367	* dummy for NAPI to work
368	* @netdev: The netdev instances
369	* @mac: Each netdev is linked to a physical MAC
370	* @irq: The IRQ that we are using
371	* @msg_enable: Ethtool msg level
372	* @ethsys: The register map pointing at the range used to setup
373	* MII modes
374	* @pctl: The register map pointing at the range used to setup
375	* GMAC port drive/slew values
376	* @dma_refcnt: track how many netdevs are using the DMA engine
377	* @tx_ring: Pointer to the memore holding info about the TX ring
378	* @rx_ring: Pointer to the memore holding info about the RX ring
80673029 JC	379	* @tx_napi: The TX NAPI struct
80673029 JC	380	* @rx_napi: The RX NAPI struct
656e7052	381	* @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
605e4fe4	382	* @phy_scratch_ring: physical address of scratch_ring
656e7052	383	* @scratch_head: The scratch memory that scratch_ring points to.
549e5495	384	* @clks: clock array for all clocks required
656e7052	385	* @mii_bus: If there is a bus we need to create an instance for it
7c78b4ad	386	* @pending_work: The workqueue used to reset the dma ring
656e7052 JC	387	*/
	388
	389	struct mtk_eth {
	390	struct device *dev;
	391	void __iomem *base;
	392	struct reset_control *rstc;
	393	spinlock_t page_lock;
7bc9ccec	394	spinlock_t irq_lock;
656e7052 JC	395	struct net_device dummy_dev;
	396	struct net_device *netdev[MTK_MAX_DEVS];
	397	struct mtk_mac *mac[MTK_MAX_DEVS];
80673029	398	int irq[3];
656e7052 JC	399	u32 msg_enable;
	400	unsigned long sysclk;
	401	struct regmap *ethsys;
	402	struct regmap *pctl;
	403	atomic_t dma_refcnt;
	404	struct mtk_tx_ring tx_ring;
	405	struct mtk_rx_ring rx_ring;
80673029	406	struct napi_struct tx_napi;
656e7052 JC	407	struct napi_struct rx_napi;
656e7052 JC	408	struct mtk_tx_dma *scratch_ring;
605e4fe4	409	dma_addr_t phy_scratch_ring;
656e7052	410	void *scratch_head;
549e5495 SW	411	struct clk *clks[MTK_CLK_MAX];
549e5495 SW	412
656e7052	413	struct mii_bus *mii_bus;
7c78b4ad	414	struct work_struct pending_work;
656e7052 JC	415	};
	416
	417	/* struct mtk_mac - the structure that holds the info about the MACs of the
	418	* SoC
	419	* @id: The number of the MAC
	420	* @of_node: Our devicetree node
	421	* @hw: Backpointer to our main datastruture
	422	* @hw_stats: Packet statistics counter
	423	* @phy_dev: The attached PHY if available
656e7052 JC	424	*/
	425	struct mtk_mac {
	426	int id;
	427	struct device_node *of_node;
	428	struct mtk_eth *hw;
	429	struct mtk_hw_stats *hw_stats;
	430	struct phy_device *phy_dev;
656e7052 JC	431	};
	432
	433	/* the struct describing the SoC. these are declared in the soc_xyz.c files */
	434	extern const struct of_device_id of_mtk_match[];
	435
	436	/* read the hardware status register */
	437	void mtk_stats_update_mac(struct mtk_mac *mac);
	438
	439	void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
	440	u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
	441
	442	#endif /* MTK_ETH_H */