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8e8e69d6 TG |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* | |
656e7052 JC |
3 | * |
4 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> | |
5 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> | |
6 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> | |
7 | */ | |
8 | ||
9 | #ifndef MTK_ETH_H | |
10 | #define MTK_ETH_H | |
11 | ||
9ffee4a8 SW |
12 | #include <linux/dma-mapping.h> |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/of_net.h> | |
15 | #include <linux/u64_stats_sync.h> | |
c6d4e63e | 16 | #include <linux/refcount.h> |
b8fc9f30 | 17 | #include <linux/phylink.h> |
502e84e2 | 18 | #include <linux/rhashtable.h> |
ba37b7ca | 19 | #include "mtk_ppe.h" |
c6d4e63e | 20 | |
656e7052 | 21 | #define MTK_QDMA_PAGE_SIZE 2048 |
4fd59792 DQ |
22 | #define MTK_MAX_RX_LENGTH 1536 |
23 | #define MTK_MAX_RX_LENGTH_2K 2048 | |
656e7052 | 24 | #define MTK_TX_DMA_BUF_LEN 0x3fff |
6b4423b2 | 25 | #define MTK_DMA_SIZE 512 |
656e7052 JC |
26 | #define MTK_NAPI_WEIGHT 64 |
27 | #define MTK_MAC_COUNT 2 | |
4fd59792 | 28 | #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) |
656e7052 JC |
29 | #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) |
30 | #define MTK_DMA_DUMMY_DESC 0xffffffff | |
31 | #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ | |
32 | NETIF_MSG_PROBE | \ | |
33 | NETIF_MSG_LINK | \ | |
34 | NETIF_MSG_TIMER | \ | |
35 | NETIF_MSG_IFDOWN | \ | |
36 | NETIF_MSG_IFUP | \ | |
37 | NETIF_MSG_RX_ERR | \ | |
38 | NETIF_MSG_TX_ERR) | |
39 | #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ | |
40 | NETIF_F_RXCSUM | \ | |
41 | NETIF_F_HW_VLAN_CTAG_TX | \ | |
42 | NETIF_F_HW_VLAN_CTAG_RX | \ | |
43 | NETIF_F_SG | NETIF_F_TSO | \ | |
44 | NETIF_F_TSO6 | \ | |
502e84e2 FF |
45 | NETIF_F_IPV6_CSUM |\ |
46 | NETIF_F_HW_TC) | |
296c9120 | 47 | #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) |
08df5fa6 | 48 | #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) |
ee406810 NC |
49 | |
50 | #define MTK_MAX_RX_RING_NUM 4 | |
51 | #define MTK_HW_LRO_DMA_SIZE 8 | |
52 | ||
53 | #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) | |
54 | #define MTK_MAX_LRO_IP_CNT 2 | |
55 | #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ | |
56 | #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ | |
57 | #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ | |
58 | #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ | |
59 | #define MTK_HW_LRO_MAX_AGG_CNT 64 | |
60 | #define MTK_HW_LRO_BW_THRE 3000 | |
61 | #define MTK_HW_LRO_REPLACE_DELTA 1000 | |
62 | #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 | |
656e7052 JC |
63 | |
64 | /* Frame Engine Global Reset Register */ | |
65 | #define MTK_RST_GL 0x04 | |
66 | #define RST_GL_PSE BIT(0) | |
67 | ||
68 | /* Frame Engine Interrupt Status Register */ | |
69 | #define MTK_INT_STATUS2 0x08 | |
70 | #define MTK_GDM1_AF BIT(28) | |
71 | #define MTK_GDM2_AF BIT(29) | |
72 | ||
ee406810 NC |
73 | /* PDMA HW LRO Alter Flow Timer Register */ |
74 | #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c | |
75 | ||
656e7052 JC |
76 | /* Frame Engine Interrupt Grouping Register */ |
77 | #define MTK_FE_INT_GRP 0x20 | |
78 | ||
87e3df49 SW |
79 | /* CDMP Ingress Control Register */ |
80 | #define MTK_CDMQ_IG_CTRL 0x1400 | |
81 | #define MTK_CDMQ_STAG_EN BIT(0) | |
82 | ||
656e7052 JC |
83 | /* CDMP Exgress Control Register */ |
84 | #define MTK_CDMP_EG_CTRL 0x404 | |
85 | ||
86 | /* GDM Exgress Control Register */ | |
87 | #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) | |
d5c53da2 | 88 | #define MTK_GDMA_SPECIAL_TAG BIT(24) |
656e7052 JC |
89 | #define MTK_GDMA_ICS_EN BIT(22) |
90 | #define MTK_GDMA_TCS_EN BIT(21) | |
91 | #define MTK_GDMA_UCS_EN BIT(20) | |
8d3f4a95 | 92 | #define MTK_GDMA_TO_PDMA 0x0 |
ba37b7ca | 93 | #define MTK_GDMA_TO_PPE 0x4444 |
8d66a818 | 94 | #define MTK_GDMA_DROP_ALL 0x7777 |
656e7052 JC |
95 | |
96 | /* Unicast Filter MAC Address Register - Low */ | |
97 | #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) | |
98 | ||
99 | /* Unicast Filter MAC Address Register - High */ | |
100 | #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) | |
101 | ||
bacfd110 NC |
102 | /* PDMA RX Base Pointer Register */ |
103 | #define MTK_PRX_BASE_PTR0 0x900 | |
ee406810 | 104 | #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) |
bacfd110 NC |
105 | |
106 | /* PDMA RX Maximum Count Register */ | |
107 | #define MTK_PRX_MAX_CNT0 0x904 | |
ee406810 | 108 | #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) |
bacfd110 NC |
109 | |
110 | /* PDMA RX CPU Pointer Register */ | |
111 | #define MTK_PRX_CRX_IDX0 0x908 | |
ee406810 NC |
112 | #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) |
113 | ||
114 | /* PDMA HW LRO Control Registers */ | |
115 | #define MTK_PDMA_LRO_CTRL_DW0 0x980 | |
116 | #define MTK_LRO_EN BIT(0) | |
117 | #define MTK_L3_CKS_UPD_EN BIT(7) | |
118 | #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) | |
ca3ba106 NC |
119 | #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) |
120 | #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) | |
ee406810 NC |
121 | |
122 | #define MTK_PDMA_LRO_CTRL_DW1 0x984 | |
123 | #define MTK_PDMA_LRO_CTRL_DW2 0x988 | |
124 | #define MTK_PDMA_LRO_CTRL_DW3 0x98c | |
125 | #define MTK_ADMA_MODE BIT(15) | |
126 | #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) | |
bacfd110 NC |
127 | |
128 | /* PDMA Global Configuration Register */ | |
129 | #define MTK_PDMA_GLO_CFG 0xa04 | |
130 | #define MTK_MULTI_EN BIT(10) | |
296c9120 | 131 | #define MTK_PDMA_SIZE_8DWORDS (1 << 4) |
bacfd110 NC |
132 | |
133 | /* PDMA Reset Index Register */ | |
134 | #define MTK_PDMA_RST_IDX 0xa08 | |
135 | #define MTK_PST_DRX_IDX0 BIT(16) | |
ee406810 | 136 | #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) |
bacfd110 NC |
137 | |
138 | /* PDMA Delay Interrupt Register */ | |
671d41e6 JC |
139 | #define MTK_PDMA_DELAY_INT 0xa0c |
140 | #define MTK_PDMA_DELAY_RX_EN BIT(15) | |
141 | #define MTK_PDMA_DELAY_RX_PINT 4 | |
142 | #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 | |
143 | #define MTK_PDMA_DELAY_RX_PTIME 4 | |
144 | #define MTK_PDMA_DELAY_RX_DELAY \ | |
145 | (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ | |
146 | (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) | |
bacfd110 NC |
147 | |
148 | /* PDMA Interrupt Status Register */ | |
149 | #define MTK_PDMA_INT_STATUS 0xa20 | |
150 | ||
151 | /* PDMA Interrupt Mask Register */ | |
152 | #define MTK_PDMA_INT_MASK 0xa28 | |
153 | ||
ee406810 NC |
154 | /* PDMA HW LRO Alter Flow Delta Register */ |
155 | #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c | |
156 | ||
80673029 JC |
157 | /* PDMA Interrupt grouping registers */ |
158 | #define MTK_PDMA_INT_GRP1 0xa50 | |
159 | #define MTK_PDMA_INT_GRP2 0xa54 | |
160 | ||
ee406810 NC |
161 | /* PDMA HW LRO IP Setting Registers */ |
162 | #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 | |
163 | #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) | |
164 | #define MTK_RING_MYIP_VLD BIT(9) | |
165 | ||
166 | /* PDMA HW LRO Ring Control Registers */ | |
167 | #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 | |
168 | #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c | |
169 | #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 | |
170 | #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) | |
171 | #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) | |
172 | #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) | |
173 | #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) | |
174 | #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) | |
175 | #define MTK_RING_AUTO_LERAN_MODE (3 << 6) | |
176 | #define MTK_RING_VLD BIT(8) | |
177 | #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) | |
178 | #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) | |
179 | #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) | |
180 | ||
656e7052 JC |
181 | /* QDMA TX Queue Configuration Registers */ |
182 | #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) | |
183 | #define QDMA_RES_THRES 4 | |
184 | ||
185 | /* QDMA TX Queue Scheduler Registers */ | |
186 | #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) | |
187 | ||
188 | /* QDMA RX Base Pointer Register */ | |
189 | #define MTK_QRX_BASE_PTR0 0x1900 | |
190 | ||
191 | /* QDMA RX Maximum Count Register */ | |
192 | #define MTK_QRX_MAX_CNT0 0x1904 | |
193 | ||
194 | /* QDMA RX CPU Pointer Register */ | |
195 | #define MTK_QRX_CRX_IDX0 0x1908 | |
196 | ||
197 | /* QDMA RX DMA Pointer Register */ | |
198 | #define MTK_QRX_DRX_IDX0 0x190C | |
199 | ||
200 | /* QDMA Global Configuration Register */ | |
201 | #define MTK_QDMA_GLO_CFG 0x1A04 | |
202 | #define MTK_RX_2B_OFFSET BIT(31) | |
203 | #define MTK_RX_BT_32DWORDS (3 << 11) | |
6675086d | 204 | #define MTK_NDP_CO_PRO BIT(10) |
656e7052 | 205 | #define MTK_TX_WB_DDONE BIT(6) |
59555a8d | 206 | #define MTK_TX_BT_32DWORDS (3 << 4) |
656e7052 JC |
207 | #define MTK_RX_DMA_BUSY BIT(3) |
208 | #define MTK_TX_DMA_BUSY BIT(1) | |
209 | #define MTK_RX_DMA_EN BIT(2) | |
210 | #define MTK_TX_DMA_EN BIT(0) | |
211 | #define MTK_DMA_BUSY_TIMEOUT HZ | |
212 | ||
213 | /* QDMA Reset Index Register */ | |
214 | #define MTK_QDMA_RST_IDX 0x1A08 | |
656e7052 JC |
215 | |
216 | /* QDMA Delay Interrupt Register */ | |
217 | #define MTK_QDMA_DELAY_INT 0x1A0C | |
218 | ||
219 | /* QDMA Flow Control Register */ | |
220 | #define MTK_QDMA_FC_THRES 0x1A10 | |
221 | #define FC_THRES_DROP_MODE BIT(20) | |
222 | #define FC_THRES_DROP_EN (7 << 16) | |
223 | #define FC_THRES_MIN 0x4444 | |
224 | ||
225 | /* QDMA Interrupt Status Register */ | |
45487403 | 226 | #define MTK_QDMA_INT_STATUS 0x1A18 |
671d41e6 | 227 | #define MTK_RX_DONE_DLY BIT(30) |
bacfd110 NC |
228 | #define MTK_RX_DONE_INT3 BIT(19) |
229 | #define MTK_RX_DONE_INT2 BIT(18) | |
656e7052 JC |
230 | #define MTK_RX_DONE_INT1 BIT(17) |
231 | #define MTK_RX_DONE_INT0 BIT(16) | |
232 | #define MTK_TX_DONE_INT3 BIT(3) | |
233 | #define MTK_TX_DONE_INT2 BIT(2) | |
234 | #define MTK_TX_DONE_INT1 BIT(1) | |
235 | #define MTK_TX_DONE_INT0 BIT(0) | |
671d41e6 | 236 | #define MTK_RX_DONE_INT MTK_RX_DONE_DLY |
656e7052 JC |
237 | #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ |
238 | MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) | |
239 | ||
80673029 JC |
240 | /* QDMA Interrupt grouping registers */ |
241 | #define MTK_QDMA_INT_GRP1 0x1a20 | |
242 | #define MTK_QDMA_INT_GRP2 0x1a24 | |
243 | #define MTK_RLS_DONE_INT BIT(0) | |
244 | ||
656e7052 JC |
245 | /* QDMA Interrupt Status Register */ |
246 | #define MTK_QDMA_INT_MASK 0x1A1C | |
247 | ||
248 | /* QDMA Interrupt Mask Register */ | |
249 | #define MTK_QDMA_HRED2 0x1A44 | |
250 | ||
251 | /* QDMA TX Forward CPU Pointer Register */ | |
252 | #define MTK_QTX_CTX_PTR 0x1B00 | |
253 | ||
254 | /* QDMA TX Forward DMA Pointer Register */ | |
255 | #define MTK_QTX_DTX_PTR 0x1B04 | |
256 | ||
257 | /* QDMA TX Release CPU Pointer Register */ | |
258 | #define MTK_QTX_CRX_PTR 0x1B10 | |
259 | ||
260 | /* QDMA TX Release DMA Pointer Register */ | |
261 | #define MTK_QTX_DRX_PTR 0x1B14 | |
262 | ||
263 | /* QDMA FQ Head Pointer Register */ | |
264 | #define MTK_QDMA_FQ_HEAD 0x1B20 | |
265 | ||
266 | /* QDMA FQ Head Pointer Register */ | |
267 | #define MTK_QDMA_FQ_TAIL 0x1B24 | |
268 | ||
269 | /* QDMA FQ Free Page Counter Register */ | |
270 | #define MTK_QDMA_FQ_CNT 0x1B28 | |
271 | ||
272 | /* QDMA FQ Free Page Buffer Length Register */ | |
273 | #define MTK_QDMA_FQ_BLEN 0x1B2C | |
274 | ||
275 | /* GMA1 Received Good Byte Count Register */ | |
276 | #define MTK_GDM1_TX_GBCNT 0x2400 | |
277 | #define MTK_STAT_OFFSET 0x40 | |
278 | ||
279 | /* QDMA descriptor txd4 */ | |
280 | #define TX_DMA_CHKSUM (0x7 << 29) | |
281 | #define TX_DMA_TSO BIT(28) | |
282 | #define TX_DMA_FPORT_SHIFT 25 | |
283 | #define TX_DMA_FPORT_MASK 0x7 | |
284 | #define TX_DMA_INS_VLAN BIT(16) | |
285 | ||
286 | /* QDMA descriptor txd3 */ | |
287 | #define TX_DMA_OWNER_CPU BIT(31) | |
288 | #define TX_DMA_LS0 BIT(30) | |
289 | #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) | |
296c9120 | 290 | #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) |
656e7052 JC |
291 | #define TX_DMA_SWC BIT(14) |
292 | #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) | |
293 | ||
296c9120 SR |
294 | /* PDMA on MT7628 */ |
295 | #define TX_DMA_DONE BIT(31) | |
296 | #define TX_DMA_LS1 BIT(14) | |
297 | #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) | |
298 | ||
656e7052 JC |
299 | /* QDMA descriptor rxd2 */ |
300 | #define RX_DMA_DONE BIT(31) | |
296c9120 | 301 | #define RX_DMA_LSO BIT(30) |
656e7052 JC |
302 | #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) |
303 | #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) | |
3f57d8c4 | 304 | #define RX_DMA_VTAG BIT(15) |
656e7052 JC |
305 | |
306 | /* QDMA descriptor rxd3 */ | |
307 | #define RX_DMA_VID(_x) ((_x) & 0xfff) | |
308 | ||
ba37b7ca FF |
309 | /* QDMA descriptor rxd4 */ |
310 | #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) | |
311 | #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) | |
312 | #define MTK_RXD4_SRC_PORT GENMASK(21, 19) | |
313 | #define MTK_RXD4_ALG GENMASK(31, 22) | |
314 | ||
656e7052 JC |
315 | /* QDMA descriptor rxd4 */ |
316 | #define RX_DMA_L4_VALID BIT(24) | |
296c9120 | 317 | #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ |
656e7052 JC |
318 | #define RX_DMA_FPORT_SHIFT 19 |
319 | #define RX_DMA_FPORT_MASK 0x7 | |
d5c53da2 | 320 | #define RX_DMA_SPECIAL_TAG BIT(22) |
656e7052 JC |
321 | |
322 | /* PHY Indirect Access Control registers */ | |
323 | #define MTK_PHY_IAC 0x10004 | |
324 | #define PHY_IAC_ACCESS BIT(31) | |
325 | #define PHY_IAC_READ BIT(19) | |
326 | #define PHY_IAC_WRITE BIT(18) | |
327 | #define PHY_IAC_START BIT(16) | |
328 | #define PHY_IAC_ADDR_SHIFT 20 | |
329 | #define PHY_IAC_REG_SHIFT 25 | |
330 | #define PHY_IAC_TIMEOUT HZ | |
331 | ||
42c03844 SW |
332 | #define MTK_MAC_MISC 0x1000c |
333 | #define MTK_MUX_TO_ESW BIT(0) | |
334 | ||
656e7052 JC |
335 | /* Mac control registers */ |
336 | #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) | |
4fd59792 DQ |
337 | #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) |
338 | #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) | |
339 | #define MAC_MCR_MAX_RX_1518 0x0 | |
340 | #define MAC_MCR_MAX_RX_1536 0x1 | |
341 | #define MAC_MCR_MAX_RX_1552 0x2 | |
342 | #define MAC_MCR_MAX_RX_2048 0x3 | |
656e7052 JC |
343 | #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) |
344 | #define MAC_MCR_FORCE_MODE BIT(15) | |
345 | #define MAC_MCR_TX_EN BIT(14) | |
346 | #define MAC_MCR_RX_EN BIT(13) | |
347 | #define MAC_MCR_BACKOFF_EN BIT(9) | |
348 | #define MAC_MCR_BACKPR_EN BIT(8) | |
349 | #define MAC_MCR_FORCE_RX_FC BIT(5) | |
350 | #define MAC_MCR_FORCE_TX_FC BIT(4) | |
351 | #define MAC_MCR_SPEED_1000 BIT(3) | |
352 | #define MAC_MCR_SPEED_100 BIT(2) | |
353 | #define MAC_MCR_FORCE_DPX BIT(1) | |
354 | #define MAC_MCR_FORCE_LINK BIT(0) | |
b8fc9f30 RD |
355 | #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) |
356 | ||
357 | /* Mac status registers */ | |
358 | #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) | |
359 | #define MAC_MSR_EEE1G BIT(7) | |
360 | #define MAC_MSR_EEE100M BIT(6) | |
361 | #define MAC_MSR_RX_FC BIT(5) | |
362 | #define MAC_MSR_TX_FC BIT(4) | |
363 | #define MAC_MSR_SPEED_1000 BIT(3) | |
364 | #define MAC_MSR_SPEED_100 BIT(2) | |
365 | #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) | |
366 | #define MAC_MSR_DPX BIT(1) | |
367 | #define MAC_MSR_LINK BIT(0) | |
656e7052 | 368 | |
f430dea7 SW |
369 | /* TRGMII RXC control register */ |
370 | #define TRGMII_RCK_CTRL 0x10300 | |
371 | #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) | |
372 | #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) | |
373 | #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) | |
a5d75538 | 374 | #define RXC_RST BIT(31) |
f430dea7 SW |
375 | #define RXC_DQSISEL BIT(30) |
376 | #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) | |
377 | #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) | |
378 | ||
a5d75538 RD |
379 | #define NUM_TRGMII_CTRL 5 |
380 | ||
f430dea7 SW |
381 | /* TRGMII RXC control register */ |
382 | #define TRGMII_TCK_CTRL 0x10340 | |
383 | #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) | |
384 | #define TXC_INV BIT(30) | |
385 | #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) | |
386 | #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) | |
387 | ||
a5d75538 RD |
388 | /* TRGMII TX Drive Strength */ |
389 | #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) | |
390 | #define TD_DM_DRVP(x) ((x) & 0xf) | |
391 | #define TD_DM_DRVN(x) (((x) & 0xf) << 4) | |
392 | ||
f430dea7 SW |
393 | /* TRGMII Interface mode register */ |
394 | #define INTF_MODE 0x10390 | |
395 | #define TRGMII_INTF_DIS BIT(0) | |
396 | #define TRGMII_MODE BIT(1) | |
397 | #define TRGMII_CENTRAL_ALIGNED BIT(2) | |
398 | #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) | |
399 | #define INTF_MODE_RGMII_10_100 0 | |
400 | ||
656e7052 JC |
401 | /* GPIO port control registers for GMAC 2*/ |
402 | #define GPIO_OD33_CTRL8 0x4c0 | |
403 | #define GPIO_BIAS_CTRL 0xed0 | |
404 | #define GPIO_DRV_SEL10 0xf00 | |
405 | ||
b95b6d99 NC |
406 | /* ethernet subsystem chip id register */ |
407 | #define ETHSYS_CHIPID0_3 0x0 | |
408 | #define ETHSYS_CHIPID4_7 0x4 | |
983e1a6c | 409 | #define MT7623_ETH 7623 |
42c03844 | 410 | #define MT7622_ETH 7622 |
889bcbde | 411 | #define MT7621_ETH 7621 |
b95b6d99 | 412 | |
8efaa653 RD |
413 | /* ethernet system control register */ |
414 | #define ETHSYS_SYSCFG 0x10 | |
415 | #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) | |
416 | ||
656e7052 JC |
417 | /* ethernet subsystem config register */ |
418 | #define ETHSYS_SYSCFG0 0x14 | |
419 | #define SYSCFG0_GE_MASK 0x3 | |
420 | #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) | |
7093f9d8 SW |
421 | #define SYSCFG0_SGMII_MASK GENMASK(9, 8) |
422 | #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) | |
423 | #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) | |
424 | #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) | |
425 | #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) | |
426 | ||
656e7052 | 427 | |
f430dea7 SW |
428 | /* ethernet subsystem clock register */ |
429 | #define ETHSYS_CLKCFG0 0x2c | |
430 | #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) | |
8efaa653 RD |
431 | #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) |
432 | #define ETHSYS_TRGMII_MT7621_APLL BIT(6) | |
433 | #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) | |
f430dea7 SW |
434 | |
435 | /* ethernet reset control register */ | |
2a8307aa SW |
436 | #define ETHSYS_RSTCTRL 0x34 |
437 | #define RSTCTRL_FE BIT(6) | |
438 | #define RSTCTRL_PPE BIT(31) | |
439 | ||
42c03844 SW |
440 | /* SGMII subsystem config registers */ |
441 | /* Register to auto-negotiation restart */ | |
442 | #define SGMSYS_PCS_CONTROL_1 0x0 | |
443 | #define SGMII_AN_RESTART BIT(9) | |
7e538372 RD |
444 | #define SGMII_ISOLATE BIT(10) |
445 | #define SGMII_AN_ENABLE BIT(12) | |
446 | #define SGMII_LINK_STATYS BIT(18) | |
447 | #define SGMII_AN_ABILITY BIT(19) | |
448 | #define SGMII_AN_COMPLETE BIT(21) | |
449 | #define SGMII_PCS_FAULT BIT(23) | |
450 | #define SGMII_AN_EXPANSION_CLR BIT(30) | |
42c03844 SW |
451 | |
452 | /* Register to programmable link timer, the unit in 2 * 8ns */ | |
453 | #define SGMSYS_PCS_LINK_TIMER 0x18 | |
454 | #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) | |
455 | ||
456 | /* Register to control remote fault */ | |
7e538372 RD |
457 | #define SGMSYS_SGMII_MODE 0x20 |
458 | #define SGMII_IF_MODE_BIT0 BIT(0) | |
459 | #define SGMII_SPEED_DUPLEX_AN BIT(1) | |
460 | #define SGMII_SPEED_10 0x0 | |
461 | #define SGMII_SPEED_100 BIT(2) | |
462 | #define SGMII_SPEED_1000 BIT(3) | |
463 | #define SGMII_DUPLEX_FULL BIT(4) | |
464 | #define SGMII_IF_MODE_BIT5 BIT(5) | |
465 | #define SGMII_REMOTE_FAULT_DIS BIT(8) | |
466 | #define SGMII_CODE_SYNC_SET_VAL BIT(9) | |
467 | #define SGMII_CODE_SYNC_SET_EN BIT(10) | |
468 | #define SGMII_SEND_AN_ERROR_EN BIT(11) | |
469 | #define SGMII_IF_MODE_MASK GENMASK(5, 1) | |
470 | ||
471 | /* Register to set SGMII speed, ANA RG_ Control Signals III*/ | |
472 | #define SGMSYS_ANA_RG_CS3 0x2028 | |
473 | #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) | |
474 | #define RG_PHY_SPEED_1_25G 0x0 | |
475 | #define RG_PHY_SPEED_3_125G BIT(2) | |
42c03844 SW |
476 | |
477 | /* Register to power up QPHY */ | |
478 | #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 | |
479 | #define SGMII_PHYA_PWD BIT(4) | |
480 | ||
7093f9d8 SW |
481 | /* Infrasys subsystem config registers */ |
482 | #define INFRA_MISC2 0x70c | |
483 | #define CO_QPHY_SEL BIT(0) | |
484 | #define GEPHY_MAC_SEL BIT(1) | |
485 | ||
296c9120 SR |
486 | /* MT7628/88 specific stuff */ |
487 | #define MT7628_PDMA_OFFSET 0x0800 | |
488 | #define MT7628_SDM_OFFSET 0x0c00 | |
489 | ||
490 | #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) | |
491 | #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) | |
492 | #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) | |
493 | #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) | |
494 | #define MT7628_PST_DTX_IDX0 BIT(0) | |
495 | ||
496 | #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) | |
497 | #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) | |
498 | ||
656e7052 JC |
499 | struct mtk_rx_dma { |
500 | unsigned int rxd1; | |
501 | unsigned int rxd2; | |
502 | unsigned int rxd3; | |
503 | unsigned int rxd4; | |
504 | } __packed __aligned(4); | |
505 | ||
506 | struct mtk_tx_dma { | |
507 | unsigned int txd1; | |
508 | unsigned int txd2; | |
509 | unsigned int txd3; | |
510 | unsigned int txd4; | |
511 | } __packed __aligned(4); | |
512 | ||
513 | struct mtk_eth; | |
514 | struct mtk_mac; | |
515 | ||
516 | /* struct mtk_hw_stats - the structure that holds the traffic statistics. | |
517 | * @stats_lock: make sure that stats operations are atomic | |
518 | * @reg_offset: the status register offset of the SoC | |
519 | * @syncp: the refcount | |
520 | * | |
521 | * All of the supported SoCs have hardware counters for traffic statistics. | |
522 | * Whenever the status IRQ triggers we can read the latest stats from these | |
523 | * counters and store them in this struct. | |
524 | */ | |
525 | struct mtk_hw_stats { | |
526 | u64 tx_bytes; | |
527 | u64 tx_packets; | |
528 | u64 tx_skip; | |
529 | u64 tx_collisions; | |
530 | u64 rx_bytes; | |
531 | u64 rx_packets; | |
532 | u64 rx_overflow; | |
533 | u64 rx_fcs_errors; | |
534 | u64 rx_short_errors; | |
535 | u64 rx_long_errors; | |
536 | u64 rx_checksum_errors; | |
537 | u64 rx_flow_control_packets; | |
538 | ||
539 | spinlock_t stats_lock; | |
540 | u32 reg_offset; | |
541 | struct u64_stats_sync syncp; | |
542 | }; | |
543 | ||
656e7052 | 544 | enum mtk_tx_flags { |
134d2152 SW |
545 | /* PDMA descriptor can point at 1-2 segments. This enum allows us to |
546 | * track how memory was allocated so that it can be freed properly. | |
547 | */ | |
656e7052 JC |
548 | MTK_TX_FLAGS_SINGLE0 = 0x01, |
549 | MTK_TX_FLAGS_PAGE0 = 0x02, | |
134d2152 SW |
550 | |
551 | /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted | |
552 | * SKB out instead of looking up through hardware TX descriptor. | |
553 | */ | |
554 | MTK_TX_FLAGS_FPORT0 = 0x04, | |
555 | MTK_TX_FLAGS_FPORT1 = 0x08, | |
656e7052 JC |
556 | }; |
557 | ||
549e5495 SW |
558 | /* This enum allows us to identify how the clock is defined on the array of the |
559 | * clock in the order | |
560 | */ | |
561 | enum mtk_clks_map { | |
562 | MTK_CLK_ETHIF, | |
d438e298 | 563 | MTK_CLK_SGMIITOP, |
549e5495 | 564 | MTK_CLK_ESW, |
42c03844 | 565 | MTK_CLK_GP0, |
549e5495 SW |
566 | MTK_CLK_GP1, |
567 | MTK_CLK_GP2, | |
d438e298 | 568 | MTK_CLK_FE, |
f430dea7 | 569 | MTK_CLK_TRGPLL, |
42c03844 SW |
570 | MTK_CLK_SGMII_TX_250M, |
571 | MTK_CLK_SGMII_RX_250M, | |
572 | MTK_CLK_SGMII_CDR_REF, | |
573 | MTK_CLK_SGMII_CDR_FB, | |
d438e298 SW |
574 | MTK_CLK_SGMII2_TX_250M, |
575 | MTK_CLK_SGMII2_RX_250M, | |
576 | MTK_CLK_SGMII2_CDR_REF, | |
577 | MTK_CLK_SGMII2_CDR_FB, | |
42c03844 SW |
578 | MTK_CLK_SGMII_CK, |
579 | MTK_CLK_ETH2PLL, | |
549e5495 SW |
580 | MTK_CLK_MAX |
581 | }; | |
582 | ||
2ec50f57 SW |
583 | #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
584 | BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ | |
585 | BIT(MTK_CLK_TRGPLL)) | |
42c03844 SW |
586 | #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
587 | BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ | |
588 | BIT(MTK_CLK_GP2) | \ | |
589 | BIT(MTK_CLK_SGMII_TX_250M) | \ | |
590 | BIT(MTK_CLK_SGMII_RX_250M) | \ | |
591 | BIT(MTK_CLK_SGMII_CDR_REF) | \ | |
592 | BIT(MTK_CLK_SGMII_CDR_FB) | \ | |
593 | BIT(MTK_CLK_SGMII_CK) | \ | |
594 | BIT(MTK_CLK_ETH2PLL)) | |
889bcbde | 595 | #define MT7621_CLKS_BITMAP (0) |
296c9120 | 596 | #define MT7628_CLKS_BITMAP (0) |
d438e298 SW |
597 | #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
598 | BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ | |
599 | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ | |
600 | BIT(MTK_CLK_SGMII_TX_250M) | \ | |
601 | BIT(MTK_CLK_SGMII_RX_250M) | \ | |
602 | BIT(MTK_CLK_SGMII_CDR_REF) | \ | |
603 | BIT(MTK_CLK_SGMII_CDR_FB) | \ | |
604 | BIT(MTK_CLK_SGMII2_TX_250M) | \ | |
605 | BIT(MTK_CLK_SGMII2_RX_250M) | \ | |
606 | BIT(MTK_CLK_SGMII2_CDR_REF) | \ | |
607 | BIT(MTK_CLK_SGMII2_CDR_FB) | \ | |
608 | BIT(MTK_CLK_SGMII_CK) | \ | |
609 | BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) | |
889bcbde | 610 | |
9ea4d311 | 611 | enum mtk_dev_state { |
dce6fa42 SW |
612 | MTK_HW_INIT, |
613 | MTK_RESETTING | |
9ea4d311 SW |
614 | }; |
615 | ||
656e7052 JC |
616 | /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at |
617 | * by the TX descriptor s | |
618 | * @skb: The SKB pointer of the packet being sent | |
619 | * @dma_addr0: The base addr of the first segment | |
620 | * @dma_len0: The length of the first segment | |
621 | * @dma_addr1: The base addr of the second segment | |
622 | * @dma_len1: The length of the second segment | |
623 | */ | |
624 | struct mtk_tx_buf { | |
625 | struct sk_buff *skb; | |
626 | u32 flags; | |
627 | DEFINE_DMA_UNMAP_ADDR(dma_addr0); | |
628 | DEFINE_DMA_UNMAP_LEN(dma_len0); | |
629 | DEFINE_DMA_UNMAP_ADDR(dma_addr1); | |
630 | DEFINE_DMA_UNMAP_LEN(dma_len1); | |
631 | }; | |
632 | ||
633 | /* struct mtk_tx_ring - This struct holds info describing a TX ring | |
634 | * @dma: The descriptor ring | |
635 | * @buf: The memory pointed at by the ring | |
636 | * @phys: The physical addr of tx_buf | |
637 | * @next_free: Pointer to the next free descriptor | |
638 | * @last_free: Pointer to the last free descriptor | |
639 | * @thresh: The threshold of minimum amount of free descriptors | |
640 | * @free_count: QDMA uses a linked list. Track how many free descriptors | |
641 | * are present | |
642 | */ | |
643 | struct mtk_tx_ring { | |
644 | struct mtk_tx_dma *dma; | |
645 | struct mtk_tx_buf *buf; | |
646 | dma_addr_t phys; | |
647 | struct mtk_tx_dma *next_free; | |
648 | struct mtk_tx_dma *last_free; | |
649 | u16 thresh; | |
650 | atomic_t free_count; | |
296c9120 SR |
651 | int dma_size; |
652 | struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ | |
653 | dma_addr_t phys_pdma; | |
654 | int cpu_idx; | |
656e7052 JC |
655 | }; |
656 | ||
ee406810 NC |
657 | /* PDMA rx ring mode */ |
658 | enum mtk_rx_flags { | |
659 | MTK_RX_FLAGS_NORMAL = 0, | |
660 | MTK_RX_FLAGS_HWLRO, | |
6427dc1d | 661 | MTK_RX_FLAGS_QDMA, |
ee406810 NC |
662 | }; |
663 | ||
656e7052 JC |
664 | /* struct mtk_rx_ring - This struct holds info describing a RX ring |
665 | * @dma: The descriptor ring | |
666 | * @data: The memory pointed at by the ring | |
667 | * @phys: The physical addr of rx_buf | |
668 | * @frag_size: How big can each fragment be | |
669 | * @buf_size: The size of each packet buffer | |
670 | * @calc_idx: The current head of ring | |
671 | */ | |
672 | struct mtk_rx_ring { | |
673 | struct mtk_rx_dma *dma; | |
674 | u8 **data; | |
675 | dma_addr_t phys; | |
676 | u16 frag_size; | |
677 | u16 buf_size; | |
ee406810 NC |
678 | u16 dma_size; |
679 | bool calc_idx_update; | |
656e7052 | 680 | u16 calc_idx; |
ee406810 | 681 | u32 crx_idx_reg; |
656e7052 JC |
682 | }; |
683 | ||
e2c74694 RD |
684 | enum mkt_eth_capabilities { |
685 | MTK_RGMII_BIT = 0, | |
686 | MTK_TRGMII_BIT, | |
687 | MTK_SGMII_BIT, | |
688 | MTK_ESW_BIT, | |
689 | MTK_GEPHY_BIT, | |
690 | MTK_MUX_BIT, | |
691 | MTK_INFRA_BIT, | |
692 | MTK_SHARED_SGMII_BIT, | |
693 | MTK_HWLRO_BIT, | |
694 | MTK_SHARED_INT_BIT, | |
695 | MTK_TRGMII_MT7621_CLK_BIT, | |
296c9120 SR |
696 | MTK_QDMA_BIT, |
697 | MTK_SOC_MT7628_BIT, | |
e2c74694 RD |
698 | |
699 | /* MUX BITS*/ | |
700 | MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, | |
701 | MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, | |
702 | MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, | |
703 | MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, | |
704 | MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, | |
705 | ||
706 | /* PATH BITS */ | |
707 | MTK_ETH_PATH_GMAC1_RGMII_BIT, | |
708 | MTK_ETH_PATH_GMAC1_TRGMII_BIT, | |
709 | MTK_ETH_PATH_GMAC1_SGMII_BIT, | |
710 | MTK_ETH_PATH_GMAC2_RGMII_BIT, | |
711 | MTK_ETH_PATH_GMAC2_SGMII_BIT, | |
712 | MTK_ETH_PATH_GMAC2_GEPHY_BIT, | |
713 | MTK_ETH_PATH_GDM1_ESW_BIT, | |
7093f9d8 SW |
714 | }; |
715 | ||
716 | /* Supported hardware group on SoCs */ | |
e2c74694 RD |
717 | #define MTK_RGMII BIT(MTK_RGMII_BIT) |
718 | #define MTK_TRGMII BIT(MTK_TRGMII_BIT) | |
719 | #define MTK_SGMII BIT(MTK_SGMII_BIT) | |
720 | #define MTK_ESW BIT(MTK_ESW_BIT) | |
721 | #define MTK_GEPHY BIT(MTK_GEPHY_BIT) | |
722 | #define MTK_MUX BIT(MTK_MUX_BIT) | |
723 | #define MTK_INFRA BIT(MTK_INFRA_BIT) | |
724 | #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) | |
725 | #define MTK_HWLRO BIT(MTK_HWLRO_BIT) | |
726 | #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) | |
727 | #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) | |
296c9120 SR |
728 | #define MTK_QDMA BIT(MTK_QDMA_BIT) |
729 | #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) | |
e2c74694 RD |
730 | |
731 | #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ | |
732 | BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) | |
733 | #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ | |
734 | BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) | |
735 | #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ | |
736 | BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) | |
737 | #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ | |
738 | BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) | |
739 | #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ | |
740 | BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) | |
7093f9d8 SW |
741 | |
742 | /* Supported path present on SoCs */ | |
e2c74694 RD |
743 | #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) |
744 | #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) | |
745 | #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) | |
746 | #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) | |
747 | #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) | |
748 | #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) | |
749 | #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) | |
750 | ||
751 | #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) | |
752 | #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) | |
753 | #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) | |
754 | #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) | |
755 | #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) | |
756 | #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) | |
757 | #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) | |
7093f9d8 SW |
758 | |
759 | /* MUXes present on SoCs */ | |
760 | /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ | |
e2c74694 | 761 | #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) |
7093f9d8 SW |
762 | |
763 | /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ | |
764 | #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ | |
e2c74694 | 765 | (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) |
7093f9d8 SW |
766 | |
767 | /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ | |
768 | #define MTK_MUX_U3_GMAC2_TO_QPHY \ | |
e2c74694 | 769 | (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) |
7093f9d8 SW |
770 | |
771 | /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ | |
772 | #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ | |
e2c74694 | 773 | (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ |
7093f9d8 SW |
774 | MTK_SHARED_SGMII) |
775 | ||
776 | /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ | |
777 | #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ | |
e2c74694 | 778 | (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) |
7093f9d8 | 779 | |
2ec50f57 SW |
780 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) |
781 | ||
8efaa653 | 782 | #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ |
296c9120 SR |
783 | MTK_GMAC2_RGMII | MTK_SHARED_INT | \ |
784 | MTK_TRGMII_MT7621_CLK | MTK_QDMA) | |
8efaa653 | 785 | |
7093f9d8 SW |
786 | #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ |
787 | MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ | |
788 | MTK_MUX_GDM1_TO_GMAC1_ESW | \ | |
296c9120 SR |
789 | MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) |
790 | ||
791 | #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ | |
792 | MTK_QDMA) | |
7093f9d8 | 793 | |
296c9120 | 794 | #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) |
7093f9d8 SW |
795 | |
796 | #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ | |
797 | MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ | |
798 | MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ | |
799 | MTK_MUX_U3_GMAC2_TO_QPHY | \ | |
296c9120 | 800 | MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) |
7093f9d8 | 801 | |
42c03844 | 802 | /* struct mtk_eth_data - This is the structure holding all differences |
2ec50f57 | 803 | * among various plaforms |
9ffee4a8 SW |
804 | * @ana_rgc3: The offset for register ANA_RGC3 related to |
805 | * sgmiisys syscon | |
2ec50f57 | 806 | * @caps Flags shown the extra capability for the SoC |
296c9120 | 807 | * @hw_features Flags shown HW features |
2ec50f57 SW |
808 | * @required_clks Flags shown the bitmap for required clocks on |
809 | * the target SoC | |
243dc5fb SW |
810 | * @required_pctl A bool value to show whether the SoC requires |
811 | * the extra setup for those pins used by GMAC. | |
2ec50f57 SW |
812 | */ |
813 | struct mtk_soc_data { | |
9ffee4a8 | 814 | u32 ana_rgc3; |
2ec50f57 SW |
815 | u32 caps; |
816 | u32 required_clks; | |
243dc5fb | 817 | bool required_pctl; |
ba37b7ca | 818 | u8 offload_version; |
296c9120 | 819 | netdev_features_t hw_features; |
2ec50f57 SW |
820 | }; |
821 | ||
656e7052 JC |
822 | /* currently no SoC has more than 2 macs */ |
823 | #define MTK_MAX_DEVS 2 | |
824 | ||
9ffee4a8 | 825 | #define MTK_SGMII_PHYSPEED_AN BIT(31) |
937a9440 | 826 | #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) |
9ffee4a8 SW |
827 | #define MTK_SGMII_PHYSPEED_1000 BIT(0) |
828 | #define MTK_SGMII_PHYSPEED_2500 BIT(1) | |
829 | #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) | |
830 | ||
831 | /* struct mtk_sgmii - This is the structure holding sgmii regmap and its | |
832 | * characteristics | |
833 | * @regmap: The register map pointing at the range used to setup | |
834 | * SGMII modes | |
835 | * @flags: The enum refers to which mode the sgmii wants to run on | |
836 | * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap | |
837 | */ | |
838 | ||
839 | struct mtk_sgmii { | |
840 | struct regmap *regmap[MTK_MAX_DEVS]; | |
841 | u32 flags[MTK_MAX_DEVS]; | |
842 | u32 ana_rgc3; | |
843 | }; | |
844 | ||
656e7052 JC |
845 | /* struct mtk_eth - This is the main datasructure for holding the state |
846 | * of the driver | |
847 | * @dev: The device pointer | |
848 | * @base: The mapped register i/o base | |
849 | * @page_lock: Make sure that register operations are atomic | |
5cce0322 JC |
850 | * @tx_irq__lock: Make sure that IRQ register operations are atomic |
851 | * @rx_irq__lock: Make sure that IRQ register operations are atomic | |
656e7052 JC |
852 | * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a |
853 | * dummy for NAPI to work | |
854 | * @netdev: The netdev instances | |
855 | * @mac: Each netdev is linked to a physical MAC | |
856 | * @irq: The IRQ that we are using | |
857 | * @msg_enable: Ethtool msg level | |
858 | * @ethsys: The register map pointing at the range used to setup | |
859 | * MII modes | |
7093f9d8 SW |
860 | * @infra: The register map pointing at the range used to setup |
861 | * SGMII and GePHY path | |
656e7052 JC |
862 | * @pctl: The register map pointing at the range used to setup |
863 | * GMAC port drive/slew values | |
864 | * @dma_refcnt: track how many netdevs are using the DMA engine | |
0c07ce7f JC |
865 | * @tx_ring: Pointer to the memory holding info about the TX ring |
866 | * @rx_ring: Pointer to the memory holding info about the RX ring | |
6427dc1d | 867 | * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring |
80673029 JC |
868 | * @tx_napi: The TX NAPI struct |
869 | * @rx_napi: The RX NAPI struct | |
656e7052 | 870 | * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring |
605e4fe4 | 871 | * @phy_scratch_ring: physical address of scratch_ring |
656e7052 | 872 | * @scratch_head: The scratch memory that scratch_ring points to. |
549e5495 | 873 | * @clks: clock array for all clocks required |
656e7052 | 874 | * @mii_bus: If there is a bus we need to create an instance for it |
7c78b4ad | 875 | * @pending_work: The workqueue used to reset the dma ring |
42c03844 | 876 | * @state: Initialization and runtime state of the device |
2ec50f57 | 877 | * @soc: Holding specific data among vaious SoCs |
656e7052 JC |
878 | */ |
879 | ||
880 | struct mtk_eth { | |
881 | struct device *dev; | |
882 | void __iomem *base; | |
656e7052 | 883 | spinlock_t page_lock; |
5cce0322 JC |
884 | spinlock_t tx_irq_lock; |
885 | spinlock_t rx_irq_lock; | |
656e7052 JC |
886 | struct net_device dummy_dev; |
887 | struct net_device *netdev[MTK_MAX_DEVS]; | |
888 | struct mtk_mac *mac[MTK_MAX_DEVS]; | |
80673029 | 889 | int irq[3]; |
656e7052 JC |
890 | u32 msg_enable; |
891 | unsigned long sysclk; | |
892 | struct regmap *ethsys; | |
7093f9d8 | 893 | struct regmap *infra; |
9ffee4a8 | 894 | struct mtk_sgmii *sgmii; |
656e7052 | 895 | struct regmap *pctl; |
ee406810 | 896 | bool hwlro; |
c6d4e63e | 897 | refcount_t dma_refcnt; |
656e7052 | 898 | struct mtk_tx_ring tx_ring; |
ee406810 | 899 | struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; |
6427dc1d | 900 | struct mtk_rx_ring rx_ring_qdma; |
80673029 | 901 | struct napi_struct tx_napi; |
656e7052 JC |
902 | struct napi_struct rx_napi; |
903 | struct mtk_tx_dma *scratch_ring; | |
605e4fe4 | 904 | dma_addr_t phy_scratch_ring; |
656e7052 | 905 | void *scratch_head; |
549e5495 SW |
906 | struct clk *clks[MTK_CLK_MAX]; |
907 | ||
656e7052 | 908 | struct mii_bus *mii_bus; |
7c78b4ad | 909 | struct work_struct pending_work; |
9ea4d311 | 910 | unsigned long state; |
2ec50f57 SW |
911 | |
912 | const struct mtk_soc_data *soc; | |
296c9120 SR |
913 | |
914 | u32 tx_int_mask_reg; | |
915 | u32 tx_int_status_reg; | |
916 | u32 rx_dma_l4_valid; | |
917 | int ip_align; | |
ba37b7ca FF |
918 | |
919 | struct mtk_ppe ppe; | |
502e84e2 | 920 | struct rhashtable flow_table; |
656e7052 JC |
921 | }; |
922 | ||
923 | /* struct mtk_mac - the structure that holds the info about the MACs of the | |
924 | * SoC | |
925 | * @id: The number of the MAC | |
b8fc9f30 | 926 | * @interface: Interface mode kept for detecting change in hw settings |
656e7052 JC |
927 | * @of_node: Our devicetree node |
928 | * @hw: Backpointer to our main datastruture | |
929 | * @hw_stats: Packet statistics counter | |
656e7052 JC |
930 | */ |
931 | struct mtk_mac { | |
932 | int id; | |
b8fc9f30 RD |
933 | phy_interface_t interface; |
934 | unsigned int mode; | |
935 | int speed; | |
656e7052 | 936 | struct device_node *of_node; |
b8fc9f30 RD |
937 | struct phylink *phylink; |
938 | struct phylink_config phylink_config; | |
656e7052 JC |
939 | struct mtk_eth *hw; |
940 | struct mtk_hw_stats *hw_stats; | |
ee406810 NC |
941 | __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; |
942 | int hwlro_ip_cnt; | |
656e7052 JC |
943 | }; |
944 | ||
945 | /* the struct describing the SoC. these are declared in the soc_xyz.c files */ | |
946 | extern const struct of_device_id of_mtk_match[]; | |
947 | ||
948 | /* read the hardware status register */ | |
949 | void mtk_stats_update_mac(struct mtk_mac *mac); | |
950 | ||
951 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); | |
952 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg); | |
953 | ||
9ffee4a8 SW |
954 | int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, |
955 | u32 ana_rgc3); | |
956 | int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); | |
7e538372 RD |
957 | int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, |
958 | const struct phylink_link_state *state); | |
959 | void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); | |
960 | ||
961 | int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); | |
962 | int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); | |
963 | int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); | |
9ffee4a8 | 964 | |
502e84e2 FF |
965 | int mtk_eth_offload_init(struct mtk_eth *eth); |
966 | int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, | |
967 | void *type_data); | |
968 | ||
969 | ||
656e7052 | 970 | #endif /* MTK_ETH_H */ |