[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.h

/*   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; version 2 of the License
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
 *   Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
 *   Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
 */

#ifndef MTK_ETH_H
#define MTK_ETH_H

#define MTK_QDMA_PAGE_SIZE	2048
#define	MTK_MAX_RX_LENGTH	1536
#define MTK_TX_DMA_BUF_LEN	0x3fff
#define MTK_DMA_SIZE		256
#define MTK_NAPI_WEIGHT		64
#define MTK_MAC_COUNT		2
#define MTK_RX_ETH_HLEN		(VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
#define MTK_RX_HLEN		(NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
#define MTK_DMA_DUMMY_DESC	0xffffffff
#define MTK_DEFAULT_MSG_ENABLE	(NETIF_MSG_DRV | \
				 NETIF_MSG_PROBE | \
				 NETIF_MSG_LINK | \
				 NETIF_MSG_TIMER | \
				 NETIF_MSG_IFDOWN | \
				 NETIF_MSG_IFUP | \
				 NETIF_MSG_RX_ERR | \
				 NETIF_MSG_TX_ERR)
#define MTK_HW_FEATURES		(NETIF_F_IP_CSUM | \
				 NETIF_F_RXCSUM | \
				 NETIF_F_HW_VLAN_CTAG_TX | \
				 NETIF_F_HW_VLAN_CTAG_RX | \
				 NETIF_F_SG | NETIF_F_TSO | \
				 NETIF_F_TSO6 | \
				 NETIF_F_IPV6_CSUM)
#define NEXT_RX_DESP_IDX(X, Y)	(((X) + 1) & ((Y) - 1))

#define MTK_MAX_RX_RING_NUM	4
#define MTK_HW_LRO_DMA_SIZE	8

#define	MTK_MAX_LRO_RX_LENGTH		(4096 * 3)
#define	MTK_MAX_LRO_IP_CNT		2
#define	MTK_HW_LRO_TIMER_UNIT		1	/* 20 us */
#define	MTK_HW_LRO_REFRESH_TIME		50000	/* 1 sec. */
#define	MTK_HW_LRO_AGG_TIME		10	/* 200us */
#define	MTK_HW_LRO_AGE_TIME		50	/* 1ms */
#define	MTK_HW_LRO_MAX_AGG_CNT		64
#define	MTK_HW_LRO_BW_THRE		3000
#define	MTK_HW_LRO_REPLACE_DELTA	1000
#define	MTK_HW_LRO_SDL_REMAIN_ROOM	1522

/* Frame Engine Global Reset Register */
#define MTK_RST_GL		0x04
#define RST_GL_PSE		BIT(0)

/* Frame Engine Interrupt Status Register */
#define MTK_INT_STATUS2		0x08
#define MTK_GDM1_AF		BIT(28)
#define MTK_GDM2_AF		BIT(29)

/* PDMA HW LRO Alter Flow Timer Register */
#define MTK_PDMA_LRO_ALT_REFRESH_TIMER	0x1c

/* Frame Engine Interrupt Grouping Register */
#define MTK_FE_INT_GRP		0x20

/* CDMP Exgress Control Register */
#define MTK_CDMP_EG_CTRL	0x404

/* GDM Exgress Control Register */
#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
#define MTK_GDMA_ICS_EN		BIT(22)
#define MTK_GDMA_TCS_EN		BIT(21)
#define MTK_GDMA_UCS_EN		BIT(20)

/* Unicast Filter MAC Address Register - Low */
#define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))

/* Unicast Filter MAC Address Register - High */
#define MTK_GDMA_MAC_ADRH(x)	(0x50C + (x * 0x1000))

/* PDMA RX Base Pointer Register */
#define MTK_PRX_BASE_PTR0	0x900
#define MTK_PRX_BASE_PTR_CFG(x)	(MTK_PRX_BASE_PTR0 + (x * 0x10))

/* PDMA RX Maximum Count Register */
#define MTK_PRX_MAX_CNT0	0x904
#define MTK_PRX_MAX_CNT_CFG(x)	(MTK_PRX_MAX_CNT0 + (x * 0x10))

/* PDMA RX CPU Pointer Register */
#define MTK_PRX_CRX_IDX0	0x908
#define MTK_PRX_CRX_IDX_CFG(x)	(MTK_PRX_CRX_IDX0 + (x * 0x10))

/* PDMA HW LRO Control Registers */
#define MTK_PDMA_LRO_CTRL_DW0	0x980
#define MTK_LRO_EN			BIT(0)
#define MTK_L3_CKS_UPD_EN		BIT(7)
#define MTK_LRO_ALT_PKT_CNT_MODE	BIT(21)
#define MTK_LRO_RING_RELINQUISH_REQ	(0x7 << 26)
#define MTK_LRO_RING_RELINQUISH_DONE	(0x7 << 29)

#define MTK_PDMA_LRO_CTRL_DW1	0x984
#define MTK_PDMA_LRO_CTRL_DW2	0x988
#define MTK_PDMA_LRO_CTRL_DW3	0x98c
#define MTK_ADMA_MODE		BIT(15)
#define MTK_LRO_MIN_RXD_SDL	(MTK_HW_LRO_SDL_REMAIN_ROOM << 16)

/* PDMA Global Configuration Register */
#define MTK_PDMA_GLO_CFG	0xa04
#define MTK_MULTI_EN		BIT(10)

/* PDMA Reset Index Register */
#define MTK_PDMA_RST_IDX	0xa08
#define MTK_PST_DRX_IDX0	BIT(16)
#define MTK_PST_DRX_IDX_CFG(x)	(MTK_PST_DRX_IDX0 << (x))

/* PDMA Delay Interrupt Register */
#define MTK_PDMA_DELAY_INT	0xa0c

/* PDMA Interrupt Status Register */
#define MTK_PDMA_INT_STATUS	0xa20

/* PDMA Interrupt Mask Register */
#define MTK_PDMA_INT_MASK	0xa28

/* PDMA HW LRO Alter Flow Delta Register */
#define MTK_PDMA_LRO_ALT_SCORE_DELTA	0xa4c

/* PDMA Interrupt grouping registers */
#define MTK_PDMA_INT_GRP1	0xa50
#define MTK_PDMA_INT_GRP2	0xa54

/* PDMA HW LRO IP Setting Registers */
#define MTK_LRO_RX_RING0_DIP_DW0	0xb04
#define MTK_LRO_DIP_DW0_CFG(x)		(MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
#define MTK_RING_MYIP_VLD		BIT(9)

/* PDMA HW LRO Ring Control Registers */
#define MTK_LRO_RX_RING0_CTRL_DW1	0xb28
#define MTK_LRO_RX_RING0_CTRL_DW2	0xb2c
#define MTK_LRO_RX_RING0_CTRL_DW3	0xb30
#define MTK_LRO_CTRL_DW1_CFG(x)		(MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
#define MTK_LRO_CTRL_DW2_CFG(x)		(MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
#define MTK_LRO_CTRL_DW3_CFG(x)		(MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
#define MTK_RING_AGE_TIME_L		((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
#define MTK_RING_AGE_TIME_H		((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
#define MTK_RING_AUTO_LERAN_MODE	(3 << 6)
#define MTK_RING_VLD			BIT(8)
#define MTK_RING_MAX_AGG_TIME		((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
#define MTK_RING_MAX_AGG_CNT_L		((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
#define MTK_RING_MAX_AGG_CNT_H		((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)

/* QDMA TX Queue Configuration Registers */
#define MTK_QTX_CFG(x)		(0x1800 + (x * 0x10))
#define QDMA_RES_THRES		4

/* QDMA TX Queue Scheduler Registers */
#define MTK_QTX_SCH(x)		(0x1804 + (x * 0x10))

/* QDMA RX Base Pointer Register */
#define MTK_QRX_BASE_PTR0	0x1900

/* QDMA RX Maximum Count Register */
#define MTK_QRX_MAX_CNT0	0x1904

/* QDMA RX CPU Pointer Register */
#define MTK_QRX_CRX_IDX0	0x1908

/* QDMA RX DMA Pointer Register */
#define MTK_QRX_DRX_IDX0	0x190C

/* QDMA Global Configuration Register */
#define MTK_QDMA_GLO_CFG	0x1A04
#define MTK_RX_2B_OFFSET	BIT(31)
#define MTK_RX_BT_32DWORDS	(3 << 11)
#define MTK_NDP_CO_PRO		BIT(10)
#define MTK_TX_WB_DDONE		BIT(6)
#define MTK_DMA_SIZE_16DWORDS	(2 << 4)
#define MTK_RX_DMA_BUSY		BIT(3)
#define MTK_TX_DMA_BUSY		BIT(1)
#define MTK_RX_DMA_EN		BIT(2)
#define MTK_TX_DMA_EN		BIT(0)
#define MTK_DMA_BUSY_TIMEOUT	HZ

/* QDMA Reset Index Register */
#define MTK_QDMA_RST_IDX	0x1A08

/* QDMA Delay Interrupt Register */
#define MTK_QDMA_DELAY_INT	0x1A0C

/* QDMA Flow Control Register */
#define MTK_QDMA_FC_THRES	0x1A10
#define FC_THRES_DROP_MODE	BIT(20)
#define FC_THRES_DROP_EN	(7 << 16)
#define FC_THRES_MIN		0x4444

/* QDMA Interrupt Status Register */
#define MTK_QMTK_INT_STATUS	0x1A18
#define MTK_RX_DONE_INT3	BIT(19)
#define MTK_RX_DONE_INT2	BIT(18)
#define MTK_RX_DONE_INT1	BIT(17)
#define MTK_RX_DONE_INT0	BIT(16)
#define MTK_TX_DONE_INT3	BIT(3)
#define MTK_TX_DONE_INT2	BIT(2)
#define MTK_TX_DONE_INT1	BIT(1)
#define MTK_TX_DONE_INT0	BIT(0)
#define MTK_RX_DONE_INT		(MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \
				 MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3)
#define MTK_TX_DONE_INT		(MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
				 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)

/* QDMA Interrupt grouping registers */
#define MTK_QDMA_INT_GRP1	0x1a20
#define MTK_QDMA_INT_GRP2	0x1a24
#define MTK_RLS_DONE_INT	BIT(0)

/* QDMA Interrupt Status Register */
#define MTK_QDMA_INT_MASK	0x1A1C

/* QDMA Interrupt Mask Register */
#define MTK_QDMA_HRED2		0x1A44

/* QDMA TX Forward CPU Pointer Register */
#define MTK_QTX_CTX_PTR		0x1B00

/* QDMA TX Forward DMA Pointer Register */
#define MTK_QTX_DTX_PTR		0x1B04

/* QDMA TX Release CPU Pointer Register */
#define MTK_QTX_CRX_PTR		0x1B10

/* QDMA TX Release DMA Pointer Register */
#define MTK_QTX_DRX_PTR		0x1B14

/* QDMA FQ Head Pointer Register */
#define MTK_QDMA_FQ_HEAD	0x1B20

/* QDMA FQ Head Pointer Register */
#define MTK_QDMA_FQ_TAIL	0x1B24

/* QDMA FQ Free Page Counter Register */
#define MTK_QDMA_FQ_CNT		0x1B28

/* QDMA FQ Free Page Buffer Length Register */
#define MTK_QDMA_FQ_BLEN	0x1B2C

/* GMA1 Received Good Byte Count Register */
#define MTK_GDM1_TX_GBCNT	0x2400
#define MTK_STAT_OFFSET		0x40

/* QDMA descriptor txd4 */
#define TX_DMA_CHKSUM		(0x7 << 29)
#define TX_DMA_TSO		BIT(28)
#define TX_DMA_FPORT_SHIFT	25
#define TX_DMA_FPORT_MASK	0x7
#define TX_DMA_INS_VLAN		BIT(16)

/* QDMA descriptor txd3 */
#define TX_DMA_OWNER_CPU	BIT(31)
#define TX_DMA_LS0		BIT(30)
#define TX_DMA_PLEN0(_x)	(((_x) & MTK_TX_DMA_BUF_LEN) << 16)
#define TX_DMA_SWC		BIT(14)
#define TX_DMA_SDL(_x)		(((_x) & 0x3fff) << 16)

/* QDMA descriptor rxd2 */
#define RX_DMA_DONE		BIT(31)
#define RX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x)	(((_x) >> 16) & 0x3fff)

/* QDMA descriptor rxd3 */
#define RX_DMA_VID(_x)		((_x) & 0xfff)

/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID		BIT(24)
#define RX_DMA_FPORT_SHIFT	19
#define RX_DMA_FPORT_MASK	0x7

/* PHY Indirect Access Control registers */
#define MTK_PHY_IAC		0x10004
#define PHY_IAC_ACCESS		BIT(31)
#define PHY_IAC_READ		BIT(19)
#define PHY_IAC_WRITE		BIT(18)
#define PHY_IAC_START		BIT(16)
#define PHY_IAC_ADDR_SHIFT	20
#define PHY_IAC_REG_SHIFT	25
#define PHY_IAC_TIMEOUT		HZ

/* Mac control registers */
#define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
#define MAC_MCR_MAX_RX_1536	BIT(24)
#define MAC_MCR_IPG_CFG		(BIT(18) | BIT(16))
#define MAC_MCR_FORCE_MODE	BIT(15)
#define MAC_MCR_TX_EN		BIT(14)
#define MAC_MCR_RX_EN		BIT(13)
#define MAC_MCR_BACKOFF_EN	BIT(9)
#define MAC_MCR_BACKPR_EN	BIT(8)
#define MAC_MCR_FORCE_RX_FC	BIT(5)
#define MAC_MCR_FORCE_TX_FC	BIT(4)
#define MAC_MCR_SPEED_1000	BIT(3)
#define MAC_MCR_SPEED_100	BIT(2)
#define MAC_MCR_FORCE_DPX	BIT(1)
#define MAC_MCR_FORCE_LINK	BIT(0)
#define MAC_MCR_FIXED_LINK	(MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
				 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
				 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
				 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
				 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
				 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)

/* TRGMII RXC control register */
#define TRGMII_RCK_CTRL		0x10300
#define DQSI0(x)		((x << 0) & GENMASK(6, 0))
#define DQSI1(x)		((x << 8) & GENMASK(14, 8))
#define RXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
#define RXC_DQSISEL		BIT(30)
#define RCK_CTRL_RGMII_1000	(RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
#define RCK_CTRL_RGMII_10_100	RXCTL_DMWTLAT(2)

/* TRGMII RXC control register */
#define TRGMII_TCK_CTRL		0x10340
#define TXCTL_DMWTLAT(x)	((x << 16) & GENMASK(18, 16))
#define TXC_INV			BIT(30)
#define TCK_CTRL_RGMII_1000	TXCTL_DMWTLAT(2)
#define TCK_CTRL_RGMII_10_100	(TXC_INV | TXCTL_DMWTLAT(2))

/* TRGMII Interface mode register */
#define INTF_MODE		0x10390
#define TRGMII_INTF_DIS		BIT(0)
#define TRGMII_MODE		BIT(1)
#define TRGMII_CENTRAL_ALIGNED	BIT(2)
#define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
#define INTF_MODE_RGMII_10_100  0

/* GPIO port control registers for GMAC 2*/
#define GPIO_OD33_CTRL8		0x4c0
#define GPIO_BIAS_CTRL		0xed0
#define GPIO_DRV_SEL10		0xf00

/* ethernet subsystem chip id register */
#define ETHSYS_CHIPID0_3	0x0
#define ETHSYS_CHIPID4_7	0x4
#define MT7623_ETH		7623

/* ethernet subsystem config register */
#define ETHSYS_SYSCFG0		0x14
#define SYSCFG0_GE_MASK		0x3
#define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))

/* ethernet subsystem clock register */
#define ETHSYS_CLKCFG0		0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)

/* ethernet reset control register */
#define ETHSYS_RSTCTRL		0x34
#define RSTCTRL_FE		BIT(6)
#define RSTCTRL_PPE		BIT(31)

struct mtk_rx_dma {
	unsigned int rxd1;
	unsigned int rxd2;
	unsigned int rxd3;
	unsigned int rxd4;
} __packed __aligned(4);

struct mtk_tx_dma {
	unsigned int txd1;
	unsigned int txd2;
	unsigned int txd3;
	unsigned int txd4;
} __packed __aligned(4);

struct mtk_eth;
struct mtk_mac;

/* struct mtk_hw_stats - the structure that holds the traffic statistics.
 * @stats_lock:		make sure that stats operations are atomic
 * @reg_offset:		the status register offset of the SoC
 * @syncp:		the refcount
 *
 * All of the supported SoCs have hardware counters for traffic statistics.
 * Whenever the status IRQ triggers we can read the latest stats from these
 * counters and store them in this struct.
 */
struct mtk_hw_stats {
	u64 tx_bytes;
	u64 tx_packets;
	u64 tx_skip;
	u64 tx_collisions;
	u64 rx_bytes;
	u64 rx_packets;
	u64 rx_overflow;
	u64 rx_fcs_errors;
	u64 rx_short_errors;
	u64 rx_long_errors;
	u64 rx_checksum_errors;
	u64 rx_flow_control_packets;

	spinlock_t		stats_lock;
	u32			reg_offset;
	struct u64_stats_sync	syncp;
};

enum mtk_tx_flags {
	/* PDMA descriptor can point at 1-2 segments. This enum allows us to
	 * track how memory was allocated so that it can be freed properly.
	 */
	MTK_TX_FLAGS_SINGLE0	= 0x01,
	MTK_TX_FLAGS_PAGE0	= 0x02,

	/* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
	 * SKB out instead of looking up through hardware TX descriptor.
	 */
	MTK_TX_FLAGS_FPORT0	= 0x04,
	MTK_TX_FLAGS_FPORT1	= 0x08,
};

/* This enum allows us to identify how the clock is defined on the array of the
 * clock in the order
 */
enum mtk_clks_map {
	MTK_CLK_ETHIF,
	MTK_CLK_ESW,
	MTK_CLK_GP1,
	MTK_CLK_GP2,
	MTK_CLK_TRGPLL,
	MTK_CLK_MAX
};

enum mtk_dev_state {
	MTK_HW_INIT,
	MTK_RESETTING
};

/* struct mtk_tx_buf -	This struct holds the pointers to the memory pointed at
 *			by the TX descriptor	s
 * @skb:		The SKB pointer of the packet being sent
 * @dma_addr0:		The base addr of the first segment
 * @dma_len0:		The length of the first segment
 * @dma_addr1:		The base addr of the second segment
 * @dma_len1:		The length of the second segment
 */
struct mtk_tx_buf {
	struct sk_buff *skb;
	u32 flags;
	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
	DEFINE_DMA_UNMAP_LEN(dma_len0);
	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
	DEFINE_DMA_UNMAP_LEN(dma_len1);
};

/* struct mtk_tx_ring -	This struct holds info describing a TX ring
 * @dma:		The descriptor ring
 * @buf:		The memory pointed at by the ring
 * @phys:		The physical addr of tx_buf
 * @next_free:		Pointer to the next free descriptor
 * @last_free:		Pointer to the last free descriptor
 * @thresh:		The threshold of minimum amount of free descriptors
 * @free_count:		QDMA uses a linked list. Track how many free descriptors
 *			are present
 */
struct mtk_tx_ring {
	struct mtk_tx_dma *dma;
	struct mtk_tx_buf *buf;
	dma_addr_t phys;
	struct mtk_tx_dma *next_free;
	struct mtk_tx_dma *last_free;
	u16 thresh;
	atomic_t free_count;
};

/* PDMA rx ring mode */
enum mtk_rx_flags {
	MTK_RX_FLAGS_NORMAL = 0,
	MTK_RX_FLAGS_HWLRO,
};

/* struct mtk_rx_ring -	This struct holds info describing a RX ring
 * @dma:		The descriptor ring
 * @data:		The memory pointed at by the ring
 * @phys:		The physical addr of rx_buf
 * @frag_size:		How big can each fragment be
 * @buf_size:		The size of each packet buffer
 * @calc_idx:		The current head of ring
 */
struct mtk_rx_ring {
	struct mtk_rx_dma *dma;
	u8 **data;
	dma_addr_t phys;
	u16 frag_size;
	u16 buf_size;
	u16 dma_size;
	bool calc_idx_update;
	u16 calc_idx;
	u32 crx_idx_reg;
};

/* currently no SoC has more than 2 macs */
#define MTK_MAX_DEVS			2

/* struct mtk_eth -	This is the main datasructure for holding the state
 *			of the driver
 * @dev:		The device pointer
 * @base:		The mapped register i/o base
 * @page_lock:		Make sure that register operations are atomic
 * @dummy_dev:		we run 2 netdevs on 1 physical DMA ring and need a
 *			dummy for NAPI to work
 * @netdev:		The netdev instances
 * @mac:		Each netdev is linked to a physical MAC
 * @irq:		The IRQ that we are using
 * @msg_enable:		Ethtool msg level
 * @ethsys:		The register map pointing at the range used to setup
 *			MII modes
 * @pctl:		The register map pointing at the range used to setup
 *			GMAC port drive/slew values
 * @dma_refcnt:		track how many netdevs are using the DMA engine
 * @tx_ring:		Pointer to the memore holding info about the TX ring
 * @rx_ring:		Pointer to the memore holding info about the RX ring
 * @tx_napi:		The TX NAPI struct
 * @rx_napi:		The RX NAPI struct
 * @scratch_ring:	Newer SoCs need memory for a second HW managed TX ring
 * @phy_scratch_ring:	physical address of scratch_ring
 * @scratch_head:	The scratch memory that scratch_ring points to.
 * @clks:		clock array for all clocks required
 * @mii_bus:		If there is a bus we need to create an instance for it
 * @pending_work:	The workqueue used to reset the dma ring
 * @state               Initialization and runtime state of the device.
 */

struct mtk_eth {
	struct device			*dev;
	void __iomem			*base;
	spinlock_t			page_lock;
	spinlock_t			irq_lock;
	struct net_device		dummy_dev;
	struct net_device		*netdev[MTK_MAX_DEVS];
	struct mtk_mac			*mac[MTK_MAX_DEVS];
	int				irq[3];
	u32				msg_enable;
	unsigned long			sysclk;
	struct regmap			*ethsys;
	struct regmap			*pctl;
	u32				chip_id;
	bool				hwlro;
	atomic_t			dma_refcnt;
	struct mtk_tx_ring		tx_ring;
	struct mtk_rx_ring		rx_ring[MTK_MAX_RX_RING_NUM];
	struct napi_struct		tx_napi;
	struct napi_struct		rx_napi;
	struct mtk_tx_dma		*scratch_ring;
	dma_addr_t			phy_scratch_ring;
	void				*scratch_head;
	struct clk			*clks[MTK_CLK_MAX];

	struct mii_bus			*mii_bus;
	struct work_struct		pending_work;
	unsigned long			state;
};

/* struct mtk_mac -	the structure that holds the info about the MACs of the
 *			SoC
 * @id:			The number of the MAC
 * @ge_mode:            Interface mode kept for setup restoring
 * @of_node:		Our devicetree node
 * @hw:			Backpointer to our main datastruture
 * @hw_stats:		Packet statistics counter
 * @trgmii		Indicate if the MAC uses TRGMII connected to internal
			switch
 */
struct mtk_mac {
	int				id;
	int				ge_mode;
	struct device_node		*of_node;
	struct mtk_eth			*hw;
	struct mtk_hw_stats		*hw_stats;
	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
	int				hwlro_ip_cnt;
	bool				trgmii;
};

/* the struct describing the SoC. these are declared in the soc_xyz.c files */
extern const struct of_device_id of_mtk_match[];

/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);

void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);

#endif /* MTK_ETH_H */
Commit	Line	Data
656e7052 JC	1	/* This program is free software; you can redistribute it and/or modify
	2	* it under the terms of the GNU General Public License as published by
	3	* the Free Software Foundation; version 2 of the License
	4	*
	5	* This program is distributed in the hope that it will be useful,
	6	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	7	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	8	* GNU General Public License for more details.
	9	*
	10	* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
	11	* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
	12	* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
	13	*/
	14
	15	#ifndef MTK_ETH_H
	16	#define MTK_ETH_H
	17
	18	#define MTK_QDMA_PAGE_SIZE 2048
	19	#define MTK_MAX_RX_LENGTH 1536
	20	#define MTK_TX_DMA_BUF_LEN 0x3fff
	21	#define MTK_DMA_SIZE 256
	22	#define MTK_NAPI_WEIGHT 64
	23	#define MTK_MAC_COUNT 2
	24	#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
	25	#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
	26	#define MTK_DMA_DUMMY_DESC 0xffffffff
	27	#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV \| \
	28	NETIF_MSG_PROBE \| \
	29	NETIF_MSG_LINK \| \
	30	NETIF_MSG_TIMER \| \
	31	NETIF_MSG_IFDOWN \| \
	32	NETIF_MSG_IFUP \| \
	33	NETIF_MSG_RX_ERR \| \
	34	NETIF_MSG_TX_ERR)
	35	#define MTK_HW_FEATURES (NETIF_F_IP_CSUM \| \
	36	NETIF_F_RXCSUM \| \
	37	NETIF_F_HW_VLAN_CTAG_TX \| \
	38	NETIF_F_HW_VLAN_CTAG_RX \| \
	39	NETIF_F_SG \| NETIF_F_TSO \| \
	40	NETIF_F_TSO6 \| \
	41	NETIF_F_IPV6_CSUM)
ee406810 NC	42	#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
	43
	44	#define MTK_MAX_RX_RING_NUM 4
	45	#define MTK_HW_LRO_DMA_SIZE 8
	46
	47	#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
	48	#define MTK_MAX_LRO_IP_CNT 2
	49	#define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
	50	#define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
	51	#define MTK_HW_LRO_AGG_TIME 10 /* 200us */
	52	#define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
	53	#define MTK_HW_LRO_MAX_AGG_CNT 64
	54	#define MTK_HW_LRO_BW_THRE 3000
	55	#define MTK_HW_LRO_REPLACE_DELTA 1000
	56	#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
656e7052 JC	57
	58	/* Frame Engine Global Reset Register */
	59	#define MTK_RST_GL 0x04
	60	#define RST_GL_PSE BIT(0)
	61
	62	/* Frame Engine Interrupt Status Register */
	63	#define MTK_INT_STATUS2 0x08
	64	#define MTK_GDM1_AF BIT(28)
	65	#define MTK_GDM2_AF BIT(29)
	66
ee406810 NC	67	/* PDMA HW LRO Alter Flow Timer Register */
	68	#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
	69
656e7052 JC	70	/* Frame Engine Interrupt Grouping Register */
	71	#define MTK_FE_INT_GRP 0x20
	72
	73	/* CDMP Exgress Control Register */
	74	#define MTK_CDMP_EG_CTRL 0x404
	75
	76	/* GDM Exgress Control Register */
	77	#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
	78	#define MTK_GDMA_ICS_EN BIT(22)
	79	#define MTK_GDMA_TCS_EN BIT(21)
	80	#define MTK_GDMA_UCS_EN BIT(20)
	81
	82	/* Unicast Filter MAC Address Register - Low */
	83	#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
	84
	85	/* Unicast Filter MAC Address Register - High */
	86	#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
	87
bacfd110 NC	88	/* PDMA RX Base Pointer Register */
bacfd110 NC	89	#define MTK_PRX_BASE_PTR0 0x900
ee406810	90	#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
bacfd110 NC	91
	92	/* PDMA RX Maximum Count Register */
	93	#define MTK_PRX_MAX_CNT0 0x904
ee406810	94	#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
bacfd110 NC	95
	96	/* PDMA RX CPU Pointer Register */
	97	#define MTK_PRX_CRX_IDX0 0x908
ee406810 NC	98	#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
	99
	100	/* PDMA HW LRO Control Registers */
	101	#define MTK_PDMA_LRO_CTRL_DW0 0x980
	102	#define MTK_LRO_EN BIT(0)
	103	#define MTK_L3_CKS_UPD_EN BIT(7)
	104	#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
ca3ba106 NC	105	#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
ca3ba106 NC	106	#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
ee406810 NC	107
	108	#define MTK_PDMA_LRO_CTRL_DW1 0x984
	109	#define MTK_PDMA_LRO_CTRL_DW2 0x988
	110	#define MTK_PDMA_LRO_CTRL_DW3 0x98c
	111	#define MTK_ADMA_MODE BIT(15)
	112	#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
bacfd110 NC	113
	114	/* PDMA Global Configuration Register */
	115	#define MTK_PDMA_GLO_CFG 0xa04
	116	#define MTK_MULTI_EN BIT(10)
	117
	118	/* PDMA Reset Index Register */
	119	#define MTK_PDMA_RST_IDX 0xa08
	120	#define MTK_PST_DRX_IDX0 BIT(16)
ee406810	121	#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
bacfd110 NC	122
	123	/* PDMA Delay Interrupt Register */
	124	#define MTK_PDMA_DELAY_INT 0xa0c
	125
	126	/* PDMA Interrupt Status Register */
	127	#define MTK_PDMA_INT_STATUS 0xa20
	128
	129	/* PDMA Interrupt Mask Register */
	130	#define MTK_PDMA_INT_MASK 0xa28
	131
ee406810 NC	132	/* PDMA HW LRO Alter Flow Delta Register */
	133	#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
	134
80673029 JC	135	/* PDMA Interrupt grouping registers */
	136	#define MTK_PDMA_INT_GRP1 0xa50
	137	#define MTK_PDMA_INT_GRP2 0xa54
	138
ee406810 NC	139	/* PDMA HW LRO IP Setting Registers */
	140	#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
	141	#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
	142	#define MTK_RING_MYIP_VLD BIT(9)
	143
	144	/* PDMA HW LRO Ring Control Registers */
	145	#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
	146	#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
	147	#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
	148	#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
	149	#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
	150	#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
	151	#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
	152	#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
	153	#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
	154	#define MTK_RING_VLD BIT(8)
	155	#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
	156	#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
	157	#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
	158
656e7052 JC	159	/* QDMA TX Queue Configuration Registers */
	160	#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
	161	#define QDMA_RES_THRES 4
	162
	163	/* QDMA TX Queue Scheduler Registers */
	164	#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
	165
	166	/* QDMA RX Base Pointer Register */
	167	#define MTK_QRX_BASE_PTR0 0x1900
	168
	169	/* QDMA RX Maximum Count Register */
	170	#define MTK_QRX_MAX_CNT0 0x1904
	171
	172	/* QDMA RX CPU Pointer Register */
	173	#define MTK_QRX_CRX_IDX0 0x1908
	174
	175	/* QDMA RX DMA Pointer Register */
	176	#define MTK_QRX_DRX_IDX0 0x190C
	177
	178	/* QDMA Global Configuration Register */
	179	#define MTK_QDMA_GLO_CFG 0x1A04
	180	#define MTK_RX_2B_OFFSET BIT(31)
	181	#define MTK_RX_BT_32DWORDS (3 << 11)
6675086d	182	#define MTK_NDP_CO_PRO BIT(10)
656e7052 JC	183	#define MTK_TX_WB_DDONE BIT(6)
	184	#define MTK_DMA_SIZE_16DWORDS (2 << 4)
	185	#define MTK_RX_DMA_BUSY BIT(3)
	186	#define MTK_TX_DMA_BUSY BIT(1)
	187	#define MTK_RX_DMA_EN BIT(2)
	188	#define MTK_TX_DMA_EN BIT(0)
	189	#define MTK_DMA_BUSY_TIMEOUT HZ
	190
	191	/* QDMA Reset Index Register */
	192	#define MTK_QDMA_RST_IDX 0x1A08
656e7052 JC	193
	194	/* QDMA Delay Interrupt Register */
	195	#define MTK_QDMA_DELAY_INT 0x1A0C
	196
	197	/* QDMA Flow Control Register */
	198	#define MTK_QDMA_FC_THRES 0x1A10
	199	#define FC_THRES_DROP_MODE BIT(20)
	200	#define FC_THRES_DROP_EN (7 << 16)
	201	#define FC_THRES_MIN 0x4444
	202
	203	/* QDMA Interrupt Status Register */
	204	#define MTK_QMTK_INT_STATUS 0x1A18
bacfd110 NC	205	#define MTK_RX_DONE_INT3 BIT(19)
bacfd110 NC	206	#define MTK_RX_DONE_INT2 BIT(18)
656e7052 JC	207	#define MTK_RX_DONE_INT1 BIT(17)
	208	#define MTK_RX_DONE_INT0 BIT(16)
	209	#define MTK_TX_DONE_INT3 BIT(3)
	210	#define MTK_TX_DONE_INT2 BIT(2)
	211	#define MTK_TX_DONE_INT1 BIT(1)
	212	#define MTK_TX_DONE_INT0 BIT(0)
bacfd110 NC	213	#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 \| MTK_RX_DONE_INT1 \| \
bacfd110 NC	214	MTK_RX_DONE_INT2 \| MTK_RX_DONE_INT3)
656e7052 JC	215	#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 \| MTK_TX_DONE_INT1 \| \
	216	MTK_TX_DONE_INT2 \| MTK_TX_DONE_INT3)
	217
80673029 JC	218	/* QDMA Interrupt grouping registers */
	219	#define MTK_QDMA_INT_GRP1 0x1a20
	220	#define MTK_QDMA_INT_GRP2 0x1a24
	221	#define MTK_RLS_DONE_INT BIT(0)
	222
656e7052 JC	223	/* QDMA Interrupt Status Register */
	224	#define MTK_QDMA_INT_MASK 0x1A1C
	225
	226	/* QDMA Interrupt Mask Register */
	227	#define MTK_QDMA_HRED2 0x1A44
	228
	229	/* QDMA TX Forward CPU Pointer Register */
	230	#define MTK_QTX_CTX_PTR 0x1B00
	231
	232	/* QDMA TX Forward DMA Pointer Register */
	233	#define MTK_QTX_DTX_PTR 0x1B04
	234
	235	/* QDMA TX Release CPU Pointer Register */
	236	#define MTK_QTX_CRX_PTR 0x1B10
	237
	238	/* QDMA TX Release DMA Pointer Register */
	239	#define MTK_QTX_DRX_PTR 0x1B14
	240
	241	/* QDMA FQ Head Pointer Register */
	242	#define MTK_QDMA_FQ_HEAD 0x1B20
	243
	244	/* QDMA FQ Head Pointer Register */
	245	#define MTK_QDMA_FQ_TAIL 0x1B24
	246
	247	/* QDMA FQ Free Page Counter Register */
	248	#define MTK_QDMA_FQ_CNT 0x1B28
	249
	250	/* QDMA FQ Free Page Buffer Length Register */
	251	#define MTK_QDMA_FQ_BLEN 0x1B2C
	252
	253	/* GMA1 Received Good Byte Count Register */
	254	#define MTK_GDM1_TX_GBCNT 0x2400
	255	#define MTK_STAT_OFFSET 0x40
	256
	257	/* QDMA descriptor txd4 */
	258	#define TX_DMA_CHKSUM (0x7 << 29)
	259	#define TX_DMA_TSO BIT(28)
	260	#define TX_DMA_FPORT_SHIFT 25
	261	#define TX_DMA_FPORT_MASK 0x7
	262	#define TX_DMA_INS_VLAN BIT(16)
	263
	264	/* QDMA descriptor txd3 */
	265	#define TX_DMA_OWNER_CPU BIT(31)
	266	#define TX_DMA_LS0 BIT(30)
	267	#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
	268	#define TX_DMA_SWC BIT(14)
	269	#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
	270
	271	/* QDMA descriptor rxd2 */
	272	#define RX_DMA_DONE BIT(31)
	273	#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
	274	#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
	275
	276	/* QDMA descriptor rxd3 */
	277	#define RX_DMA_VID(_x) ((_x) & 0xfff)
	278
	279	/* QDMA descriptor rxd4 */
	280	#define RX_DMA_L4_VALID BIT(24)
	281	#define RX_DMA_FPORT_SHIFT 19
	282	#define RX_DMA_FPORT_MASK 0x7
	283
	284	/* PHY Indirect Access Control registers */
	285	#define MTK_PHY_IAC 0x10004
	286	#define PHY_IAC_ACCESS BIT(31)
287	#define PHY_IAC_READ BIT(19)
288	#define PHY_IAC_WRITE BIT(18)
289	#define PHY_IAC_START BIT(16)
290	#define PHY_IAC_ADDR_SHIFT 20
291	#define PHY_IAC_REG_SHIFT 25
292	#define PHY_IAC_TIMEOUT HZ
293
294	/* Mac control registers */
295	#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
296	#define MAC_MCR_MAX_RX_1536 BIT(24)
297	#define MAC_MCR_IPG_CFG (BIT(18) \| BIT(16))
298	#define MAC_MCR_FORCE_MODE BIT(15)
299	#define MAC_MCR_TX_EN BIT(14)
300	#define MAC_MCR_RX_EN BIT(13)
301	#define MAC_MCR_BACKOFF_EN BIT(9)
302	#define MAC_MCR_BACKPR_EN BIT(8)
303	#define MAC_MCR_FORCE_RX_FC BIT(5)
304	#define MAC_MCR_FORCE_TX_FC BIT(4)
305	#define MAC_MCR_SPEED_1000 BIT(3)
306	#define MAC_MCR_SPEED_100 BIT(2)
307	#define MAC_MCR_FORCE_DPX BIT(1)
308	#define MAC_MCR_FORCE_LINK BIT(0)
309	#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 \| MAC_MCR_IPG_CFG \| \
310	MAC_MCR_FORCE_MODE \| MAC_MCR_TX_EN \| \
311	MAC_MCR_RX_EN \| MAC_MCR_BACKOFF_EN \| \
312	MAC_MCR_BACKPR_EN \| MAC_MCR_FORCE_RX_FC \| \
313	MAC_MCR_FORCE_TX_FC \| MAC_MCR_SPEED_1000 \| \
314	MAC_MCR_FORCE_DPX \| MAC_MCR_FORCE_LINK)
315
f430dea7 SW	316	/* TRGMII RXC control register */
	317	#define TRGMII_RCK_CTRL 0x10300
	318	#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
	319	#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
	320	#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
	321	#define RXC_DQSISEL BIT(30)
	322	#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL \| RXCTL_DMWTLAT(2) \| DQSI1(16))
	323	#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
	324
	325	/* TRGMII RXC control register */
	326	#define TRGMII_TCK_CTRL 0x10340
	327	#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
	328	#define TXC_INV BIT(30)
	329	#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
	330	#define TCK_CTRL_RGMII_10_100 (TXC_INV \| TXCTL_DMWTLAT(2))
	331
	332	/* TRGMII Interface mode register */
	333	#define INTF_MODE 0x10390
	334	#define TRGMII_INTF_DIS BIT(0)
	335	#define TRGMII_MODE BIT(1)
	336	#define TRGMII_CENTRAL_ALIGNED BIT(2)
	337	#define INTF_MODE_RGMII_1000 (TRGMII_MODE \| TRGMII_CENTRAL_ALIGNED)
	338	#define INTF_MODE_RGMII_10_100 0
	339
656e7052 JC	340	/* GPIO port control registers for GMAC 2*/
	341	#define GPIO_OD33_CTRL8 0x4c0
	342	#define GPIO_BIAS_CTRL 0xed0
	343	#define GPIO_DRV_SEL10 0xf00
	344
b95b6d99 NC	345	/* ethernet subsystem chip id register */
	346	#define ETHSYS_CHIPID0_3 0x0
	347	#define ETHSYS_CHIPID4_7 0x4
983e1a6c	348	#define MT7623_ETH 7623
b95b6d99	349
656e7052 JC	350	/* ethernet subsystem config register */
	351	#define ETHSYS_SYSCFG0 0x14
	352	#define SYSCFG0_GE_MASK 0x3
	353	#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
	354
f430dea7 SW	355	/* ethernet subsystem clock register */
	356	#define ETHSYS_CLKCFG0 0x2c
	357	#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
	358
	359	/* ethernet reset control register */
2a8307aa SW	360	#define ETHSYS_RSTCTRL 0x34
	361	#define RSTCTRL_FE BIT(6)
	362	#define RSTCTRL_PPE BIT(31)
	363
656e7052 JC	364	struct mtk_rx_dma {
	365	unsigned int rxd1;
	366	unsigned int rxd2;
	367	unsigned int rxd3;
	368	unsigned int rxd4;
	369	} __packed __aligned(4);
	370
	371	struct mtk_tx_dma {
	372	unsigned int txd1;
	373	unsigned int txd2;
	374	unsigned int txd3;
	375	unsigned int txd4;
	376	} __packed __aligned(4);
	377
	378	struct mtk_eth;
	379	struct mtk_mac;
	380
	381	/* struct mtk_hw_stats - the structure that holds the traffic statistics.
	382	* @stats_lock: make sure that stats operations are atomic
	383	* @reg_offset: the status register offset of the SoC
	384	* @syncp: the refcount
	385	*
	386	* All of the supported SoCs have hardware counters for traffic statistics.
	387	* Whenever the status IRQ triggers we can read the latest stats from these
	388	* counters and store them in this struct.
	389	*/
	390	struct mtk_hw_stats {
	391	u64 tx_bytes;
	392	u64 tx_packets;
	393	u64 tx_skip;
	394	u64 tx_collisions;
	395	u64 rx_bytes;
	396	u64 rx_packets;
	397	u64 rx_overflow;
	398	u64 rx_fcs_errors;
	399	u64 rx_short_errors;
	400	u64 rx_long_errors;
	401	u64 rx_checksum_errors;
	402	u64 rx_flow_control_packets;
	403
	404	spinlock_t stats_lock;
	405	u32 reg_offset;
	406	struct u64_stats_sync syncp;
	407	};
	408
656e7052	409	enum mtk_tx_flags {
134d2152 SW	410	/* PDMA descriptor can point at 1-2 segments. This enum allows us to
	411	* track how memory was allocated so that it can be freed properly.
	412	*/
656e7052 JC	413	MTK_TX_FLAGS_SINGLE0 = 0x01,
656e7052 JC	414	MTK_TX_FLAGS_PAGE0 = 0x02,
134d2152 SW	415
	416	/* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
	417	* SKB out instead of looking up through hardware TX descriptor.
	418	*/
	419	MTK_TX_FLAGS_FPORT0 = 0x04,
	420	MTK_TX_FLAGS_FPORT1 = 0x08,
656e7052 JC	421	};
656e7052 JC	422
549e5495 SW	423	/* This enum allows us to identify how the clock is defined on the array of the
	424	* clock in the order
	425	*/
	426	enum mtk_clks_map {
	427	MTK_CLK_ETHIF,
	428	MTK_CLK_ESW,
	429	MTK_CLK_GP1,
	430	MTK_CLK_GP2,
f430dea7	431	MTK_CLK_TRGPLL,
549e5495 SW	432	MTK_CLK_MAX
	433	};
	434
9ea4d311	435	enum mtk_dev_state {
dce6fa42 SW	436	MTK_HW_INIT,
dce6fa42 SW	437	MTK_RESETTING
9ea4d311 SW	438	};
9ea4d311 SW	439
656e7052 JC	440	/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
	441	* by the TX descriptor s
	442	* @skb: The SKB pointer of the packet being sent
	443	* @dma_addr0: The base addr of the first segment
	444	* @dma_len0: The length of the first segment
	445	* @dma_addr1: The base addr of the second segment
	446	* @dma_len1: The length of the second segment
	447	*/
	448	struct mtk_tx_buf {
	449	struct sk_buff *skb;
	450	u32 flags;
	451	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
	452	DEFINE_DMA_UNMAP_LEN(dma_len0);
	453	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
	454	DEFINE_DMA_UNMAP_LEN(dma_len1);
	455	};
	456
	457	/* struct mtk_tx_ring - This struct holds info describing a TX ring
	458	* @dma: The descriptor ring
	459	* @buf: The memory pointed at by the ring
	460	* @phys: The physical addr of tx_buf
	461	* @next_free: Pointer to the next free descriptor
	462	* @last_free: Pointer to the last free descriptor
	463	* @thresh: The threshold of minimum amount of free descriptors
	464	* @free_count: QDMA uses a linked list. Track how many free descriptors
	465	* are present
	466	*/
	467	struct mtk_tx_ring {
	468	struct mtk_tx_dma *dma;
	469	struct mtk_tx_buf *buf;
	470	dma_addr_t phys;
	471	struct mtk_tx_dma *next_free;
	472	struct mtk_tx_dma *last_free;
	473	u16 thresh;
	474	atomic_t free_count;
	475	};
	476
ee406810 NC	477	/* PDMA rx ring mode */
	478	enum mtk_rx_flags {
	479	MTK_RX_FLAGS_NORMAL = 0,
	480	MTK_RX_FLAGS_HWLRO,
	481	};
	482
656e7052 JC	483	/* struct mtk_rx_ring - This struct holds info describing a RX ring
	484	* @dma: The descriptor ring
	485	* @data: The memory pointed at by the ring
	486	* @phys: The physical addr of rx_buf
	487	* @frag_size: How big can each fragment be
	488	* @buf_size: The size of each packet buffer
	489	* @calc_idx: The current head of ring
	490	*/
	491	struct mtk_rx_ring {
	492	struct mtk_rx_dma *dma;
	493	u8 **data;
	494	dma_addr_t phys;
	495	u16 frag_size;
	496	u16 buf_size;
ee406810 NC	497	u16 dma_size;
ee406810 NC	498	bool calc_idx_update;
656e7052	499	u16 calc_idx;
ee406810	500	u32 crx_idx_reg;
656e7052 JC	501	};
	502
	503	/* currently no SoC has more than 2 macs */
	504	#define MTK_MAX_DEVS 2
	505
	506	/* struct mtk_eth - This is the main datasructure for holding the state
	507	* of the driver
	508	* @dev: The device pointer
	509	* @base: The mapped register i/o base
	510	* @page_lock: Make sure that register operations are atomic
	511	* @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
	512	* dummy for NAPI to work
	513	* @netdev: The netdev instances
	514	* @mac: Each netdev is linked to a physical MAC
	515	* @irq: The IRQ that we are using
	516	* @msg_enable: Ethtool msg level
	517	* @ethsys: The register map pointing at the range used to setup
	518	* MII modes
	519	* @pctl: The register map pointing at the range used to setup
	520	* GMAC port drive/slew values
	521	* @dma_refcnt: track how many netdevs are using the DMA engine
	522	* @tx_ring: Pointer to the memore holding info about the TX ring
	523	* @rx_ring: Pointer to the memore holding info about the RX ring
80673029 JC	524	* @tx_napi: The TX NAPI struct
80673029 JC	525	* @rx_napi: The RX NAPI struct
656e7052	526	* @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
605e4fe4	527	* @phy_scratch_ring: physical address of scratch_ring
656e7052	528	* @scratch_head: The scratch memory that scratch_ring points to.
549e5495	529	* @clks: clock array for all clocks required
656e7052	530	* @mii_bus: If there is a bus we need to create an instance for it
7c78b4ad	531	* @pending_work: The workqueue used to reset the dma ring
9ea4d311	532	* @state Initialization and runtime state of the device.
656e7052 JC	533	*/
	534
	535	struct mtk_eth {
	536	struct device *dev;
	537	void __iomem *base;
656e7052	538	spinlock_t page_lock;
7bc9ccec	539	spinlock_t irq_lock;
656e7052 JC	540	struct net_device dummy_dev;
	541	struct net_device *netdev[MTK_MAX_DEVS];
	542	struct mtk_mac *mac[MTK_MAX_DEVS];
80673029	543	int irq[3];
656e7052 JC	544	u32 msg_enable;
	545	unsigned long sysclk;
	546	struct regmap *ethsys;
	547	struct regmap *pctl;
b95b6d99	548	u32 chip_id;
ee406810	549	bool hwlro;
656e7052 JC	550	atomic_t dma_refcnt;
656e7052 JC	551	struct mtk_tx_ring tx_ring;
ee406810	552	struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
80673029	553	struct napi_struct tx_napi;
656e7052 JC	554	struct napi_struct rx_napi;
656e7052 JC	555	struct mtk_tx_dma *scratch_ring;
605e4fe4	556	dma_addr_t phy_scratch_ring;
656e7052	557	void *scratch_head;
549e5495 SW	558	struct clk *clks[MTK_CLK_MAX];
549e5495 SW	559
656e7052	560	struct mii_bus *mii_bus;
7c78b4ad	561	struct work_struct pending_work;
9ea4d311	562	unsigned long state;
656e7052 JC	563	};
	564
	565	/* struct mtk_mac - the structure that holds the info about the MACs of the
	566	* SoC
	567	* @id: The number of the MAC
9ea4d311	568	* @ge_mode: Interface mode kept for setup restoring
656e7052 JC	569	* @of_node: Our devicetree node
	570	* @hw: Backpointer to our main datastruture
	571	* @hw_stats: Packet statistics counter
572de608 SW	572	* @trgmii Indicate if the MAC uses TRGMII connected to internal
572de608 SW	573	switch
656e7052 JC	574	*/
	575	struct mtk_mac {
	576	int id;
9ea4d311	577	int ge_mode;
656e7052 JC	578	struct device_node *of_node;
	579	struct mtk_eth *hw;
	580	struct mtk_hw_stats *hw_stats;
ee406810 NC	581	__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
ee406810 NC	582	int hwlro_ip_cnt;
572de608	583	bool trgmii;
656e7052 JC	584	};
	585
	586	/* the struct describing the SoC. these are declared in the soc_xyz.c files */
	587	extern const struct of_device_id of_mtk_match[];
	588
	589	/* read the hardware status register */
	590	void mtk_stats_update_mac(struct mtk_mac *mac);
	591
	592	void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
	593	u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
	594
	595	#endif /* MTK_ETH_H */