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Commit | Line | Data |
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8e8e69d6 TG |
1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* | |
656e7052 JC |
3 | * |
4 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> | |
5 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> | |
6 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> | |
7 | */ | |
8 | ||
9 | #ifndef MTK_ETH_H | |
10 | #define MTK_ETH_H | |
11 | ||
9ffee4a8 SW |
12 | #include <linux/dma-mapping.h> |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/of_net.h> | |
15 | #include <linux/u64_stats_sync.h> | |
c6d4e63e | 16 | #include <linux/refcount.h> |
b8fc9f30 | 17 | #include <linux/phylink.h> |
502e84e2 | 18 | #include <linux/rhashtable.h> |
e9229ffd | 19 | #include <linux/dim.h> |
ba37b7ca | 20 | #include "mtk_ppe.h" |
c6d4e63e | 21 | |
656e7052 | 22 | #define MTK_QDMA_PAGE_SIZE 2048 |
4fd59792 DQ |
23 | #define MTK_MAX_RX_LENGTH 1536 |
24 | #define MTK_MAX_RX_LENGTH_2K 2048 | |
656e7052 | 25 | #define MTK_TX_DMA_BUF_LEN 0x3fff |
6b4423b2 | 26 | #define MTK_DMA_SIZE 512 |
656e7052 JC |
27 | #define MTK_NAPI_WEIGHT 64 |
28 | #define MTK_MAC_COUNT 2 | |
4fd59792 | 29 | #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) |
656e7052 JC |
30 | #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) |
31 | #define MTK_DMA_DUMMY_DESC 0xffffffff | |
32 | #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ | |
33 | NETIF_MSG_PROBE | \ | |
34 | NETIF_MSG_LINK | \ | |
35 | NETIF_MSG_TIMER | \ | |
36 | NETIF_MSG_IFDOWN | \ | |
37 | NETIF_MSG_IFUP | \ | |
38 | NETIF_MSG_RX_ERR | \ | |
39 | NETIF_MSG_TX_ERR) | |
40 | #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ | |
41 | NETIF_F_RXCSUM | \ | |
42 | NETIF_F_HW_VLAN_CTAG_TX | \ | |
43 | NETIF_F_HW_VLAN_CTAG_RX | \ | |
44 | NETIF_F_SG | NETIF_F_TSO | \ | |
45 | NETIF_F_TSO6 | \ | |
502e84e2 FF |
46 | NETIF_F_IPV6_CSUM |\ |
47 | NETIF_F_HW_TC) | |
296c9120 | 48 | #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) |
08df5fa6 | 49 | #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) |
ee406810 NC |
50 | |
51 | #define MTK_MAX_RX_RING_NUM 4 | |
52 | #define MTK_HW_LRO_DMA_SIZE 8 | |
53 | ||
54 | #define MTK_MAX_LRO_RX_LENGTH (4096 * 3) | |
55 | #define MTK_MAX_LRO_IP_CNT 2 | |
56 | #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */ | |
57 | #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */ | |
58 | #define MTK_HW_LRO_AGG_TIME 10 /* 200us */ | |
59 | #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */ | |
60 | #define MTK_HW_LRO_MAX_AGG_CNT 64 | |
61 | #define MTK_HW_LRO_BW_THRE 3000 | |
62 | #define MTK_HW_LRO_REPLACE_DELTA 1000 | |
63 | #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522 | |
656e7052 JC |
64 | |
65 | /* Frame Engine Global Reset Register */ | |
66 | #define MTK_RST_GL 0x04 | |
67 | #define RST_GL_PSE BIT(0) | |
68 | ||
69 | /* Frame Engine Interrupt Status Register */ | |
70 | #define MTK_INT_STATUS2 0x08 | |
71 | #define MTK_GDM1_AF BIT(28) | |
72 | #define MTK_GDM2_AF BIT(29) | |
73 | ||
ee406810 NC |
74 | /* PDMA HW LRO Alter Flow Timer Register */ |
75 | #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c | |
76 | ||
656e7052 JC |
77 | /* Frame Engine Interrupt Grouping Register */ |
78 | #define MTK_FE_INT_GRP 0x20 | |
79 | ||
87e3df49 SW |
80 | /* CDMP Ingress Control Register */ |
81 | #define MTK_CDMQ_IG_CTRL 0x1400 | |
82 | #define MTK_CDMQ_STAG_EN BIT(0) | |
83 | ||
656e7052 JC |
84 | /* CDMP Exgress Control Register */ |
85 | #define MTK_CDMP_EG_CTRL 0x404 | |
86 | ||
87 | /* GDM Exgress Control Register */ | |
88 | #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) | |
d5c53da2 | 89 | #define MTK_GDMA_SPECIAL_TAG BIT(24) |
656e7052 JC |
90 | #define MTK_GDMA_ICS_EN BIT(22) |
91 | #define MTK_GDMA_TCS_EN BIT(21) | |
92 | #define MTK_GDMA_UCS_EN BIT(20) | |
8d3f4a95 | 93 | #define MTK_GDMA_TO_PDMA 0x0 |
ba37b7ca | 94 | #define MTK_GDMA_TO_PPE 0x4444 |
8d66a818 | 95 | #define MTK_GDMA_DROP_ALL 0x7777 |
656e7052 JC |
96 | |
97 | /* Unicast Filter MAC Address Register - Low */ | |
98 | #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) | |
99 | ||
100 | /* Unicast Filter MAC Address Register - High */ | |
101 | #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) | |
102 | ||
bacfd110 NC |
103 | /* PDMA RX Base Pointer Register */ |
104 | #define MTK_PRX_BASE_PTR0 0x900 | |
ee406810 | 105 | #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10)) |
bacfd110 NC |
106 | |
107 | /* PDMA RX Maximum Count Register */ | |
108 | #define MTK_PRX_MAX_CNT0 0x904 | |
ee406810 | 109 | #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10)) |
bacfd110 NC |
110 | |
111 | /* PDMA RX CPU Pointer Register */ | |
112 | #define MTK_PRX_CRX_IDX0 0x908 | |
ee406810 NC |
113 | #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10)) |
114 | ||
115 | /* PDMA HW LRO Control Registers */ | |
116 | #define MTK_PDMA_LRO_CTRL_DW0 0x980 | |
117 | #define MTK_LRO_EN BIT(0) | |
118 | #define MTK_L3_CKS_UPD_EN BIT(7) | |
119 | #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21) | |
ca3ba106 NC |
120 | #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26) |
121 | #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29) | |
ee406810 NC |
122 | |
123 | #define MTK_PDMA_LRO_CTRL_DW1 0x984 | |
124 | #define MTK_PDMA_LRO_CTRL_DW2 0x988 | |
125 | #define MTK_PDMA_LRO_CTRL_DW3 0x98c | |
126 | #define MTK_ADMA_MODE BIT(15) | |
127 | #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16) | |
bacfd110 NC |
128 | |
129 | /* PDMA Global Configuration Register */ | |
130 | #define MTK_PDMA_GLO_CFG 0xa04 | |
131 | #define MTK_MULTI_EN BIT(10) | |
296c9120 | 132 | #define MTK_PDMA_SIZE_8DWORDS (1 << 4) |
bacfd110 NC |
133 | |
134 | /* PDMA Reset Index Register */ | |
135 | #define MTK_PDMA_RST_IDX 0xa08 | |
136 | #define MTK_PST_DRX_IDX0 BIT(16) | |
ee406810 | 137 | #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x)) |
bacfd110 NC |
138 | |
139 | /* PDMA Delay Interrupt Register */ | |
671d41e6 | 140 | #define MTK_PDMA_DELAY_INT 0xa0c |
e9229ffd | 141 | #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) |
671d41e6 | 142 | #define MTK_PDMA_DELAY_RX_EN BIT(15) |
671d41e6 | 143 | #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 |
e9229ffd FF |
144 | #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 |
145 | ||
146 | #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) | |
147 | #define MTK_PDMA_DELAY_TX_EN BIT(31) | |
148 | #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 | |
149 | #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 | |
150 | ||
151 | #define MTK_PDMA_DELAY_PINT_MASK 0x7f | |
152 | #define MTK_PDMA_DELAY_PTIME_MASK 0xff | |
bacfd110 NC |
153 | |
154 | /* PDMA Interrupt Status Register */ | |
155 | #define MTK_PDMA_INT_STATUS 0xa20 | |
156 | ||
157 | /* PDMA Interrupt Mask Register */ | |
158 | #define MTK_PDMA_INT_MASK 0xa28 | |
159 | ||
ee406810 NC |
160 | /* PDMA HW LRO Alter Flow Delta Register */ |
161 | #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c | |
162 | ||
80673029 JC |
163 | /* PDMA Interrupt grouping registers */ |
164 | #define MTK_PDMA_INT_GRP1 0xa50 | |
165 | #define MTK_PDMA_INT_GRP2 0xa54 | |
166 | ||
ee406810 NC |
167 | /* PDMA HW LRO IP Setting Registers */ |
168 | #define MTK_LRO_RX_RING0_DIP_DW0 0xb04 | |
169 | #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40)) | |
170 | #define MTK_RING_MYIP_VLD BIT(9) | |
171 | ||
172 | /* PDMA HW LRO Ring Control Registers */ | |
173 | #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28 | |
174 | #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c | |
175 | #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30 | |
176 | #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40)) | |
177 | #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40)) | |
178 | #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40)) | |
179 | #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22) | |
180 | #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f) | |
181 | #define MTK_RING_AUTO_LERAN_MODE (3 << 6) | |
182 | #define MTK_RING_VLD BIT(8) | |
183 | #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10) | |
184 | #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26) | |
185 | #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3) | |
186 | ||
656e7052 JC |
187 | /* QDMA TX Queue Configuration Registers */ |
188 | #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) | |
189 | #define QDMA_RES_THRES 4 | |
190 | ||
191 | /* QDMA TX Queue Scheduler Registers */ | |
192 | #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) | |
193 | ||
194 | /* QDMA RX Base Pointer Register */ | |
195 | #define MTK_QRX_BASE_PTR0 0x1900 | |
196 | ||
197 | /* QDMA RX Maximum Count Register */ | |
198 | #define MTK_QRX_MAX_CNT0 0x1904 | |
199 | ||
200 | /* QDMA RX CPU Pointer Register */ | |
201 | #define MTK_QRX_CRX_IDX0 0x1908 | |
202 | ||
203 | /* QDMA RX DMA Pointer Register */ | |
204 | #define MTK_QRX_DRX_IDX0 0x190C | |
205 | ||
206 | /* QDMA Global Configuration Register */ | |
207 | #define MTK_QDMA_GLO_CFG 0x1A04 | |
208 | #define MTK_RX_2B_OFFSET BIT(31) | |
209 | #define MTK_RX_BT_32DWORDS (3 << 11) | |
6675086d | 210 | #define MTK_NDP_CO_PRO BIT(10) |
656e7052 | 211 | #define MTK_TX_WB_DDONE BIT(6) |
59555a8d | 212 | #define MTK_TX_BT_32DWORDS (3 << 4) |
656e7052 JC |
213 | #define MTK_RX_DMA_BUSY BIT(3) |
214 | #define MTK_TX_DMA_BUSY BIT(1) | |
215 | #define MTK_RX_DMA_EN BIT(2) | |
216 | #define MTK_TX_DMA_EN BIT(0) | |
3bc8e0af | 217 | #define MTK_DMA_BUSY_TIMEOUT_US 1000000 |
656e7052 JC |
218 | |
219 | /* QDMA Reset Index Register */ | |
220 | #define MTK_QDMA_RST_IDX 0x1A08 | |
656e7052 JC |
221 | |
222 | /* QDMA Delay Interrupt Register */ | |
223 | #define MTK_QDMA_DELAY_INT 0x1A0C | |
224 | ||
225 | /* QDMA Flow Control Register */ | |
226 | #define MTK_QDMA_FC_THRES 0x1A10 | |
227 | #define FC_THRES_DROP_MODE BIT(20) | |
228 | #define FC_THRES_DROP_EN (7 << 16) | |
229 | #define FC_THRES_MIN 0x4444 | |
230 | ||
231 | /* QDMA Interrupt Status Register */ | |
45487403 | 232 | #define MTK_QDMA_INT_STATUS 0x1A18 |
671d41e6 | 233 | #define MTK_RX_DONE_DLY BIT(30) |
e9229ffd | 234 | #define MTK_TX_DONE_DLY BIT(28) |
bacfd110 NC |
235 | #define MTK_RX_DONE_INT3 BIT(19) |
236 | #define MTK_RX_DONE_INT2 BIT(18) | |
656e7052 JC |
237 | #define MTK_RX_DONE_INT1 BIT(17) |
238 | #define MTK_RX_DONE_INT0 BIT(16) | |
239 | #define MTK_TX_DONE_INT3 BIT(3) | |
240 | #define MTK_TX_DONE_INT2 BIT(2) | |
241 | #define MTK_TX_DONE_INT1 BIT(1) | |
242 | #define MTK_TX_DONE_INT0 BIT(0) | |
671d41e6 | 243 | #define MTK_RX_DONE_INT MTK_RX_DONE_DLY |
e9229ffd | 244 | #define MTK_TX_DONE_INT MTK_TX_DONE_DLY |
656e7052 | 245 | |
80673029 JC |
246 | /* QDMA Interrupt grouping registers */ |
247 | #define MTK_QDMA_INT_GRP1 0x1a20 | |
248 | #define MTK_QDMA_INT_GRP2 0x1a24 | |
249 | #define MTK_RLS_DONE_INT BIT(0) | |
250 | ||
656e7052 JC |
251 | /* QDMA Interrupt Status Register */ |
252 | #define MTK_QDMA_INT_MASK 0x1A1C | |
253 | ||
254 | /* QDMA Interrupt Mask Register */ | |
255 | #define MTK_QDMA_HRED2 0x1A44 | |
256 | ||
257 | /* QDMA TX Forward CPU Pointer Register */ | |
258 | #define MTK_QTX_CTX_PTR 0x1B00 | |
259 | ||
260 | /* QDMA TX Forward DMA Pointer Register */ | |
261 | #define MTK_QTX_DTX_PTR 0x1B04 | |
262 | ||
263 | /* QDMA TX Release CPU Pointer Register */ | |
264 | #define MTK_QTX_CRX_PTR 0x1B10 | |
265 | ||
266 | /* QDMA TX Release DMA Pointer Register */ | |
267 | #define MTK_QTX_DRX_PTR 0x1B14 | |
268 | ||
269 | /* QDMA FQ Head Pointer Register */ | |
270 | #define MTK_QDMA_FQ_HEAD 0x1B20 | |
271 | ||
272 | /* QDMA FQ Head Pointer Register */ | |
273 | #define MTK_QDMA_FQ_TAIL 0x1B24 | |
274 | ||
275 | /* QDMA FQ Free Page Counter Register */ | |
276 | #define MTK_QDMA_FQ_CNT 0x1B28 | |
277 | ||
278 | /* QDMA FQ Free Page Buffer Length Register */ | |
279 | #define MTK_QDMA_FQ_BLEN 0x1B2C | |
280 | ||
ad79fd2c SR |
281 | /* GMA1 counter / statics register */ |
282 | #define MTK_GDM1_RX_GBCNT_L 0x2400 | |
283 | #define MTK_GDM1_RX_GBCNT_H 0x2404 | |
284 | #define MTK_GDM1_RX_GPCNT 0x2408 | |
285 | #define MTK_GDM1_RX_OERCNT 0x2410 | |
286 | #define MTK_GDM1_RX_FERCNT 0x2414 | |
287 | #define MTK_GDM1_RX_SERCNT 0x2418 | |
288 | #define MTK_GDM1_RX_LENCNT 0x241c | |
289 | #define MTK_GDM1_RX_CERCNT 0x2420 | |
290 | #define MTK_GDM1_RX_FCCNT 0x2424 | |
291 | #define MTK_GDM1_TX_SKIPCNT 0x2428 | |
292 | #define MTK_GDM1_TX_COLCNT 0x242c | |
293 | #define MTK_GDM1_TX_GBCNT_L 0x2430 | |
294 | #define MTK_GDM1_TX_GBCNT_H 0x2434 | |
295 | #define MTK_GDM1_TX_GPCNT 0x2438 | |
656e7052 JC |
296 | #define MTK_STAT_OFFSET 0x40 |
297 | ||
298 | /* QDMA descriptor txd4 */ | |
299 | #define TX_DMA_CHKSUM (0x7 << 29) | |
300 | #define TX_DMA_TSO BIT(28) | |
301 | #define TX_DMA_FPORT_SHIFT 25 | |
302 | #define TX_DMA_FPORT_MASK 0x7 | |
303 | #define TX_DMA_INS_VLAN BIT(16) | |
304 | ||
305 | /* QDMA descriptor txd3 */ | |
306 | #define TX_DMA_OWNER_CPU BIT(31) | |
307 | #define TX_DMA_LS0 BIT(30) | |
308 | #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) | |
296c9120 | 309 | #define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN) |
656e7052 JC |
310 | #define TX_DMA_SWC BIT(14) |
311 | #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) | |
312 | ||
296c9120 SR |
313 | /* PDMA on MT7628 */ |
314 | #define TX_DMA_DONE BIT(31) | |
315 | #define TX_DMA_LS1 BIT(14) | |
316 | #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE) | |
317 | ||
656e7052 JC |
318 | /* QDMA descriptor rxd2 */ |
319 | #define RX_DMA_DONE BIT(31) | |
296c9120 | 320 | #define RX_DMA_LSO BIT(30) |
656e7052 JC |
321 | #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) |
322 | #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) | |
3f57d8c4 | 323 | #define RX_DMA_VTAG BIT(15) |
656e7052 JC |
324 | |
325 | /* QDMA descriptor rxd3 */ | |
326 | #define RX_DMA_VID(_x) ((_x) & 0xfff) | |
327 | ||
ba37b7ca FF |
328 | /* QDMA descriptor rxd4 */ |
329 | #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) | |
330 | #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) | |
331 | #define MTK_RXD4_SRC_PORT GENMASK(21, 19) | |
332 | #define MTK_RXD4_ALG GENMASK(31, 22) | |
333 | ||
656e7052 JC |
334 | /* QDMA descriptor rxd4 */ |
335 | #define RX_DMA_L4_VALID BIT(24) | |
296c9120 | 336 | #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ |
656e7052 JC |
337 | #define RX_DMA_FPORT_SHIFT 19 |
338 | #define RX_DMA_FPORT_MASK 0x7 | |
d5c53da2 | 339 | #define RX_DMA_SPECIAL_TAG BIT(22) |
656e7052 JC |
340 | |
341 | /* PHY Indirect Access Control registers */ | |
342 | #define MTK_PHY_IAC 0x10004 | |
343 | #define PHY_IAC_ACCESS BIT(31) | |
04e8f84a DG |
344 | #define PHY_IAC_REG_MASK GENMASK(29, 25) |
345 | #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) | |
346 | #define PHY_IAC_ADDR_MASK GENMASK(24, 20) | |
347 | #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) | |
348 | #define PHY_IAC_CMD_MASK GENMASK(19, 18) | |
349 | #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) | |
350 | #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) | |
351 | #define PHY_IAC_START_MASK GENMASK(17, 16) | |
352 | #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) | |
353 | #define PHY_IAC_DATA_MASK GENMASK(15, 0) | |
354 | #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) | |
656e7052 JC |
355 | #define PHY_IAC_TIMEOUT HZ |
356 | ||
42c03844 SW |
357 | #define MTK_MAC_MISC 0x1000c |
358 | #define MTK_MUX_TO_ESW BIT(0) | |
359 | ||
656e7052 JC |
360 | /* Mac control registers */ |
361 | #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) | |
4fd59792 DQ |
362 | #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) |
363 | #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) | |
364 | #define MAC_MCR_MAX_RX_1518 0x0 | |
365 | #define MAC_MCR_MAX_RX_1536 0x1 | |
366 | #define MAC_MCR_MAX_RX_1552 0x2 | |
367 | #define MAC_MCR_MAX_RX_2048 0x3 | |
656e7052 JC |
368 | #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) |
369 | #define MAC_MCR_FORCE_MODE BIT(15) | |
370 | #define MAC_MCR_TX_EN BIT(14) | |
371 | #define MAC_MCR_RX_EN BIT(13) | |
372 | #define MAC_MCR_BACKOFF_EN BIT(9) | |
373 | #define MAC_MCR_BACKPR_EN BIT(8) | |
374 | #define MAC_MCR_FORCE_RX_FC BIT(5) | |
375 | #define MAC_MCR_FORCE_TX_FC BIT(4) | |
376 | #define MAC_MCR_SPEED_1000 BIT(3) | |
377 | #define MAC_MCR_SPEED_100 BIT(2) | |
378 | #define MAC_MCR_FORCE_DPX BIT(1) | |
379 | #define MAC_MCR_FORCE_LINK BIT(0) | |
b8fc9f30 RD |
380 | #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) |
381 | ||
382 | /* Mac status registers */ | |
383 | #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) | |
384 | #define MAC_MSR_EEE1G BIT(7) | |
385 | #define MAC_MSR_EEE100M BIT(6) | |
386 | #define MAC_MSR_RX_FC BIT(5) | |
387 | #define MAC_MSR_TX_FC BIT(4) | |
388 | #define MAC_MSR_SPEED_1000 BIT(3) | |
389 | #define MAC_MSR_SPEED_100 BIT(2) | |
390 | #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100) | |
391 | #define MAC_MSR_DPX BIT(1) | |
392 | #define MAC_MSR_LINK BIT(0) | |
656e7052 | 393 | |
f430dea7 SW |
394 | /* TRGMII RXC control register */ |
395 | #define TRGMII_RCK_CTRL 0x10300 | |
396 | #define DQSI0(x) ((x << 0) & GENMASK(6, 0)) | |
397 | #define DQSI1(x) ((x << 8) & GENMASK(14, 8)) | |
398 | #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) | |
a5d75538 | 399 | #define RXC_RST BIT(31) |
f430dea7 SW |
400 | #define RXC_DQSISEL BIT(30) |
401 | #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) | |
402 | #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) | |
403 | ||
a5d75538 RD |
404 | #define NUM_TRGMII_CTRL 5 |
405 | ||
f430dea7 SW |
406 | /* TRGMII RXC control register */ |
407 | #define TRGMII_TCK_CTRL 0x10340 | |
408 | #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) | |
409 | #define TXC_INV BIT(30) | |
410 | #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) | |
411 | #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) | |
412 | ||
a5d75538 RD |
413 | /* TRGMII TX Drive Strength */ |
414 | #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i)) | |
415 | #define TD_DM_DRVP(x) ((x) & 0xf) | |
416 | #define TD_DM_DRVN(x) (((x) & 0xf) << 4) | |
417 | ||
f430dea7 SW |
418 | /* TRGMII Interface mode register */ |
419 | #define INTF_MODE 0x10390 | |
420 | #define TRGMII_INTF_DIS BIT(0) | |
421 | #define TRGMII_MODE BIT(1) | |
422 | #define TRGMII_CENTRAL_ALIGNED BIT(2) | |
423 | #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) | |
424 | #define INTF_MODE_RGMII_10_100 0 | |
425 | ||
656e7052 JC |
426 | /* GPIO port control registers for GMAC 2*/ |
427 | #define GPIO_OD33_CTRL8 0x4c0 | |
428 | #define GPIO_BIAS_CTRL 0xed0 | |
429 | #define GPIO_DRV_SEL10 0xf00 | |
430 | ||
b95b6d99 NC |
431 | /* ethernet subsystem chip id register */ |
432 | #define ETHSYS_CHIPID0_3 0x0 | |
433 | #define ETHSYS_CHIPID4_7 0x4 | |
983e1a6c | 434 | #define MT7623_ETH 7623 |
42c03844 | 435 | #define MT7622_ETH 7622 |
889bcbde | 436 | #define MT7621_ETH 7621 |
b95b6d99 | 437 | |
8efaa653 RD |
438 | /* ethernet system control register */ |
439 | #define ETHSYS_SYSCFG 0x10 | |
440 | #define SYSCFG_DRAM_TYPE_DDR2 BIT(4) | |
441 | ||
656e7052 JC |
442 | /* ethernet subsystem config register */ |
443 | #define ETHSYS_SYSCFG0 0x14 | |
444 | #define SYSCFG0_GE_MASK 0x3 | |
445 | #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) | |
7093f9d8 SW |
446 | #define SYSCFG0_SGMII_MASK GENMASK(9, 8) |
447 | #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK) | |
448 | #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) | |
449 | #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) | |
450 | #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) | |
451 | ||
656e7052 | 452 | |
f430dea7 SW |
453 | /* ethernet subsystem clock register */ |
454 | #define ETHSYS_CLKCFG0 0x2c | |
455 | #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) | |
8efaa653 RD |
456 | #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6)) |
457 | #define ETHSYS_TRGMII_MT7621_APLL BIT(6) | |
458 | #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5) | |
f430dea7 SW |
459 | |
460 | /* ethernet reset control register */ | |
2a8307aa SW |
461 | #define ETHSYS_RSTCTRL 0x34 |
462 | #define RSTCTRL_FE BIT(6) | |
463 | #define RSTCTRL_PPE BIT(31) | |
464 | ||
42c03844 SW |
465 | /* SGMII subsystem config registers */ |
466 | /* Register to auto-negotiation restart */ | |
467 | #define SGMSYS_PCS_CONTROL_1 0x0 | |
468 | #define SGMII_AN_RESTART BIT(9) | |
7e538372 RD |
469 | #define SGMII_ISOLATE BIT(10) |
470 | #define SGMII_AN_ENABLE BIT(12) | |
471 | #define SGMII_LINK_STATYS BIT(18) | |
472 | #define SGMII_AN_ABILITY BIT(19) | |
473 | #define SGMII_AN_COMPLETE BIT(21) | |
474 | #define SGMII_PCS_FAULT BIT(23) | |
475 | #define SGMII_AN_EXPANSION_CLR BIT(30) | |
42c03844 SW |
476 | |
477 | /* Register to programmable link timer, the unit in 2 * 8ns */ | |
478 | #define SGMSYS_PCS_LINK_TIMER 0x18 | |
479 | #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) | |
480 | ||
481 | /* Register to control remote fault */ | |
7e538372 RD |
482 | #define SGMSYS_SGMII_MODE 0x20 |
483 | #define SGMII_IF_MODE_BIT0 BIT(0) | |
484 | #define SGMII_SPEED_DUPLEX_AN BIT(1) | |
485 | #define SGMII_SPEED_10 0x0 | |
486 | #define SGMII_SPEED_100 BIT(2) | |
487 | #define SGMII_SPEED_1000 BIT(3) | |
488 | #define SGMII_DUPLEX_FULL BIT(4) | |
489 | #define SGMII_IF_MODE_BIT5 BIT(5) | |
490 | #define SGMII_REMOTE_FAULT_DIS BIT(8) | |
491 | #define SGMII_CODE_SYNC_SET_VAL BIT(9) | |
492 | #define SGMII_CODE_SYNC_SET_EN BIT(10) | |
493 | #define SGMII_SEND_AN_ERROR_EN BIT(11) | |
494 | #define SGMII_IF_MODE_MASK GENMASK(5, 1) | |
495 | ||
496 | /* Register to set SGMII speed, ANA RG_ Control Signals III*/ | |
497 | #define SGMSYS_ANA_RG_CS3 0x2028 | |
498 | #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) | |
499 | #define RG_PHY_SPEED_1_25G 0x0 | |
500 | #define RG_PHY_SPEED_3_125G BIT(2) | |
42c03844 SW |
501 | |
502 | /* Register to power up QPHY */ | |
503 | #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 | |
504 | #define SGMII_PHYA_PWD BIT(4) | |
505 | ||
7093f9d8 SW |
506 | /* Infrasys subsystem config registers */ |
507 | #define INFRA_MISC2 0x70c | |
508 | #define CO_QPHY_SEL BIT(0) | |
509 | #define GEPHY_MAC_SEL BIT(1) | |
510 | ||
296c9120 SR |
511 | /* MT7628/88 specific stuff */ |
512 | #define MT7628_PDMA_OFFSET 0x0800 | |
513 | #define MT7628_SDM_OFFSET 0x0c00 | |
514 | ||
515 | #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00) | |
516 | #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04) | |
517 | #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08) | |
518 | #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c) | |
519 | #define MT7628_PST_DTX_IDX0 BIT(0) | |
520 | ||
521 | #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c) | |
522 | #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10) | |
523 | ||
ad79fd2c SR |
524 | /* Counter / stat register */ |
525 | #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100) | |
526 | #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104) | |
527 | #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108) | |
528 | #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c) | |
529 | #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110) | |
530 | ||
656e7052 JC |
531 | struct mtk_rx_dma { |
532 | unsigned int rxd1; | |
533 | unsigned int rxd2; | |
534 | unsigned int rxd3; | |
535 | unsigned int rxd4; | |
536 | } __packed __aligned(4); | |
537 | ||
538 | struct mtk_tx_dma { | |
539 | unsigned int txd1; | |
540 | unsigned int txd2; | |
541 | unsigned int txd3; | |
542 | unsigned int txd4; | |
543 | } __packed __aligned(4); | |
544 | ||
545 | struct mtk_eth; | |
546 | struct mtk_mac; | |
547 | ||
548 | /* struct mtk_hw_stats - the structure that holds the traffic statistics. | |
549 | * @stats_lock: make sure that stats operations are atomic | |
550 | * @reg_offset: the status register offset of the SoC | |
551 | * @syncp: the refcount | |
552 | * | |
553 | * All of the supported SoCs have hardware counters for traffic statistics. | |
554 | * Whenever the status IRQ triggers we can read the latest stats from these | |
555 | * counters and store them in this struct. | |
556 | */ | |
557 | struct mtk_hw_stats { | |
558 | u64 tx_bytes; | |
559 | u64 tx_packets; | |
560 | u64 tx_skip; | |
561 | u64 tx_collisions; | |
562 | u64 rx_bytes; | |
563 | u64 rx_packets; | |
564 | u64 rx_overflow; | |
565 | u64 rx_fcs_errors; | |
566 | u64 rx_short_errors; | |
567 | u64 rx_long_errors; | |
568 | u64 rx_checksum_errors; | |
569 | u64 rx_flow_control_packets; | |
570 | ||
571 | spinlock_t stats_lock; | |
572 | u32 reg_offset; | |
573 | struct u64_stats_sync syncp; | |
574 | }; | |
575 | ||
656e7052 | 576 | enum mtk_tx_flags { |
134d2152 SW |
577 | /* PDMA descriptor can point at 1-2 segments. This enum allows us to |
578 | * track how memory was allocated so that it can be freed properly. | |
579 | */ | |
656e7052 JC |
580 | MTK_TX_FLAGS_SINGLE0 = 0x01, |
581 | MTK_TX_FLAGS_PAGE0 = 0x02, | |
134d2152 SW |
582 | |
583 | /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted | |
584 | * SKB out instead of looking up through hardware TX descriptor. | |
585 | */ | |
586 | MTK_TX_FLAGS_FPORT0 = 0x04, | |
587 | MTK_TX_FLAGS_FPORT1 = 0x08, | |
656e7052 JC |
588 | }; |
589 | ||
549e5495 SW |
590 | /* This enum allows us to identify how the clock is defined on the array of the |
591 | * clock in the order | |
592 | */ | |
593 | enum mtk_clks_map { | |
594 | MTK_CLK_ETHIF, | |
d438e298 | 595 | MTK_CLK_SGMIITOP, |
549e5495 | 596 | MTK_CLK_ESW, |
42c03844 | 597 | MTK_CLK_GP0, |
549e5495 SW |
598 | MTK_CLK_GP1, |
599 | MTK_CLK_GP2, | |
d438e298 | 600 | MTK_CLK_FE, |
f430dea7 | 601 | MTK_CLK_TRGPLL, |
42c03844 SW |
602 | MTK_CLK_SGMII_TX_250M, |
603 | MTK_CLK_SGMII_RX_250M, | |
604 | MTK_CLK_SGMII_CDR_REF, | |
605 | MTK_CLK_SGMII_CDR_FB, | |
d438e298 SW |
606 | MTK_CLK_SGMII2_TX_250M, |
607 | MTK_CLK_SGMII2_RX_250M, | |
608 | MTK_CLK_SGMII2_CDR_REF, | |
609 | MTK_CLK_SGMII2_CDR_FB, | |
42c03844 SW |
610 | MTK_CLK_SGMII_CK, |
611 | MTK_CLK_ETH2PLL, | |
549e5495 SW |
612 | MTK_CLK_MAX |
613 | }; | |
614 | ||
2ec50f57 SW |
615 | #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
616 | BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ | |
617 | BIT(MTK_CLK_TRGPLL)) | |
42c03844 SW |
618 | #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
619 | BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ | |
620 | BIT(MTK_CLK_GP2) | \ | |
621 | BIT(MTK_CLK_SGMII_TX_250M) | \ | |
622 | BIT(MTK_CLK_SGMII_RX_250M) | \ | |
623 | BIT(MTK_CLK_SGMII_CDR_REF) | \ | |
624 | BIT(MTK_CLK_SGMII_CDR_FB) | \ | |
625 | BIT(MTK_CLK_SGMII_CK) | \ | |
626 | BIT(MTK_CLK_ETH2PLL)) | |
889bcbde | 627 | #define MT7621_CLKS_BITMAP (0) |
296c9120 | 628 | #define MT7628_CLKS_BITMAP (0) |
d438e298 SW |
629 | #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ |
630 | BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ | |
631 | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ | |
632 | BIT(MTK_CLK_SGMII_TX_250M) | \ | |
633 | BIT(MTK_CLK_SGMII_RX_250M) | \ | |
634 | BIT(MTK_CLK_SGMII_CDR_REF) | \ | |
635 | BIT(MTK_CLK_SGMII_CDR_FB) | \ | |
636 | BIT(MTK_CLK_SGMII2_TX_250M) | \ | |
637 | BIT(MTK_CLK_SGMII2_RX_250M) | \ | |
638 | BIT(MTK_CLK_SGMII2_CDR_REF) | \ | |
639 | BIT(MTK_CLK_SGMII2_CDR_FB) | \ | |
640 | BIT(MTK_CLK_SGMII_CK) | \ | |
641 | BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) | |
889bcbde | 642 | |
9ea4d311 | 643 | enum mtk_dev_state { |
dce6fa42 SW |
644 | MTK_HW_INIT, |
645 | MTK_RESETTING | |
9ea4d311 SW |
646 | }; |
647 | ||
656e7052 JC |
648 | /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at |
649 | * by the TX descriptor s | |
650 | * @skb: The SKB pointer of the packet being sent | |
651 | * @dma_addr0: The base addr of the first segment | |
652 | * @dma_len0: The length of the first segment | |
653 | * @dma_addr1: The base addr of the second segment | |
654 | * @dma_len1: The length of the second segment | |
655 | */ | |
656 | struct mtk_tx_buf { | |
657 | struct sk_buff *skb; | |
658 | u32 flags; | |
659 | DEFINE_DMA_UNMAP_ADDR(dma_addr0); | |
660 | DEFINE_DMA_UNMAP_LEN(dma_len0); | |
661 | DEFINE_DMA_UNMAP_ADDR(dma_addr1); | |
662 | DEFINE_DMA_UNMAP_LEN(dma_len1); | |
663 | }; | |
664 | ||
665 | /* struct mtk_tx_ring - This struct holds info describing a TX ring | |
666 | * @dma: The descriptor ring | |
667 | * @buf: The memory pointed at by the ring | |
668 | * @phys: The physical addr of tx_buf | |
669 | * @next_free: Pointer to the next free descriptor | |
670 | * @last_free: Pointer to the last free descriptor | |
4e6bf609 | 671 | * @last_free_ptr: Hardware pointer value of the last free descriptor |
656e7052 JC |
672 | * @thresh: The threshold of minimum amount of free descriptors |
673 | * @free_count: QDMA uses a linked list. Track how many free descriptors | |
674 | * are present | |
675 | */ | |
676 | struct mtk_tx_ring { | |
677 | struct mtk_tx_dma *dma; | |
678 | struct mtk_tx_buf *buf; | |
679 | dma_addr_t phys; | |
680 | struct mtk_tx_dma *next_free; | |
681 | struct mtk_tx_dma *last_free; | |
4e6bf609 | 682 | u32 last_free_ptr; |
656e7052 JC |
683 | u16 thresh; |
684 | atomic_t free_count; | |
296c9120 SR |
685 | int dma_size; |
686 | struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */ | |
687 | dma_addr_t phys_pdma; | |
688 | int cpu_idx; | |
656e7052 JC |
689 | }; |
690 | ||
ee406810 NC |
691 | /* PDMA rx ring mode */ |
692 | enum mtk_rx_flags { | |
693 | MTK_RX_FLAGS_NORMAL = 0, | |
694 | MTK_RX_FLAGS_HWLRO, | |
6427dc1d | 695 | MTK_RX_FLAGS_QDMA, |
ee406810 NC |
696 | }; |
697 | ||
656e7052 JC |
698 | /* struct mtk_rx_ring - This struct holds info describing a RX ring |
699 | * @dma: The descriptor ring | |
700 | * @data: The memory pointed at by the ring | |
701 | * @phys: The physical addr of rx_buf | |
702 | * @frag_size: How big can each fragment be | |
703 | * @buf_size: The size of each packet buffer | |
704 | * @calc_idx: The current head of ring | |
705 | */ | |
706 | struct mtk_rx_ring { | |
707 | struct mtk_rx_dma *dma; | |
708 | u8 **data; | |
709 | dma_addr_t phys; | |
710 | u16 frag_size; | |
711 | u16 buf_size; | |
ee406810 NC |
712 | u16 dma_size; |
713 | bool calc_idx_update; | |
656e7052 | 714 | u16 calc_idx; |
ee406810 | 715 | u32 crx_idx_reg; |
656e7052 JC |
716 | }; |
717 | ||
e2c74694 RD |
718 | enum mkt_eth_capabilities { |
719 | MTK_RGMII_BIT = 0, | |
720 | MTK_TRGMII_BIT, | |
721 | MTK_SGMII_BIT, | |
722 | MTK_ESW_BIT, | |
723 | MTK_GEPHY_BIT, | |
724 | MTK_MUX_BIT, | |
725 | MTK_INFRA_BIT, | |
726 | MTK_SHARED_SGMII_BIT, | |
727 | MTK_HWLRO_BIT, | |
728 | MTK_SHARED_INT_BIT, | |
729 | MTK_TRGMII_MT7621_CLK_BIT, | |
296c9120 SR |
730 | MTK_QDMA_BIT, |
731 | MTK_SOC_MT7628_BIT, | |
e2c74694 RD |
732 | |
733 | /* MUX BITS*/ | |
734 | MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, | |
735 | MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, | |
736 | MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, | |
737 | MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, | |
738 | MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, | |
739 | ||
740 | /* PATH BITS */ | |
741 | MTK_ETH_PATH_GMAC1_RGMII_BIT, | |
742 | MTK_ETH_PATH_GMAC1_TRGMII_BIT, | |
743 | MTK_ETH_PATH_GMAC1_SGMII_BIT, | |
744 | MTK_ETH_PATH_GMAC2_RGMII_BIT, | |
745 | MTK_ETH_PATH_GMAC2_SGMII_BIT, | |
746 | MTK_ETH_PATH_GMAC2_GEPHY_BIT, | |
747 | MTK_ETH_PATH_GDM1_ESW_BIT, | |
7093f9d8 SW |
748 | }; |
749 | ||
750 | /* Supported hardware group on SoCs */ | |
e2c74694 RD |
751 | #define MTK_RGMII BIT(MTK_RGMII_BIT) |
752 | #define MTK_TRGMII BIT(MTK_TRGMII_BIT) | |
753 | #define MTK_SGMII BIT(MTK_SGMII_BIT) | |
754 | #define MTK_ESW BIT(MTK_ESW_BIT) | |
755 | #define MTK_GEPHY BIT(MTK_GEPHY_BIT) | |
756 | #define MTK_MUX BIT(MTK_MUX_BIT) | |
757 | #define MTK_INFRA BIT(MTK_INFRA_BIT) | |
758 | #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) | |
759 | #define MTK_HWLRO BIT(MTK_HWLRO_BIT) | |
760 | #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) | |
761 | #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) | |
296c9120 SR |
762 | #define MTK_QDMA BIT(MTK_QDMA_BIT) |
763 | #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) | |
e2c74694 RD |
764 | |
765 | #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ | |
766 | BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) | |
767 | #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ | |
768 | BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) | |
769 | #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ | |
770 | BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) | |
771 | #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ | |
772 | BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) | |
773 | #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ | |
774 | BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) | |
7093f9d8 SW |
775 | |
776 | /* Supported path present on SoCs */ | |
e2c74694 RD |
777 | #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) |
778 | #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) | |
779 | #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) | |
780 | #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) | |
781 | #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) | |
782 | #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) | |
783 | #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) | |
784 | ||
785 | #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) | |
786 | #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) | |
787 | #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII) | |
788 | #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) | |
789 | #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) | |
790 | #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) | |
791 | #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) | |
7093f9d8 SW |
792 | |
793 | /* MUXes present on SoCs */ | |
794 | /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ | |
e2c74694 | 795 | #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX) |
7093f9d8 SW |
796 | |
797 | /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */ | |
798 | #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \ | |
e2c74694 | 799 | (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA) |
7093f9d8 SW |
800 | |
801 | /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */ | |
802 | #define MTK_MUX_U3_GMAC2_TO_QPHY \ | |
e2c74694 | 803 | (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA) |
7093f9d8 SW |
804 | |
805 | /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */ | |
806 | #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ | |
e2c74694 | 807 | (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ |
7093f9d8 SW |
808 | MTK_SHARED_SGMII) |
809 | ||
810 | /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ | |
811 | #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ | |
e2c74694 | 812 | (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) |
7093f9d8 | 813 | |
2ec50f57 SW |
814 | #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) |
815 | ||
8efaa653 | 816 | #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ |
296c9120 SR |
817 | MTK_GMAC2_RGMII | MTK_SHARED_INT | \ |
818 | MTK_TRGMII_MT7621_CLK | MTK_QDMA) | |
8efaa653 | 819 | |
7093f9d8 SW |
820 | #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ |
821 | MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ | |
822 | MTK_MUX_GDM1_TO_GMAC1_ESW | \ | |
296c9120 SR |
823 | MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) |
824 | ||
825 | #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ | |
826 | MTK_QDMA) | |
7093f9d8 | 827 | |
296c9120 | 828 | #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) |
7093f9d8 SW |
829 | |
830 | #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ | |
831 | MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ | |
832 | MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ | |
833 | MTK_MUX_U3_GMAC2_TO_QPHY | \ | |
296c9120 | 834 | MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) |
7093f9d8 | 835 | |
42c03844 | 836 | /* struct mtk_eth_data - This is the structure holding all differences |
2ec50f57 | 837 | * among various plaforms |
9ffee4a8 SW |
838 | * @ana_rgc3: The offset for register ANA_RGC3 related to |
839 | * sgmiisys syscon | |
2ec50f57 | 840 | * @caps Flags shown the extra capability for the SoC |
296c9120 | 841 | * @hw_features Flags shown HW features |
2ec50f57 SW |
842 | * @required_clks Flags shown the bitmap for required clocks on |
843 | * the target SoC | |
243dc5fb SW |
844 | * @required_pctl A bool value to show whether the SoC requires |
845 | * the extra setup for those pins used by GMAC. | |
2ec50f57 SW |
846 | */ |
847 | struct mtk_soc_data { | |
9ffee4a8 | 848 | u32 ana_rgc3; |
2ec50f57 SW |
849 | u32 caps; |
850 | u32 required_clks; | |
243dc5fb | 851 | bool required_pctl; |
ba37b7ca | 852 | u8 offload_version; |
296c9120 | 853 | netdev_features_t hw_features; |
2ec50f57 SW |
854 | }; |
855 | ||
656e7052 JC |
856 | /* currently no SoC has more than 2 macs */ |
857 | #define MTK_MAX_DEVS 2 | |
858 | ||
9ffee4a8 | 859 | #define MTK_SGMII_PHYSPEED_AN BIT(31) |
937a9440 | 860 | #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) |
9ffee4a8 SW |
861 | #define MTK_SGMII_PHYSPEED_1000 BIT(0) |
862 | #define MTK_SGMII_PHYSPEED_2500 BIT(1) | |
863 | #define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) | |
864 | ||
865 | /* struct mtk_sgmii - This is the structure holding sgmii regmap and its | |
866 | * characteristics | |
867 | * @regmap: The register map pointing at the range used to setup | |
868 | * SGMII modes | |
869 | * @flags: The enum refers to which mode the sgmii wants to run on | |
870 | * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap | |
871 | */ | |
872 | ||
873 | struct mtk_sgmii { | |
874 | struct regmap *regmap[MTK_MAX_DEVS]; | |
875 | u32 flags[MTK_MAX_DEVS]; | |
876 | u32 ana_rgc3; | |
877 | }; | |
878 | ||
656e7052 JC |
879 | /* struct mtk_eth - This is the main datasructure for holding the state |
880 | * of the driver | |
881 | * @dev: The device pointer | |
882 | * @base: The mapped register i/o base | |
883 | * @page_lock: Make sure that register operations are atomic | |
5cce0322 JC |
884 | * @tx_irq__lock: Make sure that IRQ register operations are atomic |
885 | * @rx_irq__lock: Make sure that IRQ register operations are atomic | |
e9229ffd | 886 | * @dim_lock: Make sure that Net DIM operations are atomic |
656e7052 JC |
887 | * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a |
888 | * dummy for NAPI to work | |
889 | * @netdev: The netdev instances | |
890 | * @mac: Each netdev is linked to a physical MAC | |
891 | * @irq: The IRQ that we are using | |
892 | * @msg_enable: Ethtool msg level | |
893 | * @ethsys: The register map pointing at the range used to setup | |
894 | * MII modes | |
7093f9d8 SW |
895 | * @infra: The register map pointing at the range used to setup |
896 | * SGMII and GePHY path | |
656e7052 JC |
897 | * @pctl: The register map pointing at the range used to setup |
898 | * GMAC port drive/slew values | |
899 | * @dma_refcnt: track how many netdevs are using the DMA engine | |
0c07ce7f JC |
900 | * @tx_ring: Pointer to the memory holding info about the TX ring |
901 | * @rx_ring: Pointer to the memory holding info about the RX ring | |
6427dc1d | 902 | * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring |
80673029 JC |
903 | * @tx_napi: The TX NAPI struct |
904 | * @rx_napi: The RX NAPI struct | |
e9229ffd FF |
905 | * @rx_events: Net DIM RX event counter |
906 | * @rx_packets: Net DIM RX packet counter | |
907 | * @rx_bytes: Net DIM RX byte counter | |
908 | * @rx_dim: Net DIM RX context | |
909 | * @tx_events: Net DIM TX event counter | |
910 | * @tx_packets: Net DIM TX packet counter | |
911 | * @tx_bytes: Net DIM TX byte counter | |
912 | * @tx_dim: Net DIM TX context | |
656e7052 | 913 | * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring |
605e4fe4 | 914 | * @phy_scratch_ring: physical address of scratch_ring |
656e7052 | 915 | * @scratch_head: The scratch memory that scratch_ring points to. |
549e5495 | 916 | * @clks: clock array for all clocks required |
656e7052 | 917 | * @mii_bus: If there is a bus we need to create an instance for it |
7c78b4ad | 918 | * @pending_work: The workqueue used to reset the dma ring |
42c03844 | 919 | * @state: Initialization and runtime state of the device |
2ec50f57 | 920 | * @soc: Holding specific data among vaious SoCs |
656e7052 JC |
921 | */ |
922 | ||
923 | struct mtk_eth { | |
924 | struct device *dev; | |
925 | void __iomem *base; | |
656e7052 | 926 | spinlock_t page_lock; |
5cce0322 JC |
927 | spinlock_t tx_irq_lock; |
928 | spinlock_t rx_irq_lock; | |
656e7052 JC |
929 | struct net_device dummy_dev; |
930 | struct net_device *netdev[MTK_MAX_DEVS]; | |
931 | struct mtk_mac *mac[MTK_MAX_DEVS]; | |
80673029 | 932 | int irq[3]; |
656e7052 JC |
933 | u32 msg_enable; |
934 | unsigned long sysclk; | |
935 | struct regmap *ethsys; | |
7093f9d8 | 936 | struct regmap *infra; |
9ffee4a8 | 937 | struct mtk_sgmii *sgmii; |
656e7052 | 938 | struct regmap *pctl; |
ee406810 | 939 | bool hwlro; |
c6d4e63e | 940 | refcount_t dma_refcnt; |
656e7052 | 941 | struct mtk_tx_ring tx_ring; |
ee406810 | 942 | struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM]; |
6427dc1d | 943 | struct mtk_rx_ring rx_ring_qdma; |
80673029 | 944 | struct napi_struct tx_napi; |
656e7052 JC |
945 | struct napi_struct rx_napi; |
946 | struct mtk_tx_dma *scratch_ring; | |
605e4fe4 | 947 | dma_addr_t phy_scratch_ring; |
656e7052 | 948 | void *scratch_head; |
549e5495 SW |
949 | struct clk *clks[MTK_CLK_MAX]; |
950 | ||
656e7052 | 951 | struct mii_bus *mii_bus; |
7c78b4ad | 952 | struct work_struct pending_work; |
9ea4d311 | 953 | unsigned long state; |
2ec50f57 SW |
954 | |
955 | const struct mtk_soc_data *soc; | |
296c9120 | 956 | |
e9229ffd FF |
957 | spinlock_t dim_lock; |
958 | ||
959 | u32 rx_events; | |
960 | u32 rx_packets; | |
961 | u32 rx_bytes; | |
962 | struct dim rx_dim; | |
963 | ||
964 | u32 tx_events; | |
965 | u32 tx_packets; | |
966 | u32 tx_bytes; | |
967 | struct dim tx_dim; | |
968 | ||
296c9120 SR |
969 | u32 tx_int_mask_reg; |
970 | u32 tx_int_status_reg; | |
971 | u32 rx_dma_l4_valid; | |
972 | int ip_align; | |
ba37b7ca FF |
973 | |
974 | struct mtk_ppe ppe; | |
502e84e2 | 975 | struct rhashtable flow_table; |
656e7052 JC |
976 | }; |
977 | ||
978 | /* struct mtk_mac - the structure that holds the info about the MACs of the | |
979 | * SoC | |
980 | * @id: The number of the MAC | |
b8fc9f30 | 981 | * @interface: Interface mode kept for detecting change in hw settings |
656e7052 JC |
982 | * @of_node: Our devicetree node |
983 | * @hw: Backpointer to our main datastruture | |
984 | * @hw_stats: Packet statistics counter | |
656e7052 JC |
985 | */ |
986 | struct mtk_mac { | |
987 | int id; | |
b8fc9f30 RD |
988 | phy_interface_t interface; |
989 | unsigned int mode; | |
990 | int speed; | |
656e7052 | 991 | struct device_node *of_node; |
b8fc9f30 RD |
992 | struct phylink *phylink; |
993 | struct phylink_config phylink_config; | |
656e7052 JC |
994 | struct mtk_eth *hw; |
995 | struct mtk_hw_stats *hw_stats; | |
ee406810 NC |
996 | __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; |
997 | int hwlro_ip_cnt; | |
656e7052 JC |
998 | }; |
999 | ||
1000 | /* the struct describing the SoC. these are declared in the soc_xyz.c files */ | |
1001 | extern const struct of_device_id of_mtk_match[]; | |
1002 | ||
1003 | /* read the hardware status register */ | |
1004 | void mtk_stats_update_mac(struct mtk_mac *mac); | |
1005 | ||
1006 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); | |
1007 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg); | |
1008 | ||
9ffee4a8 SW |
1009 | int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, |
1010 | u32 ana_rgc3); | |
1011 | int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); | |
7e538372 RD |
1012 | int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, |
1013 | const struct phylink_link_state *state); | |
1014 | void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); | |
1015 | ||
1016 | int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); | |
1017 | int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); | |
1018 | int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); | |
9ffee4a8 | 1019 | |
502e84e2 FF |
1020 | int mtk_eth_offload_init(struct mtk_eth *eth); |
1021 | int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, | |
1022 | void *type_data); | |
1023 | ||
1024 | ||
656e7052 | 1025 | #endif /* MTK_ETH_H */ |