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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/sched.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
ee40fa06 | 37 | #include <linux/export.h> |
225c7b1f RD |
38 | #include <linux/pci.h> |
39 | #include <linux/errno.h> | |
40 | ||
41 | #include <linux/mlx4/cmd.h> | |
e8f081aa | 42 | #include <linux/semaphore.h> |
225c7b1f RD |
43 | |
44 | #include <asm/io.h> | |
45 | ||
46 | #include "mlx4.h" | |
e8f081aa | 47 | #include "fw.h" |
225c7b1f RD |
48 | |
49 | #define CMD_POLL_TOKEN 0xffff | |
e8f081aa YP |
50 | #define INBOX_MASK 0xffffffffffffff00ULL |
51 | ||
52 | #define CMD_CHAN_VER 1 | |
53 | #define CMD_CHAN_IF_REV 1 | |
225c7b1f RD |
54 | |
55 | enum { | |
56 | /* command completed successfully: */ | |
57 | CMD_STAT_OK = 0x00, | |
58 | /* Internal error (such as a bus error) occurred while processing command: */ | |
59 | CMD_STAT_INTERNAL_ERR = 0x01, | |
60 | /* Operation/command not supported or opcode modifier not supported: */ | |
61 | CMD_STAT_BAD_OP = 0x02, | |
62 | /* Parameter not supported or parameter out of range: */ | |
63 | CMD_STAT_BAD_PARAM = 0x03, | |
64 | /* System not enabled or bad system state: */ | |
65 | CMD_STAT_BAD_SYS_STATE = 0x04, | |
66 | /* Attempt to access reserved or unallocaterd resource: */ | |
67 | CMD_STAT_BAD_RESOURCE = 0x05, | |
68 | /* Requested resource is currently executing a command, or is otherwise busy: */ | |
69 | CMD_STAT_RESOURCE_BUSY = 0x06, | |
70 | /* Required capability exceeds device limits: */ | |
71 | CMD_STAT_EXCEED_LIM = 0x08, | |
72 | /* Resource is not in the appropriate state or ownership: */ | |
73 | CMD_STAT_BAD_RES_STATE = 0x09, | |
74 | /* Index out of range: */ | |
75 | CMD_STAT_BAD_INDEX = 0x0a, | |
76 | /* FW image corrupted: */ | |
77 | CMD_STAT_BAD_NVMEM = 0x0b, | |
899698da JM |
78 | /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */ |
79 | CMD_STAT_ICM_ERROR = 0x0c, | |
225c7b1f RD |
80 | /* Attempt to modify a QP/EE which is not in the presumed state: */ |
81 | CMD_STAT_BAD_QP_STATE = 0x10, | |
82 | /* Bad segment parameters (Address/Size): */ | |
83 | CMD_STAT_BAD_SEG_PARAM = 0x20, | |
84 | /* Memory Region has Memory Windows bound to: */ | |
85 | CMD_STAT_REG_BOUND = 0x21, | |
86 | /* HCA local attached memory not present: */ | |
87 | CMD_STAT_LAM_NOT_PRE = 0x22, | |
88 | /* Bad management packet (silently discarded): */ | |
89 | CMD_STAT_BAD_PKT = 0x30, | |
90 | /* More outstanding CQEs in CQ than new CQ size: */ | |
cc4ac2e7 YP |
91 | CMD_STAT_BAD_SIZE = 0x40, |
92 | /* Multi Function device support required: */ | |
93 | CMD_STAT_MULTI_FUNC_REQ = 0x50, | |
225c7b1f RD |
94 | }; |
95 | ||
96 | enum { | |
97 | HCR_IN_PARAM_OFFSET = 0x00, | |
98 | HCR_IN_MODIFIER_OFFSET = 0x08, | |
99 | HCR_OUT_PARAM_OFFSET = 0x0c, | |
100 | HCR_TOKEN_OFFSET = 0x14, | |
101 | HCR_STATUS_OFFSET = 0x18, | |
102 | ||
103 | HCR_OPMOD_SHIFT = 12, | |
104 | HCR_T_BIT = 21, | |
105 | HCR_E_BIT = 22, | |
106 | HCR_GO_BIT = 23 | |
107 | }; | |
108 | ||
109 | enum { | |
36ce10d3 | 110 | GO_BIT_TIMEOUT_MSECS = 10000 |
225c7b1f RD |
111 | }; |
112 | ||
113 | struct mlx4_cmd_context { | |
114 | struct completion done; | |
115 | int result; | |
116 | int next; | |
117 | u64 out_param; | |
118 | u16 token; | |
e8f081aa | 119 | u8 fw_status; |
225c7b1f RD |
120 | }; |
121 | ||
e8f081aa YP |
122 | static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave, |
123 | struct mlx4_vhcr_cmd *in_vhcr); | |
124 | ||
ca281211 RD |
125 | static int mlx4_status_to_errno(u8 status) |
126 | { | |
225c7b1f RD |
127 | static const int trans_table[] = { |
128 | [CMD_STAT_INTERNAL_ERR] = -EIO, | |
129 | [CMD_STAT_BAD_OP] = -EPERM, | |
130 | [CMD_STAT_BAD_PARAM] = -EINVAL, | |
131 | [CMD_STAT_BAD_SYS_STATE] = -ENXIO, | |
132 | [CMD_STAT_BAD_RESOURCE] = -EBADF, | |
133 | [CMD_STAT_RESOURCE_BUSY] = -EBUSY, | |
134 | [CMD_STAT_EXCEED_LIM] = -ENOMEM, | |
135 | [CMD_STAT_BAD_RES_STATE] = -EBADF, | |
136 | [CMD_STAT_BAD_INDEX] = -EBADF, | |
137 | [CMD_STAT_BAD_NVMEM] = -EFAULT, | |
899698da | 138 | [CMD_STAT_ICM_ERROR] = -ENFILE, |
225c7b1f RD |
139 | [CMD_STAT_BAD_QP_STATE] = -EINVAL, |
140 | [CMD_STAT_BAD_SEG_PARAM] = -EFAULT, | |
141 | [CMD_STAT_REG_BOUND] = -EBUSY, | |
142 | [CMD_STAT_LAM_NOT_PRE] = -EAGAIN, | |
143 | [CMD_STAT_BAD_PKT] = -EINVAL, | |
144 | [CMD_STAT_BAD_SIZE] = -ENOMEM, | |
cc4ac2e7 | 145 | [CMD_STAT_MULTI_FUNC_REQ] = -EACCES, |
225c7b1f RD |
146 | }; |
147 | ||
148 | if (status >= ARRAY_SIZE(trans_table) || | |
149 | (status != CMD_STAT_OK && trans_table[status] == 0)) | |
150 | return -EIO; | |
151 | ||
152 | return trans_table[status]; | |
153 | } | |
154 | ||
e8f081aa YP |
155 | static int comm_pending(struct mlx4_dev *dev) |
156 | { | |
157 | struct mlx4_priv *priv = mlx4_priv(dev); | |
158 | u32 status = readl(&priv->mfunc.comm->slave_read); | |
159 | ||
160 | return (swab32(status) >> 31) != priv->cmd.comm_toggle; | |
161 | } | |
162 | ||
163 | static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param) | |
164 | { | |
165 | struct mlx4_priv *priv = mlx4_priv(dev); | |
166 | u32 val; | |
167 | ||
168 | priv->cmd.comm_toggle ^= 1; | |
169 | val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31); | |
170 | __raw_writel((__force u32) cpu_to_be32(val), | |
171 | &priv->mfunc.comm->slave_write); | |
172 | mmiowb(); | |
173 | } | |
174 | ||
e8f081aa YP |
175 | static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param, |
176 | unsigned long timeout) | |
177 | { | |
178 | struct mlx4_priv *priv = mlx4_priv(dev); | |
179 | unsigned long end; | |
180 | int err = 0; | |
181 | int ret_from_pending = 0; | |
182 | ||
183 | /* First, verify that the master reports correct status */ | |
184 | if (comm_pending(dev)) { | |
185 | mlx4_warn(dev, "Communication channel is not idle." | |
186 | "my toggle is %d (cmd:0x%x)\n", | |
187 | priv->cmd.comm_toggle, cmd); | |
188 | return -EAGAIN; | |
189 | } | |
190 | ||
191 | /* Write command */ | |
192 | down(&priv->cmd.poll_sem); | |
193 | mlx4_comm_cmd_post(dev, cmd, param); | |
194 | ||
195 | end = msecs_to_jiffies(timeout) + jiffies; | |
196 | while (comm_pending(dev) && time_before(jiffies, end)) | |
197 | cond_resched(); | |
198 | ret_from_pending = comm_pending(dev); | |
199 | if (ret_from_pending) { | |
200 | /* check if the slave is trying to boot in the middle of | |
201 | * FLR process. The only non-zero result in the RESET command | |
202 | * is MLX4_DELAY_RESET_SLAVE*/ | |
203 | if ((MLX4_COMM_CMD_RESET == cmd)) { | |
204 | mlx4_warn(dev, "Got slave FLRed from Communication" | |
205 | " channel (ret:0x%x)\n", ret_from_pending); | |
206 | err = MLX4_DELAY_RESET_SLAVE; | |
207 | } else { | |
208 | mlx4_warn(dev, "Communication channel timed out\n"); | |
209 | err = -ETIMEDOUT; | |
210 | } | |
211 | } | |
212 | ||
213 | up(&priv->cmd.poll_sem); | |
214 | return err; | |
215 | } | |
216 | ||
217 | static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op, | |
218 | u16 param, unsigned long timeout) | |
219 | { | |
220 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
221 | struct mlx4_cmd_context *context; | |
222 | int err = 0; | |
223 | ||
224 | down(&cmd->event_sem); | |
225 | ||
226 | spin_lock(&cmd->context_lock); | |
227 | BUG_ON(cmd->free_head < 0); | |
228 | context = &cmd->context[cmd->free_head]; | |
229 | context->token += cmd->token_mask + 1; | |
230 | cmd->free_head = context->next; | |
231 | spin_unlock(&cmd->context_lock); | |
232 | ||
233 | init_completion(&context->done); | |
234 | ||
235 | mlx4_comm_cmd_post(dev, op, param); | |
236 | ||
237 | if (!wait_for_completion_timeout(&context->done, | |
238 | msecs_to_jiffies(timeout))) { | |
239 | err = -EBUSY; | |
240 | goto out; | |
241 | } | |
242 | ||
243 | err = context->result; | |
244 | if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) { | |
245 | mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", | |
246 | op, context->fw_status); | |
247 | goto out; | |
248 | } | |
249 | ||
250 | out: | |
251 | spin_lock(&cmd->context_lock); | |
252 | context->next = cmd->free_head; | |
253 | cmd->free_head = context - cmd->context; | |
254 | spin_unlock(&cmd->context_lock); | |
255 | ||
256 | up(&cmd->event_sem); | |
257 | return err; | |
258 | } | |
259 | ||
260 | static int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, | |
261 | unsigned long timeout) | |
262 | { | |
263 | if (mlx4_priv(dev)->cmd.use_events) | |
264 | return mlx4_comm_cmd_wait(dev, cmd, param, timeout); | |
265 | return mlx4_comm_cmd_poll(dev, cmd, param, timeout); | |
266 | } | |
267 | ||
225c7b1f RD |
268 | static int cmd_pending(struct mlx4_dev *dev) |
269 | { | |
270 | u32 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); | |
271 | ||
272 | return (status & swab32(1 << HCR_GO_BIT)) || | |
273 | (mlx4_priv(dev)->cmd.toggle == | |
274 | !!(status & swab32(1 << HCR_T_BIT))); | |
275 | } | |
276 | ||
277 | static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param, | |
278 | u32 in_modifier, u8 op_modifier, u16 op, u16 token, | |
279 | int event) | |
280 | { | |
281 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
282 | u32 __iomem *hcr = cmd->hcr; | |
283 | int ret = -EAGAIN; | |
284 | unsigned long end; | |
285 | ||
286 | mutex_lock(&cmd->hcr_mutex); | |
287 | ||
288 | end = jiffies; | |
289 | if (event) | |
36ce10d3 | 290 | end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS); |
225c7b1f RD |
291 | |
292 | while (cmd_pending(dev)) { | |
e8f081aa YP |
293 | if (time_after_eq(jiffies, end)) { |
294 | mlx4_err(dev, "%s:cmd_pending failed\n", __func__); | |
225c7b1f | 295 | goto out; |
e8f081aa | 296 | } |
225c7b1f RD |
297 | cond_resched(); |
298 | } | |
299 | ||
300 | /* | |
301 | * We use writel (instead of something like memcpy_toio) | |
302 | * because writes of less than 32 bits to the HCR don't work | |
303 | * (and some architectures such as ia64 implement memcpy_toio | |
304 | * in terms of writeb). | |
305 | */ | |
306 | __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0); | |
307 | __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1); | |
308 | __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2); | |
309 | __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3); | |
310 | __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4); | |
311 | __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5); | |
312 | ||
313 | /* __raw_writel may not order writes. */ | |
314 | wmb(); | |
315 | ||
316 | __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | | |
317 | (cmd->toggle << HCR_T_BIT) | | |
318 | (event ? (1 << HCR_E_BIT) : 0) | | |
319 | (op_modifier << HCR_OPMOD_SHIFT) | | |
e8f081aa | 320 | op), hcr + 6); |
2e61c646 RD |
321 | |
322 | /* | |
323 | * Make sure that our HCR writes don't get mixed in with | |
324 | * writes from another CPU starting a FW command. | |
325 | */ | |
326 | mmiowb(); | |
327 | ||
225c7b1f RD |
328 | cmd->toggle = cmd->toggle ^ 1; |
329 | ||
330 | ret = 0; | |
331 | ||
332 | out: | |
333 | mutex_unlock(&cmd->hcr_mutex); | |
334 | return ret; | |
335 | } | |
336 | ||
e8f081aa YP |
337 | static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, |
338 | int out_is_imm, u32 in_modifier, u8 op_modifier, | |
339 | u16 op, unsigned long timeout) | |
340 | { | |
341 | struct mlx4_priv *priv = mlx4_priv(dev); | |
342 | struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr; | |
343 | int ret; | |
344 | ||
345 | down(&priv->cmd.slave_sem); | |
346 | vhcr->in_param = cpu_to_be64(in_param); | |
347 | vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0; | |
348 | vhcr->in_modifier = cpu_to_be32(in_modifier); | |
349 | vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff)); | |
350 | vhcr->token = cpu_to_be16(CMD_POLL_TOKEN); | |
351 | vhcr->status = 0; | |
352 | vhcr->flags = !!(priv->cmd.use_events) << 6; | |
353 | if (mlx4_is_master(dev)) { | |
354 | ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr); | |
355 | if (!ret) { | |
356 | if (out_is_imm) { | |
357 | if (out_param) | |
358 | *out_param = | |
359 | be64_to_cpu(vhcr->out_param); | |
360 | else { | |
361 | mlx4_err(dev, "response expected while" | |
362 | "output mailbox is NULL for " | |
363 | "command 0x%x\n", op); | |
364 | vhcr->status = -EINVAL; | |
365 | } | |
366 | } | |
367 | ret = vhcr->status; | |
368 | } | |
369 | } else { | |
370 | ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, | |
371 | MLX4_COMM_TIME + timeout); | |
372 | if (!ret) { | |
373 | if (out_is_imm) { | |
374 | if (out_param) | |
375 | *out_param = | |
376 | be64_to_cpu(vhcr->out_param); | |
377 | else { | |
378 | mlx4_err(dev, "response expected while" | |
379 | "output mailbox is NULL for " | |
380 | "command 0x%x\n", op); | |
381 | vhcr->status = -EINVAL; | |
382 | } | |
383 | } | |
384 | ret = vhcr->status; | |
385 | } else | |
386 | mlx4_err(dev, "failed execution of VHCR_POST command" | |
387 | "opcode 0x%x\n", op); | |
388 | } | |
389 | up(&priv->cmd.slave_sem); | |
390 | return ret; | |
391 | } | |
392 | ||
225c7b1f RD |
393 | static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param, |
394 | int out_is_imm, u32 in_modifier, u8 op_modifier, | |
395 | u16 op, unsigned long timeout) | |
396 | { | |
397 | struct mlx4_priv *priv = mlx4_priv(dev); | |
398 | void __iomem *hcr = priv->cmd.hcr; | |
399 | int err = 0; | |
400 | unsigned long end; | |
e8f081aa | 401 | u32 stat; |
225c7b1f RD |
402 | |
403 | down(&priv->cmd.poll_sem); | |
404 | ||
405 | err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, | |
406 | in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0); | |
407 | if (err) | |
408 | goto out; | |
409 | ||
410 | end = msecs_to_jiffies(timeout) + jiffies; | |
411 | while (cmd_pending(dev) && time_before(jiffies, end)) | |
412 | cond_resched(); | |
413 | ||
414 | if (cmd_pending(dev)) { | |
415 | err = -ETIMEDOUT; | |
416 | goto out; | |
417 | } | |
418 | ||
419 | if (out_is_imm) | |
420 | *out_param = | |
421 | (u64) be32_to_cpu((__force __be32) | |
422 | __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 | | |
423 | (u64) be32_to_cpu((__force __be32) | |
424 | __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4)); | |
e8f081aa YP |
425 | stat = be32_to_cpu((__force __be32) |
426 | __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24; | |
427 | err = mlx4_status_to_errno(stat); | |
428 | if (err) | |
429 | mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", | |
430 | op, stat); | |
225c7b1f RD |
431 | |
432 | out: | |
433 | up(&priv->cmd.poll_sem); | |
434 | return err; | |
435 | } | |
436 | ||
437 | void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param) | |
438 | { | |
439 | struct mlx4_priv *priv = mlx4_priv(dev); | |
440 | struct mlx4_cmd_context *context = | |
441 | &priv->cmd.context[token & priv->cmd.token_mask]; | |
442 | ||
443 | /* previously timed out command completing at long last */ | |
444 | if (token != context->token) | |
445 | return; | |
446 | ||
e8f081aa | 447 | context->fw_status = status; |
225c7b1f RD |
448 | context->result = mlx4_status_to_errno(status); |
449 | context->out_param = out_param; | |
450 | ||
225c7b1f RD |
451 | complete(&context->done); |
452 | } | |
453 | ||
454 | static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param, | |
455 | int out_is_imm, u32 in_modifier, u8 op_modifier, | |
456 | u16 op, unsigned long timeout) | |
457 | { | |
458 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
459 | struct mlx4_cmd_context *context; | |
460 | int err = 0; | |
461 | ||
462 | down(&cmd->event_sem); | |
463 | ||
464 | spin_lock(&cmd->context_lock); | |
465 | BUG_ON(cmd->free_head < 0); | |
466 | context = &cmd->context[cmd->free_head]; | |
0981582d | 467 | context->token += cmd->token_mask + 1; |
225c7b1f RD |
468 | cmd->free_head = context->next; |
469 | spin_unlock(&cmd->context_lock); | |
470 | ||
471 | init_completion(&context->done); | |
472 | ||
473 | mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0, | |
474 | in_modifier, op_modifier, op, context->token, 1); | |
475 | ||
e8f081aa YP |
476 | if (!wait_for_completion_timeout(&context->done, |
477 | msecs_to_jiffies(timeout))) { | |
225c7b1f RD |
478 | err = -EBUSY; |
479 | goto out; | |
480 | } | |
481 | ||
482 | err = context->result; | |
e8f081aa YP |
483 | if (err) { |
484 | mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n", | |
485 | op, context->fw_status); | |
225c7b1f | 486 | goto out; |
e8f081aa | 487 | } |
225c7b1f RD |
488 | |
489 | if (out_is_imm) | |
490 | *out_param = context->out_param; | |
491 | ||
492 | out: | |
493 | spin_lock(&cmd->context_lock); | |
494 | context->next = cmd->free_head; | |
495 | cmd->free_head = context - cmd->context; | |
496 | spin_unlock(&cmd->context_lock); | |
497 | ||
498 | up(&cmd->event_sem); | |
499 | return err; | |
500 | } | |
501 | ||
502 | int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, | |
503 | int out_is_imm, u32 in_modifier, u8 op_modifier, | |
f9baff50 | 504 | u16 op, unsigned long timeout, int native) |
225c7b1f | 505 | { |
e8f081aa YP |
506 | if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) { |
507 | if (mlx4_priv(dev)->cmd.use_events) | |
508 | return mlx4_cmd_wait(dev, in_param, out_param, | |
509 | out_is_imm, in_modifier, | |
510 | op_modifier, op, timeout); | |
511 | else | |
512 | return mlx4_cmd_poll(dev, in_param, out_param, | |
513 | out_is_imm, in_modifier, | |
514 | op_modifier, op, timeout); | |
515 | } | |
516 | return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm, | |
517 | in_modifier, op_modifier, op, timeout); | |
225c7b1f RD |
518 | } |
519 | EXPORT_SYMBOL_GPL(__mlx4_cmd); | |
520 | ||
e8f081aa YP |
521 | |
522 | static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev) | |
523 | { | |
524 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL, | |
525 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
526 | } | |
527 | ||
528 | static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr, | |
529 | int slave, u64 slave_addr, | |
530 | int size, int is_read) | |
531 | { | |
532 | u64 in_param; | |
533 | u64 out_param; | |
534 | ||
535 | if ((slave_addr & 0xfff) | (master_addr & 0xfff) | | |
536 | (slave & ~0x7f) | (size & 0xff)) { | |
537 | mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx " | |
538 | "master_addr:0x%llx slave_id:%d size:%d\n", | |
539 | slave_addr, master_addr, slave, size); | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | if (is_read) { | |
544 | in_param = (u64) slave | slave_addr; | |
545 | out_param = (u64) dev->caps.function | master_addr; | |
546 | } else { | |
547 | in_param = (u64) dev->caps.function | master_addr; | |
548 | out_param = (u64) slave | slave_addr; | |
549 | } | |
550 | ||
551 | return mlx4_cmd_imm(dev, in_param, &out_param, size, 0, | |
552 | MLX4_CMD_ACCESS_MEM, | |
553 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
554 | } | |
555 | ||
556 | int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, | |
557 | struct mlx4_vhcr *vhcr, | |
558 | struct mlx4_cmd_mailbox *inbox, | |
559 | struct mlx4_cmd_mailbox *outbox, | |
560 | struct mlx4_cmd_info *cmd) | |
561 | { | |
562 | u64 in_param; | |
563 | u64 out_param; | |
564 | int err; | |
565 | ||
566 | in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param; | |
567 | out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param; | |
568 | if (cmd->encode_slave_id) { | |
569 | in_param &= 0xffffffffffffff00ll; | |
570 | in_param |= slave; | |
571 | } | |
572 | ||
573 | err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm, | |
574 | vhcr->in_modifier, vhcr->op_modifier, vhcr->op, | |
575 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
576 | ||
577 | if (cmd->out_is_imm) | |
578 | vhcr->out_param = out_param; | |
579 | ||
580 | return err; | |
581 | } | |
582 | ||
583 | static struct mlx4_cmd_info cmd_info[] = { | |
584 | { | |
585 | .opcode = MLX4_CMD_QUERY_FW, | |
586 | .has_inbox = false, | |
587 | .has_outbox = true, | |
588 | .out_is_imm = false, | |
589 | .encode_slave_id = false, | |
590 | .verify = NULL, | |
591 | .wrapper = NULL | |
592 | }, | |
593 | { | |
594 | .opcode = MLX4_CMD_QUERY_HCA, | |
595 | .has_inbox = false, | |
596 | .has_outbox = true, | |
597 | .out_is_imm = false, | |
598 | .encode_slave_id = false, | |
599 | .verify = NULL, | |
600 | .wrapper = NULL | |
601 | }, | |
602 | { | |
603 | .opcode = MLX4_CMD_QUERY_DEV_CAP, | |
604 | .has_inbox = false, | |
605 | .has_outbox = true, | |
606 | .out_is_imm = false, | |
607 | .encode_slave_id = false, | |
608 | .verify = NULL, | |
609 | .wrapper = NULL | |
610 | }, | |
c82e9aa0 EC |
611 | { |
612 | .opcode = MLX4_CMD_QUERY_FUNC_CAP, | |
613 | .has_inbox = false, | |
614 | .has_outbox = true, | |
615 | .out_is_imm = false, | |
616 | .encode_slave_id = false, | |
617 | .verify = NULL, | |
618 | .wrapper = mlx4_QUERY_FUNC_CAP_wrapper | |
619 | }, | |
620 | { | |
621 | .opcode = MLX4_CMD_QUERY_ADAPTER, | |
622 | .has_inbox = false, | |
623 | .has_outbox = true, | |
624 | .out_is_imm = false, | |
625 | .encode_slave_id = false, | |
626 | .verify = NULL, | |
627 | .wrapper = NULL | |
628 | }, | |
629 | { | |
630 | .opcode = MLX4_CMD_INIT_PORT, | |
631 | .has_inbox = false, | |
632 | .has_outbox = false, | |
633 | .out_is_imm = false, | |
634 | .encode_slave_id = false, | |
635 | .verify = NULL, | |
636 | .wrapper = mlx4_INIT_PORT_wrapper | |
637 | }, | |
638 | { | |
639 | .opcode = MLX4_CMD_CLOSE_PORT, | |
640 | .has_inbox = false, | |
641 | .has_outbox = false, | |
642 | .out_is_imm = false, | |
643 | .encode_slave_id = false, | |
644 | .verify = NULL, | |
645 | .wrapper = mlx4_CLOSE_PORT_wrapper | |
646 | }, | |
647 | { | |
648 | .opcode = MLX4_CMD_QUERY_PORT, | |
649 | .has_inbox = false, | |
650 | .has_outbox = true, | |
651 | .out_is_imm = false, | |
652 | .encode_slave_id = false, | |
653 | .verify = NULL, | |
654 | .wrapper = mlx4_QUERY_PORT_wrapper | |
655 | }, | |
656 | { | |
657 | .opcode = MLX4_CMD_MAP_EQ, | |
658 | .has_inbox = false, | |
659 | .has_outbox = false, | |
660 | .out_is_imm = false, | |
661 | .encode_slave_id = false, | |
662 | .verify = NULL, | |
663 | .wrapper = mlx4_MAP_EQ_wrapper | |
664 | }, | |
665 | { | |
666 | .opcode = MLX4_CMD_SW2HW_EQ, | |
667 | .has_inbox = true, | |
668 | .has_outbox = false, | |
669 | .out_is_imm = false, | |
670 | .encode_slave_id = true, | |
671 | .verify = NULL, | |
672 | .wrapper = mlx4_SW2HW_EQ_wrapper | |
673 | }, | |
674 | { | |
675 | .opcode = MLX4_CMD_HW_HEALTH_CHECK, | |
676 | .has_inbox = false, | |
677 | .has_outbox = false, | |
678 | .out_is_imm = false, | |
679 | .encode_slave_id = false, | |
680 | .verify = NULL, | |
681 | .wrapper = NULL | |
682 | }, | |
683 | { | |
684 | .opcode = MLX4_CMD_NOP, | |
685 | .has_inbox = false, | |
686 | .has_outbox = false, | |
687 | .out_is_imm = false, | |
688 | .encode_slave_id = false, | |
689 | .verify = NULL, | |
690 | .wrapper = NULL | |
691 | }, | |
692 | { | |
693 | .opcode = MLX4_CMD_ALLOC_RES, | |
694 | .has_inbox = false, | |
695 | .has_outbox = false, | |
696 | .out_is_imm = true, | |
697 | .encode_slave_id = false, | |
698 | .verify = NULL, | |
699 | .wrapper = mlx4_ALLOC_RES_wrapper | |
700 | }, | |
701 | { | |
702 | .opcode = MLX4_CMD_FREE_RES, | |
703 | .has_inbox = false, | |
704 | .has_outbox = false, | |
705 | .out_is_imm = false, | |
706 | .encode_slave_id = false, | |
707 | .verify = NULL, | |
708 | .wrapper = mlx4_FREE_RES_wrapper | |
709 | }, | |
710 | { | |
711 | .opcode = MLX4_CMD_SW2HW_MPT, | |
712 | .has_inbox = true, | |
713 | .has_outbox = false, | |
714 | .out_is_imm = false, | |
715 | .encode_slave_id = true, | |
716 | .verify = NULL, | |
717 | .wrapper = mlx4_SW2HW_MPT_wrapper | |
718 | }, | |
719 | { | |
720 | .opcode = MLX4_CMD_QUERY_MPT, | |
721 | .has_inbox = false, | |
722 | .has_outbox = true, | |
723 | .out_is_imm = false, | |
724 | .encode_slave_id = false, | |
725 | .verify = NULL, | |
726 | .wrapper = mlx4_QUERY_MPT_wrapper | |
727 | }, | |
728 | { | |
729 | .opcode = MLX4_CMD_HW2SW_MPT, | |
730 | .has_inbox = false, | |
731 | .has_outbox = false, | |
732 | .out_is_imm = false, | |
733 | .encode_slave_id = false, | |
734 | .verify = NULL, | |
735 | .wrapper = mlx4_HW2SW_MPT_wrapper | |
736 | }, | |
737 | { | |
738 | .opcode = MLX4_CMD_READ_MTT, | |
739 | .has_inbox = false, | |
740 | .has_outbox = true, | |
741 | .out_is_imm = false, | |
742 | .encode_slave_id = false, | |
743 | .verify = NULL, | |
744 | .wrapper = NULL | |
745 | }, | |
746 | { | |
747 | .opcode = MLX4_CMD_WRITE_MTT, | |
748 | .has_inbox = true, | |
749 | .has_outbox = false, | |
750 | .out_is_imm = false, | |
751 | .encode_slave_id = false, | |
752 | .verify = NULL, | |
753 | .wrapper = mlx4_WRITE_MTT_wrapper | |
754 | }, | |
755 | { | |
756 | .opcode = MLX4_CMD_SYNC_TPT, | |
757 | .has_inbox = true, | |
758 | .has_outbox = false, | |
759 | .out_is_imm = false, | |
760 | .encode_slave_id = false, | |
761 | .verify = NULL, | |
762 | .wrapper = NULL | |
763 | }, | |
764 | { | |
765 | .opcode = MLX4_CMD_HW2SW_EQ, | |
766 | .has_inbox = false, | |
767 | .has_outbox = true, | |
768 | .out_is_imm = false, | |
769 | .encode_slave_id = true, | |
770 | .verify = NULL, | |
771 | .wrapper = mlx4_HW2SW_EQ_wrapper | |
772 | }, | |
773 | { | |
774 | .opcode = MLX4_CMD_QUERY_EQ, | |
775 | .has_inbox = false, | |
776 | .has_outbox = true, | |
777 | .out_is_imm = false, | |
778 | .encode_slave_id = true, | |
779 | .verify = NULL, | |
780 | .wrapper = mlx4_QUERY_EQ_wrapper | |
781 | }, | |
782 | { | |
783 | .opcode = MLX4_CMD_SW2HW_CQ, | |
784 | .has_inbox = true, | |
785 | .has_outbox = false, | |
786 | .out_is_imm = false, | |
787 | .encode_slave_id = true, | |
788 | .verify = NULL, | |
789 | .wrapper = mlx4_SW2HW_CQ_wrapper | |
790 | }, | |
791 | { | |
792 | .opcode = MLX4_CMD_HW2SW_CQ, | |
793 | .has_inbox = false, | |
794 | .has_outbox = false, | |
795 | .out_is_imm = false, | |
796 | .encode_slave_id = false, | |
797 | .verify = NULL, | |
798 | .wrapper = mlx4_HW2SW_CQ_wrapper | |
799 | }, | |
800 | { | |
801 | .opcode = MLX4_CMD_QUERY_CQ, | |
802 | .has_inbox = false, | |
803 | .has_outbox = true, | |
804 | .out_is_imm = false, | |
805 | .encode_slave_id = false, | |
806 | .verify = NULL, | |
807 | .wrapper = mlx4_QUERY_CQ_wrapper | |
808 | }, | |
809 | { | |
810 | .opcode = MLX4_CMD_MODIFY_CQ, | |
811 | .has_inbox = true, | |
812 | .has_outbox = false, | |
813 | .out_is_imm = true, | |
814 | .encode_slave_id = false, | |
815 | .verify = NULL, | |
816 | .wrapper = mlx4_MODIFY_CQ_wrapper | |
817 | }, | |
818 | { | |
819 | .opcode = MLX4_CMD_SW2HW_SRQ, | |
820 | .has_inbox = true, | |
821 | .has_outbox = false, | |
822 | .out_is_imm = false, | |
823 | .encode_slave_id = true, | |
824 | .verify = NULL, | |
825 | .wrapper = mlx4_SW2HW_SRQ_wrapper | |
826 | }, | |
827 | { | |
828 | .opcode = MLX4_CMD_HW2SW_SRQ, | |
829 | .has_inbox = false, | |
830 | .has_outbox = false, | |
831 | .out_is_imm = false, | |
832 | .encode_slave_id = false, | |
833 | .verify = NULL, | |
834 | .wrapper = mlx4_HW2SW_SRQ_wrapper | |
835 | }, | |
836 | { | |
837 | .opcode = MLX4_CMD_QUERY_SRQ, | |
838 | .has_inbox = false, | |
839 | .has_outbox = true, | |
840 | .out_is_imm = false, | |
841 | .encode_slave_id = false, | |
842 | .verify = NULL, | |
843 | .wrapper = mlx4_QUERY_SRQ_wrapper | |
844 | }, | |
845 | { | |
846 | .opcode = MLX4_CMD_ARM_SRQ, | |
847 | .has_inbox = false, | |
848 | .has_outbox = false, | |
849 | .out_is_imm = false, | |
850 | .encode_slave_id = false, | |
851 | .verify = NULL, | |
852 | .wrapper = mlx4_ARM_SRQ_wrapper | |
853 | }, | |
854 | { | |
855 | .opcode = MLX4_CMD_RST2INIT_QP, | |
856 | .has_inbox = true, | |
857 | .has_outbox = false, | |
858 | .out_is_imm = false, | |
859 | .encode_slave_id = true, | |
860 | .verify = NULL, | |
861 | .wrapper = mlx4_RST2INIT_QP_wrapper | |
862 | }, | |
863 | { | |
864 | .opcode = MLX4_CMD_INIT2INIT_QP, | |
865 | .has_inbox = true, | |
866 | .has_outbox = false, | |
867 | .out_is_imm = false, | |
868 | .encode_slave_id = false, | |
869 | .verify = NULL, | |
870 | .wrapper = mlx4_GEN_QP_wrapper | |
871 | }, | |
872 | { | |
873 | .opcode = MLX4_CMD_INIT2RTR_QP, | |
874 | .has_inbox = true, | |
875 | .has_outbox = false, | |
876 | .out_is_imm = false, | |
877 | .encode_slave_id = false, | |
878 | .verify = NULL, | |
879 | .wrapper = mlx4_INIT2RTR_QP_wrapper | |
880 | }, | |
881 | { | |
882 | .opcode = MLX4_CMD_RTR2RTS_QP, | |
883 | .has_inbox = true, | |
884 | .has_outbox = false, | |
885 | .out_is_imm = false, | |
886 | .encode_slave_id = false, | |
887 | .verify = NULL, | |
888 | .wrapper = mlx4_GEN_QP_wrapper | |
889 | }, | |
890 | { | |
891 | .opcode = MLX4_CMD_RTS2RTS_QP, | |
892 | .has_inbox = true, | |
893 | .has_outbox = false, | |
894 | .out_is_imm = false, | |
895 | .encode_slave_id = false, | |
896 | .verify = NULL, | |
897 | .wrapper = mlx4_GEN_QP_wrapper | |
898 | }, | |
899 | { | |
900 | .opcode = MLX4_CMD_SQERR2RTS_QP, | |
901 | .has_inbox = true, | |
902 | .has_outbox = false, | |
903 | .out_is_imm = false, | |
904 | .encode_slave_id = false, | |
905 | .verify = NULL, | |
906 | .wrapper = mlx4_GEN_QP_wrapper | |
907 | }, | |
908 | { | |
909 | .opcode = MLX4_CMD_2ERR_QP, | |
910 | .has_inbox = false, | |
911 | .has_outbox = false, | |
912 | .out_is_imm = false, | |
913 | .encode_slave_id = false, | |
914 | .verify = NULL, | |
915 | .wrapper = mlx4_GEN_QP_wrapper | |
916 | }, | |
917 | { | |
918 | .opcode = MLX4_CMD_RTS2SQD_QP, | |
919 | .has_inbox = false, | |
920 | .has_outbox = false, | |
921 | .out_is_imm = false, | |
922 | .encode_slave_id = false, | |
923 | .verify = NULL, | |
924 | .wrapper = mlx4_GEN_QP_wrapper | |
925 | }, | |
926 | { | |
927 | .opcode = MLX4_CMD_SQD2SQD_QP, | |
928 | .has_inbox = true, | |
929 | .has_outbox = false, | |
930 | .out_is_imm = false, | |
931 | .encode_slave_id = false, | |
932 | .verify = NULL, | |
933 | .wrapper = mlx4_GEN_QP_wrapper | |
934 | }, | |
935 | { | |
936 | .opcode = MLX4_CMD_SQD2RTS_QP, | |
937 | .has_inbox = true, | |
938 | .has_outbox = false, | |
939 | .out_is_imm = false, | |
940 | .encode_slave_id = false, | |
941 | .verify = NULL, | |
942 | .wrapper = mlx4_GEN_QP_wrapper | |
943 | }, | |
944 | { | |
945 | .opcode = MLX4_CMD_2RST_QP, | |
946 | .has_inbox = false, | |
947 | .has_outbox = false, | |
948 | .out_is_imm = false, | |
949 | .encode_slave_id = false, | |
950 | .verify = NULL, | |
951 | .wrapper = mlx4_2RST_QP_wrapper | |
952 | }, | |
953 | { | |
954 | .opcode = MLX4_CMD_QUERY_QP, | |
955 | .has_inbox = false, | |
956 | .has_outbox = true, | |
957 | .out_is_imm = false, | |
958 | .encode_slave_id = false, | |
959 | .verify = NULL, | |
960 | .wrapper = mlx4_GEN_QP_wrapper | |
961 | }, | |
962 | { | |
963 | .opcode = MLX4_CMD_SUSPEND_QP, | |
964 | .has_inbox = false, | |
965 | .has_outbox = false, | |
966 | .out_is_imm = false, | |
967 | .encode_slave_id = false, | |
968 | .verify = NULL, | |
969 | .wrapper = mlx4_GEN_QP_wrapper | |
970 | }, | |
971 | { | |
972 | .opcode = MLX4_CMD_UNSUSPEND_QP, | |
973 | .has_inbox = false, | |
974 | .has_outbox = false, | |
975 | .out_is_imm = false, | |
976 | .encode_slave_id = false, | |
977 | .verify = NULL, | |
978 | .wrapper = mlx4_GEN_QP_wrapper | |
979 | }, | |
980 | { | |
981 | .opcode = MLX4_CMD_QUERY_IF_STAT, | |
982 | .has_inbox = false, | |
983 | .has_outbox = true, | |
984 | .out_is_imm = false, | |
985 | .encode_slave_id = false, | |
986 | .verify = NULL, | |
987 | .wrapper = mlx4_QUERY_IF_STAT_wrapper | |
988 | }, | |
989 | /* Native multicast commands are not available for guests */ | |
990 | { | |
991 | .opcode = MLX4_CMD_QP_ATTACH, | |
992 | .has_inbox = true, | |
993 | .has_outbox = false, | |
994 | .out_is_imm = false, | |
995 | .encode_slave_id = false, | |
996 | .verify = NULL, | |
997 | .wrapper = mlx4_QP_ATTACH_wrapper | |
998 | }, | |
999 | { | |
1000 | .opcode = MLX4_CMD_INFORM_FLR_DONE, | |
1001 | .has_inbox = false, | |
1002 | .has_outbox = false, | |
1003 | .out_is_imm = false, | |
1004 | .encode_slave_id = false, | |
1005 | .verify = NULL, | |
1006 | .wrapper = NULL | |
1007 | }, | |
e8f081aa YP |
1008 | }; |
1009 | ||
1010 | static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave, | |
1011 | struct mlx4_vhcr_cmd *in_vhcr) | |
1012 | { | |
1013 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1014 | struct mlx4_cmd_info *cmd = NULL; | |
1015 | struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr; | |
1016 | struct mlx4_vhcr *vhcr; | |
1017 | struct mlx4_cmd_mailbox *inbox = NULL; | |
1018 | struct mlx4_cmd_mailbox *outbox = NULL; | |
1019 | u64 in_param; | |
1020 | u64 out_param; | |
1021 | int ret = 0; | |
1022 | int i; | |
1023 | ||
1024 | /* Create sw representation of Virtual HCR */ | |
1025 | vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL); | |
1026 | if (!vhcr) | |
1027 | return -ENOMEM; | |
1028 | ||
1029 | /* DMA in the vHCR */ | |
1030 | if (!in_vhcr) { | |
1031 | ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, | |
1032 | priv->mfunc.master.slave_state[slave].vhcr_dma, | |
1033 | ALIGN(sizeof(struct mlx4_vhcr_cmd), | |
1034 | MLX4_ACCESS_MEM_ALIGN), 1); | |
1035 | if (ret) { | |
1036 | mlx4_err(dev, "%s:Failed reading vhcr" | |
1037 | "ret: 0x%x\n", __func__, ret); | |
1038 | kfree(vhcr); | |
1039 | return ret; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* Fill SW VHCR fields */ | |
1044 | vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param); | |
1045 | vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param); | |
1046 | vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier); | |
1047 | vhcr->token = be16_to_cpu(vhcr_cmd->token); | |
1048 | vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff; | |
1049 | vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12); | |
1050 | vhcr->e_bit = vhcr_cmd->flags & (1 << 6); | |
1051 | ||
1052 | /* Lookup command */ | |
1053 | for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) { | |
1054 | if (vhcr->op == cmd_info[i].opcode) { | |
1055 | cmd = &cmd_info[i]; | |
1056 | break; | |
1057 | } | |
1058 | } | |
1059 | if (!cmd) { | |
1060 | mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n", | |
1061 | vhcr->op, slave); | |
1062 | vhcr_cmd->status = -EINVAL; | |
1063 | goto out_status; | |
1064 | } | |
1065 | ||
1066 | /* Read inbox */ | |
1067 | if (cmd->has_inbox) { | |
1068 | vhcr->in_param &= INBOX_MASK; | |
1069 | inbox = mlx4_alloc_cmd_mailbox(dev); | |
1070 | if (IS_ERR(inbox)) { | |
1071 | ret = PTR_ERR(inbox); | |
1072 | inbox = NULL; | |
1073 | goto out; | |
1074 | } | |
1075 | ||
1076 | ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave, | |
1077 | vhcr->in_param, | |
1078 | MLX4_MAILBOX_SIZE, 1); | |
1079 | if (ret) { | |
1080 | mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n", | |
1081 | __func__, cmd->opcode); | |
1082 | goto out; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | /* Apply permission and bound checks if applicable */ | |
1087 | if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) { | |
1088 | mlx4_warn(dev, "Command:0x%x from slave: %d failed protection " | |
1089 | "checks for resource_id:%d\n", vhcr->op, slave, | |
1090 | vhcr->in_modifier); | |
1091 | vhcr_cmd->status = -EPERM; | |
1092 | goto out_status; | |
1093 | } | |
1094 | ||
1095 | /* Allocate outbox */ | |
1096 | if (cmd->has_outbox) { | |
1097 | outbox = mlx4_alloc_cmd_mailbox(dev); | |
1098 | if (IS_ERR(outbox)) { | |
1099 | ret = PTR_ERR(outbox); | |
1100 | outbox = NULL; | |
1101 | goto out; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | /* Execute the command! */ | |
1106 | if (cmd->wrapper) { | |
1107 | vhcr_cmd->status = cmd->wrapper(dev, slave, vhcr, inbox, outbox, | |
1108 | cmd); | |
1109 | if (cmd->out_is_imm) | |
1110 | vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); | |
1111 | } else { | |
1112 | in_param = cmd->has_inbox ? (u64) inbox->dma : | |
1113 | vhcr->in_param; | |
1114 | out_param = cmd->has_outbox ? (u64) outbox->dma : | |
1115 | vhcr->out_param; | |
1116 | vhcr_cmd->status = __mlx4_cmd(dev, in_param, &out_param, | |
1117 | cmd->out_is_imm, vhcr->in_modifier, | |
1118 | vhcr->op_modifier, vhcr->op, | |
1119 | MLX4_CMD_TIME_CLASS_A, | |
1120 | MLX4_CMD_NATIVE); | |
1121 | ||
1122 | if (vhcr_cmd->status) { | |
1123 | mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with" | |
1124 | " error:%d, status %d\n", | |
1125 | vhcr->op, slave, vhcr->errno, | |
1126 | vhcr_cmd->status); | |
1127 | ret = vhcr_cmd->status; | |
1128 | goto out; | |
1129 | } | |
1130 | ||
1131 | if (cmd->out_is_imm) { | |
1132 | vhcr->out_param = out_param; | |
1133 | vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | /* Write outbox if command completed successfully */ | |
1138 | if (cmd->has_outbox && !vhcr->errno) { | |
1139 | ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave, | |
1140 | vhcr->out_param, | |
1141 | MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED); | |
1142 | if (ret) { | |
1143 | mlx4_err(dev, "%s:Failed writing outbox\n", __func__); | |
1144 | goto out; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | out_status: | |
1149 | /* DMA back vhcr result */ | |
1150 | if (!in_vhcr) { | |
1151 | ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, | |
1152 | priv->mfunc.master.slave_state[slave].vhcr_dma, | |
1153 | ALIGN(sizeof(struct mlx4_vhcr), | |
1154 | MLX4_ACCESS_MEM_ALIGN), | |
1155 | MLX4_CMD_WRAPPED); | |
1156 | if (ret) | |
1157 | mlx4_err(dev, "%s:Failed writing vhcr result\n", | |
1158 | __func__); | |
1159 | else if (vhcr->e_bit && | |
1160 | mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe)) | |
1161 | mlx4_warn(dev, "Failed to generate command completion " | |
1162 | "eqe for slave %d\n", slave); | |
1163 | } | |
1164 | ||
1165 | out: | |
1166 | kfree(vhcr); | |
1167 | mlx4_free_cmd_mailbox(dev, inbox); | |
1168 | mlx4_free_cmd_mailbox(dev, outbox); | |
1169 | return ret; | |
1170 | } | |
1171 | ||
1172 | static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd, | |
1173 | u16 param, u8 toggle) | |
1174 | { | |
1175 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1176 | struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; | |
1177 | u32 reply; | |
1178 | u32 slave_status = 0; | |
1179 | u8 is_going_down = 0; | |
1180 | ||
1181 | slave_state[slave].comm_toggle ^= 1; | |
1182 | reply = (u32) slave_state[slave].comm_toggle << 31; | |
1183 | if (toggle != slave_state[slave].comm_toggle) { | |
1184 | mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER" | |
1185 | "STATE COMPROMISIED ***\n", toggle, slave); | |
1186 | goto reset_slave; | |
1187 | } | |
1188 | if (cmd == MLX4_COMM_CMD_RESET) { | |
1189 | mlx4_warn(dev, "Received reset from slave:%d\n", slave); | |
1190 | slave_state[slave].active = false; | |
1191 | /*check if we are in the middle of FLR process, | |
1192 | if so return "retry" status to the slave*/ | |
1193 | if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) { | |
1194 | slave_status = MLX4_DELAY_RESET_SLAVE; | |
1195 | goto inform_slave_state; | |
1196 | } | |
1197 | ||
1198 | /* write the version in the event field */ | |
1199 | reply |= mlx4_comm_get_version(); | |
1200 | ||
1201 | goto reset_slave; | |
1202 | } | |
1203 | /*command from slave in the middle of FLR*/ | |
1204 | if (cmd != MLX4_COMM_CMD_RESET && | |
1205 | MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) { | |
1206 | mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) " | |
1207 | "in the middle of FLR\n", slave, cmd); | |
1208 | return; | |
1209 | } | |
1210 | ||
1211 | switch (cmd) { | |
1212 | case MLX4_COMM_CMD_VHCR0: | |
1213 | if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET) | |
1214 | goto reset_slave; | |
1215 | slave_state[slave].vhcr_dma = ((u64) param) << 48; | |
1216 | priv->mfunc.master.slave_state[slave].cookie = 0; | |
1217 | mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]); | |
1218 | break; | |
1219 | case MLX4_COMM_CMD_VHCR1: | |
1220 | if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0) | |
1221 | goto reset_slave; | |
1222 | slave_state[slave].vhcr_dma |= ((u64) param) << 32; | |
1223 | break; | |
1224 | case MLX4_COMM_CMD_VHCR2: | |
1225 | if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1) | |
1226 | goto reset_slave; | |
1227 | slave_state[slave].vhcr_dma |= ((u64) param) << 16; | |
1228 | break; | |
1229 | case MLX4_COMM_CMD_VHCR_EN: | |
1230 | if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2) | |
1231 | goto reset_slave; | |
1232 | slave_state[slave].vhcr_dma |= param; | |
1233 | slave_state[slave].active = true; | |
1234 | break; | |
1235 | case MLX4_COMM_CMD_VHCR_POST: | |
1236 | if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) && | |
1237 | (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) | |
1238 | goto reset_slave; | |
1239 | down(&priv->cmd.slave_sem); | |
1240 | if (mlx4_master_process_vhcr(dev, slave, NULL)) { | |
1241 | mlx4_err(dev, "Failed processing vhcr for slave:%d," | |
1242 | " reseting slave.\n", slave); | |
1243 | up(&priv->cmd.slave_sem); | |
1244 | goto reset_slave; | |
1245 | } | |
1246 | up(&priv->cmd.slave_sem); | |
1247 | break; | |
1248 | default: | |
1249 | mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave); | |
1250 | goto reset_slave; | |
1251 | } | |
1252 | spin_lock(&priv->mfunc.master.slave_state_lock); | |
1253 | if (!slave_state[slave].is_slave_going_down) | |
1254 | slave_state[slave].last_cmd = cmd; | |
1255 | else | |
1256 | is_going_down = 1; | |
1257 | spin_unlock(&priv->mfunc.master.slave_state_lock); | |
1258 | if (is_going_down) { | |
1259 | mlx4_warn(dev, "Slave is going down aborting command(%d)" | |
1260 | " executing from slave:%d\n", | |
1261 | cmd, slave); | |
1262 | return; | |
1263 | } | |
1264 | __raw_writel((__force u32) cpu_to_be32(reply), | |
1265 | &priv->mfunc.comm[slave].slave_read); | |
1266 | mmiowb(); | |
1267 | ||
1268 | return; | |
1269 | ||
1270 | reset_slave: | |
c82e9aa0 EC |
1271 | /* cleanup any slave resources */ |
1272 | mlx4_delete_all_resources_for_slave(dev, slave); | |
e8f081aa YP |
1273 | spin_lock(&priv->mfunc.master.slave_state_lock); |
1274 | if (!slave_state[slave].is_slave_going_down) | |
1275 | slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET; | |
1276 | spin_unlock(&priv->mfunc.master.slave_state_lock); | |
1277 | /*with slave in the middle of flr, no need to clean resources again.*/ | |
1278 | inform_slave_state: | |
1279 | memset(&slave_state[slave].event_eq, 0, | |
1280 | sizeof(struct mlx4_slave_event_eq_info)); | |
1281 | __raw_writel((__force u32) cpu_to_be32(reply), | |
1282 | &priv->mfunc.comm[slave].slave_read); | |
1283 | wmb(); | |
1284 | } | |
1285 | ||
1286 | /* master command processing */ | |
1287 | void mlx4_master_comm_channel(struct work_struct *work) | |
1288 | { | |
1289 | struct mlx4_mfunc_master_ctx *master = | |
1290 | container_of(work, | |
1291 | struct mlx4_mfunc_master_ctx, | |
1292 | comm_work); | |
1293 | struct mlx4_mfunc *mfunc = | |
1294 | container_of(master, struct mlx4_mfunc, master); | |
1295 | struct mlx4_priv *priv = | |
1296 | container_of(mfunc, struct mlx4_priv, mfunc); | |
1297 | struct mlx4_dev *dev = &priv->dev; | |
1298 | __be32 *bit_vec; | |
1299 | u32 comm_cmd; | |
1300 | u32 vec; | |
1301 | int i, j, slave; | |
1302 | int toggle; | |
1303 | int served = 0; | |
1304 | int reported = 0; | |
1305 | u32 slt; | |
1306 | ||
1307 | bit_vec = master->comm_arm_bit_vector; | |
1308 | for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) { | |
1309 | vec = be32_to_cpu(bit_vec[i]); | |
1310 | for (j = 0; j < 32; j++) { | |
1311 | if (!(vec & (1 << j))) | |
1312 | continue; | |
1313 | ++reported; | |
1314 | slave = (i * 32) + j; | |
1315 | comm_cmd = swab32(readl( | |
1316 | &mfunc->comm[slave].slave_write)); | |
1317 | slt = swab32(readl(&mfunc->comm[slave].slave_read)) | |
1318 | >> 31; | |
1319 | toggle = comm_cmd >> 31; | |
1320 | if (toggle != slt) { | |
1321 | if (master->slave_state[slave].comm_toggle | |
1322 | != slt) { | |
1323 | printk(KERN_INFO "slave %d out of sync." | |
1324 | " read toggle %d, state toggle %d. " | |
1325 | "Resynching.\n", slave, slt, | |
1326 | master->slave_state[slave].comm_toggle); | |
1327 | master->slave_state[slave].comm_toggle = | |
1328 | slt; | |
1329 | } | |
1330 | mlx4_master_do_cmd(dev, slave, | |
1331 | comm_cmd >> 16 & 0xff, | |
1332 | comm_cmd & 0xffff, toggle); | |
1333 | ++served; | |
1334 | } | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | if (reported && reported != served) | |
1339 | mlx4_warn(dev, "Got command event with bitmask from %d slaves" | |
1340 | " but %d were served\n", | |
1341 | reported, served); | |
1342 | ||
1343 | if (mlx4_ARM_COMM_CHANNEL(dev)) | |
1344 | mlx4_warn(dev, "Failed to arm comm channel events\n"); | |
1345 | } | |
1346 | ||
225c7b1f RD |
1347 | int mlx4_cmd_init(struct mlx4_dev *dev) |
1348 | { | |
1349 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1350 | ||
1351 | mutex_init(&priv->cmd.hcr_mutex); | |
1352 | sema_init(&priv->cmd.poll_sem, 1); | |
1353 | priv->cmd.use_events = 0; | |
1354 | priv->cmd.toggle = 1; | |
1355 | ||
e8f081aa YP |
1356 | priv->cmd.hcr = NULL; |
1357 | priv->mfunc.vhcr = NULL; | |
1358 | ||
1359 | if (!mlx4_is_slave(dev)) { | |
1360 | priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) + | |
1361 | MLX4_HCR_BASE, MLX4_HCR_SIZE); | |
1362 | if (!priv->cmd.hcr) { | |
1363 | mlx4_err(dev, "Couldn't map command register.\n"); | |
1364 | return -ENOMEM; | |
1365 | } | |
225c7b1f RD |
1366 | } |
1367 | ||
1368 | priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev, | |
1369 | MLX4_MAILBOX_SIZE, | |
1370 | MLX4_MAILBOX_SIZE, 0); | |
e8f081aa YP |
1371 | if (!priv->cmd.pool) |
1372 | goto err_hcr; | |
225c7b1f RD |
1373 | |
1374 | return 0; | |
e8f081aa YP |
1375 | |
1376 | err_hcr: | |
1377 | if (!mlx4_is_slave(dev)) | |
1378 | iounmap(priv->cmd.hcr); | |
1379 | return -ENOMEM; | |
225c7b1f RD |
1380 | } |
1381 | ||
1382 | void mlx4_cmd_cleanup(struct mlx4_dev *dev) | |
1383 | { | |
1384 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1385 | ||
1386 | pci_pool_destroy(priv->cmd.pool); | |
e8f081aa YP |
1387 | |
1388 | if (!mlx4_is_slave(dev)) | |
1389 | iounmap(priv->cmd.hcr); | |
225c7b1f RD |
1390 | } |
1391 | ||
1392 | /* | |
1393 | * Switch to using events to issue FW commands (can only be called | |
1394 | * after event queue for command events has been initialized). | |
1395 | */ | |
1396 | int mlx4_cmd_use_events(struct mlx4_dev *dev) | |
1397 | { | |
1398 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1399 | int i; | |
e8f081aa | 1400 | int err = 0; |
225c7b1f RD |
1401 | |
1402 | priv->cmd.context = kmalloc(priv->cmd.max_cmds * | |
1403 | sizeof (struct mlx4_cmd_context), | |
1404 | GFP_KERNEL); | |
1405 | if (!priv->cmd.context) | |
1406 | return -ENOMEM; | |
1407 | ||
1408 | for (i = 0; i < priv->cmd.max_cmds; ++i) { | |
1409 | priv->cmd.context[i].token = i; | |
1410 | priv->cmd.context[i].next = i + 1; | |
1411 | } | |
1412 | ||
1413 | priv->cmd.context[priv->cmd.max_cmds - 1].next = -1; | |
1414 | priv->cmd.free_head = 0; | |
1415 | ||
1416 | sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds); | |
1417 | spin_lock_init(&priv->cmd.context_lock); | |
1418 | ||
1419 | for (priv->cmd.token_mask = 1; | |
1420 | priv->cmd.token_mask < priv->cmd.max_cmds; | |
1421 | priv->cmd.token_mask <<= 1) | |
1422 | ; /* nothing */ | |
1423 | --priv->cmd.token_mask; | |
1424 | ||
225c7b1f | 1425 | down(&priv->cmd.poll_sem); |
e8f081aa | 1426 | priv->cmd.use_events = 1; |
225c7b1f | 1427 | |
e8f081aa | 1428 | return err; |
225c7b1f RD |
1429 | } |
1430 | ||
1431 | /* | |
1432 | * Switch back to polling (used when shutting down the device) | |
1433 | */ | |
1434 | void mlx4_cmd_use_polling(struct mlx4_dev *dev) | |
1435 | { | |
1436 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1437 | int i; | |
1438 | ||
1439 | priv->cmd.use_events = 0; | |
1440 | ||
1441 | for (i = 0; i < priv->cmd.max_cmds; ++i) | |
1442 | down(&priv->cmd.event_sem); | |
1443 | ||
1444 | kfree(priv->cmd.context); | |
1445 | ||
1446 | up(&priv->cmd.poll_sem); | |
1447 | } | |
1448 | ||
1449 | struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev) | |
1450 | { | |
1451 | struct mlx4_cmd_mailbox *mailbox; | |
1452 | ||
1453 | mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL); | |
1454 | if (!mailbox) | |
1455 | return ERR_PTR(-ENOMEM); | |
1456 | ||
1457 | mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL, | |
1458 | &mailbox->dma); | |
1459 | if (!mailbox->buf) { | |
1460 | kfree(mailbox); | |
1461 | return ERR_PTR(-ENOMEM); | |
1462 | } | |
1463 | ||
1464 | return mailbox; | |
1465 | } | |
1466 | EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox); | |
1467 | ||
e8f081aa YP |
1468 | void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, |
1469 | struct mlx4_cmd_mailbox *mailbox) | |
225c7b1f RD |
1470 | { |
1471 | if (!mailbox) | |
1472 | return; | |
1473 | ||
1474 | pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma); | |
1475 | kfree(mailbox); | |
1476 | } | |
1477 | EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox); | |
e8f081aa YP |
1478 | |
1479 | u32 mlx4_comm_get_version(void) | |
1480 | { | |
1481 | return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER; | |
1482 | } |