[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / cq.c

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/hardirq.h>
#include <linux/export.h>

#include <linux/mlx4/cmd.h>
#include <linux/mlx4/cq.h>

#include "mlx4.h"
#include "icm.h"

#define MLX4_CQ_STATUS_OK		( 0 << 28)
#define MLX4_CQ_STATUS_OVERFLOW		( 9 << 28)
#define MLX4_CQ_STATUS_WRITE_FAIL	(10 << 28)
#define MLX4_CQ_FLAG_CC			( 1 << 18)
#define MLX4_CQ_FLAG_OI			( 1 << 17)
#define MLX4_CQ_STATE_ARMED		( 9 <<  8)
#define MLX4_CQ_STATE_ARMED_SOL		( 6 <<  8)
#define MLX4_EQ_STATE_FIRED		(10 <<  8)

#define TASKLET_MAX_TIME 2
#define TASKLET_MAX_TIME_JIFFIES msecs_to_jiffies(TASKLET_MAX_TIME)

void mlx4_cq_tasklet_cb(unsigned long data)
{
	unsigned long flags;
	unsigned long end = jiffies + TASKLET_MAX_TIME_JIFFIES;
	struct mlx4_eq_tasklet *ctx = (struct mlx4_eq_tasklet *)data;
	struct mlx4_cq *mcq, *temp;

	spin_lock_irqsave(&ctx->lock, flags);
	list_splice_tail_init(&ctx->list, &ctx->process_list);
	spin_unlock_irqrestore(&ctx->lock, flags);

	list_for_each_entry_safe(mcq, temp, &ctx->process_list, tasklet_ctx.list) {
		list_del_init(&mcq->tasklet_ctx.list);
		mcq->tasklet_ctx.comp(mcq);
		if (atomic_dec_and_test(&mcq->refcount))
			complete(&mcq->free);
		if (time_after(jiffies, end))
			break;
	}

	if (!list_empty(&ctx->process_list))
		tasklet_schedule(&ctx->task);
}

static void mlx4_add_cq_to_tasklet(struct mlx4_cq *cq)
{
	unsigned long flags;
	struct mlx4_eq_tasklet *tasklet_ctx = cq->tasklet_ctx.priv;

	spin_lock_irqsave(&tasklet_ctx->lock, flags);
	/* When migrating CQs between EQs will be implemented, please note
	 * that you need to sync this point. It is possible that
	 * while migrating a CQ, completions on the old EQs could
	 * still arrive.
	 */
	if (list_empty_careful(&cq->tasklet_ctx.list)) {
		atomic_inc(&cq->refcount);
		list_add_tail(&cq->tasklet_ctx.list, &tasklet_ctx->list);
	}
	spin_unlock_irqrestore(&tasklet_ctx->lock, flags);
}

void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
{
	struct mlx4_cq *cq;

	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
			       cqn & (dev->caps.num_cqs - 1));
	if (!cq) {
		mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
		return;
	}

	++cq->arm_sn;

	cq->comp(cq);
}

void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
{
	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	struct mlx4_cq *cq;

	spin_lock(&cq_table->lock);

	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
	if (cq)
		atomic_inc(&cq->refcount);

	spin_unlock(&cq_table->lock);

	if (!cq) {
		mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
		return;
	}

	cq->event(cq, event_type);

	if (atomic_dec_and_test(&cq->refcount))
		complete(&cq->free);
}

static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num)
{
	return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
			MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
			MLX4_CMD_WRAPPED);
}

static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num, u32 opmod)
{
	return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
			MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
}

static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num)
{
	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
			    cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
			    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
}

int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
		   u16 count, u16 period)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	cq_context = mailbox->buf;
	cq_context->cq_max_count = cpu_to_be16(count);
	cq_context->cq_period    = cpu_to_be16(period);

	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_modify);

int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
		   int entries, struct mlx4_mtt *mtt)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	u64 mtt_addr;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	cq_context = mailbox->buf;
	cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
	cq_context->log_page_size   = mtt->page_shift - 12;
	mtt_addr = mlx4_mtt_addr(dev, mtt);
	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);

	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_resize);

int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	int err;

	*cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
	if (*cqn == -1)
		return -ENOMEM;

	err = mlx4_table_get(dev, &cq_table->table, *cqn, GFP_KERNEL);
	if (err)
		goto err_out;

	err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn, GFP_KERNEL);
	if (err)
		goto err_put;
	return 0;

err_put:
	mlx4_table_put(dev, &cq_table->table, *cqn);

err_out:
	mlx4_bitmap_free(&cq_table->bitmap, *cqn, MLX4_NO_RR);
	return err;
}

static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
{
	u64 out_param;
	int err;

	if (mlx4_is_mfunc(dev)) {
		err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
				   RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
				   MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
		if (err)
			return err;
		else {
			*cqn = get_param_l(&out_param);
			return 0;
		}
	}
	return __mlx4_cq_alloc_icm(dev, cqn);
}

void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;

	mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
	mlx4_table_put(dev, &cq_table->table, cqn);
	mlx4_bitmap_free(&cq_table->bitmap, cqn, MLX4_NO_RR);
}

static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
{
	u64 in_param = 0;
	int err;

	if (mlx4_is_mfunc(dev)) {
		set_param_l(&in_param, cqn);
		err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
			       MLX4_CMD_FREE_RES,
			       MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
		if (err)
			mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
	} else
		__mlx4_cq_free_icm(dev, cqn);
}

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
		  struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec,
		  struct mlx4_cq *cq, unsigned vector, int collapsed,
		  int timestamp_en)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	u64 mtt_addr;
	int err;

	if (vector > dev->caps.num_comp_vectors + dev->caps.comp_pool)
		return -EINVAL;

	cq->vector = vector;

	err = mlx4_cq_alloc_icm(dev, &cq->cqn);
	if (err)
		return err;

	spin_lock_irq(&cq_table->lock);
	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
	spin_unlock_irq(&cq_table->lock);
	if (err)
		goto err_icm;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox)) {
		err = PTR_ERR(mailbox);
		goto err_radix;
	}

	cq_context = mailbox->buf;
	cq_context->flags	    = cpu_to_be32(!!collapsed << 18);
	if (timestamp_en)
		cq_context->flags  |= cpu_to_be32(1 << 19);

	cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
	cq_context->comp_eqn	    = priv->eq_table.eq[vector].eqn;
	cq_context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;

	mtt_addr = mlx4_mtt_addr(dev, mtt);
	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	cq_context->db_rec_addr     = cpu_to_be64(db_rec);

	err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
	mlx4_free_cmd_mailbox(dev, mailbox);
	if (err)
		goto err_radix;

	cq->cons_index = 0;
	cq->arm_sn     = 1;
	cq->uar        = uar;
	atomic_set(&cq->refcount, 1);
	init_completion(&cq->free);
	cq->comp = mlx4_add_cq_to_tasklet;
	cq->tasklet_ctx.priv =
		&priv->eq_table.eq[cq->vector].tasklet_ctx;
	INIT_LIST_HEAD(&cq->tasklet_ctx.list);


	cq->irq = priv->eq_table.eq[cq->vector].irq;
	return 0;

err_radix:
	spin_lock_irq(&cq_table->lock);
	radix_tree_delete(&cq_table->tree, cq->cqn);
	spin_unlock_irq(&cq_table->lock);

err_icm:
	mlx4_cq_free_icm(dev, cq->cqn);

	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_alloc);

void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	int err;

	err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
	if (err)
		mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);

	synchronize_irq(priv->eq_table.eq[cq->vector].irq);

	spin_lock_irq(&cq_table->lock);
	radix_tree_delete(&cq_table->tree, cq->cqn);
	spin_unlock_irq(&cq_table->lock);

	if (atomic_dec_and_test(&cq->refcount))
		complete(&cq->free);
	wait_for_completion(&cq->free);

	mlx4_cq_free_icm(dev, cq->cqn);
}
EXPORT_SYMBOL_GPL(mlx4_cq_free);

int mlx4_init_cq_table(struct mlx4_dev *dev)
{
	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	int err;

	spin_lock_init(&cq_table->lock);
	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
	if (mlx4_is_slave(dev))
		return 0;

	err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
			       dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
	if (err)
		return err;

	return 0;
}

void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
{
	if (mlx4_is_slave(dev))
		return;
	/* Nothing to do to clean up radix_tree */
	mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
}
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
	4	* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0	5	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*/
	36
225c7b1f	37	#include <linux/hardirq.h>
ee40fa06	38	#include <linux/export.h>
225c7b1f RD	39
225c7b1f RD	40	#include <linux/mlx4/cmd.h>
3fdcb97f	41	#include <linux/mlx4/cq.h>
225c7b1f RD	42
	43	#include "mlx4.h"
	44	#include "icm.h"
	45
225c7b1f RD	46	#define MLX4_CQ_STATUS_OK ( 0 << 28)
	47	#define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
	48	#define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
	49	#define MLX4_CQ_FLAG_CC ( 1 << 18)
	50	#define MLX4_CQ_FLAG_OI ( 1 << 17)
	51	#define MLX4_CQ_STATE_ARMED ( 9 << 8)
	52	#define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
	53	#define MLX4_EQ_STATE_FIRED (10 << 8)
	54
3dca0f42 MB	55	#define TASKLET_MAX_TIME 2
	56	#define TASKLET_MAX_TIME_JIFFIES msecs_to_jiffies(TASKLET_MAX_TIME)
	57
	58	void mlx4_cq_tasklet_cb(unsigned long data)
	59	{
	60	unsigned long flags;
	61	unsigned long end = jiffies + TASKLET_MAX_TIME_JIFFIES;
	62	struct mlx4_eq_tasklet ctx = (struct mlx4_eq_tasklet )data;
	63	struct mlx4_cq mcq, temp;
	64
	65	spin_lock_irqsave(&ctx->lock, flags);
	66	list_splice_tail_init(&ctx->list, &ctx->process_list);
	67	spin_unlock_irqrestore(&ctx->lock, flags);
	68
	69	list_for_each_entry_safe(mcq, temp, &ctx->process_list, tasklet_ctx.list) {
	70	list_del_init(&mcq->tasklet_ctx.list);
	71	mcq->tasklet_ctx.comp(mcq);
	72	if (atomic_dec_and_test(&mcq->refcount))
	73	complete(&mcq->free);
	74	if (time_after(jiffies, end))
	75	break;
	76	}
	77
	78	if (!list_empty(&ctx->process_list))
	79	tasklet_schedule(&ctx->task);
	80	}
	81
	82	static void mlx4_add_cq_to_tasklet(struct mlx4_cq *cq)
	83	{
	84	unsigned long flags;
	85	struct mlx4_eq_tasklet *tasklet_ctx = cq->tasklet_ctx.priv;
	86
	87	spin_lock_irqsave(&tasklet_ctx->lock, flags);
	88	/* When migrating CQs between EQs will be implemented, please note
	89	* that you need to sync this point. It is possible that
	90	* while migrating a CQ, completions on the old EQs could
	91	* still arrive.
	92	*/
	93	if (list_empty_careful(&cq->tasklet_ctx.list)) {
	94	atomic_inc(&cq->refcount);
	95	list_add_tail(&cq->tasklet_ctx.list, &tasklet_ctx->list);
	96	}
	97	spin_unlock_irqrestore(&tasklet_ctx->lock, flags);
	98	}
	99
225c7b1f RD	100	void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
	101	{
	102	struct mlx4_cq *cq;
	103
	104	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
	105	cqn & (dev->caps.num_cqs - 1));
	106	if (!cq) {
d7233386	107	mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
225c7b1f RD	108	return;
	109	}
	110
	111	++cq->arm_sn;
	112
	113	cq->comp(cq);
	114	}
	115
	116	void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
	117	{
	118	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	119	struct mlx4_cq *cq;
	120
	121	spin_lock(&cq_table->lock);
	122
	123	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
	124	if (cq)
	125	atomic_inc(&cq->refcount);
	126
	127	spin_unlock(&cq_table->lock);
	128
	129	if (!cq) {
	130	mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
	131	return;
	132	}
	133
	134	cq->event(cq, event_type);
	135
	136	if (atomic_dec_and_test(&cq->refcount))
	137	complete(&cq->free);
	138	}
	139
	140	static int mlx4_SW2HW_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	141	int cq_num)
	142	{
eb41049f	143	return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
d7233386 JM	144	MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
d7233386 JM	145	MLX4_CMD_WRAPPED);
225c7b1f RD	146	}
225c7b1f RD	147
3fdcb97f EC	148	static int mlx4_MODIFY_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	149	int cq_num, u32 opmod)
	150	{
	151	return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
f9baff50	152	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
3fdcb97f EC	153	}
3fdcb97f EC	154
225c7b1f RD	155	static int mlx4_HW2SW_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	156	int cq_num)
	157	{
eb41049f	158	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
d7233386	159	cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
f9baff50	160	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f RD	161	}
225c7b1f RD	162
3fdcb97f EC	163	int mlx4_cq_modify(struct mlx4_dev dev, struct mlx4_cq cq,
	164	u16 count, u16 period)
	165	{
	166	struct mlx4_cmd_mailbox *mailbox;
	167	struct mlx4_cq_context *cq_context;
	168	int err;
	169
	170	mailbox = mlx4_alloc_cmd_mailbox(dev);
	171	if (IS_ERR(mailbox))
	172	return PTR_ERR(mailbox);
	173
	174	cq_context = mailbox->buf;
3fdcb97f EC	175	cq_context->cq_max_count = cpu_to_be16(count);
	176	cq_context->cq_period = cpu_to_be16(period);
	177
	178	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
	179
	180	mlx4_free_cmd_mailbox(dev, mailbox);
	181	return err;
	182	}
	183	EXPORT_SYMBOL_GPL(mlx4_cq_modify);
	184
bbf8eed1 VS	185	int mlx4_cq_resize(struct mlx4_dev dev, struct mlx4_cq cq,
	186	int entries, struct mlx4_mtt *mtt)
	187	{
	188	struct mlx4_cmd_mailbox *mailbox;
	189	struct mlx4_cq_context *cq_context;
	190	u64 mtt_addr;
	191	int err;
	192
	193	mailbox = mlx4_alloc_cmd_mailbox(dev);
	194	if (IS_ERR(mailbox))
	195	return PTR_ERR(mailbox);
	196
	197	cq_context = mailbox->buf;
bbf8eed1 VS	198	cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
	199	cq_context->log_page_size = mtt->page_shift - 12;
	200	mtt_addr = mlx4_mtt_addr(dev, mtt);
	201	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	202	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	203
f5b3a096	204	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
bbf8eed1 VS	205
	206	mlx4_free_cmd_mailbox(dev, mailbox);
	207	return err;
	208	}
	209	EXPORT_SYMBOL_GPL(mlx4_cq_resize);
	210
c82e9aa0	211	int __mlx4_cq_alloc_icm(struct mlx4_dev dev, int cqn)
d7233386 JM	212	{
	213	struct mlx4_priv *priv = mlx4_priv(dev);
	214	struct mlx4_cq_table *cq_table = &priv->cq_table;
	215	int err;
	216
	217	*cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
	218	if (*cqn == -1)
	219	return -ENOMEM;
	220
40f2287b	221	err = mlx4_table_get(dev, &cq_table->table, *cqn, GFP_KERNEL);
d7233386 JM	222	if (err)
	223	goto err_out;
	224
40f2287b	225	err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn, GFP_KERNEL);
d7233386 JM	226	if (err)
	227	goto err_put;
	228	return 0;
	229
	230	err_put:
	231	mlx4_table_put(dev, &cq_table->table, *cqn);
	232
	233	err_out:
7c6d74d2	234	mlx4_bitmap_free(&cq_table->bitmap, *cqn, MLX4_NO_RR);
d7233386 JM	235	return err;
	236	}
	237
	238	static int mlx4_cq_alloc_icm(struct mlx4_dev dev, int cqn)
	239	{
	240	u64 out_param;
	241	int err;
	242
	243	if (mlx4_is_mfunc(dev)) {
	244	err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
	245	RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
	246	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
	247	if (err)
	248	return err;
	249	else {
	250	*cqn = get_param_l(&out_param);
	251	return 0;
	252	}
	253	}
	254	return __mlx4_cq_alloc_icm(dev, cqn);
	255	}
	256
c82e9aa0	257	void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
d7233386 JM	258	{
	259	struct mlx4_priv *priv = mlx4_priv(dev);
	260	struct mlx4_cq_table *cq_table = &priv->cq_table;
	261
	262	mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
	263	mlx4_table_put(dev, &cq_table->table, cqn);
7c6d74d2	264	mlx4_bitmap_free(&cq_table->bitmap, cqn, MLX4_NO_RR);
d7233386 JM	265	}
	266
	267	static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
	268	{
e7dbeba8	269	u64 in_param = 0;
d7233386 JM	270	int err;
	271
	272	if (mlx4_is_mfunc(dev)) {
	273	set_param_l(&in_param, cqn);
	274	err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
	275	MLX4_CMD_FREE_RES,
	276	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
	277	if (err)
	278	mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
	279	} else
	280	__mlx4_cq_free_icm(dev, cqn);
	281	}
	282
ec693d47 AV	283	int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
	284	struct mlx4_mtt mtt, struct mlx4_uar uar, u64 db_rec,
	285	struct mlx4_cq *cq, unsigned vector, int collapsed,
	286	int timestamp_en)
225c7b1f RD	287	{
	288	struct mlx4_priv *priv = mlx4_priv(dev);
	289	struct mlx4_cq_table *cq_table = &priv->cq_table;
	290	struct mlx4_cmd_mailbox *mailbox;
	291	struct mlx4_cq_context *cq_context;
	292	u64 mtt_addr;
	293	int err;
	294
0b7ca5a9	295	if (vector > dev->caps.num_comp_vectors + dev->caps.comp_pool)
b8dd786f YP	296	return -EINVAL;
	297
	298	cq->vector = vector;
	299
d7233386	300	err = mlx4_cq_alloc_icm(dev, &cq->cqn);
225c7b1f	301	if (err)
d7233386	302	return err;
225c7b1f RD	303
	304	spin_lock_irq(&cq_table->lock);
	305	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
	306	spin_unlock_irq(&cq_table->lock);
	307	if (err)
d7233386	308	goto err_icm;
225c7b1f RD	309
	310	mailbox = mlx4_alloc_cmd_mailbox(dev);
	311	if (IS_ERR(mailbox)) {
	312	err = PTR_ERR(mailbox);
	313	goto err_radix;
	314	}
	315
	316	cq_context = mailbox->buf;
e463c7b1	317	cq_context->flags = cpu_to_be32(!!collapsed << 18);
ec693d47 AV	318	if (timestamp_en)
	319	cq_context->flags \|= cpu_to_be32(1 << 19);
	320
225c7b1f	321	cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) \| uar->index);
b8dd786f	322	cq_context->comp_eqn = priv->eq_table.eq[vector].eqn;
225c7b1f RD	323	cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
	324
	325	mtt_addr = mlx4_mtt_addr(dev, mtt);
	326	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	327	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	328	cq_context->db_rec_addr = cpu_to_be64(db_rec);
	329
	330	err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
	331	mlx4_free_cmd_mailbox(dev, mailbox);
	332	if (err)
	333	goto err_radix;
	334
	335	cq->cons_index = 0;
	336	cq->arm_sn = 1;
	337	cq->uar = uar;
	338	atomic_set(&cq->refcount, 1);
	339	init_completion(&cq->free);
3dca0f42 MB	340	cq->comp = mlx4_add_cq_to_tasklet;
	341	cq->tasklet_ctx.priv =
	342	&priv->eq_table.eq[cq->vector].tasklet_ctx;
	343	INIT_LIST_HEAD(&cq->tasklet_ctx.list);
	344
225c7b1f	345
2eacc23c	346	cq->irq = priv->eq_table.eq[cq->vector].irq;
225c7b1f RD	347	return 0;
	348
	349	err_radix:
	350	spin_lock_irq(&cq_table->lock);
	351	radix_tree_delete(&cq_table->tree, cq->cqn);
	352	spin_unlock_irq(&cq_table->lock);
	353
d7233386 JM	354	err_icm:
d7233386 JM	355	mlx4_cq_free_icm(dev, cq->cqn);
225c7b1f RD	356
	357	return err;
	358	}
	359	EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
	360
	361	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq)
	362	{
	363	struct mlx4_priv *priv = mlx4_priv(dev);
	364	struct mlx4_cq_table *cq_table = &priv->cq_table;
	365	int err;
	366
	367	err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
	368	if (err)
	369	mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
	370
b8dd786f	371	synchronize_irq(priv->eq_table.eq[cq->vector].irq);
225c7b1f RD	372
	373	spin_lock_irq(&cq_table->lock);
	374	radix_tree_delete(&cq_table->tree, cq->cqn);
	375	spin_unlock_irq(&cq_table->lock);
	376
	377	if (atomic_dec_and_test(&cq->refcount))
	378	complete(&cq->free);
	379	wait_for_completion(&cq->free);
	380
d7233386	381	mlx4_cq_free_icm(dev, cq->cqn);
225c7b1f RD	382	}
	383	EXPORT_SYMBOL_GPL(mlx4_cq_free);
	384
3d73c288	385	int mlx4_init_cq_table(struct mlx4_dev *dev)
225c7b1f RD	386	{
	387	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	388	int err;
	389
	390	spin_lock_init(&cq_table->lock);
	391	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
d7233386 JM	392	if (mlx4_is_slave(dev))
d7233386 JM	393	return 0;
225c7b1f RD	394
225c7b1f RD	395	err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
93fc9e1b	396	dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
225c7b1f RD	397	if (err)
	398	return err;
	399
	400	return 0;
	401	}
	402
	403	void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
	404	{
d7233386 JM	405	if (mlx4_is_slave(dev))
d7233386 JM	406	return;
225c7b1f RD	407	/* Nothing to do to clean up radix_tree */
	408	mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
	409	}