[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / cq.c

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/hardirq.h>
#include <linux/export.h>

#include <linux/mlx4/cmd.h>
#include <linux/mlx4/cq.h>

#include "mlx4.h"
#include "icm.h"

#define MLX4_CQ_STATUS_OK		( 0 << 28)
#define MLX4_CQ_STATUS_OVERFLOW		( 9 << 28)
#define MLX4_CQ_STATUS_WRITE_FAIL	(10 << 28)
#define MLX4_CQ_FLAG_CC			( 1 << 18)
#define MLX4_CQ_FLAG_OI			( 1 << 17)
#define MLX4_CQ_STATE_ARMED		( 9 <<  8)
#define MLX4_CQ_STATE_ARMED_SOL		( 6 <<  8)
#define MLX4_EQ_STATE_FIRED		(10 <<  8)

#define TASKLET_MAX_TIME 2
#define TASKLET_MAX_TIME_JIFFIES msecs_to_jiffies(TASKLET_MAX_TIME)

void mlx4_cq_tasklet_cb(unsigned long data)
{
	unsigned long flags;
	unsigned long end = jiffies + TASKLET_MAX_TIME_JIFFIES;
	struct mlx4_eq_tasklet *ctx = (struct mlx4_eq_tasklet *)data;
	struct mlx4_cq *mcq, *temp;

	spin_lock_irqsave(&ctx->lock, flags);
	list_splice_tail_init(&ctx->list, &ctx->process_list);
	spin_unlock_irqrestore(&ctx->lock, flags);

	list_for_each_entry_safe(mcq, temp, &ctx->process_list, tasklet_ctx.list) {
		list_del_init(&mcq->tasklet_ctx.list);
		mcq->tasklet_ctx.comp(mcq);
		if (atomic_dec_and_test(&mcq->refcount))
			complete(&mcq->free);
		if (time_after(jiffies, end))
			break;
	}

	if (!list_empty(&ctx->process_list))
		tasklet_schedule(&ctx->task);
}

static void mlx4_add_cq_to_tasklet(struct mlx4_cq *cq)
{
	struct mlx4_eq_tasklet *tasklet_ctx = cq->tasklet_ctx.priv;
	unsigned long flags;
	bool kick;

	spin_lock_irqsave(&tasklet_ctx->lock, flags);
	/* When migrating CQs between EQs will be implemented, please note
	 * that you need to sync this point. It is possible that
	 * while migrating a CQ, completions on the old EQs could
	 * still arrive.
	 */
	if (list_empty_careful(&cq->tasklet_ctx.list)) {
		atomic_inc(&cq->refcount);
		kick = list_empty(&tasklet_ctx->list);
		list_add_tail(&cq->tasklet_ctx.list, &tasklet_ctx->list);
		if (kick)
			tasklet_schedule(&tasklet_ctx->task);
	}
	spin_unlock_irqrestore(&tasklet_ctx->lock, flags);
}

void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
{
	struct mlx4_cq *cq;

	rcu_read_lock();
	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
			       cqn & (dev->caps.num_cqs - 1));
	rcu_read_unlock();

	if (!cq) {
		mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
		return;
	}

	/* Acessing the CQ outside of rcu_read_lock is safe, because
	 * the CQ is freed only after interrupt handling is completed.
	 */
	++cq->arm_sn;

	cq->comp(cq);
}

void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
{
	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	struct mlx4_cq *cq;

	rcu_read_lock();
	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
	rcu_read_unlock();

	if (!cq) {
		mlx4_dbg(dev, "Async event for bogus CQ %08x\n", cqn);
		return;
	}

	/* Acessing the CQ outside of rcu_read_lock is safe, because
	 * the CQ is freed only after interrupt handling is completed.
	 */
	cq->event(cq, event_type);
}

static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num)
{
	return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
			MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
			MLX4_CMD_WRAPPED);
}

static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num, u32 opmod)
{
	return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
			MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
}

static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int cq_num)
{
	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
			    cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
			    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
}

int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
		   u16 count, u16 period)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	cq_context = mailbox->buf;
	cq_context->cq_max_count = cpu_to_be16(count);
	cq_context->cq_period    = cpu_to_be16(period);

	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_modify);

int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
		   int entries, struct mlx4_mtt *mtt)
{
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	u64 mtt_addr;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);

	cq_context = mailbox->buf;
	cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
	cq_context->log_page_size   = mtt->page_shift - 12;
	mtt_addr = mlx4_mtt_addr(dev, mtt);
	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);

	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);

	mlx4_free_cmd_mailbox(dev, mailbox);
	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_resize);

int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	int err;

	*cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
	if (*cqn == -1)
		return -ENOMEM;

	err = mlx4_table_get(dev, &cq_table->table, *cqn);
	if (err)
		goto err_out;

	err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn);
	if (err)
		goto err_put;
	return 0;

err_put:
	mlx4_table_put(dev, &cq_table->table, *cqn);

err_out:
	mlx4_bitmap_free(&cq_table->bitmap, *cqn, MLX4_NO_RR);
	return err;
}

static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
{
	u64 out_param;
	int err;

	if (mlx4_is_mfunc(dev)) {
		err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
				   RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
				   MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
		if (err)
			return err;
		else {
			*cqn = get_param_l(&out_param);
			return 0;
		}
	}
	return __mlx4_cq_alloc_icm(dev, cqn);
}

void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;

	mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
	mlx4_table_put(dev, &cq_table->table, cqn);
	mlx4_bitmap_free(&cq_table->bitmap, cqn, MLX4_NO_RR);
}

static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
{
	u64 in_param = 0;
	int err;

	if (mlx4_is_mfunc(dev)) {
		set_param_l(&in_param, cqn);
		err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
			       MLX4_CMD_FREE_RES,
			       MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
		if (err)
			mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
	} else
		__mlx4_cq_free_icm(dev, cqn);
}

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
		  struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec,
		  struct mlx4_cq *cq, unsigned vector, int collapsed,
		  int timestamp_en)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_cq_context *cq_context;
	u64 mtt_addr;
	int err;

	if (vector >= dev->caps.num_comp_vectors)
		return -EINVAL;

	cq->vector = vector;

	err = mlx4_cq_alloc_icm(dev, &cq->cqn);
	if (err)
		return err;

	spin_lock(&cq_table->lock);
	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
	spin_unlock(&cq_table->lock);
	if (err)
		goto err_icm;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox)) {
		err = PTR_ERR(mailbox);
		goto err_radix;
	}

	cq_context = mailbox->buf;
	cq_context->flags	    = cpu_to_be32(!!collapsed << 18);
	if (timestamp_en)
		cq_context->flags  |= cpu_to_be32(1 << 19);

	cq_context->logsize_usrpage =
		cpu_to_be32((ilog2(nent) << 24) |
			    mlx4_to_hw_uar_index(dev, uar->index));
	cq_context->comp_eqn	    = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn;
	cq_context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;

	mtt_addr = mlx4_mtt_addr(dev, mtt);
	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	cq_context->db_rec_addr     = cpu_to_be64(db_rec);

	err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
	mlx4_free_cmd_mailbox(dev, mailbox);
	if (err)
		goto err_radix;

	cq->cons_index = 0;
	cq->arm_sn     = 1;
	cq->uar        = uar;
	atomic_set(&cq->refcount, 1);
	init_completion(&cq->free);
	cq->comp = mlx4_add_cq_to_tasklet;
	cq->tasklet_ctx.priv =
		&priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].tasklet_ctx;
	INIT_LIST_HEAD(&cq->tasklet_ctx.list);


	cq->irq = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].irq;
	return 0;

err_radix:
	spin_lock(&cq_table->lock);
	radix_tree_delete(&cq_table->tree, cq->cqn);
	spin_unlock(&cq_table->lock);

err_icm:
	mlx4_cq_free_icm(dev, cq->cqn);

	return err;
}
EXPORT_SYMBOL_GPL(mlx4_cq_alloc);

void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cq_table *cq_table = &priv->cq_table;
	int err;

	err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
	if (err)
		mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);

	spin_lock(&cq_table->lock);
	radix_tree_delete(&cq_table->tree, cq->cqn);
	spin_unlock(&cq_table->lock);

	synchronize_irq(priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq);
	if (priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq !=
	    priv->eq_table.eq[MLX4_EQ_ASYNC].irq)
		synchronize_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq);

	if (atomic_dec_and_test(&cq->refcount))
		complete(&cq->free);
	wait_for_completion(&cq->free);

	mlx4_cq_free_icm(dev, cq->cqn);
}
EXPORT_SYMBOL_GPL(mlx4_cq_free);

int mlx4_init_cq_table(struct mlx4_dev *dev)
{
	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	int err;

	spin_lock_init(&cq_table->lock);
	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
	if (mlx4_is_slave(dev))
		return 0;

	err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
			       dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
	if (err)
		return err;

	return 0;
}

void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
{
	if (mlx4_is_slave(dev))
		return;
	/* Nothing to do to clean up radix_tree */
	mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
}
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
	3	* Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
	4	* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0	5	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	6	* Copyright (c) 2004 Voltaire, Inc. All rights reserved.
	7	*
	8	* This software is available to you under a choice of one of two
	9	* licenses. You may choose to be licensed under the terms of the GNU
	10	* General Public License (GPL) Version 2, available from the file
	11	* COPYING in the main directory of this source tree, or the
	12	* OpenIB.org BSD license below:
	13	*
	14	* Redistribution and use in source and binary forms, with or
	15	* without modification, are permitted provided that the following
	16	* conditions are met:
	17	*
	18	* - Redistributions of source code must retain the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer.
	21	*
	22	* - Redistributions in binary form must reproduce the above
	23	* copyright notice, this list of conditions and the following
	24	* disclaimer in the documentation and/or other materials
	25	* provided with the distribution.
	26	*
	27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	28	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	29	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	30	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	31	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	32	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	33	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	34	* SOFTWARE.
	35	*/
	36
225c7b1f	37	#include <linux/hardirq.h>
ee40fa06	38	#include <linux/export.h>
225c7b1f RD	39
225c7b1f RD	40	#include <linux/mlx4/cmd.h>
3fdcb97f	41	#include <linux/mlx4/cq.h>
225c7b1f RD	42
	43	#include "mlx4.h"
	44	#include "icm.h"
	45
225c7b1f RD	46	#define MLX4_CQ_STATUS_OK ( 0 << 28)
	47	#define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
	48	#define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
	49	#define MLX4_CQ_FLAG_CC ( 1 << 18)
	50	#define MLX4_CQ_FLAG_OI ( 1 << 17)
	51	#define MLX4_CQ_STATE_ARMED ( 9 << 8)
	52	#define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
	53	#define MLX4_EQ_STATE_FIRED (10 << 8)
	54
3dca0f42 MB	55	#define TASKLET_MAX_TIME 2
	56	#define TASKLET_MAX_TIME_JIFFIES msecs_to_jiffies(TASKLET_MAX_TIME)
	57
	58	void mlx4_cq_tasklet_cb(unsigned long data)
	59	{
	60	unsigned long flags;
	61	unsigned long end = jiffies + TASKLET_MAX_TIME_JIFFIES;
	62	struct mlx4_eq_tasklet ctx = (struct mlx4_eq_tasklet )data;
	63	struct mlx4_cq mcq, temp;
	64
	65	spin_lock_irqsave(&ctx->lock, flags);
	66	list_splice_tail_init(&ctx->list, &ctx->process_list);
	67	spin_unlock_irqrestore(&ctx->lock, flags);
	68
	69	list_for_each_entry_safe(mcq, temp, &ctx->process_list, tasklet_ctx.list) {
	70	list_del_init(&mcq->tasklet_ctx.list);
	71	mcq->tasklet_ctx.comp(mcq);
	72	if (atomic_dec_and_test(&mcq->refcount))
	73	complete(&mcq->free);
	74	if (time_after(jiffies, end))
	75	break;
	76	}
	77
	78	if (!list_empty(&ctx->process_list))
	79	tasklet_schedule(&ctx->task);
	80	}
	81
	82	static void mlx4_add_cq_to_tasklet(struct mlx4_cq *cq)
	83	{
3dca0f42	84	struct mlx4_eq_tasklet *tasklet_ctx = cq->tasklet_ctx.priv;
01f0f425 ED	85	unsigned long flags;
01f0f425 ED	86	bool kick;
3dca0f42 MB	87
	88	spin_lock_irqsave(&tasklet_ctx->lock, flags);
	89	/* When migrating CQs between EQs will be implemented, please note
	90	* that you need to sync this point. It is possible that
	91	* while migrating a CQ, completions on the old EQs could
	92	* still arrive.
	93	*/
	94	if (list_empty_careful(&cq->tasklet_ctx.list)) {
	95	atomic_inc(&cq->refcount);
01f0f425	96	kick = list_empty(&tasklet_ctx->list);
3dca0f42	97	list_add_tail(&cq->tasklet_ctx.list, &tasklet_ctx->list);
01f0f425 ED	98	if (kick)
01f0f425 ED	99	tasklet_schedule(&tasklet_ctx->task);
3dca0f42 MB	100	}
	101	spin_unlock_irqrestore(&tasklet_ctx->lock, flags);
	102	}
	103
225c7b1f RD	104	void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
	105	{
	106	struct mlx4_cq *cq;
	107
291c566a	108	rcu_read_lock();
225c7b1f RD	109	cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
225c7b1f RD	110	cqn & (dev->caps.num_cqs - 1));
291c566a JM	111	rcu_read_unlock();
291c566a JM	112
225c7b1f	113	if (!cq) {
d7233386	114	mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
225c7b1f RD	115	return;
	116	}
	117
291c566a JM	118	/* Acessing the CQ outside of rcu_read_lock is safe, because
	119	* the CQ is freed only after interrupt handling is completed.
	120	*/
225c7b1f RD	121	++cq->arm_sn;
	122
	123	cq->comp(cq);
	124	}
	125
	126	void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
	127	{
	128	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	129	struct mlx4_cq *cq;
	130
291c566a	131	rcu_read_lock();
225c7b1f	132	cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
291c566a	133	rcu_read_unlock();
225c7b1f RD	134
225c7b1f RD	135	if (!cq) {
291c566a	136	mlx4_dbg(dev, "Async event for bogus CQ %08x\n", cqn);
225c7b1f RD	137	return;
	138	}
	139
291c566a JM	140	/* Acessing the CQ outside of rcu_read_lock is safe, because
	141	* the CQ is freed only after interrupt handling is completed.
	142	*/
225c7b1f	143	cq->event(cq, event_type);
225c7b1f RD	144	}
	145
	146	static int mlx4_SW2HW_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	147	int cq_num)
	148	{
eb41049f	149	return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
d7233386 JM	150	MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
d7233386 JM	151	MLX4_CMD_WRAPPED);
225c7b1f RD	152	}
225c7b1f RD	153
3fdcb97f EC	154	static int mlx4_MODIFY_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	155	int cq_num, u32 opmod)
	156	{
	157	return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
f9baff50	158	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
3fdcb97f EC	159	}
3fdcb97f EC	160
225c7b1f RD	161	static int mlx4_HW2SW_CQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	162	int cq_num)
	163	{
eb41049f	164	return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
d7233386	165	cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
f9baff50	166	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f RD	167	}
225c7b1f RD	168
3fdcb97f EC	169	int mlx4_cq_modify(struct mlx4_dev dev, struct mlx4_cq cq,
	170	u16 count, u16 period)
	171	{
	172	struct mlx4_cmd_mailbox *mailbox;
	173	struct mlx4_cq_context *cq_context;
	174	int err;
	175
	176	mailbox = mlx4_alloc_cmd_mailbox(dev);
	177	if (IS_ERR(mailbox))
	178	return PTR_ERR(mailbox);
	179
	180	cq_context = mailbox->buf;
3fdcb97f EC	181	cq_context->cq_max_count = cpu_to_be16(count);
	182	cq_context->cq_period = cpu_to_be16(period);
	183
	184	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
	185
	186	mlx4_free_cmd_mailbox(dev, mailbox);
	187	return err;
	188	}
	189	EXPORT_SYMBOL_GPL(mlx4_cq_modify);
	190
bbf8eed1 VS	191	int mlx4_cq_resize(struct mlx4_dev dev, struct mlx4_cq cq,
	192	int entries, struct mlx4_mtt *mtt)
	193	{
	194	struct mlx4_cmd_mailbox *mailbox;
	195	struct mlx4_cq_context *cq_context;
	196	u64 mtt_addr;
	197	int err;
	198
	199	mailbox = mlx4_alloc_cmd_mailbox(dev);
	200	if (IS_ERR(mailbox))
	201	return PTR_ERR(mailbox);
	202
	203	cq_context = mailbox->buf;
bbf8eed1 VS	204	cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
	205	cq_context->log_page_size = mtt->page_shift - 12;
	206	mtt_addr = mlx4_mtt_addr(dev, mtt);
	207	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	208	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	209
f5b3a096	210	err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
bbf8eed1 VS	211
	212	mlx4_free_cmd_mailbox(dev, mailbox);
	213	return err;
	214	}
	215	EXPORT_SYMBOL_GPL(mlx4_cq_resize);
	216
c82e9aa0	217	int __mlx4_cq_alloc_icm(struct mlx4_dev dev, int cqn)
d7233386 JM	218	{
	219	struct mlx4_priv *priv = mlx4_priv(dev);
	220	struct mlx4_cq_table *cq_table = &priv->cq_table;
	221	int err;
	222
	223	*cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
	224	if (*cqn == -1)
	225	return -ENOMEM;
	226
8900b894	227	err = mlx4_table_get(dev, &cq_table->table, *cqn);
d7233386 JM	228	if (err)
	229	goto err_out;
	230
8900b894	231	err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn);
d7233386 JM	232	if (err)
	233	goto err_put;
	234	return 0;
	235
	236	err_put:
	237	mlx4_table_put(dev, &cq_table->table, *cqn);
	238
	239	err_out:
7c6d74d2	240	mlx4_bitmap_free(&cq_table->bitmap, *cqn, MLX4_NO_RR);
d7233386 JM	241	return err;
	242	}
	243
	244	static int mlx4_cq_alloc_icm(struct mlx4_dev dev, int cqn)
	245	{
	246	u64 out_param;
	247	int err;
	248
	249	if (mlx4_is_mfunc(dev)) {
	250	err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
	251	RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
	252	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
	253	if (err)
	254	return err;
	255	else {
	256	*cqn = get_param_l(&out_param);
	257	return 0;
	258	}
	259	}
	260	return __mlx4_cq_alloc_icm(dev, cqn);
	261	}
	262
c82e9aa0	263	void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
d7233386 JM	264	{
	265	struct mlx4_priv *priv = mlx4_priv(dev);
	266	struct mlx4_cq_table *cq_table = &priv->cq_table;
	267
	268	mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
	269	mlx4_table_put(dev, &cq_table->table, cqn);
7c6d74d2	270	mlx4_bitmap_free(&cq_table->bitmap, cqn, MLX4_NO_RR);
d7233386 JM	271	}
	272
	273	static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
	274	{
e7dbeba8	275	u64 in_param = 0;
d7233386 JM	276	int err;
	277
	278	if (mlx4_is_mfunc(dev)) {
	279	set_param_l(&in_param, cqn);
	280	err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
	281	MLX4_CMD_FREE_RES,
	282	MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
	283	if (err)
	284	mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
	285	} else
	286	__mlx4_cq_free_icm(dev, cqn);
	287	}
	288
ec693d47 AV	289	int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
	290	struct mlx4_mtt mtt, struct mlx4_uar uar, u64 db_rec,
	291	struct mlx4_cq *cq, unsigned vector, int collapsed,
	292	int timestamp_en)
225c7b1f RD	293	{
	294	struct mlx4_priv *priv = mlx4_priv(dev);
	295	struct mlx4_cq_table *cq_table = &priv->cq_table;
	296	struct mlx4_cmd_mailbox *mailbox;
	297	struct mlx4_cq_context *cq_context;
	298	u64 mtt_addr;
	299	int err;
	300
c66fa19c	301	if (vector >= dev->caps.num_comp_vectors)
b8dd786f YP	302	return -EINVAL;
	303
	304	cq->vector = vector;
	305
d7233386	306	err = mlx4_cq_alloc_icm(dev, &cq->cqn);
225c7b1f	307	if (err)
d7233386	308	return err;
225c7b1f	309
291c566a	310	spin_lock(&cq_table->lock);
225c7b1f	311	err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
291c566a	312	spin_unlock(&cq_table->lock);
225c7b1f	313	if (err)
d7233386	314	goto err_icm;
225c7b1f RD	315
	316	mailbox = mlx4_alloc_cmd_mailbox(dev);
	317	if (IS_ERR(mailbox)) {
	318	err = PTR_ERR(mailbox);
	319	goto err_radix;
	320	}
	321
	322	cq_context = mailbox->buf;
e463c7b1	323	cq_context->flags = cpu_to_be32(!!collapsed << 18);
ec693d47 AV	324	if (timestamp_en)
	325	cq_context->flags \|= cpu_to_be32(1 << 19);
	326
85743f1e HN	327	cq_context->logsize_usrpage =
	328	cpu_to_be32((ilog2(nent) << 24) \|
	329	mlx4_to_hw_uar_index(dev, uar->index));
c66fa19c	330	cq_context->comp_eqn = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn;
225c7b1f RD	331	cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
	332
	333	mtt_addr = mlx4_mtt_addr(dev, mtt);
	334	cq_context->mtt_base_addr_h = mtt_addr >> 32;
	335	cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
	336	cq_context->db_rec_addr = cpu_to_be64(db_rec);
	337
	338	err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
	339	mlx4_free_cmd_mailbox(dev, mailbox);
	340	if (err)
	341	goto err_radix;
	342
	343	cq->cons_index = 0;
	344	cq->arm_sn = 1;
	345	cq->uar = uar;
	346	atomic_set(&cq->refcount, 1);
	347	init_completion(&cq->free);
3dca0f42 MB	348	cq->comp = mlx4_add_cq_to_tasklet;
3dca0f42 MB	349	cq->tasklet_ctx.priv =
c66fa19c	350	&priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].tasklet_ctx;
3dca0f42 MB	351	INIT_LIST_HEAD(&cq->tasklet_ctx.list);
3dca0f42 MB	352
225c7b1f	353
c66fa19c	354	cq->irq = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].irq;
225c7b1f RD	355	return 0;
	356
	357	err_radix:
291c566a	358	spin_lock(&cq_table->lock);
225c7b1f	359	radix_tree_delete(&cq_table->tree, cq->cqn);
291c566a	360	spin_unlock(&cq_table->lock);
225c7b1f	361
d7233386 JM	362	err_icm:
d7233386 JM	363	mlx4_cq_free_icm(dev, cq->cqn);
225c7b1f RD	364
	365	return err;
	366	}
	367	EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
	368
	369	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq)
	370	{
	371	struct mlx4_priv *priv = mlx4_priv(dev);
	372	struct mlx4_cq_table *cq_table = &priv->cq_table;
	373	int err;
	374
	375	err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
	376	if (err)
	377	mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
	378
291c566a JM	379	spin_lock(&cq_table->lock);
	380	radix_tree_delete(&cq_table->tree, cq->cqn);
	381	spin_unlock(&cq_table->lock);
	382
c66fa19c	383	synchronize_irq(priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq);
6d90aa5c MB	384	if (priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq !=
	385	priv->eq_table.eq[MLX4_EQ_ASYNC].irq)
	386	synchronize_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f	387
225c7b1f RD	388	if (atomic_dec_and_test(&cq->refcount))
	389	complete(&cq->free);
	390	wait_for_completion(&cq->free);
	391
d7233386	392	mlx4_cq_free_icm(dev, cq->cqn);
225c7b1f RD	393	}
	394	EXPORT_SYMBOL_GPL(mlx4_cq_free);
	395
3d73c288	396	int mlx4_init_cq_table(struct mlx4_dev *dev)
225c7b1f RD	397	{
	398	struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
	399	int err;
	400
	401	spin_lock_init(&cq_table->lock);
	402	INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
d7233386 JM	403	if (mlx4_is_slave(dev))
d7233386 JM	404	return 0;
225c7b1f RD	405
225c7b1f RD	406	err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
93fc9e1b	407	dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
225c7b1f RD	408	if (err)
	409	return err;
	410
	411	return 0;
	412	}
	413
	414	void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
	415	{
d7233386 JM	416	if (mlx4_is_slave(dev))
d7233386 JM	417	return;
225c7b1f RD	418	/* Nothing to do to clean up radix_tree */
	419	mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
	420	}