[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / en_clock.c

/*
 * Copyright (c) 2012 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#include <linux/mlx4/device.h>
#include <linux/clocksource.h>

#include "mlx4_en.h"

/* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
 */
static cycle_t mlx4_en_read_clock(const struct cyclecounter *tc)
{
	struct mlx4_en_dev *mdev =
		container_of(tc, struct mlx4_en_dev, cycles);
	struct mlx4_dev *dev = mdev->dev;

	return mlx4_read_clock(dev) & tc->mask;
}

u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe)
{
	u64 hi, lo;
	struct mlx4_ts_cqe *ts_cqe = (struct mlx4_ts_cqe *)cqe;

	lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo);
	hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16;

	return hi | lo;
}

void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
			    struct skb_shared_hwtstamps *hwts,
			    u64 timestamp)
{
	unsigned long flags;
	u64 nsec;

	read_lock_irqsave(&mdev->clock_lock, flags);
	nsec = timecounter_cyc2time(&mdev->clock, timestamp);
	read_unlock_irqrestore(&mdev->clock_lock, flags);

	memset(hwts, 0, sizeof(struct skb_shared_hwtstamps));
	hwts->hwtstamp = ns_to_ktime(nsec);
}

/**
 * mlx4_en_remove_timestamp - disable PTP device
 * @mdev: board private structure
 *
 * Stop the PTP support.
 **/
void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev)
{
	if (mdev->ptp_clock) {
		ptp_clock_unregister(mdev->ptp_clock);
		mdev->ptp_clock = NULL;
		mlx4_info(mdev, "removed PHC\n");
	}
}

void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev)
{
	bool timeout = time_is_before_jiffies(mdev->last_overflow_check +
					      mdev->overflow_period);
	unsigned long flags;

	if (timeout) {
		write_lock_irqsave(&mdev->clock_lock, flags);
		timecounter_read(&mdev->clock);
		write_unlock_irqrestore(&mdev->clock_lock, flags);
		mdev->last_overflow_check = jiffies;
	}
}

/**
 * mlx4_en_phc_adjfreq - adjust the frequency of the hardware clock
 * @ptp: ptp clock structure
 * @delta: Desired frequency change in parts per billion
 *
 * Adjust the frequency of the PHC cycle counter by the indicated delta from
 * the base frequency.
 **/
static int mlx4_en_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta)
{
	u64 adj;
	u32 diff, mult;
	int neg_adj = 0;
	unsigned long flags;
	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
						ptp_clock_info);

	if (delta < 0) {
		neg_adj = 1;
		delta = -delta;
	}
	mult = mdev->nominal_c_mult;
	adj = mult;
	adj *= delta;
	diff = div_u64(adj, 1000000000ULL);

	write_lock_irqsave(&mdev->clock_lock, flags);
	timecounter_read(&mdev->clock);
	mdev->cycles.mult = neg_adj ? mult - diff : mult + diff;
	write_unlock_irqrestore(&mdev->clock_lock, flags);

	return 0;
}

/**
 * mlx4_en_phc_adjtime - Shift the time of the hardware clock
 * @ptp: ptp clock structure
 * @delta: Desired change in nanoseconds
 *
 * Adjust the timer by resetting the timecounter structure.
 **/
static int mlx4_en_phc_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
						ptp_clock_info);
	unsigned long flags;

	write_lock_irqsave(&mdev->clock_lock, flags);
	timecounter_adjtime(&mdev->clock, delta);
	write_unlock_irqrestore(&mdev->clock_lock, flags);

	return 0;
}

/**
 * mlx4_en_phc_gettime - Reads the current time from the hardware clock
 * @ptp: ptp clock structure
 * @ts: timespec structure to hold the current time value
 *
 * Read the timecounter and return the correct value in ns after converting
 * it into a struct timespec.
 **/
static int mlx4_en_phc_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
						ptp_clock_info);
	unsigned long flags;
	u32 remainder;
	u64 ns;

	write_lock_irqsave(&mdev->clock_lock, flags);
	ns = timecounter_read(&mdev->clock);
	write_unlock_irqrestore(&mdev->clock_lock, flags);

	ts->tv_sec = div_u64_rem(ns, NSEC_PER_SEC, &remainder);
	ts->tv_nsec = remainder;

	return 0;
}

/**
 * mlx4_en_phc_settime - Set the current time on the hardware clock
 * @ptp: ptp clock structure
 * @ts: timespec containing the new time for the cycle counter
 *
 * Reset the timecounter to use a new base value instead of the kernel
 * wall timer value.
 **/
static int mlx4_en_phc_settime(struct ptp_clock_info *ptp,
			       const struct timespec *ts)
{
	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
						ptp_clock_info);
	u64 ns = timespec_to_ns(ts);
	unsigned long flags;

	/* reset the timecounter */
	write_lock_irqsave(&mdev->clock_lock, flags);
	timecounter_init(&mdev->clock, &mdev->cycles, ns);
	write_unlock_irqrestore(&mdev->clock_lock, flags);

	return 0;
}

/**
 * mlx4_en_phc_enable - enable or disable an ancillary feature
 * @ptp: ptp clock structure
 * @request: Desired resource to enable or disable
 * @on: Caller passes one to enable or zero to disable
 *
 * Enable (or disable) ancillary features of the PHC subsystem.
 * Currently, no ancillary features are supported.
 **/
static int mlx4_en_phc_enable(struct ptp_clock_info __always_unused *ptp,
			      struct ptp_clock_request __always_unused *request,
			      int __always_unused on)
{
	return -EOPNOTSUPP;
}

static const struct ptp_clock_info mlx4_en_ptp_clock_info = {
	.owner		= THIS_MODULE,
	.max_adj	= 100000000,
	.n_alarm	= 0,
	.n_ext_ts	= 0,
	.n_per_out	= 0,
	.n_pins		= 0,
	.pps		= 0,
	.adjfreq	= mlx4_en_phc_adjfreq,
	.adjtime	= mlx4_en_phc_adjtime,
	.gettime	= mlx4_en_phc_gettime,
	.settime	= mlx4_en_phc_settime,
	.enable		= mlx4_en_phc_enable,
};

void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev)
{
	struct mlx4_dev *dev = mdev->dev;
	unsigned long flags;
	u64 ns, zero = 0;

	rwlock_init(&mdev->clock_lock);

	memset(&mdev->cycles, 0, sizeof(mdev->cycles));
	mdev->cycles.read = mlx4_en_read_clock;
	mdev->cycles.mask = CLOCKSOURCE_MASK(48);
	/* Using shift to make calculation more accurate. Since current HW
	 * clock frequency is 427 MHz, and cycles are given using a 48 bits
	 * register, the biggest shift when calculating using u64, is 14
	 * (max_cycles * multiplier < 2^64)
	 */
	mdev->cycles.shift = 14;
	mdev->cycles.mult =
		clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift);
	mdev->nominal_c_mult = mdev->cycles.mult;

	write_lock_irqsave(&mdev->clock_lock, flags);
	timecounter_init(&mdev->clock, &mdev->cycles,
			 ktime_to_ns(ktime_get_real()));
	write_unlock_irqrestore(&mdev->clock_lock, flags);

	/* Calculate period in seconds to call the overflow watchdog - to make
	 * sure counter is checked at least once every wrap around.
	 */
	ns = cyclecounter_cyc2ns(&mdev->cycles, mdev->cycles.mask, zero, &zero);
	do_div(ns, NSEC_PER_SEC / 2 / HZ);
	mdev->overflow_period = ns;

	/* Configure the PHC */
	mdev->ptp_clock_info = mlx4_en_ptp_clock_info;
	snprintf(mdev->ptp_clock_info.name, 16, "mlx4 ptp");

	mdev->ptp_clock = ptp_clock_register(&mdev->ptp_clock_info,
					     &mdev->pdev->dev);
	if (IS_ERR(mdev->ptp_clock)) {
		mdev->ptp_clock = NULL;
		mlx4_err(mdev, "ptp_clock_register failed\n");
	} else {
		mlx4_info(mdev, "registered PHC clock\n");
	}

}
Commit	Line	Data
ec693d47 AV	1	/*
	2	* Copyright (c) 2012 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#include <linux/mlx4/device.h>
d9f39373	35	#include <linux/clocksource.h>
ec693d47 AV	36
	37	#include "mlx4_en.h"
	38
ec693d47 AV	39	/* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
	40	*/
	41	static cycle_t mlx4_en_read_clock(const struct cyclecounter *tc)
	42	{
	43	struct mlx4_en_dev *mdev =
	44	container_of(tc, struct mlx4_en_dev, cycles);
	45	struct mlx4_dev *dev = mdev->dev;
	46
	47	return mlx4_read_clock(dev) & tc->mask;
	48	}
	49
	50	u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe)
	51	{
	52	u64 hi, lo;
	53	struct mlx4_ts_cqe ts_cqe = (struct mlx4_ts_cqe )cqe;
	54
	55	lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo);
	56	hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16;
	57
	58	return hi \| lo;
	59	}
	60
	61	void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
	62	struct skb_shared_hwtstamps *hwts,
	63	u64 timestamp)
	64	{
ad7d4eae	65	unsigned long flags;
ec693d47 AV	66	u64 nsec;
ec693d47 AV	67
ad7d4eae	68	read_lock_irqsave(&mdev->clock_lock, flags);
ec693d47	69	nsec = timecounter_cyc2time(&mdev->clock, timestamp);
ad7d4eae	70	read_unlock_irqrestore(&mdev->clock_lock, flags);
ec693d47 AV	71
	72	memset(hwts, 0, sizeof(struct skb_shared_hwtstamps));
	73	hwts->hwtstamp = ns_to_ktime(nsec);
	74	}
	75
ad7d4eae SB	76	/**
	77	* mlx4_en_remove_timestamp - disable PTP device
	78	* @mdev: board private structure
	79	*
	80	* Stop the PTP support.
	81	**/
	82	void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev)
	83	{
	84	if (mdev->ptp_clock) {
	85	ptp_clock_unregister(mdev->ptp_clock);
	86	mdev->ptp_clock = NULL;
	87	mlx4_info(mdev, "removed PHC\n");
	88	}
	89	}
	90
	91	void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev)
	92	{
	93	bool timeout = time_is_before_jiffies(mdev->last_overflow_check +
	94	mdev->overflow_period);
	95	unsigned long flags;
	96
	97	if (timeout) {
	98	write_lock_irqsave(&mdev->clock_lock, flags);
	99	timecounter_read(&mdev->clock);
	100	write_unlock_irqrestore(&mdev->clock_lock, flags);
	101	mdev->last_overflow_check = jiffies;
	102	}
	103	}
	104
	105	/**
	106	* mlx4_en_phc_adjfreq - adjust the frequency of the hardware clock
	107	* @ptp: ptp clock structure
	108	* @delta: Desired frequency change in parts per billion
	109	*
	110	* Adjust the frequency of the PHC cycle counter by the indicated delta from
	111	* the base frequency.
	112	**/
	113	static int mlx4_en_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta)
	114	{
	115	u64 adj;
	116	u32 diff, mult;
	117	int neg_adj = 0;
	118	unsigned long flags;
	119	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
	120	ptp_clock_info);
	121
	122	if (delta < 0) {
	123	neg_adj = 1;
	124	delta = -delta;
	125	}
	126	mult = mdev->nominal_c_mult;
	127	adj = mult;
	128	adj *= delta;
	129	diff = div_u64(adj, 1000000000ULL);
	130
	131	write_lock_irqsave(&mdev->clock_lock, flags);
	132	timecounter_read(&mdev->clock);
	133	mdev->cycles.mult = neg_adj ? mult - diff : mult + diff;
	134	write_unlock_irqrestore(&mdev->clock_lock, flags);
	135
	136	return 0;
	137	}
	138
	139	/**
140	* mlx4_en_phc_adjtime - Shift the time of the hardware clock
141	* @ptp: ptp clock structure
142	* @delta: Desired change in nanoseconds
143	*
144	* Adjust the timer by resetting the timecounter structure.
145	**/
146	static int mlx4_en_phc_adjtime(struct ptp_clock_info *ptp, s64 delta)
147	{
148	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
149	ptp_clock_info);
150	unsigned long flags;
ad7d4eae SB	151
ad7d4eae SB	152	write_lock_irqsave(&mdev->clock_lock, flags);
ce51ff09	153	timecounter_adjtime(&mdev->clock, delta);
ad7d4eae SB	154	write_unlock_irqrestore(&mdev->clock_lock, flags);
	155
	156	return 0;
	157	}
	158
	159	/**
	160	* mlx4_en_phc_gettime - Reads the current time from the hardware clock
	161	* @ptp: ptp clock structure
	162	* @ts: timespec structure to hold the current time value
	163	*
	164	* Read the timecounter and return the correct value in ns after converting
	165	* it into a struct timespec.
	166	**/
	167	static int mlx4_en_phc_gettime(struct ptp_clock_info ptp, struct timespec ts)
	168	{
	169	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
	170	ptp_clock_info);
	171	unsigned long flags;
	172	u32 remainder;
	173	u64 ns;
	174
	175	write_lock_irqsave(&mdev->clock_lock, flags);
	176	ns = timecounter_read(&mdev->clock);
	177	write_unlock_irqrestore(&mdev->clock_lock, flags);
	178
	179	ts->tv_sec = div_u64_rem(ns, NSEC_PER_SEC, &remainder);
	180	ts->tv_nsec = remainder;
	181
	182	return 0;
	183	}
	184
	185	/**
	186	* mlx4_en_phc_settime - Set the current time on the hardware clock
	187	* @ptp: ptp clock structure
	188	* @ts: timespec containing the new time for the cycle counter
	189	*
	190	* Reset the timecounter to use a new base value instead of the kernel
	191	* wall timer value.
	192	**/
	193	static int mlx4_en_phc_settime(struct ptp_clock_info *ptp,
	194	const struct timespec *ts)
	195	{
	196	struct mlx4_en_dev *mdev = container_of(ptp, struct mlx4_en_dev,
	197	ptp_clock_info);
	198	u64 ns = timespec_to_ns(ts);
	199	unsigned long flags;
	200
	201	/* reset the timecounter */
	202	write_lock_irqsave(&mdev->clock_lock, flags);
	203	timecounter_init(&mdev->clock, &mdev->cycles, ns);
	204	write_unlock_irqrestore(&mdev->clock_lock, flags);
	205
	206	return 0;
	207	}
	208
	209	/**
	210	* mlx4_en_phc_enable - enable or disable an ancillary feature
	211	* @ptp: ptp clock structure
	212	* @request: Desired resource to enable or disable
	213	* @on: Caller passes one to enable or zero to disable
	214	*
	215	* Enable (or disable) ancillary features of the PHC subsystem.
	216	* Currently, no ancillary features are supported.
	217	**/
218	static int mlx4_en_phc_enable(struct ptp_clock_info __always_unused *ptp,
219	struct ptp_clock_request __always_unused *request,
220	int __always_unused on)
221	{
222	return -EOPNOTSUPP;
223	}
224
225	static const struct ptp_clock_info mlx4_en_ptp_clock_info = {
226	.owner = THIS_MODULE,
227	.max_adj = 100000000,
228	.n_alarm = 0,
229	.n_ext_ts = 0,
230	.n_per_out = 0,
4986b4f0	231	.n_pins = 0,
ad7d4eae SB	232	.pps = 0,
	233	.adjfreq = mlx4_en_phc_adjfreq,
	234	.adjtime = mlx4_en_phc_adjtime,
	235	.gettime = mlx4_en_phc_gettime,
	236	.settime = mlx4_en_phc_settime,
	237	.enable = mlx4_en_phc_enable,
	238	};
	239
ec693d47 AV	240	void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev)
	241	{
	242	struct mlx4_dev *dev = mdev->dev;
ad7d4eae	243	unsigned long flags;
2eebdde6	244	u64 ns, zero = 0;
ec693d47	245
ad7d4eae SB	246	rwlock_init(&mdev->clock_lock);
ad7d4eae SB	247
ec693d47 AV	248	memset(&mdev->cycles, 0, sizeof(mdev->cycles));
	249	mdev->cycles.read = mlx4_en_read_clock;
	250	mdev->cycles.mask = CLOCKSOURCE_MASK(48);
	251	/* Using shift to make calculation more accurate. Since current HW
	252	* clock frequency is 427 MHz, and cycles are given using a 48 bits
	253	* register, the biggest shift when calculating using u64, is 14
	254	* (max_cycles * multiplier < 2^64)
	255	*/
	256	mdev->cycles.shift = 14;
	257	mdev->cycles.mult =
	258	clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift);
ad7d4eae	259	mdev->nominal_c_mult = mdev->cycles.mult;
ec693d47	260
ad7d4eae	261	write_lock_irqsave(&mdev->clock_lock, flags);
ec693d47 AV	262	timecounter_init(&mdev->clock, &mdev->cycles,
ec693d47 AV	263	ktime_to_ns(ktime_get_real()));
ad7d4eae	264	write_unlock_irqrestore(&mdev->clock_lock, flags);
b6c39bfc AV	265
	266	/* Calculate period in seconds to call the overflow watchdog - to make
	267	* sure counter is checked at least once every wrap around.
	268	*/
2eebdde6	269	ns = cyclecounter_cyc2ns(&mdev->cycles, mdev->cycles.mask, zero, &zero);
fe86d714 ED	270	do_div(ns, NSEC_PER_SEC / 2 / HZ);
fe86d714 ED	271	mdev->overflow_period = ns;
b6c39bfc	272
ad7d4eae SB	273	/* Configure the PHC */
	274	mdev->ptp_clock_info = mlx4_en_ptp_clock_info;
	275	snprintf(mdev->ptp_clock_info.name, 16, "mlx4 ptp");
b6c39bfc	276
ad7d4eae SB	277	mdev->ptp_clock = ptp_clock_register(&mdev->ptp_clock_info,
	278	&mdev->pdev->dev);
	279	if (IS_ERR(mdev->ptp_clock)) {
	280	mdev->ptp_clock = NULL;
	281	mlx4_err(mdev, "ptp_clock_register failed\n");
	282	} else {
	283	mlx4_info(mdev, "registered PHC clock\n");
b6c39bfc	284	}
ad7d4eae	285
ec693d47	286	}