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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
35 | #include <linux/mlx4/qp.h> | |
36 | #include <linux/mlx4/cmd.h> | |
37 | ||
38 | #include "mlx4_en.h" | |
39 | ||
40 | static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event) | |
41 | { | |
42 | return; | |
43 | } | |
44 | ||
45 | ||
46 | int mlx4_en_create_cq(struct mlx4_en_priv *priv, | |
41d942d5 | 47 | struct mlx4_en_cq **pcq, |
163561a4 EE |
48 | int entries, int ring, enum cq_type mode, |
49 | int node) | |
c27a02cd YP |
50 | { |
51 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 52 | struct mlx4_en_cq *cq; |
c27a02cd YP |
53 | int err; |
54 | ||
163561a4 | 55 | cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node); |
41d942d5 | 56 | if (!cq) { |
163561a4 EE |
57 | cq = kzalloc(sizeof(*cq), GFP_KERNEL); |
58 | if (!cq) { | |
59 | en_err(priv, "Failed to allocate CQ structure\n"); | |
60 | return -ENOMEM; | |
61 | } | |
41d942d5 EE |
62 | } |
63 | ||
c27a02cd | 64 | cq->size = entries; |
08ff3235 | 65 | cq->buf_size = cq->size * mdev->dev->caps.cqe_size; |
c27a02cd YP |
66 | |
67 | cq->ring = ring; | |
ccc109b8 | 68 | cq->type = mode; |
c66fa19c | 69 | cq->vector = mdev->dev->caps.num_comp_vectors; |
c27a02cd | 70 | |
163561a4 EE |
71 | /* Allocate HW buffers on provided NUMA node. |
72 | * dev->numa_node is used in mtt range allocation flow. | |
73 | */ | |
872bf2fb | 74 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
c27a02cd | 75 | err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres, |
73898db0 | 76 | cq->buf_size); |
872bf2fb | 77 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 78 | if (err) |
41d942d5 | 79 | goto err_cq; |
c27a02cd | 80 | |
41d942d5 EE |
81 | cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf; |
82 | *pcq = cq; | |
c27a02cd | 83 | |
41d942d5 EE |
84 | return 0; |
85 | ||
41d942d5 EE |
86 | err_cq: |
87 | kfree(cq); | |
88 | *pcq = NULL; | |
c27a02cd YP |
89 | return err; |
90 | } | |
91 | ||
76532d0c AG |
92 | int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, |
93 | int cq_idx) | |
c27a02cd YP |
94 | { |
95 | struct mlx4_en_dev *mdev = priv->mdev; | |
1fb9876e | 96 | int err = 0; |
ec693d47 | 97 | int timestamp_en = 0; |
c66fa19c | 98 | bool assigned_eq = false; |
c27a02cd YP |
99 | |
100 | cq->dev = mdev->pndev[priv->port]; | |
101 | cq->mcq.set_ci_db = cq->wqres.db.db; | |
102 | cq->mcq.arm_db = cq->wqres.db.db + 1; | |
103 | *cq->mcq.set_ci_db = 0; | |
104 | *cq->mcq.arm_db = 0; | |
c27a02cd YP |
105 | memset(cq->buf, 0, cq->buf_size); |
106 | ||
ccc109b8 | 107 | if (cq->type == RX) { |
c66fa19c MB |
108 | if (!mlx4_is_eq_vector_valid(mdev->dev, priv->port, |
109 | cq->vector)) { | |
de161803 | 110 | cq->vector = cpumask_first(priv->rx_ring[cq->ring]->affinity_mask); |
c66fa19c MB |
111 | |
112 | err = mlx4_assign_eq(mdev->dev, priv->port, | |
113 | &cq->vector); | |
114 | if (err) { | |
b0f64463 CS |
115 | mlx4_err(mdev, "Failed assigning an EQ to CQ vector %d\n", |
116 | cq->vector); | |
c66fa19c | 117 | goto free_eq; |
1fb9876e | 118 | } |
c66fa19c MB |
119 | |
120 | assigned_eq = true; | |
1fb9876e | 121 | } |
858e6c32 AV |
122 | |
123 | cq->irq_desc = | |
124 | irq_to_desc(mlx4_eq_get_irq(mdev->dev, | |
125 | cq->vector)); | |
1fb9876e | 126 | } else { |
76532d0c AG |
127 | /* For TX we use the same irq per |
128 | ring we assigned for the RX */ | |
129 | struct mlx4_en_cq *rx_cq; | |
67f8b1dc | 130 | |
76532d0c | 131 | cq_idx = cq_idx % priv->rx_ring_num; |
41d942d5 | 132 | rx_cq = priv->rx_cq[cq_idx]; |
76532d0c | 133 | cq->vector = rx_cq->vector; |
1fb9876e YP |
134 | } |
135 | ||
ccc109b8 | 136 | if (cq->type == RX) |
41d942d5 | 137 | cq->size = priv->rx_ring[cq->ring]->actual_size; |
38aab07c | 138 | |
ccc109b8 TT |
139 | if ((cq->type != RX && priv->hwtstamp_config.tx_type) || |
140 | (cq->type == RX && priv->hwtstamp_config.rx_filter)) | |
ec693d47 AV |
141 | timestamp_en = 1; |
142 | ||
143 | err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt, | |
144 | &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq, | |
145 | cq->vector, 0, timestamp_en); | |
c27a02cd | 146 | if (err) |
c66fa19c | 147 | goto free_eq; |
c27a02cd | 148 | |
c27a02cd YP |
149 | cq->mcq.event = mlx4_en_cq_event; |
150 | ||
6c78511b TT |
151 | switch (cq->type) { |
152 | case TX: | |
153 | cq->mcq.comp = mlx4_en_tx_irq; | |
d64b5e85 ED |
154 | netif_tx_napi_add(cq->dev, &cq->napi, mlx4_en_poll_tx_cq, |
155 | NAPI_POLL_WEIGHT); | |
6c78511b TT |
156 | napi_enable(&cq->napi); |
157 | break; | |
158 | case RX: | |
159 | cq->mcq.comp = mlx4_en_rx_irq; | |
c27a02cd | 160 | netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64); |
6c78511b TT |
161 | napi_enable(&cq->napi); |
162 | break; | |
163 | case TX_XDP: | |
164 | /* nothing regarding napi, it's shared with rx ring */ | |
165 | cq->xdp_busy = false; | |
166 | break; | |
167 | } | |
0276a330 | 168 | |
c27a02cd | 169 | return 0; |
c66fa19c MB |
170 | |
171 | free_eq: | |
172 | if (assigned_eq) | |
173 | mlx4_release_eq(mdev->dev, cq->vector); | |
174 | cq->vector = mdev->dev->caps.num_comp_vectors; | |
175 | return err; | |
c27a02cd YP |
176 | } |
177 | ||
41d942d5 | 178 | void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq) |
c27a02cd YP |
179 | { |
180 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 181 | struct mlx4_en_cq *cq = *pcq; |
c27a02cd | 182 | |
c27a02cd | 183 | mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); |
c66fa19c | 184 | if (mlx4_is_eq_vector_valid(mdev->dev, priv->port, cq->vector) && |
ccc109b8 | 185 | cq->type == RX) |
1fb9876e | 186 | mlx4_release_eq(priv->mdev->dev, cq->vector); |
cd3109d2 | 187 | cq->vector = 0; |
c27a02cd YP |
188 | cq->buf_size = 0; |
189 | cq->buf = NULL; | |
41d942d5 EE |
190 | kfree(cq); |
191 | *pcq = NULL; | |
c27a02cd YP |
192 | } |
193 | ||
194 | void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) | |
195 | { | |
6c78511b TT |
196 | if (cq->type != TX_XDP) { |
197 | napi_disable(&cq->napi); | |
198 | netif_napi_del(&cq->napi); | |
199 | } | |
c27a02cd | 200 | |
e22979d9 | 201 | mlx4_cq_free(priv->mdev->dev, &cq->mcq); |
c27a02cd YP |
202 | } |
203 | ||
204 | /* Set rx cq moderation parameters */ | |
205 | int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) | |
206 | { | |
207 | return mlx4_cq_modify(priv->mdev->dev, &cq->mcq, | |
208 | cq->moder_cnt, cq->moder_time); | |
209 | } | |
210 | ||
211 | int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq) | |
212 | { | |
c27a02cd YP |
213 | mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map, |
214 | &priv->mdev->uar_lock); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 |