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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/netdevice.h> | |
af22d9de | 37 | #include <linux/mlx4/driver.h> |
7202da8b | 38 | #include <linux/mlx4/device.h> |
f90a3673 HHZ |
39 | #include <linux/in.h> |
40 | #include <net/ip.h> | |
6fcd2735 | 41 | #include <linux/bitmap.h> |
c27a02cd YP |
42 | |
43 | #include "mlx4_en.h" | |
44 | #include "en_port.h" | |
45 | ||
82067281 | 46 | #define EN_ETHTOOL_QP_ATTACH (1ull << 63) |
82067281 HHZ |
47 | #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff) |
48 | #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff) | |
c27a02cd | 49 | |
79c54b6b AV |
50 | static int mlx4_en_moderation_update(struct mlx4_en_priv *priv) |
51 | { | |
67f8b1dc | 52 | int i, t; |
79c54b6b AV |
53 | int err = 0; |
54 | ||
67f8b1dc TT |
55 | for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) { |
56 | for (i = 0; i < priv->tx_ring_num[t]; i++) { | |
57 | priv->tx_cq[t][i]->moder_cnt = priv->tx_frames; | |
58 | priv->tx_cq[t][i]->moder_time = priv->tx_usecs; | |
59 | if (priv->port_up) { | |
60 | err = mlx4_en_set_cq_moder(priv, | |
61 | priv->tx_cq[t][i]); | |
62 | if (err) | |
63 | return err; | |
64 | } | |
38463e2c | 65 | } |
79c54b6b AV |
66 | } |
67 | ||
68 | if (priv->adaptive_rx_coal) | |
69 | return 0; | |
70 | ||
71 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
72 | priv->rx_cq[i]->moder_cnt = priv->rx_frames; |
73 | priv->rx_cq[i]->moder_time = priv->rx_usecs; | |
79c54b6b | 74 | priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; |
38463e2c | 75 | if (priv->port_up) { |
41d942d5 | 76 | err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]); |
38463e2c EE |
77 | if (err) |
78 | return err; | |
79 | } | |
79c54b6b AV |
80 | } |
81 | ||
82 | return err; | |
83 | } | |
84 | ||
c27a02cd YP |
85 | static void |
86 | mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) | |
87 | { | |
88 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
89 | struct mlx4_en_dev *mdev = priv->mdev; | |
90 | ||
612a94d6 | 91 | strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); |
808df6a2 | 92 | strlcpy(drvinfo->version, DRV_VERSION, |
612a94d6 RJ |
93 | sizeof(drvinfo->version)); |
94 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | |
95 | "%d.%d.%d", | |
c27a02cd YP |
96 | (u16) (mdev->dev->caps.fw_ver >> 32), |
97 | (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff), | |
98 | (u16) (mdev->dev->caps.fw_ver & 0xffff)); | |
872bf2fb | 99 | strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev), |
612a94d6 | 100 | sizeof(drvinfo->bus_info)); |
c27a02cd YP |
101 | } |
102 | ||
0fef9d03 AV |
103 | static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = { |
104 | "blueflame", | |
e38af4fa | 105 | "phv-bit" |
0fef9d03 AV |
106 | }; |
107 | ||
c27a02cd | 108 | static const char main_strings[][ETH_GSTRING_LEN] = { |
6fcd2735 | 109 | /* main statistics */ |
c27a02cd YP |
110 | "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", |
111 | "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", | |
112 | "rx_length_errors", "rx_over_errors", "rx_crc_errors", | |
113 | "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", | |
114 | "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", | |
115 | "tx_heartbeat_errors", "tx_window_errors", | |
116 | ||
117 | /* port statistics */ | |
fa37a958 | 118 | "tso_packets", |
9fab426d | 119 | "xmit_more", |
7d7bfc6a | 120 | "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_pages", |
f8c6455b | 121 | "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload", |
c27a02cd | 122 | |
b42de4d0 EBE |
123 | /* pf statistics */ |
124 | "pf_rx_packets", | |
125 | "pf_rx_bytes", | |
126 | "pf_tx_packets", | |
127 | "pf_tx_bytes", | |
128 | ||
0b131561 MB |
129 | /* priority flow control statistics rx */ |
130 | "rx_pause_prio_0", "rx_pause_duration_prio_0", | |
131 | "rx_pause_transition_prio_0", | |
132 | "rx_pause_prio_1", "rx_pause_duration_prio_1", | |
133 | "rx_pause_transition_prio_1", | |
134 | "rx_pause_prio_2", "rx_pause_duration_prio_2", | |
135 | "rx_pause_transition_prio_2", | |
136 | "rx_pause_prio_3", "rx_pause_duration_prio_3", | |
137 | "rx_pause_transition_prio_3", | |
138 | "rx_pause_prio_4", "rx_pause_duration_prio_4", | |
139 | "rx_pause_transition_prio_4", | |
140 | "rx_pause_prio_5", "rx_pause_duration_prio_5", | |
141 | "rx_pause_transition_prio_5", | |
142 | "rx_pause_prio_6", "rx_pause_duration_prio_6", | |
143 | "rx_pause_transition_prio_6", | |
144 | "rx_pause_prio_7", "rx_pause_duration_prio_7", | |
145 | "rx_pause_transition_prio_7", | |
146 | ||
147 | /* flow control statistics rx */ | |
148 | "rx_pause", "rx_pause_duration", "rx_pause_transition", | |
149 | ||
150 | /* priority flow control statistics tx */ | |
151 | "tx_pause_prio_0", "tx_pause_duration_prio_0", | |
152 | "tx_pause_transition_prio_0", | |
153 | "tx_pause_prio_1", "tx_pause_duration_prio_1", | |
154 | "tx_pause_transition_prio_1", | |
155 | "tx_pause_prio_2", "tx_pause_duration_prio_2", | |
156 | "tx_pause_transition_prio_2", | |
157 | "tx_pause_prio_3", "tx_pause_duration_prio_3", | |
158 | "tx_pause_transition_prio_3", | |
159 | "tx_pause_prio_4", "tx_pause_duration_prio_4", | |
160 | "tx_pause_transition_prio_4", | |
161 | "tx_pause_prio_5", "tx_pause_duration_prio_5", | |
162 | "tx_pause_transition_prio_5", | |
163 | "tx_pause_prio_6", "tx_pause_duration_prio_6", | |
164 | "tx_pause_transition_prio_6", | |
165 | "tx_pause_prio_7", "tx_pause_duration_prio_7", | |
166 | "tx_pause_transition_prio_7", | |
167 | ||
168 | /* flow control statistics tx */ | |
169 | "tx_pause", "tx_pause_duration", "tx_pause_transition", | |
170 | ||
c27a02cd | 171 | /* packet statistics */ |
a3333b35 EBE |
172 | "rx_multicast_packets", |
173 | "rx_broadcast_packets", | |
174 | "rx_jabbers", | |
175 | "rx_in_range_length_error", | |
176 | "rx_out_range_length_error", | |
177 | "tx_multicast_packets", | |
178 | "tx_broadcast_packets", | |
179 | "rx_prio_0_packets", "rx_prio_0_bytes", | |
180 | "rx_prio_1_packets", "rx_prio_1_bytes", | |
181 | "rx_prio_2_packets", "rx_prio_2_bytes", | |
182 | "rx_prio_3_packets", "rx_prio_3_bytes", | |
183 | "rx_prio_4_packets", "rx_prio_4_bytes", | |
184 | "rx_prio_5_packets", "rx_prio_5_bytes", | |
185 | "rx_prio_6_packets", "rx_prio_6_bytes", | |
186 | "rx_prio_7_packets", "rx_prio_7_bytes", | |
187 | "rx_novlan_packets", "rx_novlan_bytes", | |
188 | "tx_prio_0_packets", "tx_prio_0_bytes", | |
189 | "tx_prio_1_packets", "tx_prio_1_bytes", | |
190 | "tx_prio_2_packets", "tx_prio_2_bytes", | |
191 | "tx_prio_3_packets", "tx_prio_3_bytes", | |
192 | "tx_prio_4_packets", "tx_prio_4_bytes", | |
193 | "tx_prio_5_packets", "tx_prio_5_bytes", | |
194 | "tx_prio_6_packets", "tx_prio_6_bytes", | |
195 | "tx_prio_7_packets", "tx_prio_7_bytes", | |
196 | "tx_novlan_packets", "tx_novlan_bytes", | |
197 | ||
15fca2c8 TT |
198 | /* xdp statistics */ |
199 | "rx_xdp_drop", | |
200 | "rx_xdp_tx", | |
201 | "rx_xdp_tx_full", | |
c27a02cd | 202 | }; |
c27a02cd | 203 | |
e7c1c2c4 | 204 | static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= { |
fd9071ec | 205 | "Interrupt Test", |
e7c1c2c4 YP |
206 | "Link Test", |
207 | "Speed Test", | |
208 | "Register Test", | |
209 | "Loopback Test", | |
210 | }; | |
211 | ||
c27a02cd YP |
212 | static u32 mlx4_en_get_msglevel(struct net_device *dev) |
213 | { | |
214 | return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable; | |
215 | } | |
216 | ||
217 | static void mlx4_en_set_msglevel(struct net_device *dev, u32 val) | |
218 | { | |
219 | ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val; | |
220 | } | |
221 | ||
222 | static void mlx4_en_get_wol(struct net_device *netdev, | |
223 | struct ethtool_wolinfo *wol) | |
224 | { | |
14c07b13 | 225 | struct mlx4_en_priv *priv = netdev_priv(netdev); |
c994f778 | 226 | struct mlx4_caps *caps = &priv->mdev->dev->caps; |
14c07b13 YP |
227 | int err = 0; |
228 | u64 config = 0; | |
559a9f1d | 229 | u64 mask; |
14c07b13 | 230 | |
559a9f1d OD |
231 | if ((priv->port < 1) || (priv->port > 2)) { |
232 | en_err(priv, "Failed to get WoL information\n"); | |
233 | return; | |
234 | } | |
235 | ||
236 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | |
237 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | |
238 | ||
c994f778 | 239 | if (!(caps->flags & mask)) { |
14c07b13 YP |
240 | wol->supported = 0; |
241 | wol->wolopts = 0; | |
242 | return; | |
243 | } | |
244 | ||
c994f778 IK |
245 | if (caps->wol_port[priv->port]) |
246 | wol->supported = WAKE_MAGIC; | |
247 | else | |
248 | wol->supported = 0; | |
249 | ||
14c07b13 YP |
250 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); |
251 | if (err) { | |
252 | en_err(priv, "Failed to get WoL information\n"); | |
253 | return; | |
254 | } | |
255 | ||
c994f778 | 256 | if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC)) |
14c07b13 YP |
257 | wol->wolopts = WAKE_MAGIC; |
258 | else | |
259 | wol->wolopts = 0; | |
260 | } | |
261 | ||
262 | static int mlx4_en_set_wol(struct net_device *netdev, | |
263 | struct ethtool_wolinfo *wol) | |
264 | { | |
265 | struct mlx4_en_priv *priv = netdev_priv(netdev); | |
266 | u64 config = 0; | |
267 | int err = 0; | |
559a9f1d OD |
268 | u64 mask; |
269 | ||
270 | if ((priv->port < 1) || (priv->port > 2)) | |
271 | return -EOPNOTSUPP; | |
272 | ||
273 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | |
274 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | |
14c07b13 | 275 | |
559a9f1d | 276 | if (!(priv->mdev->dev->caps.flags & mask)) |
14c07b13 YP |
277 | return -EOPNOTSUPP; |
278 | ||
279 | if (wol->supported & ~WAKE_MAGIC) | |
280 | return -EINVAL; | |
281 | ||
282 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); | |
283 | if (err) { | |
284 | en_err(priv, "Failed to get WoL info, unable to modify\n"); | |
285 | return err; | |
286 | } | |
287 | ||
288 | if (wol->wolopts & WAKE_MAGIC) { | |
289 | config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED | | |
290 | MLX4_EN_WOL_MAGIC; | |
291 | } else { | |
292 | config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC); | |
293 | config |= MLX4_EN_WOL_DO_MODIFY; | |
294 | } | |
295 | ||
296 | err = mlx4_wol_write(priv->mdev->dev, config, priv->port); | |
297 | if (err) | |
298 | en_err(priv, "Failed to set WoL information\n"); | |
299 | ||
300 | return err; | |
c27a02cd YP |
301 | } |
302 | ||
6fcd2735 EBE |
303 | struct bitmap_iterator { |
304 | unsigned long *stats_bitmap; | |
305 | unsigned int count; | |
306 | unsigned int iterator; | |
307 | bool advance_array; /* if set, force no increments */ | |
308 | }; | |
309 | ||
310 | static inline void bitmap_iterator_init(struct bitmap_iterator *h, | |
311 | unsigned long *stats_bitmap, | |
312 | int count) | |
313 | { | |
314 | h->iterator = 0; | |
315 | h->advance_array = !bitmap_empty(stats_bitmap, count); | |
316 | h->count = h->advance_array ? bitmap_weight(stats_bitmap, count) | |
317 | : count; | |
318 | h->stats_bitmap = stats_bitmap; | |
319 | } | |
320 | ||
321 | static inline int bitmap_iterator_test(struct bitmap_iterator *h) | |
322 | { | |
323 | return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap); | |
324 | } | |
325 | ||
326 | static inline int bitmap_iterator_inc(struct bitmap_iterator *h) | |
327 | { | |
328 | return h->iterator++; | |
329 | } | |
330 | ||
331 | static inline unsigned int | |
332 | bitmap_iterator_count(struct bitmap_iterator *h) | |
333 | { | |
334 | return h->count; | |
335 | } | |
336 | ||
c27a02cd YP |
337 | static int mlx4_en_get_sset_count(struct net_device *dev, int sset) |
338 | { | |
339 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
6fcd2735 EBE |
340 | struct bitmap_iterator it; |
341 | ||
3da8a36c | 342 | bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); |
c27a02cd | 343 | |
e7c1c2c4 YP |
344 | switch (sset) { |
345 | case ETH_SS_STATS: | |
6fcd2735 | 346 | return bitmap_iterator_count(&it) + |
67f8b1dc | 347 | (priv->tx_ring_num[TX] * 2) + |
15fca2c8 | 348 | (priv->rx_ring_num * (3 + NUM_XDP_STATS)); |
e7c1c2c4 | 349 | case ETH_SS_TEST: |
ccf86321 OG |
350 | return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags |
351 | & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2; | |
0fef9d03 AV |
352 | case ETH_SS_PRIV_FLAGS: |
353 | return ARRAY_SIZE(mlx4_en_priv_flags); | |
e7c1c2c4 | 354 | default: |
c27a02cd | 355 | return -EOPNOTSUPP; |
e7c1c2c4 | 356 | } |
c27a02cd YP |
357 | } |
358 | ||
359 | static void mlx4_en_get_ethtool_stats(struct net_device *dev, | |
360 | struct ethtool_stats *stats, uint64_t *data) | |
361 | { | |
362 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
363 | int index = 0; | |
6fcd2735 EBE |
364 | int i; |
365 | struct bitmap_iterator it; | |
366 | ||
3da8a36c | 367 | bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); |
c27a02cd YP |
368 | |
369 | spin_lock_bh(&priv->stats_lock); | |
370 | ||
40931b85 ED |
371 | mlx4_en_fold_software_stats(dev); |
372 | ||
6fcd2735 EBE |
373 | for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it)) |
374 | if (bitmap_iterator_test(&it)) | |
f73a6f43 | 375 | data[index++] = ((unsigned long *)&dev->stats)[i]; |
6fcd2735 EBE |
376 | |
377 | for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it)) | |
378 | if (bitmap_iterator_test(&it)) | |
379 | data[index++] = ((unsigned long *)&priv->port_stats)[i]; | |
380 | ||
b42de4d0 EBE |
381 | for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it)) |
382 | if (bitmap_iterator_test(&it)) | |
383 | data[index++] = | |
384 | ((unsigned long *)&priv->pf_stats)[i]; | |
385 | ||
0b131561 MB |
386 | for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX; |
387 | i++, bitmap_iterator_inc(&it)) | |
388 | if (bitmap_iterator_test(&it)) | |
389 | data[index++] = | |
390 | ((u64 *)&priv->rx_priority_flowstats)[i]; | |
391 | ||
392 | for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it)) | |
393 | if (bitmap_iterator_test(&it)) | |
394 | data[index++] = ((u64 *)&priv->rx_flowstats)[i]; | |
395 | ||
396 | for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX; | |
397 | i++, bitmap_iterator_inc(&it)) | |
398 | if (bitmap_iterator_test(&it)) | |
399 | data[index++] = | |
400 | ((u64 *)&priv->tx_priority_flowstats)[i]; | |
401 | ||
402 | for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it)) | |
403 | if (bitmap_iterator_test(&it)) | |
404 | data[index++] = ((u64 *)&priv->tx_flowstats)[i]; | |
405 | ||
6fcd2735 EBE |
406 | for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it)) |
407 | if (bitmap_iterator_test(&it)) | |
408 | data[index++] = ((unsigned long *)&priv->pkstats)[i]; | |
409 | ||
15fca2c8 TT |
410 | for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it)) |
411 | if (bitmap_iterator_test(&it)) | |
412 | data[index++] = ((unsigned long *)&priv->xdp_stats)[i]; | |
413 | ||
67f8b1dc TT |
414 | for (i = 0; i < priv->tx_ring_num[TX]; i++) { |
415 | data[index++] = priv->tx_ring[TX][i]->packets; | |
416 | data[index++] = priv->tx_ring[TX][i]->bytes; | |
c27a02cd YP |
417 | } |
418 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
419 | data[index++] = priv->rx_ring[i]->packets; |
420 | data[index++] = priv->rx_ring[i]->bytes; | |
d21ed3a3 | 421 | data[index++] = priv->rx_ring[i]->dropped; |
15fca2c8 TT |
422 | data[index++] = priv->rx_ring[i]->xdp_drop; |
423 | data[index++] = priv->rx_ring[i]->xdp_tx; | |
424 | data[index++] = priv->rx_ring[i]->xdp_tx_full; | |
c27a02cd | 425 | } |
c27a02cd YP |
426 | spin_unlock_bh(&priv->stats_lock); |
427 | ||
428 | } | |
429 | ||
e7c1c2c4 YP |
430 | static void mlx4_en_self_test(struct net_device *dev, |
431 | struct ethtool_test *etest, u64 *buf) | |
432 | { | |
433 | mlx4_en_ex_selftest(dev, &etest->flags, buf); | |
434 | } | |
435 | ||
c27a02cd YP |
436 | static void mlx4_en_get_strings(struct net_device *dev, |
437 | uint32_t stringset, uint8_t *data) | |
438 | { | |
439 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
440 | int index = 0; | |
6fcd2735 EBE |
441 | int i, strings = 0; |
442 | struct bitmap_iterator it; | |
443 | ||
3da8a36c | 444 | bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS); |
c27a02cd | 445 | |
e7c1c2c4 YP |
446 | switch (stringset) { |
447 | case ETH_SS_TEST: | |
448 | for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++) | |
449 | strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); | |
ccf86321 | 450 | if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) |
e7c1c2c4 YP |
451 | for (; i < MLX4_EN_NUM_SELF_TEST; i++) |
452 | strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]); | |
453 | break; | |
454 | ||
455 | case ETH_SS_STATS: | |
456 | /* Add main counters */ | |
6fcd2735 EBE |
457 | for (i = 0; i < NUM_MAIN_STATS; i++, strings++, |
458 | bitmap_iterator_inc(&it)) | |
459 | if (bitmap_iterator_test(&it)) | |
93ece0c1 | 460 | strcpy(data + (index++) * ETH_GSTRING_LEN, |
6fcd2735 EBE |
461 | main_strings[strings]); |
462 | ||
463 | for (i = 0; i < NUM_PORT_STATS; i++, strings++, | |
464 | bitmap_iterator_inc(&it)) | |
465 | if (bitmap_iterator_test(&it)) | |
93ece0c1 | 466 | strcpy(data + (index++) * ETH_GSTRING_LEN, |
6fcd2735 | 467 | main_strings[strings]); |
b42de4d0 EBE |
468 | |
469 | for (i = 0; i < NUM_PF_STATS; i++, strings++, | |
470 | bitmap_iterator_inc(&it)) | |
471 | if (bitmap_iterator_test(&it)) | |
472 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
473 | main_strings[strings]); | |
6fcd2735 | 474 | |
0b131561 MB |
475 | for (i = 0; i < NUM_FLOW_STATS; i++, strings++, |
476 | bitmap_iterator_inc(&it)) | |
477 | if (bitmap_iterator_test(&it)) | |
478 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
479 | main_strings[strings]); | |
480 | ||
6fcd2735 EBE |
481 | for (i = 0; i < NUM_PKT_STATS; i++, strings++, |
482 | bitmap_iterator_inc(&it)) | |
483 | if (bitmap_iterator_test(&it)) | |
93ece0c1 | 484 | strcpy(data + (index++) * ETH_GSTRING_LEN, |
6fcd2735 EBE |
485 | main_strings[strings]); |
486 | ||
15fca2c8 TT |
487 | for (i = 0; i < NUM_XDP_STATS; i++, strings++, |
488 | bitmap_iterator_inc(&it)) | |
489 | if (bitmap_iterator_test(&it)) | |
490 | strcpy(data + (index++) * ETH_GSTRING_LEN, | |
491 | main_strings[strings]); | |
492 | ||
67f8b1dc | 493 | for (i = 0; i < priv->tx_ring_num[TX]; i++) { |
e7c1c2c4 YP |
494 | sprintf(data + (index++) * ETH_GSTRING_LEN, |
495 | "tx%d_packets", i); | |
496 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
497 | "tx%d_bytes", i); | |
498 | } | |
499 | for (i = 0; i < priv->rx_ring_num; i++) { | |
500 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
501 | "rx%d_packets", i); | |
502 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
503 | "rx%d_bytes", i); | |
d21ed3a3 EBE |
504 | sprintf(data + (index++) * ETH_GSTRING_LEN, |
505 | "rx%d_dropped", i); | |
15fca2c8 TT |
506 | sprintf(data + (index++) * ETH_GSTRING_LEN, |
507 | "rx%d_xdp_drop", i); | |
508 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
509 | "rx%d_xdp_tx", i); | |
510 | sprintf(data + (index++) * ETH_GSTRING_LEN, | |
511 | "rx%d_xdp_tx_full", i); | |
e7c1c2c4 | 512 | } |
e7c1c2c4 | 513 | break; |
0fef9d03 AV |
514 | case ETH_SS_PRIV_FLAGS: |
515 | for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++) | |
516 | strcpy(data + i * ETH_GSTRING_LEN, | |
517 | mlx4_en_priv_flags[i]); | |
518 | break; | |
519 | ||
e7c1c2c4 | 520 | } |
c27a02cd YP |
521 | } |
522 | ||
2c762679 SM |
523 | static u32 mlx4_en_autoneg_get(struct net_device *dev) |
524 | { | |
525 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
526 | struct mlx4_en_dev *mdev = priv->mdev; | |
527 | u32 autoneg = AUTONEG_DISABLE; | |
528 | ||
529 | if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) && | |
530 | (priv->port_state.flags & MLX4_EN_PORT_ANE)) | |
531 | autoneg = AUTONEG_ENABLE; | |
532 | ||
533 | return autoneg; | |
534 | } | |
535 | ||
3d8f7cc7 DD |
536 | static void ptys2ethtool_update_supported_port(unsigned long *mask, |
537 | struct mlx4_ptys_reg *ptys_reg) | |
2c762679 SM |
538 | { |
539 | u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); | |
540 | ||
541 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) | |
542 | | MLX4_PROT_MASK(MLX4_1000BASE_T) | |
543 | | MLX4_PROT_MASK(MLX4_100BASE_TX))) { | |
3d8f7cc7 DD |
544 | __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); |
545 | } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) | |
2c762679 SM |
546 | | MLX4_PROT_MASK(MLX4_10GBASE_SR) |
547 | | MLX4_PROT_MASK(MLX4_56GBASE_SR4) | |
548 | | MLX4_PROT_MASK(MLX4_40GBASE_CR4) | |
549 | | MLX4_PROT_MASK(MLX4_40GBASE_SR4) | |
550 | | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { | |
3d8f7cc7 DD |
551 | __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask); |
552 | } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) | |
2c762679 SM |
553 | | MLX4_PROT_MASK(MLX4_40GBASE_KR4) |
554 | | MLX4_PROT_MASK(MLX4_20GBASE_KR2) | |
555 | | MLX4_PROT_MASK(MLX4_10GBASE_KR) | |
556 | | MLX4_PROT_MASK(MLX4_10GBASE_KX4) | |
557 | | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { | |
3d8f7cc7 | 558 | __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask); |
2c762679 | 559 | } |
2c762679 SM |
560 | } |
561 | ||
562 | static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg) | |
563 | { | |
564 | u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper); | |
565 | ||
566 | if (!eth_proto) /* link down */ | |
567 | eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap); | |
568 | ||
569 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T) | |
570 | | MLX4_PROT_MASK(MLX4_1000BASE_T) | |
571 | | MLX4_PROT_MASK(MLX4_100BASE_TX))) { | |
572 | return PORT_TP; | |
573 | } | |
574 | ||
575 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR) | |
576 | | MLX4_PROT_MASK(MLX4_56GBASE_SR4) | |
577 | | MLX4_PROT_MASK(MLX4_40GBASE_SR4) | |
578 | | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) { | |
579 | return PORT_FIBRE; | |
580 | } | |
581 | ||
582 | if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR) | |
583 | | MLX4_PROT_MASK(MLX4_56GBASE_CR4) | |
584 | | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) { | |
585 | return PORT_DA; | |
586 | } | |
587 | ||
588 | if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4) | |
589 | | MLX4_PROT_MASK(MLX4_40GBASE_KR4) | |
590 | | MLX4_PROT_MASK(MLX4_20GBASE_KR2) | |
591 | | MLX4_PROT_MASK(MLX4_10GBASE_KR) | |
592 | | MLX4_PROT_MASK(MLX4_10GBASE_KX4) | |
593 | | MLX4_PROT_MASK(MLX4_1000BASE_KX))) { | |
594 | return PORT_NONE; | |
595 | } | |
596 | return PORT_OTHER; | |
597 | } | |
598 | ||
599 | #define MLX4_LINK_MODES_SZ \ | |
600 | (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8) | |
601 | ||
602 | enum ethtool_report { | |
603 | SUPPORTED = 0, | |
604 | ADVERTISED = 1, | |
2c762679 SM |
605 | }; |
606 | ||
3d8f7cc7 DD |
607 | struct ptys2ethtool_config { |
608 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); | |
609 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); | |
610 | u32 speed; | |
611 | }; | |
612 | ||
613 | static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg, | |
614 | enum ethtool_report report) | |
615 | { | |
616 | switch (report) { | |
617 | case SUPPORTED: | |
618 | return cfg->supported; | |
619 | case ADVERTISED: | |
620 | return cfg->advertised; | |
621 | } | |
622 | return NULL; | |
623 | } | |
624 | ||
625 | #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \ | |
626 | ({ \ | |
627 | struct ptys2ethtool_config *cfg; \ | |
628 | const unsigned int modes[] = { __VA_ARGS__ }; \ | |
629 | unsigned int i; \ | |
630 | cfg = &ptys2ethtool_map[reg_]; \ | |
631 | cfg->speed = speed_; \ | |
632 | bitmap_zero(cfg->supported, \ | |
633 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
634 | bitmap_zero(cfg->advertised, \ | |
635 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
636 | for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ | |
637 | __set_bit(modes[i], cfg->supported); \ | |
638 | __set_bit(modes[i], cfg->advertised); \ | |
639 | } \ | |
640 | }) | |
641 | ||
2c762679 | 642 | /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */ |
3d8f7cc7 DD |
643 | static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ]; |
644 | ||
645 | void __init mlx4_en_init_ptys2ethtool_map(void) | |
646 | { | |
647 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100, | |
648 | ETHTOOL_LINK_MODE_100baseT_Full_BIT); | |
649 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000, | |
650 | ETHTOOL_LINK_MODE_1000baseT_Full_BIT); | |
651 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000, | |
652 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); | |
653 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000, | |
654 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); | |
655 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000, | |
656 | ETHTOOL_LINK_MODE_10000baseT_Full_BIT); | |
657 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000, | |
658 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); | |
659 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000, | |
660 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); | |
661 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000, | |
662 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
663 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000, | |
664 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
665 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000, | |
666 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
667 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000, | |
668 | ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT, | |
669 | ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); | |
670 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000, | |
671 | ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); | |
672 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000, | |
673 | ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); | |
674 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000, | |
675 | ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); | |
676 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000, | |
677 | ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); | |
678 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000, | |
679 | ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT); | |
680 | MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000, | |
681 | ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT); | |
2c762679 SM |
682 | }; |
683 | ||
3d8f7cc7 DD |
684 | static void ptys2ethtool_update_link_modes(unsigned long *link_modes, |
685 | u32 eth_proto, | |
686 | enum ethtool_report report) | |
2c762679 SM |
687 | { |
688 | int i; | |
2c762679 SM |
689 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { |
690 | if (eth_proto & MLX4_PROT_MASK(i)) | |
3d8f7cc7 DD |
691 | bitmap_or(link_modes, link_modes, |
692 | ptys2ethtool_link_mode(&ptys2ethtool_map[i], | |
693 | report), | |
694 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
2c762679 | 695 | } |
2c762679 SM |
696 | } |
697 | ||
3d8f7cc7 DD |
698 | static u32 ethtool2ptys_link_modes(const unsigned long *link_modes, |
699 | enum ethtool_report report) | |
d48b3ab4 SM |
700 | { |
701 | int i; | |
702 | u32 ptys_modes = 0; | |
703 | ||
704 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
3d8f7cc7 DD |
705 | if (bitmap_intersects( |
706 | ptys2ethtool_link_mode(&ptys2ethtool_map[i], | |
707 | report), | |
708 | link_modes, | |
709 | __ETHTOOL_LINK_MODE_MASK_NBITS)) | |
d48b3ab4 SM |
710 | ptys_modes |= 1 << i; |
711 | } | |
712 | return ptys_modes; | |
713 | } | |
714 | ||
715 | /* Convert actual speed (SPEED_XXX) to ptys link modes */ | |
716 | static u32 speed2ptys_link_modes(u32 speed) | |
717 | { | |
718 | int i; | |
719 | u32 ptys_modes = 0; | |
720 | ||
721 | for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { | |
3d8f7cc7 | 722 | if (ptys2ethtool_map[i].speed == speed) |
d48b3ab4 SM |
723 | ptys_modes |= 1 << i; |
724 | } | |
725 | return ptys_modes; | |
726 | } | |
727 | ||
3d8f7cc7 DD |
728 | static int |
729 | ethtool_get_ptys_link_ksettings(struct net_device *dev, | |
730 | struct ethtool_link_ksettings *link_ksettings) | |
2c762679 SM |
731 | { |
732 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
733 | struct mlx4_ptys_reg ptys_reg; | |
734 | u32 eth_proto; | |
735 | int ret; | |
736 | ||
737 | memset(&ptys_reg, 0, sizeof(ptys_reg)); | |
738 | ptys_reg.local_port = priv->port; | |
739 | ptys_reg.proto_mask = MLX4_PTYS_EN; | |
740 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, | |
741 | MLX4_ACCESS_REG_QUERY, &ptys_reg); | |
742 | if (ret) { | |
743 | en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)", | |
744 | ret); | |
745 | return ret; | |
746 | } | |
747 | en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n", | |
748 | ptys_reg.proto_mask); | |
749 | en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n", | |
750 | be32_to_cpu(ptys_reg.eth_proto_cap)); | |
751 | en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n", | |
752 | be32_to_cpu(ptys_reg.eth_proto_admin)); | |
753 | en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n", | |
754 | be32_to_cpu(ptys_reg.eth_proto_oper)); | |
755 | en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n", | |
756 | be32_to_cpu(ptys_reg.eth_proto_lp_adv)); | |
757 | ||
3d8f7cc7 DD |
758 | /* reset supported/advertising masks */ |
759 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); | |
760 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); | |
2c762679 | 761 | |
3d8f7cc7 DD |
762 | ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported, |
763 | &ptys_reg); | |
2c762679 SM |
764 | |
765 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap); | |
3d8f7cc7 DD |
766 | ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported, |
767 | eth_proto, SUPPORTED); | |
2c762679 SM |
768 | |
769 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin); | |
3d8f7cc7 DD |
770 | ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising, |
771 | eth_proto, ADVERTISED); | |
2c762679 | 772 | |
3d8f7cc7 DD |
773 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, |
774 | Pause); | |
775 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
776 | Asym_Pause); | |
2c762679 | 777 | |
3d8f7cc7 DD |
778 | if (priv->prof->tx_pause) |
779 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
780 | advertising, Pause); | |
781 | if (priv->prof->tx_pause ^ priv->prof->rx_pause) | |
782 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
783 | advertising, Asym_Pause); | |
2c762679 | 784 | |
3d8f7cc7 | 785 | link_ksettings->base.port = ptys_get_active_port(&ptys_reg); |
2c762679 SM |
786 | |
787 | if (mlx4_en_autoneg_get(dev)) { | |
3d8f7cc7 DD |
788 | ethtool_link_ksettings_add_link_mode(link_ksettings, |
789 | supported, Autoneg); | |
790 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
791 | advertising, Autoneg); | |
2c762679 SM |
792 | } |
793 | ||
3d8f7cc7 DD |
794 | link_ksettings->base.autoneg |
795 | = (priv->port_state.flags & MLX4_EN_PORT_ANC) ? | |
2c762679 SM |
796 | AUTONEG_ENABLE : AUTONEG_DISABLE; |
797 | ||
798 | eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv); | |
2c762679 | 799 | |
3d8f7cc7 DD |
800 | ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising); |
801 | ptys2ethtool_update_link_modes( | |
802 | link_ksettings->link_modes.lp_advertising, | |
803 | eth_proto, ADVERTISED); | |
804 | if (priv->port_state.flags & MLX4_EN_PORT_ANC) | |
805 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
806 | lp_advertising, Autoneg); | |
2c762679 | 807 | |
3d8f7cc7 DD |
808 | link_ksettings->base.phy_address = 0; |
809 | link_ksettings->base.mdio_support = 0; | |
810 | link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID; | |
811 | link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
2c762679 SM |
812 | |
813 | return ret; | |
814 | } | |
815 | ||
3d8f7cc7 DD |
816 | static void |
817 | ethtool_get_default_link_ksettings( | |
818 | struct net_device *dev, struct ethtool_link_ksettings *link_ksettings) | |
c27a02cd | 819 | { |
7699517d YP |
820 | struct mlx4_en_priv *priv = netdev_priv(dev); |
821 | int trans_type; | |
822 | ||
3d8f7cc7 DD |
823 | link_ksettings->base.autoneg = AUTONEG_DISABLE; |
824 | ||
825 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); | |
826 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
827 | 10000baseT_Full); | |
7699517d | 828 | |
3d8f7cc7 DD |
829 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); |
830 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, | |
831 | 10000baseT_Full); | |
832 | ||
833 | trans_type = priv->port_state.transceiver; | |
7699517d | 834 | if (trans_type > 0 && trans_type <= 0xC) { |
3d8f7cc7 DD |
835 | link_ksettings->base.port = PORT_FIBRE; |
836 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
837 | supported, FIBRE); | |
838 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
839 | advertising, FIBRE); | |
7699517d | 840 | } else if (trans_type == 0x80 || trans_type == 0) { |
3d8f7cc7 DD |
841 | link_ksettings->base.port = PORT_TP; |
842 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
843 | supported, TP); | |
844 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
845 | advertising, TP); | |
7699517d | 846 | } else { |
3d8f7cc7 | 847 | link_ksettings->base.port = -1; |
7699517d | 848 | } |
2c762679 SM |
849 | } |
850 | ||
3d8f7cc7 DD |
851 | static int |
852 | mlx4_en_get_link_ksettings(struct net_device *dev, | |
853 | struct ethtool_link_ksettings *link_ksettings) | |
2c762679 SM |
854 | { |
855 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
856 | int ret = -EINVAL; | |
857 | ||
858 | if (mlx4_en_QUERY_PORT(priv->mdev, priv->port)) | |
859 | return -ENOMEM; | |
860 | ||
861 | en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n", | |
862 | priv->port_state.flags & MLX4_EN_PORT_ANC, | |
863 | priv->port_state.flags & MLX4_EN_PORT_ANE); | |
864 | ||
865 | if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) | |
3d8f7cc7 | 866 | ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings); |
2c762679 | 867 | if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */ |
3d8f7cc7 | 868 | ethtool_get_default_link_ksettings(dev, link_ksettings); |
2c762679 SM |
869 | |
870 | if (netif_carrier_ok(dev)) { | |
3d8f7cc7 DD |
871 | link_ksettings->base.speed = priv->port_state.link_speed; |
872 | link_ksettings->base.duplex = DUPLEX_FULL; | |
2c762679 | 873 | } else { |
3d8f7cc7 DD |
874 | link_ksettings->base.speed = SPEED_UNKNOWN; |
875 | link_ksettings->base.duplex = DUPLEX_UNKNOWN; | |
2c762679 | 876 | } |
c27a02cd YP |
877 | return 0; |
878 | } | |
879 | ||
d48b3ab4 SM |
880 | /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */ |
881 | static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed, | |
882 | __be32 proto_cap) | |
883 | { | |
884 | __be32 proto_admin = 0; | |
885 | ||
886 | if (!speed) { /* Speed = 0 ==> Reset Link modes */ | |
887 | proto_admin = proto_cap; | |
888 | en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n", | |
889 | be32_to_cpu(proto_cap)); | |
890 | } else { | |
891 | u32 ptys_link_modes = speed2ptys_link_modes(speed); | |
892 | ||
893 | proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap; | |
894 | en_info(priv, "Setting Speed to %d\n", speed); | |
895 | } | |
896 | return proto_admin; | |
897 | } | |
898 | ||
3d8f7cc7 DD |
899 | static int |
900 | mlx4_en_set_link_ksettings(struct net_device *dev, | |
901 | const struct ethtool_link_ksettings *link_ksettings) | |
c27a02cd | 902 | { |
d48b3ab4 SM |
903 | struct mlx4_en_priv *priv = netdev_priv(dev); |
904 | struct mlx4_ptys_reg ptys_reg; | |
905 | __be32 proto_admin; | |
297e1cf2 | 906 | u8 cur_autoneg; |
d48b3ab4 SM |
907 | int ret; |
908 | ||
3d8f7cc7 DD |
909 | u32 ptys_adv = ethtool2ptys_link_modes( |
910 | link_ksettings->link_modes.advertising, ADVERTISED); | |
911 | const int speed = link_ksettings->base.speed; | |
d48b3ab4 | 912 | |
3d8f7cc7 DD |
913 | en_dbg(DRV, priv, |
914 | "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n", | |
915 | speed, __ETHTOOL_LINK_MODE_MASK_NBITS, | |
916 | link_ksettings->link_modes.advertising, | |
917 | link_ksettings->base.autoneg, | |
918 | link_ksettings->base.duplex); | |
d48b3ab4 | 919 | |
3d8f7cc7 DD |
920 | if (!(priv->mdev->dev->caps.flags2 & |
921 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) || | |
922 | (link_ksettings->base.duplex == DUPLEX_HALF)) | |
c27a02cd YP |
923 | return -EINVAL; |
924 | ||
d48b3ab4 SM |
925 | memset(&ptys_reg, 0, sizeof(ptys_reg)); |
926 | ptys_reg.local_port = priv->port; | |
927 | ptys_reg.proto_mask = MLX4_PTYS_EN; | |
928 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, | |
929 | MLX4_ACCESS_REG_QUERY, &ptys_reg); | |
930 | if (ret) { | |
931 | en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n", | |
932 | ret); | |
933 | return 0; | |
934 | } | |
935 | ||
297e1cf2 AL |
936 | cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ? |
937 | AUTONEG_DISABLE : AUTONEG_ENABLE; | |
938 | ||
939 | if (link_ksettings->base.autoneg == AUTONEG_DISABLE) { | |
940 | proto_admin = speed_set_ptys_admin(priv, speed, | |
941 | ptys_reg.eth_proto_cap); | |
942 | if ((be32_to_cpu(proto_admin) & | |
943 | (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) | | |
944 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) && | |
945 | (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP)) | |
946 | ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN; | |
947 | } else { | |
948 | proto_admin = cpu_to_be32(ptys_adv); | |
949 | ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN; | |
950 | } | |
d48b3ab4 SM |
951 | |
952 | proto_admin &= ptys_reg.eth_proto_cap; | |
d48b3ab4 SM |
953 | if (!proto_admin) { |
954 | en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n"); | |
955 | return -EINVAL; /* nothing to change due to bad input */ | |
956 | } | |
957 | ||
297e1cf2 AL |
958 | if ((proto_admin == ptys_reg.eth_proto_admin) && |
959 | ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) && | |
960 | (link_ksettings->base.autoneg == cur_autoneg))) | |
5a228c03 SM |
961 | return 0; /* Nothing to change */ |
962 | ||
d48b3ab4 SM |
963 | en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n", |
964 | be32_to_cpu(proto_admin)); | |
965 | ||
966 | ptys_reg.eth_proto_admin = proto_admin; | |
967 | ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE, | |
968 | &ptys_reg); | |
969 | if (ret) { | |
970 | en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)", | |
971 | be32_to_cpu(ptys_reg.eth_proto_admin), ret); | |
972 | return ret; | |
973 | } | |
974 | ||
d48b3ab4 SM |
975 | mutex_lock(&priv->mdev->state_lock); |
976 | if (priv->port_up) { | |
5a228c03 | 977 | en_warn(priv, "Port link mode changed, restarting port...\n"); |
d48b3ab4 SM |
978 | mlx4_en_stop_port(dev, 1); |
979 | if (mlx4_en_start_port(dev)) | |
980 | en_err(priv, "Failed restarting port %d\n", priv->port); | |
981 | } | |
982 | mutex_unlock(&priv->mdev->state_lock); | |
c27a02cd YP |
983 | return 0; |
984 | } | |
985 | ||
986 | static int mlx4_en_get_coalesce(struct net_device *dev, | |
987 | struct ethtool_coalesce *coal) | |
988 | { | |
989 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
990 | ||
a19a848a YP |
991 | coal->tx_coalesce_usecs = priv->tx_usecs; |
992 | coal->tx_max_coalesced_frames = priv->tx_frames; | |
fbc6daf1 AV |
993 | coal->tx_max_coalesced_frames_irq = priv->tx_work_limit; |
994 | ||
c27a02cd YP |
995 | coal->rx_coalesce_usecs = priv->rx_usecs; |
996 | coal->rx_max_coalesced_frames = priv->rx_frames; | |
997 | ||
998 | coal->pkt_rate_low = priv->pkt_rate_low; | |
999 | coal->rx_coalesce_usecs_low = priv->rx_usecs_low; | |
1000 | coal->pkt_rate_high = priv->pkt_rate_high; | |
1001 | coal->rx_coalesce_usecs_high = priv->rx_usecs_high; | |
1002 | coal->rate_sample_interval = priv->sample_interval; | |
1003 | coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal; | |
fbc6daf1 | 1004 | |
c27a02cd YP |
1005 | return 0; |
1006 | } | |
1007 | ||
1008 | static int mlx4_en_set_coalesce(struct net_device *dev, | |
1009 | struct ethtool_coalesce *coal) | |
1010 | { | |
1011 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 1012 | |
fbc6daf1 AV |
1013 | if (!coal->tx_max_coalesced_frames_irq) |
1014 | return -EINVAL; | |
1015 | ||
c27a02cd YP |
1016 | priv->rx_frames = (coal->rx_max_coalesced_frames == |
1017 | MLX4_EN_AUTO_CONF) ? | |
3db36fb2 | 1018 | MLX4_EN_RX_COAL_TARGET : |
c27a02cd YP |
1019 | coal->rx_max_coalesced_frames; |
1020 | priv->rx_usecs = (coal->rx_coalesce_usecs == | |
1021 | MLX4_EN_AUTO_CONF) ? | |
1022 | MLX4_EN_RX_COAL_TIME : | |
1023 | coal->rx_coalesce_usecs; | |
1024 | ||
a19a848a YP |
1025 | /* Setting TX coalescing parameters */ |
1026 | if (coal->tx_coalesce_usecs != priv->tx_usecs || | |
1027 | coal->tx_max_coalesced_frames != priv->tx_frames) { | |
1028 | priv->tx_usecs = coal->tx_coalesce_usecs; | |
1029 | priv->tx_frames = coal->tx_max_coalesced_frames; | |
a19a848a YP |
1030 | } |
1031 | ||
c27a02cd YP |
1032 | /* Set adaptive coalescing params */ |
1033 | priv->pkt_rate_low = coal->pkt_rate_low; | |
1034 | priv->rx_usecs_low = coal->rx_coalesce_usecs_low; | |
1035 | priv->pkt_rate_high = coal->pkt_rate_high; | |
1036 | priv->rx_usecs_high = coal->rx_coalesce_usecs_high; | |
1037 | priv->sample_interval = coal->rate_sample_interval; | |
1038 | priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce; | |
fbc6daf1 | 1039 | priv->tx_work_limit = coal->tx_max_coalesced_frames_irq; |
c27a02cd | 1040 | |
79c54b6b | 1041 | return mlx4_en_moderation_update(priv); |
c27a02cd YP |
1042 | } |
1043 | ||
1044 | static int mlx4_en_set_pauseparam(struct net_device *dev, | |
1045 | struct ethtool_pauseparam *pause) | |
1046 | { | |
1047 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1048 | struct mlx4_en_dev *mdev = priv->mdev; | |
1049 | int err; | |
1050 | ||
278d436a IV |
1051 | if (pause->autoneg) |
1052 | return -EINVAL; | |
1053 | ||
d53b93f2 YP |
1054 | priv->prof->tx_pause = pause->tx_pause != 0; |
1055 | priv->prof->rx_pause = pause->rx_pause != 0; | |
c27a02cd YP |
1056 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, |
1057 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
1058 | priv->prof->tx_pause, |
1059 | priv->prof->tx_ppp, | |
1060 | priv->prof->rx_pause, | |
1061 | priv->prof->rx_ppp); | |
c27a02cd | 1062 | if (err) |
453a6082 | 1063 | en_err(priv, "Failed setting pause params\n"); |
0b131561 MB |
1064 | else |
1065 | mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap, | |
1066 | priv->prof->rx_ppp, | |
1067 | priv->prof->rx_pause, | |
1068 | priv->prof->tx_ppp, | |
1069 | priv->prof->tx_pause); | |
c27a02cd YP |
1070 | |
1071 | return err; | |
1072 | } | |
1073 | ||
1074 | static void mlx4_en_get_pauseparam(struct net_device *dev, | |
1075 | struct ethtool_pauseparam *pause) | |
1076 | { | |
1077 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd | 1078 | |
d53b93f2 YP |
1079 | pause->tx_pause = priv->prof->tx_pause; |
1080 | pause->rx_pause = priv->prof->rx_pause; | |
c27a02cd YP |
1081 | } |
1082 | ||
18cc42a3 YP |
1083 | static int mlx4_en_set_ringparam(struct net_device *dev, |
1084 | struct ethtool_ringparam *param) | |
1085 | { | |
1086 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1087 | struct mlx4_en_dev *mdev = priv->mdev; | |
ec25bc04 EE |
1088 | struct mlx4_en_port_profile new_prof; |
1089 | struct mlx4_en_priv *tmp; | |
18cc42a3 YP |
1090 | u32 rx_size, tx_size; |
1091 | int port_up = 0; | |
1092 | int err = 0; | |
1093 | ||
1094 | if (param->rx_jumbo_pending || param->rx_mini_pending) | |
1095 | return -EINVAL; | |
1096 | ||
1097 | rx_size = roundup_pow_of_two(param->rx_pending); | |
1098 | rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE); | |
bd531e36 | 1099 | rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE); |
18cc42a3 YP |
1100 | tx_size = roundup_pow_of_two(param->tx_pending); |
1101 | tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE); | |
bd531e36 | 1102 | tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE); |
18cc42a3 | 1103 | |
41d942d5 EE |
1104 | if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size : |
1105 | priv->rx_ring[0]->size) && | |
67f8b1dc | 1106 | tx_size == priv->tx_ring[TX][0]->size) |
18cc42a3 YP |
1107 | return 0; |
1108 | ||
ec25bc04 EE |
1109 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
1110 | if (!tmp) | |
1111 | return -ENOMEM; | |
1112 | ||
18cc42a3 | 1113 | mutex_lock(&mdev->state_lock); |
ec25bc04 EE |
1114 | memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); |
1115 | new_prof.tx_ring_size = tx_size; | |
1116 | new_prof.rx_ring_size = rx_size; | |
770f8225 | 1117 | err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true); |
ec25bc04 EE |
1118 | if (err) |
1119 | goto out; | |
1120 | ||
18cc42a3 YP |
1121 | if (priv->port_up) { |
1122 | port_up = 1; | |
3484aac1 | 1123 | mlx4_en_stop_port(dev, 1); |
18cc42a3 YP |
1124 | } |
1125 | ||
ec25bc04 | 1126 | mlx4_en_safe_replace_resources(priv, tmp); |
18cc42a3 | 1127 | |
18cc42a3 YP |
1128 | if (port_up) { |
1129 | err = mlx4_en_start_port(dev); | |
1130 | if (err) | |
453a6082 | 1131 | en_err(priv, "Failed starting port\n"); |
18cc42a3 YP |
1132 | } |
1133 | ||
79c54b6b | 1134 | err = mlx4_en_moderation_update(priv); |
18cc42a3 | 1135 | out: |
ec25bc04 | 1136 | kfree(tmp); |
18cc42a3 YP |
1137 | mutex_unlock(&mdev->state_lock); |
1138 | return err; | |
1139 | } | |
1140 | ||
c27a02cd YP |
1141 | static void mlx4_en_get_ringparam(struct net_device *dev, |
1142 | struct ethtool_ringparam *param) | |
1143 | { | |
1144 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
1145 | |
1146 | memset(param, 0, sizeof(*param)); | |
bd531e36 YP |
1147 | param->rx_max_pending = MLX4_EN_MAX_RX_SIZE; |
1148 | param->tx_max_pending = MLX4_EN_MAX_TX_SIZE; | |
bc081cec | 1149 | param->rx_pending = priv->port_up ? |
41d942d5 | 1150 | priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size; |
67f8b1dc | 1151 | param->tx_pending = priv->tx_ring[TX][0]->size; |
c27a02cd YP |
1152 | } |
1153 | ||
93d3e367 YP |
1154 | static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev) |
1155 | { | |
1156 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1157 | ||
f7d3c1cb | 1158 | return rounddown_pow_of_two(priv->rx_ring_num); |
93d3e367 YP |
1159 | } |
1160 | ||
b9d1ab7e ED |
1161 | static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev) |
1162 | { | |
1163 | return MLX4_EN_RSS_KEY_SIZE; | |
1164 | } | |
1165 | ||
947cbb0a EP |
1166 | static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc) |
1167 | { | |
1168 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1169 | ||
1170 | /* check if requested function is supported by the device */ | |
b3706909 AV |
1171 | if (hfunc == ETH_RSS_HASH_TOP) { |
1172 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) | |
1173 | return -EINVAL; | |
1174 | if (!(dev->features & NETIF_F_RXHASH)) | |
1175 | en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n"); | |
1176 | return 0; | |
1177 | } else if (hfunc == ETH_RSS_HASH_XOR) { | |
1178 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)) | |
1179 | return -EINVAL; | |
1180 | if (dev->features & NETIF_F_RXHASH) | |
1181 | en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n"); | |
1182 | return 0; | |
1183 | } | |
947cbb0a | 1184 | |
b3706909 | 1185 | return -EINVAL; |
947cbb0a EP |
1186 | } |
1187 | ||
892311f6 EP |
1188 | static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key, |
1189 | u8 *hfunc) | |
93d3e367 YP |
1190 | { |
1191 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
f7d3c1cb ED |
1192 | u32 n = mlx4_en_get_rxfh_indir_size(dev); |
1193 | u32 i, rss_rings; | |
93d3e367 YP |
1194 | int err = 0; |
1195 | ||
f7d3c1cb ED |
1196 | rss_rings = priv->prof->rss_rings ?: n; |
1197 | rss_rings = rounddown_pow_of_two(rss_rings); | |
93d3e367 | 1198 | |
f7d3c1cb | 1199 | for (i = 0; i < n; i++) { |
892311f6 EP |
1200 | if (!ring_index) |
1201 | break; | |
f7d3c1cb | 1202 | ring_index[i] = i % rss_rings; |
93d3e367 | 1203 | } |
b9d1ab7e | 1204 | if (key) |
bd635c35 | 1205 | memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE); |
892311f6 | 1206 | if (hfunc) |
947cbb0a | 1207 | *hfunc = priv->rss_hash_fn; |
93d3e367 YP |
1208 | return err; |
1209 | } | |
1210 | ||
fe62d001 | 1211 | static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index, |
892311f6 | 1212 | const u8 *key, const u8 hfunc) |
93d3e367 YP |
1213 | { |
1214 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
f7d3c1cb | 1215 | u32 n = mlx4_en_get_rxfh_indir_size(dev); |
93d3e367 YP |
1216 | struct mlx4_en_dev *mdev = priv->mdev; |
1217 | int port_up = 0; | |
1218 | int err = 0; | |
1219 | int i; | |
1220 | int rss_rings = 0; | |
1221 | ||
1222 | /* Calculate RSS table size and make sure flows are spread evenly | |
1223 | * between rings | |
1224 | */ | |
f7d3c1cb | 1225 | for (i = 0; i < n; i++) { |
bd635c35 | 1226 | if (!ring_index) |
f7d3c1cb | 1227 | break; |
93d3e367 YP |
1228 | if (i > 0 && !ring_index[i] && !rss_rings) |
1229 | rss_rings = i; | |
1230 | ||
f7d3c1cb | 1231 | if (ring_index[i] != (i % (rss_rings ?: n))) |
93d3e367 YP |
1232 | return -EINVAL; |
1233 | } | |
1234 | ||
1235 | if (!rss_rings) | |
f7d3c1cb | 1236 | rss_rings = n; |
93d3e367 YP |
1237 | |
1238 | /* RSS table size must be an order of 2 */ | |
1239 | if (!is_power_of_2(rss_rings)) | |
1240 | return -EINVAL; | |
1241 | ||
947cbb0a EP |
1242 | if (hfunc != ETH_RSS_HASH_NO_CHANGE) { |
1243 | err = mlx4_en_check_rxfh_func(dev, hfunc); | |
1244 | if (err) | |
1245 | return err; | |
1246 | } | |
1247 | ||
93d3e367 YP |
1248 | mutex_lock(&mdev->state_lock); |
1249 | if (priv->port_up) { | |
1250 | port_up = 1; | |
3484aac1 | 1251 | mlx4_en_stop_port(dev, 1); |
93d3e367 YP |
1252 | } |
1253 | ||
bd635c35 ED |
1254 | if (ring_index) |
1255 | priv->prof->rss_rings = rss_rings; | |
1256 | if (key) | |
1257 | memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE); | |
b3706909 AV |
1258 | if (hfunc != ETH_RSS_HASH_NO_CHANGE) |
1259 | priv->rss_hash_fn = hfunc; | |
947cbb0a | 1260 | |
93d3e367 YP |
1261 | if (port_up) { |
1262 | err = mlx4_en_start_port(dev); | |
1263 | if (err) | |
1264 | en_err(priv, "Failed starting port\n"); | |
1265 | } | |
1266 | ||
1267 | mutex_unlock(&mdev->state_lock); | |
1268 | return err; | |
1269 | } | |
1270 | ||
82067281 HHZ |
1271 | #define all_zeros_or_all_ones(field) \ |
1272 | ((field) == 0 || (field) == (__force typeof(field))-1) | |
1273 | ||
1274 | static int mlx4_en_validate_flow(struct net_device *dev, | |
1275 | struct ethtool_rxnfc *cmd) | |
1276 | { | |
1277 | struct ethtool_usrip4_spec *l3_mask; | |
1278 | struct ethtool_tcpip4_spec *l4_mask; | |
1279 | struct ethhdr *eth_mask; | |
82067281 HHZ |
1280 | |
1281 | if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) | |
1282 | return -EINVAL; | |
1283 | ||
520dfe3a YB |
1284 | if (cmd->fs.flow_type & FLOW_MAC_EXT) { |
1285 | /* dest mac mask must be ff:ff:ff:ff:ff:ff */ | |
1286 | if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest)) | |
1287 | return -EINVAL; | |
1288 | } | |
1289 | ||
1290 | switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { | |
82067281 HHZ |
1291 | case TCP_V4_FLOW: |
1292 | case UDP_V4_FLOW: | |
1293 | if (cmd->fs.m_u.tcp_ip4_spec.tos) | |
1294 | return -EINVAL; | |
1295 | l4_mask = &cmd->fs.m_u.tcp_ip4_spec; | |
1296 | /* don't allow mask which isn't all 0 or 1 */ | |
1297 | if (!all_zeros_or_all_ones(l4_mask->ip4src) || | |
1298 | !all_zeros_or_all_ones(l4_mask->ip4dst) || | |
1299 | !all_zeros_or_all_ones(l4_mask->psrc) || | |
1300 | !all_zeros_or_all_ones(l4_mask->pdst)) | |
1301 | return -EINVAL; | |
1302 | break; | |
1303 | case IP_USER_FLOW: | |
1304 | l3_mask = &cmd->fs.m_u.usr_ip4_spec; | |
1305 | if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto || | |
1306 | cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 || | |
1307 | (!l3_mask->ip4src && !l3_mask->ip4dst) || | |
1308 | !all_zeros_or_all_ones(l3_mask->ip4src) || | |
1309 | !all_zeros_or_all_ones(l3_mask->ip4dst)) | |
1310 | return -EINVAL; | |
1311 | break; | |
1312 | case ETHER_FLOW: | |
1313 | eth_mask = &cmd->fs.m_u.ether_spec; | |
1314 | /* source mac mask must not be set */ | |
c402b947 | 1315 | if (!is_zero_ether_addr(eth_mask->h_source)) |
82067281 HHZ |
1316 | return -EINVAL; |
1317 | ||
1318 | /* dest mac mask must be ff:ff:ff:ff:ff:ff */ | |
c402b947 | 1319 | if (!is_broadcast_ether_addr(eth_mask->h_dest)) |
82067281 HHZ |
1320 | return -EINVAL; |
1321 | ||
1322 | if (!all_zeros_or_all_ones(eth_mask->h_proto)) | |
1323 | return -EINVAL; | |
1324 | break; | |
1325 | default: | |
1326 | return -EINVAL; | |
1327 | } | |
1328 | ||
1329 | if ((cmd->fs.flow_type & FLOW_EXT)) { | |
1330 | if (cmd->fs.m_ext.vlan_etype || | |
8258bd27 HHZ |
1331 | !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == |
1332 | 0 || | |
1333 | (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) == | |
1334 | cpu_to_be16(VLAN_VID_MASK))) | |
82067281 | 1335 | return -EINVAL; |
8258bd27 | 1336 | |
69d7126b HHZ |
1337 | if (cmd->fs.m_ext.vlan_tci) { |
1338 | if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID) | |
1339 | return -EINVAL; | |
8258bd27 | 1340 | |
69d7126b | 1341 | } |
82067281 HHZ |
1342 | } |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
f90a3673 HHZ |
1347 | static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd, |
1348 | struct list_head *rule_list_h, | |
1349 | struct mlx4_spec_list *spec_l2, | |
1350 | unsigned char *mac) | |
1351 | { | |
1352 | int err = 0; | |
1353 | __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16); | |
1354 | ||
1355 | spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH; | |
1356 | memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN); | |
1357 | memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN); | |
1358 | ||
8258bd27 HHZ |
1359 | if ((cmd->fs.flow_type & FLOW_EXT) && |
1360 | (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) { | |
f90a3673 | 1361 | spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci; |
8258bd27 | 1362 | spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK); |
f90a3673 HHZ |
1363 | } |
1364 | ||
1365 | list_add_tail(&spec_l2->list, rule_list_h); | |
1366 | ||
1367 | return err; | |
1368 | } | |
1369 | ||
1370 | static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv, | |
1371 | struct ethtool_rxnfc *cmd, | |
1372 | struct list_head *rule_list_h, | |
1373 | struct mlx4_spec_list *spec_l2, | |
1374 | __be32 ipv4_dst) | |
1375 | { | |
f9d96862 | 1376 | #ifdef CONFIG_INET |
f90a3673 HHZ |
1377 | unsigned char mac[ETH_ALEN]; |
1378 | ||
1379 | if (!ipv4_is_multicast(ipv4_dst)) { | |
6bbb6d99 | 1380 | if (cmd->fs.flow_type & FLOW_MAC_EXT) |
f90a3673 | 1381 | memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN); |
6bbb6d99 YB |
1382 | else |
1383 | memcpy(&mac, priv->dev->dev_addr, ETH_ALEN); | |
f90a3673 HHZ |
1384 | } else { |
1385 | ip_eth_mc_map(ipv4_dst, mac); | |
1386 | } | |
1387 | ||
1388 | return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]); | |
f9d96862 HHZ |
1389 | #else |
1390 | return -EINVAL; | |
1391 | #endif | |
f90a3673 HHZ |
1392 | } |
1393 | ||
82067281 | 1394 | static int add_ip_rule(struct mlx4_en_priv *priv, |
f90a3673 HHZ |
1395 | struct ethtool_rxnfc *cmd, |
1396 | struct list_head *list_h) | |
82067281 | 1397 | { |
377d9739 | 1398 | int err; |
f90a3673 HHZ |
1399 | struct mlx4_spec_list *spec_l2 = NULL; |
1400 | struct mlx4_spec_list *spec_l3 = NULL; | |
82067281 HHZ |
1401 | struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec; |
1402 | ||
f90a3673 HHZ |
1403 | spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); |
1404 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); | |
1405 | if (!spec_l2 || !spec_l3) { | |
377d9739 HHZ |
1406 | err = -ENOMEM; |
1407 | goto free_spec; | |
82067281 HHZ |
1408 | } |
1409 | ||
377d9739 HHZ |
1410 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2, |
1411 | cmd->fs.h_u. | |
1412 | usr_ip4_spec.ip4dst); | |
1413 | if (err) | |
1414 | goto free_spec; | |
82067281 HHZ |
1415 | spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; |
1416 | spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src; | |
1417 | if (l3_mask->ip4src) | |
1418 | spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1419 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst; | |
1420 | if (l3_mask->ip4dst) | |
1421 | spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1422 | list_add_tail(&spec_l3->list, list_h); | |
1423 | ||
1424 | return 0; | |
377d9739 HHZ |
1425 | |
1426 | free_spec: | |
1427 | kfree(spec_l2); | |
1428 | kfree(spec_l3); | |
1429 | return err; | |
82067281 HHZ |
1430 | } |
1431 | ||
1432 | static int add_tcp_udp_rule(struct mlx4_en_priv *priv, | |
1433 | struct ethtool_rxnfc *cmd, | |
1434 | struct list_head *list_h, int proto) | |
1435 | { | |
377d9739 | 1436 | int err; |
f90a3673 HHZ |
1437 | struct mlx4_spec_list *spec_l2 = NULL; |
1438 | struct mlx4_spec_list *spec_l3 = NULL; | |
1439 | struct mlx4_spec_list *spec_l4 = NULL; | |
82067281 HHZ |
1440 | struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec; |
1441 | ||
f90a3673 HHZ |
1442 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); |
1443 | spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL); | |
1444 | spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL); | |
1445 | if (!spec_l2 || !spec_l3 || !spec_l4) { | |
377d9739 HHZ |
1446 | err = -ENOMEM; |
1447 | goto free_spec; | |
82067281 HHZ |
1448 | } |
1449 | ||
1450 | spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4; | |
1451 | ||
1452 | if (proto == TCP_V4_FLOW) { | |
377d9739 HHZ |
1453 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, |
1454 | spec_l2, | |
1455 | cmd->fs.h_u. | |
1456 | tcp_ip4_spec.ip4dst); | |
1457 | if (err) | |
1458 | goto free_spec; | |
82067281 HHZ |
1459 | spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP; |
1460 | spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src; | |
1461 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst; | |
1462 | spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc; | |
1463 | spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst; | |
1464 | } else { | |
377d9739 HHZ |
1465 | err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, |
1466 | spec_l2, | |
1467 | cmd->fs.h_u. | |
1468 | udp_ip4_spec.ip4dst); | |
1469 | if (err) | |
1470 | goto free_spec; | |
82067281 HHZ |
1471 | spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP; |
1472 | spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src; | |
1473 | spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst; | |
1474 | spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc; | |
1475 | spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst; | |
1476 | } | |
1477 | ||
1478 | if (l4_mask->ip4src) | |
1479 | spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1480 | if (l4_mask->ip4dst) | |
1481 | spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK; | |
1482 | ||
1483 | if (l4_mask->psrc) | |
1484 | spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK; | |
1485 | if (l4_mask->pdst) | |
1486 | spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK; | |
1487 | ||
1488 | list_add_tail(&spec_l3->list, list_h); | |
1489 | list_add_tail(&spec_l4->list, list_h); | |
1490 | ||
1491 | return 0; | |
377d9739 HHZ |
1492 | |
1493 | free_spec: | |
1494 | kfree(spec_l2); | |
1495 | kfree(spec_l3); | |
1496 | kfree(spec_l4); | |
1497 | return err; | |
82067281 HHZ |
1498 | } |
1499 | ||
1500 | static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev, | |
1501 | struct ethtool_rxnfc *cmd, | |
1502 | struct list_head *rule_list_h) | |
1503 | { | |
1504 | int err; | |
82067281 | 1505 | struct ethhdr *eth_spec; |
82067281 | 1506 | struct mlx4_spec_list *spec_l2; |
f90a3673 | 1507 | struct mlx4_en_priv *priv = netdev_priv(dev); |
82067281 HHZ |
1508 | |
1509 | err = mlx4_en_validate_flow(dev, cmd); | |
1510 | if (err) | |
1511 | return err; | |
1512 | ||
520dfe3a | 1513 | switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { |
82067281 | 1514 | case ETHER_FLOW: |
f90a3673 HHZ |
1515 | spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL); |
1516 | if (!spec_l2) | |
1517 | return -ENOMEM; | |
1518 | ||
82067281 | 1519 | eth_spec = &cmd->fs.h_u.ether_spec; |
f90a3673 HHZ |
1520 | mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, |
1521 | ð_spec->h_dest[0]); | |
82067281 HHZ |
1522 | spec_l2->eth.ether_type = eth_spec->h_proto; |
1523 | if (eth_spec->h_proto) | |
1524 | spec_l2->eth.ether_type_enable = 1; | |
1525 | break; | |
1526 | case IP_USER_FLOW: | |
1527 | err = add_ip_rule(priv, cmd, rule_list_h); | |
1528 | break; | |
1529 | case TCP_V4_FLOW: | |
1530 | err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW); | |
1531 | break; | |
1532 | case UDP_V4_FLOW: | |
1533 | err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW); | |
1534 | break; | |
1535 | } | |
1536 | ||
1537 | return err; | |
1538 | } | |
1539 | ||
1540 | static int mlx4_en_flow_replace(struct net_device *dev, | |
1541 | struct ethtool_rxnfc *cmd) | |
1542 | { | |
1543 | int err; | |
1544 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1545 | struct ethtool_flow_id *loc_rule; | |
1546 | struct mlx4_spec_list *spec, *tmp_spec; | |
1547 | u32 qpn; | |
1548 | u64 reg_id; | |
1549 | ||
1550 | struct mlx4_net_trans_rule rule = { | |
1551 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
1552 | .exclusive = 0, | |
1553 | .allow_loopback = 1, | |
f9162539 | 1554 | .promisc_mode = MLX4_FS_REGULAR, |
82067281 HHZ |
1555 | }; |
1556 | ||
1557 | rule.port = priv->port; | |
1558 | rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location; | |
1559 | INIT_LIST_HEAD(&rule.list); | |
1560 | ||
1561 | /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */ | |
1562 | if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC) | |
cabdc8ee | 1563 | qpn = priv->drop_qp.qpn; |
82067281 HHZ |
1564 | else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) { |
1565 | qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1); | |
1566 | } else { | |
1567 | if (cmd->fs.ring_cookie >= priv->rx_ring_num) { | |
1a91de28 | 1568 | en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n", |
82067281 HHZ |
1569 | cmd->fs.ring_cookie); |
1570 | return -EINVAL; | |
1571 | } | |
1572 | qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn; | |
1573 | if (!qpn) { | |
1a91de28 | 1574 | en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n", |
82067281 HHZ |
1575 | cmd->fs.ring_cookie); |
1576 | return -EINVAL; | |
1577 | } | |
1578 | } | |
1579 | rule.qpn = qpn; | |
1580 | err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list); | |
1581 | if (err) | |
1582 | goto out_free_list; | |
1583 | ||
1584 | loc_rule = &priv->ethtool_rules[cmd->fs.location]; | |
1585 | if (loc_rule->id) { | |
1586 | err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id); | |
1587 | if (err) { | |
1588 | en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n", | |
1589 | cmd->fs.location, loc_rule->id); | |
1590 | goto out_free_list; | |
1591 | } | |
1592 | loc_rule->id = 0; | |
1593 | memset(&loc_rule->flow_spec, 0, | |
1594 | sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1595 | list_del(&loc_rule->list); |
82067281 HHZ |
1596 | } |
1597 | err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id); | |
1598 | if (err) { | |
1a91de28 | 1599 | en_err(priv, "Fail to attach network rule at location %d\n", |
82067281 HHZ |
1600 | cmd->fs.location); |
1601 | goto out_free_list; | |
1602 | } | |
1603 | loc_rule->id = reg_id; | |
1604 | memcpy(&loc_rule->flow_spec, &cmd->fs, | |
1605 | sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1606 | list_add_tail(&loc_rule->list, &priv->ethtool_list); |
82067281 HHZ |
1607 | |
1608 | out_free_list: | |
1609 | list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) { | |
1610 | list_del(&spec->list); | |
1611 | kfree(spec); | |
1612 | } | |
1613 | return err; | |
1614 | } | |
1615 | ||
1616 | static int mlx4_en_flow_detach(struct net_device *dev, | |
1617 | struct ethtool_rxnfc *cmd) | |
1618 | { | |
1619 | int err = 0; | |
1620 | struct ethtool_flow_id *rule; | |
1621 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1622 | ||
1623 | if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) | |
1624 | return -EINVAL; | |
1625 | ||
1626 | rule = &priv->ethtool_rules[cmd->fs.location]; | |
1627 | if (!rule->id) { | |
1628 | err = -ENOENT; | |
1629 | goto out; | |
1630 | } | |
1631 | ||
1632 | err = mlx4_flow_detach(priv->mdev->dev, rule->id); | |
1633 | if (err) { | |
1634 | en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n", | |
1635 | cmd->fs.location, rule->id); | |
1636 | goto out; | |
1637 | } | |
1638 | rule->id = 0; | |
1639 | memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec)); | |
0d256c0e | 1640 | list_del(&rule->list); |
82067281 HHZ |
1641 | out: |
1642 | return err; | |
1643 | ||
1644 | } | |
1645 | ||
1646 | static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, | |
1647 | int loc) | |
1648 | { | |
1649 | int err = 0; | |
1650 | struct ethtool_flow_id *rule; | |
1651 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1652 | ||
1653 | if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) | |
1654 | return -EINVAL; | |
1655 | ||
1656 | rule = &priv->ethtool_rules[loc]; | |
1657 | if (rule->id) | |
1658 | memcpy(&cmd->fs, &rule->flow_spec, | |
1659 | sizeof(struct ethtool_rx_flow_spec)); | |
1660 | else | |
1661 | err = -ENOENT; | |
1662 | ||
1663 | return err; | |
1664 | } | |
1665 | ||
1666 | static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv) | |
1667 | { | |
1668 | ||
1669 | int i, res = 0; | |
1670 | for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { | |
1671 | if (priv->ethtool_rules[i].id) | |
1672 | res++; | |
1673 | } | |
1674 | return res; | |
1675 | ||
1676 | } | |
1677 | ||
93d3e367 YP |
1678 | static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
1679 | u32 *rule_locs) | |
1680 | { | |
1681 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
82067281 | 1682 | struct mlx4_en_dev *mdev = priv->mdev; |
93d3e367 | 1683 | int err = 0; |
82067281 HHZ |
1684 | int i = 0, priority = 0; |
1685 | ||
1686 | if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT || | |
1687 | cmd->cmd == ETHTOOL_GRXCLSRULE || | |
1688 | cmd->cmd == ETHTOOL_GRXCLSRLALL) && | |
280fce1e HHZ |
1689 | (mdev->dev->caps.steering_mode != |
1690 | MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)) | |
82067281 | 1691 | return -EINVAL; |
93d3e367 YP |
1692 | |
1693 | switch (cmd->cmd) { | |
1694 | case ETHTOOL_GRXRINGS: | |
1695 | cmd->data = priv->rx_ring_num; | |
1696 | break; | |
82067281 HHZ |
1697 | case ETHTOOL_GRXCLSRLCNT: |
1698 | cmd->rule_cnt = mlx4_en_get_num_flows(priv); | |
1699 | break; | |
1700 | case ETHTOOL_GRXCLSRULE: | |
1701 | err = mlx4_en_get_flow(dev, cmd, cmd->fs.location); | |
1702 | break; | |
1703 | case ETHTOOL_GRXCLSRLALL: | |
1704 | while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) { | |
1705 | err = mlx4_en_get_flow(dev, cmd, i); | |
1706 | if (!err) | |
1707 | rule_locs[priority++] = i; | |
1708 | i++; | |
1709 | } | |
1710 | err = 0; | |
1711 | break; | |
93d3e367 YP |
1712 | default: |
1713 | err = -EOPNOTSUPP; | |
1714 | break; | |
1715 | } | |
1716 | ||
1717 | return err; | |
1718 | } | |
1719 | ||
82067281 HHZ |
1720 | static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
1721 | { | |
1722 | int err = 0; | |
1723 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1724 | struct mlx4_en_dev *mdev = priv->mdev; | |
1725 | ||
280fce1e HHZ |
1726 | if (mdev->dev->caps.steering_mode != |
1727 | MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up) | |
82067281 HHZ |
1728 | return -EINVAL; |
1729 | ||
1730 | switch (cmd->cmd) { | |
1731 | case ETHTOOL_SRXCLSRLINS: | |
1732 | err = mlx4_en_flow_replace(dev, cmd); | |
1733 | break; | |
1734 | case ETHTOOL_SRXCLSRLDEL: | |
1735 | err = mlx4_en_flow_detach(dev, cmd); | |
1736 | break; | |
1737 | default: | |
1738 | en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd); | |
1739 | return -EINVAL; | |
1740 | } | |
1741 | ||
1742 | return err; | |
1743 | } | |
1744 | ||
d317966b AV |
1745 | static void mlx4_en_get_channels(struct net_device *dev, |
1746 | struct ethtool_channels *channel) | |
1747 | { | |
1748 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1749 | ||
d317966b AV |
1750 | channel->max_rx = MAX_RX_RINGS; |
1751 | channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP; | |
1752 | ||
1753 | channel->rx_count = priv->rx_ring_num; | |
f21ad614 IK |
1754 | channel->tx_count = priv->tx_ring_num[TX] / |
1755 | priv->prof->num_up; | |
d317966b AV |
1756 | } |
1757 | ||
1758 | static int mlx4_en_set_channels(struct net_device *dev, | |
1759 | struct ethtool_channels *channel) | |
1760 | { | |
1761 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1762 | struct mlx4_en_dev *mdev = priv->mdev; | |
ec25bc04 EE |
1763 | struct mlx4_en_port_profile new_prof; |
1764 | struct mlx4_en_priv *tmp; | |
da26a625 | 1765 | int port_up = 0; |
67f8b1dc | 1766 | int xdp_count; |
d317966b | 1767 | int err = 0; |
ec327f7a | 1768 | u8 up; |
d317966b | 1769 | |
e91ef71d | 1770 | if (!channel->tx_count || !channel->rx_count) |
d317966b AV |
1771 | return -EINVAL; |
1772 | ||
ec25bc04 EE |
1773 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
1774 | if (!tmp) | |
1775 | return -ENOMEM; | |
1776 | ||
d317966b | 1777 | mutex_lock(&mdev->state_lock); |
67f8b1dc | 1778 | xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0; |
f21ad614 IK |
1779 | if (channel->tx_count * priv->prof->num_up + xdp_count > |
1780 | MAX_TX_RINGS) { | |
67f8b1dc TT |
1781 | err = -EINVAL; |
1782 | en_err(priv, | |
1783 | "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n", | |
f21ad614 | 1784 | channel->tx_count * priv->prof->num_up + xdp_count, |
67f8b1dc TT |
1785 | MAX_TX_RINGS); |
1786 | goto out; | |
1787 | } | |
1788 | ||
ec25bc04 EE |
1789 | memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); |
1790 | new_prof.num_tx_rings_p_up = channel->tx_count; | |
f21ad614 | 1791 | new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up; |
67f8b1dc | 1792 | new_prof.tx_ring_num[TX_XDP] = xdp_count; |
ec25bc04 EE |
1793 | new_prof.rx_ring_num = channel->rx_count; |
1794 | ||
770f8225 | 1795 | err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true); |
ec25bc04 EE |
1796 | if (err) |
1797 | goto out; | |
1798 | ||
d317966b AV |
1799 | if (priv->port_up) { |
1800 | port_up = 1; | |
3484aac1 | 1801 | mlx4_en_stop_port(dev, 1); |
d317966b AV |
1802 | } |
1803 | ||
ec25bc04 | 1804 | mlx4_en_safe_replace_resources(priv, tmp); |
d317966b | 1805 | |
d317966b AV |
1806 | netif_set_real_num_rx_queues(dev, priv->rx_ring_num); |
1807 | ||
ec327f7a IK |
1808 | up = (priv->prof->num_up == MLX4_EN_NUM_UP_LOW) ? |
1809 | 0 : priv->prof->num_up; | |
1810 | mlx4_en_setup_tc(dev, up); | |
d317966b | 1811 | |
67f8b1dc | 1812 | en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]); |
d317966b AV |
1813 | en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num); |
1814 | ||
1815 | if (port_up) { | |
1816 | err = mlx4_en_start_port(dev); | |
1817 | if (err) | |
1818 | en_err(priv, "Failed starting port\n"); | |
1819 | } | |
1820 | ||
1821 | err = mlx4_en_moderation_update(priv); | |
d317966b AV |
1822 | out: |
1823 | mutex_unlock(&mdev->state_lock); | |
67f8b1dc | 1824 | kfree(tmp); |
d317966b AV |
1825 | return err; |
1826 | } | |
1827 | ||
ec693d47 AV |
1828 | static int mlx4_en_get_ts_info(struct net_device *dev, |
1829 | struct ethtool_ts_info *info) | |
1830 | { | |
1831 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1832 | struct mlx4_en_dev *mdev = priv->mdev; | |
1833 | int ret; | |
1834 | ||
1835 | ret = ethtool_op_get_ts_info(dev, info); | |
1836 | if (ret) | |
1837 | return ret; | |
1838 | ||
1839 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1840 | info->so_timestamping |= | |
1841 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1842 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1843 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1844 | ||
1845 | info->tx_types = | |
1846 | (1 << HWTSTAMP_TX_OFF) | | |
1847 | (1 << HWTSTAMP_TX_ON); | |
1848 | ||
1849 | info->rx_filters = | |
1850 | (1 << HWTSTAMP_FILTER_NONE) | | |
1851 | (1 << HWTSTAMP_FILTER_ALL); | |
ad7d4eae SB |
1852 | |
1853 | if (mdev->ptp_clock) | |
1854 | info->phc_index = ptp_clock_index(mdev->ptp_clock); | |
ec693d47 AV |
1855 | } |
1856 | ||
1857 | return ret; | |
1858 | } | |
1859 | ||
3f6148e7 | 1860 | static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags) |
0fef9d03 AV |
1861 | { |
1862 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
e38af4fa | 1863 | struct mlx4_en_dev *mdev = priv->mdev; |
0fef9d03 AV |
1864 | bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); |
1865 | bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
e38af4fa HHZ |
1866 | bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV); |
1867 | bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV); | |
0fef9d03 | 1868 | int i; |
e38af4fa | 1869 | int ret = 0; |
0fef9d03 | 1870 | |
7c509a48 | 1871 | if (bf_enabled_new != bf_enabled_old) { |
67f8b1dc TT |
1872 | int t; |
1873 | ||
7c509a48 HHZ |
1874 | if (bf_enabled_new) { |
1875 | bool bf_supported = true; | |
0fef9d03 | 1876 | |
67f8b1dc TT |
1877 | for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) |
1878 | for (i = 0; i < priv->tx_ring_num[t]; i++) | |
1879 | bf_supported &= | |
1880 | priv->tx_ring[t][i]->bf_alloced; | |
0fef9d03 | 1881 | |
7c509a48 HHZ |
1882 | if (!bf_supported) { |
1883 | en_err(priv, "BlueFlame is not supported\n"); | |
1884 | return -EINVAL; | |
1885 | } | |
0fef9d03 | 1886 | |
7c509a48 HHZ |
1887 | priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME; |
1888 | } else { | |
1889 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
0fef9d03 AV |
1890 | } |
1891 | ||
67f8b1dc TT |
1892 | for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) |
1893 | for (i = 0; i < priv->tx_ring_num[t]; i++) | |
1894 | priv->tx_ring[t][i]->bf_enabled = | |
1895 | bf_enabled_new; | |
0fef9d03 | 1896 | |
7c509a48 HHZ |
1897 | en_info(priv, "BlueFlame %s\n", |
1898 | bf_enabled_new ? "Enabled" : "Disabled"); | |
1899 | } | |
0fef9d03 | 1900 | |
e38af4fa HHZ |
1901 | if (phv_enabled_new != phv_enabled_old) { |
1902 | ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new); | |
1903 | if (ret) | |
1904 | return ret; | |
1905 | else if (phv_enabled_new) | |
1906 | priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; | |
1907 | else | |
1908 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV; | |
1909 | en_info(priv, "PHV bit %s\n", | |
1910 | phv_enabled_new ? "Enabled" : "Disabled"); | |
1911 | } | |
0fef9d03 AV |
1912 | return 0; |
1913 | } | |
1914 | ||
3f6148e7 | 1915 | static u32 mlx4_en_get_priv_flags(struct net_device *dev) |
0fef9d03 AV |
1916 | { |
1917 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1918 | ||
1919 | return priv->pflags; | |
1920 | } | |
1921 | ||
1556b874 ED |
1922 | static int mlx4_en_get_tunable(struct net_device *dev, |
1923 | const struct ethtool_tunable *tuna, | |
1924 | void *data) | |
1925 | { | |
1926 | const struct mlx4_en_priv *priv = netdev_priv(dev); | |
1927 | int ret = 0; | |
1928 | ||
1929 | switch (tuna->id) { | |
1930 | case ETHTOOL_TX_COPYBREAK: | |
1931 | *(u32 *)data = priv->prof->inline_thold; | |
1932 | break; | |
1933 | default: | |
1934 | ret = -EINVAL; | |
1935 | break; | |
1936 | } | |
1937 | ||
1938 | return ret; | |
1939 | } | |
1940 | ||
1941 | static int mlx4_en_set_tunable(struct net_device *dev, | |
1942 | const struct ethtool_tunable *tuna, | |
1943 | const void *data) | |
1944 | { | |
1945 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1946 | int val, ret = 0; | |
1947 | ||
1948 | switch (tuna->id) { | |
1949 | case ETHTOOL_TX_COPYBREAK: | |
1950 | val = *(u32 *)data; | |
1951 | if (val < MIN_PKT_LEN || val > MAX_INLINE) | |
1952 | ret = -EINVAL; | |
1953 | else | |
1954 | priv->prof->inline_thold = val; | |
1955 | break; | |
1956 | default: | |
1957 | ret = -EINVAL; | |
1958 | break; | |
1959 | } | |
1960 | ||
1961 | return ret; | |
1962 | } | |
1963 | ||
7202da8b SM |
1964 | static int mlx4_en_get_module_info(struct net_device *dev, |
1965 | struct ethtool_modinfo *modinfo) | |
1966 | { | |
1967 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1968 | struct mlx4_en_dev *mdev = priv->mdev; | |
1969 | int ret; | |
1970 | u8 data[4]; | |
1971 | ||
1972 | /* Read first 2 bytes to get Module & REV ID */ | |
1973 | ret = mlx4_get_module_info(mdev->dev, priv->port, | |
1974 | 0/*offset*/, 2/*size*/, data); | |
1975 | if (ret < 2) | |
1976 | return -EIO; | |
1977 | ||
1978 | switch (data[0] /* identifier */) { | |
1979 | case MLX4_MODULE_ID_QSFP: | |
1980 | modinfo->type = ETH_MODULE_SFF_8436; | |
1981 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1982 | break; | |
1983 | case MLX4_MODULE_ID_QSFP_PLUS: | |
1984 | if (data[1] >= 0x3) { /* revision id */ | |
1985 | modinfo->type = ETH_MODULE_SFF_8636; | |
1986 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1987 | } else { | |
1988 | modinfo->type = ETH_MODULE_SFF_8436; | |
1989 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1990 | } | |
1991 | break; | |
1992 | case MLX4_MODULE_ID_QSFP28: | |
1993 | modinfo->type = ETH_MODULE_SFF_8636; | |
1994 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1995 | break; | |
1996 | case MLX4_MODULE_ID_SFP: | |
1997 | modinfo->type = ETH_MODULE_SFF_8472; | |
1998 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
1999 | break; | |
2000 | default: | |
72b8eaab | 2001 | return -EINVAL; |
7202da8b SM |
2002 | } |
2003 | ||
2004 | return 0; | |
2005 | } | |
2006 | ||
2007 | static int mlx4_en_get_module_eeprom(struct net_device *dev, | |
2008 | struct ethtool_eeprom *ee, | |
2009 | u8 *data) | |
2010 | { | |
2011 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2012 | struct mlx4_en_dev *mdev = priv->mdev; | |
2013 | int offset = ee->offset; | |
2014 | int i = 0, ret; | |
2015 | ||
2016 | if (ee->len == 0) | |
2017 | return -EINVAL; | |
2018 | ||
2019 | memset(data, 0, ee->len); | |
2020 | ||
2021 | while (i < ee->len) { | |
2022 | en_dbg(DRV, priv, | |
2023 | "mlx4_get_module_info i(%d) offset(%d) len(%d)\n", | |
2024 | i, offset, ee->len - i); | |
2025 | ||
2026 | ret = mlx4_get_module_info(mdev->dev, priv->port, | |
2027 | offset, ee->len - i, data + i); | |
2028 | ||
2029 | if (!ret) /* Done reading */ | |
2030 | return 0; | |
2031 | ||
2032 | if (ret < 0) { | |
2033 | en_err(priv, | |
2034 | "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n", | |
2035 | i, offset, ee->len - i, ret); | |
2036 | return 0; | |
2037 | } | |
2038 | ||
2039 | i += ret; | |
2040 | offset += ret; | |
2041 | } | |
2042 | return 0; | |
2043 | } | |
0fef9d03 | 2044 | |
51af33cf IS |
2045 | static int mlx4_en_set_phys_id(struct net_device *dev, |
2046 | enum ethtool_phys_id_state state) | |
2047 | { | |
2048 | int err; | |
2049 | u16 beacon_duration; | |
2050 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2051 | struct mlx4_en_dev *mdev = priv->mdev; | |
2052 | ||
2053 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON)) | |
2054 | return -EOPNOTSUPP; | |
2055 | ||
2056 | switch (state) { | |
2057 | case ETHTOOL_ID_ACTIVE: | |
2058 | beacon_duration = PORT_BEACON_MAX_LIMIT; | |
2059 | break; | |
2060 | case ETHTOOL_ID_INACTIVE: | |
2061 | beacon_duration = 0; | |
2062 | break; | |
2063 | default: | |
2064 | return -EOPNOTSUPP; | |
2065 | } | |
2066 | ||
2067 | err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration); | |
2068 | return err; | |
2069 | } | |
2070 | ||
c27a02cd YP |
2071 | const struct ethtool_ops mlx4_en_ethtool_ops = { |
2072 | .get_drvinfo = mlx4_en_get_drvinfo, | |
3d8f7cc7 DD |
2073 | .get_link_ksettings = mlx4_en_get_link_ksettings, |
2074 | .set_link_ksettings = mlx4_en_set_link_ksettings, | |
c27a02cd | 2075 | .get_link = ethtool_op_get_link, |
c27a02cd YP |
2076 | .get_strings = mlx4_en_get_strings, |
2077 | .get_sset_count = mlx4_en_get_sset_count, | |
2078 | .get_ethtool_stats = mlx4_en_get_ethtool_stats, | |
e7c1c2c4 | 2079 | .self_test = mlx4_en_self_test, |
51af33cf | 2080 | .set_phys_id = mlx4_en_set_phys_id, |
c27a02cd | 2081 | .get_wol = mlx4_en_get_wol, |
14c07b13 | 2082 | .set_wol = mlx4_en_set_wol, |
c27a02cd YP |
2083 | .get_msglevel = mlx4_en_get_msglevel, |
2084 | .set_msglevel = mlx4_en_set_msglevel, | |
2085 | .get_coalesce = mlx4_en_get_coalesce, | |
2086 | .set_coalesce = mlx4_en_set_coalesce, | |
2087 | .get_pauseparam = mlx4_en_get_pauseparam, | |
2088 | .set_pauseparam = mlx4_en_set_pauseparam, | |
2089 | .get_ringparam = mlx4_en_get_ringparam, | |
18cc42a3 | 2090 | .set_ringparam = mlx4_en_set_ringparam, |
93d3e367 | 2091 | .get_rxnfc = mlx4_en_get_rxnfc, |
82067281 | 2092 | .set_rxnfc = mlx4_en_set_rxnfc, |
93d3e367 | 2093 | .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size, |
b9d1ab7e | 2094 | .get_rxfh_key_size = mlx4_en_get_rxfh_key_size, |
fe62d001 BH |
2095 | .get_rxfh = mlx4_en_get_rxfh, |
2096 | .set_rxfh = mlx4_en_set_rxfh, | |
d317966b AV |
2097 | .get_channels = mlx4_en_get_channels, |
2098 | .set_channels = mlx4_en_set_channels, | |
ec693d47 | 2099 | .get_ts_info = mlx4_en_get_ts_info, |
0fef9d03 AV |
2100 | .set_priv_flags = mlx4_en_set_priv_flags, |
2101 | .get_priv_flags = mlx4_en_get_priv_flags, | |
1556b874 ED |
2102 | .get_tunable = mlx4_en_get_tunable, |
2103 | .set_tunable = mlx4_en_set_tunable, | |
7202da8b SM |
2104 | .get_module_info = mlx4_en_get_module_info, |
2105 | .get_module_eeprom = mlx4_en_get_module_eeprom | |
c27a02cd YP |
2106 | }; |
2107 | ||
2108 | ||
2109 | ||
2110 | ||
2111 |