]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/net/ethernet/mellanox/mlx4/en_netdev.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bpf: xdp: Allow head adjustment in XDP prog
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
47a38e15 34#include <linux/bpf.h>
c27a02cd
YP		 35#include <linux/etherdevice.h>
36#include <linux/tcp.h>
37#include <linux/if_vlan.h>
38#include <linux/delay.h>
5a0e3ad6 39#include <linux/slab.h>
1eb8c695
AV		 40#include <linux/hash.h>
41#include <net/ip.h>
076bb0c8 42#include <net/busy_poll.h>
1b136de1 43#include <net/vxlan.h>
09d4d087 44#include <net/devlink.h>
c27a02cd
YP		 45
46#include <linux/mlx4/driver.h>
47#include <linux/mlx4/device.h>
48#include <linux/mlx4/cmd.h>
49#include <linux/mlx4/cq.h>
50
51#include "mlx4_en.h"
52#include "en_port.h"
53
d317966b 54int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 55{
bc6a4744
AV		 56 struct mlx4_en_priv *priv = netdev_priv(dev);
57 int i;
d317966b 58 unsigned int offset = 0;
bc6a4744
AV		 59
60 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 61 return -EINVAL;
62
bc6a4744
AV		 63 netdev_set_num_tc(dev, up);
64
65 /* Partition Tx queues evenly amongst UP's */
bc6a4744 66 for (i = 0; i < up; i++) {
d317966b
AV		 67 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
68 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 69 }
70
af7d5185
RS		 71#ifdef CONFIG_MLX4_EN_DCB
72 if (!mlx4_is_slave(priv->mdev->dev)) {
73 if (up) {
564ed9b1
TT		 74 if (priv->dcbx_cap)
75 priv->flags |= MLX4_EN_FLAG_DCB_ENABLED;
af7d5185
RS		 76 } else {
77 priv->flags &= ~MLX4_EN_FLAG_DCB_ENABLED;
564ed9b1 78 priv->cee_config.pfc_state = false;
af7d5185
RS		 79 }
80 }
81#endif /* CONFIG_MLX4_EN_DCB */
82
897d7846
AV		 83 return 0;
84}
85
16e5cc64
JF		 86static int __mlx4_en_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
87 struct tc_to_netdev *tc)
e4c6734e 88{
5eb4dce3 89 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 90 return -EINVAL;
91
16e5cc64 92 return mlx4_en_setup_tc(dev, tc->tc);
e4c6734e
JF		 93}
94
1eb8c695
AV		 95#ifdef CONFIG_RFS_ACCEL
96
97struct mlx4_en_filter {
98 struct list_head next;
99 struct work_struct work;
100
75a353d4 101 u8 ip_proto;
1eb8c695
AV		 102 __be32 src_ip;
103 __be32 dst_ip;
104 __be16 src_port;
105 __be16 dst_port;
106
107 int rxq_index;
108 struct mlx4_en_priv *priv;
109 u32 flow_id; /* RFS infrastructure id */
110 int id; /* mlx4_en driver id */
111 u64 reg_id; /* Flow steering API id */
112 u8 activated; /* Used to prevent expiry before filter
113 * is attached
114 */
115 struct hlist_node filter_chain;
116};
117
118static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
119
75a353d4
EP		 120static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
121{
122 switch (ip_proto) {
123 case IPPROTO_UDP:
124 return MLX4_NET_TRANS_RULE_ID_UDP;
125 case IPPROTO_TCP:
126 return MLX4_NET_TRANS_RULE_ID_TCP;
127 default:
c3ca5205 128 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 129 }
130};
131
b6e01232
TT		 132/* Must not acquire state_lock, as its corresponding work_sync
133 * is done under it.
134 */
1eb8c695
AV		 135static void mlx4_en_filter_work(struct work_struct *work)
136{
137 struct mlx4_en_filter *filter = container_of(work,
138 struct mlx4_en_filter,
139 work);
140 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 141 struct mlx4_spec_list spec_tcp_udp = {
142 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 143 {
144 .tcp_udp = {
145 .dst_port = filter->dst_port,
146 .dst_port_msk = (__force __be16)-1,
147 .src_port = filter->src_port,
148 .src_port_msk = (__force __be16)-1,
149 },
150 },
151 };
152 struct mlx4_spec_list spec_ip = {
153 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
154 {
155 .ipv4 = {
156 .dst_ip = filter->dst_ip,
157 .dst_ip_msk = (__force __be32)-1,
158 .src_ip = filter->src_ip,
159 .src_ip_msk = (__force __be32)-1,
160 },
161 },
162 };
163 struct mlx4_spec_list spec_eth = {
164 .id = MLX4_NET_TRANS_RULE_ID_ETH,
165 };
166 struct mlx4_net_trans_rule rule = {
167 .list = LIST_HEAD_INIT(rule.list),
168 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
169 .exclusive = 1,
170 .allow_loopback = 1,
f9162539 171 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 172 .port = priv->port,
173 .priority = MLX4_DOMAIN_RFS,
174 };
175 int rc;
1eb8c695
AV		 176 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
177
c3ca5205 178 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 179 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
180 filter->ip_proto);
181 goto ignore;
182 }
1eb8c695
AV		 183 list_add_tail(&spec_eth.list, &rule.list);
184 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 185 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 186
1eb8c695 187 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 188 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 189 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
190
191 filter->activated = 0;
192
193 if (filter->reg_id) {
194 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
195 if (rc && rc != -ENOENT)
196 en_err(priv, "Error detaching flow. rc = %d\n", rc);
197 }
198
199 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
200 if (rc)
201 en_err(priv, "Error attaching flow. err = %d\n", rc);
202
75a353d4 203ignore:
1eb8c695
AV		 204 mlx4_en_filter_rfs_expire(priv);
205
206 filter->activated = 1;
207}
208
209static inline struct hlist_head *
210filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
211 __be16 src_port, __be16 dst_port)
212{
213 unsigned long l;
214 int bucket_idx;
215
216 l = (__force unsigned long)src_port |
217 ((__force unsigned long)dst_port << 2);
218 l ^= (__force unsigned long)(src_ip ^ dst_ip);
219
220 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
221
222 return &priv->filter_hash[bucket_idx];
223}
224
225static struct mlx4_en_filter *
226mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 227 __be32 dst_ip, u8 ip_proto, __be16 src_port,
228 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 229{
230 struct mlx4_en_filter *filter = NULL;
231
232 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
233 if (!filter)
234 return NULL;
235
236 filter->priv = priv;
237 filter->rxq_index = rxq_index;
238 INIT_WORK(&filter->work, mlx4_en_filter_work);
239
240 filter->src_ip = src_ip;
241 filter->dst_ip = dst_ip;
75a353d4 242 filter->ip_proto = ip_proto;
1eb8c695
AV		 243 filter->src_port = src_port;
244 filter->dst_port = dst_port;
245
246 filter->flow_id = flow_id;
247
ee64c0ee 248 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 249
250 list_add_tail(&filter->next, &priv->filters);
251 hlist_add_head(&filter->filter_chain,
252 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
253 dst_port));
254
255 return filter;
256}
257
258static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
259{
260 struct mlx4_en_priv *priv = filter->priv;
261 int rc;
262
263 list_del(&filter->next);
264
265 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
266 if (rc && rc != -ENOENT)
267 en_err(priv, "Error detaching flow. rc = %d\n", rc);
268
269 kfree(filter);
270}
271
272static inline struct mlx4_en_filter *
273mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 274 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 275{
1eb8c695
AV		 276 struct mlx4_en_filter *filter;
277 struct mlx4_en_filter *ret = NULL;
278
b67bfe0d 279 hlist_for_each_entry(filter,
1eb8c695
AV		 280 filter_hash_bucket(priv, src_ip, dst_ip,
281 src_port, dst_port),
282 filter_chain) {
283 if (filter->src_ip == src_ip &&
284 filter->dst_ip == dst_ip &&
75a353d4 285 filter->ip_proto == ip_proto &&
1eb8c695
AV		 286 filter->src_port == src_port &&
287 filter->dst_port == dst_port) {
288 ret = filter;
289 break;
290 }
291 }
292
293 return ret;
294}
295
296static int
297mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
298 u16 rxq_index, u32 flow_id)
299{
300 struct mlx4_en_priv *priv = netdev_priv(net_dev);
301 struct mlx4_en_filter *filter;
302 const struct iphdr *ip;
303 const __be16 *ports;
75a353d4 304 u8 ip_proto;
1eb8c695
AV		 305 __be32 src_ip;
306 __be32 dst_ip;
307 __be16 src_port;
308 __be16 dst_port;
309 int nhoff = skb_network_offset(skb);
310 int ret = 0;
311
312 if (skb->protocol != htons(ETH_P_IP))
313 return -EPROTONOSUPPORT;
314
315 ip = (const struct iphdr *)(skb->data + nhoff);
316 if (ip_is_fragment(ip))
317 return -EPROTONOSUPPORT;
318
75a353d4
EP		 319 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
320 return -EPROTONOSUPPORT;
1eb8c695
AV		 321 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
322
75a353d4 323 ip_proto = ip->protocol;
1eb8c695
AV		 324 src_ip = ip->saddr;
325 dst_ip = ip->daddr;
326 src_port = ports[0];
327 dst_port = ports[1];
328
1eb8c695 329 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 330 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
331 src_port, dst_port);
1eb8c695
AV		 332 if (filter) {
333 if (filter->rxq_index == rxq_index)
334 goto out;
335
336 filter->rxq_index = rxq_index;
337 } else {
338 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 339 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 340 src_port, dst_port, flow_id);
341 if (!filter) {
342 ret = -ENOMEM;
343 goto err;
344 }
345 }
346
347 queue_work(priv->mdev->workqueue, &filter->work);
348
349out:
350 ret = filter->id;
351err:
352 spin_unlock_bh(&priv->filters_lock);
353
354 return ret;
355}
356
41d942d5 357void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 358{
359 struct mlx4_en_filter *filter, *tmp;
360 LIST_HEAD(del_list);
361
362 spin_lock_bh(&priv->filters_lock);
363 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
364 list_move(&filter->next, &del_list);
365 hlist_del(&filter->filter_chain);
366 }
367 spin_unlock_bh(&priv->filters_lock);
368
369 list_for_each_entry_safe(filter, tmp, &del_list, next) {
370 cancel_work_sync(&filter->work);
371 mlx4_en_filter_free(filter);
372 }
373}
374
375static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
376{
377 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
378 LIST_HEAD(del_list);
379 int i = 0;
380
381 spin_lock_bh(&priv->filters_lock);
382 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
383 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
384 break;
385
386 if (filter->activated &&
387 !work_pending(&filter->work) &&
388 rps_may_expire_flow(priv->dev,
389 filter->rxq_index, filter->flow_id,
390 filter->id)) {
391 list_move(&filter->next, &del_list);
392 hlist_del(&filter->filter_chain);
393 } else
394 last_filter = filter;
395
396 i++;
397 }
398
399 if (last_filter && (&last_filter->next != priv->filters.next))
400 list_move(&priv->filters, &last_filter->next);
401
402 spin_unlock_bh(&priv->filters_lock);
403
404 list_for_each_entry_safe(filter, tmp, &del_list, next)
405 mlx4_en_filter_free(filter);
406}
407#endif
408
80d5c368
PM		 409static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
410 __be16 proto, u16 vid)
c27a02cd
YP		 411{
412 struct mlx4_en_priv *priv = netdev_priv(dev);
413 struct mlx4_en_dev *mdev = priv->mdev;
414 int err;
4c3eb3ca 415 int idx;
c27a02cd 416
f1b553fb 417 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 418
f1b553fb 419 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 420
421 /* Add VID to port VLAN filter */
422 mutex_lock(&mdev->state_lock);
423 if (mdev->device_up && priv->port_up) {
f1b553fb 424 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
93c098af 425 if (err) {
453a6082 426 en_err(priv, "Failed configuring VLAN filter\n");
93c098af
KH		 427 goto out;
428 }
c27a02cd 429 }
93c098af
KH		 430 err = mlx4_register_vlan(mdev->dev, priv->port, vid, &idx);
431 if (err)
432 en_dbg(HW, priv, "Failed adding vlan %d\n", vid);
4c3eb3ca 433
93c098af
KH		 434out:
435 mutex_unlock(&mdev->state_lock);
436 return err;
c27a02cd
YP		 437}
438
80d5c368
PM		 439static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
440 __be16 proto, u16 vid)
c27a02cd
YP		 441{
442 struct mlx4_en_priv *priv = netdev_priv(dev);
443 struct mlx4_en_dev *mdev = priv->mdev;
93c098af 444 int err = 0;
c27a02cd 445
f1b553fb 446 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 447
f1b553fb 448 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 449
450 /* Remove VID from port VLAN filter */
451 mutex_lock(&mdev->state_lock);
2009d005 452 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 453
c27a02cd 454 if (mdev->device_up && priv->port_up) {
f1b553fb 455 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 456 if (err)
453a6082 457 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 458 }
459 mutex_unlock(&mdev->state_lock);
8e586137 460
93c098af 461 return err;
c27a02cd
YP		 462}
463
6bbb6d99
YB		 464static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
465{
bab6a9ea
YB		 466 int i;
467 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 468 dst_mac[i] = src_mac & 0xff;
469 src_mac >>= 8;
470 }
471 memset(&dst_mac[ETH_ALEN], 0, 2);
472}
473
837052d0
OG		 474
475static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
476 int qpn, u64 *reg_id)
477{
478 int err;
837052d0 479
5eff6dad
OG		 480 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
481 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 482 return 0; /* do nothing */
483
b95089d0
OG		 484 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
485 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 486 if (err) {
487 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
488 return err;
489 }
490 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
491 return 0;
492}
493
494
16a10ffd
YB		 495static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
496 unsigned char *mac, int *qpn, u64 *reg_id)
497{
498 struct mlx4_en_dev *mdev = priv->mdev;
499 struct mlx4_dev *dev = mdev->dev;
500 int err;
501
502 switch (dev->caps.steering_mode) {
503 case MLX4_STEERING_MODE_B0: {
504 struct mlx4_qp qp;
505 u8 gid[16] = {0};
506
507 qp.qpn = *qpn;
508 memcpy(&gid[10], mac, ETH_ALEN);
509 gid[5] = priv->port;
510
511 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
512 break;
513 }
514 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
515 struct mlx4_spec_list spec_eth = { {NULL} };
516 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
517
518 struct mlx4_net_trans_rule rule = {
519 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
520 .exclusive = 0,
521 .allow_loopback = 1,
f9162539 522 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 523 .priority = MLX4_DOMAIN_NIC,
524 };
525
526 rule.port = priv->port;
527 rule.qpn = *qpn;
528 INIT_LIST_HEAD(&rule.list);
529
530 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
531 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
532 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
533 list_add_tail(&spec_eth.list, &rule.list);
534
535 err = mlx4_flow_attach(dev, &rule, reg_id);
536 break;
537 }
538 default:
539 return -EINVAL;
540 }
541 if (err)
542 en_warn(priv, "Failed Attaching Unicast\n");
543
544 return err;
545}
546
547static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
548 unsigned char *mac, int qpn, u64 reg_id)
549{
550 struct mlx4_en_dev *mdev = priv->mdev;
551 struct mlx4_dev *dev = mdev->dev;
552
553 switch (dev->caps.steering_mode) {
554 case MLX4_STEERING_MODE_B0: {
555 struct mlx4_qp qp;
556 u8 gid[16] = {0};
557
558 qp.qpn = qpn;
559 memcpy(&gid[10], mac, ETH_ALEN);
560 gid[5] = priv->port;
561
562 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
563 break;
564 }
565 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
566 mlx4_flow_detach(dev, reg_id);
567 break;
568 }
569 default:
570 en_err(priv, "Invalid steering mode.\n");
571 }
572}
573
574static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
575{
576 struct mlx4_en_dev *mdev = priv->mdev;
577 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 578 int index = 0;
579 int err = 0;
16a10ffd 580 int *qpn = &priv->base_qpn;
9813337a 581 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 582
583 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
584 priv->dev->dev_addr);
585 index = mlx4_register_mac(dev, priv->port, mac);
586 if (index < 0) {
587 err = index;
588 en_err(priv, "Failed adding MAC: %pM\n",
589 priv->dev->dev_addr);
590 return err;
591 }
592
593 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
594 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
595 *qpn = base_qpn + index;
596 return 0;
597 }
598
d57febe1 599 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 600 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
601 if (err) {
602 en_err(priv, "Failed to reserve qp for mac registration\n");
ba4b87ae
IS		 603 mlx4_unregister_mac(dev, priv->port, mac);
604 return err;
16a10ffd 605 }
16a10ffd 606
c07cb4b0 607 return 0;
16a10ffd
YB		 608}
609
610static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
611{
612 struct mlx4_en_dev *mdev = priv->mdev;
613 struct mlx4_dev *dev = mdev->dev;
16a10ffd 614 int qpn = priv->base_qpn;
16a10ffd 615
83a5a6ce 616 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
ba4b87ae 617 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 618 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
619 priv->dev->dev_addr);
620 mlx4_unregister_mac(dev, priv->port, mac);
621 } else {
83a5a6ce
YB		 622 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
623 priv->port, qpn);
624 mlx4_qp_release_range(dev, qpn, 1);
625 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 626 }
627}
628
629static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 630 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 631{
632 struct mlx4_en_dev *mdev = priv->mdev;
633 struct mlx4_dev *dev = mdev->dev;
16a10ffd 634 int err = 0;
9813337a 635 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 636
637 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 638 struct hlist_head *bucket;
639 unsigned int mac_hash;
640 struct mlx4_mac_entry *entry;
b67bfe0d 641 struct hlist_node *tmp;
9813337a 642 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 643
644 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 645 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 646 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
647 mlx4_en_uc_steer_release(priv, entry->mac,
648 qpn, entry->reg_id);
649 mlx4_unregister_mac(dev, priv->port,
650 prev_mac_u64);
651 hlist_del_rcu(&entry->hlist);
652 synchronize_rcu();
653 memcpy(entry->mac, new_mac, ETH_ALEN);
654 entry->reg_id = 0;
655 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
656 hlist_add_head_rcu(&entry->hlist,
657 &priv->mac_hash[mac_hash]);
658 mlx4_register_mac(dev, priv->port, new_mac_u64);
659 err = mlx4_en_uc_steer_add(priv, new_mac,
660 &qpn,
661 &entry->reg_id);
2a2083f7
OG		 662 if (err)
663 return err;
664 if (priv->tunnel_reg_id) {
665 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
666 priv->tunnel_reg_id = 0;
667 }
668 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
669 &priv->tunnel_reg_id);
c07cb4b0
YB		 670 return err;
671 }
672 }
673 return -EINVAL;
16a10ffd
YB		 674 }
675
676 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
677}
678
2695bab2
NO		 679static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
680 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 681{
c27a02cd
YP		 682 int err = 0;
683
c27a02cd
YP		 684 if (priv->port_up) {
685 /* Remove old MAC and insert the new one */
16a10ffd 686 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 687 new_mac, priv->current_mac);
c27a02cd 688 if (err)
453a6082 689 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 690 } else
48e551ff 691 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 692
2695bab2
NO		 693 if (!err)
694 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 695
bfa8ab47
YB		 696 return err;
697}
698
699static int mlx4_en_set_mac(struct net_device *dev, void *addr)
700{
701 struct mlx4_en_priv *priv = netdev_priv(dev);
702 struct mlx4_en_dev *mdev = priv->mdev;
703 struct sockaddr *saddr = addr;
2695bab2 704 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 705 int err;
706
707 if (!is_valid_ether_addr(saddr->sa_data))
708 return -EADDRNOTAVAIL;
709
bfa8ab47 710 mutex_lock(&mdev->state_lock);
2695bab2
NO		 711 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
712 err = mlx4_en_do_set_mac(priv, new_mac);
713 if (!err)
714 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 715 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 716
717 return err;
c27a02cd
YP		 718}
719
720static void mlx4_en_clear_list(struct net_device *dev)
721{
722 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 723 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 724
6d199937
YP		 725 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
726 list_del(&mc_to_del->list);
727 kfree(mc_to_del);
728 }
c27a02cd
YP		 729}
730
731static void mlx4_en_cache_mclist(struct net_device *dev)
732{
733 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 734 struct netdev_hw_addr *ha;
6d199937 735 struct mlx4_en_mc_list *tmp;
ff6e2163 736
0e03567a 737 mlx4_en_clear_list(dev);
6d199937
YP		 738 netdev_for_each_mc_addr(ha, dev) {
739 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
740 if (!tmp) {
6d199937
YP		 741 mlx4_en_clear_list(dev);
742 return;
743 }
744 memcpy(tmp->addr, ha->addr, ETH_ALEN);
745 list_add_tail(&tmp->list, &priv->mc_list);
746 }
c27a02cd
YP		 747}
748
6d199937
YP		 749static void update_mclist_flags(struct mlx4_en_priv *priv,
750 struct list_head *dst,
751 struct list_head *src)
752{
753 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
754 bool found;
755
756 /* Find all the entries that should be removed from dst,
757 * These are the entries that are not found in src
758 */
759 list_for_each_entry(dst_tmp, dst, list) {
760 found = false;
761 list_for_each_entry(src_tmp, src, list) {
c0623e58 762 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 763 found = true;
764 break;
765 }
766 }
767 if (!found)
768 dst_tmp->action = MCLIST_REM;
769 }
770
771 /* Add entries that exist in src but not in dst
772 * mark them as need to add
773 */
774 list_for_each_entry(src_tmp, src, list) {
775 found = false;
776 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 777 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 778 dst_tmp->action = MCLIST_NONE;
779 found = true;
780 break;
781 }
782 }
783 if (!found) {
14f8dc49
JP		 784 new_mc = kmemdup(src_tmp,
785 sizeof(struct mlx4_en_mc_list),
6d199937 786 GFP_KERNEL);
14f8dc49 787 if (!new_mc)
6d199937 788 return;
14f8dc49 789
6d199937
YP		 790 new_mc->action = MCLIST_ADD;
791 list_add_tail(&new_mc->list, dst);
792 }
793 }
794}
c27a02cd 795
0eb74fdd 796static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 797{
798 struct mlx4_en_priv *priv = netdev_priv(dev);
799
800 if (!priv->port_up)
801 return;
802
0eb74fdd 803 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 804}
805
0eb74fdd
YB		 806static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
807 struct mlx4_en_dev *mdev)
c27a02cd 808{
c96d97f4 809 int err = 0;
c27a02cd 810
0eb74fdd 811 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 812 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 813 en_warn(priv, "Entering promiscuous mode\n");
814 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 815
0eb74fdd 816 /* Enable promiscouos mode */
c96d97f4 817 switch (mdev->dev->caps.steering_mode) {
592e49dd 818 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 819 err = mlx4_flow_steer_promisc_add(mdev->dev,
820 priv->port,
821 priv->base_qpn,
f9162539 822 MLX4_FS_ALL_DEFAULT);
592e49dd 823 if (err)
0eb74fdd
YB		 824 en_err(priv, "Failed enabling promiscuous mode\n");
825 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 826 break;
827
c96d97f4 828 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 829 err = mlx4_unicast_promisc_add(mdev->dev,
830 priv->base_qpn,
831 priv->port);
c96d97f4 832 if (err)
0eb74fdd
YB		 833 en_err(priv, "Failed enabling unicast promiscuous mode\n");
834
835 /* Add the default qp number as multicast
836 * promisc
837 */
838 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
839 err = mlx4_multicast_promisc_add(mdev->dev,
840 priv->base_qpn,
841 priv->port);
c96d97f4 842 if (err)
0eb74fdd
YB		 843 en_err(priv, "Failed enabling multicast promiscuous mode\n");
844 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 845 }
846 break;
c27a02cd 847
c96d97f4
HHZ		 848 case MLX4_STEERING_MODE_A0:
849 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
850 priv->port,
0eb74fdd
YB		 851 priv->base_qpn,
852 1);
1679200f 853 if (err)
0eb74fdd 854 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 855 break;
1679200f
YP		 856 }
857
0eb74fdd
YB		 858 /* Disable port multicast filter (unconditionally) */
859 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
860 0, MLX4_MCAST_DISABLE);
861 if (err)
862 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 863 }
864}
865
866static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
867 struct mlx4_en_dev *mdev)
868{
869 int err = 0;
870
871 if (netif_msg_rx_status(priv))
872 en_warn(priv, "Leaving promiscuous mode\n");
873 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
874
875 /* Disable promiscouos mode */
876 switch (mdev->dev->caps.steering_mode) {
877 case MLX4_STEERING_MODE_DEVICE_MANAGED:
878 err = mlx4_flow_steer_promisc_remove(mdev->dev,
879 priv->port,
f9162539 880 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 881 if (err)
882 en_err(priv, "Failed disabling promiscuous mode\n");
883 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
884 break;
885
886 case MLX4_STEERING_MODE_B0:
887 err = mlx4_unicast_promisc_remove(mdev->dev,
888 priv->base_qpn,
889 priv->port);
890 if (err)
891 en_err(priv, "Failed disabling unicast promiscuous mode\n");
892 /* Disable Multicast promisc */
893 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
894 err = mlx4_multicast_promisc_remove(mdev->dev,
895 priv->base_qpn,
896 priv->port);
897 if (err)
898 en_err(priv, "Failed disabling multicast promiscuous mode\n");
899 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
900 }
901 break;
902
903 case MLX4_STEERING_MODE_A0:
904 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
905 priv->port,
906 priv->base_qpn, 0);
907 if (err)
908 en_err(priv, "Failed disabling promiscuous mode\n");
909 break;
c27a02cd 910 }
0eb74fdd
YB		 911}
912
913static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
914 struct net_device *dev,
915 struct mlx4_en_dev *mdev)
916{
917 struct mlx4_en_mc_list *mclist, *tmp;
918 u64 mcast_addr = 0;
919 u8 mc_list[16] = {0};
920 int err = 0;
921
c27a02cd
YP		 922 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
923 if (dev->flags & IFF_ALLMULTI) {
924 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
925 0, MLX4_MCAST_DISABLE);
926 if (err)
453a6082 927 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 928
929 /* Add the default qp number as multicast promisc */
930 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 931 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 932 case MLX4_STEERING_MODE_DEVICE_MANAGED:
933 err = mlx4_flow_steer_promisc_add(mdev->dev,
934 priv->port,
935 priv->base_qpn,
f9162539 936 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 937 break;
938
c96d97f4
HHZ		 939 case MLX4_STEERING_MODE_B0:
940 err = mlx4_multicast_promisc_add(mdev->dev,
941 priv->base_qpn,
942 priv->port);
943 break;
944
945 case MLX4_STEERING_MODE_A0:
946 break;
947 }
1679200f
YP		 948 if (err)
949 en_err(priv, "Failed entering multicast promisc mode\n");
950 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
951 }
c27a02cd 952 } else {
1679200f
YP		 953 /* Disable Multicast promisc */
954 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 955 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 956 case MLX4_STEERING_MODE_DEVICE_MANAGED:
957 err = mlx4_flow_steer_promisc_remove(mdev->dev,
958 priv->port,
f9162539 959 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 960 break;
961
c96d97f4
HHZ		 962 case MLX4_STEERING_MODE_B0:
963 err = mlx4_multicast_promisc_remove(mdev->dev,
964 priv->base_qpn,
965 priv->port);
966 break;
967
968 case MLX4_STEERING_MODE_A0:
969 break;
970 }
1679200f 971 if (err)
25985edc 972 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 973 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
974 }
ff6e2163 975
c27a02cd
YP		 976 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
977 0, MLX4_MCAST_DISABLE);
978 if (err)
453a6082 979 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 980
981 /* Flush mcast filter and init it with broadcast address */
982 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
983 1, MLX4_MCAST_CONFIG);
984
985 /* Update multicast list - we cache all addresses so they won't
986 * change while HW is updated holding the command semaphor */
dbd501a8 987 netif_addr_lock_bh(dev);
c27a02cd 988 mlx4_en_cache_mclist(dev);
dbd501a8 989 netif_addr_unlock_bh(dev);
6d199937 990 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 991 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 992 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
993 mcast_addr, 0, MLX4_MCAST_CONFIG);
994 }
995 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
996 0, MLX4_MCAST_ENABLE);
997 if (err)
453a6082 998 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 999
1000 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1001 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1002 if (mclist->action == MCLIST_REM) {
1003 /* detach this address and delete from list */
1004 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1005 mc_list[5] = priv->port;
1006 err = mlx4_multicast_detach(mdev->dev,
1007 &priv->rss_map.indir_qp,
1008 mc_list,
0ff1fb65
HHZ		 1009 MLX4_PROT_ETH,
1010 mclist->reg_id);
6d199937
YP		 1011 if (err)
1012 en_err(priv, "Fail to detach multicast address\n");
1013
837052d0
OG		 1014 if (mclist->tunnel_reg_id) {
1015 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1016 if (err)
1017 en_err(priv, "Failed to detach multicast address\n");
1018 }
1019
6d199937
YP		 1020 /* remove from list */
1021 list_del(&mclist->list);
1022 kfree(mclist);
9c64508a 1023 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1024 /* attach the address */
1025 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1026 /* needed for B0 steering support */
6d199937
YP		 1027 mc_list[5] = priv->port;
1028 err = mlx4_multicast_attach(mdev->dev,
1029 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1030 mc_list,
1031 priv->port, 0,
1032 MLX4_PROT_ETH,
1033 &mclist->reg_id);
6d199937
YP		 1034 if (err)
1035 en_err(priv, "Fail to attach multicast address\n");
1036
837052d0
OG		 1037 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1038 &mclist->tunnel_reg_id);
1039 if (err)
1040 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1041 }
1042 }
c27a02cd 1043 }
0eb74fdd
YB		 1044}
1045
cc5387f7
YB		 1046static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1047 struct net_device *dev,
1048 struct mlx4_en_dev *mdev)
1049{
1050 struct netdev_hw_addr *ha;
1051 struct mlx4_mac_entry *entry;
b67bfe0d 1052 struct hlist_node *tmp;
cc5387f7
YB		 1053 bool found;
1054 u64 mac;
1055 int err = 0;
1056 struct hlist_head *bucket;
1057 unsigned int i;
1058 int removed = 0;
1059 u32 prev_flags;
1060
1061 /* Note that we do not need to protect our mac_hash traversal with rcu,
1062 * since all modification code is protected by mdev->state_lock
1063 */
1064
1065 /* find what to remove */
1066 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1067 bucket = &priv->mac_hash[i];
b67bfe0d 1068 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1069 found = false;
1070 netdev_for_each_uc_addr(ha, dev) {
1071 if (ether_addr_equal_64bits(entry->mac,
1072 ha->addr)) {
1073 found = true;
1074 break;
1075 }
1076 }
1077
1078 /* MAC address of the port is not in uc list */
2695bab2
NO		 1079 if (ether_addr_equal_64bits(entry->mac,
1080 priv->current_mac))
cc5387f7
YB		 1081 found = true;
1082
1083 if (!found) {
9813337a 1084 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1085 mlx4_en_uc_steer_release(priv, entry->mac,
1086 priv->base_qpn,
1087 entry->reg_id);
1088 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1089
1090 hlist_del_rcu(&entry->hlist);
1091 kfree_rcu(entry, rcu);
1092 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1093 entry->mac, priv->port);
1094 ++removed;
1095 }
1096 }
1097 }
1098
1099 /* if we didn't remove anything, there is no use in trying to add
1100 * again once we are in a forced promisc mode state
1101 */
1102 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1103 return;
1104
1105 prev_flags = priv->flags;
1106 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1107
1108 /* find what to add */
1109 netdev_for_each_uc_addr(ha, dev) {
1110 found = false;
1111 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1112 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1113 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1114 found = true;
1115 break;
1116 }
1117 }
1118
1119 if (!found) {
1120 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1121 if (!entry) {
1122 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1123 ha->addr, priv->port);
1124 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1125 break;
1126 }
9813337a 1127 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1128 memcpy(entry->mac, ha->addr, ETH_ALEN);
1129 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1130 if (err < 0) {
1131 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1132 ha->addr, priv->port, err);
1133 kfree(entry);
1134 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1135 break;
1136 }
1137 err = mlx4_en_uc_steer_add(priv, ha->addr,
1138 &priv->base_qpn,
1139 &entry->reg_id);
1140 if (err) {
1141 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1142 ha->addr, priv->port, err);
1143 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1144 kfree(entry);
1145 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1146 break;
1147 } else {
1148 unsigned int mac_hash;
1149 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1150 ha->addr, priv->port);
1151 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1152 bucket = &priv->mac_hash[mac_hash];
1153 hlist_add_head_rcu(&entry->hlist, bucket);
1154 }
1155 }
1156 }
1157
1158 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1159 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1160 priv->port);
1161 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1162 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1163 priv->port);
1164 }
1165}
1166
0eb74fdd
YB		 1167static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1168{
1169 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1170 rx_mode_task);
1171 struct mlx4_en_dev *mdev = priv->mdev;
1172 struct net_device *dev = priv->dev;
1173
1174 mutex_lock(&mdev->state_lock);
1175 if (!mdev->device_up) {
1176 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1177 goto out;
1178 }
1179 if (!priv->port_up) {
1180 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1181 goto out;
1182 }
1183
1184 if (!netif_carrier_ok(dev)) {
1185 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1186 if (priv->port_state.link_state) {
1187 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1188 netif_carrier_on(dev);
1189 en_dbg(LINK, priv, "Link Up\n");
1190 }
1191 }
1192 }
1193
cc5387f7
YB		 1194 if (dev->priv_flags & IFF_UNICAST_FLT)
1195 mlx4_en_do_uc_filter(priv, dev, mdev);
1196
0eb74fdd 1197 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1198 if ((dev->flags & IFF_PROMISC) ||
1199 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1200 mlx4_en_set_promisc_mode(priv, mdev);
1201 goto out;
1202 }
1203
1204 /* Not in promiscuous mode */
1205 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1206 mlx4_en_clear_promisc_mode(priv, mdev);
1207
1208 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1209out:
1210 mutex_unlock(&mdev->state_lock);
1211}
1212
1213#ifdef CONFIG_NET_POLL_CONTROLLER
1214static void mlx4_en_netpoll(struct net_device *dev)
1215{
1216 struct mlx4_en_priv *priv = netdev_priv(dev);
1217 struct mlx4_en_cq *cq;
c27a02cd
YP		 1218 int i;
1219
67f8b1dc
TT		 1220 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1221 cq = priv->tx_cq[TX][i];
c98235cb 1222 napi_schedule(&cq->napi);
c27a02cd
YP		 1223 }
1224}
1225#endif
1226
ba4b87ae
IS		 1227static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1228{
1229 u64 reg_id;
1230 int err = 0;
1231 int *qpn = &priv->base_qpn;
1232 struct mlx4_mac_entry *entry;
1233
1234 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
1235 if (err)
1236 return err;
1237
1238 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1239 &priv->tunnel_reg_id);
1240 if (err)
1241 goto tunnel_err;
1242
1243 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1244 if (!entry) {
1245 err = -ENOMEM;
1246 goto alloc_err;
1247 }
1248
1249 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1250 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1251 entry->reg_id = reg_id;
1252 hlist_add_head_rcu(&entry->hlist,
1253 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1254
1255 return 0;
1256
1257alloc_err:
1258 if (priv->tunnel_reg_id)
1259 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1260
1261tunnel_err:
1262 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1263 return err;
1264}
1265
1266static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1267{
1268 u64 mac;
1269 unsigned int i;
1270 int qpn = priv->base_qpn;
1271 struct hlist_head *bucket;
1272 struct hlist_node *tmp;
1273 struct mlx4_mac_entry *entry;
1274
1275 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1276 bucket = &priv->mac_hash[i];
1277 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1278 mac = mlx4_mac_to_u64(entry->mac);
1279 en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1280 entry->mac);
1281 mlx4_en_uc_steer_release(priv, entry->mac,
1282 qpn, entry->reg_id);
1283
1284 mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1285 hlist_del_rcu(&entry->hlist);
1286 kfree_rcu(entry, rcu);
1287 }
1288 }
1289
1290 if (priv->tunnel_reg_id) {
1291 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1292 priv->tunnel_reg_id = 0;
1293 }
1294}
1295
c27a02cd
YP		 1296static void mlx4_en_tx_timeout(struct net_device *dev)
1297{
1298 struct mlx4_en_priv *priv = netdev_priv(dev);
1299 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1300 int i;
c27a02cd
YP		 1301
1302 if (netif_msg_timer(priv))
453a6082 1303 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1304
67f8b1dc
TT		 1305 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1306 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][i];
1307
b944ebec
YP		 1308 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1309 continue;
1310 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
e3f42f84 1311 i, tx_ring->qpn, tx_ring->sp_cqn,
67f8b1dc 1312 tx_ring->cons, tx_ring->prod);
b944ebec
YP		 1313 }
1314
1e338db5 1315 priv->port_stats.tx_timeout++;
453a6082 1316 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1317 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1318}
1319
1320
9ed17db1
ED		 1321static struct rtnl_link_stats64 *
1322mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
c27a02cd
YP		 1323{
1324 struct mlx4_en_priv *priv = netdev_priv(dev);
1325
1326 spin_lock_bh(&priv->stats_lock);
40931b85 1327 mlx4_en_fold_software_stats(dev);
f73a6f43 1328 netdev_stats_to_stats64(stats, &dev->stats);
c27a02cd
YP		 1329 spin_unlock_bh(&priv->stats_lock);
1330
9ed17db1 1331 return stats;
c27a02cd
YP		 1332}
1333
1334static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1335{
c27a02cd 1336 struct mlx4_en_cq *cq;
67f8b1dc 1337 int i, t;
c27a02cd
YP		 1338
1339 /* If we haven't received a specific coalescing setting
98a1708d 1340 * (module param), we set the moderation parameters as follows:
c27a02cd 1341 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1342 * satisfy our coalescing target.
c27a02cd
YP		 1343 * - moder_time is set to a fixed value.
1344 */
3db36fb2 1345 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1346 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1347 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1348 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1349 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1350 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1351
1352 /* Setup cq moderation params */
1353 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1354 cq = priv->rx_cq[i];
c27a02cd
YP		 1355 cq->moder_cnt = priv->rx_frames;
1356 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1357 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1358 priv->last_moder_packets[i] = 0;
1359 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1360 }
1361
67f8b1dc
TT		 1362 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1363 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1364 cq = priv->tx_cq[t][i];
1365 cq->moder_cnt = priv->tx_frames;
1366 cq->moder_time = priv->tx_usecs;
1367 }
c27a02cd
YP		 1368 }
1369
1370 /* Reset auto-moderation params */
1371 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1372 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1373 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1374 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1375 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1376 priv->adaptive_rx_coal = 1;
c27a02cd 1377 priv->last_moder_jiffies = 0;
c27a02cd 1378 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1379}
1380
1381static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1382{
1383 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1384 struct mlx4_en_cq *cq;
1385 unsigned long packets;
1386 unsigned long rate;
1387 unsigned long avg_pkt_size;
1388 unsigned long rx_packets;
1389 unsigned long rx_bytes;
c27a02cd
YP		 1390 unsigned long rx_pkt_diff;
1391 int moder_time;
6b4d8d9f 1392 int ring, err;
c27a02cd
YP		 1393
1394 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1395 return;
1396
6b4d8d9f 1397 for (ring = 0; ring < priv->rx_ring_num; ring++) {
b9972d22
ED		 1398 rx_packets = READ_ONCE(priv->rx_ring[ring]->packets);
1399 rx_bytes = READ_ONCE(priv->rx_ring[ring]->bytes);
6b4d8d9f
AG		 1400
1401 rx_pkt_diff = ((unsigned long) (rx_packets -
1402 priv->last_moder_packets[ring]));
1403 packets = rx_pkt_diff;
1404 rate = packets * HZ / period;
1405 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1406 priv->last_moder_bytes[ring])) / packets : 0;
1407
1408 /* Apply auto-moderation only when packet rate
1409 * exceeds a rate that it matters */
1410 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1411 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1412 if (rate < priv->pkt_rate_low)
1413 moder_time = priv->rx_usecs_low;
1414 else if (rate > priv->pkt_rate_high)
1415 moder_time = priv->rx_usecs_high;
1416 else
1417 moder_time = (rate - priv->pkt_rate_low) *
1418 (priv->rx_usecs_high - priv->rx_usecs_low) /
1419 (priv->pkt_rate_high - priv->pkt_rate_low) +
1420 priv->rx_usecs_low;
6b4d8d9f
AG		 1421 } else {
1422 moder_time = priv->rx_usecs_low;
c27a02cd 1423 }
c27a02cd 1424
6b4d8d9f
AG		 1425 if (moder_time != priv->last_moder_time[ring]) {
1426 priv->last_moder_time[ring] = moder_time;
41d942d5 1427 cq = priv->rx_cq[ring];
c27a02cd 1428 cq->moder_time = moder_time;
a1c6693a 1429 cq->moder_cnt = priv->rx_frames;
c27a02cd 1430 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1431 if (err)
48e551ff
YB		 1432 en_err(priv, "Failed modifying moderation for cq:%d\n",
1433 ring);
c27a02cd 1434 }
6b4d8d9f
AG		 1435 priv->last_moder_packets[ring] = rx_packets;
1436 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1437 }
1438
c27a02cd
YP		 1439 priv->last_moder_jiffies = jiffies;
1440}
1441
1442static void mlx4_en_do_get_stats(struct work_struct *work)
1443{
bf6aede7 1444 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1445 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1446 stats_task);
1447 struct mlx4_en_dev *mdev = priv->mdev;
1448 int err;
1449
c27a02cd
YP		 1450 mutex_lock(&mdev->state_lock);
1451 if (mdev->device_up) {
6123db2e
JM		 1452 if (priv->port_up) {
1453 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1454 if (err)
1455 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1456
c27a02cd 1457 mlx4_en_auto_moderation(priv);
6123db2e 1458 }
c27a02cd
YP		 1459
1460 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1461 }
d7e1a487 1462 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1463 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1464 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1465 }
c27a02cd
YP		 1466 mutex_unlock(&mdev->state_lock);
1467}
1468
b6c39bfc
AV		 1469/* mlx4_en_service_task - Run service task for tasks that needed to be done
1470 * periodically
1471 */
1472static void mlx4_en_service_task(struct work_struct *work)
1473{
1474 struct delayed_work *delay = to_delayed_work(work);
1475 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1476 service_task);
1477 struct mlx4_en_dev *mdev = priv->mdev;
1478
1479 mutex_lock(&mdev->state_lock);
1480 if (mdev->device_up) {
dc8142ea
AV		 1481 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1482 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc 1483
07841f9d 1484 mlx4_en_recover_from_oom(priv);
b6c39bfc
AV		 1485 queue_delayed_work(mdev->workqueue, &priv->service_task,
1486 SERVICE_TASK_DELAY);
1487 }
1488 mutex_unlock(&mdev->state_lock);
1489}
1490
c27a02cd
YP		 1491static void mlx4_en_linkstate(struct work_struct *work)
1492{
1493 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1494 linkstate_task);
1495 struct mlx4_en_dev *mdev = priv->mdev;
1496 int linkstate = priv->link_state;
1497
1498 mutex_lock(&mdev->state_lock);
1499 /* If observable port state changed set carrier state and
1500 * report to system log */
1501 if (priv->last_link_state != linkstate) {
1502 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1503 en_info(priv, "Link Down\n");
c27a02cd
YP		 1504 netif_carrier_off(priv->dev);
1505 } else {
e5cc44b2 1506 en_info(priv, "Link Up\n");
c27a02cd
YP		 1507 netif_carrier_on(priv->dev);
1508 }
1509 }
1510 priv->last_link_state = linkstate;
1511 mutex_unlock(&mdev->state_lock);
1512}
1513
9e311e77
YA		 1514static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1515{
1516 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1517 int numa_node = priv->mdev->dev->numa_node;
9e311e77
YA		 1518
1519 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1520 return -ENOMEM;
1521
f36963c9
RR		 1522 cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1523 ring->affinity_mask);
1524 return 0;
9e311e77
YA		 1525}
1526
1527static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1528{
1529 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1530}
c27a02cd 1531
9ecc2d86
BB		 1532static void mlx4_en_init_recycle_ring(struct mlx4_en_priv *priv,
1533 int tx_ring_idx)
1534{
67f8b1dc
TT		 1535 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX_XDP][tx_ring_idx];
1536 int rr_index = tx_ring_idx;
9ecc2d86 1537
67f8b1dc
TT		 1538 tx_ring->free_tx_desc = mlx4_en_recycle_tx_desc;
1539 tx_ring->recycle_ring = priv->rx_ring[rr_index];
1540 en_dbg(DRV, priv, "Set tx_ring[%d][%d]->recycle_ring = rx_ring[%d]\n",
1541 TX_XDP, tx_ring_idx, rr_index);
9ecc2d86
BB		 1542}
1543
18cc42a3 1544int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1545{
1546 struct mlx4_en_priv *priv = netdev_priv(dev);
1547 struct mlx4_en_dev *mdev = priv->mdev;
1548 struct mlx4_en_cq *cq;
1549 struct mlx4_en_tx_ring *tx_ring;
c27a02cd 1550 int rx_index = 0;
c27a02cd 1551 int err = 0;
67f8b1dc 1552 int i, t;
c27a02cd 1553 int j;
1679200f 1554 u8 mc_list[16] = {0};
c27a02cd
YP		 1555
1556 if (priv->port_up) {
453a6082 1557 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1558 return 0;
1559 }
1560
6d199937
YP		 1561 INIT_LIST_HEAD(&priv->mc_list);
1562 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1563 INIT_LIST_HEAD(&priv->ethtool_list);
1564 memset(&priv->ethtool_rules[0], 0,
1565 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1566
c27a02cd
YP		 1567 /* Calculate Rx buf size */
1568 dev->mtu = min(dev->mtu, priv->max_mtu);
1569 mlx4_en_calc_rx_buf(dev);
453a6082 1570 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1571
c27a02cd 1572 /* Configure rx cq's and rings */
38aab07c
YP		 1573 err = mlx4_en_activate_rx_rings(priv);
1574 if (err) {
453a6082 1575 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1576 return err;
1577 }
c27a02cd 1578 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1579 cq = priv->rx_cq[i];
c27a02cd 1580
9e311e77
YA		 1581 err = mlx4_en_init_affinity_hint(priv, i);
1582 if (err) {
1583 en_err(priv, "Failed preparing IRQ affinity hint\n");
1584 goto cq_err;
1585 }
1586
76532d0c 1587 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1588 if (err) {
453a6082 1589 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1590 mlx4_en_free_affinity_hint(priv, i);
a4233304 1591 goto cq_err;
c27a02cd 1592 }
c3f2511f
IS		 1593
1594 for (j = 0; j < cq->size; j++) {
1595 struct mlx4_cqe *cqe = NULL;
1596
1597 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1598 priv->cqe_factor;
1599 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1600 }
1601
c27a02cd
YP		 1602 err = mlx4_en_set_cq_moder(priv, cq);
1603 if (err) {
1a91de28 1604 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1605 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1606 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1607 goto cq_err;
1608 }
1609 mlx4_en_arm_cq(priv, cq);
41d942d5 1610 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1611 ++rx_index;
1612 }
1613
ffe455ad
EE		 1614 /* Set qp number */
1615 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1616 err = mlx4_en_get_qp(priv);
1679200f 1617 if (err) {
ffe455ad 1618 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1619 goto cq_err;
1620 }
1621 mdev->mac_removed[priv->port] = 0;
1622
6de5f7f6
EBE		 1623 priv->counter_index =
1624 mlx4_get_default_counter_index(mdev->dev, priv->port);
1625
c27a02cd
YP		 1626 err = mlx4_en_config_rss_steer(priv);
1627 if (err) {
453a6082 1628 en_err(priv, "Failed configuring rss steering\n");
1679200f 1629 goto mac_err;
c27a02cd
YP		 1630 }
1631
cabdc8ee
HHZ		 1632 err = mlx4_en_create_drop_qp(priv);
1633 if (err)
1634 goto rss_err;
1635
c27a02cd 1636 /* Configure tx cq's and rings */
67f8b1dc
TT		 1637 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1638 u8 num_tx_rings_p_up = t == TX ? priv->num_tx_rings_p_up : 1;
c27a02cd 1639
67f8b1dc
TT		 1640 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1641 /* Configure cq */
1642 cq = priv->tx_cq[t][i];
1643 err = mlx4_en_activate_cq(priv, cq, i);
1644 if (err) {
1645 en_err(priv, "Failed allocating Tx CQ\n");
1646 goto tx_err;
1647 }
1648 err = mlx4_en_set_cq_moder(priv, cq);
1649 if (err) {
1650 en_err(priv, "Failed setting cq moderation parameters\n");
1651 mlx4_en_deactivate_cq(priv, cq);
1652 goto tx_err;
1653 }
1654 en_dbg(DRV, priv,
1655 "Resetting index of collapsed CQ:%d to -1\n", i);
1656 cq->buf->wqe_index = cpu_to_be16(0xffff);
1657
1658 /* Configure ring */
1659 tx_ring = priv->tx_ring[t][i];
1660 err = mlx4_en_activate_tx_ring(priv, tx_ring,
1661 cq->mcq.cqn,
1662 i / num_tx_rings_p_up);
1663 if (err) {
1664 en_err(priv, "Failed allocating Tx ring\n");
1665 mlx4_en_deactivate_cq(priv, cq);
1666 goto tx_err;
1667 }
1668 if (t != TX_XDP) {
1669 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
1670 tx_ring->recycle_ring = NULL;
1671 } else {
1672 mlx4_en_init_recycle_ring(priv, i);
1673 }
9ecc2d86 1674
67f8b1dc
TT		 1675 /* Arm CQ for TX completions */
1676 mlx4_en_arm_cq(priv, cq);
e22979d9 1677
67f8b1dc
TT		 1678 /* Set initial ownership of all Tx TXBBs to SW (1) */
1679 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1680 *((u32 *)(tx_ring->buf + j)) = 0xffffffff;
1681 }
c27a02cd
YP		 1682 }
1683
1684 /* Configure port */
1685 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1686 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1687 priv->prof->tx_pause,
1688 priv->prof->tx_ppp,
1689 priv->prof->rx_pause,
1690 priv->prof->rx_ppp);
c27a02cd 1691 if (err) {
48e551ff
YB		 1692 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1693 priv->port, err);
c27a02cd
YP		 1694 goto tx_err;
1695 }
1696 /* Set default qp number */
1697 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1698 if (err) {
453a6082 1699 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1700 goto tx_err;
1701 }
c27a02cd 1702
837052d0 1703 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1704 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1705 if (err) {
1706 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1707 err);
1708 goto tx_err;
1709 }
1710 }
1711
c27a02cd 1712 /* Init port */
453a6082 1713 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1714 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1715 if (err) {
453a6082 1716 en_err(priv, "Failed Initializing port\n");
1679200f 1717 goto tx_err;
c27a02cd
YP		 1718 }
1719
ba4b87ae
IS		 1720 /* Set Unicast and VXLAN steering rules */
1721 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1722 mlx4_en_set_rss_steer_rules(priv))
1723 mlx4_warn(mdev, "Failed setting steering rules\n");
1724
1679200f 1725 /* Attach rx QP to bradcast address */
c7bf7169 1726 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1727 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1728 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1729 priv->port, 0, MLX4_PROT_ETH,
1730 &priv->broadcast_id))
1679200f
YP		 1731 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1732
b5845f98
HX		 1733 /* Must redo promiscuous mode setup. */
1734 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1735
c27a02cd 1736 /* Schedule multicast task to populate multicast list */
0eb74fdd 1737 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1738
9737c6ab 1739 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
a831274a
AD		 1740 udp_tunnel_get_rx_info(dev);
1741
c27a02cd 1742 priv->port_up = true;
8d59de8f
ES		 1743
1744 /* Process all completions if exist to prevent
1745 * the queues freezing if they are full
1746 */
1747 for (i = 0; i < priv->rx_ring_num; i++)
1748 napi_schedule(&priv->rx_cq[i]->napi);
1749
a11faac7 1750 netif_tx_start_all_queues(dev);
3484aac1
AV		 1751 netif_device_attach(dev);
1752
c27a02cd
YP		 1753 return 0;
1754
c27a02cd 1755tx_err:
67f8b1dc
TT		 1756 if (t == MLX4_EN_NUM_TX_TYPES) {
1757 t--;
1758 i = priv->tx_ring_num[t];
1759 }
1760 while (t >= 0) {
1761 while (i--) {
1762 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1763 mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1764 }
1765 if (!t--)
1766 break;
1767 i = priv->tx_ring_num[t];
c27a02cd 1768 }
cabdc8ee
HHZ		 1769 mlx4_en_destroy_drop_qp(priv);
1770rss_err:
c27a02cd 1771 mlx4_en_release_rss_steer(priv);
1679200f 1772mac_err:
16a10ffd 1773 mlx4_en_put_qp(priv);
c27a02cd 1774cq_err:
9e311e77 1775 while (rx_index--) {
41d942d5 1776 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
f94813f3 1777 mlx4_en_free_affinity_hint(priv, rx_index);
9e311e77 1778 }
38aab07c 1779 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1780 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1781
1782 return err; /* need to close devices */
1783}
1784
1785
3484aac1 1786void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1787{
1788 struct mlx4_en_priv *priv = netdev_priv(dev);
1789 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1790 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1791 struct ethtool_flow_id *flow, *tmp_flow;
67f8b1dc 1792 int i, t;
1679200f 1793 u8 mc_list[16] = {0};
c27a02cd
YP		 1794
1795 if (!priv->port_up) {
453a6082 1796 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1797 return;
1798 }
c27a02cd 1799
0cc5c8bf
EE		 1800 /* close port*/
1801 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1802
c27a02cd
YP		 1803 /* Synchronize with tx routine */
1804 netif_tx_lock_bh(dev);
3484aac1
AV		 1805 if (detach)
1806 netif_device_detach(dev);
3c05f5ef 1807 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1808 netif_tx_unlock_bh(dev);
1809
3484aac1
AV		 1810 netif_tx_disable(dev);
1811
7f7bf160
ED		 1812 spin_lock_bh(&priv->stats_lock);
1813 mlx4_en_fold_software_stats(dev);
7c287380 1814 /* Set port as not active */
3c05f5ef 1815 priv->port_up = false;
7f7bf160
ED		 1816 spin_unlock_bh(&priv->stats_lock);
1817
6de5f7f6 1818 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
c27a02cd 1819
db0e7cba
AY		 1820 /* Promsicuous mode */
1821 if (mdev->dev->caps.steering_mode ==
1822 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1823 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1824 MLX4_EN_FLAG_MC_PROMISC);
1825 mlx4_flow_steer_promisc_remove(mdev->dev,
1826 priv->port,
f9162539 1827 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1828 mlx4_flow_steer_promisc_remove(mdev->dev,
1829 priv->port,
f9162539 1830 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1831 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1832 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1833
1834 /* Disable promiscouos mode */
1835 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1836 priv->port);
1837
1838 /* Disable Multicast promisc */
1839 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1840 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1841 priv->port);
1842 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1843 }
1844 }
1845
1679200f 1846 /* Detach All multicasts */
c7bf7169 1847 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1848 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1849 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1850 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1851 list_for_each_entry(mclist, &priv->curr_list, list) {
1852 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1853 mc_list[5] = priv->port;
1854 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1855 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1856 if (mclist->tunnel_reg_id)
1857 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1858 }
1859 mlx4_en_clear_list(dev);
6d199937
YP		 1860 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1861 list_del(&mclist->list);
1862 kfree(mclist);
1863 }
1864
1679200f
YP		 1865 /* Flush multicast filter */
1866 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1867
6efb5fac
HHZ		 1868 /* Remove flow steering rules for the port*/
1869 if (mdev->dev->caps.steering_mode ==
1870 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1871 ASSERT_RTNL();
1872 list_for_each_entry_safe(flow, tmp_flow,
1873 &priv->ethtool_list, list) {
1874 mlx4_flow_detach(mdev->dev, flow->id);
1875 list_del(&flow->list);
1876 }
1877 }
1878
cabdc8ee
HHZ		 1879 mlx4_en_destroy_drop_qp(priv);
1880
c27a02cd 1881 /* Free TX Rings */
67f8b1dc
TT		 1882 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
1883 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1884 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1885 mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1886 }
c27a02cd
YP		 1887 }
1888 msleep(10);
1889
67f8b1dc
TT		 1890 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1891 for (i = 0; i < priv->tx_ring_num[t]; i++)
1892 mlx4_en_free_tx_buf(dev, priv->tx_ring[t][i]);
c27a02cd 1893
ba4b87ae
IS		 1894 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1895 mlx4_en_delete_rss_steer_rules(priv);
1896
c27a02cd
YP		 1897 /* Free RSS qps */
1898 mlx4_en_release_rss_steer(priv);
1899
ffe455ad 1900 /* Unregister Mac address for the port */
16a10ffd 1901 mlx4_en_put_qp(priv);
5930e8d0 1902 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1903 mdev->mac_removed[priv->port] = 1;
ffe455ad 1904
c27a02cd
YP		 1905 /* Free RX Rings */
1906 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1907 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8 1908
f4a36751 1909 napi_synchronize(&cq->napi);
41d942d5 1910 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1911 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1912
1913 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1914 }
1915}
1916
1917static void mlx4_en_restart(struct work_struct *work)
1918{
1919 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1920 watchdog_task);
1921 struct mlx4_en_dev *mdev = priv->mdev;
1922 struct net_device *dev = priv->dev;
1923
453a6082 1924 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5 1925
0c5c3252 1926 rtnl_lock();
1e338db5
YP		 1927 mutex_lock(&mdev->state_lock);
1928 if (priv->port_up) {
3484aac1 1929 mlx4_en_stop_port(dev, 1);
1e338db5 1930 if (mlx4_en_start_port(dev))
453a6082 1931 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1932 }
1933 mutex_unlock(&mdev->state_lock);
0c5c3252 1934 rtnl_unlock();
c27a02cd
YP		 1935}
1936
b477ba62 1937static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1938{
1939 struct mlx4_en_priv *priv = netdev_priv(dev);
1940 struct mlx4_en_dev *mdev = priv->mdev;
67f8b1dc 1941 struct mlx4_en_tx_ring **tx_ring;
c27a02cd 1942 int i;
c27a02cd 1943
eb4b6788
TT		 1944 if (!mlx4_is_slave(mdev->dev))
1945 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
1946 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd 1947
c27a02cd 1948 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1949 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1950 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 1951 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
1952 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
1953 memset(&priv->rx_priority_flowstats, 0,
1954 sizeof(priv->rx_priority_flowstats));
1955 memset(&priv->tx_priority_flowstats, 0,
1956 sizeof(priv->tx_priority_flowstats));
b42de4d0 1957 memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
c27a02cd 1958
67f8b1dc
TT		 1959 tx_ring = priv->tx_ring[TX];
1960 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1961 tx_ring[i]->bytes = 0;
1962 tx_ring[i]->packets = 0;
1963 tx_ring[i]->tx_csum = 0;
1964 tx_ring[i]->tx_dropped = 0;
1965 tx_ring[i]->queue_stopped = 0;
1966 tx_ring[i]->wake_queue = 0;
1967 tx_ring[i]->tso_packets = 0;
1968 tx_ring[i]->xmit_more = 0;
c27a02cd
YP		 1969 }
1970 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1971 priv->rx_ring[i]->bytes = 0;
1972 priv->rx_ring[i]->packets = 0;
1973 priv->rx_ring[i]->csum_ok = 0;
1974 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1975 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1976 }
b477ba62
EE		 1977}
1978
1979static int mlx4_en_open(struct net_device *dev)
1980{
1981 struct mlx4_en_priv *priv = netdev_priv(dev);
1982 struct mlx4_en_dev *mdev = priv->mdev;
1983 int err = 0;
1984
1985 mutex_lock(&mdev->state_lock);
1986
1987 if (!mdev->device_up) {
1988 en_err(priv, "Cannot open - device down/disabled\n");
1989 err = -EBUSY;
1990 goto out;
1991 }
1992
1993 /* Reset HW statistics and SW counters */
1994 mlx4_en_clear_stats(dev);
c27a02cd 1995
c27a02cd
YP		 1996 err = mlx4_en_start_port(dev);
1997 if (err)
453a6082 1998 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1999
2000out:
2001 mutex_unlock(&mdev->state_lock);
2002 return err;
2003}
2004
2005
2006static int mlx4_en_close(struct net_device *dev)
2007{
2008 struct mlx4_en_priv *priv = netdev_priv(dev);
2009 struct mlx4_en_dev *mdev = priv->mdev;
2010
453a6082 2011 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 2012
2013 mutex_lock(&mdev->state_lock);
2014
3484aac1 2015 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 2016 netif_carrier_off(dev);
2017
2018 mutex_unlock(&mdev->state_lock);
2019 return 0;
2020}
2021
ec25bc04 2022static void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd 2023{
67f8b1dc 2024 int i, t;
c27a02cd 2025
1eb8c695 2026#ifdef CONFIG_RFS_ACCEL
1eb8c695
AV		 2027 priv->dev->rx_cpu_rmap = NULL;
2028#endif
2029
67f8b1dc
TT		 2030 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2031 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2032 if (priv->tx_ring[t] && priv->tx_ring[t][i])
2033 mlx4_en_destroy_tx_ring(priv,
2034 &priv->tx_ring[t][i]);
2035 if (priv->tx_cq[t] && priv->tx_cq[t][i])
2036 mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2037 }
c27a02cd
YP		 2038 }
2039
2040 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 2041 if (priv->rx_ring[i])
68355f71
TLSC		 2042 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2043 priv->prof->rx_ring_size, priv->stride);
41d942d5 2044 if (priv->rx_cq[i])
fe0af03c 2045 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 2046 }
044ca2a5 2047
c27a02cd
YP		 2048}
2049
ec25bc04 2050static int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 2051{
c27a02cd 2052 struct mlx4_en_port_profile *prof = priv->prof;
67f8b1dc 2053 int i, t;
163561a4 2054 int node;
87a5c389 2055
c27a02cd 2056 /* Create tx Rings */
67f8b1dc
TT		 2057 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2058 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2059 node = cpu_to_node(i % num_online_cpus());
2060 if (mlx4_en_create_cq(priv, &priv->tx_cq[t][i],
2061 prof->tx_ring_size, i, t, node))
2062 goto err;
2063
2064 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[t][i],
2065 prof->tx_ring_size,
2066 TXBB_SIZE, node, i))
2067 goto err;
2068 }
c27a02cd
YP		 2069 }
2070
2071 /* Create rx Rings */
2072 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2073 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2074 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2075 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2076 goto err;
2077
2078 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2079 prof->rx_ring_size, priv->stride,
2080 node))
c27a02cd
YP		 2081 goto err;
2082 }
2083
1eb8c695 2084#ifdef CONFIG_RFS_ACCEL
c66fa19c 2085 priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
1eb8c695
AV		 2086#endif
2087
c27a02cd
YP		 2088 return 0;
2089
2090err:
453a6082 2091 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2092 for (i = 0; i < priv->rx_ring_num; i++) {
2093 if (priv->rx_ring[i])
2094 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2095 prof->rx_ring_size,
2096 priv->stride);
2097 if (priv->rx_cq[i])
2098 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2099 }
67f8b1dc
TT		 2100 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2101 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2102 if (priv->tx_ring[t][i])
2103 mlx4_en_destroy_tx_ring(priv,
2104 &priv->tx_ring[t][i]);
2105 if (priv->tx_cq[t][i])
2106 mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2107 }
41d942d5 2108 }
c27a02cd
YP		 2109 return -ENOMEM;
2110}
2111
2112
ec25bc04
EE		 2113static int mlx4_en_copy_priv(struct mlx4_en_priv *dst,
2114 struct mlx4_en_priv *src,
2115 struct mlx4_en_port_profile *prof)
2116{
67f8b1dc
TT		 2117 int t;
2118
ec25bc04
EE		 2119 memcpy(&dst->hwtstamp_config, &prof->hwtstamp_config,
2120 sizeof(dst->hwtstamp_config));
2121 dst->num_tx_rings_p_up = src->mdev->profile.num_tx_rings_p_up;
ec25bc04
EE		 2122 dst->rx_ring_num = prof->rx_ring_num;
2123 dst->flags = prof->flags;
2124 dst->mdev = src->mdev;
2125 dst->port = src->port;
2126 dst->dev = src->dev;
2127 dst->prof = prof;
2128 dst->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2129 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2130
67f8b1dc
TT		 2131 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2132 dst->tx_ring_num[t] = prof->tx_ring_num[t];
2133 if (!dst->tx_ring_num[t])
2134 continue;
ec25bc04 2135
67f8b1dc
TT		 2136 dst->tx_ring[t] = kzalloc(sizeof(struct mlx4_en_tx_ring *) *
2137 MAX_TX_RINGS, GFP_KERNEL);
2138 if (!dst->tx_ring[t])
2139 goto err_free_tx;
2140
2141 dst->tx_cq[t] = kzalloc(sizeof(struct mlx4_en_cq *) *
2142 MAX_TX_RINGS, GFP_KERNEL);
2143 if (!dst->tx_cq[t]) {
2144 kfree(dst->tx_ring[t]);
2145 goto err_free_tx;
2146 }
ec25bc04 2147 }
67f8b1dc 2148
ec25bc04 2149 return 0;
67f8b1dc
TT		 2150
2151err_free_tx:
2152 while (t--) {
2153 kfree(dst->tx_ring[t]);
2154 kfree(dst->tx_cq[t]);
2155 }
2156 return -ENOMEM;
ec25bc04
EE		 2157}
2158
2159static void mlx4_en_update_priv(struct mlx4_en_priv *dst,
2160 struct mlx4_en_priv *src)
2161{
67f8b1dc 2162 int t;
ec25bc04
EE		 2163 memcpy(dst->rx_ring, src->rx_ring,
2164 sizeof(struct mlx4_en_rx_ring *) * src->rx_ring_num);
2165 memcpy(dst->rx_cq, src->rx_cq,
2166 sizeof(struct mlx4_en_cq *) * src->rx_ring_num);
2167 memcpy(&dst->hwtstamp_config, &src->hwtstamp_config,
2168 sizeof(dst->hwtstamp_config));
67f8b1dc
TT		 2169 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2170 dst->tx_ring_num[t] = src->tx_ring_num[t];
2171 dst->tx_ring[t] = src->tx_ring[t];
2172 dst->tx_cq[t] = src->tx_cq[t];
2173 }
ec25bc04 2174 dst->rx_ring_num = src->rx_ring_num;
ec25bc04
EE		 2175 memcpy(dst->prof, src->prof, sizeof(struct mlx4_en_port_profile));
2176}
2177
2178int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
2179 struct mlx4_en_priv *tmp,
2180 struct mlx4_en_port_profile *prof)
2181{
67f8b1dc
TT		 2182 int t;
2183
ec25bc04
EE		 2184 mlx4_en_copy_priv(tmp, priv, prof);
2185
2186 if (mlx4_en_alloc_resources(tmp)) {
2187 en_warn(priv,
2188 "%s: Resource allocation failed, using previous configuration\n",
2189 __func__);
67f8b1dc
TT		 2190 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2191 kfree(tmp->tx_ring[t]);
2192 kfree(tmp->tx_cq[t]);
2193 }
ec25bc04
EE		 2194 return -ENOMEM;
2195 }
2196 return 0;
2197}
2198
2199void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
2200 struct mlx4_en_priv *tmp)
2201{
2202 mlx4_en_free_resources(priv);
2203 mlx4_en_update_priv(priv, tmp);
2204}
2205
c27a02cd
YP		 2206void mlx4_en_destroy_netdev(struct net_device *dev)
2207{
2208 struct mlx4_en_priv *priv = netdev_priv(dev);
2209 struct mlx4_en_dev *mdev = priv->mdev;
67f8b1dc 2210 int t;
c27a02cd 2211
453a6082 2212 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2213
2214 /* Unregister device - this will close the port if it was up */
09d4d087
JP		 2215 if (priv->registered) {
2216 devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev,
2217 priv->port));
b4353708 2218 unregister_netdev(dev);
09d4d087 2219 }
c27a02cd
YP		 2220
2221 if (priv->allocated)
2222 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2223
2224 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2225 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2226 /* flush any pending task for this netdev */
2227 flush_workqueue(mdev->workqueue);
2228
90683061
EE		 2229 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2230 mlx4_en_remove_timestamp(mdev);
2231
c27a02cd
YP		 2232 /* Detach the netdev so tasks would not attempt to access it */
2233 mutex_lock(&mdev->state_lock);
2234 mdev->pndev[priv->port] = NULL;
5da03547 2235 mdev->upper[priv->port] = NULL;
c27a02cd 2236
30f56e3c
EE		 2237#ifdef CONFIG_RFS_ACCEL
2238 mlx4_en_cleanup_filters(priv);
2239#endif
2240
fe0af03c 2241 mlx4_en_free_resources(priv);
b6e01232 2242 mutex_unlock(&mdev->state_lock);
564c274c 2243
67f8b1dc
TT		 2244 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2245 kfree(priv->tx_ring[t]);
2246 kfree(priv->tx_cq[t]);
2247 }
bc6a4744 2248
b4353708 2249 free_netdev(dev);
c27a02cd
YP		 2250}
2251
2252static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2253{
2254 struct mlx4_en_priv *priv = netdev_priv(dev);
2255 struct mlx4_en_dev *mdev = priv->mdev;
2256 int err = 0;
2257
453a6082 2258 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2259 dev->mtu, new_mtu);
2260
67f8b1dc 2261 if (priv->tx_ring_num[TX_XDP] && MLX4_EN_EFF_MTU(new_mtu) > FRAG_SZ0) {
47a38e15
BB		 2262 en_err(priv, "MTU size:%d requires frags but XDP running\n",
2263 new_mtu);
2264 return -EOPNOTSUPP;
2265 }
c27a02cd
YP		 2266 dev->mtu = new_mtu;
2267
2268 if (netif_running(dev)) {
2269 mutex_lock(&mdev->state_lock);
2270 if (!mdev->device_up) {
2271 /* NIC is probably restarting - let watchdog task reset
2272 * the port */
453a6082 2273 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2274 } else {
3484aac1 2275 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2276 err = mlx4_en_start_port(dev);
2277 if (err) {
453a6082 2278 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2279 priv->port);
2280 queue_work(mdev->workqueue, &priv->watchdog_task);
2281 }
2282 }
2283 mutex_unlock(&mdev->state_lock);
2284 }
2285 return 0;
2286}
2287
100dbda8 2288static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2289{
2290 struct mlx4_en_priv *priv = netdev_priv(dev);
2291 struct mlx4_en_dev *mdev = priv->mdev;
2292 struct hwtstamp_config config;
2293
2294 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2295 return -EFAULT;
2296
2297 /* reserved for future extensions */
2298 if (config.flags)
2299 return -EINVAL;
2300
2301 /* device doesn't support time stamping */
2302 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2303 return -EINVAL;
2304
2305 /* TX HW timestamp */
2306 switch (config.tx_type) {
2307 case HWTSTAMP_TX_OFF:
2308 case HWTSTAMP_TX_ON:
2309 break;
2310 default:
2311 return -ERANGE;
2312 }
2313
2314 /* RX HW timestamp */
2315 switch (config.rx_filter) {
2316 case HWTSTAMP_FILTER_NONE:
2317 break;
2318 case HWTSTAMP_FILTER_ALL:
2319 case HWTSTAMP_FILTER_SOME:
2320 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2321 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2322 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2323 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2324 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2325 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2326 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2327 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2328 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2329 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2330 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2331 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2332 config.rx_filter = HWTSTAMP_FILTER_ALL;
2333 break;
2334 default:
2335 return -ERANGE;
2336 }
2337
7787fa66 2338 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2339 config.tx_type = HWTSTAMP_TX_OFF;
2340 config.rx_filter = HWTSTAMP_FILTER_NONE;
2341 }
2342
2343 return copy_to_user(ifr->ifr_data, &config,
2344 sizeof(config)) ? -EFAULT : 0;
2345}
2346
100dbda8
BH		 2347static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2348{
2349 struct mlx4_en_priv *priv = netdev_priv(dev);
2350
2351 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2352 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2353}
2354
ec693d47
AV		 2355static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2356{
2357 switch (cmd) {
2358 case SIOCSHWTSTAMP:
100dbda8
BH		 2359 return mlx4_en_hwtstamp_set(dev, ifr);
2360 case SIOCGHWTSTAMP:
2361 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2362 default:
2363 return -EOPNOTSUPP;
2364 }
2365}
2366
e38af4fa
HHZ		 2367static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2368 netdev_features_t features)
2369{
2370 struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2371 struct mlx4_en_dev *mdev = en_priv->mdev;
2372
2373 /* Since there is no support for separate RX C-TAG/S-TAG vlan accel
2374 * enable/disable make sure S-TAG flag is always in same state as
2375 * C-TAG.
2376 */
2377 if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2378 !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2379 features |= NETIF_F_HW_VLAN_STAG_RX;
2380 else
2381 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2382
2383 return features;
2384}
2385
60d6fe99
AV		 2386static int mlx4_en_set_features(struct net_device *netdev,
2387 netdev_features_t features)
2388{
2389 struct mlx4_en_priv *priv = netdev_priv(netdev);
f0df3503 2390 bool reset = false;
537f6f95
SM		 2391 int ret = 0;
2392
f0df3503
MM		 2393 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2394 en_info(priv, "Turn %s RX-FCS\n",
2395 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2396 reset = true;
2397 }
2398
78500b8c
MM		 2399 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2400 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2401
2402 en_info(priv, "Turn %s RX-ALL\n",
2403 ignore_fcs_value ? "ON" : "OFF");
2404 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2405 priv->port, ignore_fcs_value);
2406 if (ret)
2407 return ret;
2408 }
2409
537f6f95
SM		 2410 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2411 en_info(priv, "Turn %s RX vlan strip offload\n",
2412 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
f0df3503 2413 reset = true;
537f6f95 2414 }
60d6fe99 2415
cfb53f36
IS		 2416 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2417 en_info(priv, "Turn %s TX vlan strip offload\n",
2418 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2419
e38af4fa
HHZ		 2420 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2421 en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2422 (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2423
241a08c3
IS		 2424 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2425 en_info(priv, "Turn %s loopback\n",
2426 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2427 mlx4_en_update_loopback_state(netdev, features);
2428 }
79aeaccd 2429
f0df3503
MM		 2430 if (reset) {
2431 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2432 features);
2433 if (ret)
2434 return ret;
2435 }
60d6fe99 2436
f0df3503 2437 return 0;
60d6fe99
AV		 2438}
2439
8f7ba3ca
RE		 2440static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2441{
2442 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2443 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2444 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca 2445
6e522422 2446 if (is_multicast_ether_addr(mac))
8f7ba3ca
RE		 2447 return -EINVAL;
2448
2449 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2450}
2451
79aab093
MS		 2452static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2453 __be16 vlan_proto)
3f7fb021
RE		 2454{
2455 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2456 struct mlx4_en_dev *mdev = en_priv->mdev;
2457
b42959dc
MS		 2458 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos,
2459 vlan_proto);
3f7fb021
RE		 2460}
2461
cda373f4
IS		 2462static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2463 int max_tx_rate)
2464{
2465 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2466 struct mlx4_en_dev *mdev = en_priv->mdev;
2467
2468 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2469 max_tx_rate);
2470}
2471
e6b6a231
RE		 2472static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2473{
2474 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2475 struct mlx4_en_dev *mdev = en_priv->mdev;
2476
2477 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2478}
2479
2cccb9e4
RE		 2480static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2481{
2482 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2483 struct mlx4_en_dev *mdev = en_priv->mdev;
2484
2485 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2486}
8f7ba3ca 2487
948e306d
RE		 2488static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2489{
2490 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2491 struct mlx4_en_dev *mdev = en_priv->mdev;
2492
2493 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2494}
84c86403 2495
62a89055
EBE		 2496static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2497 struct ifla_vf_stats *vf_stats)
2498{
2499 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2500 struct mlx4_en_dev *mdev = en_priv->mdev;
2501
2502 return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2503}
2504
84c86403
HHZ		 2505#define PORT_ID_BYTE_LEN 8
2506static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2507 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2508{
2509 struct mlx4_en_priv *priv = netdev_priv(dev);
2510 struct mlx4_dev *mdev = priv->mdev->dev;
2511 int i;
2512 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2513
2514 if (!phys_port_id)
2515 return -EOPNOTSUPP;
2516
2517 ppid->id_len = sizeof(phys_port_id);
2518 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2519 ppid->id[i] = phys_port_id & 0xff;
2520 phys_port_id >>= 8;
2521 }
2522 return 0;
2523}
2524
1b136de1
OG		 2525static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2526{
2527 int ret;
2528 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2529 vxlan_add_task);
2530
2531 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2532 if (ret)
2533 goto out;
2534
2535 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2536 VXLAN_STEER_BY_OUTER_MAC, 1);
2537out:
f4a1edd5 2538 if (ret) {
1b136de1 2539 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2540 return;
2541 }
2542
2543 /* set offloads */
09067122
AD		 2544 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2545 NETIF_F_RXCSUM |
2546 NETIF_F_TSO | NETIF_F_TSO6 |
2547 NETIF_F_GSO_UDP_TUNNEL |
3c9346b2
AD		 2548 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2549 NETIF_F_GSO_PARTIAL;
1b136de1
OG		 2550}
2551
2552static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2553{
2554 int ret;
2555 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2556 vxlan_del_task);
f4a1edd5 2557 /* unset offloads */
09067122
AD		 2558 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2559 NETIF_F_RXCSUM |
2560 NETIF_F_TSO | NETIF_F_TSO6 |
2561 NETIF_F_GSO_UDP_TUNNEL |
3c9346b2
AD		 2562 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2563 NETIF_F_GSO_PARTIAL);
1b136de1
OG		 2564
2565 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2566 VXLAN_STEER_BY_OUTER_MAC, 0);
2567 if (ret)
2568 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2569
2570 priv->vxlan_port = 0;
2571}
2572
2573static void mlx4_en_add_vxlan_port(struct net_device *dev,
a831274a 2574 struct udp_tunnel_info *ti)
1b136de1
OG		 2575{
2576 struct mlx4_en_priv *priv = netdev_priv(dev);
a831274a 2577 __be16 port = ti->port;
1b136de1
OG		 2578 __be16 current_port;
2579
a831274a 2580 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
1b136de1
OG		 2581 return;
2582
a831274a
AD		 2583 if (ti->sa_family != AF_INET)
2584 return;
2585
2586 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2587 return;
2588
2589 current_port = priv->vxlan_port;
2590 if (current_port && current_port != port) {
2591 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2592 ntohs(current_port), ntohs(port));
2593 return;
2594 }
2595
2596 priv->vxlan_port = port;
2597 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2598}
2599
2600static void mlx4_en_del_vxlan_port(struct net_device *dev,
a831274a 2601 struct udp_tunnel_info *ti)
1b136de1
OG		 2602{
2603 struct mlx4_en_priv *priv = netdev_priv(dev);
a831274a 2604 __be16 port = ti->port;
1b136de1
OG		 2605 __be16 current_port;
2606
a831274a 2607 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
1b136de1
OG		 2608 return;
2609
a831274a
AD		 2610 if (ti->sa_family != AF_INET)
2611 return;
2612
2613 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2614 return;
2615
2616 current_port = priv->vxlan_port;
2617 if (current_port != port) {
2618 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2619 return;
2620 }
2621
2622 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2623}
956bdab2 2624
5f35227e
JG		 2625static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2626 struct net_device *dev,
2627 netdev_features_t features)
956bdab2 2628{
8cb65d00 2629 features = vlan_features_check(skb, features);
09067122
AD		 2630 features = vxlan_features_check(skb, features);
2631
2632 /* The ConnectX-3 doesn't support outer IPv6 checksums but it does
2633 * support inner IPv6 checksums and segmentation so we need to
2634 * strip that feature if this is an IPv6 encapsulated frame.
2635 */
2636 if (skb->encapsulation &&
a547224d
AD		 2637 (skb->ip_summed == CHECKSUM_PARTIAL)) {
2638 struct mlx4_en_priv *priv = netdev_priv(dev);
2639
2640 if (!priv->vxlan_port ||
2641 (ip_hdr(skb)->version != 4) ||
2642 (udp_hdr(skb)->dest != priv->vxlan_port))
2643 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2644 }
09067122
AD		 2645
2646 return features;
956bdab2 2647}
1b136de1 2648
de1cf8a7 2649static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2650{
2651 struct mlx4_en_priv *priv = netdev_priv(dev);
67f8b1dc 2652 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][queue_index];
c10e4fc6
OG		 2653 struct mlx4_update_qp_params params;
2654 int err;
2655
2656 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2657 return -EOPNOTSUPP;
2658
2659 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2660 if (maxrate >> 12) {
2661 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2662 params.rate_val = maxrate / 1000;
2663 } else if (maxrate) {
2664 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2665 params.rate_val = maxrate;
2666 } else { /* zero serves to revoke the QP rate-limitation */
2667 params.rate_unit = 0;
2668 params.rate_val = 0;
2669 }
2670
2671 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2672 &params);
2673 return err;
2674}
2675
47a38e15
BB		 2676static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog)
2677{
2678 struct mlx4_en_priv *priv = netdev_priv(dev);
d576acf0 2679 struct mlx4_en_dev *mdev = priv->mdev;
67f8b1dc 2680 struct mlx4_en_port_profile new_prof;
47a38e15 2681 struct bpf_prog *old_prog;
67f8b1dc
TT		 2682 struct mlx4_en_priv *tmp;
2683 int tx_changed = 0;
47a38e15 2684 int xdp_ring_num;
d576acf0
BB		 2685 int port_up = 0;
2686 int err;
47a38e15
BB		 2687 int i;
2688
17bedab2
MKL		 2689 if (prog && prog->xdp_adjust_head) {
2690 en_err(priv, "Does not support bpf_xdp_adjust_head()\n");
2691 return -EOPNOTSUPP;
2692 }
2693
67f8b1dc 2694 xdp_ring_num = prog ? priv->rx_ring_num : 0;
47a38e15 2695
d576acf0
BB		 2696 /* No need to reconfigure buffers when simply swapping the
2697 * program for a new one.
2698 */
67f8b1dc 2699 if (priv->tx_ring_num[TX_XDP] == xdp_ring_num) {
d576acf0
BB		 2700 if (prog) {
2701 prog = bpf_prog_add(prog, priv->rx_ring_num - 1);
2702 if (IS_ERR(prog))
2703 return PTR_ERR(prog);
2704 }
326fe02d 2705 mutex_lock(&mdev->state_lock);
d576acf0 2706 for (i = 0; i < priv->rx_ring_num; i++) {
326fe02d
BB		 2707 old_prog = rcu_dereference_protected(
2708 priv->rx_ring[i]->xdp_prog,
2709 lockdep_is_held(&mdev->state_lock));
2710 rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog);
d576acf0
BB		 2711 if (old_prog)
2712 bpf_prog_put(old_prog);
2713 }
326fe02d 2714 mutex_unlock(&mdev->state_lock);
d576acf0
BB		 2715 return 0;
2716 }
2717
47a38e15
BB		 2718 if (priv->num_frags > 1) {
2719 en_err(priv, "Cannot set XDP if MTU requires multiple frags\n");
2720 return -EOPNOTSUPP;
2721 }
2722
67f8b1dc
TT		 2723 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2724 if (!tmp)
2725 return -ENOMEM;
9ecc2d86 2726
47a38e15
BB		 2727 if (prog) {
2728 prog = bpf_prog_add(prog, priv->rx_ring_num - 1);
67f8b1dc
TT		 2729 if (IS_ERR(prog)) {
2730 err = PTR_ERR(prog);
2731 goto out;
2732 }
47a38e15
BB		 2733 }
2734
d576acf0 2735 mutex_lock(&mdev->state_lock);
67f8b1dc
TT		 2736 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
2737 new_prof.tx_ring_num[TX_XDP] = xdp_ring_num;
2738
2739 if (priv->tx_ring_num[TX] + xdp_ring_num > MAX_TX_RINGS) {
2740 tx_changed = 1;
2741 new_prof.tx_ring_num[TX] =
2742 MAX_TX_RINGS - ALIGN(xdp_ring_num, MLX4_EN_NUM_UP);
2743 en_warn(priv, "Reducing the number of TX rings, to not exceed the max total rings number.\n");
2744 }
2745
2746 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
c540594f
DB		 2747 if (err) {
2748 if (prog)
2749 bpf_prog_sub(prog, priv->rx_ring_num - 1);
67f8b1dc 2750 goto unlock_out;
c540594f 2751 }
67f8b1dc 2752
d576acf0
BB		 2753 if (priv->port_up) {
2754 port_up = 1;
2755 mlx4_en_stop_port(dev, 1);
2756 }
2757
67f8b1dc
TT		 2758 mlx4_en_safe_replace_resources(priv, tmp);
2759 if (tx_changed)
2760 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
47a38e15 2761
47a38e15 2762 for (i = 0; i < priv->rx_ring_num; i++) {
326fe02d
BB		 2763 old_prog = rcu_dereference_protected(
2764 priv->rx_ring[i]->xdp_prog,
2765 lockdep_is_held(&mdev->state_lock));
2766 rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog);
47a38e15
BB		 2767 if (old_prog)
2768 bpf_prog_put(old_prog);
2769 }
2770
d576acf0
BB		 2771 if (port_up) {
2772 err = mlx4_en_start_port(dev);
2773 if (err) {
2774 en_err(priv, "Failed starting port %d for XDP change\n",
2775 priv->port);
2776 queue_work(mdev->workqueue, &priv->watchdog_task);
2777 }
2778 }
2779
67f8b1dc 2780unlock_out:
d576acf0 2781 mutex_unlock(&mdev->state_lock);
67f8b1dc
TT		 2782out:
2783 kfree(tmp);
2784 return err;
47a38e15
BB		 2785}
2786
2787static bool mlx4_xdp_attached(struct net_device *dev)
2788{
2789 struct mlx4_en_priv *priv = netdev_priv(dev);
2790
67f8b1dc 2791 return !!priv->tx_ring_num[TX_XDP];
47a38e15
BB		 2792}
2793
2794static int mlx4_xdp(struct net_device *dev, struct netdev_xdp *xdp)
2795{
2796 switch (xdp->command) {
2797 case XDP_SETUP_PROG:
2798 return mlx4_xdp_set(dev, xdp->prog);
2799 case XDP_QUERY_PROG:
2800 xdp->prog_attached = mlx4_xdp_attached(dev);
2801 return 0;
2802 default:
2803 return -EINVAL;
2804 }
2805}
2806
3addc568
SH		 2807static const struct net_device_ops mlx4_netdev_ops = {
2808 .ndo_open = mlx4_en_open,
2809 .ndo_stop = mlx4_en_close,
2810 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2811 .ndo_select_queue = mlx4_en_select_queue,
9ed17db1 2812 .ndo_get_stats64 = mlx4_en_get_stats64,
0eb74fdd 2813 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2814 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2815 .ndo_validate_addr = eth_validate_addr,
3addc568 2816 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2817 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2818 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2819 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2820 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2821#ifdef CONFIG_NET_POLL_CONTROLLER
2822 .ndo_poll_controller = mlx4_en_netpoll,
2823#endif
60d6fe99 2824 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2825 .ndo_fix_features = mlx4_en_fix_features,
e4c6734e 2826 .ndo_setup_tc = __mlx4_en_setup_tc,
1eb8c695
AV		 2827#ifdef CONFIG_RFS_ACCEL
2828 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
9e77a2b8 2829#endif
84c86403 2830 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a831274a
AD		 2831 .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2832 .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
5f35227e 2833 .ndo_features_check = mlx4_en_features_check,
c10e4fc6 2834 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
47a38e15 2835 .ndo_xdp = mlx4_xdp,
3addc568
SH		 2836};
2837
8f7ba3ca
RE		 2838static const struct net_device_ops mlx4_netdev_ops_master = {
2839 .ndo_open = mlx4_en_open,
2840 .ndo_stop = mlx4_en_close,
2841 .ndo_start_xmit = mlx4_en_xmit,
2842 .ndo_select_queue = mlx4_en_select_queue,
9ed17db1 2843 .ndo_get_stats64 = mlx4_en_get_stats64,
8f7ba3ca
RE		 2844 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2845 .ndo_set_mac_address = mlx4_en_set_mac,
2846 .ndo_validate_addr = eth_validate_addr,
2847 .ndo_change_mtu = mlx4_en_change_mtu,
2848 .ndo_tx_timeout = mlx4_en_tx_timeout,
2849 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2850 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2851 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2852 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2853 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2854 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2855 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
62a89055 2856 .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2cccb9e4 2857 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2858#ifdef CONFIG_NET_POLL_CONTROLLER
2859 .ndo_poll_controller = mlx4_en_netpoll,
2860#endif
2861 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2862 .ndo_fix_features = mlx4_en_fix_features,
e4c6734e 2863 .ndo_setup_tc = __mlx4_en_setup_tc,
8f7ba3ca
RE		 2864#ifdef CONFIG_RFS_ACCEL
2865 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2866#endif
84c86403 2867 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a831274a
AD		 2868 .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2869 .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
5f35227e 2870 .ndo_features_check = mlx4_en_features_check,
c10e4fc6 2871 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
47a38e15 2872 .ndo_xdp = mlx4_xdp,
8f7ba3ca
RE		 2873};
2874
5da03547
MS		 2875struct mlx4_en_bond {
2876 struct work_struct work;
2877 struct mlx4_en_priv *priv;
2878 int is_bonded;
2879 struct mlx4_port_map port_map;
2880};
2881
2882static void mlx4_en_bond_work(struct work_struct *work)
2883{
2884 struct mlx4_en_bond *bond = container_of(work,
2885 struct mlx4_en_bond,
2886 work);
2887 int err = 0;
2888 struct mlx4_dev *dev = bond->priv->mdev->dev;
2889
2890 if (bond->is_bonded) {
2891 if (!mlx4_is_bonded(dev)) {
2892 err = mlx4_bond(dev);
2893 if (err)
2894 en_err(bond->priv, "Fail to bond device\n");
2895 }
2896 if (!err) {
2897 err = mlx4_port_map_set(dev, &bond->port_map);
2898 if (err)
2899 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2900 bond->port_map.port1,
2901 bond->port_map.port2,
2902 err);
2903 }
2904 } else if (mlx4_is_bonded(dev)) {
2905 err = mlx4_unbond(dev);
2906 if (err)
2907 en_err(bond->priv, "Fail to unbond device\n");
2908 }
2909 dev_put(bond->priv->dev);
2910 kfree(bond);
2911}
2912
2913static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2914 u8 v2p_p1, u8 v2p_p2)
2915{
2916 struct mlx4_en_bond *bond = NULL;
2917
2918 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2919 if (!bond)
2920 return -ENOMEM;
2921
2922 INIT_WORK(&bond->work, mlx4_en_bond_work);
2923 bond->priv = priv;
2924 bond->is_bonded = is_bonded;
2925 bond->port_map.port1 = v2p_p1;
2926 bond->port_map.port2 = v2p_p2;
2927 dev_hold(priv->dev);
2928 queue_work(priv->mdev->workqueue, &bond->work);
2929 return 0;
2930}
2931
2932int mlx4_en_netdev_event(struct notifier_block *this,
2933 unsigned long event, void *ptr)
2934{
2935 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2936 u8 port = 0;
2937 struct mlx4_en_dev *mdev;
2938 struct mlx4_dev *dev;
2939 int i, num_eth_ports = 0;
2940 bool do_bond = true;
2941 struct mlx4_en_priv *priv;
2942 u8 v2p_port1 = 0;
2943 u8 v2p_port2 = 0;
2944
2945 if (!net_eq(dev_net(ndev), &init_net))
2946 return NOTIFY_DONE;
2947
2948 mdev = container_of(this, struct mlx4_en_dev, nb);
2949 dev = mdev->dev;
2950
2951 /* Go into this mode only when two network devices set on two ports
2952 * of the same mlx4 device are slaves of the same bonding master
2953 */
2954 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2955 ++num_eth_ports;
2956 if (!port && (mdev->pndev[i] == ndev))
2957 port = i;
2958 mdev->upper[i] = mdev->pndev[i] ?
2959 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2960 /* condition not met: network device is a slave */
2961 if (!mdev->upper[i])
2962 do_bond = false;
2963 if (num_eth_ports < 2)
2964 continue;
2965 /* condition not met: same master */
2966 if (mdev->upper[i] != mdev->upper[i-1])
2967 do_bond = false;
2968 }
2969 /* condition not met: 2 salves */
2970 do_bond = (num_eth_ports == 2) ? do_bond : false;
2971
2972 /* handle only events that come with enough info */
2973 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2974 return NOTIFY_DONE;
2975
2976 priv = netdev_priv(ndev);
2977 if (do_bond) {
2978 struct netdev_notifier_bonding_info *notifier_info = ptr;
2979 struct netdev_bonding_info *bonding_info =
2980 &notifier_info->bonding_info;
2981
2982 /* required mode 1, 2 or 4 */
2983 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2984 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2985 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2986 do_bond = false;
2987
2988 /* require exactly 2 slaves */
2989 if (bonding_info->master.num_slaves != 2)
2990 do_bond = false;
2991
2992 /* calc v2p */
2993 if (do_bond) {
2994 if (bonding_info->master.bond_mode ==
2995 BOND_MODE_ACTIVEBACKUP) {
2996 /* in active-backup mode virtual ports are
2997 * mapped to the physical port of the active
2998 * slave */
2999 if (bonding_info->slave.state ==
3000 BOND_STATE_BACKUP) {
3001 if (port == 1) {
3002 v2p_port1 = 2;
3003 v2p_port2 = 2;
3004 } else {
3005 v2p_port1 = 1;
3006 v2p_port2 = 1;
3007 }
3008 } else { /* BOND_STATE_ACTIVE */
3009 if (port == 1) {
3010 v2p_port1 = 1;
3011 v2p_port2 = 1;
3012 } else {
3013 v2p_port1 = 2;
3014 v2p_port2 = 2;
3015 }
3016 }
3017 } else { /* Active-Active */
3018 /* in active-active mode a virtual port is
3019 * mapped to the native physical port if and only
3020 * if the physical port is up */
3021 __s8 link = bonding_info->slave.link;
3022
3023 if (port == 1)
3024 v2p_port2 = 2;
3025 else
3026 v2p_port1 = 1;
3027 if ((link == BOND_LINK_UP) ||
3028 (link == BOND_LINK_FAIL)) {
3029 if (port == 1)
3030 v2p_port1 = 1;
3031 else
3032 v2p_port2 = 2;
3033 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
3034 if (port == 1)
3035 v2p_port1 = 2;
3036 else
3037 v2p_port2 = 1;
3038 }
3039 }
3040 }
3041 }
3042
3043 mlx4_en_queue_bond_work(priv, do_bond,
3044 v2p_port1, v2p_port2);
3045
3046 return NOTIFY_DONE;
3047}
3048
0b131561
MB		 3049void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
3050 struct mlx4_en_stats_bitmap *stats_bitmap,
3051 u8 rx_ppp, u8 rx_pause,
3052 u8 tx_ppp, u8 tx_pause)
3053{
b42de4d0 3054 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
0b131561
MB		 3055
3056 if (!mlx4_is_slave(dev) &&
3057 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
3058 mutex_lock(&stats_bitmap->mutex);
3059 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
3060
3061 if (rx_ppp)
3062 bitmap_set(stats_bitmap->bitmap, last_i,
3063 NUM_FLOW_PRIORITY_STATS_RX);
3064 last_i += NUM_FLOW_PRIORITY_STATS_RX;
3065
3066 if (rx_pause && !(rx_ppp))
3067 bitmap_set(stats_bitmap->bitmap, last_i,
3068 NUM_FLOW_STATS_RX);
3069 last_i += NUM_FLOW_STATS_RX;
3070
3071 if (tx_ppp)
3072 bitmap_set(stats_bitmap->bitmap, last_i,
3073 NUM_FLOW_PRIORITY_STATS_TX);
3074 last_i += NUM_FLOW_PRIORITY_STATS_TX;
3075
3076 if (tx_pause && !(tx_ppp))
3077 bitmap_set(stats_bitmap->bitmap, last_i,
3078 NUM_FLOW_STATS_TX);
3079 last_i += NUM_FLOW_STATS_TX;
3080
3081 mutex_unlock(&stats_bitmap->mutex);
3082 }
3083}
3084
6fcd2735 3085void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 3086 struct mlx4_en_stats_bitmap *stats_bitmap,
3087 u8 rx_ppp, u8 rx_pause,
3088 u8 tx_ppp, u8 tx_pause)
ffa88f37 3089{
6fcd2735
EBE		 3090 int last_i = 0;
3091
3da8a36c
EBE		 3092 mutex_init(&stats_bitmap->mutex);
3093 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 3094
3095 if (mlx4_is_slave(dev)) {
3da8a36c 3096 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3097 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 3098 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3099 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 3100 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3101 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 3102 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3103 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 3104 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3105 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 3106 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 3107 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
3108 } else {
3da8a36c 3109 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 3110 }
6fcd2735 3111 last_i += NUM_MAIN_STATS;
ffa88f37 3112
3da8a36c 3113 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 3114 last_i += NUM_PORT_STATS;
ffa88f37 3115
b42de4d0
EBE		 3116 if (mlx4_is_master(dev))
3117 bitmap_set(stats_bitmap->bitmap, last_i,
3118 NUM_PF_STATS);
3119 last_i += NUM_PF_STATS;
3120
0b131561
MB		 3121 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
3122 rx_ppp, rx_pause,
3123 tx_ppp, tx_pause);
3124 last_i += NUM_FLOW_STATS;
3125
6fcd2735 3126 if (!mlx4_is_slave(dev))
3da8a36c 3127 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
15fca2c8
TT		 3128 last_i += NUM_PKT_STATS;
3129
3130 bitmap_set(stats_bitmap->bitmap, last_i, NUM_XDP_STATS);
3131 last_i += NUM_XDP_STATS;
ffa88f37
EBE		 3132}
3133
c27a02cd
YP		 3134int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
3135 struct mlx4_en_port_profile *prof)
3136{
3137 struct net_device *dev;
3138 struct mlx4_en_priv *priv;
67f8b1dc 3139 int i, t;
c27a02cd
YP		 3140 int err;
3141
f1593d22 3142 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 3143 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 3144 if (dev == NULL)
c27a02cd 3145 return -ENOMEM;
c27a02cd 3146
67f8b1dc 3147 netif_set_real_num_tx_queues(dev, prof->tx_ring_num[TX]);
d317966b
AV		 3148 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
3149
872bf2fb 3150 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 3151 dev->dev_port = port - 1;
c27a02cd
YP		 3152
3153 /*
3154 * Initialize driver private data
3155 */
3156
3157 priv = netdev_priv(dev);
3158 memset(priv, 0, sizeof(struct mlx4_en_priv));
6de5f7f6 3159 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
207af6c5
EE		 3160 spin_lock_init(&priv->stats_lock);
3161 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
3162 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
3163 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
3164 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
3165 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
207af6c5
EE		 3166 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
3167 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
207af6c5
EE		 3168#ifdef CONFIG_RFS_ACCEL
3169 INIT_LIST_HEAD(&priv->filters);
3170 spin_lock_init(&priv->filters_lock);
3171#endif
3172
c27a02cd
YP		 3173 priv->dev = dev;
3174 priv->mdev = mdev;
ebf8c9aa 3175 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 3176 priv->prof = prof;
3177 priv->port = port;
3178 priv->port_up = false;
c27a02cd 3179 priv->flags = prof->flags;
0fef9d03 3180 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 3181 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
3182 MLX4_WQE_CTRL_SOLICITED);
d317966b 3183 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
fbc6daf1 3184 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 3185 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 3186
67f8b1dc
TT		 3187 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
3188 priv->tx_ring_num[t] = prof->tx_ring_num[t];
3189 if (!priv->tx_ring_num[t])
3190 continue;
3191
3192 priv->tx_ring[t] = kzalloc(sizeof(struct mlx4_en_tx_ring *) *
3193 MAX_TX_RINGS, GFP_KERNEL);
3194 if (!priv->tx_ring[t]) {
3195 err = -ENOMEM;
3196 goto err_free_tx;
3197 }
3198 priv->tx_cq[t] = kzalloc(sizeof(struct mlx4_en_cq *) *
3199 MAX_TX_RINGS, GFP_KERNEL);
3200 if (!priv->tx_cq[t]) {
3201 kfree(priv->tx_ring[t]);
3202 err = -ENOMEM;
3203 goto out;
3204 }
bc6a4744 3205 }
c27a02cd 3206 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 3207 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 3208 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 3209 priv->mac_index = -1;
3210 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 3211#ifdef CONFIG_MLX4_EN_DCB
540b3a39 3212 if (!mlx4_is_slave(priv->mdev->dev)) {
564ed9b1
TT		 3213 priv->dcbx_cap = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_HOST |
3214 DCB_CAP_DCBX_VER_IEEE;
af7d5185 3215 priv->flags |= MLX4_EN_DCB_ENABLED;
564ed9b1 3216 priv->cee_config.pfc_state = false;
af7d5185 3217
564ed9b1
TT		 3218 for (i = 0; i < MLX4_EN_NUM_UP; i++)
3219 priv->cee_config.dcb_pfc[i] = pfc_disabled;
af7d5185 3220
3742cc65 3221 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 3222 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
3223 } else {
3224 en_info(priv, "enabling only PFC DCB ops\n");
3225 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
3226 }
3227 }
564c274c 3228#endif
c27a02cd 3229
c07cb4b0
YB		 3230 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
3231 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 3232
c27a02cd
YP		 3233 /* Query for default mac and max mtu */
3234 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 3235
f8c6455b
SM		 3236 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
3237 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
3238 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
3239
6bbb6d99
YB		 3240 /* Set default MAC */
3241 dev->addr_len = ETH_ALEN;
3242 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
3243 if (!is_valid_ether_addr(dev->dev_addr)) {
2b3ddf27
JM		 3244 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
3245 priv->port, dev->dev_addr);
3246 err = -EINVAL;
3247 goto out;
3248 } else if (mlx4_is_slave(priv->mdev->dev) &&
3249 (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
3250 /* Random MAC was assigned in mlx4_slave_cap
3251 * in mlx4_core module
3252 */
3253 dev->addr_assign_type |= NET_ADDR_RANDOM;
3254 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
c27a02cd
YP		 3255 }
3256
2695bab2 3257 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 3258
c27a02cd
YP		 3259 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
3260 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
3261 err = mlx4_en_alloc_resources(priv);
3262 if (err)
3263 goto out;
3264
ec693d47
AV		 3265 /* Initialize time stamping config */
3266 priv->hwtstamp_config.flags = 0;
3267 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
3268 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3269
c27a02cd
YP		 3270 /* Allocate page for receive rings */
3271 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
73898db0 3272 MLX4_EN_PAGE_SIZE);
c27a02cd 3273 if (err) {
453a6082 3274 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 3275 goto out;
3276 }
3277 priv->allocated = 1;
3278
c27a02cd
YP		 3279 /*
3280 * Initialize netdev entry points
3281 */
8f7ba3ca
RE		 3282 if (mlx4_is_master(priv->mdev->dev))
3283 dev->netdev_ops = &mlx4_netdev_ops_master;
3284 else
3285 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 3286 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
67f8b1dc 3287 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
1eb63a28 3288 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 3289
7ad24ea4 3290 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 3291
c27a02cd
YP		 3292 /*
3293 * Set driver features
3294 */
c8c64cff
MM		 3295 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3296 if (mdev->LSO_support)
3297 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
3298
3299 dev->vlan_features = dev->hw_features;
3300
ad86107f 3301 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 3302 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 3303 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3304 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 3305 dev->hw_features |= NETIF_F_LOOPBACK |
3306 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 3307
e38af4fa
HHZ		 3308 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
3309 dev->features |= NETIF_F_HW_VLAN_STAG_RX |
3310 NETIF_F_HW_VLAN_STAG_FILTER;
3311 dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
3312 }
3313
3314 if (mlx4_is_slave(mdev->dev)) {
0815fe3a 3315 bool vlan_offload_disabled;
e38af4fa
HHZ		 3316 int phv;
3317
3318 err = get_phv_bit(mdev->dev, port, &phv);
3319 if (!err && phv) {
3320 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3321 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
3322 }
0815fe3a
MS		 3323 err = mlx4_get_is_vlan_offload_disabled(mdev->dev, port,
3324 &vlan_offload_disabled);
3325 if (!err && vlan_offload_disabled) {
3326 dev->hw_features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3327 NETIF_F_HW_VLAN_CTAG_RX |
3328 NETIF_F_HW_VLAN_STAG_TX |
3329 NETIF_F_HW_VLAN_STAG_RX);
3330 dev->features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3331 NETIF_F_HW_VLAN_CTAG_RX |
3332 NETIF_F_HW_VLAN_STAG_TX |
3333 NETIF_F_HW_VLAN_STAG_RX);
3334 }
e38af4fa
HHZ		 3335 } else {
3336 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
3337 !(mdev->dev->caps.flags2 &
3338 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
3339 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3340 }
3341
f0df3503
MM		 3342 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
3343 dev->hw_features |= NETIF_F_RXFCS;
3344
78500b8c
MM		 3345 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
3346 dev->hw_features |= NETIF_F_RXALL;
3347
1eb8c695 3348 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 3349 MLX4_STEERING_MODE_DEVICE_MANAGED &&
3350 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 3351 dev->hw_features |= NETIF_F_NTUPLE;
3352
cc5387f7
YB		 3353 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
3354 dev->priv_flags |= IFF_UNICAST_FLT;
3355
947cbb0a
EP		 3356 /* Setting a default hash function value */
3357 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
3358 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3359 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
3360 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
3361 } else {
3362 en_warn(priv,
3363 "No RSS hash capabilities exposed, using Toeplitz\n");
3364 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3365 }
3366
925ab1aa 3367 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3c9346b2
AD		 3368 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3369 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3370 NETIF_F_GSO_PARTIAL;
3371 dev->features |= NETIF_F_GSO_UDP_TUNNEL |
3372 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3373 NETIF_F_GSO_PARTIAL;
3374 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
925ab1aa
EE		 3375 }
3376
b80f71f5
JW		 3377 /* MTU range: 46 - hw-specific max */
3378 dev->min_mtu = MLX4_EN_MIN_MTU;
3379 dev->max_mtu = priv->max_mtu;
3380
c27a02cd 3381 mdev->pndev[port] = dev;
5da03547 3382 mdev->upper[port] = NULL;
c27a02cd
YP		 3383
3384 netif_carrier_off(dev);
4801ae70
EE		 3385 mlx4_en_set_default_moderation(priv);
3386
67f8b1dc 3387 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num[TX]);
453a6082
YP		 3388 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
3389
79aeaccd
YB		 3390 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
3391
90822265 3392 /* Configure port */
5c8e9046 3393 mlx4_en_calc_rx_buf(dev);
90822265 3394 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 3395 priv->rx_skb_size + ETH_FCS_LEN,
3396 prof->tx_pause, prof->tx_ppp,
3397 prof->rx_pause, prof->rx_ppp);
90822265 3398 if (err) {
1a91de28
JP		 3399 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3400 priv->port, err);
90822265
YP		 3401 goto out;
3402 }
3403
837052d0 3404 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 3405 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 3406 if (err) {
3407 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3408 err);
3409 goto out;
3410 }
3411 }
3412
90822265
YP		 3413 /* Init port */
3414 en_warn(priv, "Initializing port\n");
3415 err = mlx4_INIT_PORT(mdev->dev, priv->port);
3416 if (err) {
3417 en_err(priv, "Failed Initializing port\n");
3418 goto out;
3419 }
c27a02cd 3420 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea 3421
90683061 3422 /* Initialize time stamp mechanism */
dc8142ea 3423 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
90683061
EE		 3424 mlx4_en_init_timestamp(mdev);
3425
fc9f5ea9
EE		 3426 queue_delayed_work(mdev->workqueue, &priv->service_task,
3427 SERVICE_TASK_DELAY);
dc8142ea 3428
0b131561
MB		 3429 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3430 mdev->profile.prof[priv->port].rx_ppp,
3431 mdev->profile.prof[priv->port].rx_pause,
3432 mdev->profile.prof[priv->port].tx_ppp,
3433 mdev->profile.prof[priv->port].tx_pause);
39de961a 3434
e5eda89d
IS		 3435 err = register_netdev(dev);
3436 if (err) {
3437 en_err(priv, "Netdev registration failed for port %d\n", port);
3438 goto out;
3439 }
3440
3441 priv->registered = 1;
09d4d087
JP		 3442 devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port),
3443 dev);
e5eda89d 3444
c27a02cd
YP		 3445 return 0;
3446
67f8b1dc
TT		 3447err_free_tx:
3448 while (t--) {
3449 kfree(priv->tx_ring[t]);
3450 kfree(priv->tx_cq[t]);
3451 }
c27a02cd
YP		 3452out:
3453 mlx4_en_destroy_netdev(dev);
3454 return err;
3455}
3456
537f6f95
SM		 3457int mlx4_en_reset_config(struct net_device *dev,
3458 struct hwtstamp_config ts_config,
3459 netdev_features_t features)
3460{
3461 struct mlx4_en_priv *priv = netdev_priv(dev);
3462 struct mlx4_en_dev *mdev = priv->mdev;
ec25bc04
EE		 3463 struct mlx4_en_port_profile new_prof;
3464 struct mlx4_en_priv *tmp;
537f6f95
SM		 3465 int port_up = 0;
3466 int err = 0;
3467
3468 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3469 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
f0df3503
MM		 3470 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3471 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
537f6f95
SM		 3472 return 0; /* Nothing to change */
3473
3474 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3475 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3476 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3477 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3478 return -EINVAL;
3479 }
3480
ec25bc04
EE		 3481 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
3482 if (!tmp)
3483 return -ENOMEM;
3484
537f6f95 3485 mutex_lock(&mdev->state_lock);
ec25bc04
EE		 3486
3487 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
3488 memcpy(&new_prof.hwtstamp_config, &ts_config, sizeof(ts_config));
3489
3490 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
3491 if (err)
3492 goto out;
3493
537f6f95
SM		 3494 if (priv->port_up) {
3495 port_up = 1;
3496 mlx4_en_stop_port(dev, 1);
3497 }
3498
537f6f95 3499 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
ec25bc04
EE		 3500 ts_config.rx_filter,
3501 !!(features & NETIF_F_HW_VLAN_CTAG_RX));
537f6f95 3502
ec25bc04 3503 mlx4_en_safe_replace_resources(priv, tmp);
537f6f95
SM		 3504
3505 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3506 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3507 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3508 else
3509 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3510 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3511 /* RX time-stamping is OFF, update the RX vlan offload
3512 * to the latest wanted state
3513 */
3514 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3515 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3516 else
3517 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3518 }
3519
f0df3503
MM		 3520 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3521 if (features & NETIF_F_RXFCS)
3522 dev->features |= NETIF_F_RXFCS;
3523 else
3524 dev->features &= ~NETIF_F_RXFCS;
3525 }
3526
537f6f95
SM		 3527 /* RX vlan offload and RX time-stamping can't co-exist !
3528 * Regardless of the caller's choice,
3529 * Turn Off RX vlan offload in case of time-stamping is ON
3530 */
3531 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3532 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3533 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3534 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3535 }
3536
537f6f95
SM		 3537 if (port_up) {
3538 err = mlx4_en_start_port(dev);
3539 if (err)
3540 en_err(priv, "Failed starting port\n");
3541 }
3542
3543out:
3544 mutex_unlock(&mdev->state_lock);
ec25bc04
EE		 3545 kfree(tmp);
3546 if (!err)
3547 netdev_features_change(dev);
537f6f95
SM		 3548 return err;
3549}
Ubuntu Hirsute Linux kernel mirror