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net/mlx4_en: Use vlan id instead of vlan index for unregistration
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV
39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
c27a02cd
YP
42
43#include <linux/mlx4/driver.h>
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/cmd.h>
46#include <linux/mlx4/cq.h>
47
48#include "mlx4_en.h"
49#include "en_port.h"
50
d317966b 51int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 52{
bc6a4744
AV
53 struct mlx4_en_priv *priv = netdev_priv(dev);
54 int i;
d317966b 55 unsigned int offset = 0;
bc6a4744
AV
56
57 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV
58 return -EINVAL;
59
bc6a4744
AV
60 netdev_set_num_tc(dev, up);
61
62 /* Partition Tx queues evenly amongst UP's */
bc6a4744 63 for (i = 0; i < up; i++) {
d317966b
AV
64 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
65 offset += priv->num_tx_rings_p_up;
bc6a4744
AV
66 }
67
897d7846
AV
68 return 0;
69}
70
e0d1095a 71#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV
72/* must be called with local_bh_disable()d */
73static int mlx4_en_low_latency_recv(struct napi_struct *napi)
74{
75 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
76 struct net_device *dev = cq->dev;
77 struct mlx4_en_priv *priv = netdev_priv(dev);
78 struct mlx4_en_rx_ring *rx_ring = &priv->rx_ring[cq->ring];
79 int done;
80
81 if (!priv->port_up)
82 return LL_FLUSH_FAILED;
83
84 if (!mlx4_en_cq_lock_poll(cq))
85 return LL_FLUSH_BUSY;
86
87 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV
88 if (likely(done))
89 rx_ring->cleaned += done;
90 else
91 rx_ring->misses++;
9e77a2b8
AV
92
93 mlx4_en_cq_unlock_poll(cq);
94
95 return done;
96}
e0d1095a 97#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 98
1eb8c695
AV
99#ifdef CONFIG_RFS_ACCEL
100
101struct mlx4_en_filter {
102 struct list_head next;
103 struct work_struct work;
104
105 __be32 src_ip;
106 __be32 dst_ip;
107 __be16 src_port;
108 __be16 dst_port;
109
110 int rxq_index;
111 struct mlx4_en_priv *priv;
112 u32 flow_id; /* RFS infrastructure id */
113 int id; /* mlx4_en driver id */
114 u64 reg_id; /* Flow steering API id */
115 u8 activated; /* Used to prevent expiry before filter
116 * is attached
117 */
118 struct hlist_node filter_chain;
119};
120
121static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
122
123static void mlx4_en_filter_work(struct work_struct *work)
124{
125 struct mlx4_en_filter *filter = container_of(work,
126 struct mlx4_en_filter,
127 work);
128 struct mlx4_en_priv *priv = filter->priv;
129 struct mlx4_spec_list spec_tcp = {
130 .id = MLX4_NET_TRANS_RULE_ID_TCP,
131 {
132 .tcp_udp = {
133 .dst_port = filter->dst_port,
134 .dst_port_msk = (__force __be16)-1,
135 .src_port = filter->src_port,
136 .src_port_msk = (__force __be16)-1,
137 },
138 },
139 };
140 struct mlx4_spec_list spec_ip = {
141 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
142 {
143 .ipv4 = {
144 .dst_ip = filter->dst_ip,
145 .dst_ip_msk = (__force __be32)-1,
146 .src_ip = filter->src_ip,
147 .src_ip_msk = (__force __be32)-1,
148 },
149 },
150 };
151 struct mlx4_spec_list spec_eth = {
152 .id = MLX4_NET_TRANS_RULE_ID_ETH,
153 };
154 struct mlx4_net_trans_rule rule = {
155 .list = LIST_HEAD_INIT(rule.list),
156 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
157 .exclusive = 1,
158 .allow_loopback = 1,
f9162539 159 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV
160 .port = priv->port,
161 .priority = MLX4_DOMAIN_RFS,
162 };
163 int rc;
1eb8c695
AV
164 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
165
166 list_add_tail(&spec_eth.list, &rule.list);
167 list_add_tail(&spec_ip.list, &rule.list);
168 list_add_tail(&spec_tcp.list, &rule.list);
169
1eb8c695 170 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 171 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV
172 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
173
174 filter->activated = 0;
175
176 if (filter->reg_id) {
177 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
178 if (rc && rc != -ENOENT)
179 en_err(priv, "Error detaching flow. rc = %d\n", rc);
180 }
181
182 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
183 if (rc)
184 en_err(priv, "Error attaching flow. err = %d\n", rc);
185
186 mlx4_en_filter_rfs_expire(priv);
187
188 filter->activated = 1;
189}
190
191static inline struct hlist_head *
192filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
193 __be16 src_port, __be16 dst_port)
194{
195 unsigned long l;
196 int bucket_idx;
197
198 l = (__force unsigned long)src_port |
199 ((__force unsigned long)dst_port << 2);
200 l ^= (__force unsigned long)(src_ip ^ dst_ip);
201
202 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
203
204 return &priv->filter_hash[bucket_idx];
205}
206
207static struct mlx4_en_filter *
208mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
209 __be32 dst_ip, __be16 src_port, __be16 dst_port,
210 u32 flow_id)
211{
212 struct mlx4_en_filter *filter = NULL;
213
214 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
215 if (!filter)
216 return NULL;
217
218 filter->priv = priv;
219 filter->rxq_index = rxq_index;
220 INIT_WORK(&filter->work, mlx4_en_filter_work);
221
222 filter->src_ip = src_ip;
223 filter->dst_ip = dst_ip;
224 filter->src_port = src_port;
225 filter->dst_port = dst_port;
226
227 filter->flow_id = flow_id;
228
ee64c0ee 229 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV
230
231 list_add_tail(&filter->next, &priv->filters);
232 hlist_add_head(&filter->filter_chain,
233 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
234 dst_port));
235
236 return filter;
237}
238
239static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
240{
241 struct mlx4_en_priv *priv = filter->priv;
242 int rc;
243
244 list_del(&filter->next);
245
246 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
247 if (rc && rc != -ENOENT)
248 en_err(priv, "Error detaching flow. rc = %d\n", rc);
249
250 kfree(filter);
251}
252
253static inline struct mlx4_en_filter *
254mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
255 __be16 src_port, __be16 dst_port)
256{
1eb8c695
AV
257 struct mlx4_en_filter *filter;
258 struct mlx4_en_filter *ret = NULL;
259
b67bfe0d 260 hlist_for_each_entry(filter,
1eb8c695
AV
261 filter_hash_bucket(priv, src_ip, dst_ip,
262 src_port, dst_port),
263 filter_chain) {
264 if (filter->src_ip == src_ip &&
265 filter->dst_ip == dst_ip &&
266 filter->src_port == src_port &&
267 filter->dst_port == dst_port) {
268 ret = filter;
269 break;
270 }
271 }
272
273 return ret;
274}
275
276static int
277mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
278 u16 rxq_index, u32 flow_id)
279{
280 struct mlx4_en_priv *priv = netdev_priv(net_dev);
281 struct mlx4_en_filter *filter;
282 const struct iphdr *ip;
283 const __be16 *ports;
284 __be32 src_ip;
285 __be32 dst_ip;
286 __be16 src_port;
287 __be16 dst_port;
288 int nhoff = skb_network_offset(skb);
289 int ret = 0;
290
291 if (skb->protocol != htons(ETH_P_IP))
292 return -EPROTONOSUPPORT;
293
294 ip = (const struct iphdr *)(skb->data + nhoff);
295 if (ip_is_fragment(ip))
296 return -EPROTONOSUPPORT;
297
298 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
299
300 src_ip = ip->saddr;
301 dst_ip = ip->daddr;
302 src_port = ports[0];
303 dst_port = ports[1];
304
305 if (ip->protocol != IPPROTO_TCP)
306 return -EPROTONOSUPPORT;
307
308 spin_lock_bh(&priv->filters_lock);
309 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, src_port, dst_port);
310 if (filter) {
311 if (filter->rxq_index == rxq_index)
312 goto out;
313
314 filter->rxq_index = rxq_index;
315 } else {
316 filter = mlx4_en_filter_alloc(priv, rxq_index,
317 src_ip, dst_ip,
318 src_port, dst_port, flow_id);
319 if (!filter) {
320 ret = -ENOMEM;
321 goto err;
322 }
323 }
324
325 queue_work(priv->mdev->workqueue, &filter->work);
326
327out:
328 ret = filter->id;
329err:
330 spin_unlock_bh(&priv->filters_lock);
331
332 return ret;
333}
334
335void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
336 struct mlx4_en_rx_ring *rx_ring)
337{
338 struct mlx4_en_filter *filter, *tmp;
339 LIST_HEAD(del_list);
340
341 spin_lock_bh(&priv->filters_lock);
342 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
343 list_move(&filter->next, &del_list);
344 hlist_del(&filter->filter_chain);
345 }
346 spin_unlock_bh(&priv->filters_lock);
347
348 list_for_each_entry_safe(filter, tmp, &del_list, next) {
349 cancel_work_sync(&filter->work);
350 mlx4_en_filter_free(filter);
351 }
352}
353
354static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
355{
356 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
357 LIST_HEAD(del_list);
358 int i = 0;
359
360 spin_lock_bh(&priv->filters_lock);
361 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
362 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
363 break;
364
365 if (filter->activated &&
366 !work_pending(&filter->work) &&
367 rps_may_expire_flow(priv->dev,
368 filter->rxq_index, filter->flow_id,
369 filter->id)) {
370 list_move(&filter->next, &del_list);
371 hlist_del(&filter->filter_chain);
372 } else
373 last_filter = filter;
374
375 i++;
376 }
377
378 if (last_filter && (&last_filter->next != priv->filters.next))
379 list_move(&priv->filters, &last_filter->next);
380
381 spin_unlock_bh(&priv->filters_lock);
382
383 list_for_each_entry_safe(filter, tmp, &del_list, next)
384 mlx4_en_filter_free(filter);
385}
386#endif
387
80d5c368
PM
388static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
389 __be16 proto, u16 vid)
c27a02cd
YP
390{
391 struct mlx4_en_priv *priv = netdev_priv(dev);
392 struct mlx4_en_dev *mdev = priv->mdev;
393 int err;
4c3eb3ca 394 int idx;
c27a02cd 395
f1b553fb 396 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 397
f1b553fb 398 set_bit(vid, priv->active_vlans);
c27a02cd
YP
399
400 /* Add VID to port VLAN filter */
401 mutex_lock(&mdev->state_lock);
402 if (mdev->device_up && priv->port_up) {
f1b553fb 403 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 404 if (err)
453a6082 405 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 406 }
4c3eb3ca 407 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 408 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 409 mutex_unlock(&mdev->state_lock);
4c3eb3ca 410
8e586137 411 return 0;
c27a02cd
YP
412}
413
80d5c368
PM
414static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
415 __be16 proto, u16 vid)
c27a02cd
YP
416{
417 struct mlx4_en_priv *priv = netdev_priv(dev);
418 struct mlx4_en_dev *mdev = priv->mdev;
419 int err;
420
f1b553fb 421 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 422
f1b553fb 423 clear_bit(vid, priv->active_vlans);
c27a02cd
YP
424
425 /* Remove VID from port VLAN filter */
426 mutex_lock(&mdev->state_lock);
2009d005 427 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 428
c27a02cd 429 if (mdev->device_up && priv->port_up) {
f1b553fb 430 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 431 if (err)
453a6082 432 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP
433 }
434 mutex_unlock(&mdev->state_lock);
8e586137
JP
435
436 return 0;
c27a02cd
YP
437}
438
6bbb6d99
YB
439static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
440{
bab6a9ea
YB
441 int i;
442 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB
443 dst_mac[i] = src_mac & 0xff;
444 src_mac >>= 8;
445 }
446 memset(&dst_mac[ETH_ALEN], 0, 2);
447}
448
16a10ffd
YB
449static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
450 unsigned char *mac, int *qpn, u64 *reg_id)
451{
452 struct mlx4_en_dev *mdev = priv->mdev;
453 struct mlx4_dev *dev = mdev->dev;
454 int err;
455
456 switch (dev->caps.steering_mode) {
457 case MLX4_STEERING_MODE_B0: {
458 struct mlx4_qp qp;
459 u8 gid[16] = {0};
460
461 qp.qpn = *qpn;
462 memcpy(&gid[10], mac, ETH_ALEN);
463 gid[5] = priv->port;
464
465 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
466 break;
467 }
468 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
469 struct mlx4_spec_list spec_eth = { {NULL} };
470 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
471
472 struct mlx4_net_trans_rule rule = {
473 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
474 .exclusive = 0,
475 .allow_loopback = 1,
f9162539 476 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB
477 .priority = MLX4_DOMAIN_NIC,
478 };
479
480 rule.port = priv->port;
481 rule.qpn = *qpn;
482 INIT_LIST_HEAD(&rule.list);
483
484 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
485 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
486 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
487 list_add_tail(&spec_eth.list, &rule.list);
488
489 err = mlx4_flow_attach(dev, &rule, reg_id);
490 break;
491 }
492 default:
493 return -EINVAL;
494 }
495 if (err)
496 en_warn(priv, "Failed Attaching Unicast\n");
497
498 return err;
499}
500
501static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
502 unsigned char *mac, int qpn, u64 reg_id)
503{
504 struct mlx4_en_dev *mdev = priv->mdev;
505 struct mlx4_dev *dev = mdev->dev;
506
507 switch (dev->caps.steering_mode) {
508 case MLX4_STEERING_MODE_B0: {
509 struct mlx4_qp qp;
510 u8 gid[16] = {0};
511
512 qp.qpn = qpn;
513 memcpy(&gid[10], mac, ETH_ALEN);
514 gid[5] = priv->port;
515
516 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
517 break;
518 }
519 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
520 mlx4_flow_detach(dev, reg_id);
521 break;
522 }
523 default:
524 en_err(priv, "Invalid steering mode.\n");
525 }
526}
527
528static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
529{
530 struct mlx4_en_dev *mdev = priv->mdev;
531 struct mlx4_dev *dev = mdev->dev;
532 struct mlx4_mac_entry *entry;
533 int index = 0;
534 int err = 0;
535 u64 reg_id;
536 int *qpn = &priv->base_qpn;
537 u64 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
538
539 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
540 priv->dev->dev_addr);
541 index = mlx4_register_mac(dev, priv->port, mac);
542 if (index < 0) {
543 err = index;
544 en_err(priv, "Failed adding MAC: %pM\n",
545 priv->dev->dev_addr);
546 return err;
547 }
548
549 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
550 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
551 *qpn = base_qpn + index;
552 return 0;
553 }
554
555 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
556 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
557 if (err) {
558 en_err(priv, "Failed to reserve qp for mac registration\n");
559 goto qp_err;
560 }
561
562 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
563 if (err)
564 goto steer_err;
565
566 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
567 if (!entry) {
568 err = -ENOMEM;
569 goto alloc_err;
570 }
571 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
572 entry->reg_id = reg_id;
573
c07cb4b0
YB
574 hlist_add_head_rcu(&entry->hlist,
575 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 576
c07cb4b0 577 return 0;
16a10ffd
YB
578
579alloc_err:
580 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
581
582steer_err:
583 mlx4_qp_release_range(dev, *qpn, 1);
584
585qp_err:
586 mlx4_unregister_mac(dev, priv->port, mac);
587 return err;
588}
589
590static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
591{
592 struct mlx4_en_dev *mdev = priv->mdev;
593 struct mlx4_dev *dev = mdev->dev;
16a10ffd 594 int qpn = priv->base_qpn;
83a5a6ce 595 u64 mac;
16a10ffd 596
83a5a6ce
YB
597 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
598 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
599 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
600 priv->dev->dev_addr);
601 mlx4_unregister_mac(dev, priv->port, mac);
602 } else {
c07cb4b0 603 struct mlx4_mac_entry *entry;
b67bfe0d 604 struct hlist_node *tmp;
c07cb4b0 605 struct hlist_head *bucket;
83a5a6ce 606 unsigned int i;
c07cb4b0 607
83a5a6ce
YB
608 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
609 bucket = &priv->mac_hash[i];
610 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
611 mac = mlx4_en_mac_to_u64(entry->mac);
612 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
613 entry->mac);
c07cb4b0
YB
614 mlx4_en_uc_steer_release(priv, entry->mac,
615 qpn, entry->reg_id);
c07cb4b0 616
83a5a6ce 617 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB
618 hlist_del_rcu(&entry->hlist);
619 kfree_rcu(entry, rcu);
c07cb4b0 620 }
16a10ffd 621 }
83a5a6ce
YB
622
623 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
624 priv->port, qpn);
625 mlx4_qp_release_range(dev, qpn, 1);
626 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB
627 }
628}
629
630static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 631 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB
632{
633 struct mlx4_en_dev *mdev = priv->mdev;
634 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB
635 int err = 0;
636 u64 new_mac_u64 = mlx4_en_mac_to_u64(new_mac);
637
638 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB
639 struct hlist_head *bucket;
640 unsigned int mac_hash;
641 struct mlx4_mac_entry *entry;
b67bfe0d 642 struct hlist_node *tmp;
c07cb4b0
YB
643 u64 prev_mac_u64 = mlx4_en_mac_to_u64(prev_mac);
644
645 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 646 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB
647 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
648 mlx4_en_uc_steer_release(priv, entry->mac,
649 qpn, entry->reg_id);
650 mlx4_unregister_mac(dev, priv->port,
651 prev_mac_u64);
652 hlist_del_rcu(&entry->hlist);
653 synchronize_rcu();
654 memcpy(entry->mac, new_mac, ETH_ALEN);
655 entry->reg_id = 0;
656 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
657 hlist_add_head_rcu(&entry->hlist,
658 &priv->mac_hash[mac_hash]);
659 mlx4_register_mac(dev, priv->port, new_mac_u64);
660 err = mlx4_en_uc_steer_add(priv, new_mac,
661 &qpn,
662 &entry->reg_id);
663 return err;
664 }
665 }
666 return -EINVAL;
16a10ffd
YB
667 }
668
669 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
670}
671
e7c1c2c4 672u64 mlx4_en_mac_to_u64(u8 *addr)
c27a02cd
YP
673{
674 u64 mac = 0;
675 int i;
676
677 for (i = 0; i < ETH_ALEN; i++) {
678 mac <<= 8;
679 mac |= addr[i];
680 }
681 return mac;
682}
683
bfa8ab47 684static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv)
c27a02cd 685{
c27a02cd
YP
686 int err = 0;
687
c27a02cd
YP
688 if (priv->port_up) {
689 /* Remove old MAC and insert the new one */
16a10ffd 690 err = mlx4_en_replace_mac(priv, priv->base_qpn,
90bbb74a 691 priv->dev->dev_addr, priv->prev_mac);
c27a02cd 692 if (err)
453a6082 693 en_err(priv, "Failed changing HW MAC address\n");
6bbb6d99
YB
694 memcpy(priv->prev_mac, priv->dev->dev_addr,
695 sizeof(priv->prev_mac));
c27a02cd 696 } else
48e551ff 697 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 698
bfa8ab47
YB
699 return err;
700}
701
702static int mlx4_en_set_mac(struct net_device *dev, void *addr)
703{
704 struct mlx4_en_priv *priv = netdev_priv(dev);
705 struct mlx4_en_dev *mdev = priv->mdev;
706 struct sockaddr *saddr = addr;
707 int err;
708
709 if (!is_valid_ether_addr(saddr->sa_data))
710 return -EADDRNOTAVAIL;
711
712 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
713
714 mutex_lock(&mdev->state_lock);
715 err = mlx4_en_do_set_mac(priv);
c27a02cd 716 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB
717
718 return err;
c27a02cd
YP
719}
720
721static void mlx4_en_clear_list(struct net_device *dev)
722{
723 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 724 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 725
6d199937
YP
726 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
727 list_del(&mc_to_del->list);
728 kfree(mc_to_del);
729 }
c27a02cd
YP
730}
731
732static void mlx4_en_cache_mclist(struct net_device *dev)
733{
734 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 735 struct netdev_hw_addr *ha;
6d199937 736 struct mlx4_en_mc_list *tmp;
ff6e2163 737
0e03567a 738 mlx4_en_clear_list(dev);
6d199937
YP
739 netdev_for_each_mc_addr(ha, dev) {
740 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
741 if (!tmp) {
6d199937
YP
742 mlx4_en_clear_list(dev);
743 return;
744 }
745 memcpy(tmp->addr, ha->addr, ETH_ALEN);
746 list_add_tail(&tmp->list, &priv->mc_list);
747 }
c27a02cd
YP
748}
749
6d199937
YP
750static void update_mclist_flags(struct mlx4_en_priv *priv,
751 struct list_head *dst,
752 struct list_head *src)
753{
754 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
755 bool found;
756
757 /* Find all the entries that should be removed from dst,
758 * These are the entries that are not found in src
759 */
760 list_for_each_entry(dst_tmp, dst, list) {
761 found = false;
762 list_for_each_entry(src_tmp, src, list) {
763 if (!memcmp(dst_tmp->addr, src_tmp->addr, ETH_ALEN)) {
764 found = true;
765 break;
766 }
767 }
768 if (!found)
769 dst_tmp->action = MCLIST_REM;
770 }
771
772 /* Add entries that exist in src but not in dst
773 * mark them as need to add
774 */
775 list_for_each_entry(src_tmp, src, list) {
776 found = false;
777 list_for_each_entry(dst_tmp, dst, list) {
778 if (!memcmp(dst_tmp->addr, src_tmp->addr, ETH_ALEN)) {
779 dst_tmp->action = MCLIST_NONE;
780 found = true;
781 break;
782 }
783 }
784 if (!found) {
14f8dc49
JP
785 new_mc = kmemdup(src_tmp,
786 sizeof(struct mlx4_en_mc_list),
6d199937 787 GFP_KERNEL);
14f8dc49 788 if (!new_mc)
6d199937 789 return;
14f8dc49 790
6d199937
YP
791 new_mc->action = MCLIST_ADD;
792 list_add_tail(&new_mc->list, dst);
793 }
794 }
795}
c27a02cd 796
0eb74fdd 797static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP
798{
799 struct mlx4_en_priv *priv = netdev_priv(dev);
800
801 if (!priv->port_up)
802 return;
803
0eb74fdd 804 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP
805}
806
0eb74fdd
YB
807static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
808 struct mlx4_en_dev *mdev)
c27a02cd 809{
c96d97f4 810 int err = 0;
c27a02cd 811
0eb74fdd 812 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 813 if (netif_msg_rx_status(priv))
0eb74fdd
YB
814 en_warn(priv, "Entering promiscuous mode\n");
815 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 816
0eb74fdd 817 /* Enable promiscouos mode */
c96d97f4 818 switch (mdev->dev->caps.steering_mode) {
592e49dd 819 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB
820 err = mlx4_flow_steer_promisc_add(mdev->dev,
821 priv->port,
822 priv->base_qpn,
f9162539 823 MLX4_FS_ALL_DEFAULT);
592e49dd 824 if (err)
0eb74fdd
YB
825 en_err(priv, "Failed enabling promiscuous mode\n");
826 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ
827 break;
828
c96d97f4 829 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB
830 err = mlx4_unicast_promisc_add(mdev->dev,
831 priv->base_qpn,
832 priv->port);
c96d97f4 833 if (err)
0eb74fdd
YB
834 en_err(priv, "Failed enabling unicast promiscuous mode\n");
835
836 /* Add the default qp number as multicast
837 * promisc
838 */
839 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
840 err = mlx4_multicast_promisc_add(mdev->dev,
841 priv->base_qpn,
842 priv->port);
c96d97f4 843 if (err)
0eb74fdd
YB
844 en_err(priv, "Failed enabling multicast promiscuous mode\n");
845 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ
846 }
847 break;
c27a02cd 848
c96d97f4
HHZ
849 case MLX4_STEERING_MODE_A0:
850 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
851 priv->port,
0eb74fdd
YB
852 priv->base_qpn,
853 1);
1679200f 854 if (err)
0eb74fdd 855 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 856 break;
1679200f
YP
857 }
858
0eb74fdd
YB
859 /* Disable port multicast filter (unconditionally) */
860 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
861 0, MLX4_MCAST_DISABLE);
862 if (err)
863 en_err(priv, "Failed disabling multicast filter\n");
864
865 /* Disable port VLAN filter */
f1b553fb 866 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 867 if (err)
0eb74fdd
YB
868 en_err(priv, "Failed disabling VLAN filter\n");
869 }
870}
871
872static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
873 struct mlx4_en_dev *mdev)
874{
875 int err = 0;
876
877 if (netif_msg_rx_status(priv))
878 en_warn(priv, "Leaving promiscuous mode\n");
879 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
880
881 /* Disable promiscouos mode */
882 switch (mdev->dev->caps.steering_mode) {
883 case MLX4_STEERING_MODE_DEVICE_MANAGED:
884 err = mlx4_flow_steer_promisc_remove(mdev->dev,
885 priv->port,
f9162539 886 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB
887 if (err)
888 en_err(priv, "Failed disabling promiscuous mode\n");
889 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
890 break;
891
892 case MLX4_STEERING_MODE_B0:
893 err = mlx4_unicast_promisc_remove(mdev->dev,
894 priv->base_qpn,
895 priv->port);
896 if (err)
897 en_err(priv, "Failed disabling unicast promiscuous mode\n");
898 /* Disable Multicast promisc */
899 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
900 err = mlx4_multicast_promisc_remove(mdev->dev,
901 priv->base_qpn,
902 priv->port);
903 if (err)
904 en_err(priv, "Failed disabling multicast promiscuous mode\n");
905 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
906 }
907 break;
908
909 case MLX4_STEERING_MODE_A0:
910 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
911 priv->port,
912 priv->base_qpn, 0);
913 if (err)
914 en_err(priv, "Failed disabling promiscuous mode\n");
915 break;
c27a02cd
YP
916 }
917
0eb74fdd
YB
918 /* Enable port VLAN filter */
919 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
920 if (err)
921 en_err(priv, "Failed enabling VLAN filter\n");
922}
923
924static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
925 struct net_device *dev,
926 struct mlx4_en_dev *mdev)
927{
928 struct mlx4_en_mc_list *mclist, *tmp;
929 u64 mcast_addr = 0;
930 u8 mc_list[16] = {0};
931 int err = 0;
932
c27a02cd
YP
933 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
934 if (dev->flags & IFF_ALLMULTI) {
935 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
936 0, MLX4_MCAST_DISABLE);
937 if (err)
453a6082 938 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP
939
940 /* Add the default qp number as multicast promisc */
941 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 942 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ
943 case MLX4_STEERING_MODE_DEVICE_MANAGED:
944 err = mlx4_flow_steer_promisc_add(mdev->dev,
945 priv->port,
946 priv->base_qpn,
f9162539 947 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ
948 break;
949
c96d97f4
HHZ
950 case MLX4_STEERING_MODE_B0:
951 err = mlx4_multicast_promisc_add(mdev->dev,
952 priv->base_qpn,
953 priv->port);
954 break;
955
956 case MLX4_STEERING_MODE_A0:
957 break;
958 }
1679200f
YP
959 if (err)
960 en_err(priv, "Failed entering multicast promisc mode\n");
961 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
962 }
c27a02cd 963 } else {
1679200f
YP
964 /* Disable Multicast promisc */
965 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 966 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ
967 case MLX4_STEERING_MODE_DEVICE_MANAGED:
968 err = mlx4_flow_steer_promisc_remove(mdev->dev,
969 priv->port,
f9162539 970 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ
971 break;
972
c96d97f4
HHZ
973 case MLX4_STEERING_MODE_B0:
974 err = mlx4_multicast_promisc_remove(mdev->dev,
975 priv->base_qpn,
976 priv->port);
977 break;
978
979 case MLX4_STEERING_MODE_A0:
980 break;
981 }
1679200f 982 if (err)
25985edc 983 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP
984 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
985 }
ff6e2163 986
c27a02cd
YP
987 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
988 0, MLX4_MCAST_DISABLE);
989 if (err)
453a6082 990 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP
991
992 /* Flush mcast filter and init it with broadcast address */
993 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
994 1, MLX4_MCAST_CONFIG);
995
996 /* Update multicast list - we cache all addresses so they won't
997 * change while HW is updated holding the command semaphor */
dbd501a8 998 netif_addr_lock_bh(dev);
c27a02cd 999 mlx4_en_cache_mclist(dev);
dbd501a8 1000 netif_addr_unlock_bh(dev);
6d199937
YP
1001 list_for_each_entry(mclist, &priv->mc_list, list) {
1002 mcast_addr = mlx4_en_mac_to_u64(mclist->addr);
c27a02cd
YP
1003 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1004 mcast_addr, 0, MLX4_MCAST_CONFIG);
1005 }
1006 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1007 0, MLX4_MCAST_ENABLE);
1008 if (err)
453a6082 1009 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP
1010
1011 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1012 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1013 if (mclist->action == MCLIST_REM) {
1014 /* detach this address and delete from list */
1015 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1016 mc_list[5] = priv->port;
1017 err = mlx4_multicast_detach(mdev->dev,
1018 &priv->rss_map.indir_qp,
1019 mc_list,
0ff1fb65
HHZ
1020 MLX4_PROT_ETH,
1021 mclist->reg_id);
6d199937
YP
1022 if (err)
1023 en_err(priv, "Fail to detach multicast address\n");
1024
1025 /* remove from list */
1026 list_del(&mclist->list);
1027 kfree(mclist);
9c64508a 1028 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP
1029 /* attach the address */
1030 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1031 /* needed for B0 steering support */
6d199937
YP
1032 mc_list[5] = priv->port;
1033 err = mlx4_multicast_attach(mdev->dev,
1034 &priv->rss_map.indir_qp,
0ff1fb65
HHZ
1035 mc_list,
1036 priv->port, 0,
1037 MLX4_PROT_ETH,
1038 &mclist->reg_id);
6d199937
YP
1039 if (err)
1040 en_err(priv, "Fail to attach multicast address\n");
1041
1042 }
1043 }
c27a02cd 1044 }
0eb74fdd
YB
1045}
1046
cc5387f7
YB
1047static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1048 struct net_device *dev,
1049 struct mlx4_en_dev *mdev)
1050{
1051 struct netdev_hw_addr *ha;
1052 struct mlx4_mac_entry *entry;
b67bfe0d 1053 struct hlist_node *tmp;
cc5387f7
YB
1054 bool found;
1055 u64 mac;
1056 int err = 0;
1057 struct hlist_head *bucket;
1058 unsigned int i;
1059 int removed = 0;
1060 u32 prev_flags;
1061
1062 /* Note that we do not need to protect our mac_hash traversal with rcu,
1063 * since all modification code is protected by mdev->state_lock
1064 */
1065
1066 /* find what to remove */
1067 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1068 bucket = &priv->mac_hash[i];
b67bfe0d 1069 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB
1070 found = false;
1071 netdev_for_each_uc_addr(ha, dev) {
1072 if (ether_addr_equal_64bits(entry->mac,
1073 ha->addr)) {
1074 found = true;
1075 break;
1076 }
1077 }
1078
1079 /* MAC address of the port is not in uc list */
1080 if (ether_addr_equal_64bits(entry->mac, dev->dev_addr))
1081 found = true;
1082
1083 if (!found) {
1084 mac = mlx4_en_mac_to_u64(entry->mac);
1085 mlx4_en_uc_steer_release(priv, entry->mac,
1086 priv->base_qpn,
1087 entry->reg_id);
1088 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1089
1090 hlist_del_rcu(&entry->hlist);
1091 kfree_rcu(entry, rcu);
1092 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1093 entry->mac, priv->port);
1094 ++removed;
1095 }
1096 }
1097 }
1098
1099 /* if we didn't remove anything, there is no use in trying to add
1100 * again once we are in a forced promisc mode state
1101 */
1102 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1103 return;
1104
1105 prev_flags = priv->flags;
1106 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1107
1108 /* find what to add */
1109 netdev_for_each_uc_addr(ha, dev) {
1110 found = false;
1111 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1112 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB
1113 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1114 found = true;
1115 break;
1116 }
1117 }
1118
1119 if (!found) {
1120 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1121 if (!entry) {
1122 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1123 ha->addr, priv->port);
1124 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1125 break;
1126 }
1127 mac = mlx4_en_mac_to_u64(ha->addr);
1128 memcpy(entry->mac, ha->addr, ETH_ALEN);
1129 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1130 if (err < 0) {
1131 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1132 ha->addr, priv->port, err);
1133 kfree(entry);
1134 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1135 break;
1136 }
1137 err = mlx4_en_uc_steer_add(priv, ha->addr,
1138 &priv->base_qpn,
1139 &entry->reg_id);
1140 if (err) {
1141 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1142 ha->addr, priv->port, err);
1143 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1144 kfree(entry);
1145 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1146 break;
1147 } else {
1148 unsigned int mac_hash;
1149 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1150 ha->addr, priv->port);
1151 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1152 bucket = &priv->mac_hash[mac_hash];
1153 hlist_add_head_rcu(&entry->hlist, bucket);
1154 }
1155 }
1156 }
1157
1158 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1159 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1160 priv->port);
1161 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1162 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1163 priv->port);
1164 }
1165}
1166
0eb74fdd
YB
1167static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1168{
1169 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1170 rx_mode_task);
1171 struct mlx4_en_dev *mdev = priv->mdev;
1172 struct net_device *dev = priv->dev;
1173
1174 mutex_lock(&mdev->state_lock);
1175 if (!mdev->device_up) {
1176 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1177 goto out;
1178 }
1179 if (!priv->port_up) {
1180 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1181 goto out;
1182 }
1183
1184 if (!netif_carrier_ok(dev)) {
1185 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1186 if (priv->port_state.link_state) {
1187 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1188 netif_carrier_on(dev);
1189 en_dbg(LINK, priv, "Link Up\n");
1190 }
1191 }
1192 }
1193
cc5387f7
YB
1194 if (dev->priv_flags & IFF_UNICAST_FLT)
1195 mlx4_en_do_uc_filter(priv, dev, mdev);
1196
0eb74fdd 1197 /* Promsicuous mode: disable all filters */
cc5387f7
YB
1198 if ((dev->flags & IFF_PROMISC) ||
1199 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB
1200 mlx4_en_set_promisc_mode(priv, mdev);
1201 goto out;
1202 }
1203
1204 /* Not in promiscuous mode */
1205 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1206 mlx4_en_clear_promisc_mode(priv, mdev);
1207
1208 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP
1209out:
1210 mutex_unlock(&mdev->state_lock);
1211}
1212
1213#ifdef CONFIG_NET_POLL_CONTROLLER
1214static void mlx4_en_netpoll(struct net_device *dev)
1215{
1216 struct mlx4_en_priv *priv = netdev_priv(dev);
1217 struct mlx4_en_cq *cq;
1218 unsigned long flags;
1219 int i;
1220
1221 for (i = 0; i < priv->rx_ring_num; i++) {
1222 cq = &priv->rx_cq[i];
1223 spin_lock_irqsave(&cq->lock, flags);
1224 napi_synchronize(&cq->napi);
1225 mlx4_en_process_rx_cq(dev, cq, 0);
1226 spin_unlock_irqrestore(&cq->lock, flags);
1227 }
1228}
1229#endif
1230
1231static void mlx4_en_tx_timeout(struct net_device *dev)
1232{
1233 struct mlx4_en_priv *priv = netdev_priv(dev);
1234 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1235 int i;
c27a02cd
YP
1236
1237 if (netif_msg_timer(priv))
453a6082 1238 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1239
b944ebec
YP
1240 for (i = 0; i < priv->tx_ring_num; i++) {
1241 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1242 continue;
1243 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
1244 i, priv->tx_ring[i].qpn, priv->tx_ring[i].cqn,
1245 priv->tx_ring[i].cons, priv->tx_ring[i].prod);
1246 }
1247
1e338db5 1248 priv->port_stats.tx_timeout++;
453a6082 1249 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1250 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP
1251}
1252
1253
1254static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1255{
1256 struct mlx4_en_priv *priv = netdev_priv(dev);
1257
1258 spin_lock_bh(&priv->stats_lock);
1259 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1260 spin_unlock_bh(&priv->stats_lock);
1261
1262 return &priv->ret_stats;
1263}
1264
1265static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1266{
c27a02cd
YP
1267 struct mlx4_en_cq *cq;
1268 int i;
1269
1270 /* If we haven't received a specific coalescing setting
98a1708d 1271 * (module param), we set the moderation parameters as follows:
c27a02cd 1272 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1273 * satisfy our coalescing target.
c27a02cd
YP
1274 * - moder_time is set to a fixed value.
1275 */
3db36fb2 1276 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1277 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP
1278 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1279 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB
1280 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1281 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP
1282
1283 /* Setup cq moderation params */
1284 for (i = 0; i < priv->rx_ring_num; i++) {
1285 cq = &priv->rx_cq[i];
1286 cq->moder_cnt = priv->rx_frames;
1287 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG
1288 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1289 priv->last_moder_packets[i] = 0;
1290 priv->last_moder_bytes[i] = 0;
c27a02cd
YP
1291 }
1292
1293 for (i = 0; i < priv->tx_ring_num; i++) {
1294 cq = &priv->tx_cq[i];
a19a848a
YP
1295 cq->moder_cnt = priv->tx_frames;
1296 cq->moder_time = priv->tx_usecs;
c27a02cd
YP
1297 }
1298
1299 /* Reset auto-moderation params */
1300 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1301 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1302 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1303 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1304 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1305 priv->adaptive_rx_coal = 1;
c27a02cd 1306 priv->last_moder_jiffies = 0;
c27a02cd 1307 priv->last_moder_tx_packets = 0;
c27a02cd
YP
1308}
1309
1310static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1311{
1312 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP
1313 struct mlx4_en_cq *cq;
1314 unsigned long packets;
1315 unsigned long rate;
1316 unsigned long avg_pkt_size;
1317 unsigned long rx_packets;
1318 unsigned long rx_bytes;
c27a02cd
YP
1319 unsigned long rx_pkt_diff;
1320 int moder_time;
6b4d8d9f 1321 int ring, err;
c27a02cd
YP
1322
1323 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1324 return;
1325
6b4d8d9f
AG
1326 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1327 spin_lock_bh(&priv->stats_lock);
1328 rx_packets = priv->rx_ring[ring].packets;
1329 rx_bytes = priv->rx_ring[ring].bytes;
1330 spin_unlock_bh(&priv->stats_lock);
1331
1332 rx_pkt_diff = ((unsigned long) (rx_packets -
1333 priv->last_moder_packets[ring]));
1334 packets = rx_pkt_diff;
1335 rate = packets * HZ / period;
1336 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1337 priv->last_moder_bytes[ring])) / packets : 0;
1338
1339 /* Apply auto-moderation only when packet rate
1340 * exceeds a rate that it matters */
1341 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1342 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP
1343 if (rate < priv->pkt_rate_low)
1344 moder_time = priv->rx_usecs_low;
1345 else if (rate > priv->pkt_rate_high)
1346 moder_time = priv->rx_usecs_high;
1347 else
1348 moder_time = (rate - priv->pkt_rate_low) *
1349 (priv->rx_usecs_high - priv->rx_usecs_low) /
1350 (priv->pkt_rate_high - priv->pkt_rate_low) +
1351 priv->rx_usecs_low;
6b4d8d9f
AG
1352 } else {
1353 moder_time = priv->rx_usecs_low;
c27a02cd 1354 }
c27a02cd 1355
6b4d8d9f
AG
1356 if (moder_time != priv->last_moder_time[ring]) {
1357 priv->last_moder_time[ring] = moder_time;
1358 cq = &priv->rx_cq[ring];
c27a02cd 1359 cq->moder_time = moder_time;
a1c6693a 1360 cq->moder_cnt = priv->rx_frames;
c27a02cd 1361 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1362 if (err)
48e551ff
YB
1363 en_err(priv, "Failed modifying moderation for cq:%d\n",
1364 ring);
c27a02cd 1365 }
6b4d8d9f
AG
1366 priv->last_moder_packets[ring] = rx_packets;
1367 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP
1368 }
1369
c27a02cd
YP
1370 priv->last_moder_jiffies = jiffies;
1371}
1372
1373static void mlx4_en_do_get_stats(struct work_struct *work)
1374{
bf6aede7 1375 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP
1376 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1377 stats_task);
1378 struct mlx4_en_dev *mdev = priv->mdev;
1379 int err;
1380
c27a02cd
YP
1381 mutex_lock(&mdev->state_lock);
1382 if (mdev->device_up) {
6123db2e
JM
1383 if (priv->port_up) {
1384 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1385 if (err)
1386 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1387
c27a02cd 1388 mlx4_en_auto_moderation(priv);
6123db2e 1389 }
c27a02cd
YP
1390
1391 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1392 }
d7e1a487 1393 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
bfa8ab47 1394 mlx4_en_do_set_mac(priv);
d7e1a487
YP
1395 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1396 }
c27a02cd
YP
1397 mutex_unlock(&mdev->state_lock);
1398}
1399
b6c39bfc
AV
1400/* mlx4_en_service_task - Run service task for tasks that needed to be done
1401 * periodically
1402 */
1403static void mlx4_en_service_task(struct work_struct *work)
1404{
1405 struct delayed_work *delay = to_delayed_work(work);
1406 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1407 service_task);
1408 struct mlx4_en_dev *mdev = priv->mdev;
1409
1410 mutex_lock(&mdev->state_lock);
1411 if (mdev->device_up) {
dc8142ea
AV
1412 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1413 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV
1414
1415 queue_delayed_work(mdev->workqueue, &priv->service_task,
1416 SERVICE_TASK_DELAY);
1417 }
1418 mutex_unlock(&mdev->state_lock);
1419}
1420
c27a02cd
YP
1421static void mlx4_en_linkstate(struct work_struct *work)
1422{
1423 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1424 linkstate_task);
1425 struct mlx4_en_dev *mdev = priv->mdev;
1426 int linkstate = priv->link_state;
1427
1428 mutex_lock(&mdev->state_lock);
1429 /* If observable port state changed set carrier state and
1430 * report to system log */
1431 if (priv->last_link_state != linkstate) {
1432 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1433 en_info(priv, "Link Down\n");
c27a02cd
YP
1434 netif_carrier_off(priv->dev);
1435 } else {
e5cc44b2 1436 en_info(priv, "Link Up\n");
c27a02cd
YP
1437 netif_carrier_on(priv->dev);
1438 }
1439 }
1440 priv->last_link_state = linkstate;
1441 mutex_unlock(&mdev->state_lock);
1442}
1443
1444
18cc42a3 1445int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP
1446{
1447 struct mlx4_en_priv *priv = netdev_priv(dev);
1448 struct mlx4_en_dev *mdev = priv->mdev;
1449 struct mlx4_en_cq *cq;
1450 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP
1451 int rx_index = 0;
1452 int tx_index = 0;
c27a02cd
YP
1453 int err = 0;
1454 int i;
1455 int j;
1679200f 1456 u8 mc_list[16] = {0};
c27a02cd
YP
1457
1458 if (priv->port_up) {
453a6082 1459 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP
1460 return 0;
1461 }
1462
6d199937
YP
1463 INIT_LIST_HEAD(&priv->mc_list);
1464 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ
1465 INIT_LIST_HEAD(&priv->ethtool_list);
1466 memset(&priv->ethtool_rules[0], 0,
1467 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1468
c27a02cd
YP
1469 /* Calculate Rx buf size */
1470 dev->mtu = min(dev->mtu, priv->max_mtu);
1471 mlx4_en_calc_rx_buf(dev);
453a6082 1472 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1473
c27a02cd 1474 /* Configure rx cq's and rings */
38aab07c
YP
1475 err = mlx4_en_activate_rx_rings(priv);
1476 if (err) {
453a6082 1477 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP
1478 return err;
1479 }
c27a02cd
YP
1480 for (i = 0; i < priv->rx_ring_num; i++) {
1481 cq = &priv->rx_cq[i];
c27a02cd 1482
9e77a2b8
AV
1483 mlx4_en_cq_init_lock(cq);
1484
76532d0c 1485 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1486 if (err) {
453a6082 1487 en_err(priv, "Failed activating Rx CQ\n");
a4233304 1488 goto cq_err;
c27a02cd
YP
1489 }
1490 for (j = 0; j < cq->size; j++)
1491 cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1492 err = mlx4_en_set_cq_moder(priv, cq);
1493 if (err) {
453a6082 1494 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP
1495 mlx4_en_deactivate_cq(priv, cq);
1496 goto cq_err;
1497 }
1498 mlx4_en_arm_cq(priv, cq);
38aab07c 1499 priv->rx_ring[i].cqn = cq->mcq.cqn;
c27a02cd
YP
1500 ++rx_index;
1501 }
1502
ffe455ad
EE
1503 /* Set qp number */
1504 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1505 err = mlx4_en_get_qp(priv);
1679200f 1506 if (err) {
ffe455ad 1507 en_err(priv, "Failed getting eth qp\n");
1679200f
YP
1508 goto cq_err;
1509 }
1510 mdev->mac_removed[priv->port] = 0;
1511
c27a02cd
YP
1512 err = mlx4_en_config_rss_steer(priv);
1513 if (err) {
453a6082 1514 en_err(priv, "Failed configuring rss steering\n");
1679200f 1515 goto mac_err;
c27a02cd
YP
1516 }
1517
cabdc8ee
HHZ
1518 err = mlx4_en_create_drop_qp(priv);
1519 if (err)
1520 goto rss_err;
1521
c27a02cd
YP
1522 /* Configure tx cq's and rings */
1523 for (i = 0; i < priv->tx_ring_num; i++) {
1524 /* Configure cq */
1525 cq = &priv->tx_cq[i];
76532d0c 1526 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1527 if (err) {
453a6082 1528 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP
1529 goto tx_err;
1530 }
1531 err = mlx4_en_set_cq_moder(priv, cq);
1532 if (err) {
453a6082 1533 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP
1534 mlx4_en_deactivate_cq(priv, cq);
1535 goto tx_err;
1536 }
453a6082 1537 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP
1538 cq->buf->wqe_index = cpu_to_be16(0xffff);
1539
1540 /* Configure ring */
1541 tx_ring = &priv->tx_ring[i];
0e98b523 1542 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1543 i / priv->num_tx_rings_p_up);
c27a02cd 1544 if (err) {
453a6082 1545 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP
1546 mlx4_en_deactivate_cq(priv, cq);
1547 goto tx_err;
1548 }
5b263f53 1549 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP
1550
1551 /* Arm CQ for TX completions */
1552 mlx4_en_arm_cq(priv, cq);
1553
c27a02cd
YP
1554 /* Set initial ownership of all Tx TXBBs to SW (1) */
1555 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1556 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1557 ++tx_index;
1558 }
1559
1560 /* Configure port */
1561 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1562 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP
1563 priv->prof->tx_pause,
1564 priv->prof->tx_ppp,
1565 priv->prof->rx_pause,
1566 priv->prof->rx_ppp);
c27a02cd 1567 if (err) {
48e551ff
YB
1568 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1569 priv->port, err);
c27a02cd
YP
1570 goto tx_err;
1571 }
1572 /* Set default qp number */
1573 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1574 if (err) {
453a6082 1575 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP
1576 goto tx_err;
1577 }
c27a02cd
YP
1578
1579 /* Init port */
453a6082 1580 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP
1581 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1582 if (err) {
453a6082 1583 en_err(priv, "Failed Initializing port\n");
1679200f 1584 goto tx_err;
c27a02cd
YP
1585 }
1586
1679200f
YP
1587 /* Attach rx QP to bradcast address */
1588 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1589 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1590 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ
1591 priv->port, 0, MLX4_PROT_ETH,
1592 &priv->broadcast_id))
1679200f
YP
1593 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1594
b5845f98
HX
1595 /* Must redo promiscuous mode setup. */
1596 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1597
c27a02cd 1598 /* Schedule multicast task to populate multicast list */
0eb74fdd 1599 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1600
93ece0c1
EE
1601 mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
1602
c27a02cd 1603 priv->port_up = true;
a11faac7 1604 netif_tx_start_all_queues(dev);
3484aac1
AV
1605 netif_device_attach(dev);
1606
c27a02cd
YP
1607 return 0;
1608
c27a02cd
YP
1609tx_err:
1610 while (tx_index--) {
1611 mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[tx_index]);
1612 mlx4_en_deactivate_cq(priv, &priv->tx_cq[tx_index]);
1613 }
cabdc8ee
HHZ
1614 mlx4_en_destroy_drop_qp(priv);
1615rss_err:
c27a02cd 1616 mlx4_en_release_rss_steer(priv);
1679200f 1617mac_err:
16a10ffd 1618 mlx4_en_put_qp(priv);
c27a02cd
YP
1619cq_err:
1620 while (rx_index--)
1621 mlx4_en_deactivate_cq(priv, &priv->rx_cq[rx_index]);
38aab07c
YP
1622 for (i = 0; i < priv->rx_ring_num; i++)
1623 mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]);
c27a02cd
YP
1624
1625 return err; /* need to close devices */
1626}
1627
1628
3484aac1 1629void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP
1630{
1631 struct mlx4_en_priv *priv = netdev_priv(dev);
1632 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1633 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1634 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1635 int i;
1679200f 1636 u8 mc_list[16] = {0};
c27a02cd
YP
1637
1638 if (!priv->port_up) {
453a6082 1639 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP
1640 return;
1641 }
c27a02cd 1642
0cc5c8bf
EE
1643 /* close port*/
1644 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1645
c27a02cd
YP
1646 /* Synchronize with tx routine */
1647 netif_tx_lock_bh(dev);
3484aac1
AV
1648 if (detach)
1649 netif_device_detach(dev);
3c05f5ef 1650 netif_tx_stop_all_queues(dev);
c27a02cd
YP
1651 netif_tx_unlock_bh(dev);
1652
3484aac1
AV
1653 netif_tx_disable(dev);
1654
7c287380 1655 /* Set port as not active */
3c05f5ef 1656 priv->port_up = false;
c27a02cd 1657
db0e7cba
AY
1658 /* Promsicuous mode */
1659 if (mdev->dev->caps.steering_mode ==
1660 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1661 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1662 MLX4_EN_FLAG_MC_PROMISC);
1663 mlx4_flow_steer_promisc_remove(mdev->dev,
1664 priv->port,
f9162539 1665 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY
1666 mlx4_flow_steer_promisc_remove(mdev->dev,
1667 priv->port,
f9162539 1668 MLX4_FS_MC_DEFAULT);
db0e7cba
AY
1669 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1670 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1671
1672 /* Disable promiscouos mode */
1673 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1674 priv->port);
1675
1676 /* Disable Multicast promisc */
1677 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1678 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1679 priv->port);
1680 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1681 }
1682 }
1683
1679200f
YP
1684 /* Detach All multicasts */
1685 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1686 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1687 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1688 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP
1689 list_for_each_entry(mclist, &priv->curr_list, list) {
1690 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP
1691 mc_list[5] = priv->port;
1692 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1693 mc_list, MLX4_PROT_ETH, mclist->reg_id);
1679200f
YP
1694 }
1695 mlx4_en_clear_list(dev);
6d199937
YP
1696 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1697 list_del(&mclist->list);
1698 kfree(mclist);
1699 }
1700
1679200f
YP
1701 /* Flush multicast filter */
1702 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1703
6efb5fac
HHZ
1704 /* Remove flow steering rules for the port*/
1705 if (mdev->dev->caps.steering_mode ==
1706 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1707 ASSERT_RTNL();
1708 list_for_each_entry_safe(flow, tmp_flow,
1709 &priv->ethtool_list, list) {
1710 mlx4_flow_detach(mdev->dev, flow->id);
1711 list_del(&flow->list);
1712 }
1713 }
1714
cabdc8ee
HHZ
1715 mlx4_en_destroy_drop_qp(priv);
1716
c27a02cd
YP
1717 /* Free TX Rings */
1718 for (i = 0; i < priv->tx_ring_num; i++) {
1719 mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[i]);
1720 mlx4_en_deactivate_cq(priv, &priv->tx_cq[i]);
1721 }
1722 msleep(10);
1723
1724 for (i = 0; i < priv->tx_ring_num; i++)
1725 mlx4_en_free_tx_buf(dev, &priv->tx_ring[i]);
1726
1727 /* Free RSS qps */
1728 mlx4_en_release_rss_steer(priv);
1729
ffe455ad 1730 /* Unregister Mac address for the port */
16a10ffd 1731 mlx4_en_put_qp(priv);
5930e8d0 1732 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1733 mdev->mac_removed[priv->port] = 1;
ffe455ad 1734
c27a02cd
YP
1735 /* Free RX Rings */
1736 for (i = 0; i < priv->rx_ring_num; i++) {
9e77a2b8
AV
1737 struct mlx4_en_cq *cq = &priv->rx_cq[i];
1738
1739 local_bh_disable();
1740 while (!mlx4_en_cq_lock_napi(cq)) {
1741 pr_info("CQ %d locked\n", i);
1742 mdelay(1);
1743 }
1744 local_bh_enable();
1745
9e77a2b8 1746 while (test_bit(NAPI_STATE_SCHED, &cq->napi.state))
c27a02cd 1747 msleep(1);
0cc5c8bf 1748 mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]);
9e77a2b8 1749 mlx4_en_deactivate_cq(priv, cq);
c27a02cd
YP
1750 }
1751}
1752
1753static void mlx4_en_restart(struct work_struct *work)
1754{
1755 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1756 watchdog_task);
1757 struct mlx4_en_dev *mdev = priv->mdev;
1758 struct net_device *dev = priv->dev;
1759
453a6082 1760 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP
1761
1762 mutex_lock(&mdev->state_lock);
1763 if (priv->port_up) {
3484aac1 1764 mlx4_en_stop_port(dev, 1);
1e338db5 1765 if (mlx4_en_start_port(dev))
453a6082 1766 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP
1767 }
1768 mutex_unlock(&mdev->state_lock);
c27a02cd
YP
1769}
1770
b477ba62 1771static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP
1772{
1773 struct mlx4_en_priv *priv = netdev_priv(dev);
1774 struct mlx4_en_dev *mdev = priv->mdev;
1775 int i;
c27a02cd 1776
c27a02cd 1777 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1778 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP
1779
1780 memset(&priv->stats, 0, sizeof(priv->stats));
1781 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE
1782 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1783 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
c27a02cd
YP
1784
1785 for (i = 0; i < priv->tx_ring_num; i++) {
1786 priv->tx_ring[i].bytes = 0;
1787 priv->tx_ring[i].packets = 0;
b477ba62 1788 priv->tx_ring[i].tx_csum = 0;
c27a02cd
YP
1789 }
1790 for (i = 0; i < priv->rx_ring_num; i++) {
1791 priv->rx_ring[i].bytes = 0;
1792 priv->rx_ring[i].packets = 0;
b477ba62
EE
1793 priv->rx_ring[i].csum_ok = 0;
1794 priv->rx_ring[i].csum_none = 0;
c27a02cd 1795 }
b477ba62
EE
1796}
1797
1798static int mlx4_en_open(struct net_device *dev)
1799{
1800 struct mlx4_en_priv *priv = netdev_priv(dev);
1801 struct mlx4_en_dev *mdev = priv->mdev;
1802 int err = 0;
1803
1804 mutex_lock(&mdev->state_lock);
1805
1806 if (!mdev->device_up) {
1807 en_err(priv, "Cannot open - device down/disabled\n");
1808 err = -EBUSY;
1809 goto out;
1810 }
1811
1812 /* Reset HW statistics and SW counters */
1813 mlx4_en_clear_stats(dev);
c27a02cd 1814
c27a02cd
YP
1815 err = mlx4_en_start_port(dev);
1816 if (err)
453a6082 1817 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP
1818
1819out:
1820 mutex_unlock(&mdev->state_lock);
1821 return err;
1822}
1823
1824
1825static int mlx4_en_close(struct net_device *dev)
1826{
1827 struct mlx4_en_priv *priv = netdev_priv(dev);
1828 struct mlx4_en_dev *mdev = priv->mdev;
1829
453a6082 1830 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP
1831
1832 mutex_lock(&mdev->state_lock);
1833
3484aac1 1834 mlx4_en_stop_port(dev, 0);
c27a02cd
YP
1835 netif_carrier_off(dev);
1836
1837 mutex_unlock(&mdev->state_lock);
1838 return 0;
1839}
1840
fe0af03c 1841void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP
1842{
1843 int i;
1844
1eb8c695
AV
1845#ifdef CONFIG_RFS_ACCEL
1846 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1847 priv->dev->rx_cpu_rmap = NULL;
1848#endif
1849
c27a02cd
YP
1850 for (i = 0; i < priv->tx_ring_num; i++) {
1851 if (priv->tx_ring[i].tx_info)
1852 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
1853 if (priv->tx_cq[i].buf)
fe0af03c 1854 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP
1855 }
1856
1857 for (i = 0; i < priv->rx_ring_num; i++) {
1858 if (priv->rx_ring[i].rx_info)
68355f71
TLSC
1859 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1860 priv->prof->rx_ring_size, priv->stride);
c27a02cd 1861 if (priv->rx_cq[i].buf)
fe0af03c 1862 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1863 }
044ca2a5
YP
1864
1865 if (priv->base_tx_qpn) {
1866 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1867 priv->base_tx_qpn = 0;
1868 }
c27a02cd
YP
1869}
1870
18cc42a3 1871int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1872{
c27a02cd
YP
1873 struct mlx4_en_port_profile *prof = priv->prof;
1874 int i;
044ca2a5 1875 int err;
87a5c389 1876
044ca2a5 1877 err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn);
87a5c389
YP
1878 if (err) {
1879 en_err(priv, "failed reserving range for TX rings\n");
1880 return err;
1881 }
c27a02cd
YP
1882
1883 /* Create tx Rings */
1884 for (i = 0; i < priv->tx_ring_num; i++) {
1885 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
1886 prof->tx_ring_size, i, TX))
1887 goto err;
1888
044ca2a5 1889 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], priv->base_tx_qpn + i,
c27a02cd
YP
1890 prof->tx_ring_size, TXBB_SIZE))
1891 goto err;
1892 }
1893
1894 /* Create rx Rings */
1895 for (i = 0; i < priv->rx_ring_num; i++) {
1896 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
1897 prof->rx_ring_size, i, RX))
1898 goto err;
1899
1900 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
1901 prof->rx_ring_size, priv->stride))
1902 goto err;
1903 }
1904
1eb8c695 1905#ifdef CONFIG_RFS_ACCEL
a229e488
AV
1906 if (priv->mdev->dev->caps.comp_pool) {
1907 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
1908 if (!priv->dev->rx_cpu_rmap)
1909 goto err;
1910 }
1eb8c695
AV
1911#endif
1912
c27a02cd
YP
1913 return 0;
1914
1915err:
453a6082 1916 en_err(priv, "Failed to allocate NIC resources\n");
c27a02cd
YP
1917 return -ENOMEM;
1918}
1919
1920
1921void mlx4_en_destroy_netdev(struct net_device *dev)
1922{
1923 struct mlx4_en_priv *priv = netdev_priv(dev);
1924 struct mlx4_en_dev *mdev = priv->mdev;
1925
453a6082 1926 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP
1927
1928 /* Unregister device - this will close the port if it was up */
1929 if (priv->registered)
1930 unregister_netdev(dev);
1931
1932 if (priv->allocated)
1933 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
1934
1935 cancel_delayed_work(&priv->stats_task);
b6c39bfc 1936 cancel_delayed_work(&priv->service_task);
c27a02cd
YP
1937 /* flush any pending task for this netdev */
1938 flush_workqueue(mdev->workqueue);
1939
1940 /* Detach the netdev so tasks would not attempt to access it */
1941 mutex_lock(&mdev->state_lock);
1942 mdev->pndev[priv->port] = NULL;
1943 mutex_unlock(&mdev->state_lock);
1944
fe0af03c 1945 mlx4_en_free_resources(priv);
564c274c 1946
bc6a4744
AV
1947 kfree(priv->tx_ring);
1948 kfree(priv->tx_cq);
1949
c27a02cd
YP
1950 free_netdev(dev);
1951}
1952
1953static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
1954{
1955 struct mlx4_en_priv *priv = netdev_priv(dev);
1956 struct mlx4_en_dev *mdev = priv->mdev;
1957 int err = 0;
1958
453a6082 1959 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP
1960 dev->mtu, new_mtu);
1961
1962 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 1963 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP
1964 return -EPERM;
1965 }
1966 dev->mtu = new_mtu;
1967
1968 if (netif_running(dev)) {
1969 mutex_lock(&mdev->state_lock);
1970 if (!mdev->device_up) {
1971 /* NIC is probably restarting - let watchdog task reset
1972 * the port */
453a6082 1973 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 1974 } else {
3484aac1 1975 mlx4_en_stop_port(dev, 1);
c27a02cd
YP
1976 err = mlx4_en_start_port(dev);
1977 if (err) {
453a6082 1978 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP
1979 priv->port);
1980 queue_work(mdev->workqueue, &priv->watchdog_task);
1981 }
1982 }
1983 mutex_unlock(&mdev->state_lock);
1984 }
1985 return 0;
1986}
1987
ec693d47
AV
1988static int mlx4_en_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1989{
1990 struct mlx4_en_priv *priv = netdev_priv(dev);
1991 struct mlx4_en_dev *mdev = priv->mdev;
1992 struct hwtstamp_config config;
1993
1994 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1995 return -EFAULT;
1996
1997 /* reserved for future extensions */
1998 if (config.flags)
1999 return -EINVAL;
2000
2001 /* device doesn't support time stamping */
2002 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2003 return -EINVAL;
2004
2005 /* TX HW timestamp */
2006 switch (config.tx_type) {
2007 case HWTSTAMP_TX_OFF:
2008 case HWTSTAMP_TX_ON:
2009 break;
2010 default:
2011 return -ERANGE;
2012 }
2013
2014 /* RX HW timestamp */
2015 switch (config.rx_filter) {
2016 case HWTSTAMP_FILTER_NONE:
2017 break;
2018 case HWTSTAMP_FILTER_ALL:
2019 case HWTSTAMP_FILTER_SOME:
2020 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2021 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2022 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2023 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2024 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2025 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2026 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2027 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2028 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2029 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2030 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2031 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2032 config.rx_filter = HWTSTAMP_FILTER_ALL;
2033 break;
2034 default:
2035 return -ERANGE;
2036 }
2037
2038 if (mlx4_en_timestamp_config(dev, config.tx_type, config.rx_filter)) {
2039 config.tx_type = HWTSTAMP_TX_OFF;
2040 config.rx_filter = HWTSTAMP_FILTER_NONE;
2041 }
2042
2043 return copy_to_user(ifr->ifr_data, &config,
2044 sizeof(config)) ? -EFAULT : 0;
2045}
2046
2047static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2048{
2049 switch (cmd) {
2050 case SIOCSHWTSTAMP:
2051 return mlx4_en_hwtstamp_ioctl(dev, ifr);
2052 default:
2053 return -EOPNOTSUPP;
2054 }
2055}
2056
60d6fe99
AV
2057static int mlx4_en_set_features(struct net_device *netdev,
2058 netdev_features_t features)
2059{
2060 struct mlx4_en_priv *priv = netdev_priv(netdev);
2061
2062 if (features & NETIF_F_LOOPBACK)
2063 priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2064 else
2065 priv->ctrl_flags &=
2066 cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
2067
79aeaccd
YB
2068 mlx4_en_update_loopback_state(netdev, features);
2069
60d6fe99
AV
2070 return 0;
2071
2072}
2073
8f7ba3ca
RE
2074static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2075{
2076 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2077 struct mlx4_en_dev *mdev = en_priv->mdev;
2078 u64 mac_u64 = mlx4_en_mac_to_u64(mac);
2079
2080 if (!is_valid_ether_addr(mac))
2081 return -EINVAL;
2082
2083 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2084}
2085
3f7fb021
RE
2086static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2087{
2088 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2089 struct mlx4_en_dev *mdev = en_priv->mdev;
2090
2091 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2092}
2093
e6b6a231
RE
2094static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2095{
2096 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2097 struct mlx4_en_dev *mdev = en_priv->mdev;
2098
2099 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2100}
2101
2cccb9e4
RE
2102static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2103{
2104 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2105 struct mlx4_en_dev *mdev = en_priv->mdev;
2106
2107 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2108}
8f7ba3ca 2109
948e306d
RE
2110static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2111{
2112 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2113 struct mlx4_en_dev *mdev = en_priv->mdev;
2114
2115 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2116}
3addc568
SH
2117static const struct net_device_ops mlx4_netdev_ops = {
2118 .ndo_open = mlx4_en_open,
2119 .ndo_stop = mlx4_en_close,
2120 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2121 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2122 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2123 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2124 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2125 .ndo_validate_addr = eth_validate_addr,
3addc568 2126 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2127 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2128 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH
2129 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2130 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2131#ifdef CONFIG_NET_POLL_CONTROLLER
2132 .ndo_poll_controller = mlx4_en_netpoll,
2133#endif
60d6fe99 2134 .ndo_set_features = mlx4_en_set_features,
897d7846 2135 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV
2136#ifdef CONFIG_RFS_ACCEL
2137 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2138#endif
e0d1095a 2139#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2140 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2141#endif
3addc568
SH
2142};
2143
8f7ba3ca
RE
2144static const struct net_device_ops mlx4_netdev_ops_master = {
2145 .ndo_open = mlx4_en_open,
2146 .ndo_stop = mlx4_en_close,
2147 .ndo_start_xmit = mlx4_en_xmit,
2148 .ndo_select_queue = mlx4_en_select_queue,
2149 .ndo_get_stats = mlx4_en_get_stats,
2150 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2151 .ndo_set_mac_address = mlx4_en_set_mac,
2152 .ndo_validate_addr = eth_validate_addr,
2153 .ndo_change_mtu = mlx4_en_change_mtu,
2154 .ndo_tx_timeout = mlx4_en_tx_timeout,
2155 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2156 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2157 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2158 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
e6b6a231 2159 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2160 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2161 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE
2162#ifdef CONFIG_NET_POLL_CONTROLLER
2163 .ndo_poll_controller = mlx4_en_netpoll,
2164#endif
2165 .ndo_set_features = mlx4_en_set_features,
2166 .ndo_setup_tc = mlx4_en_setup_tc,
2167#ifdef CONFIG_RFS_ACCEL
2168 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2169#endif
2170};
2171
c27a02cd
YP
2172int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2173 struct mlx4_en_port_profile *prof)
2174{
2175 struct net_device *dev;
2176 struct mlx4_en_priv *priv;
c07cb4b0 2177 int i;
c27a02cd 2178 int err;
ef96f7d4 2179 u64 mac_u64;
c27a02cd 2180
f1593d22 2181 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2182 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2183 if (dev == NULL)
c27a02cd 2184 return -ENOMEM;
c27a02cd 2185
d317966b
AV
2186 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2187 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2188
c27a02cd 2189 SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev);
741a00be 2190 dev->dev_id = port - 1;
c27a02cd
YP
2191
2192 /*
2193 * Initialize driver private data
2194 */
2195
2196 priv = netdev_priv(dev);
2197 memset(priv, 0, sizeof(struct mlx4_en_priv));
2198 priv->dev = dev;
2199 priv->mdev = mdev;
ebf8c9aa 2200 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP
2201 priv->prof = prof;
2202 priv->port = port;
2203 priv->port_up = false;
c27a02cd 2204 priv->flags = prof->flags;
60d6fe99
AV
2205 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2206 MLX4_WQE_CTRL_SOLICITED);
d317966b 2207 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2208 priv->tx_ring_num = prof->tx_ring_num;
d317966b
AV
2209
2210 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring) * MAX_TX_RINGS,
2211 GFP_KERNEL);
bc6a4744
AV
2212 if (!priv->tx_ring) {
2213 err = -ENOMEM;
2214 goto out;
2215 }
427a9625 2216 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq) * MAX_TX_RINGS,
d317966b 2217 GFP_KERNEL);
bc6a4744
AV
2218 if (!priv->tx_cq) {
2219 err = -ENOMEM;
2220 goto out;
2221 }
c27a02cd 2222 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2223 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
c27a02cd
YP
2224 priv->mac_index = -1;
2225 priv->msg_enable = MLX4_EN_MSG_LEVEL;
2226 spin_lock_init(&priv->stats_lock);
0eb74fdd 2227 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
c27a02cd
YP
2228 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2229 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2230 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
b6c39bfc 2231 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
564c274c 2232#ifdef CONFIG_MLX4_EN_DCB
540b3a39
OG
2233 if (!mlx4_is_slave(priv->mdev->dev)) {
2234 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
2235 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2236 } else {
2237 en_info(priv, "enabling only PFC DCB ops\n");
2238 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2239 }
2240 }
564c274c 2241#endif
c27a02cd 2242
c07cb4b0
YB
2243 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2244 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2245
c27a02cd
YP
2246 /* Query for default mac and max mtu */
2247 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99
YB
2248
2249 /* Set default MAC */
2250 dev->addr_len = ETH_ALEN;
2251 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2252 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG
2253 if (mlx4_is_slave(priv->mdev->dev)) {
2254 eth_hw_addr_random(dev);
2255 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
2256 mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
2257 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2258 } else {
2259 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2260 priv->port, dev->dev_addr);
2261 err = -EINVAL;
2262 goto out;
2263 }
c27a02cd
YP
2264 }
2265
6bbb6d99
YB
2266 memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
2267
c27a02cd
YP
2268 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2269 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2270 err = mlx4_en_alloc_resources(priv);
2271 if (err)
2272 goto out;
2273
78fb2de7
AV
2274#ifdef CONFIG_RFS_ACCEL
2275 INIT_LIST_HEAD(&priv->filters);
2276 spin_lock_init(&priv->filters_lock);
2277#endif
2278
ec693d47
AV
2279 /* Initialize time stamping config */
2280 priv->hwtstamp_config.flags = 0;
2281 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2282 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2283
c27a02cd
YP
2284 /* Allocate page for receive rings */
2285 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2286 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2287 if (err) {
453a6082 2288 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP
2289 goto out;
2290 }
2291 priv->allocated = 1;
2292
c27a02cd
YP
2293 /*
2294 * Initialize netdev entry points
2295 */
8f7ba3ca
RE
2296 if (mlx4_is_master(priv->mdev->dev))
2297 dev->netdev_ops = &mlx4_netdev_ops_master;
2298 else
2299 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2300 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH
2301 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2302 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2303
c27a02cd
YP
2304 SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
2305
c27a02cd
YP
2306 /*
2307 * Set driver features
2308 */
c8c64cff
MM
2309 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2310 if (mdev->LSO_support)
2311 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2312
2313 dev->vlan_features = dev->hw_features;
2314
ad86107f 2315 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2316 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM
2317 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2318 NETIF_F_HW_VLAN_CTAG_FILTER;
60d6fe99 2319 dev->hw_features |= NETIF_F_LOOPBACK;
c27a02cd 2320
1eb8c695
AV
2321 if (mdev->dev->caps.steering_mode ==
2322 MLX4_STEERING_MODE_DEVICE_MANAGED)
2323 dev->hw_features |= NETIF_F_NTUPLE;
2324
cc5387f7
YB
2325 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2326 dev->priv_flags |= IFF_UNICAST_FLT;
2327
c27a02cd
YP
2328 mdev->pndev[port] = dev;
2329
2330 netif_carrier_off(dev);
4801ae70
EE
2331 mlx4_en_set_default_moderation(priv);
2332
c27a02cd
YP
2333 err = register_netdev(dev);
2334 if (err) {
453a6082 2335 en_err(priv, "Netdev registration failed for port %d\n", port);
c27a02cd
YP
2336 goto out;
2337 }
4234144f 2338 priv->registered = 1;
453a6082
YP
2339
2340 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2341 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2342
79aeaccd
YB
2343 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2344
90822265 2345 /* Configure port */
5c8e9046 2346 mlx4_en_calc_rx_buf(dev);
90822265 2347 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP
2348 priv->rx_skb_size + ETH_FCS_LEN,
2349 prof->tx_pause, prof->tx_ppp,
2350 prof->rx_pause, prof->rx_ppp);
90822265
YP
2351 if (err) {
2352 en_err(priv, "Failed setting port general configurations "
2353 "for port %d, with error %d\n", priv->port, err);
2354 goto out;
2355 }
2356
2357 /* Init port */
2358 en_warn(priv, "Initializing port\n");
2359 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2360 if (err) {
2361 en_err(priv, "Failed Initializing port\n");
2362 goto out;
2363 }
c27a02cd 2364 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV
2365
2366 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2367 queue_delayed_work(mdev->workqueue, &priv->service_task,
2368 SERVICE_TASK_DELAY);
2369
c27a02cd
YP
2370 return 0;
2371
2372out:
2373 mlx4_en_destroy_netdev(dev);
2374 return err;
2375}
2376