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r8152: correct some messages
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
c27a02cd
YP		 42
43#include <linux/mlx4/driver.h>
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/cmd.h>
46#include <linux/mlx4/cq.h>
47
48#include "mlx4_en.h"
49#include "en_port.h"
50
d317966b 51int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 52{
bc6a4744
AV		 53 struct mlx4_en_priv *priv = netdev_priv(dev);
54 int i;
d317966b 55 unsigned int offset = 0;
bc6a4744
AV		 56
57 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 58 return -EINVAL;
59
bc6a4744
AV		 60 netdev_set_num_tc(dev, up);
61
62 /* Partition Tx queues evenly amongst UP's */
bc6a4744 63 for (i = 0; i < up; i++) {
d317966b
AV		 64 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
65 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 66 }
67
897d7846
AV		 68 return 0;
69}
70
e0d1095a 71#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 72/* must be called with local_bh_disable()d */
73static int mlx4_en_low_latency_recv(struct napi_struct *napi)
74{
75 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
76 struct net_device *dev = cq->dev;
77 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 78 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 79 int done;
80
81 if (!priv->port_up)
82 return LL_FLUSH_FAILED;
83
84 if (!mlx4_en_cq_lock_poll(cq))
85 return LL_FLUSH_BUSY;
86
87 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 88 if (likely(done))
89 rx_ring->cleaned += done;
90 else
91 rx_ring->misses++;
9e77a2b8
AV		 92
93 mlx4_en_cq_unlock_poll(cq);
94
95 return done;
96}
e0d1095a 97#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 98
1eb8c695
AV		 99#ifdef CONFIG_RFS_ACCEL
100
101struct mlx4_en_filter {
102 struct list_head next;
103 struct work_struct work;
104
75a353d4 105 u8 ip_proto;
1eb8c695
AV		 106 __be32 src_ip;
107 __be32 dst_ip;
108 __be16 src_port;
109 __be16 dst_port;
110
111 int rxq_index;
112 struct mlx4_en_priv *priv;
113 u32 flow_id; /* RFS infrastructure id */
114 int id; /* mlx4_en driver id */
115 u64 reg_id; /* Flow steering API id */
116 u8 activated; /* Used to prevent expiry before filter
117 * is attached
118 */
119 struct hlist_node filter_chain;
120};
121
122static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
123
75a353d4
EP		 124static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
125{
126 switch (ip_proto) {
127 case IPPROTO_UDP:
128 return MLX4_NET_TRANS_RULE_ID_UDP;
129 case IPPROTO_TCP:
130 return MLX4_NET_TRANS_RULE_ID_TCP;
131 default:
132 return -EPROTONOSUPPORT;
133 }
134};
135
1eb8c695
AV		 136static void mlx4_en_filter_work(struct work_struct *work)
137{
138 struct mlx4_en_filter *filter = container_of(work,
139 struct mlx4_en_filter,
140 work);
141 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 142 struct mlx4_spec_list spec_tcp_udp = {
143 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 144 {
145 .tcp_udp = {
146 .dst_port = filter->dst_port,
147 .dst_port_msk = (__force __be16)-1,
148 .src_port = filter->src_port,
149 .src_port_msk = (__force __be16)-1,
150 },
151 },
152 };
153 struct mlx4_spec_list spec_ip = {
154 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
155 {
156 .ipv4 = {
157 .dst_ip = filter->dst_ip,
158 .dst_ip_msk = (__force __be32)-1,
159 .src_ip = filter->src_ip,
160 .src_ip_msk = (__force __be32)-1,
161 },
162 },
163 };
164 struct mlx4_spec_list spec_eth = {
165 .id = MLX4_NET_TRANS_RULE_ID_ETH,
166 };
167 struct mlx4_net_trans_rule rule = {
168 .list = LIST_HEAD_INIT(rule.list),
169 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
170 .exclusive = 1,
171 .allow_loopback = 1,
f9162539 172 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 173 .port = priv->port,
174 .priority = MLX4_DOMAIN_RFS,
175 };
176 int rc;
1eb8c695
AV		 177 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
178
75a353d4
EP		 179 if (spec_tcp_udp.id < 0) {
180 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
181 filter->ip_proto);
182 goto ignore;
183 }
1eb8c695
AV		 184 list_add_tail(&spec_eth.list, &rule.list);
185 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 186 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 187
1eb8c695 188 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 189 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 190 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
191
192 filter->activated = 0;
193
194 if (filter->reg_id) {
195 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
196 if (rc && rc != -ENOENT)
197 en_err(priv, "Error detaching flow. rc = %d\n", rc);
198 }
199
200 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
201 if (rc)
202 en_err(priv, "Error attaching flow. err = %d\n", rc);
203
75a353d4 204ignore:
1eb8c695
AV		 205 mlx4_en_filter_rfs_expire(priv);
206
207 filter->activated = 1;
208}
209
210static inline struct hlist_head *
211filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
212 __be16 src_port, __be16 dst_port)
213{
214 unsigned long l;
215 int bucket_idx;
216
217 l = (__force unsigned long)src_port |
218 ((__force unsigned long)dst_port << 2);
219 l ^= (__force unsigned long)(src_ip ^ dst_ip);
220
221 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
222
223 return &priv->filter_hash[bucket_idx];
224}
225
226static struct mlx4_en_filter *
227mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 228 __be32 dst_ip, u8 ip_proto, __be16 src_port,
229 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 230{
231 struct mlx4_en_filter *filter = NULL;
232
233 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
234 if (!filter)
235 return NULL;
236
237 filter->priv = priv;
238 filter->rxq_index = rxq_index;
239 INIT_WORK(&filter->work, mlx4_en_filter_work);
240
241 filter->src_ip = src_ip;
242 filter->dst_ip = dst_ip;
75a353d4 243 filter->ip_proto = ip_proto;
1eb8c695
AV		 244 filter->src_port = src_port;
245 filter->dst_port = dst_port;
246
247 filter->flow_id = flow_id;
248
ee64c0ee 249 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 250
251 list_add_tail(&filter->next, &priv->filters);
252 hlist_add_head(&filter->filter_chain,
253 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
254 dst_port));
255
256 return filter;
257}
258
259static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
260{
261 struct mlx4_en_priv *priv = filter->priv;
262 int rc;
263
264 list_del(&filter->next);
265
266 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
267 if (rc && rc != -ENOENT)
268 en_err(priv, "Error detaching flow. rc = %d\n", rc);
269
270 kfree(filter);
271}
272
273static inline struct mlx4_en_filter *
274mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 275 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 276{
1eb8c695
AV		 277 struct mlx4_en_filter *filter;
278 struct mlx4_en_filter *ret = NULL;
279
b67bfe0d 280 hlist_for_each_entry(filter,
1eb8c695
AV		 281 filter_hash_bucket(priv, src_ip, dst_ip,
282 src_port, dst_port),
283 filter_chain) {
284 if (filter->src_ip == src_ip &&
285 filter->dst_ip == dst_ip &&
75a353d4 286 filter->ip_proto == ip_proto &&
1eb8c695
AV		 287 filter->src_port == src_port &&
288 filter->dst_port == dst_port) {
289 ret = filter;
290 break;
291 }
292 }
293
294 return ret;
295}
296
297static int
298mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
299 u16 rxq_index, u32 flow_id)
300{
301 struct mlx4_en_priv *priv = netdev_priv(net_dev);
302 struct mlx4_en_filter *filter;
303 const struct iphdr *ip;
304 const __be16 *ports;
75a353d4 305 u8 ip_proto;
1eb8c695
AV		 306 __be32 src_ip;
307 __be32 dst_ip;
308 __be16 src_port;
309 __be16 dst_port;
310 int nhoff = skb_network_offset(skb);
311 int ret = 0;
312
313 if (skb->protocol != htons(ETH_P_IP))
314 return -EPROTONOSUPPORT;
315
316 ip = (const struct iphdr *)(skb->data + nhoff);
317 if (ip_is_fragment(ip))
318 return -EPROTONOSUPPORT;
319
75a353d4
EP		 320 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
321 return -EPROTONOSUPPORT;
1eb8c695
AV		 322 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
323
75a353d4 324 ip_proto = ip->protocol;
1eb8c695
AV		 325 src_ip = ip->saddr;
326 dst_ip = ip->daddr;
327 src_port = ports[0];
328 dst_port = ports[1];
329
1eb8c695 330 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 331 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
332 src_port, dst_port);
1eb8c695
AV		 333 if (filter) {
334 if (filter->rxq_index == rxq_index)
335 goto out;
336
337 filter->rxq_index = rxq_index;
338 } else {
339 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 340 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 341 src_port, dst_port, flow_id);
342 if (!filter) {
343 ret = -ENOMEM;
344 goto err;
345 }
346 }
347
348 queue_work(priv->mdev->workqueue, &filter->work);
349
350out:
351 ret = filter->id;
352err:
353 spin_unlock_bh(&priv->filters_lock);
354
355 return ret;
356}
357
41d942d5 358void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 359{
360 struct mlx4_en_filter *filter, *tmp;
361 LIST_HEAD(del_list);
362
363 spin_lock_bh(&priv->filters_lock);
364 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
365 list_move(&filter->next, &del_list);
366 hlist_del(&filter->filter_chain);
367 }
368 spin_unlock_bh(&priv->filters_lock);
369
370 list_for_each_entry_safe(filter, tmp, &del_list, next) {
371 cancel_work_sync(&filter->work);
372 mlx4_en_filter_free(filter);
373 }
374}
375
376static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
377{
378 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
379 LIST_HEAD(del_list);
380 int i = 0;
381
382 spin_lock_bh(&priv->filters_lock);
383 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
384 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
385 break;
386
387 if (filter->activated &&
388 !work_pending(&filter->work) &&
389 rps_may_expire_flow(priv->dev,
390 filter->rxq_index, filter->flow_id,
391 filter->id)) {
392 list_move(&filter->next, &del_list);
393 hlist_del(&filter->filter_chain);
394 } else
395 last_filter = filter;
396
397 i++;
398 }
399
400 if (last_filter && (&last_filter->next != priv->filters.next))
401 list_move(&priv->filters, &last_filter->next);
402
403 spin_unlock_bh(&priv->filters_lock);
404
405 list_for_each_entry_safe(filter, tmp, &del_list, next)
406 mlx4_en_filter_free(filter);
407}
408#endif
409
80d5c368
PM		 410static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
411 __be16 proto, u16 vid)
c27a02cd
YP		 412{
413 struct mlx4_en_priv *priv = netdev_priv(dev);
414 struct mlx4_en_dev *mdev = priv->mdev;
415 int err;
4c3eb3ca 416 int idx;
c27a02cd 417
f1b553fb 418 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 419
f1b553fb 420 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 421
422 /* Add VID to port VLAN filter */
423 mutex_lock(&mdev->state_lock);
424 if (mdev->device_up && priv->port_up) {
f1b553fb 425 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 426 if (err)
453a6082 427 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 428 }
4c3eb3ca 429 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 430 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 431 mutex_unlock(&mdev->state_lock);
4c3eb3ca 432
8e586137 433 return 0;
c27a02cd
YP		 434}
435
80d5c368
PM		 436static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
437 __be16 proto, u16 vid)
c27a02cd
YP		 438{
439 struct mlx4_en_priv *priv = netdev_priv(dev);
440 struct mlx4_en_dev *mdev = priv->mdev;
441 int err;
442
f1b553fb 443 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 444
f1b553fb 445 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 446
447 /* Remove VID from port VLAN filter */
448 mutex_lock(&mdev->state_lock);
2009d005 449 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 450
c27a02cd 451 if (mdev->device_up && priv->port_up) {
f1b553fb 452 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 453 if (err)
453a6082 454 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 455 }
456 mutex_unlock(&mdev->state_lock);
8e586137
JP		 457
458 return 0;
c27a02cd
YP		 459}
460
6bbb6d99
YB		 461static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
462{
bab6a9ea
YB		 463 int i;
464 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 465 dst_mac[i] = src_mac & 0xff;
466 src_mac >>= 8;
467 }
468 memset(&dst_mac[ETH_ALEN], 0, 2);
469}
470
837052d0
OG		 471
472static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
473 int qpn, u64 *reg_id)
474{
475 int err;
476 struct mlx4_spec_list spec_eth_outer = { {NULL} };
477 struct mlx4_spec_list spec_vxlan = { {NULL} };
478 struct mlx4_spec_list spec_eth_inner = { {NULL} };
479
480 struct mlx4_net_trans_rule rule = {
481 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
482 .exclusive = 0,
483 .allow_loopback = 1,
484 .promisc_mode = MLX4_FS_REGULAR,
485 .priority = MLX4_DOMAIN_NIC,
486 };
487
488 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
489
490 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
491 return 0; /* do nothing */
492
493 rule.port = priv->port;
494 rule.qpn = qpn;
495 INIT_LIST_HEAD(&rule.list);
496
497 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
498 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
499 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
500
501 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
502 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
503
504 list_add_tail(&spec_eth_outer.list, &rule.list);
505 list_add_tail(&spec_vxlan.list, &rule.list);
506 list_add_tail(&spec_eth_inner.list, &rule.list);
507
508 err = mlx4_flow_attach(priv->mdev->dev, &rule, reg_id);
509 if (err) {
510 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
511 return err;
512 }
513 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
514 return 0;
515}
516
517
16a10ffd
YB		 518static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
519 unsigned char *mac, int *qpn, u64 *reg_id)
520{
521 struct mlx4_en_dev *mdev = priv->mdev;
522 struct mlx4_dev *dev = mdev->dev;
523 int err;
524
525 switch (dev->caps.steering_mode) {
526 case MLX4_STEERING_MODE_B0: {
527 struct mlx4_qp qp;
528 u8 gid[16] = {0};
529
530 qp.qpn = *qpn;
531 memcpy(&gid[10], mac, ETH_ALEN);
532 gid[5] = priv->port;
533
534 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
535 break;
536 }
537 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
538 struct mlx4_spec_list spec_eth = { {NULL} };
539 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
540
541 struct mlx4_net_trans_rule rule = {
542 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
543 .exclusive = 0,
544 .allow_loopback = 1,
f9162539 545 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 546 .priority = MLX4_DOMAIN_NIC,
547 };
548
549 rule.port = priv->port;
550 rule.qpn = *qpn;
551 INIT_LIST_HEAD(&rule.list);
552
553 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
554 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
555 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
556 list_add_tail(&spec_eth.list, &rule.list);
557
558 err = mlx4_flow_attach(dev, &rule, reg_id);
559 break;
560 }
561 default:
562 return -EINVAL;
563 }
564 if (err)
565 en_warn(priv, "Failed Attaching Unicast\n");
566
567 return err;
568}
569
570static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
571 unsigned char *mac, int qpn, u64 reg_id)
572{
573 struct mlx4_en_dev *mdev = priv->mdev;
574 struct mlx4_dev *dev = mdev->dev;
575
576 switch (dev->caps.steering_mode) {
577 case MLX4_STEERING_MODE_B0: {
578 struct mlx4_qp qp;
579 u8 gid[16] = {0};
580
581 qp.qpn = qpn;
582 memcpy(&gid[10], mac, ETH_ALEN);
583 gid[5] = priv->port;
584
585 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
586 break;
587 }
588 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
589 mlx4_flow_detach(dev, reg_id);
590 break;
591 }
592 default:
593 en_err(priv, "Invalid steering mode.\n");
594 }
595}
596
597static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
598{
599 struct mlx4_en_dev *mdev = priv->mdev;
600 struct mlx4_dev *dev = mdev->dev;
601 struct mlx4_mac_entry *entry;
602 int index = 0;
603 int err = 0;
604 u64 reg_id;
605 int *qpn = &priv->base_qpn;
606 u64 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
607
608 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
609 priv->dev->dev_addr);
610 index = mlx4_register_mac(dev, priv->port, mac);
611 if (index < 0) {
612 err = index;
613 en_err(priv, "Failed adding MAC: %pM\n",
614 priv->dev->dev_addr);
615 return err;
616 }
617
618 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
619 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
620 *qpn = base_qpn + index;
621 return 0;
622 }
623
624 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
625 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
626 if (err) {
627 en_err(priv, "Failed to reserve qp for mac registration\n");
628 goto qp_err;
629 }
630
631 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
632 if (err)
633 goto steer_err;
634
837052d0
OG		 635 if (mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
636 &priv->tunnel_reg_id))
637 goto tunnel_err;
638
16a10ffd
YB		 639 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
640 if (!entry) {
641 err = -ENOMEM;
642 goto alloc_err;
643 }
644 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
645 entry->reg_id = reg_id;
646
c07cb4b0
YB		 647 hlist_add_head_rcu(&entry->hlist,
648 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 649
c07cb4b0 650 return 0;
16a10ffd
YB		 651
652alloc_err:
837052d0
OG		 653 if (priv->tunnel_reg_id)
654 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
655tunnel_err:
16a10ffd
YB		 656 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
657
658steer_err:
659 mlx4_qp_release_range(dev, *qpn, 1);
660
661qp_err:
662 mlx4_unregister_mac(dev, priv->port, mac);
663 return err;
664}
665
666static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
667{
668 struct mlx4_en_dev *mdev = priv->mdev;
669 struct mlx4_dev *dev = mdev->dev;
16a10ffd 670 int qpn = priv->base_qpn;
83a5a6ce 671 u64 mac;
16a10ffd 672
83a5a6ce
YB		 673 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
674 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
675 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
676 priv->dev->dev_addr);
677 mlx4_unregister_mac(dev, priv->port, mac);
678 } else {
c07cb4b0 679 struct mlx4_mac_entry *entry;
b67bfe0d 680 struct hlist_node *tmp;
c07cb4b0 681 struct hlist_head *bucket;
83a5a6ce 682 unsigned int i;
c07cb4b0 683
83a5a6ce
YB		 684 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
685 bucket = &priv->mac_hash[i];
686 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
687 mac = mlx4_en_mac_to_u64(entry->mac);
688 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
689 entry->mac);
c07cb4b0
YB		 690 mlx4_en_uc_steer_release(priv, entry->mac,
691 qpn, entry->reg_id);
c07cb4b0 692
83a5a6ce 693 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 694 hlist_del_rcu(&entry->hlist);
695 kfree_rcu(entry, rcu);
c07cb4b0 696 }
16a10ffd 697 }
83a5a6ce 698
837052d0
OG		 699 if (priv->tunnel_reg_id) {
700 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
701 priv->tunnel_reg_id = 0;
702 }
703
83a5a6ce
YB		 704 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
705 priv->port, qpn);
706 mlx4_qp_release_range(dev, qpn, 1);
707 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 708 }
709}
710
711static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 712 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 713{
714 struct mlx4_en_dev *mdev = priv->mdev;
715 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 716 int err = 0;
717 u64 new_mac_u64 = mlx4_en_mac_to_u64(new_mac);
718
719 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 720 struct hlist_head *bucket;
721 unsigned int mac_hash;
722 struct mlx4_mac_entry *entry;
b67bfe0d 723 struct hlist_node *tmp;
c07cb4b0
YB		 724 u64 prev_mac_u64 = mlx4_en_mac_to_u64(prev_mac);
725
726 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 727 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 728 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
729 mlx4_en_uc_steer_release(priv, entry->mac,
730 qpn, entry->reg_id);
731 mlx4_unregister_mac(dev, priv->port,
732 prev_mac_u64);
733 hlist_del_rcu(&entry->hlist);
734 synchronize_rcu();
735 memcpy(entry->mac, new_mac, ETH_ALEN);
736 entry->reg_id = 0;
737 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
738 hlist_add_head_rcu(&entry->hlist,
739 &priv->mac_hash[mac_hash]);
740 mlx4_register_mac(dev, priv->port, new_mac_u64);
741 err = mlx4_en_uc_steer_add(priv, new_mac,
742 &qpn,
743 &entry->reg_id);
744 return err;
745 }
746 }
747 return -EINVAL;
16a10ffd
YB		 748 }
749
750 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
751}
752
e7c1c2c4 753u64 mlx4_en_mac_to_u64(u8 *addr)
c27a02cd
YP		 754{
755 u64 mac = 0;
756 int i;
757
758 for (i = 0; i < ETH_ALEN; i++) {
759 mac <<= 8;
760 mac |= addr[i];
761 }
762 return mac;
763}
764
bfa8ab47 765static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv)
c27a02cd 766{
c27a02cd
YP		 767 int err = 0;
768
c27a02cd
YP		 769 if (priv->port_up) {
770 /* Remove old MAC and insert the new one */
16a10ffd 771 err = mlx4_en_replace_mac(priv, priv->base_qpn,
90bbb74a 772 priv->dev->dev_addr, priv->prev_mac);
c27a02cd 773 if (err)
453a6082 774 en_err(priv, "Failed changing HW MAC address\n");
6bbb6d99
YB		 775 memcpy(priv->prev_mac, priv->dev->dev_addr,
776 sizeof(priv->prev_mac));
c27a02cd 777 } else
48e551ff 778 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 779
bfa8ab47
YB		 780 return err;
781}
782
783static int mlx4_en_set_mac(struct net_device *dev, void *addr)
784{
785 struct mlx4_en_priv *priv = netdev_priv(dev);
786 struct mlx4_en_dev *mdev = priv->mdev;
787 struct sockaddr *saddr = addr;
788 int err;
789
790 if (!is_valid_ether_addr(saddr->sa_data))
791 return -EADDRNOTAVAIL;
792
793 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
794
795 mutex_lock(&mdev->state_lock);
796 err = mlx4_en_do_set_mac(priv);
c27a02cd 797 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 798
799 return err;
c27a02cd
YP		 800}
801
802static void mlx4_en_clear_list(struct net_device *dev)
803{
804 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 805 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 806
6d199937
YP		 807 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
808 list_del(&mc_to_del->list);
809 kfree(mc_to_del);
810 }
c27a02cd
YP		 811}
812
813static void mlx4_en_cache_mclist(struct net_device *dev)
814{
815 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 816 struct netdev_hw_addr *ha;
6d199937 817 struct mlx4_en_mc_list *tmp;
ff6e2163 818
0e03567a 819 mlx4_en_clear_list(dev);
6d199937
YP		 820 netdev_for_each_mc_addr(ha, dev) {
821 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
822 if (!tmp) {
6d199937
YP		 823 mlx4_en_clear_list(dev);
824 return;
825 }
826 memcpy(tmp->addr, ha->addr, ETH_ALEN);
827 list_add_tail(&tmp->list, &priv->mc_list);
828 }
c27a02cd
YP		 829}
830
6d199937
YP		 831static void update_mclist_flags(struct mlx4_en_priv *priv,
832 struct list_head *dst,
833 struct list_head *src)
834{
835 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
836 bool found;
837
838 /* Find all the entries that should be removed from dst,
839 * These are the entries that are not found in src
840 */
841 list_for_each_entry(dst_tmp, dst, list) {
842 found = false;
843 list_for_each_entry(src_tmp, src, list) {
c0623e58 844 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 845 found = true;
846 break;
847 }
848 }
849 if (!found)
850 dst_tmp->action = MCLIST_REM;
851 }
852
853 /* Add entries that exist in src but not in dst
854 * mark them as need to add
855 */
856 list_for_each_entry(src_tmp, src, list) {
857 found = false;
858 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 859 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 860 dst_tmp->action = MCLIST_NONE;
861 found = true;
862 break;
863 }
864 }
865 if (!found) {
14f8dc49
JP		 866 new_mc = kmemdup(src_tmp,
867 sizeof(struct mlx4_en_mc_list),
6d199937 868 GFP_KERNEL);
14f8dc49 869 if (!new_mc)
6d199937 870 return;
14f8dc49 871
6d199937
YP		 872 new_mc->action = MCLIST_ADD;
873 list_add_tail(&new_mc->list, dst);
874 }
875 }
876}
c27a02cd 877
0eb74fdd 878static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 879{
880 struct mlx4_en_priv *priv = netdev_priv(dev);
881
882 if (!priv->port_up)
883 return;
884
0eb74fdd 885 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 886}
887
0eb74fdd
YB		 888static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
889 struct mlx4_en_dev *mdev)
c27a02cd 890{
c96d97f4 891 int err = 0;
c27a02cd 892
0eb74fdd 893 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 894 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 895 en_warn(priv, "Entering promiscuous mode\n");
896 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 897
0eb74fdd 898 /* Enable promiscouos mode */
c96d97f4 899 switch (mdev->dev->caps.steering_mode) {
592e49dd 900 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 901 err = mlx4_flow_steer_promisc_add(mdev->dev,
902 priv->port,
903 priv->base_qpn,
f9162539 904 MLX4_FS_ALL_DEFAULT);
592e49dd 905 if (err)
0eb74fdd
YB		 906 en_err(priv, "Failed enabling promiscuous mode\n");
907 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 908 break;
909
c96d97f4 910 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 911 err = mlx4_unicast_promisc_add(mdev->dev,
912 priv->base_qpn,
913 priv->port);
c96d97f4 914 if (err)
0eb74fdd
YB		 915 en_err(priv, "Failed enabling unicast promiscuous mode\n");
916
917 /* Add the default qp number as multicast
918 * promisc
919 */
920 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
921 err = mlx4_multicast_promisc_add(mdev->dev,
922 priv->base_qpn,
923 priv->port);
c96d97f4 924 if (err)
0eb74fdd
YB		 925 en_err(priv, "Failed enabling multicast promiscuous mode\n");
926 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 927 }
928 break;
c27a02cd 929
c96d97f4
HHZ		 930 case MLX4_STEERING_MODE_A0:
931 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
932 priv->port,
0eb74fdd
YB		 933 priv->base_qpn,
934 1);
1679200f 935 if (err)
0eb74fdd 936 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 937 break;
1679200f
YP		 938 }
939
0eb74fdd
YB		 940 /* Disable port multicast filter (unconditionally) */
941 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
942 0, MLX4_MCAST_DISABLE);
943 if (err)
944 en_err(priv, "Failed disabling multicast filter\n");
945
946 /* Disable port VLAN filter */
f1b553fb 947 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 948 if (err)
0eb74fdd
YB		 949 en_err(priv, "Failed disabling VLAN filter\n");
950 }
951}
952
953static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
954 struct mlx4_en_dev *mdev)
955{
956 int err = 0;
957
958 if (netif_msg_rx_status(priv))
959 en_warn(priv, "Leaving promiscuous mode\n");
960 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
961
962 /* Disable promiscouos mode */
963 switch (mdev->dev->caps.steering_mode) {
964 case MLX4_STEERING_MODE_DEVICE_MANAGED:
965 err = mlx4_flow_steer_promisc_remove(mdev->dev,
966 priv->port,
f9162539 967 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 968 if (err)
969 en_err(priv, "Failed disabling promiscuous mode\n");
970 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
971 break;
972
973 case MLX4_STEERING_MODE_B0:
974 err = mlx4_unicast_promisc_remove(mdev->dev,
975 priv->base_qpn,
976 priv->port);
977 if (err)
978 en_err(priv, "Failed disabling unicast promiscuous mode\n");
979 /* Disable Multicast promisc */
980 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
981 err = mlx4_multicast_promisc_remove(mdev->dev,
982 priv->base_qpn,
983 priv->port);
984 if (err)
985 en_err(priv, "Failed disabling multicast promiscuous mode\n");
986 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
987 }
988 break;
989
990 case MLX4_STEERING_MODE_A0:
991 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
992 priv->port,
993 priv->base_qpn, 0);
994 if (err)
995 en_err(priv, "Failed disabling promiscuous mode\n");
996 break;
c27a02cd
YP		 997 }
998
0eb74fdd
YB		 999 /* Enable port VLAN filter */
1000 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
1001 if (err)
1002 en_err(priv, "Failed enabling VLAN filter\n");
1003}
1004
1005static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
1006 struct net_device *dev,
1007 struct mlx4_en_dev *mdev)
1008{
1009 struct mlx4_en_mc_list *mclist, *tmp;
1010 u64 mcast_addr = 0;
1011 u8 mc_list[16] = {0};
1012 int err = 0;
1013
c27a02cd
YP		 1014 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
1015 if (dev->flags & IFF_ALLMULTI) {
1016 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1017 0, MLX4_MCAST_DISABLE);
1018 if (err)
453a6082 1019 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 1020
1021 /* Add the default qp number as multicast promisc */
1022 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 1023 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1024 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1025 err = mlx4_flow_steer_promisc_add(mdev->dev,
1026 priv->port,
1027 priv->base_qpn,
f9162539 1028 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1029 break;
1030
c96d97f4
HHZ		 1031 case MLX4_STEERING_MODE_B0:
1032 err = mlx4_multicast_promisc_add(mdev->dev,
1033 priv->base_qpn,
1034 priv->port);
1035 break;
1036
1037 case MLX4_STEERING_MODE_A0:
1038 break;
1039 }
1679200f
YP		 1040 if (err)
1041 en_err(priv, "Failed entering multicast promisc mode\n");
1042 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1043 }
c27a02cd 1044 } else {
1679200f
YP		 1045 /* Disable Multicast promisc */
1046 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1047 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1048 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1049 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1050 priv->port,
f9162539 1051 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1052 break;
1053
c96d97f4
HHZ		 1054 case MLX4_STEERING_MODE_B0:
1055 err = mlx4_multicast_promisc_remove(mdev->dev,
1056 priv->base_qpn,
1057 priv->port);
1058 break;
1059
1060 case MLX4_STEERING_MODE_A0:
1061 break;
1062 }
1679200f 1063 if (err)
25985edc 1064 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1065 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1066 }
ff6e2163 1067
c27a02cd
YP		 1068 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1069 0, MLX4_MCAST_DISABLE);
1070 if (err)
453a6082 1071 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1072
1073 /* Flush mcast filter and init it with broadcast address */
1074 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1075 1, MLX4_MCAST_CONFIG);
1076
1077 /* Update multicast list - we cache all addresses so they won't
1078 * change while HW is updated holding the command semaphor */
dbd501a8 1079 netif_addr_lock_bh(dev);
c27a02cd 1080 mlx4_en_cache_mclist(dev);
dbd501a8 1081 netif_addr_unlock_bh(dev);
6d199937
YP		 1082 list_for_each_entry(mclist, &priv->mc_list, list) {
1083 mcast_addr = mlx4_en_mac_to_u64(mclist->addr);
c27a02cd
YP		 1084 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1085 mcast_addr, 0, MLX4_MCAST_CONFIG);
1086 }
1087 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1088 0, MLX4_MCAST_ENABLE);
1089 if (err)
453a6082 1090 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1091
1092 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1093 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1094 if (mclist->action == MCLIST_REM) {
1095 /* detach this address and delete from list */
1096 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1097 mc_list[5] = priv->port;
1098 err = mlx4_multicast_detach(mdev->dev,
1099 &priv->rss_map.indir_qp,
1100 mc_list,
0ff1fb65
HHZ		 1101 MLX4_PROT_ETH,
1102 mclist->reg_id);
6d199937
YP		 1103 if (err)
1104 en_err(priv, "Fail to detach multicast address\n");
1105
837052d0
OG		 1106 if (mclist->tunnel_reg_id) {
1107 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1108 if (err)
1109 en_err(priv, "Failed to detach multicast address\n");
1110 }
1111
6d199937
YP		 1112 /* remove from list */
1113 list_del(&mclist->list);
1114 kfree(mclist);
9c64508a 1115 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1116 /* attach the address */
1117 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1118 /* needed for B0 steering support */
6d199937
YP		 1119 mc_list[5] = priv->port;
1120 err = mlx4_multicast_attach(mdev->dev,
1121 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1122 mc_list,
1123 priv->port, 0,
1124 MLX4_PROT_ETH,
1125 &mclist->reg_id);
6d199937
YP		 1126 if (err)
1127 en_err(priv, "Fail to attach multicast address\n");
1128
837052d0
OG		 1129 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1130 &mclist->tunnel_reg_id);
1131 if (err)
1132 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1133 }
1134 }
c27a02cd 1135 }
0eb74fdd
YB		 1136}
1137
cc5387f7
YB		 1138static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1139 struct net_device *dev,
1140 struct mlx4_en_dev *mdev)
1141{
1142 struct netdev_hw_addr *ha;
1143 struct mlx4_mac_entry *entry;
b67bfe0d 1144 struct hlist_node *tmp;
cc5387f7
YB		 1145 bool found;
1146 u64 mac;
1147 int err = 0;
1148 struct hlist_head *bucket;
1149 unsigned int i;
1150 int removed = 0;
1151 u32 prev_flags;
1152
1153 /* Note that we do not need to protect our mac_hash traversal with rcu,
1154 * since all modification code is protected by mdev->state_lock
1155 */
1156
1157 /* find what to remove */
1158 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1159 bucket = &priv->mac_hash[i];
b67bfe0d 1160 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1161 found = false;
1162 netdev_for_each_uc_addr(ha, dev) {
1163 if (ether_addr_equal_64bits(entry->mac,
1164 ha->addr)) {
1165 found = true;
1166 break;
1167 }
1168 }
1169
1170 /* MAC address of the port is not in uc list */
1171 if (ether_addr_equal_64bits(entry->mac, dev->dev_addr))
1172 found = true;
1173
1174 if (!found) {
1175 mac = mlx4_en_mac_to_u64(entry->mac);
1176 mlx4_en_uc_steer_release(priv, entry->mac,
1177 priv->base_qpn,
1178 entry->reg_id);
1179 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1180
1181 hlist_del_rcu(&entry->hlist);
1182 kfree_rcu(entry, rcu);
1183 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1184 entry->mac, priv->port);
1185 ++removed;
1186 }
1187 }
1188 }
1189
1190 /* if we didn't remove anything, there is no use in trying to add
1191 * again once we are in a forced promisc mode state
1192 */
1193 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1194 return;
1195
1196 prev_flags = priv->flags;
1197 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1198
1199 /* find what to add */
1200 netdev_for_each_uc_addr(ha, dev) {
1201 found = false;
1202 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1203 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1204 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1205 found = true;
1206 break;
1207 }
1208 }
1209
1210 if (!found) {
1211 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1212 if (!entry) {
1213 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1214 ha->addr, priv->port);
1215 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1216 break;
1217 }
1218 mac = mlx4_en_mac_to_u64(ha->addr);
1219 memcpy(entry->mac, ha->addr, ETH_ALEN);
1220 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1221 if (err < 0) {
1222 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1223 ha->addr, priv->port, err);
1224 kfree(entry);
1225 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1226 break;
1227 }
1228 err = mlx4_en_uc_steer_add(priv, ha->addr,
1229 &priv->base_qpn,
1230 &entry->reg_id);
1231 if (err) {
1232 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1233 ha->addr, priv->port, err);
1234 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1235 kfree(entry);
1236 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1237 break;
1238 } else {
1239 unsigned int mac_hash;
1240 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1241 ha->addr, priv->port);
1242 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1243 bucket = &priv->mac_hash[mac_hash];
1244 hlist_add_head_rcu(&entry->hlist, bucket);
1245 }
1246 }
1247 }
1248
1249 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1250 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1251 priv->port);
1252 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1253 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1254 priv->port);
1255 }
1256}
1257
0eb74fdd
YB		 1258static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1259{
1260 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1261 rx_mode_task);
1262 struct mlx4_en_dev *mdev = priv->mdev;
1263 struct net_device *dev = priv->dev;
1264
1265 mutex_lock(&mdev->state_lock);
1266 if (!mdev->device_up) {
1267 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1268 goto out;
1269 }
1270 if (!priv->port_up) {
1271 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1272 goto out;
1273 }
1274
1275 if (!netif_carrier_ok(dev)) {
1276 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1277 if (priv->port_state.link_state) {
1278 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1279 netif_carrier_on(dev);
1280 en_dbg(LINK, priv, "Link Up\n");
1281 }
1282 }
1283 }
1284
cc5387f7
YB		 1285 if (dev->priv_flags & IFF_UNICAST_FLT)
1286 mlx4_en_do_uc_filter(priv, dev, mdev);
1287
0eb74fdd 1288 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1289 if ((dev->flags & IFF_PROMISC) ||
1290 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1291 mlx4_en_set_promisc_mode(priv, mdev);
1292 goto out;
1293 }
1294
1295 /* Not in promiscuous mode */
1296 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1297 mlx4_en_clear_promisc_mode(priv, mdev);
1298
1299 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1300out:
1301 mutex_unlock(&mdev->state_lock);
1302}
1303
1304#ifdef CONFIG_NET_POLL_CONTROLLER
1305static void mlx4_en_netpoll(struct net_device *dev)
1306{
1307 struct mlx4_en_priv *priv = netdev_priv(dev);
1308 struct mlx4_en_cq *cq;
1309 unsigned long flags;
1310 int i;
1311
1312 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1313 cq = priv->rx_cq[i];
c27a02cd
YP		 1314 spin_lock_irqsave(&cq->lock, flags);
1315 napi_synchronize(&cq->napi);
1316 mlx4_en_process_rx_cq(dev, cq, 0);
1317 spin_unlock_irqrestore(&cq->lock, flags);
1318 }
1319}
1320#endif
1321
1322static void mlx4_en_tx_timeout(struct net_device *dev)
1323{
1324 struct mlx4_en_priv *priv = netdev_priv(dev);
1325 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1326 int i;
c27a02cd
YP		 1327
1328 if (netif_msg_timer(priv))
453a6082 1329 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1330
b944ebec
YP		 1331 for (i = 0; i < priv->tx_ring_num; i++) {
1332 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1333 continue;
1334 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1335 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1336 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1337 }
1338
1e338db5 1339 priv->port_stats.tx_timeout++;
453a6082 1340 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1341 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1342}
1343
1344
1345static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1346{
1347 struct mlx4_en_priv *priv = netdev_priv(dev);
1348
1349 spin_lock_bh(&priv->stats_lock);
1350 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1351 spin_unlock_bh(&priv->stats_lock);
1352
1353 return &priv->ret_stats;
1354}
1355
1356static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1357{
c27a02cd
YP		 1358 struct mlx4_en_cq *cq;
1359 int i;
1360
1361 /* If we haven't received a specific coalescing setting
98a1708d 1362 * (module param), we set the moderation parameters as follows:
c27a02cd 1363 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1364 * satisfy our coalescing target.
c27a02cd
YP		 1365 * - moder_time is set to a fixed value.
1366 */
3db36fb2 1367 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1368 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1369 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1370 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1371 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1372 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1373
1374 /* Setup cq moderation params */
1375 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1376 cq = priv->rx_cq[i];
c27a02cd
YP		 1377 cq->moder_cnt = priv->rx_frames;
1378 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1379 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1380 priv->last_moder_packets[i] = 0;
1381 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1382 }
1383
1384 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1385 cq = priv->tx_cq[i];
a19a848a
YP		 1386 cq->moder_cnt = priv->tx_frames;
1387 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1388 }
1389
1390 /* Reset auto-moderation params */
1391 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1392 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1393 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1394 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1395 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1396 priv->adaptive_rx_coal = 1;
c27a02cd 1397 priv->last_moder_jiffies = 0;
c27a02cd 1398 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1399}
1400
1401static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1402{
1403 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1404 struct mlx4_en_cq *cq;
1405 unsigned long packets;
1406 unsigned long rate;
1407 unsigned long avg_pkt_size;
1408 unsigned long rx_packets;
1409 unsigned long rx_bytes;
c27a02cd
YP		 1410 unsigned long rx_pkt_diff;
1411 int moder_time;
6b4d8d9f 1412 int ring, err;
c27a02cd
YP		 1413
1414 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1415 return;
1416
6b4d8d9f
AG		 1417 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1418 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1419 rx_packets = priv->rx_ring[ring]->packets;
1420 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1421 spin_unlock_bh(&priv->stats_lock);
1422
1423 rx_pkt_diff = ((unsigned long) (rx_packets -
1424 priv->last_moder_packets[ring]));
1425 packets = rx_pkt_diff;
1426 rate = packets * HZ / period;
1427 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1428 priv->last_moder_bytes[ring])) / packets : 0;
1429
1430 /* Apply auto-moderation only when packet rate
1431 * exceeds a rate that it matters */
1432 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1433 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1434 if (rate < priv->pkt_rate_low)
1435 moder_time = priv->rx_usecs_low;
1436 else if (rate > priv->pkt_rate_high)
1437 moder_time = priv->rx_usecs_high;
1438 else
1439 moder_time = (rate - priv->pkt_rate_low) *
1440 (priv->rx_usecs_high - priv->rx_usecs_low) /
1441 (priv->pkt_rate_high - priv->pkt_rate_low) +
1442 priv->rx_usecs_low;
6b4d8d9f
AG		 1443 } else {
1444 moder_time = priv->rx_usecs_low;
c27a02cd 1445 }
c27a02cd 1446
6b4d8d9f
AG		 1447 if (moder_time != priv->last_moder_time[ring]) {
1448 priv->last_moder_time[ring] = moder_time;
41d942d5 1449 cq = priv->rx_cq[ring];
c27a02cd 1450 cq->moder_time = moder_time;
a1c6693a 1451 cq->moder_cnt = priv->rx_frames;
c27a02cd 1452 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1453 if (err)
48e551ff
YB		 1454 en_err(priv, "Failed modifying moderation for cq:%d\n",
1455 ring);
c27a02cd 1456 }
6b4d8d9f
AG		 1457 priv->last_moder_packets[ring] = rx_packets;
1458 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1459 }
1460
c27a02cd
YP		 1461 priv->last_moder_jiffies = jiffies;
1462}
1463
1464static void mlx4_en_do_get_stats(struct work_struct *work)
1465{
bf6aede7 1466 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1467 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1468 stats_task);
1469 struct mlx4_en_dev *mdev = priv->mdev;
1470 int err;
1471
c27a02cd
YP		 1472 mutex_lock(&mdev->state_lock);
1473 if (mdev->device_up) {
6123db2e
JM		 1474 if (priv->port_up) {
1475 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1476 if (err)
1477 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1478
c27a02cd 1479 mlx4_en_auto_moderation(priv);
6123db2e 1480 }
c27a02cd
YP		 1481
1482 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1483 }
d7e1a487 1484 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
bfa8ab47 1485 mlx4_en_do_set_mac(priv);
d7e1a487
YP		 1486 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1487 }
c27a02cd
YP		 1488 mutex_unlock(&mdev->state_lock);
1489}
1490
b6c39bfc
AV		 1491/* mlx4_en_service_task - Run service task for tasks that needed to be done
1492 * periodically
1493 */
1494static void mlx4_en_service_task(struct work_struct *work)
1495{
1496 struct delayed_work *delay = to_delayed_work(work);
1497 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1498 service_task);
1499 struct mlx4_en_dev *mdev = priv->mdev;
1500
1501 mutex_lock(&mdev->state_lock);
1502 if (mdev->device_up) {
dc8142ea
AV		 1503 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1504 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV		 1505
1506 queue_delayed_work(mdev->workqueue, &priv->service_task,
1507 SERVICE_TASK_DELAY);
1508 }
1509 mutex_unlock(&mdev->state_lock);
1510}
1511
c27a02cd
YP		 1512static void mlx4_en_linkstate(struct work_struct *work)
1513{
1514 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1515 linkstate_task);
1516 struct mlx4_en_dev *mdev = priv->mdev;
1517 int linkstate = priv->link_state;
1518
1519 mutex_lock(&mdev->state_lock);
1520 /* If observable port state changed set carrier state and
1521 * report to system log */
1522 if (priv->last_link_state != linkstate) {
1523 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1524 en_info(priv, "Link Down\n");
c27a02cd
YP		 1525 netif_carrier_off(priv->dev);
1526 } else {
e5cc44b2 1527 en_info(priv, "Link Up\n");
c27a02cd
YP		 1528 netif_carrier_on(priv->dev);
1529 }
1530 }
1531 priv->last_link_state = linkstate;
1532 mutex_unlock(&mdev->state_lock);
1533}
1534
1535
18cc42a3 1536int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1537{
1538 struct mlx4_en_priv *priv = netdev_priv(dev);
1539 struct mlx4_en_dev *mdev = priv->mdev;
1540 struct mlx4_en_cq *cq;
1541 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1542 int rx_index = 0;
1543 int tx_index = 0;
c27a02cd
YP		 1544 int err = 0;
1545 int i;
1546 int j;
1679200f 1547 u8 mc_list[16] = {0};
c27a02cd
YP		 1548
1549 if (priv->port_up) {
453a6082 1550 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1551 return 0;
1552 }
1553
6d199937
YP		 1554 INIT_LIST_HEAD(&priv->mc_list);
1555 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1556 INIT_LIST_HEAD(&priv->ethtool_list);
1557 memset(&priv->ethtool_rules[0], 0,
1558 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1559
c27a02cd
YP		 1560 /* Calculate Rx buf size */
1561 dev->mtu = min(dev->mtu, priv->max_mtu);
1562 mlx4_en_calc_rx_buf(dev);
453a6082 1563 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1564
c27a02cd 1565 /* Configure rx cq's and rings */
38aab07c
YP		 1566 err = mlx4_en_activate_rx_rings(priv);
1567 if (err) {
453a6082 1568 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1569 return err;
1570 }
c27a02cd 1571 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1572 cq = priv->rx_cq[i];
c27a02cd 1573
9e77a2b8
AV		 1574 mlx4_en_cq_init_lock(cq);
1575
76532d0c 1576 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1577 if (err) {
453a6082 1578 en_err(priv, "Failed activating Rx CQ\n");
a4233304 1579 goto cq_err;
c27a02cd
YP		 1580 }
1581 for (j = 0; j < cq->size; j++)
1582 cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1583 err = mlx4_en_set_cq_moder(priv, cq);
1584 if (err) {
453a6082 1585 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1586 mlx4_en_deactivate_cq(priv, cq);
1587 goto cq_err;
1588 }
1589 mlx4_en_arm_cq(priv, cq);
41d942d5 1590 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1591 ++rx_index;
1592 }
1593
ffe455ad
EE		 1594 /* Set qp number */
1595 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1596 err = mlx4_en_get_qp(priv);
1679200f 1597 if (err) {
ffe455ad 1598 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1599 goto cq_err;
1600 }
1601 mdev->mac_removed[priv->port] = 0;
1602
c27a02cd
YP		 1603 err = mlx4_en_config_rss_steer(priv);
1604 if (err) {
453a6082 1605 en_err(priv, "Failed configuring rss steering\n");
1679200f 1606 goto mac_err;
c27a02cd
YP		 1607 }
1608
cabdc8ee
HHZ		 1609 err = mlx4_en_create_drop_qp(priv);
1610 if (err)
1611 goto rss_err;
1612
c27a02cd
YP		 1613 /* Configure tx cq's and rings */
1614 for (i = 0; i < priv->tx_ring_num; i++) {
1615 /* Configure cq */
41d942d5 1616 cq = priv->tx_cq[i];
76532d0c 1617 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1618 if (err) {
453a6082 1619 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1620 goto tx_err;
1621 }
1622 err = mlx4_en_set_cq_moder(priv, cq);
1623 if (err) {
453a6082 1624 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1625 mlx4_en_deactivate_cq(priv, cq);
1626 goto tx_err;
1627 }
453a6082 1628 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1629 cq->buf->wqe_index = cpu_to_be16(0xffff);
1630
1631 /* Configure ring */
41d942d5 1632 tx_ring = priv->tx_ring[i];
0e98b523 1633 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1634 i / priv->num_tx_rings_p_up);
c27a02cd 1635 if (err) {
453a6082 1636 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1637 mlx4_en_deactivate_cq(priv, cq);
1638 goto tx_err;
1639 }
5b263f53 1640 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1641
1642 /* Arm CQ for TX completions */
1643 mlx4_en_arm_cq(priv, cq);
1644
c27a02cd
YP		 1645 /* Set initial ownership of all Tx TXBBs to SW (1) */
1646 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1647 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1648 ++tx_index;
1649 }
1650
1651 /* Configure port */
1652 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1653 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1654 priv->prof->tx_pause,
1655 priv->prof->tx_ppp,
1656 priv->prof->rx_pause,
1657 priv->prof->rx_ppp);
c27a02cd 1658 if (err) {
48e551ff
YB		 1659 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1660 priv->port, err);
c27a02cd
YP		 1661 goto tx_err;
1662 }
1663 /* Set default qp number */
1664 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1665 if (err) {
453a6082 1666 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1667 goto tx_err;
1668 }
c27a02cd 1669
837052d0
OG		 1670 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1671 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
1672 if (err) {
1673 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1674 err);
1675 goto tx_err;
1676 }
1677 }
1678
c27a02cd 1679 /* Init port */
453a6082 1680 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1681 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1682 if (err) {
453a6082 1683 en_err(priv, "Failed Initializing port\n");
1679200f 1684 goto tx_err;
c27a02cd
YP		 1685 }
1686
1679200f
YP		 1687 /* Attach rx QP to bradcast address */
1688 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1689 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1690 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1691 priv->port, 0, MLX4_PROT_ETH,
1692 &priv->broadcast_id))
1679200f
YP		 1693 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1694
b5845f98
HX		 1695 /* Must redo promiscuous mode setup. */
1696 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1697
c27a02cd 1698 /* Schedule multicast task to populate multicast list */
0eb74fdd 1699 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1700
93ece0c1
EE		 1701 mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
1702
c27a02cd 1703 priv->port_up = true;
a11faac7 1704 netif_tx_start_all_queues(dev);
3484aac1
AV		 1705 netif_device_attach(dev);
1706
c27a02cd
YP		 1707 return 0;
1708
c27a02cd
YP		 1709tx_err:
1710 while (tx_index--) {
41d942d5
EE		 1711 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1712 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1713 }
cabdc8ee
HHZ		 1714 mlx4_en_destroy_drop_qp(priv);
1715rss_err:
c27a02cd 1716 mlx4_en_release_rss_steer(priv);
1679200f 1717mac_err:
16a10ffd 1718 mlx4_en_put_qp(priv);
c27a02cd
YP		 1719cq_err:
1720 while (rx_index--)
41d942d5 1721 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
38aab07c 1722 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1723 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1724
1725 return err; /* need to close devices */
1726}
1727
1728
3484aac1 1729void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1730{
1731 struct mlx4_en_priv *priv = netdev_priv(dev);
1732 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1733 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1734 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1735 int i;
1679200f 1736 u8 mc_list[16] = {0};
c27a02cd
YP		 1737
1738 if (!priv->port_up) {
453a6082 1739 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1740 return;
1741 }
c27a02cd 1742
0cc5c8bf
EE		 1743 /* close port*/
1744 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1745
c27a02cd
YP		 1746 /* Synchronize with tx routine */
1747 netif_tx_lock_bh(dev);
3484aac1
AV		 1748 if (detach)
1749 netif_device_detach(dev);
3c05f5ef 1750 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1751 netif_tx_unlock_bh(dev);
1752
3484aac1
AV		 1753 netif_tx_disable(dev);
1754
7c287380 1755 /* Set port as not active */
3c05f5ef 1756 priv->port_up = false;
c27a02cd 1757
db0e7cba
AY		 1758 /* Promsicuous mode */
1759 if (mdev->dev->caps.steering_mode ==
1760 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1761 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1762 MLX4_EN_FLAG_MC_PROMISC);
1763 mlx4_flow_steer_promisc_remove(mdev->dev,
1764 priv->port,
f9162539 1765 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1766 mlx4_flow_steer_promisc_remove(mdev->dev,
1767 priv->port,
f9162539 1768 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1769 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1770 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1771
1772 /* Disable promiscouos mode */
1773 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1774 priv->port);
1775
1776 /* Disable Multicast promisc */
1777 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1778 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1779 priv->port);
1780 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1781 }
1782 }
1783
1679200f
YP		 1784 /* Detach All multicasts */
1785 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1786 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1787 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1788 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1789 list_for_each_entry(mclist, &priv->curr_list, list) {
1790 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1791 mc_list[5] = priv->port;
1792 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1793 mc_list, MLX4_PROT_ETH, mclist->reg_id);
1679200f
YP		 1794 }
1795 mlx4_en_clear_list(dev);
6d199937
YP		 1796 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1797 list_del(&mclist->list);
1798 kfree(mclist);
1799 }
1800
1679200f
YP		 1801 /* Flush multicast filter */
1802 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1803
6efb5fac
HHZ		 1804 /* Remove flow steering rules for the port*/
1805 if (mdev->dev->caps.steering_mode ==
1806 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1807 ASSERT_RTNL();
1808 list_for_each_entry_safe(flow, tmp_flow,
1809 &priv->ethtool_list, list) {
1810 mlx4_flow_detach(mdev->dev, flow->id);
1811 list_del(&flow->list);
1812 }
1813 }
1814
cabdc8ee
HHZ		 1815 mlx4_en_destroy_drop_qp(priv);
1816
c27a02cd
YP		 1817 /* Free TX Rings */
1818 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1819 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1820 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1821 }
1822 msleep(10);
1823
1824 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1825 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1826
1827 /* Free RSS qps */
1828 mlx4_en_release_rss_steer(priv);
1829
ffe455ad 1830 /* Unregister Mac address for the port */
16a10ffd 1831 mlx4_en_put_qp(priv);
5930e8d0 1832 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1833 mdev->mac_removed[priv->port] = 1;
ffe455ad 1834
c27a02cd
YP		 1835 /* Free RX Rings */
1836 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1837 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1838
1839 local_bh_disable();
1840 while (!mlx4_en_cq_lock_napi(cq)) {
1841 pr_info("CQ %d locked\n", i);
1842 mdelay(1);
1843 }
1844 local_bh_enable();
1845
9e77a2b8 1846 while (test_bit(NAPI_STATE_SCHED, &cq->napi.state))
c27a02cd 1847 msleep(1);
41d942d5 1848 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1849 mlx4_en_deactivate_cq(priv, cq);
c27a02cd
YP		 1850 }
1851}
1852
1853static void mlx4_en_restart(struct work_struct *work)
1854{
1855 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1856 watchdog_task);
1857 struct mlx4_en_dev *mdev = priv->mdev;
1858 struct net_device *dev = priv->dev;
1859
453a6082 1860 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1861
1862 mutex_lock(&mdev->state_lock);
1863 if (priv->port_up) {
3484aac1 1864 mlx4_en_stop_port(dev, 1);
1e338db5 1865 if (mlx4_en_start_port(dev))
453a6082 1866 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1867 }
1868 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1869}
1870
b477ba62 1871static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1872{
1873 struct mlx4_en_priv *priv = netdev_priv(dev);
1874 struct mlx4_en_dev *mdev = priv->mdev;
1875 int i;
c27a02cd 1876
c27a02cd 1877 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1878 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1879
1880 memset(&priv->stats, 0, sizeof(priv->stats));
1881 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1882 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1883 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
c27a02cd
YP		 1884
1885 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1886 priv->tx_ring[i]->bytes = 0;
1887 priv->tx_ring[i]->packets = 0;
1888 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1889 }
1890 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1891 priv->rx_ring[i]->bytes = 0;
1892 priv->rx_ring[i]->packets = 0;
1893 priv->rx_ring[i]->csum_ok = 0;
1894 priv->rx_ring[i]->csum_none = 0;
c27a02cd 1895 }
b477ba62
EE		 1896}
1897
1898static int mlx4_en_open(struct net_device *dev)
1899{
1900 struct mlx4_en_priv *priv = netdev_priv(dev);
1901 struct mlx4_en_dev *mdev = priv->mdev;
1902 int err = 0;
1903
1904 mutex_lock(&mdev->state_lock);
1905
1906 if (!mdev->device_up) {
1907 en_err(priv, "Cannot open - device down/disabled\n");
1908 err = -EBUSY;
1909 goto out;
1910 }
1911
1912 /* Reset HW statistics and SW counters */
1913 mlx4_en_clear_stats(dev);
c27a02cd 1914
c27a02cd
YP		 1915 err = mlx4_en_start_port(dev);
1916 if (err)
453a6082 1917 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1918
1919out:
1920 mutex_unlock(&mdev->state_lock);
1921 return err;
1922}
1923
1924
1925static int mlx4_en_close(struct net_device *dev)
1926{
1927 struct mlx4_en_priv *priv = netdev_priv(dev);
1928 struct mlx4_en_dev *mdev = priv->mdev;
1929
453a6082 1930 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1931
1932 mutex_lock(&mdev->state_lock);
1933
3484aac1 1934 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1935 netif_carrier_off(dev);
1936
1937 mutex_unlock(&mdev->state_lock);
1938 return 0;
1939}
1940
fe0af03c 1941void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1942{
1943 int i;
1944
1eb8c695
AV		 1945#ifdef CONFIG_RFS_ACCEL
1946 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1947 priv->dev->rx_cpu_rmap = NULL;
1948#endif
1949
c27a02cd 1950 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1951 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1952 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1953 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1954 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1955 }
1956
1957 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1958 if (priv->rx_ring[i])
68355f71
TLSC		 1959 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1960 priv->prof->rx_ring_size, priv->stride);
41d942d5 1961 if (priv->rx_cq[i])
fe0af03c 1962 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1963 }
044ca2a5
YP		 1964
1965 if (priv->base_tx_qpn) {
1966 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1967 priv->base_tx_qpn = 0;
1968 }
c27a02cd
YP		 1969}
1970
18cc42a3 1971int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1972{
c27a02cd
YP		 1973 struct mlx4_en_port_profile *prof = priv->prof;
1974 int i;
044ca2a5 1975 int err;
163561a4 1976 int node;
87a5c389 1977
044ca2a5 1978 err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn);
87a5c389
YP		 1979 if (err) {
1980 en_err(priv, "failed reserving range for TX rings\n");
1981 return err;
1982 }
c27a02cd
YP		 1983
1984 /* Create tx Rings */
1985 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1986 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1987 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1988 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1989 goto err;
1990
d03a68f8
IS		 1991 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
1992 priv->base_tx_qpn + i,
1993 prof->tx_ring_size, TXBB_SIZE,
1994 node, i))
c27a02cd
YP		 1995 goto err;
1996 }
1997
1998 /* Create rx Rings */
1999 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2000 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2001 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2002 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2003 goto err;
2004
2005 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2006 prof->rx_ring_size, priv->stride,
2007 node))
c27a02cd
YP		 2008 goto err;
2009 }
2010
1eb8c695 2011#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2012 if (priv->mdev->dev->caps.comp_pool) {
2013 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2014 if (!priv->dev->rx_cpu_rmap)
2015 goto err;
2016 }
1eb8c695
AV		 2017#endif
2018
c27a02cd
YP		 2019 return 0;
2020
2021err:
453a6082 2022 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2023 for (i = 0; i < priv->rx_ring_num; i++) {
2024 if (priv->rx_ring[i])
2025 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2026 prof->rx_ring_size,
2027 priv->stride);
2028 if (priv->rx_cq[i])
2029 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2030 }
2031 for (i = 0; i < priv->tx_ring_num; i++) {
2032 if (priv->tx_ring[i])
2033 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2034 if (priv->tx_cq[i])
2035 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2036 }
c27a02cd
YP		 2037 return -ENOMEM;
2038}
2039
2040
2041void mlx4_en_destroy_netdev(struct net_device *dev)
2042{
2043 struct mlx4_en_priv *priv = netdev_priv(dev);
2044 struct mlx4_en_dev *mdev = priv->mdev;
2045
453a6082 2046 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2047
2048 /* Unregister device - this will close the port if it was up */
2049 if (priv->registered)
2050 unregister_netdev(dev);
2051
2052 if (priv->allocated)
2053 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2054
2055 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2056 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2057 /* flush any pending task for this netdev */
2058 flush_workqueue(mdev->workqueue);
2059
2060 /* Detach the netdev so tasks would not attempt to access it */
2061 mutex_lock(&mdev->state_lock);
2062 mdev->pndev[priv->port] = NULL;
2063 mutex_unlock(&mdev->state_lock);
2064
fe0af03c 2065 mlx4_en_free_resources(priv);
564c274c 2066
bc6a4744
AV		 2067 kfree(priv->tx_ring);
2068 kfree(priv->tx_cq);
2069
c27a02cd
YP		 2070 free_netdev(dev);
2071}
2072
2073static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2074{
2075 struct mlx4_en_priv *priv = netdev_priv(dev);
2076 struct mlx4_en_dev *mdev = priv->mdev;
2077 int err = 0;
2078
453a6082 2079 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2080 dev->mtu, new_mtu);
2081
2082 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2083 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2084 return -EPERM;
2085 }
2086 dev->mtu = new_mtu;
2087
2088 if (netif_running(dev)) {
2089 mutex_lock(&mdev->state_lock);
2090 if (!mdev->device_up) {
2091 /* NIC is probably restarting - let watchdog task reset
2092 * the port */
453a6082 2093 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2094 } else {
3484aac1 2095 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2096 err = mlx4_en_start_port(dev);
2097 if (err) {
453a6082 2098 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2099 priv->port);
2100 queue_work(mdev->workqueue, &priv->watchdog_task);
2101 }
2102 }
2103 mutex_unlock(&mdev->state_lock);
2104 }
2105 return 0;
2106}
2107
100dbda8 2108static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2109{
2110 struct mlx4_en_priv *priv = netdev_priv(dev);
2111 struct mlx4_en_dev *mdev = priv->mdev;
2112 struct hwtstamp_config config;
2113
2114 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2115 return -EFAULT;
2116
2117 /* reserved for future extensions */
2118 if (config.flags)
2119 return -EINVAL;
2120
2121 /* device doesn't support time stamping */
2122 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2123 return -EINVAL;
2124
2125 /* TX HW timestamp */
2126 switch (config.tx_type) {
2127 case HWTSTAMP_TX_OFF:
2128 case HWTSTAMP_TX_ON:
2129 break;
2130 default:
2131 return -ERANGE;
2132 }
2133
2134 /* RX HW timestamp */
2135 switch (config.rx_filter) {
2136 case HWTSTAMP_FILTER_NONE:
2137 break;
2138 case HWTSTAMP_FILTER_ALL:
2139 case HWTSTAMP_FILTER_SOME:
2140 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2141 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2142 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2143 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2144 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2145 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2146 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2147 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2148 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2149 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2150 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2151 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2152 config.rx_filter = HWTSTAMP_FILTER_ALL;
2153 break;
2154 default:
2155 return -ERANGE;
2156 }
2157
2158 if (mlx4_en_timestamp_config(dev, config.tx_type, config.rx_filter)) {
2159 config.tx_type = HWTSTAMP_TX_OFF;
2160 config.rx_filter = HWTSTAMP_FILTER_NONE;
2161 }
2162
2163 return copy_to_user(ifr->ifr_data, &config,
2164 sizeof(config)) ? -EFAULT : 0;
2165}
2166
100dbda8
BH		 2167static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2168{
2169 struct mlx4_en_priv *priv = netdev_priv(dev);
2170
2171 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2172 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2173}
2174
ec693d47
AV		 2175static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2176{
2177 switch (cmd) {
2178 case SIOCSHWTSTAMP:
100dbda8
BH		 2179 return mlx4_en_hwtstamp_set(dev, ifr);
2180 case SIOCGHWTSTAMP:
2181 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2182 default:
2183 return -EOPNOTSUPP;
2184 }
2185}
2186
60d6fe99
AV		 2187static int mlx4_en_set_features(struct net_device *netdev,
2188 netdev_features_t features)
2189{
2190 struct mlx4_en_priv *priv = netdev_priv(netdev);
2191
2192 if (features & NETIF_F_LOOPBACK)
2193 priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2194 else
2195 priv->ctrl_flags &=
2196 cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
2197
79aeaccd
YB		 2198 mlx4_en_update_loopback_state(netdev, features);
2199
60d6fe99
AV		 2200 return 0;
2201
2202}
2203
8f7ba3ca
RE		 2204static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2205{
2206 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2207 struct mlx4_en_dev *mdev = en_priv->mdev;
2208 u64 mac_u64 = mlx4_en_mac_to_u64(mac);
2209
2210 if (!is_valid_ether_addr(mac))
2211 return -EINVAL;
2212
2213 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2214}
2215
3f7fb021
RE		 2216static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2217{
2218 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2219 struct mlx4_en_dev *mdev = en_priv->mdev;
2220
2221 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2222}
2223
e6b6a231
RE		 2224static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2225{
2226 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2227 struct mlx4_en_dev *mdev = en_priv->mdev;
2228
2229 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2230}
2231
2cccb9e4
RE		 2232static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2233{
2234 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2235 struct mlx4_en_dev *mdev = en_priv->mdev;
2236
2237 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2238}
8f7ba3ca 2239
948e306d
RE		 2240static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2241{
2242 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2243 struct mlx4_en_dev *mdev = en_priv->mdev;
2244
2245 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2246}
84c86403
HHZ		 2247
2248#define PORT_ID_BYTE_LEN 8
2249static int mlx4_en_get_phys_port_id(struct net_device *dev,
2250 struct netdev_phys_port_id *ppid)
2251{
2252 struct mlx4_en_priv *priv = netdev_priv(dev);
2253 struct mlx4_dev *mdev = priv->mdev->dev;
2254 int i;
2255 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2256
2257 if (!phys_port_id)
2258 return -EOPNOTSUPP;
2259
2260 ppid->id_len = sizeof(phys_port_id);
2261 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2262 ppid->id[i] = phys_port_id & 0xff;
2263 phys_port_id >>= 8;
2264 }
2265 return 0;
2266}
2267
3addc568
SH		 2268static const struct net_device_ops mlx4_netdev_ops = {
2269 .ndo_open = mlx4_en_open,
2270 .ndo_stop = mlx4_en_close,
2271 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2272 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2273 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2274 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2275 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2276 .ndo_validate_addr = eth_validate_addr,
3addc568 2277 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2278 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2279 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2280 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2281 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2282#ifdef CONFIG_NET_POLL_CONTROLLER
2283 .ndo_poll_controller = mlx4_en_netpoll,
2284#endif
60d6fe99 2285 .ndo_set_features = mlx4_en_set_features,
897d7846 2286 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2287#ifdef CONFIG_RFS_ACCEL
2288 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2289#endif
e0d1095a 2290#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2291 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2292#endif
84c86403 2293 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
3addc568
SH		 2294};
2295
8f7ba3ca
RE		 2296static const struct net_device_ops mlx4_netdev_ops_master = {
2297 .ndo_open = mlx4_en_open,
2298 .ndo_stop = mlx4_en_close,
2299 .ndo_start_xmit = mlx4_en_xmit,
2300 .ndo_select_queue = mlx4_en_select_queue,
2301 .ndo_get_stats = mlx4_en_get_stats,
2302 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2303 .ndo_set_mac_address = mlx4_en_set_mac,
2304 .ndo_validate_addr = eth_validate_addr,
2305 .ndo_change_mtu = mlx4_en_change_mtu,
2306 .ndo_tx_timeout = mlx4_en_tx_timeout,
2307 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2308 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2309 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2310 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
e6b6a231 2311 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2312 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2313 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2314#ifdef CONFIG_NET_POLL_CONTROLLER
2315 .ndo_poll_controller = mlx4_en_netpoll,
2316#endif
2317 .ndo_set_features = mlx4_en_set_features,
2318 .ndo_setup_tc = mlx4_en_setup_tc,
2319#ifdef CONFIG_RFS_ACCEL
2320 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2321#endif
84c86403 2322 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
8f7ba3ca
RE		 2323};
2324
c27a02cd
YP		 2325int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2326 struct mlx4_en_port_profile *prof)
2327{
2328 struct net_device *dev;
2329 struct mlx4_en_priv *priv;
c07cb4b0 2330 int i;
c27a02cd 2331 int err;
ef96f7d4 2332 u64 mac_u64;
c27a02cd 2333
f1593d22 2334 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2335 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2336 if (dev == NULL)
c27a02cd 2337 return -ENOMEM;
c27a02cd 2338
d317966b
AV		 2339 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2340 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2341
c27a02cd 2342 SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev);
741a00be 2343 dev->dev_id = port - 1;
c27a02cd
YP		 2344
2345 /*
2346 * Initialize driver private data
2347 */
2348
2349 priv = netdev_priv(dev);
2350 memset(priv, 0, sizeof(struct mlx4_en_priv));
2351 priv->dev = dev;
2352 priv->mdev = mdev;
ebf8c9aa 2353 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2354 priv->prof = prof;
2355 priv->port = port;
2356 priv->port_up = false;
c27a02cd 2357 priv->flags = prof->flags;
60d6fe99
AV		 2358 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2359 MLX4_WQE_CTRL_SOLICITED);
d317966b 2360 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2361 priv->tx_ring_num = prof->tx_ring_num;
d317966b 2362
41d942d5 2363 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2364 GFP_KERNEL);
bc6a4744
AV		 2365 if (!priv->tx_ring) {
2366 err = -ENOMEM;
2367 goto out;
2368 }
41d942d5 2369 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2370 GFP_KERNEL);
bc6a4744
AV		 2371 if (!priv->tx_cq) {
2372 err = -ENOMEM;
2373 goto out;
2374 }
c27a02cd 2375 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2376 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
c27a02cd
YP		 2377 priv->mac_index = -1;
2378 priv->msg_enable = MLX4_EN_MSG_LEVEL;
2379 spin_lock_init(&priv->stats_lock);
0eb74fdd 2380 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
c27a02cd
YP		 2381 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2382 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2383 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
b6c39bfc 2384 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
564c274c 2385#ifdef CONFIG_MLX4_EN_DCB
540b3a39
OG		 2386 if (!mlx4_is_slave(priv->mdev->dev)) {
2387 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
2388 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2389 } else {
2390 en_info(priv, "enabling only PFC DCB ops\n");
2391 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2392 }
2393 }
564c274c 2394#endif
c27a02cd 2395
c07cb4b0
YB		 2396 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2397 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2398
c27a02cd
YP		 2399 /* Query for default mac and max mtu */
2400 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99
YB		 2401
2402 /* Set default MAC */
2403 dev->addr_len = ETH_ALEN;
2404 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2405 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2406 if (mlx4_is_slave(priv->mdev->dev)) {
2407 eth_hw_addr_random(dev);
2408 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
2409 mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
2410 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2411 } else {
2412 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2413 priv->port, dev->dev_addr);
2414 err = -EINVAL;
2415 goto out;
2416 }
c27a02cd
YP		 2417 }
2418
6bbb6d99
YB		 2419 memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
2420
c27a02cd
YP		 2421 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2422 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2423 err = mlx4_en_alloc_resources(priv);
2424 if (err)
2425 goto out;
2426
78fb2de7
AV		 2427#ifdef CONFIG_RFS_ACCEL
2428 INIT_LIST_HEAD(&priv->filters);
2429 spin_lock_init(&priv->filters_lock);
2430#endif
2431
ec693d47
AV		 2432 /* Initialize time stamping config */
2433 priv->hwtstamp_config.flags = 0;
2434 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2435 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2436
c27a02cd
YP		 2437 /* Allocate page for receive rings */
2438 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2439 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2440 if (err) {
453a6082 2441 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2442 goto out;
2443 }
2444 priv->allocated = 1;
2445
c27a02cd
YP		 2446 /*
2447 * Initialize netdev entry points
2448 */
8f7ba3ca
RE		 2449 if (mlx4_is_master(priv->mdev->dev))
2450 dev->netdev_ops = &mlx4_netdev_ops_master;
2451 else
2452 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2453 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2454 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2455 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2456
c27a02cd
YP		 2457 SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
2458
c27a02cd
YP		 2459 /*
2460 * Set driver features
2461 */
c8c64cff
MM		 2462 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2463 if (mdev->LSO_support)
2464 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2465
2466 dev->vlan_features = dev->hw_features;
2467
ad86107f 2468 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2469 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2470 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2471 NETIF_F_HW_VLAN_CTAG_FILTER;
60d6fe99 2472 dev->hw_features |= NETIF_F_LOOPBACK;
c27a02cd 2473
1eb8c695
AV		 2474 if (mdev->dev->caps.steering_mode ==
2475 MLX4_STEERING_MODE_DEVICE_MANAGED)
2476 dev->hw_features |= NETIF_F_NTUPLE;
2477
cc5387f7
YB		 2478 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2479 dev->priv_flags |= IFF_UNICAST_FLT;
2480
837052d0
OG		 2481 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2482 dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2483 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2484 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2485 dev->features |= NETIF_F_GSO_UDP_TUNNEL;
2486 }
2487
c27a02cd
YP		 2488 mdev->pndev[port] = dev;
2489
2490 netif_carrier_off(dev);
4801ae70
EE		 2491 mlx4_en_set_default_moderation(priv);
2492
c27a02cd
YP		 2493 err = register_netdev(dev);
2494 if (err) {
453a6082 2495 en_err(priv, "Netdev registration failed for port %d\n", port);
c27a02cd
YP		 2496 goto out;
2497 }
4234144f 2498 priv->registered = 1;
453a6082
YP		 2499
2500 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2501 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2502
79aeaccd
YB		 2503 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2504
90822265 2505 /* Configure port */
5c8e9046 2506 mlx4_en_calc_rx_buf(dev);
90822265 2507 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2508 priv->rx_skb_size + ETH_FCS_LEN,
2509 prof->tx_pause, prof->tx_ppp,
2510 prof->rx_pause, prof->rx_ppp);
90822265
YP		 2511 if (err) {
2512 en_err(priv, "Failed setting port general configurations "
2513 "for port %d, with error %d\n", priv->port, err);
2514 goto out;
2515 }
2516
837052d0
OG		 2517 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2518 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
2519 if (err) {
2520 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2521 err);
2522 goto out;
2523 }
2524 }
2525
90822265
YP		 2526 /* Init port */
2527 en_warn(priv, "Initializing port\n");
2528 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2529 if (err) {
2530 en_err(priv, "Failed Initializing port\n");
2531 goto out;
2532 }
c27a02cd 2533 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2534
2535 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2536 queue_delayed_work(mdev->workqueue, &priv->service_task,
2537 SERVICE_TASK_DELAY);
2538
c27a02cd
YP		 2539 return 0;
2540
2541out:
2542 mlx4_en_destroy_netdev(dev);
2543 return err;
2544}
2545
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